19-5580; Rev 10/10
FEATURES
10 years minimum data r etent ion in the
absence of external power
Data is automatically pro tected during power
loss
Directly replaces 2k x 8 volatile static RAM
or EE P R O M
Unlimited write c ycles
Low-power CMOS
JEDEC standard 24-pin DIP packag e
Read and write access times of 100 ns
Lithium energy sour ce is electrically
disconnected to retain freshness until power
is applied for the first time
Full ±10% VCC operating range (DS1220AD)
Optional ±5% VCC operating range
(DS1220AB)
Optional industrial temperature range of
-40°C to +85°C, designated IND
16k Nonvolatile SRAM
PIN ASSIGNMENT
24-Pin ENCAPSULATED PACKAGE
720-mil EXTENDED
PIN DESCRIPTION
A0-A10 - Address Inputs
DQ0-DQ7 - Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
V
- Power (+5V)
CC
GND - Ground
DESCRIPTION
The DS1220AB and DS1220AD 16k Nonvolatile SRAMs are 16,384-bit, fully st atic, nonvolatile SRAMs
organized as 2048 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
cont r ol c ircuit ry w h i ch c onsta n tly mon ito r s VCC fo r a n o ut-of-to ler a nc e c o nditio n. Whe n s uc h a c o nd ition
occurs, the lithium energy source is automatically switched on and write prot ection is uncond itionally
enabled to prevent data corruption. The NV SRAMs can be used in place of existing 2k x 8 SRAMs
directly conforming to the popular bytewide 24-pin DIP standard. The devices also match the pinout of
the 2716 EPROM and the 2816 EEPROM, allowing direct substitution while enhancing performance.
There is no limit o n t he number of write cycles that can be execut ed and no additional support circuitry is
required for microp ro cessor interfacing.
1 of 8
READ MODE
DS1220AB/AD
The DS1220AB and DS1220AD execute a read cycle whenever
(Write Enable) is inact ive (high) and
(Chip Enable) and OE(Output Enable) are active (low). The unique address specified by the 11
address inputs (A0-A10) defines which of the 2048 bytes o f data is to be accessed. Valid data w ill be
available to the eight data output drivers within t
stable, providing that the CEand
access t imes are also sat isfied. If CEand
(Access T ime) after the last address input signal is
ACC
access times are not
satisfied, then data access must be measured fro m the later-oc cu rr ing s ig na l a nd t he li miting p ar a meter is
either tCO for CEor tOE for OE rather than address access.
WRITE MODE
The DS1220AB and DS1220AD execute a write cycle whenever the
after address inputs are stable. T he latt er occurring falling edge of CEor
the write cycle. Th e write cycle is terminated b y the earlier r ising edge o f CEor
must be kept va lid t hro ug ho ut the wr it e c ycle.
time ( tWR ) before a not her cycle can be in itiated. The
must return to the high state for a minimum recovery
co ntrol sig nal s hould be kept inact ive (hig h)
during write cycles to avoid bus contention. However, if the output drivers are enabled (CEand
active) then
will disable the o utputs in t
from its falling edge.
ODW
and CE signals are act ive (low)
will de ter mine t he start of
. All address inputs
DATA RETENTION MODE
The DS1220AB provides full functional capability for V
4.5V. The DS1220AD provides full functional capability for VCC greater than 4.5 volts and write protects
by 4.25V. Data is maintained in the absence of VCC without any additional support circuitry. The
nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high
impedance. As VCC falls below approximately 3.0 volts, a power sw itching circu it co nnects the lithiu m
energy source to RAM to r etain data. During power-up , when VCC rises above approximately 3.0 volts,
the power sw itching c ircuit connect s external VCC to RAM and disconnects the lithium energy source.
Normal RAM operat ion can resu me after VCC exceeds 4.75 volts for the DS1220AB and 4.5 volts for the
DS1220AD.
greater t han 4.75 volts and wr ite protect s by
CC
FRESHNESS SEAL
Each DS1220 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing fu ll energ y capac it y. When VCC is first app lied at a level o f greater t han VTP, t he lithi um
energy source is enabled for battery backup operation.
DS1220AB/AD
DS1220AB Power Supply Voltage
DS1220AD Power Supply Voltage
Operating Current
(Commercial)
Operating Current
(Industrial)
Write Protection Voltage
(DS1220AB)
Write Protection Voltage
Input Capacitance
Input/O utput Capacitanc e
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperat ur e Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Storage Temperatu r e -40°C to +85°C
Lead Temperature (soldering, 10s) +260°C
Note: EDIP is wave or hand soldered only.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this
specification is not i mplied. Exposure to absolute m ax imum rating condition s for extended periods of tim e may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DC ELECTRICAL CHARACTERISTICS (TA: See Note 10)
(V
= 5V ± 5% for DS1220AB)
CC
(V
= 5V ± 10% for DS1220AD)
CC
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
≥ V
≤ VCC
IH
Standby Current
= 2.2V
=
I
CCS1
I
CCS2
I
CC01
I
CCO1
IO
+1.0
µA
5.0 10.0 mA
3.0 5.0 mA
75 mA
85 mA
I
VTP 4.5 4.62 4.75 V
(DS1220AD)
VTP 4.25 4.37 4.5 V
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES