MAXIM DS1086 User Manual

General Description

The DS1086 EconOscillator™ is a programmable clock generator that produces a spread-spectrum (dithered) square-wave output of frequencies from 260kHz to 133MHz. The selectable dithered output reduces radiated-emission peaks by dithering the frequency 2% or 4% below the programmed frequency. The DS1086 has a power-down mode and an output-enable control for power-sensitive applications. All the device settings are stored in nonvolatile (NV) EEPROM memory allowing it to operate in stand-alone applications.

Applications

Printers

Copiers

PCs

Computer Peripherals

Cell Phones

Cable Modems

Features

o User-Programmable Square-Wave Generator

o Frequencies Programmable from 260kHz to

133MHz

o 2% or 4% Selectable Dithered Output

o Glitchless Output-Enable Control

o 2-Wire Serial Interface

o Nonvolatile Settings

o 5V Supply

o No External Timing Components Required

o Power-Down Mode

o 10kHz Master Frequency Step Size

o EMI Reduction

DS1086

Spread-Spectrum EconOscillator

________________________________________________________________

Maxim Integrated Products

Pin Configuration

Ordering Information

Typical Operating Circuit

19-6224; Rev 2; 3/12

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Note: Contact the factory for custom settings.

Denotes a lead(Pb)-free/RoHS-compliant package.

PART TEMP RANGE PIN-PACKAGE

DS1086U 0°C to +70°C 8 µSOP

DS1086U+ 0°C to +70°C 8 µSOP

DS1086Z 0°C to +70°C 8 SO

DS1086Z+ 0°C to +70°C 8 SO

EconOscillator is a trademark of Maxim Integrated Products, Inc.

MICRO-

PROCESSOR

XTL1/OSC1

XTL2/OSC2

*SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086 NEVER NEEDS TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING.

DITHERED 260kHz TO

133MHz OUTPUT

OUT

N.C.

DECOUPLING CAPACITORS

(0.1µF and 0.01µF)

SPRD

GND

DS1086

SCL*

SDA*

PDN

TOP VIEW

OUT

DS1086

µSOP/SO

87SCL

SDASPRD

PDN

OEGND

DS1086

Spread-Spectrum EconOscillator

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED DC OPERATING CONDITIONS

(VCC= 5V ±5%, TA= 0°C to +70°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

(VCC= 5V ±5%, TA= 0°C to +70°C.)

Voltage on VCCRelative to Ground ......................-0.5V to +6.0V

Voltage on SPRD, PDN, OE, SDA,

SCL Relative to Ground (See Note 1).......-0.5 to (V

+ 0.5V)

Continuous Power Dissipation (T

= +70°C)

µSOP (derate 4.5mW/°C above +70°C)........................362mW

SO (derate 5.9mW/°C above +70°C).........................470.6mW

Junction Temperature......................................................+150°C

Operating Temperature Range...............................0°C to +70°C

Storage Temperature Range .............................-55°C to +125°C

Soldering Temperature (reflow)

Lead(Pb)-free................................................................+260°C

Containing lead(Pb) .....................................................+240°C

Note 1: This voltage must not exceed 6.0V.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage V

High-Level Input Voltage (SDA, SCL)

Low-Level Input Voltage (SDA, SCL)

High-Level Input Voltage (SPRD, PDN, OE)

Low-Level Input Voltage (SPRD, PDN, OE)

(Note 1) 4.75 5.00 5.25 V

0.7 x V

-0.3

-0.3 0.8 V

VCC +

0.3

0.3 x V

0.3

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

High-Level Output Voltage (OUT) V

Low-Level Output Voltage (OUT) V

High-Level Input Current I

Low-Level Input Current I

Supply Current (Active)

Standby Current (Power-Down) I

CCQ

IOH = -4mA, VCC = min 2.4 V

IOL = 4mA 0.4 V

VCC = 5.25V 1 µA

VIL = 0V -1 µA

CL = 15pF (output at default frequency) 35 mA

Power-down mode 35 µA

DS1086

Spread-Spectrum EconOscillator

_______________________________________________________________________________________ 3

MASTER OSCILLATOR CHARACTERISTICS

(VCC= 5V ±5%, TA= 0°C to +70°C.)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

Master Oscillator Range f

Default Master Oscillator Frequency f

Master Oscillator Frequency Tolerance

Voltage Frequency Variation

Dither Frequency Range

Integral Nonlinearity of Frequency DAC

DAC Step Size

DAC Span

DAC Default Factory default register setting 500 decimal

Offset Step Size

Offset Default OS

Dither Rate f0/4096 Hz

OSC

INL Entire range (Note 7) -0.4 +0.4 %

(Note 2) 66 133 MHz

VCC = 5V,

∆ f

= +25°C

∆

(Notes 3,17)

Over voltage range,

0 Prescaler bit J0 = 0 (Note 6) 4

= +25°C (Note 4)

Over temperature range, V (Note 5)

Prescaler bit J0 = 1 (Note 6) 2

∆ between two consecutive DAC values (Note 8)

Frequency range for one offset setting (see Table 2)

∆ between two consecutive offset values (see Table 2)

Factory default OFFSET register setting (5 LSBs) (see Table 2)

= 5V

Default frequency (f0) -0.75 +0.75

DAC step size -0.75 +0.75

Default frequency -0.75 +0.75

DAC step size -0.75 +0.75

Default frequency -0.5 +0.5

133MHz -0.5 +0.5Temperature Frequency Variation

66MHz -1.0 +1.0

97.1 MHz

10 kHz

10.24 MHz

5.12 MHz

RANGE

(5 LSBs of

RANGE register)

hex

DS1086

Spread-Spectrum EconOscillator

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS

(VCC= 5V ±5%, TA= 0°C to +70°C.)

AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE

(VCC= 5V ±5%, TA= 0°C to +70°C.)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

Frequency Stable After Prescaler Change

Frequency Stable After DAC or Offset Change

Power-Up Time t

Enable of OUT After Exiting Power-Down Mode

OUT High-Z After Entering Power-Down Mode

Load Capacitance C

Output Duty Cycle (OUT) 40 60 % PDN Rise/Fall Time 1µs

+ t

stab

pdn

(Note 9) 0.2 1 ms

(Note 10) 0.1 0.5 ms

stab

(Note 11) 15 50 pF

1 Period

500 µs

0.1 ms

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

SCL Clock Frequency f

Bus Free Time Between a STOP and START Condition

Hold Time (Repeated) START Condition

LOW Period of SCL t

HIGH Period of SCL t

Setup Time for a Repeated START

Data Hold Time t

Data Setup Time t

Rise Time of Both SDA and SCL Signals

Fall Time of Both SDA and SCL Signals

SCL

BUF

HD:STA

LOW

HIGH

SU:STA

HD:DAT

SU:DAT

Fast mode 400 Standard mode Fast mode 1.3

Standard mode

Fast mode 0.6

Standard mode

Fast mode 1.3 Standard mode Fast mode 0.6 Standard mode Fast mode 0.6

Standard mode

Fast mode

Standard mode

Fast mode 100 Standard mode Fast mode 20 + 0.1C

Standard mode

Fast mode 20 + 0.1C

Standard mode

(Note 12)

(Notes 12, 13)

(Note 12)

(Notes 12, 14, 15) 0 0.9 µs

(Note 12)

(Note 16)

4.7

4.0

4.7

4.0

4.7

250

20 + 0.1C

100

300

1000

300

1000

kHz

µs

DS1086

Spread-Spectrum EconOscillator

_______________________________________________________________________________________ 5

AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE (continued)

(VCC= 5V ±5%, TA= 0°C to +70°C.)

Note 1: All voltages are referenced to ground. Note 2: DAC and OFFSET register settings must be configured to maintain the master oscillator frequency within this range.

Correct operation of the device is not guaranteed if these limits are exceeded.

Note 3: This is the absolute accuracy of the master oscillator frequency at the default settings. Note 4: This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at

= +25°C.

Note 5: This is the percentage frequency change from the +25°C frequency due to temperature at V

= 5V. The maximum temperature change varies with the master oscillator frequency setting. The minimum occurs at the default master oscillator frequency (f

default

). The maximum occurs at the extremes of the master oscillator frequency range (66MHz or 133MHz)

(see Figure 2).

Note 6: The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency. Note 7: The integral nonlinearity of the frequency adjust DAC is a measure of the deviation from a straight line drawn between the

two endpoints of a range. The error is in percentage of the span.

Note 8: This is true when the prescaler = 1. Note 9: Frequency settles faster for small changes in value. During a change, the frequency transitions smoothly from the original

value to the new value.

Note 10: This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally

introduced to allow the oscillator to stabilize. t

stab

is equivalent to approximately 512 master clock cycles and therefore

depends on the programmed clock frequency.

Note 11: Output voltage swings can be impaired at high frequencies combined with high output loading. Note 12: A fast-mode device can be used in a standard-mode system, but the requirement t

SU:DAT

> 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line at least t

R MAX

+ t

SU:DAT

1000ns + 250ns = 1250ns before the SCL line is released.

Note 13: After this period, the first clock pulse is generated. Note 14: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V

IH MIN

of the SCL sig-

nal) in order to bridge the undefined region of the falling edge of SCL.

Note 15: The maximum t

HD:DAT

need only be met if the device does not stretch the LOW period (t

LOW

) of the SCL signal.

Note 16: C

—total capacitance of one bus line, timing referenced to 0.9 x VCCand 0.1 x VCC.

Note 17: Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr

+125°C bake, 168hr 85°C/85%RH moisture soak, and 3 solder reflow passes +240 +0/-5°C peak) followed by 1000hr max V

biased 125°C HTOL, 1000 temperature cycles at -55°C to +125°C, 96hr 130°C/85%RH/5.5V HAST and 168hr

121°C/2 ATM Steam/Unbiased Autoclave.

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

Setup Time for STOP t

Capacitive Load for Each Bus Line

NV Write-Cycle Time t

Input Capacitance C

SU:STO

Fast mode 0.6

Standard mode 4.0

(Note 16) 400 pF

5pF

10 ms

µs

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