MAXIM 78M6612 User Manual
78M6612
Power and Energy Measurement IC
19-5348; Rev 2; 1/12
MPU
RTC
TIMERS
IA
VA
IB
XIN
XOUT
VREF
V1
TX0
RX0
COM0..3
V3.3A
V3.3
SYS
VBAT
V2.5
VBIAS
SEG0..18
GNDA GNDD
SEG 24..31/
DIO 4..11
SEG 34..37/
DIO 14..17
ICE
I2C or µWire
EEPROM
POWER
FAULT
COMPARATOR
SERIAL PORTS
OSC/PLL
CONVERTER
DIO, PULSE
COMPUTE
ENGINE
FLASH
RAM
VOLTAGE REF
REGULATOR
POWER SUPPLY
TERIDIAN
78M6612
TEMP
SENSOR
32 kHz
LIVE
NEUT
CT
VB
PWR MODE
CONTROL
WAKE-UP
BATTERY
ICE_E
GNDD
V3P3D
SEG 32,33,
38/ICE
TX1
RX1
OPTIONAL
OUTLET
OPTIONAL
Teridian is a trademark and Single Converter Technology is a registered
Single-Phase, Dual-Outlet
DATA SHEET
DS_6612_001
DESCRIPTION
The Teridian™ 78M6612 is a highly integrated, single-phase,
power and energy measurement and monitoring system-onchip (SoC) that includes a 32-bit compute engine (CE), an
MPU core, RTC, and flash. Our Single Converter
Technology® with a 22-bit delta-sigma ADC, four analog
inputs, digital temperature compensation, and precision
voltage reference supports a wide range of single-phase,
dual-outlet power measurement applications with very few
external components.
With measurement technology leveraged from Maxim’s flagship
utility metering ICs, the device offers features including 32 KB
of flash program memory, 2 KB shared RAM, three low-power
modes with internal timer or external event wake-up, two
UARTs, I2C/MICROWIRE® EEPROM I/F, and an in-system
programmable flash. Complete outlet measurement unit (OMU)
and AC power monitor (AC-PMON) firmware is available or can
be preloaded into the IC.
A complete array of ICE and development tools, programming
libraries and reference designs enable rapid development and
certification of power and energy measurement solutions that
meet the most demanding worldwide electricity metering
standards.
trademark of Maxim Integrated Products, Inc.
MICROW IRE is a registered trademark of National Semiconductor Corp.
Rev 2 1
FE ATURES
• Measures Each Outlet of a Duplex Receptacle with
a Single IC
• Provides Complete Energy Measurement and
Communication Protocol Capability in a Single IC
• Intelligent Switch Control Capability
• < 0.5% Wh Accuracy Over 2000:1 Current Range
and Over Temperature
• Exceeds IEC 62053/ANSIC12.20 Standards
• Voltage Referenc e < 40 ppm/°C
• Four Sensor Inputs – VDD Referenced
• Low Jitter Wh and VARh Pulse Test Outputs
(10 kHz max)
• Pulse Count for Pulse Outputs
• Line Frequency Count for RTC
• Digital Temperature Compensation
• Sag Detection for Phase A and B
• Independent 32-Bit Compute Engine
• 46-64 Hz Line Frequency Range with Same Calibration
• Phase Compensation (±7°)
• Battery Backup for RTC and Battery Monitor
• Three Battery Modes with Wake-Up Timer:
Brownout Mode (48 µA)
LCD Mode (5.7 µA)
Sleep Mode (2.9 µA)
• Energy Display on Main Power Failure
• Wake-Up Timer
• 22-Bit Delta-Sigma ADC
• 8-Bit MPU (80515), 1 Clock Cycle per Instruction
with Integrated ICE for MPU Debug
• RTC with Temperature Com pensation
• Auto-Calibration
• Hardware watchdog Timer, Power-Fail Monitor
• LCD Driver (Up to 152 Pixels)
• Up to 18 General-Purpose I/O Pins
• 32 kHz Time Base
• 32 KB Flash with Security
• 2 KB MPU XRAM
• Two UARTs
• Digital I/O Pins Compatible with 5 V Inputs
• 64-Pin LQFP or 68-Pin QFN Package
• RoHS-Compliant (6/6) Lead(Pb)-Free Packages
• Complete Application Firmware Available
78M6612 Data Sheet DS_6612_001
Table of Contents
Hardware Description .................................................................................................................... 7
1
1.1 Hardware Overview................................................................................................................. 7
1.2 Analog Front End (AFE) .......................................................................................................... 8
1.2.1 Input Multiplexer .......................................................................................................... 8
1.2.2 A/D Converter (ADC) ................................................................................................... 9
1.2.3 FIR Filter ..................................................................................................................... 9
1.2.4 Voltage References ..................................................................................................... 9
1.2.5 Temperature Sensor.................................................................................................... 9
1.2.6 Battery Monitor ............................................................................................................ 9
1.3 Digital Computation Engine (CE) ........................................................................................... 10
1.3.1 Real-Time Monitor ..................................................................................................... 10
1.3.2 Pulse Generator ........................................................................................................ 10
1.3.3 Data RAM (XRAM) .................................................................................................... 10
1.4 80515 MPU Core .................................................................................................................. 11
1.4.1 UARTs ...................................................................................................................... 11
1.5 On-Chip Resources............................................................................................................... 11
1.5.1 Oscillator ................................................................................................................... 11
1.5.2 PLL and Internal Clocks............................................................................................. 11
1.5.3 Real-Time Clock (RTC) ............................................................................................. 12
1.5.4 Temperature Sensor.................................................................................................. 12
1.5.5 Flash Memory ........................................................................................................... 12
1.5.6 Optical Interface ........................................................................................................ 13
1.5.7 Digital I/O .................................................................................................................. 13
1.5.8 LCD Drivers .............................................................................................................. 16
1.5.9 EEPROM Interface .................................................................................................... 16
1.5.10 Hardware Watchdog Timer ........................................................................................ 17
1.5.11 Test Ports (TXUXOUT pin) ........................................................................................ 17
2 Functional Description ................................................................................................................ 18
2.1 Theory of Operation .............................................................................................................. 18
2.2 Fault and Reset Behavior ...................................................................................................... 19
2.2.1 Reset Mode ............................................................................................................... 19
2.2.2 Power Fault Circuit .................................................................................................... 19
2.3 Data Flow ............................................................................................................................. 19
2.4 CE/MPU Communication ...................................................................................................... 20
3 Application Information ............................................................................................................... 21
3.1 Connection of Sensors (CT, Resistive Shunt) ........................................................................ 21
3.2 Connecting 5 V Devices ........................................................................................................ 22
3.3 Temperature Measurement ................................................................................................... 22
3.4 Temperature Compensation .................................................................................................. 22
3.5 Connecting LCDs .................................................................................................................. 23
3.6 Connecting I2C EEPROMs .................................................................................................... 23
3.7 Connecting Three-Wire EEPROMs ....................................................................................... 24
3.8 UART0 (TX0/RX0) ................................................................................................................ 24
3.9 UART1 (TX1/RX1) ................................................................................................................ 25
3.10 Connecting V1 and Reset Pins .............................................................................................. 25
3.11 Connecting the Emulator Port Pins ........................................................................................ 26
3.12 Flash Programming ............................................................................................................... 26
3.13 MPU Firmware Library .......................................................................................................... 26
3.14 Crystal Oscillator ................................................................................................................... 26
3.15 Measurement Calibration ...................................................................................................... 27
4 Electrical Specifications .............................................................................................................. 28
4.1 Absolute Maximum Ratings ................................................................................................... 28
4.2 Recommended External Components ................................................................................... 29
2 Rev 2
DS_6612_001 78M6612 Data Sheet
4.3 Recommended Operating Conditions .................................................................................... 29
4.4 Performance Specifications ................................................................................................... 30
4.4.1 Input Logic Levels ..................................................................................................... 30
4.4.2 Output Logic Levels ................................................................................................... 30
4.4.3 Power-Fault Comparator ........................................................................................... 30
4.4.4 Battery Monitor .......................................................................................................... 31
4.4.5 Supply Current .......................................................................................................... 31
4.4.6 V3P3D Switch ........................................................................................................... 31
4.4.7 2.5V Voltage Regulator ............................................................................................. 32
4.4.8 Low Power Voltage Regulator ................................................................................... 32
4.4.9 Crystal Oscillator ....................................................................................................... 32
4.4.10 VREF, VBIAS ............................................................................................................ 33
4.4.11 LCD Drivers .............................................................................................................. 33
4.4.12 ADC Converter, V3P3A Referenced .......................................................................... 34
4.4.13 UART1 Interface........................................................................................................ 34
4.4.14 Temperature Sensor.................................................................................................. 34
4.5 Timing Specifications ............................................................................................................ 35
4.5.1 RAM and Flash Memory ............................................................................................ 35
4.5.2 Flash Memory Timing ................................................................................................ 35
4.5.3 EEPROM Interface .................................................................................................... 35
4.5.4 RESET and V1 .......................................................................................................... 35
4.5.5 RTC .......................................................................................................................... 35
5 Packaging .................................................................................................................................... 36
5.1 64-Pin LQFP Package .......................................................................................................... 36
5.1.1 Pinout........................................................................................................................ 36
5.1.2 Package Outline (LQFP 64) ....................................................................................... 37
5.1.3 Recommended PCB Land Pattern for the LQFP-64 Package..................................... 38
5.2 68-Pin QFN Package ............................................................................................................ 39
5.2.1 Pinout........................................................................................................................ 39
5.2.2 Package Outline ........................................................................................................ 40
5.2.3 Recommended PCB Land Pattern for the QFN-68 Package ...................................... 41
6 Pin Descriptions .......................................................................................................................... 42
6.1 Power/Ground Pins ............................................................................................................... 42
6.2 Analog Pins........................................................................................................................... 42
6.3 Digital Pins ............................................................................................................................ 43
7 I/O Equivalent Circuits ................................................................................................................. 44
8 Ordering Information ................................................................................................................... 45
9 Contact Information ..................................................................................................................... 45
Revision History .................................................................................................................................. 46
Rev 2 3
78M6612 Data Sheet DS_6612_001
Figures
Figure 1: IC Functional Block Diagram ..................................................................................................... 6
Figure 2: AFE Block Diagram ................................................................................................................... 8
Figure 3: Connecting an External Load to DIO Pins ............................................................................... 15
Figure 4: Functions Defined by V1 ......................................................................................................... 17
Figure 5: Voltage, Current, Momentary and Accumulated Energy ........................................................... 18
Figure 6: MPU/CE Data Flow ................................................................................................................. 19
Figure 7: MPU/CE Communication ........................................................................................................ 20
Figure 8: Resistive Voltage Divider ........................................................................................................ 21
Figure 9: Resistive Current Shunt .......................................................................................................... 21
Figure 10: Current Transformer .............................................................................................................. 21
Figure 11: Connecting LCDs .................................................................................................................. 23
Figure 12: I
Figure 13: Three-Wire EEPROM Connection ......................................................................................... 24
Figure 14: Connections for the RX0 Pin ................................................................................................. 24
Figure 15: Voltage Divider for V1 ........................................................................................................... 25
Figure 16: External Components for RESET: Development Circuit (Left), Production Circuit (Right) ....... 25
Figure 17: External Components for the Emulator Interface.................................................................... 26
Figure 18: 64-Pin LQFP Pinout .............................................................................................................. 36
Figure 19: 68-Pin QFN Pinout ................................................................................................................ 39
2
C EEPROM Connection ...................................................................................................... 23
4 Rev 2
DS_6612_001 78M6612 Data Sheet
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ....................................................... 8
Table 2: Data/Direction Registers and Internal Resources for DIO Pin Groups ....................................... 14
Table 3: DIO_DIR Control Bit ................................................................................................................. 15
Table 4: Selectable Controls using the DIO_DIR Bits ............................................................................. 16
Table 5: Absolute Maximum Ratings ...................................................................................................... 28
Table 6: Recommended External Components ...................................................................................... 29
Table 7: Recommended Operation Conditions ....................................................................................... 29
Table 8: Input Logic Levels .................................................................................................................... 30
Table 9: Output Logic Levels ................................................................................................................. 30
Table 10: Power-Fault Comparator Performance Specifications ............................................................. 30
Table 11: Power-Fault Comparator Performance Specifications (BME=1) .............................................. 31
Table 12: Supply Current Performance Specifications ............................................................................ 31
Table 13: V3P3D Switch Performance Specifications ............................................................................. 31
Table 14: 2.5 V Voltage Regulator Performance Specifications .............................................................. 32
Table 15: Low-Power Voltage Regulator Performance Specifications ..................................................... 32
Table 16: Crystal Oscillator Performance Specifications ......................................................................... 32
Table 17: VREF, VBIAS Performance Specifications.............................................................................. 33
Table 18: LCD Drivers Performance Specifications ................................................................................ 33
Table 19: ADC Converter Performance Specifications ........................................................................... 34
Table 20: UART1 Interface Performance Specifications ......................................................................... 34
Table 21: Temperature Sensor Performance Specifications ................................................................... 34
Table 22: RAM and Flash Memory Specifications .................................................................................. 35
Table 23: Flash Memory Timing Specifications ...................................................................................... 35
Table 24: EEPROM Interface Timing ..................................................................................................... 35
Table 25: RESET and V1 Timing ........................................................................................................... 35
Table 26: RTC Range ............................................................................................................................ 35
Table 27: Power/Ground Pins ................................................................................................................ 42
Table 28: Analog Pins ............................................................................................................................ 42
Rev 2 5
78M6612 Data Sheet DS_6612_001
IA
VA
MUX
XIN
XOUT
VREF
CKADC
CKTEST/
SEG19
CE
32 bit Compute
Engine
MPU
(80515)
CE
CONTROL
RX1 /
DIO1
TX1 /
DIO2 /
WPULSE /
VARPULSE
RESET
V1
EMULATOR
PORT
CE_BUSY
UART
TX
RX
XFER BUSY
COM0..3
VLC2
LCD DISPLAY
DRIVER
DATA
00-7F
PROG
000-7FF
DATA
0000-FFFF
PROG
0000-7FFF
00007FFF
MPU XRAM
(2KB)
0000-07FF
DIGITAL I/O
CONFIG
2000-20FF
I/O RAM
CE RAM
(0.5KB)
MEMORY SHARE
1000-11FF
RTCLK
RTCLK (32KHz)
MUX_SYNC
CKCE
CKMPU
CK32
CE_E
RTM_E
LCD_E
LCD_CLK
LCD_MODE
DIO
4.9MHz
<
4.9MHz
4.9MHz
GNDD
V3P3A
V3P3D
VBAT
VOLT
REG
2.5V to logic
V2P5
MPU_DIV
SUM_CYCLES
PRE_SAMPS
EQU
CKOUT_E
32KHz
TMUXOUT
MPU_RSTZ
FAULTZ
WAKE
TMUX[4:0]
CONFIGURATION
PARAMETERS
GNDA
VBIAS
CROSS
CK_GEN
OSC
(32KHz)
CK32
CKOUT_E
MCK
PLL
VREF
VREF_DIS
DIV
ADC
MUX
CTRL
MUX_DIV
CHOP_E
EQU
STRT
IB
MUX
MUX
CKFIR
4.9MHz
RTM
SEG34 / DIO14 ..
SEG37 / DIO17,
SEG39 / DIO19,
SEG40 / DIO20
WPULSE
VARPULSE
WPULSE
VARPULSE
TEST
TEST
MODE
LCD_MODE
VLC1
VLC0
LCD_E
<
4.9MHz
LCD_NUM
DIO_R
DIO_DIR
LCD_NUM
DIO_PV/PW
MUX_ALT
SEG24 / DIO4 ..
SEG31 / DIO11
SDCK
SDOUT
SDIN
E_RXTX/SEG38
E_TCLK/SEG33
E_RST/SEG32
FLASH
(32KB)
FLSH66ZT
V3P3A
FIR_LEN
FIR
SEG0..18
EEPROM
INTERFACE
DIO_EEX
CK_2X
ECK_DIS
V3P3D
LCD_GEN
RTC
RTC_INC_SEC
RTC_DEC_SEC
VB
VBIAS
MEMORY
SHARE
SEG32,33
SEG19,38
E_RXTX
E_TCLK
E_RST (Open Drain)
ICE_E
DIO1,2
VREF_CAL
∆Σ ADC
CONVERTER
+
-
VREF
ADC_E
RTM_0..3
CE_LCTN
PLS_MAXWIDTH
PLS_INTERVAL
PLS_INV
LCD_BLKMAP
LCD_SEG
LCD_Y
SLEEP
LCD_ONLY
V3P3SYS
TEST
MUX
DIO3,
DIO21 / SEG41
(68 Pin Package Only)
V3P3D
TEMP
VBAT
VBAT
VBIAS
OPTICAL
COMP_STAT
POWER FAULT
OPT_TXE
OPT_TXINV
OPT_RXINV
OPT_RXDIS
MOD
OPT_TXMOD
OPT_FDC
CE_LCTN
(SEG13 and SEG 14
on 68 Pin Package
Only)
Figure 1: IC Functional Block Diagram
6 Rev 2
DS_6612_001 78M6612 Data Sheet
1 Hardware Description
1.1 Hardware Overview
The Teridian 78M6612 single-chip measurement and monitoring IC integrates all the primary AC
measurement and control blocks required to implement a solid-state electricity Power and Energy
Measurement function. The 78M6618 includes:
• A four-input analog front end (AFE)
• An independent digital computation engine (CE)
• An 8051-compatible microprocessor (MPU) which executes one instruction per clock cycle (80515)
• A precision voltage reference
• A temperature sensor
• LCD drivers
• RAM and Flash memory
• A real time clock (RTC)
• A variety of I/O pins
Various current sensor technologies are supported including Current Transformers (CT), and Resistive
Shunts.
In a typical application, the 32-bit compute engine (CE) of the 78M6612 sequentially processes the
samples from the analog inputs on pins IA, VA, IB, VB and performs calculations to measure active
energy (Wh), reactive energy (VARh), A
measurements are then accessed by the MPU, processed further, and output using the peripheral
devices available to the MPU.
In addition to advanced measurement functions, the real time clock function allows the 78M6612 to
record time of use (TOU) measurement information for multi-rate applications and to time-stamp events.
Measurements can be displayed on 3.3 V LCDs if desired. Flexible mapping of LCD display segments
will facilitate utilization of existing custom LCDs. Design trade-off between number of LCD segments vs.
DIO pins can be implemented in software to accommodate various requirements.
In addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature
compensation mechanism includes a temperature sensor and associated controls for correction of
unwanted temperature effects on measurement and RTC accuracy, e.g. to meet the requirements of
ANSI and IEC standards. Temperature-dependent external components such as crystal oscillator,
current transformers (CTs), and their corresponding signal conditioning circuits can be characterized and
their correction factors can be programmed to produce measurements with exceptional accuracy over the
industrial temperature range.
A block diagram of the IC is shown in Figure 1. A detailed description of various functional blocks follows.
2
h, and V2h for four-quadrant measurement. These
Rev 2 7
78M6612 Data Sheet DS_6612_001
Mux State
Mux State
EQU 0 1 2 3 0 1 2 3
IA
VA
MUX
VREF
4.9MHz
VBIAS
CROSS
CK32
VREF
VREF_DIS
MUX
CTRL
MUX_DIV
CHOP_E
EQU
IB
MUX
MUX_ALT
V3P3A
FIR_LEN
FIR
VB
VBIAS
VREF_CAL
∆Σ ADC
CONVERTER
+
-
VREF
ADC_E
TEMP
VBAT
FIR_DONE
FIR_START
1.2 Analog Front End (AFE)
The AFE functions as a data acquisition system, controlled by the MPU. It consists of an input
multiplexer, a delta-sigma A/D converter, and a voltage reference. The main signals (IA, VA, IB, VB) are
sampled and the ADC counts obtained are stored in CE DRAM where they can be accessed by the CE
and, if necessary, by the MPU.
Figure 2: AFE Block Diagram
1.2.1 Input Multiplexer
The input multiplexer supports up to four input signals that are applied to pins IA, VA, IB, and VB of the
device. Additionally, using the alternate multiplexer selection, it has the ability to select temperature and
the battery voltage. The multiplexer can be operated in two modes:
• During a normal multiplexer cycle, the signals from the IA, IB, VA, and VB pins are selected.
• During the alternate multiplexer cycle, the temperature signal (TEMP) and the battery monitor are
selected, along with the signal sources shown in Table 1. To prevent unnecessary drainage on the
battery, the battery monitor is enabled only with the BME bit (0x2020[6]) in the I/O RAM.
The alternate multiplexer cycles are usually performed infrequently (e.g. every second or so) by the MPU.
In order to prevent disruption of the voltage tracking PLL and voltage allpass networks, VA is not
replaced in the ALT mux selections. Table 1 details the regular and alternative multiplexer sequences.
Missing samples due to an ALT multiplexer sequence are filled in by the CE.
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
Regular MUX Sequence ALT MUX Sequence
2 IA VA IB VB TEMP VA VBAT VB
In a typical application, IA and IB are connected to current sensors that sense the current on each branch
of the line voltage. VA and VB are typically connected to voltage sensors through resistor dividers. The
multiplexer control circuit is clocked by CK32, the 32.768 kHz clock from the PLL block, and launches with
each new pass of the CE program. The duration of each multiplexer state depends on the number of
ADC samples processed by the FIR.
8 Rev 2
DS_6612_001 78M6612 Data Sheet
1.2.2 A/D Converter (ADC)
A single delta-sigma A/D converter digitizes the voltage and current inputs to the 78M6612. The
resolution of the ADC is configurable to either 21 or 22 bit. At the end of each ADC conversion, the FIR
filter output data is stored into the CE RAM location.
1.2.3 FIR Filter
The finite impulse response filter is an integral part of the ADC and it is optimized for use with the
multiplexer. The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the
end of each ADC conversion, the output data is stored into the CE RAM location determined by the
multiplexer selection. FIR data is stored LSB justified, but shifted left by nine bits.
1.2.4 Voltage References
The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero
techniques. The reference is trimmed to minimize errors caused by component mismatch and drift. The
result is a voltage output with a predictable temperature coefficient.
1.2.5 Temperature Sensor
The 78M6612 includes an on-chip temperature sensor implemented as a bandgap reference. It is used
to determine the die temperature The MPU reads the temperature sensor output during alternate
multiplexer cycles. The primary use of the temperature data is to determine the magnitude of
compensation required to offset the thermal drift in the system (see Section 3.4 Temperature
Compensation).
1.2.6 Battery Monitor
The 78M6618 also has the ability to measure battery voltage by the ADC during alternative multiplexer
frames. When set, an on-chip 45 kΩ load resistor is applied to the battery and a scaled fraction of the
battery voltage is applied to the ADC input. Battery operating modes are not supported in all firmware
libraries. Contact Maxim support for more information.
Rev 2 9
78M6612 Data Sheet DS_6612_001
1.3 Digital Computation Engine (CE)
The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to
accurately measure energy. The CE calculations and processes include:
• Multiplication of each current sample with its associated voltage sample to obtain the energy per
sample (when multiplied with the constant sample time).
• Frequency-insensitive delay cancellation on all four channels (to compensate for the delay between
samples caused by the multiplexing scheme).
• 90° phase shifter (for narrowband VAR calculations).
• Pulse generation.
• Monitoring of the input signal frequency (for frequency and phase information).
• Monitoring of the input signal amplitude (for sag detection).
• Scaling of the processed samples based on calibration coefficients.
CE code is provided by Maxim as a part of the application firmware available. The CE is not
programmable by the user. Measurement algorithms in the CE code can be customized by Maxim
upon request.
The CE program resides in Flash memory. Allocated Flash space for the CE program cannot exceed
1024 words (2 KB). The CE can access up to 2 KB of data RAM (XRAM), or 512 32-bit data words. The
CE is also aided by support hardware to facilitate implementation of equations, pulse counters and
accumulators. Usage of this hardware is firmware specific.
1.3.1 Real-Time Monitor
The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable CE
DRAM locations at full sample rate
for system debug purposes. The four monitored locations can be serially
output to the TMUXOUT pin via the digital output multiplexer at the beginning of each CE code pass.
The RTM output is clocked by CKTEST.
1.3.2 Pulse Generator
The CE provides four pulse generators used to output CE status indicators (e.g. SAG) directly to
designated DIO pins.
1.3.3 Data RAM (XRAM)
The CE and MPU use a single general-purpose Data RAM (also referred to as XRAM). When the MPU
and CE are clocking at maximum frequency (10 MHz), the RAM may be accessed up to four times during
each 100 ns interval. These consist of two MPU accesses, one CE access and one SPI access.
10 Rev 2
DS_6612_001 78M6612 Data Sheet
1.4 80515 MPU Core
The 78M6612 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one
clock cycle. Using a 5 MHz (4.9152 MHz) clock results in a processing throughput of 5 MIPS. The 80515
architecture eliminates redundant bus states and implements parallel execution of fetch and execution
phases. Normally a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte
instructions are performed in a single machine cycle (MPU clock cycle). This leads to an 8x average
performance improvement (in terms of MIPS) over the Intel
8051 device running at the same clock
frequency. Actual processor clocking speed can be adjusted to the total processing demand of the
application (measurement calculations, memory management and I/O management).
Typical power and energy measurement functions based on the results provided by the internal
32-bit compute engine (CE) are available for the MPU as part of Maxim’s standard library. A
standard ANSI “C” 80515 application program library is available to help reduce design cycle.
1.4.1 UARTs
The 78M6612 includes two UARTs (UART0 and UART1) that can be programmed to communicate with a
variety of external devices. The UARTs are dedicated 2-wire serial interfaces, which can communicate at
rates up to 38,400 bits/s. All UART transfers are programmable for parity enable, parity, 2 stop bits/1
stop bit and XON/XOFF option for variable communication baud rates from 300 to 38,400 bps.
1.5 On-Chip Resources
1.5.1 Oscillator
The 78M6612 oscillator drives a standard 32.768 kHz watch crystal. These crystals are accurate and do
not require a high-current oscillator circuit. The 78M6612 oscillator has been designed specifically to
handle these crystals and is compatible with their high impedance and limited power handling capability.
1.5.2 PLL and Internal Clocks
Timing for the device is derived from the 32.768 kHz oscillator output. On-chip timing functions include:
• The MPU master clock
• A real time clock (RTC)
• The delta-sigma sample clock.
The two general-purpose counter/timers are contained in the MPU.
The ADC master clock, CKADC, is generated by an on-chip PLL. It multiplies the oscillator output
frequency (CK32) by 150.
The CE clock frequency is always CK32 * 150, or 4.9152 MHz, where CK32 is the 32 kHz clock. The
MPU clock frequency is determined by MPU_DIV and can be 4.9152 MHz *2
varies from 0 to 7 (MPU_DIV is 0 on power-up). This makes the MPU clock scalable from 4.9152 MHz
down to 38.4 kHz. The circuit also generates a 2x MPU clock for use by the emulator. This 2x MPU
clock is not generated when ECK_DIS is asserted by the MPU.
The setting of MPU_DIV is maintained when the device transitions to BROWNOUT mode, but the time
base in BROWNOUT mode is 28,672 Hz.
-
MPU_DIV
Hz where MPU_DIV
Rev 2 11
78M6612 Data Sheet DS_6612_001
1.5.3 Real-Time Clock (RTC)
The RTC is driven directly by the crystal oscillator. The RTC consists of a counter chain and output
registers. The counter chain consists of seconds, minutes, hours, day of week, day of month, month, and
year. The RTC is not supported in all firmware libraries. Contact Maxim support for more information.
1.5.4 Temperature Sensor
The device includes an on-chip temperature sensor for determining the temperature of the bandgap
reference. The MPU may request an alternate multiplexer frame containing the temperature sensor
output by asserting MUX_ALT. The primary use of the temperature data is to determine the magnitude of
compensation required to offset the thermal drift in the system (see Section 3.4 Temperature
Compensation).
1.5.5 Flash Memory
The 78M6612 includes 32 KB of on-chip Flash memory. The Flash memory primarily contains MPU and
CE program code. It also contains images of the CE DRAM, MPU RAM, and I/O RAM. On power-up,
before enabling the CE, the MPU copies these images to their respective locations.
The Flash memory is segmented into individually erasable 1024-byte pages. Flash space allocated for the CE
program is limited to 1024 words (2 KB). The CE program must begin on a 1-KB boundary of the Flash address
space.
Flash Write Procedures
The MPU has the ability to write to the Flash memory when the CE is disabled. As an alternative to using Flash, a
small EEPROM can store data without compromises. EEPROM interfaces are included in the device.
Updating Individual Bytes in Flash Memory
The original state of a Flash byte is 0xFF (all ones). Once a value other than 0xFF is written to a Flash memory cell,
overwriting with a different value usually requires that the cell be erased first. Since cells cannot be erased
individually, the page has to be copied to RAM, followed by a page erase. After this, the page can be updated in
RAM and then written back to the Flash memory.
Flash Erase Procedures
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special
pattern/sequence requirements prevent inadvertent erasure of the Flash memory.
The mass erase sequence is:
1. Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1].
2. Write pattern 0xAA to FLSH_ERASE (SFR address 0x94).
The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is:
1. Write the page address to FLSH_PGADR (SFR address 0xB7[7:1].
2. Write pattern 0x55 to FLSH_ERASE (SFR address 0x94).
12 Rev 2
DS_6612_001 78M6612 Data Sheet
1.5.6 Optical Interface
The device includes an interface to implement an IR/optical port on UART1. The pin TX1 is designed to
directly drive an external LED for transmitting data on an optical link. The pin RX1 is designed to sense
the input from an external photo detector used as the receiver for the optical link. The IR/optical interface
is not supported in all firmware libraries. Contact Maxim support for more information.
1.5.7 Digital I/O
The device includes up to 18 pins (QFN 68 package) or 16 pins (LQFP 64 package) of general purpose
digital I/O. These pins are compatible with 5V inputs (no current-limiting resistors are needed). Some of
them are dedicated DIO (DIO3), some are dual-function that can alternatively be used as LCD drivers
(DIO4-11, 14-17, 19-21) and some share functions with the optical port (DIO1, DIO2). On reset or
power-up, all DIO pins are inputs until they are configured for the desired direction under MPU control.
The pins are configured by the DIO registers and by the five bits of the LCD_NUM register (located in I/O
RAM). Once declared as DIO, each pin can be configured independently as an input or output with the
DIO_DIRn bits. A 3-bit configuration word, DIO_Rx, can be used for certain pins, when configured as
DIO, to individually assign an internal resource such as an interrupt or a timer control. Table 2 lists the
direction registers and configurability associated with each group of DIO pins. Table 3 shows the configuration for a DIO pin through its associated bit in its DIO_DIR register.
Tables showing the relationship between LCD_NUM and the available segment/DIO pins can be found in
Section 3.5 Connecting LCDs and in Section 4.3 I/O Description under LCD_NUM[4:0].
Rev 2 13
78M6612 Data Sheet DS_6612_001
7
3
1
Configurable
2
4
DIO_DIR2 (SFR 0xA1)
Configurable
Table 2: Data/Direction Registers and Internal Resources for DIO Pin Groups
DIO x 1 2 3 4 5 6 7 8 9
Pin no. (64 LQFP)
Pin no. (68 QFN)
Data Register
Direction Register
– 5
– 6
0
3 –
3 5
– 1 2 3 4 5 6 7 0 1 2 3 – – 6 7
– 1 2 3 4 5 6 7 0 1 2 3 – – 6 7
36 37 38 39 40 41 42 4
39 40 41 42 43 44 45 4
–
–
Internal Resources
–
Y Y Y Y Y Y Y Y Y Y Y – – – –
DIO 16
Pin no. (64 LQFP) 22
Pin no. (68 QFN) 23
1
7
1
1
3
1
8
–
–
19 20 2
23 4
24 47 6
22 2
1
– – –
8
3
0 1 – 3 4 5 – –
Data Register
Direction Register
Internal Resources
0 1 – 3 4 5 – –
N N – N N N – –
DIO2=P2 (SFR 0xA0)
10 11 12 13 14 1
– –
– –
6
DIO1=P1 (SFR 0x90)
DIO_DIR1 (SFR 0x91)
5
20 2
21 2
2
14 Rev 2
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