Maverick EP7312 User Manual
User’s Manual
EP7312 USER’S MANUAL
EP7312
Copyright © 2000– Cirrus Logic Inc. All Rights Reserved.
Note: Cirrus Logic assumes no responsibility for the attached information which is provided
“AS IS” without warranty of any kind (expressed or implied).
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2000
(All Rights Reserved)
SEPT ‘00
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1
TABLE OF CONTENTS
PART I: EP7312 USER’S MANUAL
1. CONVENTIONS ...................................................................................................................... 10
1.1 Acronyms and Abbreviations ............................................................................................ 10
1.2 Units of Measurement ......................................................................................................11
1.3 General Conventions ........................................................................................................12
1.4 Pin Description Conventions ............................................................................................. 12
2. EP7312 FUNCTIONAL DESCRIPTION ................................................................................. 13
2.1 CPU Core .......................................................................................................................... 14
2.2 State Control ..................................................................................................................... 15
2.2.1 Standby State .......................................................................................................... 15
2.2.1.1 UART in Standby State ............................................................................... 17
2.2.2 Idle State ................................................................................................................. 17
2.2.3 Keyboard Interrupt ................................................................................................... 18
2.3 Power-Up Sequence ......................................................................................................... 18
2.4 Resets ............................................................................................................................... 19
2.5 Clocks ............................................................................................................................... 20
2.5.1 On-Chip PLL ............................................................................................................ 20
2.5.1.1 Characteristics of the PLL Interface ............................................................ 20
2.5.2 External Clock Input (13 MHz) ................................................................................ 21
2.5.3 Dynamic Clock Switching When in the PLL Clocking Mode .................................... 22
2.6 Interrupt Controller ............................................................................................................ 22
2.6.1 Interrupt Latencies in Different States ..................................................................... 24
2.6.1.1 Operating State ........................................................................................... 24
2.6.1.2 Idle State ..................................................................................................... 24
2.6.1.3 Standby State .............................................................................................. 24
2.7 EP7312 Boot ROM .......................................................................................................... 26
2.8 Memory and I/O Expansion Interface ............................................................................... 27
2.9 SDRAM Controller ............................................................................................................ 28
2.10 SDRAM Initialization ....................................................................................................... 31
2.11 CL-PS6700 PC Card Controller Interface ....................................................................... 32
2.12 Serial Interfaces .............................................................................................................. 35
2.13 CODEC Sound Interface ................................................................................................. 36
2.14 Endianness ..................................................................................................................... 37
2.15 Internal UARTs (Two) and SIR Encoder ......................................................................... 39
2.15.1 Digital Audio Interface ........................................................................................... 40
2.15.1.1 DAI Operation ............................................................................................ 41
2.15.1.2 DAI Frame Format ..................................................................................... 42
2.15.1.3 DAI Signals ................................................................................................ 43
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information
describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained
in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express
or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third part ies. This
document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied,
reproduced, stored in a retrieval system, or transmi tted, in any for m or by any means (e lectron ic, mechanic al, photogra phic, or other wise ) withou t the pr ior wri tte n
consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may
be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior
written consent of Ci rrus Logic, Inc.Furth ermore, no part of this pu blicati on may be u sed as a basis fo r manufacture or sale o f any items without the prior written
consent of Cirrus Logi c, Inc. The names of pr oduct s of Cirrus Log ic, Inc. or other vendo rs and suppliers appearing in this document may be trademarks or servi ce
marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at
http://www.cirrus.com.
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2.15.2 ADC Interface — Master Mode Only SSI1 (Synchronous Serial Interface) ...........43
2.15.3 Master / Slave SSI2 (Synchronous Serial Interface 2) .......................................... 44
2.15.3.1 Read Back of Residual Data ..................................................................... 46
2.15.3.2 Support for Asymmetric Traffic .................................................................. 46
2.15.3.3 Continuous Data Transfer ......................................................................... 47
2.15.3.4 Discontinuous Clock ..................................................................................47
2.15.3.5 Error Conditions ......................................................................................... 47
2.15.3.6 Clock Polarity .............................................................................................47
2.16 LCD Controller with Support for On-Chip Frame Buffer .................................................. 48
2.17 Timer Counters ...............................................................................................................50
2.17.1 Free Running Mode ...............................................................................................50
2.17.2 Prescale Mode ...................... ....... ...... ....... ...... ...... ....... ...... ....... ...... .......................50
2.18 Real Time Clock ..............................................................................................................50
2.18.1 Characteristics of the Real Time Clock Interface ...................................................51
2.19 Dedicated LED Flasher ................................................................................................... 51
2.20 Two PWM Interfaces .......................................................................................................51
2.21 Boundary Scan ................................................................................................................52
2.22 In-Circuit Emulation .........................................................................................................53
2.22.1 Introduction ........................................................... ....... ....................................... ...53
2.22.2 Functionality .................................................... ...... ....... ...... ....... ...... ....... ...... ....... .. .53
2.23 Maximum-Configured EP7312-Based System ................................................................53
2.24 I/O Buffer Characteristics ................................................................................................55
3. TEST MODES . ....... ...... ....... ...... ....... ...... ....... ...... ....................................... ...... ....... ...... . ...... ... 56
3.1 Oscillator and PLL Bypass Mode ...................................................................................... 56
3.2 Oscillator and PLL Test Mode ........................................................................................... 57
3.3 Debug / ICE Test Mode ....................................................................................................58
3.4 Hi-Z (System) Test Mode ................................................................................................. 58
3.5 Software Selectable Test Functionality ............................................................................58
PART II: PIN AND REGISTER REFERENCE
4. PIN DESCRIPTIONS ... ....... ...... ....... ...... ....................................... ...... ....... ...... ....... ...... ...... . ... 60
4.1 External Signal Functions ................................................................................................ 60
4.2 SSI / CODEC / DAI Pin Multiplexing ................................................................................ 66
4.3 Output Bi-Directional Pins ..............................................................................................66
5. EP7312 MEMORY MAP ......................................................................................................... 67
6. REGISTER DESCRIPTIONS .................................................................................................. 68
6.1 Internal Registers ..............................................................................................................68
6.1.1 PADR — Port A Data Register ................................................................................ 72
6.1.2 PBDR — Port B Data Register ................................................................................ 72
6.1.3 PDDR — Port D Data Register ................................................................................73
6.1.4 PADDR — Port A Data Direction Register ..............................................................73
6.1.5 PBDDR — Port B Data Direction Register ..............................................................73
6.1.6 PDDDR — Port D Data Direction Register ..............................................................73
6.1.7 PEDR — Port E Data Register ................................................................................ 73
6.1.8 PEDDR — Port E Data Direction Register ..............................................................73
6.2 System Control Registers .................................................................................................74
6.2.1 SYSCON1 — System Control Register 1 ................................................................74
6.2.2 SYSCON2— System Control Register 2 .................................................................77
6.2.3 SYSCON3 — System Control Register 3 ...............................................................79
6.2.4 SYSFLG1 — System Status Flags Register ............................................................80
6.2.5 SYSFLG2 — System Status Register 2 ..................................................................82
6.3 Interrupt Registers .............................................................................................................83
6.3.1 INTSR1 — Interrupt Status Register 1 ....................................................................83
6.3.2 INTMR1 — Interrupt Mask Register 1 .....................................................................84
4 DS508UM1
6.3.3 INTSR2 — Interrupt Status Register 2 .................................................................... 85
6.3.4 INTMR2 — Interrupt Mask Register 2 ..................................................................... 85
6.3.5 INTSR3 — Interrupt Status Register 3 .................................................................... 86
6.3.6 INTMR3 — Interrupt Mask Register 3 ..................................................................... 86
6.4 Memory Configuration Registers ...................................................................................... 86
6.4.1 MEMCFG1 — Memory Configuration Register 1 .................................................... 86
6.4.2 MEMCFG2 — Memory Configuration Register 2 .................................................... 87
6.5 Timer / Counter Registers ................................................................................................. 90
6.5.1 TC1D — Timer Counter 1 Data Register ................................................................ 90
6.5.2 TC2D — Timer Counter 2 Data Register ................................................................ 90
6.5.3 RTCDR — Real Time Clock Data Register ............................................................. 90
6.5.4 RTCMR — Real Time Clock Match Register .......................................................... 90
6.6 LEDFLSH Register ...........................................................................................................90
6.7 SDCONF — SDRAM Control Register ............................................................................. 91
6.8 SDRFPR — SDRAM Refresh Period Register ................................................................. 92
6.9 UNIQID Register ............................................................................................................... 92
6.10 RANDID0 Register ..........................................................................................................92
6.11 RANDID1 Register ..........................................................................................................93
6.12 RANDID2 Register ..........................................................................................................93
6.13 RANDID3 Register ..........................................................................................................93
6.14 PMPCON — Pump Control Register .............................................................................. 93
6.15 CODR — CODEC Interface Data Register ..................................................................... 94
6.16 UART Registers .............................................................................................................. 95
6.16.1 UARTDR1–2, UART1–2 Data Regist ers ............................................................... 95
6.16.2 UBRLCR1–2 UART1–2 Bit Rate and Line Control Registers ............................... 96
6.17 LCD Registers ................................................................................................................. 97
6.17.1 LCDCON — LCD Control Register ....................................................................... 97
6.17.2 PALLSW — Least Significant Word — LCD Palette Register ............................... 99
6.17.3 PALMSW — Most Significant Word — LCD Palette Register ............................... 99
6.17.4 FBADDR — LCD Frame Buffer Start Address Register ...................................... 100
6.18 SSI Registers ................................................................................................................ 101
6.18.1 SYNCIO — Synchronous Serial ADC Interface Data Register ........................... 101
6.19 STFCLR — Clear All “Start Up Reason” Flags Location .............................................. 102
6.20 End Of Interrupt Locations ............................................................................................ 102
6.20.1 BLEOI Battery Low End of Interrupt .................................................................... 102
6.20.2 MCEOI Media Changed End of Interrupt ............................................................ 102
6.20.3 TEOI Tick End of Interrupt Location .................................................................... 102
6.20.4 TC1EOI TC1 End of Interrupt Location ............................................................... 103
6.20.5 TC2EOI TC2 End of Interrupt Location ............................................................... 103
6.20.6 RTCEOI — RTC Match End of Interrupt ............................................................. 103
6.20.7 UMSEOI — UART1 Modem Status Changed End of Interrupt ........................... 103
6.20.8 COEOI — CODEC End of Interrupt Location ...................................................... 103
6.20.9 KBDEOI — Keyboard End of Interrupt Location ................................................. 103
6.20.10 SRXEOF — End of Interrupt Location ............................................................... 103
6.21 State Control Registers ................................................................................................. 104
6.21.1 STDBY — Enter the Standby State Location ...................................................... 104
6.21.2 HALT — Enter the Idle State Location ................................................................ 104
6.22 SS2 Registers ............................................................................................................... 104
6.22.1 SS2DR — Synchronous Serial Interface 2 Data Register ................................... 104
6.22.2 SS2POP — Synchronous Serial Interface 2 Pop Residual Byte ......................... 104
6.23 DAI Register Definitions ................................................................................................ 105
6.23.1 DAIR — DAI Control Register ............................................................................. 106
6.23.1.1 DAI Enable (DAIEN) ................................................................................ 107
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6.23.1.2 DAI Interrupt Generation .........................................................................107
6.23.1.3 Left Channel Transmit FIFO Interrupt Mask (LCTM) ...............................107
6.23.1.4 Left Channel Receive FIFO Interrupt Mask (LARM) ................................ 107
6.23.1.5 Right Channel Transmit FIFO Interrupt Mask (RCTM) ............................107
6.23.1.6 Right Channel Receive FIFO Interrupt Mask (RCRM) ............................108
6.23.2 DAI64Fs Control Register .................. ....... ...... ...... ....... ....................................... . 109
6.23.3 DAI Data Registers ................................................................... ...... ....... ..............110
6.23.3.1 DAIDR0 — DAI Data Register 0 ..............................................................110
6.23.3.2 DAIDR1 — DAI Data Register 1 ..............................................................111
6.23.3.3 DAIDR2 — DAI Data Register 2 ..............................................................112
6.23.4 DAISR — DAI Status Register ........................ ...... ....... ...... .................................. 113
6.23.4.1 Right Channel Transmit FIFO Service Request Flag (RCTS) .................115
6.23.4.2 Right Channel Receive FIFO Service Request Flag (RCRS) ..................115
6.23.4.3 Left Channel Transmit FIFO Service Request Flag (LCTS) ....................115
6.23.4.4 Left Channel Receive FIFO Service Request Flag (LCRS) ..................... 115
6.23.4.5 Right Channel Transmit FIFO Underrun Status (RCTU) .........................115
6.23.4.6 Right Channel Receive FIFO Overrun Status (RCRO) ...........................115
6.23.4.7 Left Channel Transmit FIFO Underrun Status (LCTU) ............................116
6.23.4.8 Left Channel Receive FIFO Overrun Status (LCRO) ..............................116
6.23.4.9 Right Channel Transmit FIFO Not Full Flag (RCNF) ...............................116
6.23.4.10 Right Channel Receive FIFO Not Empty Flag (RCNE) .........................116
6.23.4.11 Left Channel Transmit FIFO Not Full Flag (LCNF) ................................116
6.23.4.12 Left Channel Receive FIFO Not Empty Flag (LCNE) ............................116
6.23.4.13 FIFO Operation Completed Flag (FIFO) ................................................116
7. LOCATIONS / NAMES OF PINS .......................................................................................... 117
7.1 208-Pin LQFP Pin Diagram .............................................................................................117
7.2 256-Pin PBGA Pin Diagram ............................................................................................ 118
8. APPENDIX A: BOOT CODE ................................................................................................ 119
LIST OF FIGURES
Figure 1. EP7312 Block Diagram..................................................................................................14
Figure 2. State Diagram ................................................................................................................ 15
Figure 3. CLKEN Timing Entering the Standby State ................................................................... 21
Figure 4. CLKEN Timing Exiting the Standby State......................................................................21
Figure 5. CODEC Interrupt Timing...................................................... ...... ....... ...... ....... ...... ....... ...37
Figure 6. Portion of the EP7312 Block Diagram Showing Multiplexed Feature ............................40
Figure 7. Digital Audio Clock Generation ...................................................................................... 42
Figure 8. EP7312 Rev B- Digital Audio Interface Timing – MSB / Left Justified format ................43
Figure 9. SSI2 Port Directions in Slave and Master Mode............................................................45
Figure 10. Residual Byte Reading.................................................................................................46
Figure 11. Video Buffer Mapping...................................................................................................49
Figure 12. Device ID Register ....................................................................................................... 52
Figure 13. A Maximum EP7312 Based System ............................................................................ 54
Figure 14. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram.........................................117
Figure 15. 256-Ball Plastic Ball Grid Array Diagram ...................................................................118
Figure 15. 256-Ball Plastic Ball Grid Array Diagram ...................................................................118
6 DS508UM1
LIST OF TABLES
Table 1. Acronyms and Abbreviations .......................................................................................... 10
Table 2. Unit of Measurement....................................................................................................... 11
Table 3. Pin Description Conventions........................................................................................... 12
Table 4. Peripheral Status in Different Power States.................................................................... 16
Table 5. Exception Priority Handling............................................................................................. 22
Table 6. Interrupt Allocation for the First Interrupt Register .......................................................... 23
Table 7. Interrupt Allocation in the Second Interrupt Register ...................................................... 23
Table 8. Interrupt Allocation in the Third Interrupt Register .......................................................... 23
Table 9. External Interrupt Sources .............................................................................................. 25
Table 10. Chip Select Address Ranges After Boot from On-Chip Boot ROM............................... 26
Table 11. Boot Options ................................................................................................................. 27
Table 12. SDRAM Configurations (SDRAM 32-Bit Memory Interface)......................................... 29
Table 13. SDRAM Configurations (SDRAM 16-Bit Memory Interface)......................................... 30
Table 14. SDRAM Address Pin Connections................................................................................ 31
Table 15. CL-PS6700 Memory Map.............................................................................................. 32
Table 16. Space Field Decoding................................................................................................... 33
Table 17. Serial Interface Options................................................................................................. 35
Table 18. Serial Pin Assignments................................................................................................. 35
Table 19. Effect of Endianness on Read Operations.................................................................... 38
Table 20. Effect of Endianness on Write Operations .................................................................... 38
Table 21. Relationship Between Audio Clocks/ Clock Sources/ Sample Frequencies ................. 41
Table 22. Matrix for Programming the MUX.................................................................................. 42
Table 23. ADC Interface Operation Frequencies.......................................................................... 44
Table 24. Instructions Supported in JTAG Mode .......................................................................... 52
Table 25. I/O Buffer Output Characteristics .................................................................................. 55
Table 26. EP7312 Hardware Test Modes..................................................................................... 56
Table 27. Oscillator and PLL Test Mode Signals.......................................................................... 57
Table 28. Software Selectable Test Functionality......................................................................... 58
Table 29. External Signal Functions .............................................................................................60
Table 30. SSI/CODEC/DAI Pin Multiplexing ................................................................................. 66
Table 31. Output Bi-Directional Pins............................................................................................. 66
Table 32. EP7312 Memory Map in External Boot Mode............................................................... 67
Table 33. EP7312 Internal Registers (Little Endian Mode)........................................................... 69
Table 34. EP7312 Internal Registers (Big Endian Mode) ............................................................. 72
Table 35. SYSCON1..................................................................................................................... 74
Table 36. SYSCON2..................................................................................................................... 77
Table 37. SYSCON3..................................................................................................................... 79
Table 38. SYSFLG1...................................................................................................................... 80
Table 39. SYSFLG2...................................................................................................................... 82
Table 40. INTSR1 ......................................................................................................................... 83
Table 41. INSTR2 ......................................................................................................................... 85
Table 42. INTSR3 ......................................................................................................................... 86
Table 43. Values of the Bus Width Field....................................................................................... 88
Table 44. Values of the Wait State Field at 13 MHz and 18 MHz................................................. 88
Table 45. Values of the Wait State Field at 36 MHz ..................................................................... 89
Table 46. MEMCFG2 .................................................................................................................... 89
Table 47. LED Flash Rates........................................................................................................... 91
Table 48. LED Duty Ratio ............................................................................................................. 91
Table 49. PMPCON ...................................................................................................................... 94
Table 50. Sense of PWM control lines.......................................................................................... 94
Table 51. UARTDR1-2 UART1-2.................................................................................................. 95
Table 53. LCDCON....................................................................................................................... 97
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Table 54. Grayscale Value to Color Mapping..............................................................................100
Table 55. SYNCIO.......................................................................................................................102
Table 56. DAI Control Register ...................................................................................................106
Table 57. DAI64Fs Control Register ........................................................................................... 109
Table 58. Clock Source for 64 fs and 128 fs ............................................................................... 109
Table 59. DAI Data Register 0 ....................................................................................................110
Table 60. DAI Data Register 1 ....................................................................................................111
Table 61. DAI Data Register 2 ....................................................................................................112
Table 62. DAI Control, Data and Status Register Locations....................................................... 113
8 DS508UM1
Part I: EP7312 User’s Manual
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1. CONVENTIONS
This section presents acronyms, abbreviations, units of measurement, and conventions used in this data
sheet.
1.1 Acronyms and Abbreviations
Table 1 lists abbreviations and acronyms used in
this data sheet.
Acronym/
Abbreviation
AC alternating current
A/D analog-to-digital
ADC analog-to-digital converter
CAS Column Address Strobe
CMOS complementary metal oxide
semiconductor
CODEC coder / decoder
CPU central processing unit
D/A digital-to-analog
DC direct current
DMA direct-memory access
EPB embedded peripheral bus
FCS frame check sequence
FIFO first in / first out
fs Sample Frequency
GPIO general purpose I/O
ICT in circuit test
IR infrared
IrDA Infrared Data Association
JTAG Joint Test Action Group
LCD liquid crystal display
LED light-emitting diode
Table 1. Acronyms and Abbreviations
Definition
Acronym/
Abbreviation
LQFP low profile quad flat pack
LSB least significant bit
MIPS millions of instructions per second
MMU memory management unit
MSB most significant bit
PBGA plastic ball grid array
PCB printed circuit board
PDA personal digital assistant
PIA peripheral interface adapter
PLL phase locked loop
PSU powe r su ppl y uni t
p/u pull-up resistor
RAM random access memory
RAS Row Address Strobe
RISC reduced instruction set computer
ROM read-only memory
RTC Real Time Clock
SDRAM Synchronous Dynamic RAM
SIR slow (9600–115.2 kbits/s) infrared
SRAM static random access memory
SSI synchronous serial interface
TAP test access port
TLB translation lookaside buffer
UART universal asynchronous receiver
Table 1. Acronyms and Abbreviations
Definition
(cont.)
10 DS508UM1
1.2 Units of Measurement
Symbol Unit of Measure
°C
fs sample frequency
Hz hertz (cycle per second)
kbits/s kilobits per second
kbyte kilobyte (1,024 bytes)
kHz kilohertz
kΩ kilohm
Mbits/s megabits (1,048,576 bits) per second
Mbyte megabyte (1,048,576 bytes)
MHz megahertz (1,000 kilohertz)
µA microampere
µFmicrofarad
µWmicrowatt
µs microsecond (1,000 nanoseconds)
mA milliampere
degree Celsius
mW milliwatt
ms millisecond (1,000 microseconds)
ns nanosecond
Vvolt
Wwatt
Table 2. Unit of Measurement
DS508UM1 11
1.3 General Conventions
Hexadecimal numbers are presented with all letters in uppercase and a lowercase “h” appended or with a
0x at the beginning. For example, 0x14 and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text (for example, ‘11’ designates a binary number). Numbers
not indicated by an “h,” 0x, or single quotation marks are decimal.
Registers are referred to by acronym, with bits listed in brackets separ ated by a hyphen (- ) (for e xample,
CODR[0-7]).
The use of “tbd” indicates values that are “to be determined,” “n/a” designates “not available,” and “n/c”
indicates a pin that is a “no connect.”
1.4 Pin Description Conventions
Abbreviations used for signal directions are listed in Table 3.
Abbreviation Direction
I Input
OOutput
I/O Input or Output
Table 3. Pin Description Conventions
12 DS508UM1
2. EP7312 FUNCTIONAL DESCRIPTION
The EP7312 device is a single-chip embedded controller designed to be used in low-cost and ultra-lowpower applications. Operating at 74 MHz, the EP7312 delivers approximately 66 Dhrystone 2.1 MIPS of
sustained performance (74 MIPS peak). This is approximately the same as a 100 MHz Pentium-based PC.
The EP7312 contains the following functional blocks:
• ARM720T processor which consists of the following functional sub-blocks:
- ARM7TDMI CPU core (which supports the l ogic for the Thumb instruction set, core debug, enhanced multiplier,
JTAG, and the Embedded ICE) running at a dynamically programmable clock speed of 18 MHz, 36 MHz, 49 MHz, or
74 MHz.
- Memory Management Unit (MMU) compatible with the ARM710 core (providing address translation and a 64-entry
translation lookaside buffer) with added support for Windows CE.
- 8 kbytes of unified instruction and data cache with a four-way set associative cache controller.
- Write buffer
• 48 kbytes (0x9600) of on-chip SRAM that can be shared between the LCD controller and general application use.
• Memory interfaces for up to 6 independent 256 Mbyte expansion segments with programming wait
states.
• 27 bits of general purpose I/O - multiplexed to provide additional functionality where necessary.
• Digital Audio Interface (DAI) for connection to CD-quality DACs and CODECs.
• Interrupt controller
• Advanced system state control and power management.
• Two full-duplex 16550A compatible UARTs with 16-byte transmit and receive FIFOs.
• IrDA SIR protocol controller capable of speeds up to 115.2 kbits/s.
• Programmable 1-, 2-, or 4-bit-per-pixel LCD controller with 16-level grayscaler.
• Programmable frame buffer start address, allowing a system to be built using only internal SRAM for
memory.
• On-chip boot ROM programmed with serial load boot sequence.
• Two 16-bit general purpose timer counters.
• A 32-bit Real Time Clock (RTC) and comparator.
• Dedicated LED flasher pin driven from the RTC with programmable duty ratio (multiplexed with a
GPIO pin).
• Two synchronous serial interfaces for Micro-wire or SPI periphera ls such as ADCs, one supporting
both the master and slave mode and the other supporting only the master mode.
• Full JTAG boundary scan and Embedded ICE support.
• Two programmable pulse-width modulation interfaces.
• An interface to one or two Cirrus Logic CL-PS6700 PC Card controller devices to support two PC Card
slots.
• Direct SDRAM interface operates at up to 36.864 MHz with 4 internal banks totaling 256 Mbits in
size. The SDRAM interface can be configured for 16-bit or 32-bit wide accesses.
• Oscillator and phase-locked loop (PLL) to generate the core clock speeds of 18.432 MHz,
36.864 MHz, 49.152 MHz, and 73.728 MHz from an external 3.6864 MHz crystal.
• An alternative external clock input at 13 MHz.
• A low-power 32.768 kHz oscillator that generates the RTC.
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A simplified block diagram of the EP7312 is shown in Figure 1. All external memory and peripheral de-
3
vices are connected to the 32-bit data bus using the external 28-bit address bus and control signals.
2.1 CPU Core
The ARM720T consists of an ARM7TDMI 32-bit RISC processor, a unified cache, and a memory management unit (MMU). The cache is four-way set associative with 8-kbytes organized as 512 lines of
4 words. The cache is directly connected to the ARM7TDMI, and therefore caches the virtual address from
the CPU. When the cache misses, the MMU translates the virtual address into a physical address. A 64entry translation lookaside buffer (TLB) is utilized to speed the address translation process and reduce bus
traffic necessary to read the page table. The MMU saves power by only translating the cache misses.
See the ARM720T Data Sheet for a complete description of the various logic blocks that make up the pro-
cessor, as well as all internal register information. The URL (Internet address) for ARM technical manuals
is http://www .arm.com/Documentation/Manuals/.
13-MHZ INPUT
3.6864 MHZ
32.768 KHZ
NPOR, RUN,
RESET, WAKEUP
BAT OK, EXTPWR
PWRFL, BATCHG
EINT[1-3], FIQ,
MEDCHG
FLASHING LED DRIVE
PORTS A, B, D (8-BIT)
PORT E (3-BIT)
KEYBD DRIVERS (0-7)
DC TO DC
ADCCLK, ADCIN,
ADCOUT, SMPCLK,
SSICLK, SSITXFR,
SSITXDA, SSIRXDA,
ADCCS
SSIRSFR
PLL
32.768-KHZ
OSCILLATOR
STATE CONTROL
POWER
MANAGEMENT
INTERRUPT
CONTROLLER
RTC
GPIO
PWM
SSI1 (ADC)
DAI
SSI2
CODEC
ARM720T
ARM7TDMI
CPU CORE
8-KBYTE
CACHE
MMU
WRITE
BUFFER
TIMER
COUNTERS(2)
ON-CHIP
BOOT ROM
EPB BRIDGE
EPB BUS
INTERNAL DATA BUS
MEMORY CONTROLLER
CL-PS6700 INTF
EXPANSION CNTRL
SDRAM CNTRL
INTERNAL ADDRESS BUS
LCD DMA
ICE-JTAG
LCD
CONTROLLER
ON-CHIP SRAM
48 KBYTES
UART1
UART2
IrDA
D[0-31]
PB[0-1], NCS[4-5]
EXPCLK, WORD, NCS[0EXPRDY, WRITE
MOE, MWE, SDCLK,
SDQM[0:1], SDRAS,
SDCAS
A[0-27],
DRA[0-14]
TEST AND
DEVELOPMENT
LCD DRIVE
LED AND
PHOTODIODE
ASYNC
INTERFACE 1
ASYNC
INTERFACE 2
Figure 1. EP7312 Block Diagram
14 DS508UM1
2.2 State Control
The EP7312 supports the following Power Management States: Operating, Idle, and Standby (see
Figure 2). The normal program execution state is the Operating State; this is a full performance state where
all of the clocks and peripheral logic are enabled. The Idle State is the same as the Operating State except
that the CPU clock is halte d. An interrupt from an external interrupt source or from the real-ti me clock will
return it back to the Operating State. The WAKEUP signal can only be used to exit the Standby State, not
the Idle State. The Standby State has the lowest power consumption of the three states. By selecting this
mode the main oscillator shuts down, leaving only the Real Time Clock and its associated logic powered.
It is important when the EP7312 is in Standby that all power and ground pins remain connected to power
and ground in order to have a proper system wake-up. The only state that Standby can transition to is the
Operating State.
In the description below, the RUN/CLKEN pin can be used either for the RUN functionality, or the CLKEN functionality to allow an external oscillator t o be disabled in the 13 MHz mode. Either RUN or CLKEN
functionality can be selected according to the state of the CLKENSL bit in the SYSCON2 register . T able 4
on page 16 on the following page shows peripheral status in various power management states.
2.2.1 Standby State
The Standby State equates to the system being switched “off” (i.e., no display, and the main oscillator is
shut down). When the 18.432–73.72 MHz mode is selected, the PLL will be shut down. In the 13 MHz
mode, if the CLKENSL bit is set low, then the CLKEN signal will be forced low and can, if required, be
used to disable an external oscillator.
In the Standby State, all the system memory and state is maintained and the system time is kept up-to-date.
The PLL-on-chip oscillator or external oscilla tor is disabled and the system is static, exce pt for the low
power watch crystal (32 kHz) oscillator and divider chain to the RTC and LED flasher. The RUN signal is
driven low , therefore this signal can be used externally in the system to power down other system modules.
Whenever the EP7312 is in the Standby State, the external address and data buses are forced low internally
by the RUN signal. This is done to prevent peripherals that are powered down from draining current. Also,
the internal peripheral’s signals get set to their Reset State.
Interrupt or rising wakeup
Standby
nPOR, power fail,
or user reset
Write to standby location,
power fail, or user reset
r
nte
I
Idle
Figure 2. State Diagram
Operating
t
p
u
r
Write to halt location
DS508UM1 15
When first powered, or reset by the nPOR (Power On Reset, active low) signal, the EP7312 is forced into
the Standby State. This is known as a cold reset, and when leaving the Standby State after a cold reset,
external wake up is the only way to wake up the device. Whe n leaving the Standby State after non-cold
reset conditions (i.e., the software has forced the device into the Standby State), the transition to the Operating State can be caused by a rising edge on the WAKEUP input signal or by an enabled interrupt. Normally, when entering the Standby State from the Operating State, the software will leave some interrupt
sources enabled.
Note: The CPU cannot be awakened by the TINT, WEINT, and BLINT interrupts when in the Standby State.
Address (W/B) Operating Idle Standby
SDRAM Control On On SELFREF Off N/A
UARTs On On Off Reset Reset
LCD FIFO On On Reset Reset Reset
LCD On On Off Reset Reset
ADC Interface On On Off Reset Reset
SSI2 Interface On On Off Reset Reset
DAI Interface On On Off Reset Reset
CODEC On On Off Reset Reset
Timers On On Off Reset Reset
RTC On On On On On
LED Flasher On On On Reset Res et
DC-to-DC On On Off Reset Reset
CPU On Off Off Reset Reset
nPOR
RESET
nURESET
RESET
Interrupt Control On On On Reset Reset
PLL/CLKEN Signal On On Off Off Off
Table 4. Peripheral Status in Different Power States
16 DS508UM1
Typically, software writes to the Standby internal memory location to cause the transition from the Operating State to the Standby S tate. Before entering the Standby S tate, if external I/O devices (such as the CLPS6700s connected to nCS[4] or nCS[5]) are in use, the software must c heck to ensure that they are idle
before issuing the write to the Standby State location.
Before entering the Standby State, the software must properly disable the DAI. Failing to do so wil l result
in higher than expected power consumption in the Standby S tate, as well as unpredictable operation of the
DAI. The DAI can be re-enabled after transitioning back to the Operating State.
The system can also be forced into the Standby State by hardware if the nPWRF L or nURESET inputs are
forced low. The only exit from the Standby State is to the Operating State.
The system will only transition to the Operating State from the Standby State under the following conditions: when the nPWRFL input pin is high when the nEXTPWR input pin is low or when the BATOK input
pin is high. This prevents the system from starting when the power supply is inadequate (i.e., the main batteries are low), corresponding to a low level on nPWRFL or BATOK.
From the Standby State, if the WAKEUP signal is applied with no clock except the 32 kHz clock running,
the EP7312 will be initialized into a state where it is ready to start and is waiting for the CPU to start receiving its clock. The CPU will still be held in reset at this point. Aft er the first clock is applied, there will
be a delay of about eight clock cycles before the CPU is enabled. This delay is to allow the clock to the
CPU time to settle.
2.2.1.1 UART in Standby State
During the Standby State, the UARTs are disabled and cannot detect any activity (i.e., start bit) on the receiver . If this functional ity is required then this can be accomplished i n software by the following method:
1) Permanently connect the RX pin to one of the active low external interrupt pins.
2) Ensure that on entry to the Standby State, the chosen interrupt source is not masked, and the UART is
enabled.
3) Send a preamble that consists of one start bit, 8 bits of zero, and one stop bit. This will cause the
EP7312 to wake and execute the enabled interrupt vector.
The UART will automatically be re-enabled when the processor re-enters the Operating State, and the preamble will be received. Since the UART was not awake at the start of the preamble, the timing of the sample point will be off-center during the preamble byte. However, the next byte transmitted will be correctly
aligned. Thus, the actual first real byte to be received by the UART will get captured correctly.
2.2.2 Idle State
If in the Operating State, the Idle State can be entered by writing to a special internal memory location
(HALT) in the EP7312. If an interrupt occurs, the EP7312 will return immediately back to the Operating
State and execute the next instruction. The WAKEUP signal can not be used to exit the Idle State. It is only
used to exit the Standby State.
DS508UM1 17
In the Idle State, the device functions just like it does when in the Operating State. However , the CPU clock
is halted while it waits for an event such as a key press to generate an interrupt. The PLL (in
18.432–73.728 MHz mode) or the external 13 MHz clock source always remains active in the Idle State.
2.2.3 Keyboard Interrupt
For the case of the keyboard interrupt, the following options are available and are selectable according to
bits 1 and 3 of the SYSCON2 register (refer to the SYSCON2 Register Description for details).
• If the KBWEN bit (SYSCON2 bit 3) is set low, then a keypress will cause a transition from a power
saving state only if the keyboard interrupt is non-masked (i.e., the interrupt mask register 2 (INTMR2
bit 0) is high).
• When KBWEN is high, a keypress will cause the device to wake up regardless of the state of the interrupt mask register. This is called the “Keyboard Direct Wakeup” mode. In this mode, the interrupt request may not get serviced. If the interrupt is masked (i.e., the interrupt mask register 2 (INTMR2 bit
0) is low), the processor simply starts re-executing code from where it left off before it entered the power saving state. If the interrupt is non-masked, then the processor will service the interrupt.
• When the KBD6 bit (SYSCON2 bit 1) is low, all 8 of Port A inputs are OR’ed together to produce the
internal wakeup signal and keyboard interrupt request. This is the default reset state.
• When the KBD6 bit (SYSCON2 bit 1) is high, only the lowest 6 bits of Port A are OR’ed together to
produce the internal wakeup signal and keyboard interrupt request. The two most significant bits of
Port A are available as GPIO when this bit is set high.
In the case where KBWEN is low and the INTMR2 bit 0 is low, it will only be possible to wakeup the
device by using the external WAKEUP pin or another enabled interrupt source. The keyboard interrupt capability allows an OS to use either a polled or interrupt-driven keyboard routine, or a combination of both.
Note: The keyboard interrupt is NOT debounced.
2.3 Power-Up Sequence
The EP7312 has a power-up sequence that should be followed for proper start up. If any of the recommended timing sequences below are violated, then it is possible that the part may not start-up properly. This
could cause the device to get lost and not recover without a hard reset.
1) Upon power, the signal nPOR must be held active (LOW) for a minimum of 100 ms, af ter VDD has
become settled.
2) After nPOR goes HIGH, the EP7312 will enter the Standby State (and only this state). In this state, the
PLL is not enabled, and thus the CPU is not enabled either. The only method that can be used to allow
the EP7312 to exit the Standby State into the Operating State is by the WAKEUP signal going active
(HIGH).
Note: Do not assert the nURESET signal before the processor goes into Operating State. This is due to the fact
that nURESET is latched into the device by the rising edge of nPOR. When nURESET is LOW on the rising
edge of nPOR, it can force the device into one of its Test Mode states.
18 DS508UM1
1) After nPOR goes HIGH, the WAKEUP signal cannot be detected as going HI GH, until after at least
two seconds. After two seconds, the WAKEUP signal can become active, and it must be HIGH for at
least 125 ms.
2) After the WAKEUP signal is detected internally, it first goes through a deglitching circuit. This is why
is must be active for at least 125 ms. Then the PLL ge ts enabled. WAKEUP is ignored immediately
after waking up the system. It also ignores it while in the Idle or Operating State. It can constantly toggle with no affect on the device. It will only be rea d again i f nPOR goe s low and the n high again, or if
software has forced the device back into the Standby State.
3) A maximum of 250 ms will pass before the CPU becomes enabled and starts to fetch the first instruction.
2.4 Resets
There are three asynchronous resets to the EP7312: nPOR, nPWRFL, and nURESET. If any of these are
active, a system reset is generated internally. This will reset all internal registers in the EP7312 except the
RTC data and match registers. These registers are only cleared by nPOR allowing the system time to be
preserved through a user reset or power fail condition.
Any reset will also reset the CPU and cause it to start execution at the reset vector when the EP7312 returns
to the Operating State.
Internal to the EP7312, three different signals are used to reset storage elements. These are nPOR,
nSYSRES and nSTBY. nPOR is an external signal. nSTBY is equivalent to the external RUN signal.
nPOR (Power On Reset, active low) is the highe st pri ori ty rese t signal. W hen a ctive (l ow), it will rese t all
storage elements in the EP7312. nPOR active forces nSYSRES and nSTBY active. nPOR will only be active after the EP7312 is first powered up and not during any other resets. nPOR active will clea r a ll flags
in the status register except for the cold reset flag (CLDFLG) bit (SYSFLG, bit 15), which is set.
nSYSRES (System Reset, active low) is generated internally to the EP7312 if nPOR, nPWRFL, or nURESET are active. It is the second highest priority reset signal, used to asynchronously reset most internal
registers in the EP7312. nSYSRES active forces nSTBY and RUN low. nSYSRES is used to reset the
EP7312 and force it into the Standby State with no co-operation from software. The CPU is also reset.
The nSTBY and RUN signals are high when the EP7312 is in the Operating or Idle States and low when
in the Standby State. The main system clock is valid when nSTBY is hi gh. The nSTBY signal will disable
any peripheral block that is clocked from the master clock source (i.e., everything except for the RTC). In
general, a system reset will clear all registers and nSTBY will disable all peripherals that require a main
clock. The following peripherals are always disabled by a low level on nSTBY : two UARTs and IrDA SIR
encoder, timer counters, telephony CODEC, and the two SSI interfaces. In addition, when in the Standby
State, the LCD controller and PWM drive are also disabled.
When operating from an external 13 MHz oscillator which has become disabled in the Standby State by
using the CLKEN (SYSCON, bit 13) signal (i.e., with CLKENSL = 0), the oscillator must be stable within
0.125 sec from the rising edge of the CLKEN signal.
DS508UM1 19
2.5 Clocks
There are two clocking modes for the EP7312. Either an external cloc k input can be used or the on-chip
PLL. The clock source is selected by a strapping option on Port E, pin 2 (PE[2]). If PE[2] is high at the
rising edge of nPOR (i.e., upon power-up), the external clock mode is selected. If PE[2] is low, then the
on-chip PLL mode is selected. After power-up, PE[2] can be used as a GPIO.
The EP7312 device contains several separate sections of logic, each clocked according to its own clock
frequency requirements. When the EP7312 is in external clock mode, the actual frequencies at the peripherals will be different than when in PLL mode. See each peripheral device section for more details. The
section below describes the clocking for both the ARM720T and address/data bus.
2.5.1 On-Chip PLL
The ARM720T clock can be programmed to 18.432 MHz, 36.864 MHz, 49.152 MHz, or 73.728 MHz
with the PLL running at twice the highest possible CPU clock frequency ( 147.456 MHz). The PLL uses
an external 3.6864 MHz crystal. By chip default, the on-chip PLL is used and configured such that the
ARM720T and address/data buses run at 18.432 MHz.
When the clock frequency is selected to be 36 MHz , both the ARM720T and the address/data buses ar e
clocked at 36 MHz. When the clock frequency is selected higher than 36 MHz, only the ARM720T gets
clocked at this higher speed. The address/data will be fixed at 36 MHz. The cl ock frequency used is selected by programming the CLKCTL[1:0] bits in the SYSCON3 register. The clock frequency selection does
not effect the EPB (external peripheral bus). Therefore, all the peripheral clocks are fixed, regardless of
the clock speed selected for the ARM720T.
Note: After modifying the CLKCTL[1:0] bits, the next instruction should always be a “NOP.”
2.5.1.1 Characteristics of the PLL Interface
When connecting a crystal to the on-chip PLL interface pins ( i.e. MOSCIN and MOSCOUT) , the crystal
and circuit should conform to the following requirements:
• The 3.6864 MHz frequency should be created by the crystal’s fundamental tone (i.e., it should be a fundamental mode crystal).
• A start-up resistor is not necessary, since one is provided internally.
• Start-up loading capacitors may be placed on each side of the external crystal and ground. Their value
should be in the range of 10 pF. However, their values should be selected based upon the crystal specifications. The total sum of the capacitance of the traces between the EP7312’s clock pins, the capacitors, and the crystal leads should be subtracted from the crystal’s specifications when determining the
values for the loading capacitors.
• The crystal should have a maximum 100 ppm frequency drift over the chip’s operating temperature
range.
Alternatively, a digital clock source can be used to drive the MOSCIN pin of the EP7312. With this approach, the voltage levels of the clock source should match that of the VDD supply for the EP7312’s pads
20 DS508UM1
(i.e. the supply voltage level used to drive all of the non-VDD core pins on the EP7312). The output clock
pin (i.e., MOSCOUT) should be left floating.
2.5.2 External Clock Input (13 MHz)
An external 13 MHz crystal oscillator can be used to drive all of the EP7312. When selected the ARM720T
and the address/data buses both get clocked at 13 MHz. The fixed clock sources to the various peripherals
will have different frequencies than in the P LL mode. In this configuration, the PLL will not be used at all.
Note: When operating at 13 MHz, the CLKCTL[1:0] bits should not be changed from their default value of “00.”
13 MHz
CLKEN
EXPCLK
(internal)
RUN
CLKEN
Interrupt /
WAKEUP
Figure 3. CLKEN Timing Entering the Standby State
Figure 4. CLKEN Timing Exiting the Standby State
DS508UM1 21
2.5.3 Dynamic Clock Switching When in the PLL Clocking Mode
The clock frequency used for the CPU and the buses is controlled by programming the CLKCTL[1:0] bits
in the SYSCON3 register. When this occurs, the state cont roller swit ches fro m the curren t to the new clock
frequency as soon as possible without causing a glitch on the clock signals. The glitch-free clock switching
logic waits until the clock that is currently in use and the newly programmed clock source are both low,
and then switches from the previous clock to the new clock without a glitch on the clocks.
2.6 Interrupt Controller
When unexpected events arise during the execution of a program (i.e., interrupt or memory fault) an e xception is usually generated. When these exceptions occur at the same time, a fixed priority system determines the order in which they are handled. Table 5 shows the priority order of all the exceptions.
The EP7312 interrupt controller has two interrupt types: interrupt request (IRQ) and fast interrupt request
(FIQ). The interrupt controller has the ability to control interrupts from 22 different FIQ and IRQ source s.
Of these, seventeen are mapped to the IRQ input and five sources are mapped to the FIQ input. FIQs have
a higher priority than IRQs. If two interrupts are received from within the same group (IRQ or FIQ), the
order in which they are serviced must be resolved in software. The priorities are listed in Table 5. All interrupts are level sensitive; that is, they must conform to the following sequence.
Priority Exception
Highest Reset
. Data Abort
.FIQ
.IRQ
. Prefetch Abort
Lowest Undefined Instruction,
Software Interrupt
Table 5. Exception Priority Handling
1) The interrupting device (either external or internal) asserts the appropriate interrupt.
2) If the appropriate bit is set in the interrupt mask register, then either a FIQ or an IRQ will be asserted
by the interrupt controller. (A description for each bit in this register can be found in Section 6.3.1
INTSR1 — Interrupt Status Register 1.
3) If interrupts are enabled the processor will jump to the appropriate address.
4) Interrupt dispatch software reads the interrupt status register to establish the source(s) of the interrupt
and calls the appropriate interrupt service routine(s).
5) Software in the interrupt service routine will clear the interrupt source by some action specific to the
device requesting the interrupt (i.e., reading the UART RX register).
22 DS508UM1
The interrupt service routine may then re-enable interrupts, and any other pending interrupts will be serviced in a similar way. Alternately, it may return to the interrupt dispatch code, which can check for any
more pending interrupts and dispatch them accordingly. The “End of Interrupt” type interrupts are latched.
All other interrupt sources (i.e., external interrupt source) must be held active until its respective service
routine starts executing. See “End Of Interrupt Locations” for more details.
Table 6, Table 7, and Table 8 show the names and allocation of interrupts in the EP7312.
Interrupt Bit in INTMR1 and
INTSR1
FIQ 0 EXTFIQ External fast interrupt input (nEXTFIQ pin)
FIQ 1 BLINT Battery low interrupt
FIQ 2 WEINT Tick Watchdog expired interrupt
FIQ 3 MCINT Media changed interrupt
IRQ 4 CSINT CODEC sound interrupt
IRQ 5 EINT1 External interrupt input 1 (nEINT[1] pin)
IRQ 6 EINT2 External interrupt input 2 (nEINT[2] pin)
IRQ 7 EINT3 External interrupt input 3 (EINT[3] pin)
IRQ 8 TC1OI TC1 underflow interrupt
IRQ 9 TC2OI TC2 underflow interrupt
IRQ 10 RTCMI RTC compare match interrupt
IRQ 11 TINT 64 Hz tick interrupt
IRQ 12 UTXINT1 Internal UART1 transmit FIFO empty interrupt
IRQ 13 URXINT1 Internal UART1 receive FIFO full interrupt
IRQ 14 UMSINT Internal UART1 modem status changed interrupt
IRQ 15 SSEOTI Synchronous serial interface 1 end of transfer interrupt
Table 6. Interrupt Allocation for the First Interrupt Register
Name Comment
Interrupt Bit in INTMR2 and
INTSR2
IRQ 0 KBDINT Key press interrupt
IRQ 1 SS2RX Master / slave SSI 16 bytes received
IRQ 2 SS2TX Master / slave SSI 16 bytes transmitted
IRQ 12 UTXINT2 UART2 transmit FIFO empty interrupt
IRQ 13 URXINT2 UART2 receive FIFO full interrupt
Table 7. Interrupt Allocation in the Second Interrupt Register
Interrupt Bit in INTMR3 and
INTSR3
FIQ 0 DAIINT DAI interface interrupt
Table 8. Interrupt Allocation in the Third Interrupt Register
DS508UM1 23
Name Comment
Name Comment
2.6.1 Interrupt Latencies in Different States
2.6.1.1 Operating State
The ARM720T processor checks for a low level on its FIQ and IRQ inputs at the end of each instruction.
The interrupt latency is therefore directly related to the amount of time it takes to complete execution of
the current instruction when the interrupt condition is detected. First, there is a one to two clock cycle synchronization penalty . For the case where the EP7312 is operating at 13 MHz with a 16-bit external memory
system, and instruction sequence stored in one wait state FLASH memory , the worst-case interrupt latency
is 251 clock cycles. This includes a delay for cache line fills for instruction prefetches, and a data abort
occurring at the end of the LDM instruction, and the LDM being non-quad word aligned. In addition, the
worst-case interrupt latency assumes that LCD DMA cycles to support a panel size of 320 x 240 at 4 bitsper-pixel, 60 Hz refresh rate, is in progress.
This would give a worst-case interrupt latency of about 19.3 µs for the ARM720T processor operating at
13 MHz in this system. For those interrupt inputs which have de-glitching, this figure is increased by the
maximum time required to pass through the deglitcher, which is approximately 125 µs (2 cycle of the
16.384 kHz clock derived from the RTC oscillator). This would create an absolute worst-case latency of
approximately 141 µs. If the ARM720T is run at 36 MHz or greater and/or 32 bit wide external memory,
the 19.3 µs value will be reduced.
All the serial data transfer peripherals included in the EP7312 (except for the master-only SS I1) have local
buffering to ensure a reasonable interrupt latency response requirement for the OS of 1 ms or less. This
assumes that the design data rates do not exceed the data rates described in this specification. If the OS
cannot meet this requirement, there will be a risk of data over/underflow occurring.
2.6.1.2 Idle State
When leaving the Idle State as a result of an interrupt, the CPU clock is restarted after approximately two
clock cycles. However, there is still potentially up to 20 µs latency as described in the first section above,
unless the code is writte n to include at l east two single cycle in structions immediat ely after the wri te to the
IDLE register (in which case the latency drops to a few microseconds).
This is important, as the Idle State can only be left because of a pending interrupt, which has to be synchronized by the processor before it can be serviced.
2.6.1.3 Standby State
The Standby State equates to the system being switched “off” (i.e., no display, and the main oscillator is
shut down). When the 18.432–73.72 MHz mode is selected, the PLL will be shut down. In the 13 MHz
mode, if the CLKENSL bit is set low, then the CLKEN signal will be forced low and can, if required, be
used to disable an external oscillator.
In the Standby State, all the system memory and state is maintained and the system time is kept up-to-date.
The PLL/on-chip oscillator or external oscillator is disabled and the system is static, except for the lowpower watch crystal (32 kHz) oscillator and divider chain to the RTC and LED flasher. The RUN signal
is driven low, therefore this signal can be used externally in the system to power down other system modules.
24 DS508UM1
Whenever the EP7312 is in the Standby S tate, the external address and data buses are driven low . The RUN
signal is used internally to force these buses to be driven low. This is done to prevent peripherals that are
power-down from draining current.
Also, the internal peripheral’s signals get set to their Reset State.
T able 9 summarizes the five external interrupt sources and the effect they have on the processor interrupts.
Interrupt
Pin
nEXTFIQ Not deglitched;
nEINT1–2 Not deglitched Worst-case
EINT3 Not deglitched Worst-case
nMEDCHG Deglitched by
Input State Operating State
Latency
Worst-case
must be active for
20 µs to be
detected
16.384 kHz clock;
must be active for
at least 122 µs to
be detected
latency of 20 µs
latency of 20 µs
latency of
19.3 µs
Worst-case
latency of 141 µs
Idle State
Latency
Worst-case
20 µs: if only
single cycle
instructions,
less than 1 µs
Worst-case
20 µs: if only
single cycle
instructions,
less than 1 µs
Worst-case
20 µs: if only
single cycle
instructions,
less than 1 µs
Worst-case
latency 141 µs;
if any single
cycle instructions = 125 µs
Standby State Latency
Including PLL / osc. settling time,
approx. 0.25 sec, or approx. 500
µs when in Idle State if in 13 MHz
mode with CLKENSL set
Including PLL / osc. settling time,
approx. 0.25 sec, or approx. 500
µs when in Idle State if in 13 MHz
mode with CLKENSL set.
Including PLL / osc. settling time,
approx. 0.25 sec, or approx. 500
µs when in Idle State if in 13 MHz
mode with CLKENSL set.
As above (note difference if in
13 MHz mode with CLKENSL
set)
Table 9. External Interrupt Sources
DS508UM1 25
2.7 EP7312 Boot ROM
The 128 bytes of on-chip Boot ROM contain an instruction sequence that initializes the device and then
configures UART1 to receive 2048 bytes of serial data that will then be placed in the on-chip SRAM. Once
the download is complete, execution jumps to the start of the on-chip SRAM. This would allow, for exam-
ple, code to be downloaded to program system FLASH during a product’ s manufacturing process. See Appendix A: Boot Code for details of the ROM Boot Code with comments to describe the stages of execution.
Selection of the Boot ROM option is determined by the state of the nMEDCHG pin during a power on
reset. If nMEDCHG is high while nPOR is active, then the EP7312 will boot from an external memory
device connected to CS[0] (normal boot mode). If nMEDCHG is low, then the boot will be from the onchip ROM. Note that in both cases, following the de-assertion of power on reset, the EP7312 will be in the
Standby State and requires a low-to-high transition on the external WAKEUP pin in order to actually start
the boot sequence.
The effect of booting from the on-chip Boot ROM is to reverse the decoding for all chip selects internally.
T able 10 shows this decoding. The control signal for the boot option is latched by nPOR, which means that
the remapping of addresses and bus widths will continue to apply until nPOR is asserted again. After booting from the Boot ROM, the contents of the Boot ROM can be read back from address 0x0000.0000 onwards, and in normal state of operation the Boot ROM contents can be read back from address range
0x7000.0000.
Address Range Chip Select
0000.0000–0FFF.FFFF CS[7]
(Internal only)
1000.0000–1FFF.FFFF CS[6]
(Internal only)
2000.0000–2FFF.FFFF nCS[5]
3000.0000–3FFF.FFFF nCS[4]
4000.0000–4FFF.FFFF nCS[3]
5000.0000–5FFF.FFFF nCS[2]
6000.0000–6FFF.FFFF nCS[1]
7000.0000–7FFF.FFFF nCS[0]
Table 10. Chip Select Address Ranges After Boot from On-Chip Boo t ROM
26 DS508UM1
2.8 Memory and I/O Expansion Interface
Six separate linear memory or expansion segments ar e decoded by the EP7312, two of which can be reserved for two PC Card cards, each interfacing to a separate single CL-PS6700 device. Each segment is
256 Mbytes in size. Two additional segments (i.e., in addition to these six) are dedicated to the on-chip
SRAM and the on-chip ROM. The on-chip ROM space and the SRAM space are fully decoded. Beyond
this address range the SRAM space is not fully decoded (i.e., any accesses be yond 128 kbyte range get
wrapped around to within 128 kbyte range). Any of the six segments are configured to interface to a conventional SRAM-like interface, and can be individually programmed to be 8-, 16-, or 32-bits wide, to support page mode access, and to execute from 1 to 8 wait states for non-sequential accesses and 0 to 3 for
burst mode accesses. The zero wait state sequential access feature is designed to support burst mode
ROMs. For writable memory devices which use the nMWE pin, zero wait state sequential accesses are not
permitted and one wait state is the minimum which should be programmed in the sequential field of the
appropriate MEMCFG register. Bus cycles can also be extended using the EXPRDY input signal.
Page mode access is accomplished by setting SQAEN = 1, which enables accesses of the form one random
address followed by three sequential addresses, etc., while keeping nCS asserted. These sequential bursts
can be up to four words long before nCS is released to allow DMA and refreshes to take place. This can
significantly improve bus bandwidth to devices such as ROMs which support page mode. When SQAEN
= 0, all accesses to memory are by random access without nCS being de-asserted between accesses. Again
nCS is de-asserted after four consecutive accesses to allow DMAS.
Bits 5 and 6 of the SYSCON2 register independently enable the interfaces to the CL-PS6700 (PC Card slot
drivers). When either of these interfaces are enabled, the corresponding chip select (nCS[4] and/or nCS[5])
becomes dedicated to that CL-PS6700 interface. The state of SYSCON2 bit 5 determines the function of
chip select nCS[4] (i.e., CL-PS6700 interface or standard chip select functionality); bit 6 controls nCS[5]
in a similar way. There is no interaction between these bits.
For applications that require a display buffer smaller than 48 kbytes, the on-chip SRAM can be used as the
frame buffer.
The width of the boot device can be chosen by selecting values of PE[1] and PE[0] during power on reset.
The inputs in Table 11 are latched by the rising edge of nPOR to select the boot option.
PE[1] PE[0] Boot Block
(nCS[0])
0 0 32-bit
0 1 8-bit
1 0 16-bit
1 1 Undefined
Table 11. Boot Options
DS508UM1 27
2.9 SDRAM Controller
The SDRAM controller in the EP7312 provides all the signals to directly interface to up to four internal
banks of SDRAM, and the width of the memory interface is progr ammable f rom 16- to 32-bits wide. All
internal banks have to be of the same width. The four internal banks that are supported c an total together
no more than 256 Mbits in size. The signals nS DRAS nSDCAS, and nWE are provided for SDRAM. Two
chip selects are provided for supporting up to 2 rows of SDRAMs. The SDRAM devices are put into selfrefresh mode when the EP7312 SDRAM controller is put into standby The SDRAM clock is halted as well.
The controller supports read, write, refresh, prec harge, and mode register write requests to the SDRAM.
Data is transferred to and from the SDRAM as unbroken quad accesses (either quad word or for 16-bit
memory , quad halfword), which is a convenient data packet size for the ARM cache line fills. For the CPU
to read smaller than a quad access, the SDRAM controller will discard the extra data. For CPU writes
smaller than a quad access, the SDQM pins (SDRAM data byte mask selects) are used to force the
SDRAMs to ignore invalid data. For CPU access sizes larger than a quad access, multiple quad accesses
are issued to the SDRAM.
The SDRAM controller can access a total memory size of 2-64 Mbytes. Each individual SDRAM should
be NEC or compatible SDRAM memory in sizes of 16-256 Mbits, arranged as shown in Table 12 on
page 29 and Table 13 on page 30.
The chip selects for the SDRAM devices in row 1 should be connected to nSDCS[0]. For row configurations, those in row2 should be connected to nSDCS[1].
For 32-bit memory access, four SDQM data byte mask selects are provided by the EP7312 to control individual byte lanes within each row. For 16-bit memory access only, SDQM[0-1] are used. For a 32-bit
memory access configuration with each row containing two 16-bit wide SDRAMs, the high order SDRAM
should have UDQM (upper SDQM) connected to SDQM[3] and LDQM (lower SDQM) connected to
SDQM[2]. The low order SDRAM follows the same convention: UDQM is connected to SDQM[1], and
LDQM is connected to SDQM[0].
Memory address line multiplexing is done internally so that the address mapping is contiguous. Ta ble 14
on page 31 indicates how the SDRAM address pins are connected to the EP7312 address pins. Note that
small SDRAM devices will not use all of these pins. For example, A12-A11 m ay not be required. However,
the bank select pins BA[0-1], are required by all SDRAMs. Smaller devices may only have one bank, so
BA1 may not be needed.
28 DS508UM1
SDRAM Details
Arrangement of SDRAMs
(C = # Columns of SDRAM, R = # Rows of SDRAM, D = # of SDRAMs)
4 Mbytes 8 Mbytes 16 Mbytes 32 Mbytes 64 Mbytes
Den-
sity
(Mbits)
16 4 818
64 4 818
128 4
256 4
Width
(bits)
8 414
16 212
8 414428
16 212224
32 111122
8 414
16 212224
8
16 212
CRDCRDCRDCRDCR D
Table 12. SDRAM Configurations (SDRAM 32-Bit Memory Interface)
DS508UM1 29
SDRAM Details
Arrangement of SDRAMs
(C = # Columns of SDRAM, R = # Rows of SDRAM, D = # of SDRAMs)
2 Mbytes 4 Mbytes 8 Mbytes 16 Mbytes 32 Mbytes 64 Mbytes
Den-
sity
(Mbits)
16. 4. . . . . . . 4. 1. 4. . . . . . . . . .
. 8. . . . 2. 1. 2. . . . . . . . . . . . .
. 16. 1. 1. 1. . . . . . . . . . . . . . . .
64. 4. . . . . . . . . . . . . 4. 1. 4. 4. 2. 8.
. 8. . . . . . . . . . 2. 1. 2. 2. 2. 4. . . .
. 16. . . . . . . 1. 1. 1. 1. 2. 2. . . . . . .
128. 4. . . . . . . . . . . . . . . . 4. 1. 4.
. 8. . . . . . . . . . . . . 2. 1. 2. 2. 2. 4.
. 16. . . . . . . . . . 1. 1. 1. 1. 2. 2. . . .
256. 4. . . . . . . . . . . . . . . . . . .
. 8. . . . . . . . . . . . . . . . 2. 1. 2.
. 16. . . . . . . . . . . . . 1. 1. 1. 1. 2. 2.
Width
(bits)
CRDCRDCRDCRDCRDCRD
Table 13. SDRAM Configurations (SDRAM 16-Bit Memory Interface)
30 DS508UM1
SDRAM Address Pins EP7312 Pin Names
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
BA0
BA1
A27/DRA0
A26/DRA1
A25/DRA2
A24/DRA3
A23/DRA4
A22/DRA5
A21/DRA6
A20/DRA7
A19/DRA8
A18/DRA9
A17/DRA10
A16/DRA11
A15/DRA12
A14/DRA13
A13/DRA14
Table 14. SDRAM Address Pin Connections
2.10 SDRAM Initialization
The SDRAM is initialized in the power-on sequence as follows:
1) To stabilize internal circuits when power is applied, a 200 ms pause (or longer) must precede any signal
toggling.
2) After the pause, all banks must be precharged using the Precharge command (includes the precharge
all banks command).
3) Once the precharge is complete, and the minimum tRP is satisfied, the mode register can be programmed. After the mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied as well.
(Only required for NEC SDRAM)
4) Eight or more refresh cycles must be performed.
DS508UM1 31
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