Matrox IS-ATHENA MGA ATHENA Specification Revision 1 - Manual No. 1034-MS

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Matrox Graphics Incorporated

MGA ATHENA Specification

Revision 1 May

16,1994

Manual No. 1034-MS

ER GRAPHICS

Trademarks

MGA TMATLAS DynaView,

PixelTOUCH,TM

,TM

TITAN,TM ATHENA,TM STORM,TM

MGA Control Panel,

DUBIC,

Instant ModeS WITCH,

MGA Marvel,

are trademarks of Matrox Graphics Inc. Matrox® is a registered trademark of Matrox Electronic Systems Ltd. IBM,© VGA,© CGA,© 8514/A,© and MDA© are registered trademarks of International Business Machines Corporation;

Micro ChannelTMis a trademark of International Business Machines Corporation Hercules© is a registered trademark of Hercules Computer Technology Inc. Intel8 is a registered trademark, and

WindowsTM

is a trademark of Microsoft Corporation; Microsoft,© MS-DOS,© and OS/2® are registered trademarks of

386,TM 486,TM

Pentium

,TM

and 80387

Microsoft Corporation

AutoCAD© is a registered trademark of Autodesk Inc.

RAMDAC

is a trademark of Brooktree

MGA

VideoPro,TM

ConsistentColor,TM

are trademarks of Intel Corporation

QCDP,

and WinSqueeze!

MGA

UnixTMis a trademark of AT& T Bell Laboratories

X-

WindowsTM

is a trademark of the Massachusetts Institute of Technology

All other nationally and internationally recognized trademarks and tradenames are hereby acknowledged.

This document contains confidential proprietary information that may not be disclosed without written permission from

Matrox Graphics Inc.

Disclaimer: Matrox Graphics Inc. reserves the right to make changes in specifications at any time and without notice. The information provided by this document is believed to be accurate and reliable. However; no responsibility is assumed by Matrox Graphics Inc. for its use; nor for any infringements of patents or other tights of third parties resulting from its use. No license is granted under any patents or patent

nghts

of Matrox Graphics Inc.

Matrox Confidential

Chapter 1: MGA Product Overview

Contents

1.1 Introduction

1.1.1

1.1.2 Features 1

.1.3

1.1.4 1

.1.5

1.16

Software Developer Support

1.1.7 Documentation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................

MGA Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Driver Support Windows Video

Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .........

Chapter 2: ATHENA Overview

2.1 Introduction

2.1.1

2.1.2 VGA

2.1.3

2.1.4

2.1.5

2.1.6 ZIALU

Bus

Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Interface Address Processing Unit (APU) Data Processing

FIFO

l-2

l-2 l-3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(BFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Unit

(DPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

l-3 l-3 l-4

l-4 l-4

2-2

..... .......

2-2

2-4

2-2

2.2 Frame Buffer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 3: Operation Modes

VGA Mode

3.1

3.1.1 FlexFont

3.1.2

3.1.3

3.1.4

3.2 Power Graphic Mode

3.2.1 Memory Configurations

3.2.2 Pixel

3.2.3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Enhanced Display

Differences Between ATHENA Ports and IBM VGA Display Adapter Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.1.4.1

3.1.4.2

3.1.4.3

3.1.4.4

Overview of Drawing

Modes

Adapter Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Hercules

CGA Mode Port Differences.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

EGA Mode Port Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

VGA Mode Port Differences

Format..

2-4

........

3-2

.3-

3-2

3-3

3-4

3-4 3-9

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Mode Port Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

..........................................................................................................................

..................................................................................................................

..................................................................................................................................

Operations

................................................................................................

Matrox Confidential

Contents i

3.2.4

DMA and Pseudo DMA

3.2.4.1 DMA

................................................................................................................

...............................................................................................................................

3-13 3-17

3.2.4.2 Pseudo DMA Programming the CRTC for Power Graphic Mode

3.2.5

3.2.5.1

3.2.5.2 Interlace Modes

3.2.5.3 Hardware Panning

3.2.5.4 Hardware Zooming

3.2.5.5 Programming Constraints

3.2.5.6

3.2.5.7 Overscan.........................................................................................................................

3.2.6 Interrupts ........................................................................................................................................

3.3

Access Restrictions to Some Resources

3.4 Initialization and Configuration

3.4.1 Configuration Elements Booting

3.4.2 Booting

3.4.3

3.5 Mode Switching

Registers.. ......................................................................................................................

Frame Buffer Alignment ................................................................................................

VGA Mode .................................................................................................................

Power Graphic

................................................................................................................................

..................................................................................................................

.......................................................................

..............................................................................................................

..........................................................................................................

........................................................................................................

.............................................................................................

...........................................................................................

........................................................................................................

.................................................................................................................

Mode..................................................................................................

3-19

3-21

.3-21

3-21 3-21 3-21 3-22 3-23 3-24

3-24 3-25 3-26

3-26

.3-26 .3-27

3-27

Switching From VGA Mode to Power Graphic Mode

3.5.1 Switching From Power Graphic Mode to VGA Mode

3.5.2

3.6

Power up

3.6.1

3.6.2

3.6.3

3.6.4

and Reset..

Hard Reset .....................................................................................................................................

Soft Reset..

Configuring ATHENA in

3.6.3.1

Reset Field

.....................................................................................................................................

Special Considerations for PCI..

Definitions

Chapter 4: Memory Mapping

4.1

ISA and PCI Configurations

Configuration Space Mapping .......................................................................................................

4.1.1

4.2 Memory

4.2.1 ISA Interface

4.2.2

4.2.3

4.3 I/O Mapping

Space Mapping....................................................................................................................

PCI Interface.. Power Graphic

.......................................................................................................................................

..................................................................

.................................................................

.........................................................................................................................

a Board-level Design..

.................................................................................................................

..............................................................................................................

....................................................................................................................................

..................................................................................................................................

Mapping (ISA and PCI) .............................................................................

Mode

.........................................................................

...................................................................................

3-27

.3-28

3-29

3-29 .3-30 .3-32

.3-32

.4-2

..4-

.4-2

4-2 4-3

..4- 3

4-8

Contents

Matrox Confidential

Chapter 5: Register Descriptions

5.1 Register Descriptions

5.1.1

Power Graphics Mode Registers

5.1.2

VGA Mode Registers

5.2 Power Graphic Mode Register Descriptions

5.3

VGA Mode Register Descriptions

.........................................................................................................................

Chapter 6: Hardware Interface

6.1 Introduction

6.2 Host Interface

6.2.1 PCI Interface

6.2.2 ISA Interface

........................................................................................................................................ 6-2

.....................................................................................................................................

....................................................................................................................................

6.2.1.1

6.2.1.2 PCI Cycles

6.2.1.3 Bus Sizing

6.2.1.4 External Devices

6.2.2.1 Bus Sizing

6.2.2.2 External Devices

PCI Bus Operation

.......................................................................................................................

........................................................................................................................

....................................................................................................................................

........................................................................................................................

.....................................................................................................

......................................................................................................................

......................................................................................

...................................................................................................

...........................................................................................................

..............................................................................................................

5-2

5-2 5-3

5-4

5-63

6-2

6-2 6-2 6-5 6-6 6-6 6-7 6-7

6-9

6.3 VRAM Interface

6.3.1 Memory Interleave

6.3.2 Patch RAM

6.3.3 ZTAG RAM

6.3.4 MCTLWTST Register Timings

6.3.5 VRAM Interconnect

6.3.6 Coprocessor Requests

6.4 VIDEO Interface

6.4.1

Power Graphic Mode (No DUBIC Mode)

6.4.2

Power Graphic Mode (DUBIC Mode)

6.4.3 VGA Mode

6.4.4 Slaving ATHENA

...............................................................................................................................

..............................................................................................................................

Appendix A: Technical Data

A. 1

Pin List.. A. 1.1 A.l.2 Host Interface (PCI Configuration).

..............................................................................................................................................

Host Interface (ISA Configuration)

........................................................................................................................

...................................................................................................................................

..................................................................................................................................

.....................................................................................................

......................................................................................................................

....................................................................................................................

....................................................................................

..........................................................................................

....................................................................................................................................

..........................................................................................................................

................................................................................................

...............................................................................................

6-10

6-12 .6-13 .6-13

6-13

6-17

6-21

6-22

6-24 6-25 6-25

A-2 A-2

A-4

A. 1.3 A. 1.4 External Device Interface (PCI Configuration) A. 1.5 A.l.6 Drawing Engine (DUBIC Mode)

Matrox Confidential

External Device Interface (ISA Configuration)

Drawing Engine (No DUBIC Mode)

.............................................................................................

...................................................................................................

.............................................................................

............................................................................

Contents -III

A-5 A-6 A-7 A-8

A.l.7 Video Interface (No DUBIC Mode)

A.l.8 Video Interface (DUBIC Mode)

A. 1.9 Miscellaneous

A.1.9.1 Fixed A. 1.9.2 Test A. 1.9.3

...............................................................................................................................

..............................................................................................................................

................................................................................................................................

VCC/GND

.....................................................................................................................

..................................................................................................

...............................................................................................

A-9 A-10 A-10

A-10 A-10

A-11

A.2 Electrical Specification

A.2.1

Maximum Ratings A.2.2 DC Specifications A.2.3

AC Specifications

A.3

A.2.3.1 A.2.3.2 A.2.3.3 A.2.3.4 A.2.3.5

Mechanical

GCLK.. Host Interface Power Graphic Mode VRAM Interface Timing VGA Mode VRAM Interface Timing

Video Interface Timing

Specification.. ...............................................................................................................

....................................................................................................................

........................................................................................................................

.........................................................................................................................

.......................................................................................................................

..........................................................................................................................

Appendix B: Customer Support

Customer Support

Power Graphic Mode Registers

Power Graphic Mode Register Fields

Timing ...................................................................................................

...........................................................

...........................................................................

.................................................................................................

A-12

A-12 A-12

..A - 16

A-16 A-16 A-25 A-41

A-48

A-5 1

B-2

VGA Mode Registers

Index

Contents

Matrox Confidential

Chapter 1: MGA Product Overview

List of Figures

Figure I- 1: Typical Implementation Block Diagram

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 2: ATHENA Overview

Figure 2- 1: ATHENA Block Diagram

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 3: Operation Modes

Figure 3-l : fbm = 0 Figure 3-2: Figure 3-3: fbm = 2

Figure 3-4: fbm = 3 .....................................................................................................................................

Figure 3-5: fbm = 4 Figure 3-6: fbm = 5 Figure 3-7: fbm = 6 Figure 3-8: fbm = 7 Figure 3-9: fbm = 10 Figure 3-10: Pixel Slice

Figure 3-11: Pixel Data

fbm

.....................................................................................................................................

= 1

.....................................................................................................................................

...................................................................................................................................

..............................................................................................................................

...............................................................................................................................

l-2

2-3

3-4 3-4 3-5 3-5 3-5 3-5 3-6 3-6

3-7 3-8

3-9 Figure 3-l2: 32-bit Access Figure 3-13: Figure 3-14: DMA General Purpose Write Sequence Figure 3-15: DMA Gen. Purpose Transfer Buffer Structure Figure 3-16: DMA Vector Sequence Figure 3-17: DMA Vector Transfer Buffer Structure Figure 3-18: DMA BLIT Write Sequence Figure 3-19: DMA BLIT Write Transfer Buffer Structure Figure 3-20: Memory Org. (1280x Figure 3-21: Configuration Bus

ILOAD/IDUMP

..........................................................................................................................

Formats / 1, 24, 32 bpp

........................................................................................................

................................................................................................

1024x8- two

................................................................................................................

Chapter 6: Hardware Interface

Figure 6-1: PCI Interface

Figure 6-2: ISA Interface Figure 6-3: Pixel Arrangement Figure 6-4: MCTLWTST for Direct Access Cycle Figure 6-5: MCTLWTST for Data Transfer Cycle

............................................................................................................................

.................................................................................................................

...........................................................................

..............................................................................

....................................................................

...............................................................................

.......................................................................

1 M Banks)

..................................................................................

..................................................................

3-9

3-10 3-12 3-13 3-14 3-14 3-15 3-15 3-23

3-29

6-3

6-8

6-12 6-14 6-14

Figure 6-6: MCTLWTST for Page Write and Page Read Cycle..

Matrox Confidential

.............................................................

List of Figures i

Figure 6-7: MCTLWTST for Refresh Cycle

............................................................................................

6-15 Figure 6-8: Page Read-Modify-Write/Anti-aliasing Cycle Figure 6-9: MCTLWTST for Page ZI Cycles

Figure 6-10: Normal Request and Release of the Bus ..............................................................................

Figure 6-11: 1 gclk Release for Refresh ...................................................................................................

Figure 6-12: ATHENA Request for Data Transfer .................................................................................

Figure 6-13: ATHENA/Memory Connection 32 Bit No MUX Figure 6-14: ATHENA/Memory Connection to 32 Bit RAMDAC Figure 6-15: ATHENA/Memory Connection to 64 Bit RAMDAC

Figure 6-16: Horizontal Video Reset (eg. 1024x768) ..............................................................................

Figure 6-17: Vertical Video Reset (eg. 1024x768)

...........................................................................................

...................................................................................

......................................................................

................................................................

.........................................................

Appendix A: Technical Data

Figure A-1: ISA Host

Figure A-2: Host PCI Input Waveform ....................................................................................................

Figure A-3: Host PCI Output Waveform .................................................................................................

Figure A-4: ROM Host Interface Waveform

Figure A-5: External Device Interface Waveform (ISA).........................................................................

Interface Waveform ..............................................................................................

...........................................................................................

6-16

6-21

6-22

.6-22

6-23 6-23 6-24 6-26

6-27

A- 17 A-20 A-20 A-21

A-21

Figure A-6: External Device Interface Waveform (PCI) .........................................................................

Figure A-8: BRQ Back Timing Figure A-9: Data Transfer Cycle Waveform Figure A-10: Hyper Page Read Cycle Waveform Figure A-l1: Page Read Cycle waveform Figure A-12: Page Write Cycle Waveform

Figure A-13: Refresh Cycle Waveform ...................................................................................................

Figure A-14: Page Read-Modify-Write Cycle Waveform .......................................................................

Figure A-15: Page ZI Cycle Waveform ...................................................................................................

Figure A-16: Video Dynamic RAM Write Cycles Figure A-17: Video Dynamic Figure A-l8: Video Dynamic RAM Page Read Figure A-19: Video Timing Figure A-20: Power Graphic Video Timing (DUBIC Mode) Figure A-21: VGA Mode (Normal) Video Timing

Figure A-22: VGA Mode (Slave) Video Timing .....................................................................................

................................................................................................................

............................................................................................

....................................................................................

...............................................................................................

..............................................................................................

...................................................................................

RAM

Read Cycles

(No DUBIC

Mode)

...................................................................................

Cycles

...........................................................................

.....................................................................................

..................................................................

..................................................................................

A-22

A-25

A-26

A-28

A-30

A-32

A-34

A-36

A-38

A-42

A-44

A-46

A-48

A-49

A-49 Figure A-23: ATHENA Mechanical Drawing Figure A-24: ATHENA Mechanical

List of Figures

..........................................................................................

Drawing (Details)

A-51

..........................................................................

A-52

Matrox Confidential

Chapter 3: Operation Modes

List of Tables

Table 3-1: Initialization of Drawing Registers Table 3-2: DMA Access Types

Table 3-3: Power Graphic Mode Video Registers ....................................................................................

Table 3-4: Interrupt Sources .....................................................................................................................

Table 3-5:

Strapping Definition:

.................................................................................................................

ATHENA-based Design..

..........................................................................................

.....................................................................

Chapter 4: Memory Mapping

Table 4-1: ATHENA Configuration Space Mapping

Table 4-2: ATHENA ISA Interface Memory Mapping .............................................................................. 4-2

Table 4-3: Table 4-4: Table 4-5:

Table 4-6: I/O Mapping ..............................................................................................................................

ATHENA PCI Interface Memory Mapping .............................................................................. 4-3

ATHENA Power Graphic Mode Memory Mapping.. ............................................................... 4-3

ATHENA Register Mapping

.....................................................................................................

.................................................................................

Chapter 6: Hardware Interface

Table 6-1: Frame Buffer Table 6-2: Frame Buffer

Config.

(No DUBIC Mode) ............................................................................. 6-10

(DUBIC Mode)

....................................................................................

3-11 3-17 3-21 3-24 3-30

4-2

4-6 4-9

6-11

Table 6-3: ATHENA/VRAM Address Connection .................................................................................. 6-19

Table 6-4: Table 6-5: Table

Table 6-7: Power Graphic Mode Video Generation ................................................................................. 6-24

Table 6-8: VGA Signal Assignment .........................................................................................................

RAS Assignment ..................................................................................................................... 6-20

CAS and OE Assignment..

6-6:

DSF Assignment..

....................................................................................................................

......................................................................................................

Appendix A: Technical Data

Table A-1: DC Specification .....................................................................................................................

Table A-2: Table A-3: Host Interface (PCI) Signal Buffers Table A-4: Table A-5: External Table A-6: Table A-7: Table A-8: Video Interface Signal Buffers (No DUBIC) Table A-9: Video Interface Signal

Host Interface

External

Drawing Engine Signal Buffers (No DUBIC) .......................................................................

Drawing

(ISA) Signal Buffers.. .....................................................................................

....................................................................................... A-13

Device Device

Engine Signal Buffers (DUBIC)

Buffers (ISA)....................................................................................

Signal

Buffers (PCI)

Signal

Buffers (DUBIC) ...............................................................................

....................................................................................

.............................................................................

......................................................................... A-15

6-20 6-21

6-25

A-12 A-l 3

A- 14 A-l4 A- 14 A- 15

A- 15

Table A-10: Miscellaneous

Matrox Confidential

Signal

Buffers..

.............................................................................................

List of Tables

A- 16

Table A- 11: Host Interface Parameter List .............................................................................................. A-19

Table A- 12: Host PCI 5 V Timing Parameters Table A- 13:

External Device Parameter List Table A- 14: BRQ Back Timing Parameter List Table A- 15: Data Transfer Cycle Parameter List

.........................................................................................

...........................................................................................

....................................................................................... A-25

..................................................................................... A-27

Table A- 16: Hyper Page Read Cycle Parameter List ...............................................................................

Table A- 17: Page Read Cycle Parameter List Table A- 18: Page Write Cycle Parameter List Table A- 19: Refresh Cycle Parameter List Table A-20: Page Read-Modify-Write Cycle Parameter List Table A-21 : Page ZI Cycle Parameter List Table A-22: Video Dynamic RAM Write Cycles Table A-23: Video Dynamic RAM Read Cycles Table A-24: Video Dynamic RAM Page Read Cycles Table A-25: Video Interface Timing Parameter List

..........................................................................................

.........................................................................................

..............................................................................................

..................................................................

..............................................................................................

....................................................................................

.....................................................................................

............................................................................ A-47

................................................................................

A-21 A-24

A-29 A-31 A-33 A-35 A-37 A-40 A-43 A-45

A-50

List of Tables

Matrox Confidential

Chapter 1:

his chapter contains an overview of the Matrox MGA chipset features

and software products.

MGA

Product Overview

1.1 Introduction

Matrox

MGA

is a high-speed, high-resolution graphics accelerator series of products designed for the

power user. MGA is very suitable for GUI environments such as Microsoft Windows 3.1 and Windows

NT, IBM OS/2 PM,

color, real-time

MGA’s

64-bit graphics power, in combination with a 486 or Pentium-class PC is in our opinion the best

Unix X-Windows, and

3D,

and many other innovative hardware and software enhancements.

AutoCAD.

It offers ultra high resolution displays with true

graphics solution if you require true workstation-level performance at a reasonable price.

1 .1 .1

The Matrox ATHENA chip lies at the heart of

MGA

Chipset

MGA’s

powerful graphics capabilities. It offers an ISA interface for ISA bus products, and a PCI interface for PCI systems. Several possible memory configurations permit design of

8,16,

24, and 32 bits/pixel displays at resolutions up to 1600 x 1200 pixels. Figure l-1 shows a block diagram of a typical graphics display adapter which uses the MGA ATHENA chip.

The

Host Processor Interface (ISA, PCI, EISA,

Figure l-l: Typical Implementation Block Diagram

chipset

functions as a stand-alone graphics controller that features an integrated VGA to offer both

MicroChannel,

VESA-VL, or proprietary)

VGA Mode and high-resolution Power Graphic mode operation. It contains a 32-location Command FIFO and address and data processing units (APU, DPU). In addition, LINE, Trapezoid, and BITBLT drawing operations are available, supported by DMA and Pseudo DMA transfers. These enhancements make screen operations such as redrawing and scrolling appear instantaneous.

ATHENA is pin-compatible with the MGA ATLAS chip, so ATLAS-based designs can take advantage of ATHENA’s additional features without modification to the board’s design.

Chapter 1: MGA Product Overview

1-2

MGA ATHENA Specification

Matrox Confidential

1 .1 .2Features

From 1 to 6 MB of frame buffer VRAM in configurations up to 32 bits/pixel . VRAM block write operations for maximum speed

Photo-realistic true color display, and QCDP (Quality Color Dithering Process) for displays of less

than 24 bits/pixel . Ultra-high resolution of 1600 x 1200, with 256 colors . Workstation performance with speeds from 2 to 12 times faster than competitors’ boards . 64-bit frame buffer data bus width

. Available Z-buffer option (2 to 4 MB DRAM) . Hardware assisted Gouraud shading and depth-cued wireframe . Integrated VGA, for full support of all DOS applications, eliminating the need for a separate VGA

card . Integrated 3D graphics engine . Integrated PCI interface . Direct RAMDAC interface . Fast, flicker-free refresh rates up to 120 Hz . Support for ISA, VESA VL, Micro Channel, EISA, PCI, and other architectures . Installation of up to four boards in a system

1 .1 .3Driver Support

MGA Power Drivers are available for Windows 3.1 and Drivers’ package contains drivers for Windows NT,

AutoCAD

OS/2,

and

MicroStation

Rel. 11/12. The ‘MGA Supplementary

(with dual display).

We provide:

. Support for popular Windows and DOS design and presentation applications

DynaView

driver for AutoCAD Release 11 and 12 that includes real-time scroll bars, spy glass, and

bird’s eye view, etc.

Support for AutoCAD 12 for Windows, and

MicroStation

. A 3D library which supports SXCI, with planned support for OPEN GL and HOOPS

1 .1 .4Windows Support

. Control Panel for Windows controls the

PixelTouch

hardware pan and zoom, Virtual Desktop, and

‘on the fly’ resolution switching (without rebooting Windows) through the use of

hotkeys.

Font anti-aliasing in hardware . In addition to the drivers listed above, the ‘MGA Supplementary Drivers’ package also contains the

ConsistentColor

printed output, and the

compression ratios of up to 28:

Matrox Confidential

monitor calibration utility to ensure accuracy between your screen display and the

WinSqueeze!

on-the-fly JPEG file compression utility, which can achieve

MGA ATHENA Specification

Introduction 1-3

1 .I .5Video Support

n MGA

The MGA

interfaces with the Matrox Marvel video capture/video windowing board.

VideoPro NTSC/PAL

animations, and

AutoCAD

Hardware-assisted Video for Windows

encoder provides output capability for recording presentations,

walk-throughs to tape.

(VfW)

and Indeo are supported.

1 .I .6Software Developer Support

. Software libraries (SXCI) are available for developers for the DOS and Windows 3.1 platforms,

with support planned for HOOPS and Open GL. SXCI is a complete exploits

MGA’s

hardware acceleration capabilities.

2D/3D

API which fully

1 .I .7Documentation

Other documentation available for Matrox MGA products includes:

MGA

TITAN

Specification (103 l&MS)* . MGA ATLAS Specification . MGA . MGA SDK Manual

DUBZC

Specification

(10330-MF)

(10348-MS)*

(10232-MS)*

A description of the Matrox MGA TITAN chip.

A description of the Matrox MGA ATLAS chip.

A description of the Matrox MGA DUBIC chip.

A user/reference manual for the MGA software developer’s kit for DOS and Windows 3.1.

. MGA

DynaView /2D

Manual (10345MN) MGA

Supplemantary

(10352-MN)

for

AutoCAD A user/reference manual for the Matrox MGA

Drivers Manual

DynaView driver for An installation/user manual which describes our

OS/2,

Windows NT, and

well as the MGA

AutoCAD

MicroStation

WinSqueeze!

and 3D Studio.

and ConsistentColor

PC drivers, as

programs for the Windows platform.

Like the ATHENA Specification, these are restricted documents. See your Matrox Sales representative

for more details.

The PCI Bus Specification from the PCI Special Interest Group contains additional information on hardware implementation for the PCI architecture.

1-4

Chapter 1: MGA Product Overview

MGA ATHENA Specification

Matrox Confidential

Chapter 2: ATHENA Overview

his chapter introduces the Matrox

sections.

MGA ATHENA

chip and its component

2.1 Introduction

The Matrox ATHENA chip supports both VGA and Power Graphic mode displays. VGA mode supports

the VGA standard, while Power Graphic mode provides additional high-speed, ultra-high resolution displays. You can switch between the two modes while using the same monitor for both. ATHENA can be configured for PCI bus systems, or for ISA (and other) bus systems.

The ATHENA chip is a stand-alone graphics controller which is composed of several sections that work together to accomplish the many tasks required of them. The ATHENA sections are listed below, and discussed in the following sections of this chapter.

Bus Interface . VGA . Bus Interface FIFO (BFIFO) . Address Processing Unit (APU)

Data Processing Unit (DPU)

n ZIALU

2.1

Bus Interface

This section of ATHENA implements the interface with the host. Two bus interfaces are supported: an ISA interface and a PCI interface for the PCI bus.

The Bus Interface section includes:

All of the control circuitry for the ISA and PCI buses

PCI control, decoding, and re-mapping circuitry

Configuration registers

I/O buffers @-location FIFO for

Byte-alignment circuitry; 32-to-8 bit access conversion for VGA and I/O

The data path (data and addresses) from the host

writable

devices; 4-location FIFO for ILOAD operations)

2.1.2 VGA

This section implements the VGA functions, and includes:

The VGA core, which interfaces directly with the frame buffer in VGA mode

The circuitry for video refresh in Power Graphic mode (see

address generation, data transfer requests, and video control

Section

circuitry

6.3.6),

which

includes

2.1.3

Bus Interface FIFO (BFIFO)

This section implements the Command FIFO from the host to the drawing engine. All access to

the drawing registers passes through this 32-location FIFO, which holds the data as well as the address of the targeted register in the drawing engine.

Chapter 2: ATHENA Overview MGA ATHENA Specification

2-2

Matrox Confidential

LOCUI

PCI

Bus Interface

,A,

2:;. ‘.&

+.. .

,.Y / .

,,,y ,...’ ,,I :_,; ‘:F:..:,..: :.,:.:,....“:; .,;,;;y:..

i ‘.

,:: .,

“’ I._

)

..,

‘(.

5% I‘

-_,;,:..;. ; :,: .,

$.r:

n 0

Figure 2-1: ATHENA Block Diagram

Matrox Confidential

MGA ATHENA Specification

Introduction 2-3

2.1.4 Address Processing Unit (APU)

This section of ATHENA generates the sequencing of the drawing operations. Each drawing operation is broken down into a sequence of read and write commands which are sent to the DPU. The APU includes:

a Generation of the sequence for each drawing operation, and the addresses and mask 0

Processing of the slope for vectors and trapezoid edges

Rectangle clipping

2.1.5

Data Processing Unit (DPU)

This section manipulates the data according to the currently-selected operation. It also converts read and write commands from the APU into memory cycles to the frame buffer. The DPU includes:

Generation of memory cycles

Host compress, decompress, and data formatting

The funnel shifter for data alignment

The Boolean ALU

Anti-aliasing

a The patterning and dithering circuitry o

The Data FIFO for BitBLlT operations

The color expansion circuitry for character drawing

The depth

comparitor

2.1.6 ZI ALU

This section implements the ALU for linear interpolation for Z and for Gouraud shading (R,G,B).

2.2 Frame Buffer

ATHENA can interface directly with the VRAM and DRAM. Memory combinations of

256Kx8

VRAM, 256Kx16 VRAM, and 256Kx16 DRAM are supported in order to permit design of different display configurations. This allows ATHENA to support 8, 16, 24 and 32 bits/pixel formats and resolutions up to 1600x1200.

VRAM is used for the frame buffer itself. Since VRAM has two ports, the serial port of the VRAM is used for the screen refresh while the random port is devoted to drawing operations. Useful VRAM functions such as split data transfer, block mode, and write/bit are all exploited.

128Kx8

VRAM,

2-4 Chapter 2: ATHENA Overview

MGA ATHENA Specification

Matrox Confidential

Chapter 3: Operation Modes

his chapter explains the VGA and Power Graphic operation modes of the Matrox MGA ATHENA chip. The Power Graphic mode description contains explanations of the memory configuration, frame buffer formats, drawing operations, initialization, configuration, and reset.

3.1 VGA Mode

ATHENA’s VGA contains all of the functions and support logic required to implement the IBM VGA, EGA, and CGA display adapter and level.

Since ATHENA is register-compatible with VGA, EGA, CGA and MDA/Hercules adapters, all display modes for these adapters can be supported. As with most display adapters, a BIOS is required to configure ATHENA for each display mode.

As well as the standard control registers required by the various display adapters, ATHENA uses

auxiliary registers to enable enhanced modes and emulation functions.

MDA/

Hercules graphics card standards at a register-compatible

3.1 .I

In all alphanumeric modes, backgrounds to a single color and allows bits

FlexFont

is an available option. When enabled, it forces the character

D4-D6

of the attribute byte to be used for character font selection. Up to eight character fonts can be displayed simultaneously. The character fonts are programmable and are stored in Dynamic Memory Plane 2.

3.1.2 Enhanced Modes

ATHENA enhances some display modes, and provides new high-resolution 256 and 16-color VGA modes.

The ATHENA chip permits high resolution VGA display modes of 640x400,640x480, 800x600, or

1024x768 pixels with 256 simultaneous colors, both interlaced and non-interlaced. ATHENA also

permits 16 color resolutions of up to 1024x768 interlaced and non-interlaced. Bits in the ATHENA auxiliary registers are used to enable these modes. Otherwise, the programming for these modes is

similar to that for VGA modes VGA mode

13h

can be enhanced to provide up to 16 pages at 320x200 resolution with 256 colors

13h

and

12h.

(standard VGA supports only one page). The CPU can access two pages simultaneously, and the others are selected for access using page select bits in ATHENA’s auxiliary ports. The CRTC start address

3-2 Chapter 3: Operation Modes

MGA ATHENA Specification

Matrox Confidential

3.1.3 Display Adapter Support

Four modes of ATHENA VGA operation and emulation are available: VGA, EGA, CGA, and MDA/Hercules.

The VGA and EGA CRTC’s are fully implemented and are used to perform the operations of a 6845 CRTC for the CGA and MDA/Hercules modes.

The control registers of the CGA and MDA/Hercules adapters are fully supported in the ATHENA hardware. When a control register bit is changed, a trap interrupt (NMI) is generated. The interrupt handler then interprets the control register’s contents and sets up the VGA CRTC to perform the required operation. In addition, the chip can be configured to allow software emulation to override any or a

11 of

the hardware functions to permit support of special display modes.

3.1.4 Differences Between ATHENA Ports and IBM VGA Display Adapter Ports

There are differences between ATHENA’s VGA mode and the IBM display adapters that it emulat

es. Some ports are changed from write-only to read/write to simplify emulation. Other ports have been deleted because they aren’t required. The list below describes the differences.

3.1.4.1

Hercules Mode Port Differences

The 6845 CRTC is replaced by the EGA or VGA CRTC. Hardware emulation of the 6845 requires software assistance and is enabled through the trap and emulation control registers.

The mode control and configuration registers are now read/write.

3.1.4.2

CGA Mode Port Differences

The 6845 CRTC is replaced by the EGA or VGA CRTC. Hardware emulation of the 6845 requires software assistance and is enabled through the trap and emulation control registers.

The mode control and color select ports are now read/write.

3.1.4.3

EGA Mode Port Differences

The CRTC registers are now read/write. Otherwise, the CRTC is identical to the IBM EGA CRTC when the EGA CRTC mode is selected. The VGA CRTC can be selected when ATHENA is in EGA mode.

The attributes controller registers are now read/write. The address and data registers of the sequencer and graphics controller are also read/write.

Graphics position registers A and B have been deleted and replaced by read-only ports for the feature control and miscellaneous registers. Graphics position A is fixed at 0 and B is fixed at 1, according to standard EGA programing practice.

3.1.4.4

VGA Mode

Port

Differences

In VGA mode, ATHENA is register compatible with the IBM VGA. The light pen set and clear ports remain accessible. The EGA CRTC can be selected when ATHENA is in VGA mode.

Matrox Confidential

MGA ATHENA Specification

VGA Mode 3-3

3.2 Power Graphic Mode

Power Graphic mode employs hardware-coded graphical acceleration to improve the speed of GUI

(Graphical User Interface) environments.

3.2.1 Memory Configurations

Several hardware memory configurations are supported in Power Graphic mode. These configurations can further be organized by the fbm (frame buffer mode) field of the OPMODE register. The three basic configurations are:

Support of up to 2 MB of VRAM and 2 MB of DRAM using supports 8, 16, and 32 bit/pixel displays.

Support of up to 4 MB of VRAM and 2 MB of DRAM using configuration supports 8, 16, and 32 bit/pixel displays.

Support of up to 6 MB of VRAM and 4 MB of DRAM. This configuration supports 24 or 32

01xX,

bit/pixel displays. Use fbm =

depending on the amount of available memory and whether the

frame buffer is configured as 24 or 32 bits.

:+ Note: In No DUBIC mode (see page 6-

fbm = 0, 1,2, and 3 may be used. Note that fbm =

17),

only Banks 0, 1,2, and 3 are supported. Therefore, only

8,9,

and 11 to 15 are undefined.

128Kx8

VRAM. This configuration

and

256Kx8

VRAM. This

In all cases, the resolution depends on the amount of available memory. Section 6.3, ‘VRAM Interface’ contains tables that show which fbms can be used with which hardware configurations. The following figures show the memory mapping of the hardware memory configurations.

Memory Configuration Tables:

Intensity:

(1)

----------------.

OOOOOOh

OFFFFFh

----------------_

1FFFFFh

___-_-___-_-___-_

200000h

3FFFFFh

--------------_-_

Z-Depth: Memory Bank:

(1) (2)

.-.

___----__- _----- /

.-.

.-----__-___-__-

OOOOOOh

1FFFFFh

Figure 3-1:

f’bm

(3)

VRAM 1

DRAM 5

= 0

Intensity:

(1)

__-_-_-___________________________

OOOOOOh

OFFFFFh

______------______________________

IOOOOOh

1 1

1FFFFFh

_____________-___-________________

Z-Depth: Memory Bank:

(1) (2)

OOOOOOh

OFFFFFh

(3)

VRAM 0

VRAM 1

Figure 3-2: fbm = 1

3-4

Chapter 3: Operation Modes

MGA ATHENA Specification

Matrox Confidential

Intensity: Z-Depth: Memory Bank:

(1)

OOOOOOh

(1) (2)

(3)

VRAM

Intensity: Z-Depth: Memory Bank:

(1)

____-_----------

OOOOOOh

07FFFFh

----------------

OSOOOOh

(1) (2)

(3)

VRAM 3

VRAM 2

27FFFFh

----------------

200000h

__-_-____-__-_--

OOOOOOh

VRAM

3FFFFFh 1FFFFFh

400000h

5FFFFFh

-_-____-_-____-__-________________

DRAM

Figure 3-3: fbm = 2

Intensity: Z-Depth:

(1) (1) (2)

Memory Bank:

(3)

----------------

400000h

______

j_______

SFFFFFh

600000h

~!%~mF

---------------700000h

b77FFFFI

----------------

OOOOOOh

I I

DRAM

1FFFFFh

_--------_---_-!OOOOOh

b27FFFFh

_---------------

VRAM 3

(4)

Figure 3-4: fbm = 3

Intensity: Z-Depth: Memory Bank:

(1)

OOOOOOh

1FFFFFh

-___---__----

200OOOh

(1) (2)

_____ --- _____

VRAM2-4

(3)

(5)

400000h

SFFFFFh

___-___-_---____--_---------------

Figure 3-5: fbm = 4

Matrox Confidential

3FFFFFh

______---_---

4OOOOOh

57FFFFh

-___-_-_----580000h

SFFFFF

--_--___-_----

600000h

7FFFFFh

------__-___-_

MGA ATHENA Specification

__-----____---.

-_-------_---_

OOOOOOh

1FFFFFh

___-_--___-_-_

Figure 3-6:

Power Graphic Mode 3-5

VRAM 2 - 3

VRAM 4 - 3

DRAM 7

DRAM 5

f’bm

= 5

(5)

Intensity: Z-Depth: Memory Bank:

(1) (2)

(3)

.____________--

Intensity: Z-Depth:

(1)

_-_--____-_---__

OOOOOOh

1FFFFFh

-----------L---200OOOh

(1) (2)

____-___-__-__

Memory Bank:

(3)

VRAM2-4

(5)

VRAM2-3

(5)

3FFFFFh

__-__-______-___.

40OOOOh

SFFFFFh

-________-------.

600000h

7FFFFFh

--_-_____-------.

Figure 3-7: fbm = 6

OOOOOOh

FFFFFh

_____--_--___--

VRAM2-3

(5)

DRAM 5

DRAM 8

LB?FFFFh--

400OOOh

SFFFFFh

_-__--____-_-___

600000h

7FFFFFh

__-____--_____-_

800ooo

_--- Gs7EFH

880000h

9FFFFFh

___--____-__----

VRAM 4 - 3

___--------_--

OOOOOOh

DRAM 5

1FFFFFh

_____-_____--__

200000

w!?27FEFl

DRAM 8

Figure 3-8: fbm = 7

(5)

Notes: (Figures 3-l to 3-9):

All addresses are hexadecimal byte addresses. These addresses correspond to pixel addresses in

(1)

8 bits/pixel mode.

Depth addresses indicate which memory is used as depth buffer space when 3D drawing is

(2)

enabled.

‘Memory Bank’ indicates the type of memory used, as well as which bank of memory is used in

(3)

this space. Refer to Section 6.3 for details on the frame buffer modes. This part of the frame buffer can’t be used for display.

(4)

3-6 Chapter 3: Operation Modes

MGA ATHENA Specification

Matrox Confidential

Intensity: Z-Depth: Memory Bank:

(1)

----

~~~-~-~h

OFFFFFh

----------------

1OOOOOh

1FFFFFh

----------------------------------

2OOOOOh

3FFFFFh

----__--__-_________--------------.

400000h

(1) (2)

---- r----------------I,

---------------

OOOOOOh

OFFFFFh

(3)

VRAM 2

-------------------------

V.M

v..M

(4)

Notes (continued):

(5)

Depending on the number of chips/banks populated in this section, any data, or possibly only 24-bit data may be stored in this section of memory.

(6)

Depending on the number of chips/banks populated in this section, and if bank 7 is populated, any data, or possibly only 24-bit data may be stored in this section of memory.

(7)

Also visible at

680OOOh -

Figure 3-9:

6FFFFFh.

f%m

DRAM

= 10

Matrox Confidential

MGA ATHENA Specification

Power Graphic Mode 3-7

3.2.2 Pixel Format

The pixel slice is 64 bits long and is organized as shown below. In all cases, the least significant bit is 0. The Alpha part of the color refers to a section of the pixel which is not used to drive the RAMDAC. In the following illustrations, ‘A’ refers to Buffer A and ‘B’ to Buffer B when a double buffer mode is selected. ANTI refers to anti-aliased pixels, and MONO is a monochrome pixel slice.

32 bm

16 bpP

Doub Buff

16 bPP

8 h-v

Doub Buff

8 bPP

4 bPP

Doub Buff

ANTI

MONO

P2A

28 24

POA PUB POA PUB POA

PI3

PlA

PO:

60 56

52 48

44 40 36

I I

PlA PI3 PlA PM PlA PI% PlA POB

P3B

P3A

P23

P73 P7A P63 P6A P5B PSA P43 P4A P3B P3A P2B P2A PIB PlA

P15

P14 P13 P12

PI1 PI0

P9 P8 P7 P6 PS P4 P3 P2 PI PO

P63

Figure

3-10:

Pixel Slice

PUB

POA

POB POA

POA

In all cases the data is true color; however in 8 bits/pixel and 4 bits/pixel formats, pseudo color can be used when shading and anti-aliasing are not used.

The figure on the next page shows how the data is organized for each pixel (for all supported pixel depths).

3-8 Chapter 3: Operation Modes

MGA ATHENA Specification

Matrox Confidential

24 16

8 0

bxv

Doub Buff

16 bpP

--‘I

ALPHA

ALPHA RED GREEN BLUE

03 03 03 0 3 03 03 0 3

RED

0 7

16 8 0

GREEN

RED GREEN BLUE

04 04

BLUE

Figure 3-11: Pixel Data

When performing direct frame buffer access, 32-bit access depends on the format of the memory at this location. Data is organized as follows for the various pixel sizes:

bpp

Doub Buff

bpp

Doub Buff

h-v

4 bpp

Doub Buff

28 24 20

POB POA POB POA PO3 POA POB POA

PIB

P3B P3A P2B P2A PI3 PIA

16 12 8 4 0

PlA

POB

POA

POB POA

ANTI

// \

‘\

MONO P31

P7 P6 PS P4 P3 P2 PI PO

Figure 3-12: 32-bit Access

Matrox Confidential

MGA ATHENA Specification

Power Graphic Mode 3-9

In addition to the direct frame buffer access format, the following formats are supported for ILOAD and

IDUMP

operations in 1, 24, and 32-bit/pixel modes. These formats are selected by the RGB (hbgr) and

compress (hcprs) fields of the Drawing Control (DWGCTL) register:

First Word

Second Word

As direct frame buffer access

24 31 16

ALPHA

RED1

GREEN2

23 8 15 0

BLUE GREEN RED

BLUE0 GREEN0

RED2

BLUE1

REDO

GREEN1

bltmod hbgr

BFCOL 0

BMONO 0

BMONO 1

BUCOL 1

hcprs

Second Word

First Word

Second Word

Third Word

BLUE3

ALPHA

BLUE1

GREEN3 RED3

BLUE GREEN RED

REDO

GREEN0

GREEN2 BLUE2 RED1

RED3

GREEN3 BLUE3 RED2

Figure 3-13: ILOAD/IDUMP Formats /

BLUE3

BLUE0

GREEN1

1,24,32

BUCOL 0

bpp

3-10

Chapter 3: Operation Modes

MGA ATHENA Specification

Matrox Confidential

3.2.3 Overview of Drawing Operations

The following three groups of drawing operations are supported by ATHENA:

LINE: Used for vectors. These operations can be auto-initialized. In this case, the Brezenham parameters are automatically computed by ATHENA. Brezenham parameters can also be provided directly by the host processor.

TRAP: Used for rectangle fills (1 operand BITBLTs) and 3D tile drawing.

BITBLT: Used for copy and other operations (2 operand BITBLTs with or without expansion).

All of these drawing operations support several attributes in order to perform different type of actions. The attributes include: line style, patterning, block mode, raster, antialiasing, Gouraud shading, depth buffer, and others.

The following table summarizes how the drawing engine registers must be initialized for these basic operations:

REGISTERS

opcode event ar0 arl

AUTO INIT Xend

LINE END 2b err LINE INIT 2b 2b-a-Sdy

DRAW END 2b err

TRAP INIT

END

BITBLT INIT sea

END X

dY1 dY1 err1 -IdXl I

eol

ssa sea

X X

ar2

Yend

2b-2a

-IdXl I

dr0 drl

dr4 dr5 dr6 dr7 (Red)

dr8 dr9

ar3 ar4 ar5 ard dr12 dr13 dr14

Xstar Ystar start ZdM ZdD Xend Yend X X ZdM ZdD

start

eor

-IdXrl dYr

em -IdXrl dYr

syinc syinc

start

X X ZdX ZdY

dr2

ZdM ZdD

X ZdM ZdD , ’ 0

zdx ZdY

dr3 (2)

drl0 drll(Gr.)

dr15

(Blue) length SGN

lines signs

signs

a signs

signs

= Xend - Xstart

= Yend - Ystart a = max( b = min(

ZdM

= Increment along major axis

ZdD

= Increment along diagonal axis

ZdX

= Increment along X axis

ZdY

= Increment along Y axis

IdxlJdyl)

Idxl,ldyl)

eor=dXr>=O?-dXr:dXr+dYr-1

eol =

dX1 >=

0 ? -

dX1: dX1

dYl -1

Where xl = left edge; xr = right edge

sea

= source and address

ssa

= source start address = source current address

sea

Table 3-l: Initialization of Drawing Registers

Every time a drawing engine operation is started, the following steps must be taken:

Since all drawing registers are accessed through the FIFO, check that there is enough room in the FIFO.

Initialize all the drawing registers, preferably starting with the ‘K’ flag registers (see Note (2)

following Table

Start the drawing engine when you write the last register by offsetting the register by

4-5),

since some degree of parallelism can be achieved doing this.

100h.

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MGA ATHENA Specification

Power Graphic Mode

3-11

3.2.4

DMA and Pseudo DMA

ATHENA supports two operating modes in which both the address and data are sent via the data bus:

DMA Pseudo DMA

A DMA channel on the host system is used to sequence operations. The host processor must sequence all access through the DMAWIN memory

space (see Chapter 4).

In both cases, the address of the modified register is generated internally by the ATHENA chip. Additional operation modes are available for both DMA and Pseudo DMA:

DMA

DMA General Purpose Write

DMA Vector Write DMA BLIT Write DMA BLIT Write

DMA General Purpose Write

Pseudo DMA

DMA General Purpose Write

DMA Vector Write

DMA BLIT Read

The first double word (dw) transferred is loaded into the Address Generator. This dw contains the addresses of the next four drawing registers to be written, and the next four dw transfers contain the data to be written to those four registers.

When each dw of data is transferred, the Address Generator will send the appropriate 7-bit address to the

Bus FIFO. When the fourth (final) address has been used, the next double word transfer reloads the Address Generator.

A direct access to a drawing register during a Pseudo DMA General Purpose write resets the Address Generator state machine to the ‘LD ADR-GEN’ state. The following Pseudo DMA write transfer must contain the addresses of the data for the next four drawing registers. The cycle is illustrated below.

24 23 22

16 15 14

876

-0

LDADR-GEN

FIFO DATA

2 FIFO DATA

3 FIFODATA

4 FIFO DATA

add1

add3 X

add2 X

3231

add1

Figure 3-14: DMA General Purpose Write Sequence

add0

data1

Chapter 3: Operation Modes MGA ATHENA Specification

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30 24 23 22 16 15

add3 X add2 X

data0

data

data2

data3

add1

876 0

add0

add3 X

add2 X

add1

add0

data0

data1

data2

Figure 3-15: DMA Gen. Purpose Transfer Buffer Structure

DMA Vector Write

The first double word transferred is loaded into the Address Generator. This dw contains one bit of

‘address select’ for each of the next 32 vector vertices to be sent to the drawing registers. These 32 bits are called the vector tags. The next 32 double word transfers contain the XY address data to be written to the drawing registers.

When the tag bit is set to zero (0), the address generator will force the address to that of the XYStart register without setting the bit to start the drawing engine. When the tag bit is set to one

generator will force the address to that of the

XYEnd

(l),

the address

When each dw of data is transferred, the Address Generator checks the associated tag bit and sends the

appropriate 7-bit address to the Bus FIFO. When the

32nd

(final) tag has been used, the next double word

transfer reloads the Address Generator with the next 32 vector tags. A direct access to a drawing register during a Pseudo DMA VECTOR resets the Address Generator state

machine to the ‘LD ADR-GEN’ state. The following Pseudo DMA write transfer must contain the vector tags for the next XY coordinate data.

The cycle is illustrated below. When Vn = 0, addn = XY-START address

(IOh)

When Vn = 1, addn = XY-END address + START DWG ENG (5 lh)

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MGA ATHENA Specification

Power Graphic Mode 3-13

0 LD ADR-GEN

FIFODATA

n FIFO DATA

1 32FIyDATA

v3 1

”

I * I

I I I

3813231

add0

Figure 3-16: DMA Vector Sequence

33 v31

Y30

Y31

I I *

x30

x31

Chapter 3: Operation Modes

Figure

3-17:

DMA Vector Transfer Buffer Structure

MGA ATHENA Specification

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DMA BLIT Write

The DMA BLIT write is hard coded, so there’s no reason to load the Address Generator. The result is that every transfer consists of data only.

When each dw of data is transferred, the Address Generator sends the srcregblit register address to the Bus FIFO. The address generator state machine is not used for this type of DMA.

All pixels expected by the drawing engine must be transferred, otherwise it could jam. The total number of dword transfers needed to complete the BLIT operation depends on, among other factors:

. The size of the window to be drawn (upper left comer coordinate, length in X and Y) . The number of bits per pixel (8, 16, or 32)

The cycle is illustrated below. No address is required for data transfer during DMA blits, so ‘add’ is

‘don’t care’.

-+O

FIFO DATA

add

Figure 3-18: DMA BLIT Write Sequence

32 31

data

data0

data 1

data2

data3

data4

data5

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data6

data7

Figure 3-19: DMA BLIT Write Transfer Buffer Structure

MGA ATHENA Specification

Power Graphic Mode 3-15

DMA BLIT Read

As specified earlier, the DMA BLIT Read mode is available for Pseudo DMA only, and is used to dump pixels from a window of the screen to system memory. Each double word that’s transferred may contain 4, 2, or 1 pixel(s), depending on the configuration (8, 16, or 32 bits per pixel, respectively).

The coordinate of the upper left comer and the length in X and Y are a few of the parameters that are required by the graphic engine for this operation.

Important Note:

It is extremely important that the number of dwords dumped accounts for all of the pixels that are to be transferred. The last

dwordfor

each scan line of pixels may contain insignificant information in the case

of 8 or 16 bit/pixel modes if the number of transferred pixels is not evenly divisible by 4 (for 8 bpp modes) or by 2 (for 16 bpp modes).

l Z.+ If the window to be drawn is not aligned at the beginning of a slice, the insignificant pixels to the

left of the window are effectively disregarded, and the slice alignment begins at the start of the window.

The following illustration shows the case of an 8 bits/pixel mode transfer that is 42 pixels wide:

Slice 0

I Slice 1 . . .

Slice 10

P40

P41 x x

P40 P4I

x x

These insignificant pixels must

still be sent as part of the slice.

3.2.4.1

DMA

The ATHENA chip’s DMA capabilities can only be used with the AT (ISA) interface.

ATHENA supports only DMA I/O write transfers. The goal is use the host’s DMA controller to transfer a block from the system memory into ATHENA’s Bus FIFO (only the Bus FIFO is accessed during DMA

write). This provides a means to write to drawing registers for specific drawing operations.

Only

16-bit

DMA transfers are supported. The total number of transfers must be an integral number of double words, to align with ATHENA’s internal 32-bit data bus. The words are accumulated before sending double words to the Bus FIFO. The memory block to be transferred must be aligned on a double word boundary.

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MGA ATHENA Specification

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Table 3-2: DMA Access

Types

To initiate a DMA transfer, take the following steps:

Ensure that ‘dmaact’ and ‘pseudodma’ (OPMODE register bits 1 and 0) are not active (active if

Program the dmamod bits (OPMODE register bits 2 and 3) to one of three modes listed below

‘

1’).

(keep dmaact and pseudodma at ‘0’):

DMA General Purpose Write

DMA BLIT Write

DMA Vector Write

The function of the dmamod bits is explained later on.

Program the host DMA controller.

Start the DMA transfer by setting dmaact to ‘ 1’ (keep pseudodma at ‘0’).

Once dmaact is set, ATHENA will request DMA service by asserting DRQ. The requests will continue until the terminal count is reached. If the Bus FIFO becomes full during the DMA transfer, the request will stop automatically and resume when there is space available in the Bus FIFO.

When the DMA transfer is in progress, any access to the following devices is forbidden:

n The drawing registers (offset

. VRAMWIN (offset OOOOh . DMAWIN (offset OOOOh - 1

1COOh - 1DFFh)

lBFFh,

BFFh,

vgaen = ‘0’ and pseudodma = ‘0’ - see Chapter 4)

vgaen = ‘0’ and pseudodma = ‘ 1’) Access to other MGA resources is still possible, however. Dmaact will be automatically reset after the last transfer, when the DMA terminal count (TC) is sampled

active. DRQ is normally n-i-state. When dmaact is active, DRQ is driven to the appropriate state. This allows for

resource sharing in a system with multiple

MGAs.

Only one MGA can have dmaact active at any time.

When dmaact becomes inactive due to TC, ATHENA will have been driving DRQ low, then it will

tri-state the signal. It’s possible to generate an interrupt when a DMA terminal count occurs. For more information, refer to

Section 3.2.6.

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MGA ATHENA Specification

Power Graphic Mode 3-17

3.2.4.2

Pseudo DMA

The goal of Pseudo DMA is the same as that of DMA, with the only difference being that read transfers are possible. Instead of using the DMA controller, Pseudo DMA transfers are ‘move string’ instructions in the DMAWIN memory space (offset

OOOOh -

lBFFh, vgaen = ‘0’ and pseudodma = ‘1’).

Only double word accesses (read or write) are allowed in the DMAWIN memory space. When performing Pseudo DMA transfers, all of the MGA map is available, except the VRAMWIN memory space, which is disabled.

Write

lkansfers

To transfer a block of data from the system memory to the Bus FIFO of the ATHENA chip, the steps

listed below must be followed:

Make sure that ‘dmaact’ and ‘pseudodma’ are not active.

Program the dmamod bits to one of the three modes listed below (keep dmaact and pseudodma at ‘0’):

DMA General Purpose Write

DMA BLIT Write

DMA Vector Write

a) If DMA BLIT Write is used, program all affected drawing registers. Note that all writes to the drawing registers must be double word accesses.

b) If DMA BLIT Write is used, send the ILOAD opcode to the drawing engine.

Set ‘pseudodma’ to ‘ 1’ (keep dmaact at ‘0’).

Transfer system memory data to the MGA DMAWIN memory space, with ‘move string’ or ‘read and write’ instructions.

Reset ‘pseudodma’ to ‘0’ at the end of the block transfer.

As long as the Bus FIFO isn’t full, and if the

nowait

bit of the OPMODE register is set to

‘I’,

then no wait will be generated for write cycles to the DMAWIN memory space. When the Bus FIFO is full, there is one more dword location, which is the Byte Accumulator of the host section. Once the Byte

Accumulator and the Bus FIFO are full, the next write to the DMAWIN space will be put in waiting as long as the Byte Accumulator data isn’t loaded in the Bus FIFO.

If the CHRDY ready signal is kept inactive for more than 64 gclks, the STATUS register bferrsts bit will be set. This will cause an interrupt if the proper interrupt enable is set. If CHRDY is still inactive after

128 gclks, the host section will abort the write cycle by reasserting CHRDY and by resetting the Byte

Accumulator full flag. For DMA BLIT Write operations, the drawing engine will fetch data until all pixels have been loaded,

once the

ILOAD

opcode is sent, and if the Bus FIFO isn’t empty.

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Chapter 3: Operation Modes

MGA ATHENA Specification

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Read

Pansfers

To dump screen data to the system memory, take these steps:

Make sure that ‘dmaact’ and ‘pseudodma’ are not active.

Program the dmamod bits to DMA BLIT Read (keep dmaact and pseudodma at ‘0’).

Program all affected drawing registers. Note that all writes to the drawing registers must be double word accesses.

Set ‘pseudodma’ to ‘ 1’ (keep dmaact at ‘0’).

Send the

Transfer data from the DMAWIN memory space to the system memory, with ‘move string’ or ‘read

IDUMP

opcode to the drawing engine.

and write’ instructions.

Reset ‘pseudodma’ to ‘0’ at the end of the dump.

Once the IDUMP opcode is sent to the drawing engine, it begins fetching pixels from the

VRAMs.

During a read in the DMAWIN memory space, CHRDY will be deactivated (ISA bus system), or a retry will be generated

(PC1

system) if the data from the drawing engine isn’t ready. When the data is available, it will be latched in the host section of ATHENA, and the access is completed. A new request will be sent to the drawing engine for the next dword when the last byte, the last word, or the current dword is being read, depending on whether ATHENA is 8, 16, or 32-bit. The latched dword will be

present until all bytes are read.

If the access takes more than 64 gclks, the bferrsts bit will be set in the STATUS register. This may cause an interrupt if the proper interrupt enable is set. If an access takes more than 128 gclks, the host section will abort the read cycle by reasserting CHRDY.

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MGA ATHENA Specification

Power Graphic Mode 3-19

3.2.5

Programming the CRTC for Power Graphic Mode

This section explains the video parameters required for the Power Graphic display modes.

3.2.5.1 Registers

In Power Graphic mode (for all resolutions and pixel depths), the video parameters that are programmed in the registers are always based on a video clock that is divided by 8.

+Note:

When you change any video parameters, it is important to halt the video operation circuitry of

the VRAM chips to prevent the

VRAMs

from entering an unrecoverable state. The ‘Screen Off’ bit in the Clocking Mode sequencer register (Address lFC5, Index 01, Bit 5) will force the screen to blank and halt the VRAM circuitry mentioned above. This bit must be maintained to ‘off’ for at

least 10

j.t.s

after the last video parameter modification.

The CRTC-CTRL register is used as specified. Table 3-3 shows the registers that are implicated in programming the video for the Power Graphic modes.

3.2.5.2

Interlace Modes

In Power Graphic mode, the hardware can only be properly programmed in interlace modes at specific

memory pitches (768, 1024, and 1280). For other pitches, the hardware must be programmed in such a

way that the display area is less than the memory pitch. It is not possible to have a horizontal resolution greater than 1280 pixels in interlace mode.

3.2.5.3

Hardware Panning

Panning is achieved by programming a start address that is equivalent to the desired region. The start address is programmed in two VGA CRTC registers and one auxiliary register. Panning must be done on a multiple of 16 pixels.

3.2.5.4 Hardware Zooming

Zooming by lx, 2x, and 4x is supported. Zooming in the X direction is performed by the clock generator. For the CRTC, this is seen simply as a

division of the video clock. However, the CRTC registers that control the horizontal signals must be reprogrammed properly (relative to the divided clock) to deliver the same frequency to the monitor.

It’s important to note that if you wish to maintain a constant image between each zoom switch, the horizontal parameters must be exact multiples. For this reason, multiples of 32 must be used for each

parameter (front porch, sync, etc.), even if you zoom by lx. To zoom in the Y direction, you must reprogram the Maximum Scan Line register in the CRTC. This will

affect the way that the CRTC address counter generates line addresses. The dt request module must also operate in non-automatic line wrap mode (refer to Bit 2 of the

CRTC-CTRL Power Graphic mode register description on page 5-61) when not zooming by lx.

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MGA ATHENA Specification

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3.2.5.5

Programming Constraints

In order to have a correct image on the screen, you must respect different constraints when calculating the video parameters. The videodelay field of the CRTC-CTRL register can be programmed for

3,4,5,

11, 24, or 28 vidclks. The video parameters must be calculated so that at least one of the six possible

values of videodelay meets the three constraints. Unexpected video results could occur otherwise.

Section

CRTC

AUX

SEO

Index Name

00 Horizontal Total

Horizontal Display Enable End

Horizontal Blanking Start

Horizontal Blanking End

03 04

Horizontal Retrace Start Horizontal Retrace End

05 06 Vertical Total

Overflow

Preset Row Scan

08 09

Maximum Scan Line OA Cursor Start OB Cursor End OC

Start Address High OD

Start Address Low OE

Cursor Position High

Cursor Position Low

Vertical Retrace Start

Vertical Retrace End

Vertical Display Enable End

Offset

13 14

Underline Location

Vertical Blanking Start

Vertical Blanking End

Mode Control

Line Compare

Mode Control Register

00 02

Emulation Control Register OA

CRTC Extended Address Register OD

Interlace Support Register

Vertical Sync Adjust Register

Clocking Mode

Miscellaneous Output Register

07 06

D5 04 03 02 DI DO

S S S 0 S S S S 0 0

0 0 S

S X X

x x x

0 x x x x x x x

s x x 1 x x s s x s x x x x x x

s s s s s s

S 0

0 S

S 0

0 S

S S

X X

S S

S S S S S S S

X X

S X X

S X

1 1 1

S S

S 0

S S

S X

X S

S S

0 0 0

S S S S S S S S 0

Z X X

S X X

S X

x x s x x x x

s x 0 s s x

S S S

0 Z X X

S X X

S X

s x

Legend:

1 X S Z

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The bit must always be programmed to 0 The bit must always be programmed to 1 The bit can be programmed to either 0 or 1 The bit works as specified

The bit is used by the zoom in the Y direction

Table 3-3: Power Graphic Mode Video Registers

MGA ATHENA Specification

Power Graphic Mode 3-21

The following formula explains how to calculate the three constraints. The drawing engine response

(in video clocks) is:

dw-eng-res

Constraint #l : Videodelay Constraint Constraint

3.2.5.6

#2:

Videodelay

#3:

Videodelay

Frame Buffer Alignment

int(925ns*videofrequency+0.9)

>= Horizontal

dw-eng-res+

Horizontal blank+

FrontPorch+2-3

l-l

5/s

I-dw-eng-res-3

When ‘No DUBIC’ mode is selected, the frame buffer display must be arranged in such a way that bank switching appends during the blank (between two lines).

For example:

Assume that we want to display

1280x1024~8

using two

1MB

banks. The bank transition occurs

after 1M pixels:

1048576

pixels

pixels/line

1280 =

819.2

lines

Round this up to 8 19 lines, and up-front padding will have to be added in order to ensure that the bank transition takes place between two lines:

1048576

pixels

pixels/line

( 1280 *

819) =

lines

256

pixels

This means that the frame buffer will have to be started at address 256 (rather than at address 0). This produces the following results:

. The CRTC start address must be 256, rather than 0.

The drawing operation must be moved by 256 pixels. This can be done automatically by the drawing engine for the destination address by initializing YDSTORG to 256. Note that this will affect the value loaded in CYBOT and CYTOP. For source addresses this adjustment will have to be done manually.

Off-screen memory is reduced by 256 bytes.

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MGA ATHENA Specification

Matrox Confidential

With

DUBIC

Frame Buffer

Offscreen

OOOOOOh

Unused

OOOlOOh

Frame Buffer

140OOOh

140100h

Offscreen

Figure 3-20: Memory Org.

3.2.5.7

Overscan

The hardware can support the

overscan

feature, but using it will reduce the length of the blank period.

200OOOh

(1280x1024~8 -

two 1M Banks)

This reduced blank will have a direct impact on your ability to meet the constraints of the video delay. It

might be possible to lose the zoom feature at low resolutions, or even the integrity of the display itself if the

overscan

3.2.6

Interrupts

ATHENA supports interrupts for both ISA and

In the ISA configuration, ATHENA can generate two types of interrrupts: edge interrupts, and level

interrupts. The choice of interrupts is system-dependent, and is programmed by the

is large.

PC1

configurations.

CONFIG

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MGA ATHENA Specification

Power Graphic Mode 3-23

InterruDt

Picking Interrupt

Vertical Sync Interrupt

Description

This interrupt is generated when a cycle is aborted. It is useful during software

This interrupt is generated when a terminal count occurred at the end of a DMA transfer.

This interrupt is generated when a pixel is written by the drawing engine.

This interrupt is generated at every vertical sync.

Note:

The vertical sync interrupt behaves differently than the others, because two other bits must be set for it to be enabled. Bit 7 of the AUX-DATA register, and Bit 5 of the Vertical Retrace End register

(lFB5/1FD5, Index 11) must be set before the

vertical sync interrupt can be enabled.

Note:

This interrupt must be cleared by accessing Bit 4 of the Vertical Retrace End register Index 11).

Table 3-4: Interrupt Sources

debming

(lFBYlFD5,

and testing.

. In the

PC1

configuration, ATHENA uses only one interrupt line (INTA), and is a single function device. In order to integrate the DUBIC interrupts, the other external interrupts, and the current TITAN interrupt, a new register has been added.

In the

PC1

configuration, the interrupts must be programmed as level interrupts (levelirq) in the

CONFIG

Three registers are used for interrupt control:

STATUS

IEN ICLEAR

This register indicates the status of each of the interrupt sources. This register is used to individually enable each of the four interrupt sources.

This register is used to individually reset each of the four interrupt sources. Note that

there is no bit in this register to clear the vertical sync interrupt, which is cleared by accessing Bit 4 of the Vertical Retrace End register

(lFBWFD5,

Index 11).

3.3 Access Restrictions to Some Resources

Consideration must be given to several resource access restrictions (which vary depending on how the ATHENA chip is used in a system). Refer to the information on bus sizing in Sections 6.2.1.3 and 6.2.2.1.

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3.4 Initialization and Configuration

3.4.1 Configuration Elements

Note: In the lists which follow, H indicates that a field is hard-reset. All others are soft-reset. When MGA is powered up, ATHENA’s

DSTx

registers are loaded with the following configuration elements:

pcbrev<3:0> product<3:0>

rambank<8:0> vgabank0

ramspeed< 1 hyperpgc

:O>

expdev tram

As well, ATHENA’s host interface section receives these configuration elements:

configc

H driverdy

:O>

H vgaen

H above 1 meg

H biosen (indirectly, H mapsel<2:0>

according to vgaen)

Poseidon

H isa

The following configuration elements are not programmed at power up:

ATHENA drawing engine: mctlwtst (RO) ATHENA host interface:

ien<3:0>

H levelirq H mousemap expdev* H nowait fbm<2:0>

* Value available in DSTO

3.4.2

Booting in VGA Mode

H mouseen

rfhcnt<3:0>

hyperpgcl tram*

crtcbppcl

alw

:O>*

:O>

interlace4

videodelay :O>

H hrsten H vrsten

:O>

vbank0

H vesafeat

The following configuration elements from the ATHENA host interface affect the VGA, and are not programmed at power up. All the other elements are VGA-standard, and are taken care of by the BIOS.

H levelirq H vesafeat H hrsten

H vrsten

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MGA ATHENA Specification lnitializa tion and Configuration

3-25

3.4.3

Booting in Power Graphic Mode

The following operations take place during the Power Graphic mode boot procedure:

In a

PC1

system, the

The card is detected

Configuration straps/switches are read

Depending on the configuration information and the selected hardware mode, the following

PC1

configuration space is initialized by the system boot prodecure.

non-initialized configuration elements must be programmed at power up with respect to:

ATHENA host interface

ATHENA drawing engine

Video interface (DUBIC if present)

RAMDAC

Q CLOCK GEN

VGA-CRTC

3.5 Mode Switching

3.5.1

Switching From VGA Mode to Power Graphic Mode

If the system has no DUBIC, disregard any step that mentions the DUBIC chip.

Make a call to the BIOS to select VGA Mode 3.

Disable VGA Mode.

Once the VGA has been disabled, reset the vgaen bits in ATHENA’s

Disable interrupts from DUBIC.

Note: If you’ll be returning to Power Graphic mode later, make a note of the current value of

CONFIG

DUBIC’s DUB-SEL register.

Set DUBIC’s DUB-SEL register to 40h.

Stop the enhanced mode sequencer.

Set the softreset bit in ATHENA’s RESET register, then wait 1.5

Set DUBIC to Power Graphic mode.

Reset the blankdel and vga-en bits in DUBIC’s DUB-CTL register.

Restart the Power Graphic sequencer.

psec.

Reset the softreset bit in ATHENA’s RESET register, then wait 1.5

Restore the value of the DUB-SEL register of the DUBIC.

Restart Initialization of Power Graphic mode.

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MGA ATHENA Specification

psec.

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3.52

Switching From Power Graphic Mode to VGA Mode

If the system has no DUBIC, disregard any step that mentions the DUBIC chip.

Disable the interrupts from DUBIC.

Note : If you’ll be returning to Power Graphic mode later, make a note of the current value of DUBIC’s DUB-SEL register.

Set DUBIC’s DUB-SEL register to 40h.

Stop the Power Graphic sequencer.

Set the softreset bit in ATHENA’s RESET register, then wait 1.5

Place DUBIC in VGA mode.

Set the srate bit in DUBIC’s DUB-CTL register. If the bus mouse is enabled, set SRATE = 18. If

psec.

the laser printer port is enabled, set SRATE = 2

Set the blankdel and

Restart the Power Graphic mode sequencer.

Reset the softreset bit in ATHENA’s RESET register, then wait 1.5

vga-en

bits of DUBIC’s DUB-CTL register.

psec.

Place the RAMDAC in VGA mode. Program the appropriate registers as shown below:

For the

BT485

RAMDAC: Command register 0 = 0000 0000 b Command register 1 = 0000 0000 b Command register 2 = 0000 0000 b Command register 3 = 0000 0000 b For the BT482 RAMDAC: Command register A = 0000 0000 b Command register B = 0001 1110 b Command register C = 0000 0000 b

Program the Lookup Table (LUT) for VGA

Activate VGA Mode

Set the vgaen and biosen bits of ATHENA’s

Restore the value of DUBIC’s DUB-SEL register.

CONFIG

Make a call to the BIOS to select a VGA mode (for example: Mode 3 for text).

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MGA ATHENA Specification

Mode Switching 3-27

3.6 Power up and Reset

It’s possible to reset ATHENA with a hard or soft reset. Both methods are explained in the following

subsections.

3.6.1 Hard Reset

A hard reset results when a low pulse is applied to the reset pin of the ATHENA chip. The minimum

pulse width required is 8

On a hard reset, the following resources are reset:

. VGA section

Drawing engine

’

Bus FIFO

. Host section

All registers As well, external configurations are loaded into registers, as appropriate. Three rules must be followed for proper chip reset:

l.ts.

In the

PC1

configuration, no host access must occur within the first two

LDCLK, GCLK, and PCLK must be active during reset.

You must ensure that a PLL or clock oscillator oscillates within

specificiations

PCLKs

of a hard reset.

when the power-up

reset ends.

3.6.2 Soft Reset

A soft reset results when bit 0 of the RESET register is set to ‘ 1 ‘, then reset to ‘0’. On a soft reset,

external strapping is not loaded. The soft reset also initializes the Bus FIFO and all of the drawing engine. The values of the drawing

registers are lost. On the host section, some register bits are hard reset only. See Chapter 5 for more details. On the control

section of the host, only three state machines are affected by the soft reset:

IDUMP state machine

. DMA state machine

ADRGEN state machine

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MGA ATHENA Specification

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3.6.3 Configuring ATHENA in a Board-level Design

The ATHENA requires that configuration information be placed on the VDc63:0> bus during reset. The configuration information defines the available resources as well as the mode in which ATHENA will operate. More specifically, the following types of information are contained in the configuration bits:

Hardware resources (memory banks, memory speed, etc.)

Product ID and revision

Host Interface information (Address mapping,

Information used internally to control the operation of the ATHENA

8/16-bit,

etc.)

There are two types of configuration bits:

Soft configuration bits are read and used by software

Hard configuration bits are loaded directly into internal registers

Upon reset, the contents of

:+ Note that the destination registers must be read before any direct access to the frame buffer, or

VD<3

1 :0> are sent to

DST0<3

:O>;

VDc63:32> is sent to DST 1 c3 1

:O>.

drawing engine operation is performed, in order to obtain valid data. Configuration bus VDc63:0> A summary of the configuration bus follows, along with a table which defines each of the configuration

bits.

'i3

HHHHHlllHSSSSliillOlllllllHsssssssssss

56555

48,;'

40,139

32,131

H s

24,23

s s s s s 0 0 0 0 1 0 0 1 I 1 H I I 0 0

16,;s

I I

8,7

Figure 3-21: Configuration Bus

Legend:

0,l

Hard bits which must be set to the indicated value upon reset.

Hard bits which are loaded directly into internal registers upon reset.

Soft bits which software must read from the bus, invert, and then load into the appropriate internal register.

Hard bits which are automatically inverted and then loaded into an internal register upon reset.

R Reserved bits:

Soft bits which software must read from the bus. These bits are not stored internally.

Soft bits which software must read from the bus and then load into the appropriate internal register.

Hard bits (H, I) which are loaded into other registers should be read from those destination registers, not from

DSTO/DST *

Since the bit is inverted, a pull-up will initialize it to 0, and a pull-down will initialize it to 1.

Matrox Confidential

MGA ATHENA Specification

Power up and Reset

3-29

VD Bus

Bit

4:o 5

15:6 18:16

23:20

32:25

34:33

35 36 37

47139

48 49 50 nodubic<O>

52:5

53 54

63:55

57 above 1 meg

61:59 mapsel

63:62

Definition

Internal

vgaen0

Internal Hard PCB Revision

block8/

Product ID

vgabank0 Hard rambank ramspeed rambank HiResI

vgaen 1

testwren

Internal

200MHz nodubic<l>

hyperpg

expdev Soft tram Soft Internal (Host):

isa

pci

driverdy

config Hard

HaraYSoft

Configuration

Hard Hard

Soft Soft Soft

Soft (s) Read from board Soft Soft Soft Hard Hard Hard Soft Soft (i) Hard Soft

Hard (H) Host (CONFIG<28>) Hard Hard Hard Hard (H) Host (CONFIG<26:24>)

(H)

Where Used

(H)

Internally (See Figure 3-21 for values) Host (CONFIG<10:9>), VGA

(H)

Internally (See Figure 3-21 for values) Read from board Host

(0 w

6) (s)

(H)

(1) @-I)

(1) (S) (9 (S)

(1) (1) (1)

(H)

(OPMODE<27>)

Read from board Host (OPMODE<l

Read from board Read from board Read from board Host

(CONFIG< 0:9>)

Host

(TEST<9>)

Internally (See Figure 3-21 for values) Host (CONFIG<2>) Host

(CONFIG<S>)

Host (CONFIG<4>) Host

(OPMODE<25:24>)

Host (CONFIG<16>) Host

(OPMODE<26>)

Host (CONFIG<27>)

Host (CONFIG<12>)

Host (CONFIGc8>)

Host (CONFIG<l

l>)

:O>)

Table 3-5: Strapping Definition: ATHENA-based Design

Note: To ensure compatibility with future software, bits enabled high (‘ I’) during reset.

3-30

Chapter 3: Operation Modes

MGA ATHENA Specification

VD<49:48>

and

VD<39>

should be

Ma trox Confidential

3.6.3.1

Special Considerations

for PCI

Since the coarse decoding is done by the

PC1

interface module, the host-module decoding section of

ATHENA is not used. This means that ATHENA will always be configured the same way:

3.6.4 Reset Field Definitions

The reset fields listed in the Table 3-5 are explained in detail below:

Internal

These bits are read from

VD<4:0>

on reset. These lines must present the value 19h during

reset.

vgaen<l:O>

Internal

DST<S>,CONFIGclO> VGA enable. Refer to the CONFIG register description in

Chapter 5 for more details. VGAENO and VGAENl are used to enable/disable the VGA. Only one bit is used at a

time (the other one is tied to GND). The following table shows how the internal bits are initialized at reset:

. When VGAENO is used, the

When VGAENl is used, the

should be used with the may cause problems with the fixed decoding of the

VGAENI

0 0 0

This field is read from

VD<37,5>.

46E8 46E8

PC1

interface, since

VGAENO

feature is enabled when the VGA is turned on.

feature is not enabled with the VGA. VGAENl

PC1

incorporates auto-configuration which

46E8

feature.

en46E8 CONFIG<10,9>

0 0

1 1

This field is read from VDc15:6> on reset. These lines must present the value 027h during reset.

Ma trox Confidential MGA ATHENA Specification

Power up and Reset

3-31

PCB

Revision

DSTO<l8: 16>

Indicates the revision of the PCB. Refer to the

description in Chapter 5 for more details.

DSTl-0

block81 <19>

Product ID

These bits are read from

OPMODE<27>.

Indicates VRAM support for

VD<19: 16>

on reset.

&bit

block mode transfers.

Refer to the OPMODE register description in Chapter 5 for more details.

DST0<23:20> Indicates the Product ID/Platform. Refer to the

DSTl-0

description in Chapter 5 for more details.

Product ID

llxx 101x

100x 0110 0111 0101

Product

Reserved (do not use)

To be defined (future platforms)

Platform

ISA Bus

VL Bus

MCA Bus

PC1

Bus

vgabank0

These bits are read from

OPMODEcl l>

VGA Bank 0. Refer to the OPMODE register description in Chapter 5

for more details. This bit is read from

VD<24>

VD<23:20>

on reset.

on reset, and stored here.

3-32 Chapter 3: Operation Modes

MGA

ATHENA Specification

Matrox Confidential

rambank <8:0>

DST1<0>, DST0<3 1:25>

Refer to the

DSTl-0

DST1<3>

indicates the presence (when ‘1’) of Banks l-8.

ramspeed <l:O>

Value

XXXXXXXXl

XXXXXXXlX

xxxxxxlxx

xxxxxlxxx

xxxxlxxxx

XXXlXXXXX

xxlxxxxxx xlxxxxxxx

hxxxXXxx

These bits are read from

DST

1~2: l>

description in Chapter 5 for more details. These bits are read from

Bank Description

8xl28Kx8

6or8x256Kx8VRAM

6~256Kx8VRAM

4 x 256K x

Reserved

2 x128K x 8 DRAM - Patch DRAM

4x64Kor256Kx

VD<32:25>, VD<35>

VRAM VRAM

16 DRAM - Reserved

16DRAM

on reset.

Indicates the speed of the on-board memory. Refer to the DST 1-O register

VD<34:33>

Note: All memory must be the same speed.

on reset.

HiRes/

testwren

Reserved

Internal

200MHz

DSTl<4>

1600 x 1200. Refer to the DST

This bit is read from

DST 1 c6>

Indicates that the board is capable of displaying at a resolution of

1-O

Value

Meaning

Board

supports

Board does not support 1600 x 1200

VD<36>

1600 x 1200

on reset

Must be pulled up. See the TEST register description on page 5-50 for more

details. This bit is read from VDc38> on reset.

These bits, which are read from VDc39> on reset, should be pulled high during reset.

These lines are read from

VD<47:40>

on reset. They must present the data

DFh

during

reset.

This bit indicates the presence of a 200 MHz RAMDAC. Refer to the CONFIG register description in Chapter 5 for more details.

Matrox Confidential

MGA ATHENA Specification

Power up and Reset

3-33

nodubic

<l:O>

CONFIG<5:4>. These bits indicate the configuration of the VRAM serial port. Refer to

the

CONFIG

hYPerPg

expdev

tram

isa

OPMODE<25:24> Support for Hyper Page mode. Refer to the OPMODE register

description in Chapter 5 for more details. These bits are read from

DST

1~20: 19>

CONFIG<

and load them here.

16>

Expansion device. Refer to the CONFIG register description in Chapter 5

VD<52:5 l>

during reset. Software must read these bits from

for more details. Read from

VD<53>

during reset. Software must read this bit from

DST1<21>

and load it

here.

OPMODE<26> Type of VRAM. Refer to the OPMODE register description in Chapter

5 for more details. Read from VDc54> during reset. Software must read this bit from

DST1<22>

and load it

here.

CONFIG<28> ISA bus identification. Refer to the

CONFIG

Chapter 5 for more details.

pci

abovelmeg

driverdy

mapsel

<2:0>

Sampled from VDc55> on reset, this bit assumes the external strapping configuration value.

CONFIGc27> In conjunction with the

Refer to the sampled from

CONFIG< 2>

CONFIG

VD<56>

on reset is inverted and stored in this bit.

Mapped above 1 MB. Refer to the CONFIG register description in

Chapter 5 for more details. The value sampled from

isa

bit, determines the type of host interface.

VD<57>

on reset is inverted and

stored in this bit.

CONFIG<8> Drive channel ready. Refer to the

5 for more details. The value sampled from

CONFIG

VD<58>

on reset is inverted and stored here.

CONFIG<26:24> Select base address of MGA board in system. Refer to the CONFIG

VD<61:59>

on reset and loaded here.

config

CONFIG< :O>

Configuration bits. Refer to the CONFIG register description in Chapter

5 for more details. This value is sampled from

3-34 Chapter 3: Operation Modes

VD<63:62>

MGA ATHENA Specification

on reset and loaded here.

Matrox Confidential

Chapter 4: Memory Mapping

his chapter summarizes the memory map for the ATHENA in both the ISA and PC/ configurations, and provides an overview of the mapping for the VGA i/O and mouse port registers.

I/O

space

4.1

ISA and PCI Configurations

The ATHENA chip supports two bus configurations:

PC1

(Peripheral Component Interconnect) and ISA

(Industry Standard Architecture, often called ‘AT-bus’). The major differences between these

configurations are that the ATHENA memory mapping is different for PCI, and the

PC1

configuration includes space that is reserved for system configuration (the ISA configuration has no ‘configuration space’).

4.1

The configuration space is supported only for

Configuration Space Mapping

PC1

devices. When modes other than

PC1

are selected, this

space (and its registers) are invisible and unused. The entire configuration space is decoded by ATHENA.

Ofiet

(1)

00 DEVID

04 08

30 c3 40 OPTION

Name Access ResetValue

DEVCTRL CLASS

HEADER

TERMBASE

ROMBASE INTCTRL

Table 4-1: ATHENA Configuration Space Mapping

R R

0000 1101 0001 0000 0100 0000 0000 0011 SO00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000

0001 0000 0010

0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1111 0000 0000 0000

1011b

OOOOb OOOOb OOOOb OOOOb OOOOb llllb OOOOb

4.2 Memory Space Mapping

4.2.1 ISA Interface

All extensions to Power Graphic mode are mapped in the memory space, as well as in the VGA frame buffer and in the VGA BIOS.

Address

OAOOOOh-OBFFFFh

OCOOOOh-OC7FFFh

OACOOOh-OAFFFFh

OC8000h-OCBFFFh OCCOOOh-OCFFFFh ODOOOOh-OD3FFFh

OD40OOh-OD7FFFh OD8000h-ODBFFFh ODCOOOh-ODFFFFh

Table 4-2: ATHENA ISA Interface Memory Mapping

Device Decoded Condition (1)

VGA frame buffer

VGA BIOS ROM

MGA Power

Graphic

,t ,, ,,

,, ,,

If vgaen is active. If biosen is active.

Mode

If disabled

If MAPSEL2 is selected. If MAPSEL3 is selected. If If If If

MAPSELl

MAPSEL4 MAPSELS

MAPSEL6 MAPSEL7

is selected

VMAPSEL = 1 (2)

is selected. is selected.

and

the VGA is

(1) Refer to the CONFIG register description in Chapter 5 for information on the control bits used to select the map options.

(2) VMAPSEL is located at I/O address

Refer to Table 4-4 for the Power Graphic Mode memory mapping for both the ISA and

4-2 Chapter 4: Memory Mapping

MGA ATHENA Specification

3CF,

Index 6, Bit 3.

either

PC1

interfaces.

Matrox Confidential

4.2.2 PCI Interface

The memory mapping for

Address Offset Range

OOOAOOOOh-OOOBFFFFh

nnnnOOOOh-nnnn7FFFh

nnnn8OOOh-nnnnFFFFh

mmmmOO00h-mmmm3FFFh

mmmm4000h-mrnmm7FFFh

mmmm8000h-mmmmBFFFh

mmmmCOO0h-mmmmHTFh

Table 4-3: ATHENA

(1) The exact location in the memory space depends on the ROMBASE register. Because ATHENA is decoded as a VGA device, the ROM should be mapped at system BIOS as specified in the PCI Bus Specification.

(2) The exact location in the memory space depends on the

PC1

mode is shown below:

Device Decoded

VGA Frame Buffer

VGA BIOS ROM (1)

MGA Power Graphic Mode (2)

Condition

If vgaen and memspace are active

If biosen and memspace are active

If memspace is active

PC1

Interface Memory Mapping

TERMBASE

OOOCOOOOh

by the

4.2.3

Power Graphic Mode Mapping (ISA and PCI)

Address Offset Range

OOOOh- 1 OOOOh- 1 OOOOh- 1

COOh-

2000h-3BFFh

3COOh-3C7Fh 3C80h-3CFFh 3DOOh-3D7Fh 3D80h-3DFFh 3D80h-3DFFh

3EOOh-3FFFh

(1)

Refer to Section 3.2.4.2, ‘Pseudo DMA’, for more information.

(2)

Refer to the following tables for definitions and specific addresses of the ATHENA internal

registers.

BFFh BFFh BFFh

1 FFFh

Condition

VgaEn/ & VgaEnl & VgaEn/ &

VgaEn/ &

ExpDevl

ExpDev ExpDev

PseudoDma/ PseudoDma PseudoDma

PseudoDmal

Mnemonic

VRAMWIN

DMAWIN IDUMP

INTREG Reserved

RAMDAC DUBIC

VIWIC

CLKGEN CLKGEN EXPDEV

Device Decoded

7K VRAM window 7K Pseudo-DMA window (1) 7K Pseudo-DMA window (1) ATHENA internal registers (2) 7K VRAM window (redundant)

Reserved RAMDAC (3) DUBIC (3)

VlWIC

(3)

EXPSU EXPSL/ (3)

EXPSU (3)

(3)

Table 4-4: ATHENA Power Graphic Mode Memory Mapping

(3)

In the external device range, all devices are double-word aligned and only accessible on

byte 0. Only byte 0 accesses are allowed. Word and double-word accesses will cause unpredictable results.

Matrox Confidential

MGA ATHENA Specification

Memory Space Mapping

4-3

Oflet

(1)

lCO0

lCO4 lCO8 lCl0 lC18

1ClC

lC20 lC24 lC30 lC40 lC44 lC50 108

lC5C

lC60 10% lC68

lC6C

lC70

1 c74

lC78

lC8C

lC90 lC94 lC98

lC9C lCA0

1 CA4

lCA8

1 CAC

lCB0

lCC0

lCC4

lCC8 1ccc lCD0 lCD4 lCD8

1 CDC

1 CEO

1 CE4

lCE8 1

CEC

1 CFO

1 CF4 1 CF8 1 CFC

IDOO-1DFC

Name

DWGCTL MACCESS MCTLWTST DSTl-0

ZMSK

PLNWT BCOL

FCOL

SRCO-3 XYSTRT

XYEN-D

SHIFT

SGN LEN

AR0

AR1 AR2 AR3 AR4 AR5 AR6 PITCH

YDST YDSTORG

YTOP YBOT

CXLEFI

CXRIGHT FXLEFT FXRIGHT XDST

DRO

DRl

DR2

DR3

DR4

DR5

DR6

DR7

DR8

DR9

DRlO

DRll

DR12

DR13

DR14

DR15

Same register mapping as OOO-OFC range (3)

Category (2)

F F F D F F F F

(continued on the next page)

Access

W W W

R W W W W W W W W W W W W W W W W W W W W W W W W W W W

W W W W W W W W W W W W

W W

ResetValue

0000 OOOOh 0000 OOOOh

FFFF FFFFh

Loaded from vd<63:0>

XXXXXXXXh XxXx XXXXh XxXx

XXXX XXXXh

XXxXXxXXh

XXXXXXXXh

XXxXXXXXh XxXx XXXXh

XXXXXXXXh

XxXx XXXXXXXXh XxXx XXxxh XxXx XXXxh XxXx XXXXh XxxxXXXXh XxXx XXXXh XxXx XXXXXxXXh

XXXXXXXXh XxXx XXXXh XxXx XxXx XXxxh

xxxx xxxx XXxxh

xxxx XxXx

XXXX XXXXh XXXX XXXXh XXXX XXXXh XXXX XXXXh XXXX XXXXh XXXX XXXXh XXXX XXXXh XXXX XXXXh XXXX XXXXh XXXX XXXXh XXXX XXXXh XXXX XXXXh XXXX XXXXh XXXX XXXXh XXXX XXXXh XXXX XXXXh

XXxxh

XXXXh

XXXxh

(7)

XxXxh

XXXXh

XXxxh XXxxh

4-4

Chapter 4: Memory Mapping

MGA ATHENA Specification

Matrox Confidential

Offset (1)

lEO0 lE08

1 EOC

lEl0 lE14

lE18

1ElC

lE28 INTSTS (10) lE40 RST lE44 TEST lE48

REV

lE50 lE54 OPMODE

lE5C

lFB0 lFB1 lFB2 lFB3 lFB4 lFB5 lFB6 lFB7 lFB8 HER-MODE lFB9

1FBA

1FBB

1 FBF

lFC0 lFC1 lFC2

1 FC3

1 FC4 lFC5 1 FC7

1FCA

1 FCC

1FCE

1FCF lFD0 lFD1 (9)

lFD2 lFD3 lFD4 lFD5

lFD6

Name

VRAMPAGE BYTACCDATA

ADRGEN

FIFOSTATUS

STATUS

ICLEAR IEN

CONFIG

CRTC ,CTRL

(8)

(9)

(8)

(9) CRTC-ADDR (5)

CRTC-DATA (5)

(8)

(9)

HER-LP-SET MISCJSTATl(5)

FEAT-Cl-L HER-LP-CLR

HER-CONF AT-I-R-ADDR (4) Am-DATA

MISC-ISTATO

MISC-OUT MISC-ISTATO

MISC-OUT

SEQ-ADDR SEQ-DATA

DAC-STATUS V FEAT-Cl-L V R

MISC-OUT

GCTL-ADDR GCTL-DATA

(8)

(9) CRTC-ADDR (5) CRTC-DATA (5) V

(8)

CaWory (2)

V V 4

V V

V 4 V

V V

V 4 V V R V R V V V

V V

V R V

V V

(continued on the next

Access

R R

page)

Reset Value

xxxx

21xx

0000 0000

xxxxh

XXXXh xxxxh

0220h

OOOxh

OOOOh

0000 OOOOh

(7)

A268 1702h

(7) (7)

0000

Hercules CGA EGA

4 d II

-\I

4 4 4

OOOOh

4 4 4 d II 4 4 4

4 4 d 4 4 4 4 4 4

4 4’

4 4 4 4 4 4 4 d 4 4 4 4 4

4 4

4 4 4 4 4 4

VGA

4 4

II 4 4 d

Ma&ox Confidential

MGA ATHENA Specification

Memory Space Mapping

4-5

Notes:

OfSset

lFD7 lFD8

lFD9

1FDA

1 FDB

1FDC 1FDE

1FDF

(1)

Name

(9) CGA-MODE

CGA-COL-SL MISCJSTATl

FEAT-CTL

CGA-LP-CLR CGA-LP-SET AUX-ADDR AUX-DATA

Access

(5)

Hercules

Table 4-5: ATHENA Register Mapping

CGA

EGA VGA

Any location within the

1COOh - 1FFFh

offset range that is not identified in Table 4-5 should be

considered as reserved. (1)

The address offsets provided are relative to the MGA Power Graphic mode base memory address, as

shown in Table 4-2. (2)

The Category refers to the special characteristics of each register. The following categories are defined:

(3)

When a register is accessed in this range, this indicates to the drawing engine to start a drawing cycle.

(4)

A read from port write to this register after a

This register is a drawing engine dynamic register. This means that the contents of the register may be modified by a drawing cycle. You must wait until the drawing engine is idle before you can read dynamic registers.

The data for this register is passed through the Command FIFO. The Command FIFO contents are sent to the drawing engine only when it is ready to use them. This is the method used to synchronize the software with the drawing engine (no access to drawing engine registers should be attempted when the FIFO is full). This means that it is guaranteed that a register will be written only when the FIFO is empty. A register should only be read when the FIFO is empty, in order to be sure that the contents of that register are stable.

These registers can be initialized when the memory sequencer is not idle. It is then preferable to initialize them first (when required) in order to achieve higher performance.

These BYTE registers are in the VGA module. They are accessed in the same way as the

VGA I/O port, except that they are memory mapped.

lFBA/lFDAh

resets this port to the Attributes Address register. The first read or

lFBA/lFDAh

reset accesses the attributes index, and the next read or

write accesses the palette. Subsequent reads or writes to this register toggle between index and palette.

(5)

DO=0

of the MISC-OUT register sets the CRTC registers to

DO=1

of the MISC-OUT register sets the CRTC registers to

(Notes continue on the next page)

4-6 Chapter 4: Memory Mapping

1FBXh

1FDXh

MGA ATHENA Specification

and the input status 1 to

1FBA.

and the input status 1 to 1

Matrox Confidential

FDAh.

(6)

See the VGA SUBSYS register description for more information.

(7)

Reset

Values. The following table lists register reset values that were too wide for the previous table:

Byte

O$Kset

(1)

lC90 lE44

lE50 lE54 OPMODE

Name

YDST TEST

CONFIG

~~~~~X~OXXXXXXXXXXX~XXXX~XXXXXXX~

0000 OOOH

0000

HHHH

0000

0000 0000 0000 0000

0000

Legend

X = Undefined

H = Sampled on hard reset (8) Alternate addresses of lFB4h/lFD4h. (9) Alternate addresses of lFBS/lFDSh.

Reset Value

0000 OOHO 0000 0000 b

OOOH

0000

OHHH

HO00

0000 0000

OOHH 0000

b b

(10) This register only exists in the

PC1

configuration.

Ma trox Confidential

MGA ATHENA Specification

Memory Space Mapping 4-7

4.3

l/O

Mapping

Two different devices are mapped in the I/O space: the VGA I/O registers, and the mouse port. The I/O

mapping remains the same for the ISA and

Port Name

238h

Mouse data register (6) R

23Ah Mouse control register (6)

23Bh

Mouse configuration register (no write effect) (6) W

23Ch

Mouse data register (6) R

23Eh Mouse control register (6)

23Fh

Mouse configuration register (no write effect) (6) W

3BOh

(3)

3Blh

(4)

3B2h

(3)

3B3h

(4)

3B4h

CRTC-ADDR

3B5h CRTC-DATA

3B6h

(3)

3B7h

(4)

3B8h

HER-MODE

3B9h

HER-LP-SET

3BAh

MISC-ISTATl

FEAT-CTL

3BBh

HER-LP-CLR

3BFh

HER-CONF

3COh

ATTR_ADDR (1)

3C 1 h

Am-DATA

3C2h

MISCJSTATO MISC-OUT

3C3h

MISCJSTATO R

MISC-OUT

3C4h

SEQ-ADDR

3C5h SEQ-DATA 3C6h

Pixel Mask Register (7)

3C7h

Pixel Read Address Register (7) W

DAC-STATUS

1C8h K9h

3CAh FEAT-CTL

3CDh

Palette Write Address Register (7)

16/8-bit

Color Palette Data (7)

3CB h

Reserved W 4

3CCh MISC-OUT

Reserved

3CEh

GCTL-

3CFh

GCTL-

ADDR

DATA

(2)

PC1

configurations.

(continued on the next page)

Decoded as:

Access Hercules CGA EGA VGA

4 4 4 4

d 4

R 4

W 4 4

II 4

R R 4 4

4 4 4

II 4

4 4

4 4 4 4

4 4 4 4 4 4 4

4 4

4 4 4

4 II

1, 4 4 4

4 4

Chapter 4: Memory Mapping

4-8

MGA ATHENA Specification Matrox Confidential

Decoded as:

Port Name

3DOh (3) 3Dlh

3D2h 3D3h 3D4h 3D5h

3D6h 3D7h 3D8h

3D9h CGA-COL-SL

3DAh

3DBh

3DCh 3DDh Reserved

3DEh

3DFh

S6E8h

(4) (3) (4)

CRTC-ADDR CRTC-DATA

(3) (4)

CGA-MODE

MISCJSTATl FEATJI’L

CGA-LP-CLR CGA-LP-SET

AUX-ADDR AUX-DATA

3B0

EXPSL/

3DF

Video Subsystem Access/Setup

102h

Video Subsystem Enable (5)

(8)

(2)

Enable

(5)

Access Hercules CGA EGA VGA

4 4 4 d 4 4 4 4 4 4 4 4 4 4 4

4 d

R 4 4

4 4 4

4 4 4 4 4

4 4 4

W 4 4 4 W 4

d d

4 4

4 d 4 4

-\I

(1)

A read from Port

to this register after a

3BA/3DAh

Table 4-6:

resets this port to the attributes address register. The first read/write

reset accesses the attributes index, and the next read/write

I/O

Mapping

accesses the palette. Subsequent reads or writes to this register toggle between index and palette.

(2) DO=0

(3) (4) (5)

of the miscellaneous output register sets: CRTC registers to 3BXh; input status 1 to 3BA.

DO=1

of the miscellaneous output register sets: CRTC registers to 3DXh; input status 1 to 3DA. Alternate addresses of Alternate addresses of In the

PC1

configuration, these locations are only decoded for write operations. Snooping is

3B4/3D4h. 3B5/3D5h.

always enabled. In the ISA configuration, these locations are decoded only when the ‘VGAENO’ bit is sampled active on reset, otherwise, they are not decoded.

(6)

For more details refer to the OPMODE register description for bits 8 and 9 contained in Chapter 5. Refer to the MGA

(7)

In the

PC1

configuration, snooping is enabled on these locations if ‘vgasnoop’ is active.

DUBZC

Specification for more information about these registers.

Otherwise, normal access is performed.

(8)

In the

PC1

configuration, external expansion space is never enabled during an I/O cycle.

+..a

Note that the

3BO-3BB,

3BF-3C5, and 3CA-3DF ranges are always decoded when VGA is enabled, even when there is no register located at a specific address. The 3BC-3BE range is never decoded.

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MGA ATHENA Specification

I/O Mapping 4-9

Chapter 5: Register Descriptions

his chapter contains a description of each of the Power Graphic and

VGA mode registers of the ATHENA chip, listed in address order for each

mode. Note that Tables 4-5 and 4-6 list all of the registers in address order. In

addition, lists of all registers (and the Power Graphic mode register fields) are presented in alphabetical order at the back of this manual.

5.1 Register Descriptions

5.1 .lPower Graphics Mode Registers SAMPLE PG

Memory Address

31 30 29 28 27 26 25 24 23 22 21 20 19 18 1716 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

field1

<22:0>

field2

<23>

field3

<26: 24>

Reserved

<31:27>

Power Graphic Mode register descriptions contain a (double-underlined) header which indicates the register’s mnemonic abbreviation and its full name. Below the header, the memory address example), attributes, and reset value for the register are provided. Next, an illustration of the register

identifies the locations of all the bits, which are then described in detail below the illustration.

Reserved field3

FIELD1 . Detailed description of the

22 to 0.

FIELD2. Detailed description of the

FIELD3. Detailed description of the cfield3> field, which comprises bits 26 to 24.

Reserved: Writing has no effect.

Attributes

Sample Power Graphic Mode Register Description

W-F

Reset Value

<value>

field1

cfieldl>

field, which comprises bits

field, which is bit 23.

(lCO0

for

Memory Address

The addresses of all the Power Graphic mode registers are provided in Chapter 4.

Attributes

The Power Graphic mode attributes are:

R: Read Only W: Write Only R/W: Read and Write D: Dynamic. The contents of the register may be modified by a drawing cycle. Before such registers

can be read, the drawing engine must be idle.

F: FIFO. Data for this type of register is passed through the Command FIFO. The contents of the

Command FIFO are used by the drawing engine only when the drawing engine is ready to access them. This is the method used to synchronize the software with the drawing engine (no access to the

drawing engine registers should be attempted when the FIFO is full). This also means that a

register is guaranteed to be written only when the FIFO is empty. The drawing engine registers should only be read when the FIFO is empty to make sure that the contents of the register are stable.

K: These registers can be initialized when the memory sequencer isn’t idle, so it’s preferable to initialize them first (when required) to achieve higher performance.

5-2 Chapter 5: Register Descriptions

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Reset Value

The reset values for the Power Graphic mode registers can be expressed as hexadecimal or binary values. Most bits are reset on both soft and hard reset. Some bits are reset on hard reset only (those bits are underlined when they appear in the register description header next to

000X OOOOh

(h = Hexadecimal)

Reset Value).

0000 0000

OX00

OOHO 0000 0000 0000

OOOOb

(b = Binary)

Legend:

X= Undefined H = Sampled on hard reset

5.1.2 VGA Mode Registers Sample VGA Mode Register Description

Memory Address <addr>

Reserved 0”

I/O

Address

D3-D2 6

<addo

0”

SAMPLE VGA

Index <index>

II w------I I

7 6 5 4 3 2 I 0

DO Dl

D3-D2

A detailed description of the function of data bit 0.

A detailed description of the function of data bit 1. A detailed description of the function of the data field which contains bits 2 and 3, etc.

ATHENA VGA Mode register descriptions contain a (single-underlined) header which indicates the register’s name and type (such as CRT Controller or Sequencer, etc.). Below the header, the memory address (1 COO for example), I/O address, and the offset index for the register are indicated. Next, an

illustration of the register identifies the locations of all the bits, which are then described in detail below

the illustration.

Memory Address

This address is an offset from the Power Graphic mode base memory address. The memory addresses can be read, write, color, or monochrome, as indicated. Note that some of the VGA mode registers have no memory address and some have no index.

I/O Address

These addresses are I/O ports. The I/O addresses can be read, write, color, or monochrome, as indicated.

Index

This is the indexed address of the specific register.

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MGA ATHENA Specification

5.2 Power Graphic Mode Register Descriptions

DEVID

Configuration Space Address 00

Reset

Vah?

device

<31: 16>

vendor

CEO>

DEVICE identifiers. The data is the

string: “ATHENA”.

The Matrox VENDOR identifier for PCI:

Attributes R

0000

1101

0001

000000010000

device

30 29 28 27 26 25 24 23 222120

0010

1Ollb

19 18 17 16 15 14 13 121110 9

5-bit

ASCII code for the first three characters of the

Ox102B.

vendor

7 6 5 4

Device ID

5-4

Chapter 5: Register Descriptions

MGA ATHENA Specification

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Device Control

Configuration Space Address 04

Attributes

DEVCTRL

R/w

Reset

Reserved

<31: 2%

devseltim R

<26:25>

Reserved

<24:8>

waitcycle R

<7>

Reserved

<6>

Value0000

0100000000000000000010000000b

Reserved

III1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

III Ill

Reserved: This field is always read as 0.

DEVice SELect TIMing.

Specifies the timing of devsel. It is read as 01.

Reserved: This field is always read as 0.

WAIT CYCLE: Specifies that ATHENA will perform continuous address/data stepping. This bit is always read as 1.

Reserved: This field is always read as 0.

vgasnoop

<5>

Reserved

<4:2>

memspace

R/w

cl>

iospace

R/wco>

VGA

SNOOPing.

Controls how ATHENA will handle access to the

PC1

system palette

. 0: Respond to a palette access.

1: Enable special snooping behavior.

Reserved: This field is always read as 0.

Device response to

MEMory

SPACE access. This bit controls all memory spaces

(EPROM, VGA frame buffer, and Power Graphic mode memory space).

0: Disable the device response

1: Enable the device response

Device response to I/O SPACE access. This bit controls all I/O space (VGA I/O, and

Mouse port).

0: Disable the device response

1: Enable the device response

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MGA ATHENA Specification

Power Graphic Mode Register Descriptions

5-5

CLASS

Configuration Space Address 08

Class Code

Attributes R

Reset Value

class<31:9>

revision

<8:0>

0000 0011

SO00

0000 0000 0000 0000 OOOOb

class

revision

30 29 28 27 26 25 24 23 222120

Device CLASS. Identifies the generic function of the device and a specific register-level programming interface according to the field according to the value of the

vgaen

Value

038OOOh

030OOOh

REVISION. Contains the current board revision. This value is always read as 0.

19 18 17 16 15 1413121110 9

PC1

specification. Two values can be read in this

CONFIG

Meaning

Other display controller Super VGA-compatible controller

8 7

HEADER

Configuration Space Address OC Attributes R

Reset Value

0000 0000 0000 0000 0000 0000 0000 OOOOb

Reserved header

Reserved

<31:24>

header

~23: 16>

Reserved

CEO>

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved: This field is always read as

HEADER layout. Specifies the layout of bytes space. Also specifies that the current device is a single function device. This field is always read as

Reserved: This field is always read as

OOh.

OOOOh.

Reserved

1514

13 121110 9 8 7 6 5 4 3 2

10h

through 3Fh in the configuration

Header

5-6 Chapter 5: Register Descriptions

MGA ATHENA Specification

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Terminator Base Address

Configuration Space Address 10 Attributes

TERMBASE

R/w

Reset Value

0000 0000 0000 0000 0000 0000 0000 OOOOb

termbase Reserved

30 29

28 27 26 252423 222120

termbase <31: 14>

TERMinator

(Power Graphic) BASE Address. Specifies the base address of the Power Graphic mode memory space. Mapping in this itself. Refer to Chapter 4 for more information.

Reserved

Reserved: This field is always read as 0.

<13:0>

ROM Base Address ROMBASE

Configuration

Space Address

Attributes

19 18

17 16 15 141312

16KB

space is decoded by ATHENA

9 8

6 5 4 3 210

Reset

Value

0000 0000 0000 0000 0000

0000 0000

OOOOb

rombase Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 1716 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rombase

<31:15>

Reserved

<14:1>

romen<O>

/’

EPROM BASE address. Specifies the base address of the EPROM. This field’s attribute changes, depending on the value of the

Reserved: This field is always read as

ROM

the

CONFIG

ENable.

Enable the ROM. This field’s attribute changes, depending on the value of

biosen ROMEN Attribute

RO. Read as 0

Rnv

CONFIG

OOOOh.

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MGA ATHENA Specification

Power Graphic Mode Register Descriptions

5-7

INTCTRL

Configuration Space Address 3C

Reset Value000000000000000000000001 1111 llllb

Attributes

Interrupt Control

Reserved

<31:16>

intpin R

<15:8>

intline

<7:0>

FUW

Reserved

intpin intline

1-7

30 29 28 27

26 25 24

Reserved: This field is always read as

Selected

INTerrupt PINS.

interrupt pin.

INTerrupt

LINE routing. This R/W field is used to communicate interrupt line routing information. It is initialized at power-up to identify for the device drivers which device interrrupt pin has been connected to which system interrupt controller pin. The value is defined as ‘unknown’ or ‘no connection’ to the interrupt controller.

23 222120

191817

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OOOOh.

This field is always read as lh, since INTA is used as the

FFh

5-8 Chapter 5: Register Descriptions

MGA ATHENA Specification

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ODtion

Configuration Space Address

Attributes

OPTION

R/w

Reset Value

Reserved

<31:2>

speed<l:O>

0000

OOOOb

Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Reserved: This field is always read as

SPEED. This field is used to select the sequence access on the TAD bus, depending on the current

PC1

bus speed. This field only affects the

in the 16K window.

speed

00 01 01

pciclk

MHz

33 33 25 25

Reserved

OOOOh.

OOOO-1FAF

cmd: time !cmd: time cycle: time

(#clk):Cns)

3.5

105

3.0:

3.0 :120

2.5

100

C#clk):Cns) C#clk):Cns)

2.5

2.0

:60

2.0: 80

1.5

: 60

and

180

5:150 5:200 41160

lFEO-3FFF

ranges

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MGA ATHENA Specification

Power Graphic Mode Register Descriptions

5-9

DWGCTL

Drawing control register

Memory Address

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

opcod

<3:0>

Operation and also affects the operation of the VRAM interface section.

lCO0

CODe:

Function

Line

Trapeziod Bitblit

Attributes

W-F

Reset

Value

0000 0000 h

%+j

Reserved

g % atype

opcod

The opcod field defines the operation selected by the drawing engine,

opcod

Subfinction

AUTO WRITE LAST AUTO, WRITE LAST

VRAM -> VRAM HOST -> VRAM VRAM -> HOST

Value

0000 0001 0010 0011 0100 TRAP

1000 1001 1010

Mnemonic

LINE-OPEN AUTOLINE-OPEN LINE-CLOSE

AUTOLINE

BITBLT

ILOAD IDUMP

All other opcodes are reserved and should not be used.

atYPe <5:4>

5-10 Chapter 5: Register Descriptions

Access TYPE: The performed.

I++

Value Mnemonic VRAM Access

atype

field is used to define the type of access to the VRAM that is

MGA ATHENA Specification

-..

Ma trox Confidential

Drawing control register (continued)

DWGCTL

blockm

<6>

linear

<7>

hop 49: 16>

BLOCK Mode: Specifies whether or not the destination will be written in block mode.

0 Normal write access

. 1 Block mode write selected

LINEAR mode: Specifies if the BITBLIT source is linear or XY.

. 0 XY bitblit

n 1 Linear bitblit

Boolean Operation between a source and a destination. The table below shows the various functions performed by the Booleen ALU in 1, 8, 16, and 32 bits/pixel modes. During block mode operations, bop must be set to 1100 (Ch).

hop

0000

0001 0010 0011 0100 0101 0110

0111

1000 1001 1010 1011 1100 1101 1110

, 1111

Function

-(D I S) D&-S

-S

(-D)

-D

DAS

-(D & S) D&S

-(D A S) D

D I -S

(-D) I S

DIS

trans

<23:20>

TRANSlucidity:

by writing one over ‘n’ pixels. The trans field specifies the following transparency patterns (where 1 is opaque and 0 is transparent):

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Specifies the percentage of opacity of the object. The opacity is realized

MGA ATHENA Specification

Power Graphic Mode Register Descriptions

5-11

DWGCTL (continued)

Drawing control register

alphadit

<24>

ALPHA

DIThering

0 0 0 0

1111 1111 1111

r--l

1111 0011

10 10

0000

10 10

0000

0111

1000 0000 0010 0000

10 11 0000 1000 0 0 0 0 0010

and shading enabled : Specifies whether the RED shader is used to

0001 10 10 0 10 1 10 10 0 10 1

0100

0000

0 10 1 0000

1000

0 0 0 0

0100 0 0 0 0 0001

1100 0100 0000 0001 0000

0010

0 10 1 10 10 0101 1010

0 10 1 0000 10 10 0000

rl I1 0 101

1001

0001 0000

0100 0000

1101 0000 0001 0 0 0 0 0100

generate the Alpha channel in 32 bits/pixel mode.

forcolc3 1:24>

is used

1 1 1 1

0 0 0 0 0 0 0 0

0000 0000

0110 0 0 0 0 0 10 1 0000 0 10 1

10 10 0 0 0 0

0 0 10

l----l

0 0 0 0

1000

1110 0010 0000 1000 0000

bltmod

<26:25>

zdrwen

<25>

. 1:

DRk28: 15

BLiT MODe

is used

selection: This field must be valid for BLITs without anti-aliasing:

b&mod

Value Mnemonic Usage

BMONO Source operand is monochrome in 1 bits/pixel .

BPLAN Source operand is monochrome from one plane. BFCOL Source operand is color. Source is formatted when it

comes from the host. Fast clipping can be used

during VRAM to VRAM

BUCOL Source operand is color. Source is in 32 bits/pixel

BLITs.

when it comes from the host. Fast clipping can’t be used during VRAM to VRAM BLITs.

This field must contain the value BFCOL in order to handle the line style properly for line drawing using line style.

DRaW

comparision

ENabled:

This field is shared with another field (see bltmod,

above). It must be valid for drawing using depth. This bit specifies whether or not Z

comparision is used.

0 Don’t use depth comparision

1 Use depth comparision

5-12 Chapter 5: Register Descriptions

MGA ATHENA Specification

Matrox Confidential

Drawing control register (continued)

DWGCTL

zlte

<26>

afor

<27>

hbgr

<27>

Z written when Less Than or Equal: This field is shared with another field. It must be valid for drawing using depth. This bit specifies whether Z is written when it is equal.

. 0 Pixel is updated if depth is

. 1 Pixel is updated if depth is 5

Anti-aliasing

FOReground

color selected: This field is shared with the hgbr field. It must be valid when anti-aliasing is selected. This bit performs the first color selection for the anti-aliasing.

DR5<22: 15>, DR9<22: 15>,

n 1

FORCOLc23:0>

is used

and DR

13~22: 1%

are used

Host data in BGR format: This field is shared with the afor field.

For ILOAD when bltmod = BUCOL

n 0 Source data is in

BGR format

. 1 Source data is in RGB format

abac

<28>

For ILOAD when bltmod = BMONO

0 Source data is in

endian

format

. 1 Source data is in Windows format

Anti-aliasing

BACkground

color selected: This field is shared with the hcprs field. It must be valid when anti-aliasing is selected. This bit performs the second color selection for the anti-aliasing.

0 Current pixel is selected

n 1

BACKCOL<23:0>

is selected

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MGA ATHENA Specification

Power Graphic Mode Register Descriptions

5-13

DWGCTL

hcprs

<28>

Host data is color

BLITs

ComPReSsed:

This field is shared with the

when the source data comes from the host and the data is in 24-bit true color

format. . 0 Source data is 32 bit/pixel

1 Source data is 24 bit/pixel

Drawing control register (continued)

abac

field. It must be valid for

pattern

<29>

transc

<30>

Reserved

<31,24,15:8>

PA’ITERNing

enable: This bit specifies whether patterning is enabled when performing

BLIT operations.

0 Patterning is disabled . 1 Patterning is enabled This bit also specifies whether the two banks are to be cleared in parallel when block

mode is enabled when

fbm

01Xx.

Note that when the two banks are cleared in parallel,

the fringes aren’t processed correctly, and so must be processed separately.

n 0 One bank only

. 1 Two banks in parallel

TRANSparency Color enabled: This field must be valid for

BLITs

with color expansion.

This bit specifies whether the background color is written. . 0 Background color is opaque

1 Background color is transparent

Reserved: Writing has no effect.

Chapter 5: Register Descriptions MGA ATHENA Specification

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Memory access register

MACCESS

Memory Address lCO4

30 29 28 27 26 25 24 23 222120

pwidth

Pixel WIDTH: Specifies the pixel width for drawing.

<l:O>

fhC

Frame Buffer Configuration: Specifies if the double buffer is used when drawing.

<3:2>

Attributes W- F

Reserved

19 181716

pwidth

Value

Mnemonic Mode

PW8 PW16 PW32

Value Mnemonic Mode

8 bits/pixel

16 bits/pixel 32 bits/pixel Reserved

Reset

15141312111098 7 6 5 4

Vale

0000 0000 h

fbc pwidth

Ill---l

3 2

Reserved

<31:4>

10 11

SBUF Full pixel width

DBUFA Buffer A DBUFB Buffer B

Reserved

When the system is in double-buffer mode, and pwidth specifies 8 bits/pixel (4 bits per buffer) or 32 bits/pixel (16 bits per buffer), the plane write mask must be used in order to prevent modification of the pixels in the other corresponding buffer. When pwidth

specifies 16 bits/pixel, only the targeted buffer will be modified. In this case, the plane write mask must not be used with ZI drawing when fbm = 10.

Reserved: Writing has no effect.

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MGA ATHENA Specification

Power Graphic Mode Register Descriptions

5-15

MCTLWTST

Memory control wait state

Memory Address

mctlwtst

<31:0>

Memory

memory sequencer. For each part of the memory cycle, a different 2-bit subfield is used. The contents of this register depend on of the type and speed of the RAM, and on the board configuration. Each subfield is defined as follows:

Description

DEFAULT DFLT RAS SETUP RAS HOLD

CAS SETUP

HOST DELAY HOST-D

CAS HOLD

READ CAS HOLD

HYPER READ CAS HOLD

Z READ CAS HOLD ZRC-HD

RAS PRECHARGE

ZI RAS HOLD

HYPER READ RAS PRECHARGE HRR-PR

Z RAD HOLD

SWITCH BUS WAIT

LAST PIXEL LP

1 CO8

30 29 28

27 26 25

ConTroL WaiT STate

mctlwtst<x+ 1

00 1 gclk 01

10 11

Attributes

24 23 222120

:x>

2 gclks 3 gclks

4 gclks

W-

Reset Value

FWFFFFF

mctlwtst

19 18 17 16 15

Mnemonic

R-SU R-HD

c-su

c-m RCJ-ID

HRC-HD

R-PR ZIR-HD

ZR-HD SWT-B mctlwtst<27:26>

W-

131211

mctlwtstcl :O> mctlwtst<3:2> mctlwtst<5:4> mctlwtst<7:6> mctlwtstc9:8> mctlwtst<l mctlwtstcl3: 12> mctlwtstcl5: 14> mctlwtstcl7: 16> mctlwtstcl9: 18> mctlwtstc21:20> mctlwtstc23:22> mctlwtst<25:24>

mctlwtstc29:28> mctlwtM3 1:3b

10 9

lO>

3 2

5- I6

Chapter 5: Register Descriptions

MGA ATHENA Specification

Ma trox Confidential

Memory control wait state (continued)

MCTLWTST

Programming mctlwtst (80 ns

C4001010h

mctlwtst is programmed to back to

Destination in

Memory Address

C4001010h

C4OOlllOh

is the default value to use, except for BUCOL ILOADs. In the latter case,

C4001010h

lCl0

VRAMs):

(one more gclk for BUCOL ILOAD access)

C4OOlllOh

prior to the BUCOL ILOAD execution. It’s put

when the BUCOL ILOAD execution has finished.

Attributes

R- D

DSTl-0

dsti0 <31 :o>

dstil

<63:32>

Reset Value

DeSTination

Loaded from vdc63:0>

dstil

In register: The

32 31

dsti0

and dstil fields are used to load configuration data on reset. The destination registers are normally used by the drawing engine. They are readable, however, since their values are initialized from the data bus on reset (breset). Note that the registers must be read before any direct access to the frame buffer or

drawing engine operation is performed in order to obtain valid data.

For more information on the definition of each bit on power up, refer to Section 3.6,

‘Power Up and Reset’.

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MGA ATHENA Specification

Power Graphic Mode Register Descriptions 5-17

ZMSK Z mask control register

Memory Address

zcol<3:0>

plnzmsk

<7:4>

zten

<8>

zcolblk

<9>

Reserved

<31: lO>

lC18

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

COLor:

PLaNe

Z tag

This field is used by the Depth Mask ALU as the source operand.

MaSK:

ENable:

Attributes W-F

Reserved

Reset Value XXXX XXXX h

Ei i;i

plnzmsk

Il-----lII

zcol

These bits are used to select the plane on the ZTAG RAM.

When 0, ZTAG RAM writes are inhibited; when 1, ZTAG RAM writes are

enabled (refer to Section 6.3.3 for more information). Z

COLor

select in

BLOCK

mode: This bit is used to load the ZTAG with 0 or 1 when in

block mode. Reserved: Writing has no effect.

Notes:

Since the ZTAG is used as a tag for the depth buffer, the following values are typically used:

Operation Z drawing

Z clear (all) Z clear (partial) Normal drawing;

zcolblk zcol plnzmsk

1 1

X 0000 0000

0000

1111 1111

pixsla pixslb

1111

where ‘pixsla’ and ‘pixslb’ are used to select which pixels in the depth buffer are updated in this group of 16 pixels. A pixel (as shown in the following illustration) is written when both the ‘col’ and the plnzmsk related to it are ‘ 1’.

plnzmsk

3 2 1 0

Chapter 5: Register Descriptions

MGA ATHENA Specification

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Plane write mask

PLNWT

Memory Address

plnwrmsk

<31:0>

PLaNe WRite MaSK:

operations. During intensity buffer write operations, the contents of this register are transmitted to the edge of

0 = Inhibit write

In 8 and 16 bits/pixel modes, some bits have to be replicated. Refer to Figure 3-8 for the definition of the slice for each mode.

+Note:

1ClC

Attributes

W-F

Reset

Value

XXXX XXXX h

plnwt

30 29 28 27 26 25 24 23 22

19 18 17 16 15 14 13 121110

Specifies the plane or planes to be protected during any write

VRAMs

through the

vd<63:0>

bus where they are latched on the falling

RAS/.

1 = Permit write

When performing a drawing operation with Z when fbm = 10, the plane write

mask must not be used, since the mask will affect both Z (depth) and I (intensity) plane masking.

9 8

6 5 4

Ma trox Confidential MGA ATHENA Specification

Power Graphic Mode Register Descriptions 5-19

Background Color

BCOL

Memory Address 1

backcol

<31:0>

C20

Attributes W-F Reset Value

XXXX XXXX h

backcol

30 29 28 27 26 25 24 23 222120

BACKground COLor:

The backcol field is used by the color expansion module to

19 18 171615 14 13 121110 9

7 6 5

generate the source pixels when the background is selected. As well, the backcol field is used as the background color for anti-aliased characters.

In 8 and 16 bits/pixel modes, some bits have to be replicated. Refer to Figure 3-10 for the definition of the slice for each mode.

4 3

FCOL

Memory Address

forcol

<31 :o>

backz

CEO>

Foreground color/Background Z value

1 C24

Attributes W-F

Reset

Value

XXXX XXXX h

forcol

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

partial forcol

FOReground COLor:

the source pixels when the foreground is selected. As well, forcol is used as foreground color for anti-aliased characters.

In 8 and 16 bits/pixel modes some bits have to be replicated. Refer to Figure 3-10 for the definition of the slice for each mode.

BACKground

Z value: The backz field is used with primitives that use the Z buffer. When the ZTAG bit specifies a background depth value, the backz register is selected instead of the destination register to perform the

The forcol field is used by the color expansion module to generate

comparision.

backz

5-20

Chapter 5: Register Descriptions

MGA ATHENA Specification

Matrox Confidential

Source register

SRCO,SRCl, SRC2, SRC3

Memory Address

127

lC30 lC34 lC38 lC3C

scrcreg3

srcreg<l27:0> SouRCe REGister:

For LINE with the RPL or RSTR attribute, the source register is used to store the line

style. The funcnt field of the SHIFT register points to the selected source register bit which is being used as the linestyle for the current pixel. The following illustration shows how the linestyle is stored in the source register.

127

. . .

Attributes W-FD

96 95

scrcreg2

Reset

scrcreg 1

Value

The Source register is used for all drawing operations.

Pattern direction

. . . . . .

stylelen

I I

Pixel 2 . . .

Pixel 1 (funcnt)

linestyle

XXXX XXXX h

scrcreg0

. . .

. For TRAP with the RPL or RSTR attribute, the source register is used to store the

pattern. The following format is used:

srcreg3

127

70707070707070707070707070707070

line7

For all BITBLT operations, and for TRAP or LINE using depth mode, the source

96 95

line6

srcreg2

line5 line4

64 63

line3 line2

srcregl

32 31

line1

srcreg0

line0

. The source register is used internally for intermediate data for all BITBLT operations.

Ma trox Confidential

MGA ATHENA Specification

Power Graphic Mode Register Descriptions

5-21

XYSTRT

X Y start address

Memory Address

30 29

The XYSTRT register is not a physical register. It is simply an alternative way to load registers AR5, AR6, XDST and YDST.

The XY STRT register is only used for LINE and AUTOLINE. XY STRT does not require

initialization for polylines because all the registers affected by XYSTRT are updated to

the endpoint of the vector at the end of the AUTOLINE. When XYSTRT is written, the following registers are affected: .

X-STARTclS:O>

X-START<lS:O>

Y-START<1 5:0>

. 0

--> sellin

C40

28 27 26 25 24 23 22

Attributes

Y START X START

--> xdst<l5:0>

-->

ar5<17:0> (sign extended)

-->

ydst<23:0>

W-FKD

Reset

Value

XXXX XXXX h

212019 18 17 16151413121110 9 8 7 6 5 4 3 2

(sign extended)

x-start

<15:0>

y-start

<31:16>

-->

newy

Y-START<lS:O> --> ar6<17:0>

STARTing

coordinate: x-start contains the X coordinate of the starting point of the

(sign extended)

vector. It is a 16-bit signed value in two’s complement notation.

STARTing

coordinate: y-start contains the Y coordinate of the end point of the vector.

This coordinate is always XY (this means that to use the XYSTRT register the linearizer

must be used). It is a 16-bit signed value in two’s complement notation.

5-22 Chapter 5: Register Descriptions

MGA ATHENA Specification

Matrox Confidential

X Y end address

XYEND

Memory Address

x-end

<15:0>

y-end

<31:16>

lC44

30 29 28 27 26 25 24

Attributes W-FKD

Y-END

23 222120

19 18 17 16

15 1413121110 9 8 7 6 5 4 3 2

Reset Value XXXX XXXX h

X-END

The XYEND register is not a physical register. It is just an alternative way to load registers

AR0

and AR2.

XYEND register is only used for AUTOLINE drawing.When XYEND is written, the following registers are affected:

X-END<lS:O>

Y_ENDcl5:0> --> ar247:0>

ENDing

coordinate: x-end contains the X coordinate of the end point of the vector. It is

--> arOc17:0>

(sign extended) (sign extended)

a 16-bit signed value in two’s complement notation.

ENDing

coordinate: y-end contains the Y coordinate of the end point of the vector. It is

a 16-bit signed value in two’s complement notation.

Matrox Confidential

MGA ATHENA Specification

Power Graphic Mode Register Descriptions 5-23

SHIFT

Funnel shifter control

Memory Address

Illllllll

funcnt

x-off

<3:0>

Y-Off

<6:4>

<6:0>

FUNnel w

. For BLIT operations, this register is incremented by the slice value to select source bits.

pattern X pattern. This offset must be in the range O-7 (bit 3 is always 0).

pattern Y pat tern.

lC50

Reserved

30 29 28 27 26 25 24 23 222120

Attributes W-FKD

fifcnt funoff

19 18 17 16 15 14 13 121110

stylelen

Reset Value

Resewed

9 8

XXXX XXXX h

funct

6 5 4 3 2 1 0

L--.-J-

y-off

x-off

COUNT value: This field is used to drive the funnel shifter bit selection.

For LINE operations, this is a countdown register. This register is used to initialize and

select the first bit of the line style.

OFFset:

This field is used for TRAP operations to specify the X offset in the

This field is used for TRAP operations to specify the Y offset in the

Reserved

<15:7>

funoff <21:16>

fifcnt

<25:22>

stylelen <22: 16>

Reserved

<31:26>

Reserved: Writing has no effect.

F’UNnel

shifter

OFFset:

For BLIT operations, this field is used to specify a bit offset in

the funnel shifter count. In this case, funoff is interpreted as a 6-bit signed value.

FIFO

COUNT: For BLIT operations, this field is used by the sequencer to determine how

many source slices are available. In this case, the field does not need to be initialized.

line STYLE

LENgth:

For LINE operations, this field specifies the linestyle length.

Reserved: Writing has no effect.

5-24

Chapter 5: Register Descriptions

MGA ATHENA Specification

Matrox Confidential

Sign

SGN

Memory Address

sdydxl

<o>

scanleft

co>

lC58

Attributes

W-FKD

Reset Value

XXXX XXXX h

Reserved

30 29 28 27 26 25 24 23 222120

19 18 17 16

r--I

151413121110 9 8 7 6 5 4 3 2

I I

sdydxl’

Sign of Delta Y minus Delta X: This bit is shared with scanleft. It is defined for LINE drawing only and specifies the Major axis. This bit is automatically initialized during

AUTOLINE operations.

n 0 Major axis is Y

. 1 Major axis is X

Horizontal SCAN direction used for TRAP and BLIT drawing. The direction in a BLT or filled trapezoid.

LEFT

(1) vs RIGHT (0): This bit is shared with sdydxl. It is

scanleft

bit is set according to the X scanning

sdxl

cl>

sdy

<2>

Reserved

<4:3>

sdxr

<5>

Normally, this bit is always programmed to zero except for BITBLT when bltmod = BPLAN or BFCOL.

Sign of delta X (line draw or left trapezoid edge): The sdxl bit specifies the X direction for a line draw (opcod = LINE) or the X direction when plotting the left edge in a filled trapezoid draw. This bit is automatically initialized during

0 delta X is positive

1 delta X is negative

AUTOLINE

operations.

Sign of delta Y: The sdy bit specifies the Y direction of the destination address. This bit is automatically initialized during AUTOLINE operations.

. 0 delta Y is positive

. 1 delta Y is negative

Reserved: Writing has no effect.

Sign of delta X (right trapezoid edge): The sdxr bit specifies the X direction of the right edge of a filled trapezoid.

. 0 . 1 delta X is negative

Reserved

Reserved: Writing has no effect.

<31:6>

Matrox Confidential

de1

ta X is positive

MGA ATHENA Specification

Power Graphic Mode Register Descriptions 5-25

LEN

Length

Memory Address

‘

length

<15:0>

LENGTH: The length bit is a 16-bit unsigned value.

Reserved

<31:16>

lC5C

Attributes W-FKD

Reserved

30 29 28 27 26 25 24 23 222120

. The length field doesn’t require initialization for

For a vector draw, length is programmed with the number of pixels to be drawn.

19 18 17 16 15 14 13 121110 9 8 7 6 5 4

auto-init

Reset Value

length

vectors.

XXXX XXXX h

. For Blits and trapezoid fills, length is programmed with the number of lines to be filled

BLITed.

Reserved: Writing has no effect.

AR0

Memory Address

ar0 <17:0>

Multi-purpose address register 0

C60

Reserved

30 29 28 27 26 25 24 23 222120

Address Register 0: The

For AUTOLINE, this register holds the X end address (see the XYEND register

Attributes W-FKD Reset

ar0

19 18

1716

15 14 13 121110 9 8 7 6 5 4

arO

field is an l&bit signed value in two’s complement notation.

Value

XXXX XXXX h

description on page 5-23).

For LINE, it holds 2 x ‘b’. . For a filled trapezoid, it holds . For a BLIT,

ar0

holds the line end source address ‘sea’.

‘dY1’.

Refer to Table 3-l for more information.

Reserved

Writing has no effect.

<31: 18>

5-26 Chapter 5: Register Descriptions MGA ATHENA Specification

Ma trox Confidential

Multi-purpose address register 1

AR1

Memory Address

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

arl

<23:0>

Address Register 1: The arl field is a 24-bit signed value in two’s complement notation. This register is also loaded when ar3 is accessed.

. For LINE, it holds the error term (initially 2 x ‘b’ - ‘a’ -[sdy]).

. For a filled trapezoid, it holds the error term in two’s complement notation; initial1

lC64

Reserved

Attributes

W-FKD

Reset

Value

arl

XXXX XXXX h

This register does not need to be loaded for AUTOLINE.

‘err1

= [sdxl] ?

For a BLIT, arl holds the line start source address ‘ssa’. Because ‘ssa’ is also requi

‘dX1’

‘dY1’ -

1 :

-‘dXl’

red

in ar3 and when writing ar3, arl is loaded, this register doesn’t need to be explicitly initialized.

Reserved

Reserved: Writing has no effect.

~31: 24>

Multi-purpose address register 2

Memory Address

C68

Attributes

Reserved

ar2

<17:0>

29 28 27

Address Register 2: The ar2 field is an

For AUTOLINE, this register holds the Y end address (see the XYEND register

description on page 5-23).

. For LINE, it holds the minor axis error increment (initially 2 x ‘b’ - 2 x ‘a’).

For a filled trapezoid, it holds the minor axis increment

26 25

24 23 222120

W-FKD

19 18

Reset

Value

XXXX XXXX h

ar2

1716

15 14 13

l&bit

signed value in two’s complement notation.

10 9

-IdXlI.

8 7

6 5

4 3 2

AR2

. This register is not used for BLIT operations.

Reserved

<31: 18>

Matrox Confidential

Reserved: Writing has no effect.

MGA ATHENA Specification

Power Graphic Mode Register Descriptions

5-27

AR3

Multi-purpose address register 3

Memory Address

ar3

<23:0>

SPVF

<26:24>

C6C

Attributes

Reserved spage

‘II

31 30 29 28 27 26 25 24 232221

W-FKD

19 18

1716

15 14 13 121110 9 8

Reset Value

ar3

7 6 5 4

XXXX XXXX h

Address Register 3: The ar3 field is a 24-bit signed value in two’s complement notation or

a 24-bit unsigned value. . This register is used during AUTOLINE, but does not need to be initialized.

This register is not used for LINE without Auto initialization, nor is it used by TRAP.

In the two operand Blit algorithms, ar3 contains the source current address

value must be initialized as the starting address for a Blit. The

‘sea’

is always linear.

‘sea’.

This

These three bits are used as an extension to ar3 in order to generate a 27-bit source or pattern address. They are not modified by ALU operations.

The spage field is not used for TRAP, LINE or

AUTOLINE

operations.

Reserved

~31: 27>

AR4

Memory Address

ar4

<17:0>

Reserved: Writing has no effect.

Multi-purpose address register 4

1C70

31 30 29 28 27 26 25 24 23 22 21 20 19 18 1716 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address register 4: The ar4 field is an 1

For TRAP, it holds the error term. Initially:

‘en-r’

. This register is used during

Attributes W-FKD Reset

Reserved

&bit

signed value in two’s complement notation.

= [sdxr] ?

‘dXr’

‘dYr’ -

AUTOLINE,

1 : -‘dXr’

but it doesn’t need to be initialized.

Value

ar4

XXXX XXXX h

. This register is not used for LINE or BLIT operations.

Reserved

<31:18>

5-28

Chapter 5: Register Descriptions MGA ATHENA Specification Ma trox Confidential

Reserved: Writing has no effect.

Multi-purpose address register 5

AR5

Memory Address

ar5

Address Register 5: The

<17:0>

. At the begining of AUTOLINE,

. This register is not used for LINE without Auto initialization. . For TRAP, it holds the minor axis increment . In BLIT algorithms,

1C74

Attributes W-FKD

Reserved

30 29 28 27 26 25 24

23 222120

ar5

field is an

Reset

Value

ar5

19 18

l&bit

ar5

holds the X start address (see the XYSTRT register

15 14 13 121110

1716

signed value in two’s complement notation.

9 8

XXXX XXXX h

6 5 4 3 2

on page 5-22). At the end of AUTOLINE the register is loaded with the X end, so it is not necessary to reload the register when drawing a polyline.

IdYrl.

ar5

holds the pitch of the source operand

‘syinc’

(See Table 3-l).

A negative pitch value specifies that the source is scanned from bottom to top while a

positive pitch value specifies a top to bottom scan.

Reserved

<31: 18>

Multi-purpose address register 6

Memory Address

ar6

<17:0>

Reserved: Writing has no effect.

AR6

1C78

Attributes W-FKD

Reserved

30 29 28 27 26 25 24 23 222120

19 18

1716

Reset

15 14 13 121110

Value

ar6

9 8

XXXX XXXX h

7 6 5 4 3

Address Register 6: This field is an 1%bit signed value in two’s complement notation. It is sign extended to 24 bits before being used by the ALU.

. At the begining of AUTOLINE, ar6 holds the Y start address (see the XYSTRT register

description on page 5-22). During AUTOLINE processing, this register is loaded with the signed Y displacement. At the end of

AUTOLINE

the register is loaded with the Y

end, so it is not necessary to reload the register when drawing a polyline. . This register is not used for LINE without Auto initialization. . For TRAP, it holds the major axis increment

This register is not used for BLIT operations.

Reserved

Reserved: Writing has no effect. These bits return all zeroes when read.

~31: 18>

Matrox Confidential

MGA ATHENA Specification

‘dYr’.

Power Graphic Mode Register Descriptions

5-29

PITCH

Memory

pitch

Memory Address

iY <12:0>

lC8C

Attributes

W-m

Reset Value XXXX XXXX h

30 29 28 27

26 25 24 232221

191817161514 13

121110

9 8 7 6

5 4 3 2

Y Increment: This field is a 13-bit unsigned value. The Y increment value is a pixel unit, and it must be a multiple of 32 (the five LSB

= 0). This field specifies the increment to be added to or subtracted from ydst between two destination lines. This field is also used as the multiplicator factor for linearizing the iy register.

It should be noted that only a few values are supported for linearization. If the pitch selected can’t be linearized, the ylin bit should be used to disable the linearization operation. The following table provides the supported pitch for linearization:

Pitch

512

640

768

800

1024

0001000000000 0001010000000

0001100000000

0001100100000

0010000000000

Pitch

1152

1280 1536 1600

0010010000000 0010100000000 0011000000000

0011001000000

Reserved

<14: 13>

ylin

<15>

Reserved

<31:16>

Reserved: Writing has no effect.

LINearization:

0 Linearize the address

1 Don’t linearize the address

This bit specifies if the address must be linearized or not.

Reserved: Writing has no effect.

5-30 Chapter 5: Register Descriptions

MGA ATHENA Specification

Matrox Confidential

Y address register

YDST

Memory Address 1

Reset Value XXXXXXX 0 XXXXXXXXXXXXXXXXXXXXXXXX b

ydst

<23:0>

Y as a signed value in two’s complement notation. Two formats are supported: linear format and XY format. The current format is selected by ylin.

When XY format is used, ydst represents the Y coordinate of the address. The valid range is -32768 to before being used.

When linear format is used, ydst must be programmed as follows:

C9O

Attributes W-FKD

i? E

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DeSTination:

The ydst field contains the current Y coordinate of the destination address

+32767 (16-bit

ydst

c--

(Y coordinate) x PITCH >> 5

signed). The XY value is always converted to a linear value

ydst

newy

<24>

Reserved

<28:25>

The Y coordinate range is from -32768 to

+32767

(16-bit signed) and the pitch range is

from 32 to 6144. Pitch is also a multiple of 32.

Before starting a vector draw, ydst must be loaded with the Y coordinate of the starting point of the vector. This can be done by accessing the

XY-START

Before starting a BLIT, ydst is loaded with the Y coordinate of the starting corner of the destination rectangle.

For trapezoids, this register must be loaded with the Y coordinate of the first scanned line of the trapezoid.

NEW Y: The newy field is a l-bit field which is always set every time the register is written by the processor (bit 24 of the data bus is discarded). This bit is cleared when ydstorg is added to ydst. This bit is used to inhibit the linearization of an address which has already been linearized. This bit is also set when the host accesses the XYSTRT register.

Reserved: Writing has no effect.

sellin <31:29>

SELected LINe.

transparency functions. During linearization, this field is loaded with the three LSB of ydst. If no linearization occurs, then those bits have to be initialized correctly if one of the above-mentioned functions is to be used.

Matrox Confidential

The

sellin

field is used to perform the dithering, patterning, and

MGA ATHENA Specification

Power Graphic Mode Register Descriptions

5-31

YDSTORG

Memory origin

Memory Address

ydstorg

<26:0>

Reserved

<31:27>

1C94

Reserved

Attributes W-FK

ydstorg

Reset Value XXXX XXXX h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DeSTination

value in pixel units, in order to position the first pixel of the first line of the screen. This

Reserved: Writing has no effect.

ORiGin:

The ydstorg field is a 27-bit unsigned value. It gives an offset

YTOP Clipper Y top boundary

Memory Address

CYtoP <26:0>

1C98

Reserved

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Attributes W-FK Reset

CytOP

Clipper Y top boundary: The cytop field contains an unsigned 27-bit value which is interpreted as a positive pixel address and compared with the current ydst. The value of

Value

XXXX XXXX h

the ydst field must be greater than or equal to cytop to be inside the drawing window. This register must be programmed with a linearized line number:

cytop = (TOP LINE NUMBER) x PITCH + YDSTORG

This register must be loaded with a multiple of 32 (the five LSB = 0). Note that since the cytop value is interpreted as positive, any negative ydst value is

automatically outside the clipping window. There is no way to disable clipping.

Reserved

Reserved: Writing has no effect.

<31:27>

5-32 Chapter 5: Register Descriptions MGA ATHENA Specification

Matrox Confidential

Clipper Y maximum boundary

YBOT

Memory Address

cybot

<26:0>

Clipper Y interpreted as a positive pixel address and compared with the current ydst. The value of the ydst field must be less than or equal to cybot to be inside the drawing window.

This register must be programmed with a linearized line number:

This register must be loaded with a multiple of 32 (the five LSB = O).There is no way to disable clipping.

Reserved

Reserved: Writing has no effect.

<31:27>

C9C

Reserved

29 28

cybot = (BOTTOM LINE NUMBER) x PITCH + YDSTORG

Attributes

27 26 25 2423222120

BOTtom

boundary: The cybot field contains an unsigned 22-bit value which is

W-FK

18 17 16 15 14

Reset

Value

XXXX XXXX h

cybot

13 121110 9 8 7 6 5 4

3 2

Clipper X minimum boundary

Memory Address

cxleft

<12:0>

Clipper X LEFT boundary: The cxleft field contains an unsigned 13-bit value which is interpreted as a positive pixel address and compared with the current xdst. The value of

lCA0

29 28 27 26 25 24 23

xdst must be greater than or equal to cxleft to be inside the drawing window. Note that since the cxleft value is interpreted as positive, any negative xdst value is

automatically outside the clipping window. There is no way to disable clipping.

Reserved

Reserved: Writing has no effect.

<31: 13>

Attributes W-FK

Reset

Value

Reserved cxleft

222120

19 18 17 16

15 14 13 121110 9 8 7 6 5 4 3 2

CXLEF’t=

XXXX XXXX h

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MGA ATHENA Specification

Power Graphic Mode Register Descriptions

5-33

CXRIGHT

Clipper X maximum boundary

Memory Address

cxright

<12:0>

Reserved

<31: 13>

1 CA4

30 29 28

27 26

a..

Attributes W-FK

Reserved

25 24 23 22

. 3 1 a

Reset

19 18 17 16 15 1413121110 9 8 7 6 5 4 3 2

n ' 3

1 ‘

Value

cxright

XXXX XXXX h

8 j

Clipper X RIGHT boundary: The cxright field contains an unsigned 13-bit value which is interpreted as a positive pixel address and compared with the current xdst. The value of xdst must be less than or equal to cxright to be inside the drawing window. There is no way to disable clipping.

Reserved: Writing has no effect.

FXLEK

Memory Address

fxleft

CEO>

Reserved

<31:16>

X address register (left)

CAM

Attributes W-FKD

Reset

Value

XXXX XXXX h

Reserved

30 29 28 27 26 25

Filled object X boundary of any filled object being drawn. It is a 16-bit signed value in two’s complement notation.

The fxleft field is not used for line drawing. . During filled trapezoid drawing, fxleft is updated during the left edge scan. . During a BLIT operation, fxleft is static, and specifies the left pixel boundary of the

area being written to.

Reserved: Writing has no effect.

24 23 222120

LEFI’

coordinate: The fxleft field contains the X coordinate of the left

18 17 16 15 14 13

121110 9 8

6 5 4 3 2

5-34 Chapter 5: Register Descriptions

MGA ATHENA Specification

Ma trox Confidential

X address register (right)

FXRIGHT

Memory Address

fxright

<15:0>

Reserved

<31:16>

Filled object X RIGHT coordinate: The fxright field contains the X coordinate of the right boundary of any filled object being drawn. It is a 16-bit signed value in two’s complement notation.

. The fxright field is not used for line drawing. . During filled trapezoid drawing, fxright is updated during the right edge scan. . During a BLIT operation, fxright is static, and specifies the right pixel boundary of the

Reserved: Writing has no effect.

1CAC

Reserved

30 29 28 27 26 25 24

area being written to.

Attributes

23 222120

W-FKD

19 18 17 16

1514

Reset

13 121110

Value

XXXX XXXX h

fxrig ht

9 8 7 6 5 4 3 2

X Destination address register

Memory Address

lCB0

Attributes

Reserved

30 29 28 27 26 25 24

xdst

<15:0>

X coordinate of the destination address: The xdst field contains the running X coordinate

of the destination address. It is a 16-bit signed value in two’s complement notation.

W-FKD

23 222120

19 18 17 16

1514

Reset

13 121110

Value

XXXX XXXX h

xdst

9 8 7 6 5 4 3 2

XDST

. Before starting a vector draw, xdst must be loaded with the X coordinate of the starting

point of the vector. At the end of a vector xdst contains the address of the last pixel of the vector. This can also be done by accessing the XYSTRT register.

. This register does not require initialization for polyline operations.

For trapezoids and

BLITs,

this register is automatically loaded from fxleft and fxright

and no initial value must be loaded.

Reserved

Reserved: Writing has no effect.

<31:16>

Ma trox Confidential MGA ATHENA Specification

Power Graphic Mode Register Descriptions

5-35

DRO

Data ALU register 0

Memory Address 1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

dr0<31:0>

Data ALU Register 0:

. For LINE with 2, the DRO register holds the current 2 value for the currently drawn

CC0

Attributes

W-FD

Reset Value

XXXX XXXX h

dr0

For TRAP with 2, the DRO register is used to scan the left edge of the trapezoid. This register must be initialized with its starting 2 value. In this case, DRO is a signed 17.15

value in two’s complement notation.

pixel. This register must be initialized with the starting Z value. In this case, DRO is a

signed 17.15 value in two’s complement notation.

For LINE with anti-aliasing, DRO holds the fraction of the pixel covered by the line

which is used by the blender. The register must be initialized with 1 (for the first part) or 0 (for the second part). In this case, DRO is a signed 16.16 value in two’s complement notation.

DRI

Memory Address

drl<31:0>

Data ALU register 1

KC4

Attributes W-FD

Reset

Value

XXXX XXXX h

drl

30 29 28 27 26 25 24 23 222120

1 I , L

Data ALU Register 1: . The DRl output is used as the current depth value. Because Z should never be negative,

a negative value is interpreted as an overflow and data is saturated before being used.

. For TRAP and LINE with Z, the DRl register holds the current Z value for the

currently drawn pixel. This register does not require initialization. In this case, DRl is a

signed 17.15 value in two’s complement notation.

. For LINE with anti-aliasing,

which is used by the blender. This register does not require initialization. In this case,

DRl is a signed 16.16 value in two’s complement notation.

19 18 17 16 15 14 13 121110 9 8 7 6 5 4 3 2

DRl

holds the fraction of the pixel covered by the line

5-36 Chapter 5: Register Descriptions

MGA ATHENA Specification

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Data ALU register 2

DR2

Memory Address

dr2<31:0>

Data ALU Register 2: . For TRAP with Z, the DR2 register holds the Z increment value along the X axis. In

. For LINE with Z, the DR2 register holds the Z increment value along the major axis. In

lCC8

Attributes W-F

Reset Value

XXXX XXXX h

dr2

30 29 28 27 26 25 24 23 222120

19 18 17 16 15 14

13 121110 9 8

6 5 4

3 2

this case, DR2 is a signed 17.15 value in two’s complement notation.

For LINE with anti-aliasing, DR2 holds the pixel coverage increment value along the

major axis. In this case, DR2 is a signed 16.16 value in two’s complement notation.

Data ALU register 3

Memory Address

30 29 28 27 26 25 24 23 222120

dr3<31:0>

Data ALU Register 3:

For TRAP with Z, the DR3 register holds the Z increment value along the Y axis. In this case, DR3 is a signed 17.15 value in two’s complement notation.

. For LINE with Z, the DR3 register holds the Z increment value along the diagonal axis.

In this case, DR3 is a signed 17.15 value in two’s complement notation.

For LINE with anti-aliasing, DR3 holds the pixel coverage increment value along the

diagonal axis. In this case, DR3 is a signed 16.16 value in two’s complement notation.

1CCC

Attributes W-F

19 18 17 16 15 141312

dr3

Reset

11109 8 7

Value

XXXX XXXX h

4 3 2

6 5

DR3

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MGA ATHENA Specification

Power Graphic Mode Register Descriptions

5-37

DR4

Data ALU register 4

Memory Address

dr4

<23:0>

Reserved

<31:24>

CD0

Attributes

Reserved

30 29 28 27 26 25 24 23 222120

VFD

19 18

dr4

1716

15 14 13 121110 9

Reset

Value

7 6 5 4 3

XXXX XXXX h

Data ALU Register 4: DR4 holds a signed 9.15 value in two’s complement notation.

For TRAP with Z, the DR4 register is used to scan the left edge of the trapezoid for the

red color (Gouraud shading). This register must be initialized with its starting red color

value.

For LINE with Z, the DR4 register holds the current red color value for the currently

drawn pixel. This register must be initialized with the starting red color. Reserved: Writing has no effect.

DR5

Memory Address

1 CD4

Attributes W- FD Reset

Reserved

30 29 28 27 26 25 24

dr5 <23:0> Data ALU Register 5:

The DR5 output is used as the current red value. Because intensity should never be

negative, a negative value is interpreted as an overflow and data is saturated before

being used.

. For TRAP and LINE with Z, the DR5 register holds the current red color value for the

currently drawn pixel. This register does not require initialization.

Reserved

<31:24>

Reserved: Writing has no effect.

Data ALU register 5

Value

XXXX XXXX h

dr5

23 222120

DR5

holds a signed 9.15 value in two’s complement notation.

19 18 17 16

15 14 13 121110 9 8

6 5 4 3 2

5-38 Chapter 5; Register Descriptions MGA ATHENA Specification Matrox Confidential

Matrox IS-ATHENA MGA ATHENA Specification Revision 1 - Manual No. 1034-MS

Specifications and Main Features

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