Matrix MT3401 Schematics

MT3401

P-Channel Enhancement Mode MOSFET

 DESCRIPTION

The MT3401 is the P-Channel logic enhancement mode power field effect transistor is produced using high

cell density, DMOS trench technology.

This high-density process is especially tailored to minimize on-state resistance.

These devices are particularly suited for low voltage application such as cellular phone and notebook

computer power management and other Battery powered circuits, and low in-line power loss are needed in a

very small outline surface mount package.

 FEATURES

¾ -30V/-4.0A, R

¾ -30V/-3.2A, R

¾ -30V/-1.2A, R

¾ Super high density cell design for extremely low

R

¾ Exceptional on-resistance and maximum DC

current capability

¾ SOT-23-3L package design

DS(ON)

= 58 mΩ @ VGS = -10V

DS(ON)

= 65 mΩ @ VGS = -4.5V

DS(ON)

= 85 mΩ @ VGS = -2.5V

DS(ON)

 PIN CONFIGURATION

 APPLICATIONS

¾ POWER Management in Note

¾ Portable Equipment

¾ Battery Powered System

¾ DC/DC Converter

¾ Load Switch

¾ DSC

DRAIN

SOURCE

GATE

- 1 - www.matrix-microtech.com.tw

Ver 1.02

 ABSOLUTE MAXIMUM RATINGS

(TA=25℃ Unless Otherwise Noted)

Parameter Symbol Maximum Unit

MT3401

P-Channel Enhancement Mode MOSFET

Drain-Source Voltage VDS -30 V

Gate-Source Voltage VGS ±12 V

TA = 25 ℃ -4.0

Continuous Drain Current

TA = 70 ℃

ID

A

-3.2

Pulsed Drain Current IDM -15 A

Continuous Source Current (Diode Conduction) IS -1.0 A

TA = 25 ℃ 1.25

Power Dissipation

TA = 70 ℃

Operating junction temperature range TJ 150 OC

Storage temperature range T

PD

- 55 to 150

STG

0.8

O

W

C

 THERMAL RESISTANCE RATINGS

Thermal Resistance Symbol Maximum Unit

Junction-to-Ambient R

120

θJA

O

C/W

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Ver 1.02

 ELECTRICAL CHARACTERISTICS

(TA=25℃ Unless Otherwise Noted)

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static Parameters

MT3401

P-Channel Enhancement Mode MOSFET

Drain-Source Breakdown Voltage V

Gate Threshold Voltage V

Gate Current I

(BR)DSSVGS

VGS = VDS, ID= -250μA -0.4 - -1.2 V

GS(th)

VDS = 0V, VGS = ±12V - - ±100 nA

GSS

= 0V, ID = -250μA -30 - - V

VDS = -24V, VGS = 0V - - -1

Zero Gate Voltage Drain Current I

DSS

V

= -24V, VGS = 0V, TJ = 55 ℃ - - -10

DS

μA

Forward Trans conductance gfs VDS = -5V, ID = -4.0A - 10 - S

On-State Drain Current I

Drain-Source On Resistance

Diode Forward Voltage VSD IS = -1.0A, V

D(ON)

R

DS(ON)

V

≦-5V, V

DS

V

= -10V, ID = -4.0A - 45 58

GS

V

= -4.5V, ID = -3.2A - 50 65

GS

= -2.5V, ID = -1.2A - 60 85

V

GS

= -10V -10 - - A

GS

= 0V -

GS

-0.8 -1.2 V

mΩ

Dynamic Parameters

Input Cap. C

Output Cap. C

Reverse Transfer Cap. C

- 540

iss

= -15V, V

V

DS

- 131

oss

F = 1MHz

rss

= 0V,

GS

pF

- 105

Total Gate Charge Qg - 14 21

= -15V, V

V

Gate-Source Charge Qgs - 1.9

DS

I

= -4.0A

D

Gate-Drain Charge Qgd

= -10V

GS

nC

- 3.7

Turn-On Time

Turn-Off Time

T

- 10 15

D(ON)

t

- 15 25

r

T

- 31 50

D(OFF)

Tf

= -15V, RL = 15Ω, ID = -1A,

V

DS

V

= -10V, RG = 6Ω

GEN

nS

- 20 30

- 3 - www.matrix-microtech.com.tw

Ver 1.02