Mathworks SIMULINK HDL CODER 1 user guide

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Simulink®HDL Code

User’s Guide

r™ 1

Page 2

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HDL Coder™ User’s Guide

Page 3

Revision History

September 2006 Online only New for Version 1.0 (Release 2006b) March 2007 Online only Updated for Version 1.1 (Release 2007a) September 2007 Online only Revised for Version 1.2 (Release 2007b) March 2008 Online only Revised for Version 1.3 (Release 2008a) October 2008 Online only Revised for Version 1.4 (Release 2008b) March 2009 Online only Revised for Version 1.5 (Release 2009a) September 2009 Online only Revised for Version 1.6 (Release 2009b) March 2010 Online only Revised for Version 1.7 (Release 2010a)

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Getting Started

Product Overview ................................. 1-2

Automated HDL Code Generation in the Hardware

Development Process

Summary of Key Features

............................ 1-2

.......................... 1-3

Contents

Expected Users and Prerequisites

Software Requirements and Installation

Software Requirements Installing the Software

Available Help and Demos

Online Help Demos

...................................... 1-10

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Introduction to HDL Code Generation

Before You Generate Code .......................... 2-2

Overview of Exercises

The sfir_fixed Demo Model

.............................. 2-3

......................... 2-4

Generating HDL Code Using the Command Line

Interface

Overview Creating a Folder and Local Model File Initializing Model Parameters with hdlsetup

........................................ 2-7

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Generating a VHDL Entity from a Subsystem .......... 2-10

Generating VHDL Test Bench Code Verifying Generated Code Generating a Verilog Module and Test Bench

........................... 2-13

.................. 2-12

........... 2-14

Generating HDL Code Using the GUI

Simulink Creating a Folder and Local Model File Viewing Coder Options in the Configuration Parameters

Dialog Box Creating a Control File Initializing Model Parameters with hdlsetup Selecting and Checking a Subsystem for HDL

Compatibility Generating VHDL Code Generating VHDL Test Bench Code Verifying Generated Code Generating Verilog Model and Test Bench Code

Simulating and Verifying Generated HDL Code

HDL Coder GUI Overview ................. 2-16

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Code Generation Options in the Simulink®HDL

Coder GUI

vi Contents

Viewing and Setting HDL Coder Options ............ 3-2

HDL Coder Options in the Configuration Parameters Dialog

Box

........................................... 3-2

HDL C oder Options in the Model Explorer HDL Coder Menu

HDL Coder Pane: General

HDL C oder Top-Level Pane Overview File name Generate HDL for Language Folder Code Generation Output Generate traceability report

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Include requirements in block comments .............. 3-16

HDL Coder Pane: Global Settings

Global Settings Overview Reset type Reset as serted level Clock input port Clock enable input port Oversampling factor Reset input port Comment in header Verilog file extension VHDL file extension Entity conflict postfix Package postfix Reserved word postfix Split entity and architecture Split entity file postfix Split arch file postfix Clocked process postfix Enable prefix Pipeline postfix Complex real part postfix Complex imaginary part postfix Input data type Output data type Clock enable output port Represent constant values by aggregates Use "rising_edge" for registers Loop unrolling Cast before sum Use Verilog Inline VHDL configuration Concatenate type safe zeros Optimize timing controller Minimize clock enables

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`timescale directives ................... 3-49

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HDL Coder Pane: Test Bench

Test Bench Overview HDL test bench Cosimulation blocks Cosimulation model for use with: Test bench name postfix

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Force clock ....................................... 3-64

Clock high time (ns) Clock low time (ns) Hold time (ns) Setup time (ns) Force clock enable Clock enable delay (in clock cycles) Force reset Reset length (in clock cycles) Hold input data betw een samples Initialize test bench inputs Multi-file test bench Test bench reference postfix Test bench data file name postfix Ignore output data checking (number of samples)

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HDL Coder Pane: EDA Tool Scripts

EDA Tool Scripts Overview Generate EDA scripts Generate multicycle path information Compilefilepostfix Compile Initialization Compile command for VHDL Compile command for Verilog Compile termination Simulation file postfix Simulation initialization Simulation command Simulation waveform viewing command Simulation termination Synthesis file postfix Synthesis initialization Synthesis command Synthesis termination

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Generating HDL Code for Multirate Models

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viii Contents

Overview of Multirate Models ...................... 4-2

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Configuring Multirate Models for HDL Code

Generation

Overview Configuring Model Parameters Configuring Sample Rates in the Model Constraints for Rate Transition Blocks and Other Blocks in

Multirate Models

...................................... 4-3

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................................ 4-4

Example: Model with a Multirate DUT

Generating a Global Oversampling Clock

Why Use a Global Oversampling Clock? Requirements for the Oversampling Factor Specifying the Oversampling Factor From the GUI Specifying the Oversampling Factor From the Command

Line

Resolving Oversampling Rate Conflicts

Generating Multicycle Path Information Files

Overview Format and Content of a Multicycle Path Information

File File Naming and Location Conventions Generating Multicycle Path Information F i les Using the

GUI Generating Multicycle Path Information F i les Using the

Command Line Limitations Demo

Properties Supporting Multirate Code Generation

Overview HoldInputDataBetweenSamples OptimizeTimingController

.......................................... 4-11

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Code Generation Control Files

Overview of Control Files .......................... 5-2

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What Is a Control File? ............................. 5-2

Selectable Block Implementations and Implementation

Parameters Implementation Mappings Control File Demo

.................................... 5-3

.......................... 5-4

................................. 5-4

Structure of a Control File

Code Generation Control O bjects and M eth ods

Overview hdlnewcontrol forEach forAll set

.............................................. 5-12

generateHDLFor hdlnewcontrolfile

Using Control Files in the Code Generation Process

Where to Locate Yo ur Control Files Creating a Control File and Saving Your H DL Code

Generation Settings Making Your Control Files More Portable Associating an Existing Control File with Your Model Detaching a Control File from Your Model Setting Up HDL Code Generation Defaults with a C ontrol

File

Specifying Block Implementations and Parameters in

the Control File

Overview Generating Selection/Action Statements with the

hdlnewforeach Function

........................................ 5-7

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x Contents

Specifying Block Implementations and

Parameters for HDL Code Generation

Summary of Block Implementations ................. 6-2

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Blocks with Multiple Implementations .............. 6-27

Overview Implementations for Commonly Used Blocks Math Function Block Implementations Divide Block Implementations Subsystem Interfaces and Special-Purpose

Implementations

A Note on Cascade Implementations

Block-Specific U sage, Requirements, and Restrictions

for HDL Code Generation

Block Usage, Requirements, and Restrictions Restrictions on Use of Blocks in the Test Bench

........................................ 6-27

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Block Implementation Parameters

Overview ConstMultiplierOptimization CoeffMultipliers Distributed Arithmetic Implementation Parameters for

Digital Filter Blocks DistributedPipelinin g InputPipeline OutputPipeline ResetType Speed vs. Area Optimizations for FIR Filter

Implementations Interface Generation Parameters

Blocks That Support Complex Data

Complex Coefficients and Data Support for the Digital

Filter and Biquad Filter Blocks

Using Lookup Table Blocks

Lookup Table (n-D) Prelookup Direct Lookup Table (n-D) Lookup Table

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The hdldemolib Block Library

Accessing the h dldemolib Library Blocks ............ 7-2

RAM Blocks

Overview o f RAM Blocks Dual Port RAM Block Simple Dual Port RAM Block Single Port RAM Block Code Generation with RAM Blocks Limitations for RAM Blocks Generic RAM and ROM Demos

HDL Counter

Overview Counter Modes Control Ports Defining the Counter Data Type and Size HDL Implementation and Implementation Parameters Parameters and Dialog Box

HDL FFT

Overview Block Inputs and Outputs HDL Implementation and Implementation Parameters Parameters and Dialog Box

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xii Contents

HDL S treaming FFT

Overview HDL Streaming FFT Block Demo Block Inputs and Outputs Timing Description HDL Implementation and Implementation Parameters Parameters and Dialog Box

Bitwise Operators

Overview of Bitwise Operator Blocks Bit Concat Bit Reduce Bit Rotate

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Bit Shift ......................................... 7-53

Bit Slice

......................................... 7-55

Generating Bit-True Cycle-Accurate Models

Overview of Generated Models ...................... 8-2

Example: Numeric Differences

Example: Latency

Defaults and Options for Generated Models

Defaults for Model Generation GUI Options Generated Model Properties for makehdl

Fixed-Point and Double-Precision Limitations for

Generated Models

Fixed-Point Limitation Double-Precision Limitation

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Code Generation Reports, HDL Compatibility

Checker, Block Support Library, and Code

.......... 8-12

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Annotation

Creating and Using a Code Generation Report ....... 9-2

Traceability and the Code Generation Report Generating an HTML Code Generation Report from the

GUI Generating an HTML Code Generation Report from the

Command Line Keeping the Report Current Tracing from Code to Model

.......................................... 9-4

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Tracing from Model to Code ......................... 9-12

Mapping Model Elements to Code Using the Traceability

Report

HTML Code Generation Report Limitations

Annotating Generated Code with Comments and

Requirements

Simulink Annotations Text Comments Requirements Comments and Hyperlinks

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HDL Comp atibility Checker

Supported Blocks Library

Code Tracing Using the Mapping File

Adding and Removing the HDL Configuration

Component

Removing the HDL Coder Configuration Component From

a Model

Adding the HDL Coder Configuration Component To a

Model

..................................... 9-33

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Interfacing Subsystems and Models to HDL

Code

Overview of HDL Interfaces ........................ 10-2

xiv Contents

Generating a Black Box Interface for a Subsystem

Generating Black Box Control Statements Using

hdlnewblackbox

Generating Interfaces for Referenced Models

................................. 10-5

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.... 10-3

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Code G e ne ration for Enabled and Triggered

Subsystems

Code Generation for Enabled Subsystems Code Generation for Triggered Subsystems Best Practices for Using Enabled and Triggered

Subsystems

..................................... 10-10

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Code Generation for HDL Cosimulation Blocks

Generating a Simulink Model for Cosimulation with an

HDL Simulator

Overview Generating a Cosimulation M odel from the GUI Structure of the Generated Model Launching a Cosimulation The Cosimulation Script File Complex and Vector Signals in the Generated Cosimulation

Model Generating a Cosimulation Model from the Command

Line Naming Conventions for Generated Cosimulation Models

and Scripts Limitations for Cosimulation Model Generation

Customizing the Generated Interface

Pass-Through and No-Op Implementations

Limitation on Generated Verilog Interfaces

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Stateflow HDL Code Generation Support

Introduction to Stateflow HDL Code Generation ..... 11-2

Overview Demos and Related Documentation

........................................ 11-2

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Quick Guide to Requirements for Stateflow HDL Code

Generation

Overview Location of Charts in the Model Data Type Usage Chart In itia lization Registered Output Restrictions on Imported Code Using Input and Output E vents Other Restrictions

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Mapping Chart Semantics to HDL

Software Realization of Chart Semantics Hardware Realization of Stateflow Semantics Restrictions for HDL Realization

Using Mealy and Moore Machine Types in HDL Code

Generation

Overview Generating HDL for a Mealy Finite State Machine GeneratingHDLCodeforaMooreFiniteStateMachine

Structuring a Model for HDL Code Ge ne ratio n

Design Patterns Using Advanced Chart Features

Temporal Logic Graphical Function Hierarchy and Parallelism Stateless Charts Truth Tables

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xvi Contents

Generating HDL Code with the Embedded

MATLAB Function Block

Introduction ...................................... 12-2

HDL Applications for the Embedded MATLAB Function

Block

Related Docume n tatio n and Dem os

......................................... 12-2

................... 12-3

Page 17

Tutorial Example: Incrementer ..................... 12-4

Example Model Overview Setting Up Creating the Model and Configuring General Model

Settings Adding an Embedded M ATLAB Function Block to the

Model Setting Optimal Fixed-Point Options for the Embedded

MATLAB Function Block Programming the Embedded MATLAB Function Block Constructing and Connecting the DUT_eML_Block

Subsystem Compiling the Model and Displayi ng Port Data Types Simulating the eml_hdl_incrementer_tut Model Generating HDL Code

Useful Embedded MATLAB Function Block Design

Patterns for HDL

The eml_hdl_design_patterns Library Efficient Fixed-Point Algorithms Using Persistent Variables to Model State Creating Intellectual Property with the Embedded

MATLAB Function Block Modeling Control L ogic and Simple Finite State

Machines Modeling Counters Modeling Hardware Elements

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Using Fixed-Point Bitwise Functions

Overview Bitwise Functions Supported for HDL Code Generation Bit Slice and Bit Concatenation Functions Shift and Rotate Functions

Using Complex Signals

Introduction Declaring Com plex Signals Conversion Between Complex and Real Signals Arithmetic Operations on Complex N umbers Support for Vectors of Complex Numbers Other Operations on Complex Numbers

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Distributed Pipeline Insertion for Embedded MATLAB

Function Blocks

Overview Example: Multiplier Chain

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Recommended Practices

Introduction Use Compiled External Functions on the Embedded

MATLAB Path BuildtheEmbeddedMATLABCodeFirst Use the hdlfimath Uti lity for Optimized FIMA TH

Settings Use Optim a l Fixed-Point Option Settings

Language Support

Fixed-Point Runtime Library Support Variables and Constants Use of Nontunable Parameter Arguments Arithmetic Operators Relational Op erato rs Logical Operators Control Flow Statements

Other Limitations

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Generating Scripts for HDL Simulators and

Synthesis Tools

xviii Contents

Overview of Script Generation for EDA Tools ........ 13-2

Defaults for Script Generation

Custom Script Generation

Overview Structure of Generated Script Files Properties for Controlling Script Generation

........................................ 13-4

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Controlling Script Generation with the EDA Tool Scripts

GUI Pane

...................................... 13-9

Using the HDL Workflow Advisor

About the HDL Workflow Advisor ................... 14-2

Starting th e HDL Workflow Advisor

Using the HDL Workflow Advisor Window

Running HDL Workflow Advisor Tasks

Task Execution Order Selecting the Device Under Test Selecting and Running Tasks Individually Selecting and Running a Sequence of Tasks

Correcting a Warning or Failure Problem

Generating HDL Workflow Advisor Reports

Viewing HDL Workflow Advisor Reports Saving HDL Workflow Advisor Reports

Performing FPGA Implementation and Analysis Tasks

with Third-Party Tools

FPGA Imple m entation and Analysis Tasks Overview Creating a Synthesis Project Performing Logic Synthesis Performing Mapping Performing Place and Route

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Annotating Your Model with Critical Path

Information

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HDL Workflow Advisor Tasks

HDL W orkflow Adv

HDL Workflow Adv Prepare Model f Check Global Se Check Algebrai Check Block Co Check Sample T HDL Code Gener Set Code Gene Set Basic Opt Set Advanced SetTestBen Generate RT FPGA Implem Create Pro Perform Sy Perform Lo Perform M Perform P Annotate

or HDL Code Gene ration Overview

ttings

cLoop

mpatibility

imes

ation Options Overview

ration Options Overview

ions

Options ch Options L Code and Test Bench

entation and Analysis Overview

ject

....................................

nthesis and P&R Overview gic Synthesis

apping

lace and Route

Model w ith Synthesis Results

isor Ta sks

isor Ta sk s Overview

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Proper

ties — Alphabetical List

15-2 15-2 15-4 15-5 15-6 15-7 15-8

15-9 15-10 15-11 15-12 15-13 15-14 15-15 15-16 15-17 15-18 15-19 15-20 15-21

xx Contents

nguage Selection Properties

ile Naming and Location Properties

Reset Properties

................................... 17-2

Prop

erty Reference

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................

-2

7-2

Page 21

Header Comment and General Nam ing Properties .... 17-3

Script Generation Properties

Port Properties

Advanced Coding Properties

Test Bench Properties

Generated Model Properties

.................................... 17-5

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Functions — Alphabetical List

....................... 17-4

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........................ 17-9

Function Reference

Code Generation Functions ........................ 19-2

Utility Functions

Control File Utilities

.................................. 19-3

............................... 19-4

Examples

Generating HDL Code Using the Command Line

Interface

........................................ A-2

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Generating HDL Code Using the GUI ................ A-2

Verifying Generated HDL Code in an HDL Simulator

.. A-2

Index

xxii Contents

Page 23

Getting Started

• “Product Overview” on page 1-2

• “Expected Users and Prerequisites” on page 1-7

• “Software Requirements and Installation” on page 1-8

• “Available Help and Demos” on page 1-10

Page 24

1 Getting Started

Product Overview

Automated HDL Code Generation in the Hardware Development Process

Simulink®HDL Coder™ software lets you generate hardware description language (H DL ) code based on Simulink machines. The coder brings the Model-BasedDesignapproachintothedomain of application-specific integrated ci rcuit (ASIC) and field programmable gate array (FPGA) development. Using the coder, system architects and designers can spend more time on fine-tuning algorithms and models through rapid prototyping and experimentation and less time on HDL coding.

In this section...

“Automated HDL Code Generation in the Hardware Development Process” on page 1-2

“Summary of Key Features” on page 1-3

models and Stateflow®finite-state

1-2

Typically, you use a Simulink model to simulate a design intended for realization as an ASIC or FPGA. Once satisfied that the model meets design requirements, you run the Simulink HDL Coder compatibility checker utility to examine model semantics and blocks for HDL code generation compatibility. You then invoke the coder, using either the command line or the graphical user interface. The coder generates VHDL or Verilog code that implements the design embodied in the model.

Usually, you also generate a corresponding test bench. You can use the test bench with HDL simulation tools to drive the generated HDL code and evaluate its behavior. The coder generates scripts that automate the process of compiling and simulating your code in these tools. You can also use EDA Simulator Link™, software from The MathWorks™ to cosimulate generated HDL entities within a Simulink model.

The test bench feature increases confidence in the correctness of the generated code and saves time spent on test bench implementation. T he design and test process is fully iterative. At any point, you can return to the original mode l, make modifications, and regenerate code.

Page 25

Product Overview

When the design and test phase of the project has be en completed, you can easily export the generated HDL code to synthesis and layout tools for hardware realization. The coder generates synthesis scripts for the Synplify family of synthesis tools.

Extending the Code Generation Process

There are a number of ways to extend the code generation process.

By attaching a code generation control file to your model, you can direct many details of the code generation process. At the simplest level, you can use a control file to set code generation options; such a control file could be u se d as a template for code generation in your organization.

Control files also let you specify how code is generated for selected sets of blocks within the model. The coder provides alternate HDL block implementations for a variety of blocks. You can use statements in a control file to select from among implementations optimized fo r characteristics such as speed, chip area, or low latency.

In some cases, block-specific optimizations may introduce latencies (delays) or numeric computations (for example, saturation or rounding operations) in the generated code that are not in the original model. To help you evaluate such cases, the coder creates a generated model — a Simulink model that corresponds exactly to the generated HDL code. This generated model lets you run simulations that produce results that are bit-true to the HDL code, and whos e timing is cycle-accurate w ith respect to the HD L code.

You can interface generated HDL code to existing or legacy HDL code. One way to do this is to use a subsystem in your model as a placeholder for an HDL entity, and generate a black box interface (comprising I/O port definitions only) to that entity. Another way is to generate a cosimulation interface by placing an HDL Cosimulation block in your m odel.

Summary of Key Features

Key features and components of the coder include

• Generation of synthes izable VHDL or Verilog code from Simulink models

and Stateflow charts

1-3

Page 26

1 Getting Started

• Code generation configured and initiated via graphical user interface or

command-line interface.

• Test bench generation (VHDL or Verilog) for validating generated code

• Generation of models that are bit-true and cycle-accurate with respect to

generated HDL code

• Numerous options for controlling the contents and style of the generated

HDL code and test bench

• Block support:

- Simu li nk built-in blocks

- Signal Processing Blockset™ blocks

- EDA Simulator Link HDL Cosimulation blocks

- Stateflow chart

- Embedded MATLAB

Function block

- Library of HDL-specific block implementations for FFT, hardware

counter, bitwise operators, and RAMs

1-4

- User-selectable optimized block implementations provided for commonly

used blocks

• Code generation control files support:

- Selection of alternate block implementations for specific blocks or sets of

blocks in the model

- Specification of code generation options (such as input or output

pipelining) for most block implementations

- Setting of general code generation options

- Selection of the model or subsystem from which code is to be generated.

- Definition of default or template HDL code generation settings for your

organization

• Generation of subsystem-based identification comments and mapping files

for easy tracing of HDL entities back to corresponding elements of the original model

Page 27

Product Overview

• Text from DocBlock and Simulink annotations rendered as comments in

generated code

• Generation of interfaces to existing HDL code via:

- Black box subsystem implementation

- Cosimulation with Mentor Graphics

(requires EDA Simulator Link software)

- Cosimulation with Cadence Incisive

Simulator Link software)

- Cosimulation with Synopsys

Simulator Link software)

• Compatib ility checker utility that exa mines your model for H DL code

generation compatibility, and generates HTML report with hyperlinks to problematic blocks

• Generation of scripts f or EDA tools:

ModelSim®HDL simulator

HDL simulator (requires EDA

Discovery™ HDL simulator (requires EDA

- Mentor Graphics ModelSim

- Synplify

• Model features supported for code generation:

- Real data types (fixed-point and double)

Note Results obtained from H DL code generated for models using

double data types cannot be guaranteed to be bit-true to results obtained from simulation of the original model.

- Complex signals can be used in the test bench without restriction.

- Complex signals can be used in the DUT with a restricted set of blocks

(see “Blocks That Support Complex Data” on page 6-81)

- Fixed-step,discrete,single-rate and multirate models

- Scalar and vector ports (row or column vectors only)

1-5

Page 28

1 Getting Started

Note The coder does not support variable-size signals for HDL code

generation.

1-6

Page 29

Expected Users and Prerequisites

Usersofthisproductaresystemandhardware architects and designers who develop, optimize, and verify ASICs or F PGA s. These designers are experienced with VHDL or Verilog but can benefit from automated HDL code generation.

Users are expected to have prerequisite knowledge in the following areas:

• Hardware design and system integration

• VHDL or Verilog

• MATLAB

• Simulink

• Signal Processing Blockset

• HDL simulators, such as the Mentor Graphics ModelSim simulator or

Cadence Incisive simulator

Fixed Point™

Expected Users and Prerequisites

• Synthesis tools, such as Synplify

1-7

Page 30

1 Getting Started

Software Requirements and Installation

In this section...

“Software Requirements” on page 1-8

“Installing the Software” on page 1-9

Software Requirements

The coder requires the following software from The M athWorks:

• MATLAB

• Simulink

• Simulink Fixed Point

• Fixed-Point Toolbox™

The following related products are recommended for use with the coder:

1-8

• Stateflow

• Filter Design Toolbox™ (This software is required for generating HDL

code for the Digital Filter block in certain cases. See “Summary of Block Implementations” on page 6-2.)

• EDA Simulator Link

• Signal Processing Toolbox™

• Signal Processing Blockset

Software Requirements for Demos

To operate some d emo s shipped with this release, the follow ing related products are required:

• Filter Design Toolbox

• Filter Design HDL Coder™

• EDA Simulator Link

Page 31

Software Requirements and Insta lla tion

• Communications Toolbox™ (required to use Viterbi Decoder demo)

• Communications Blockset™ (required to use Viterbi Decoder demo)

• Image Processing Toolbox™ (required to use Image Reconstruction demos)

VHDL and Verilog Language Support

Before installing the coder , make sure that you have compatible compilers and other tools. Generated code is compatible with HDL compilers, simulators and other tools that support:

• VHDL versions 93 and 02

• Verilog-2001 (IEEE 1364-2001) or later

Installing the Software

For information on installing the required software listed previously, and optional software, see the MATLAB installation documentation for your platform.

After completing your installation:

• Read “Before You Generate Code” on page 2-2 to learn about recommended

practices for ensuring that your models are compatible with HDL code generation.

• Work through the examples in Chapter 2, “Introduction to HDL Code

Generation” to acquaint yourself with the operation of the product.

1-9

Page 32

1 Getting Started

Available Help and Demos

In this section...

“Online Help” on page 1-10

“Demos” on page 1-10

Online Help

The following online help is available:

• Online help is available in the MATLAB Help browser. Click the Simulink

HDL Coder product link in the browser’s Contents pane.

• To view documentation in PDF format, click the Simulink HDL

Coder > Printable Documentation (PDF) link in the browser’s

Contents pane.

• Command-line help for the functions

hdllib,andhdlsetup is availa b le through the doc and help commands.

For example:

help makehdl

makehdl, makehdltb, checkhdl,

Demos

To access models demonstrating aspects of HDL code gen eration:

1 Inthecommand-linewindow,type the following command:

demos

The Help window opens.

2 In the Demos pane on the left, select Simulink > Simulink HDL Coder.

3 The

rightpanedisplayshyperlinkstotheavailabledemos. Clickthelinkto

desired demo and follow the demo instructions.

the

1-10

Page 33

Introduction to HDL Code Generation

• “Before You Generate Co de ” on page 2-2

• “Overview of Exercises” on page 2-3

• “The sfir_fixed Demo Model” on page 2-4

• “Generating HDL Code Using the Command Line Interface” on page 2-7

• “Generating HDL Code Using the GUI” on page 2-16

• “Simulating and Verifying Generated HDL Code” on page 2-34

Page 34

2 Intr oduction to HDL Code Generation

Before You Generate Code

The exercises in this introduction use a preconfigured demo model. All blocks in this demo m odel support HDL code generation, and the parameters of the model itself have been configured properly for HDL code generation.

After you complete the exercises, you will probably proceed to generating HDL code from your existing models, or newly constructed models. Before you generate HDL code from y our own mo de ls, you should do the following to ensure that your models are HDL code generation compatible:

• Use the

supported for HDL code generation, as described in “Supported Blocks Library” on page 9-28. By constructing models with blocks from this library, you can ensure HDL compatibility for all your models.

The set of supported blocks will change in future releases, so you should rebuild your supported blocks library each time you install a new version of this product.

• Use the Run Compatibility Checker option (described in “Selecting

and Checking a Subsystem for HDL Compatibility” on page 2-27) to check HDL compatibility of your model or DUT and g enerate an HDL Code Generation Check Report.

Alternatively, you can invoke the the compatibility checker.

• Before generating code, use the

Model Parameters with hdlsetup” on page 2-8) to set up your model for HDL code generation quickly and consistently.

hdllib utility to create a library of all blocks that are currently

checkhdl function (see checkhdl)torun

hdlsetup utility (described in “Init ializing

2-2

Page 35

Overview of Exercises

The coder supports HDL code ge neration in your choice of environments:

• The MATLAB Command Window supports code generation using the

makehdl, makehdltb, and other functions.

• The Simulink GUI (the Configuration Parameters dialog box and/or Model

Explorer) provides an integrated view of the model simulation parameters and HDL code generation parameters and functions.

The hands-on exercises in this chapter introduce you to the mechanics of generating and simulating HDL code, using the same model to generate code in both environments. In a series of steps, you will

• Configure a simple model for code generation.

• Generate VHDL code from a subsystem of the model.

• Generate a VHDL test bench and scripts for the Mentor Graphics ModelSim

simulator to drive a simulation of the model.

Overview of Exercises

• Compile and execute the model and test bench code in the simulator.

• Generate and simulate Verilog code from the same model.

• Check a model for compatibility with the coder.

2-3

Page 36

2 Intr oduction to HDL Code Generation

The sfir_fixed Demo Model

These exercises use the sfir_fixed demo model as a source model for HDL code generation. The model simulates a symmetric finite impulse response (FIR) filter algorithm, implemented with fixed-point arithmetic. The following figure shows the top level of the model.

2-4

This model employs a division of labor that is useful in HDL design:

• The

• The top-level model components that drive the subsystem work as a test

symmetric_fir subsystem, which implements the filter algorithm, is

the dev ice under tes t (DUT). An H DL entity will be generated, tested, and eventually synthesized from this subsystem.

bench.

Page 37

The sfir_fixed Demo Model

The top-level model generates 16-bit fixed-point input signals for the

symmetric_fir subsystem. The Signal From Workspace block generates a

test input (stimulus) signal for the filter. The four Constant blocks provide filter coefficients.

The Scope blocks are used in simulation only. They are virtual blocks, and do not generate any HDL code.

The following figure shows the

symmetric_fir subsystem.

Appropriate fixed-point data types propagate throughout the subsystem. Inputs inherit the data types of the signals presented to them. Where required, internal rules of the blocks determine the correct output data type, given the input data types and the operation performed (for example, the Productblocksoutput32-bitsignals).

2-5

Page 38

2 Intr oduction to HDL Code Generation

The filter outputs a 32-bit fixed-point result at the y_out port, and a lso replicates its input (after passing it through several delay stages) at the

delayed_x_out port.

In the exercises that follow, you generate VHDL code that implements the

symmetric_fir subsystemasanentity. Youthengenerateatestbench

from the top-level model. The test bench drives the generated entity, for the required number of clock steps, with stimulus data generated from the Signal From Workspace block.

2-6

Page 39

Generating HDL Code Using the Command Line Interface

In this section...

“Overview” on page 2-7

“Creating a Folder and Local Model File” on page 2-7

“Initializing M odel Parameters with hdlsetup” on page 2-8

“Generating a VHDL Entity from a Subsystem” on page 2-10

“Generating VHDL Test Bench Code” on page 2-12

“Verifying Generated Code” on page 2-13

“Generating a Verilog Module and Test Bench” on page 2-14

Overview

This exercise provides a step-by-step introduction to code and test bench generation commands, their arguments, and the files created by the code generator. The exercise assumes that you have familiarized yourself with the demomodel(see“Thesfir_fixedDemoModel”onpage2-4).

Creating a Folder and Local Model File

Make a local copy of the demo model and store it in a working folder, as follows.

1 Start the MATLAB software.

2 Create a folder named sl_hdlcoder_work, for example:

mkdir C:\work\sl_hdlcoder_work

The sl_hdlcoder_work folder will store a local copy of the demo model and to store folders and code g enerated by the coder. The location of the folder does not matter, except that it should not be within the MATLAB tree.

3 Make the sl_hdlcoder_work folder your working folder, for example:

cd C:\work\sl_hdlcoder_work

2-7

Page 40

2 Intr oduction to HDL Code Generation

4 To open the demo model, type the following command at the MATLAB

prompt:

demos

5 The Help window opens. In the Demos pane on the left, click the + for

Simulink.Thenclickthe

the list entry for the Symmetric FIR Filter Demo.

The

sfir_fixed model opens.

6 Select Save As from the Simulink File menu and save a local copy of

sfir_fixed.mdl. to your working folder.

7 Leave the sfir_fixed model open and proceed to the next section.

Initializing Model Parameters with hdlsetup

Before generating code, you must set some parameters of the model. Rather than doing this manually, use the command uses the set_param function to set up models for HDL code generation quickly and consistently.

+ for Simulink HDL Coder.Thendouble-click

hdlsetup command. The hdlsetup

2-8

To set the model parameters:

1 At the MATLAB comman d prompt, type

hdlsetup('sfir_fixed')

2 Select Save from the File menu, to save the model with its new settings.

Before continuing with code generation, consider the settings that

hdlsetup

applies to the model.

hdlsetup configures the Solver options that are recommended or required by

the coder. These are

• Type:

under limited conditions. See

Fixed-step. (The coder currently supports variable-step solvers

hdlsetup.)

Page 41

Generating HDL Code Using the Command Line Interface

• Solver: Discrete (no continuous states). Other fixed-step solvers

couldbeselected,butthisoptionisusually the correct one for simulating discrete systems.

• Tasking mode:

SingleTasking. The coder does not currently support

models that execute in multitasking mode.

Do not set Tasking mode to

hdlsetup also configures the m odel start and stop times and fixed-step size as

Auto.

follows:

• Start Time:

• Stop Time:

• Fixed step size (fundamental periodic sample time) :

0.0 s

10 s

auto

If Fixed step size is set to auto the step size is chosen automatically, based on the sample times specified in the model. In the demo m odel, only the Signal From Workspace block specifies an explicit sample time (1 s); all other blocks inherit this sample time.

The model start and stop times determine the total simulation time. This in turn determines the size of data arrays that are generated to provide stimulus and output data for generated test benches. For the d emo model, computation of 10 seconds of test data doesnottakeasignificantamountof time. Computation of sample values for more complex models can be time consuming. In such cases, you may want to decrease the total simulation time.

The remaining parameters set by

hdlsetup affect error severity levels, data

logging, and model display options. If you want to view the complete set of model parameters affected by

hdlsetup,openhdlsetup.m in the MATLAB

Editor.

The model parameter settings provided by

hdlsetup are intended as useful

defaults, but they may not be appropriate for all your applications. For example, simulation time of 1000 s would be more realistic for a test of the

hdlsetup sets a default Simulation stop time of 10 s. A total

sfir_fixed

demo model. If you would like to ch ange the simulation time, enter the desired value into the Simulation stop time field of the Simulink window.

2-9

Page 42

2 Intr oduction to HDL Code Generation

See the “Model Parameters” table in the “Model and Block Parameters” section of the Simulink documentation for a summary of user-settable model parameters.

Generating a VHDL Entity from a S ubsystem

In this section, you will use the makehdl function to generate code for a VHDL entity from the generates script files for third-party HDL simulation and synthesis tools.

makehdl lets you specify num erous properties that control various features

of the generated code. In this exam ple, you will use defaults for all properties.

Before generating code, make sure that you have completed the steps described in “Creating a Folde r and Local Model File” on page 2-7 and “Initializing Model Parameters with hdlsetup” on page 2-8.

To generate code:

symmetric_fir subsystem of the demo model. makehdl also

makehdl

2-10

1 Select Current Folder from the Desktop menu in the MATLAB window.

This dis play s the MATLAB Current Folder browser, which lets you easily access your working folder and the files that will be generated within it.

2 At the MATLAB prompt, type the command

makehdl('sfir_fixed/symmetric_fir')

This comm and directs the coder to generate code from the symmetric_fir subsystem within the sfir_fixed model, using default values for all properties.

3 As code generation proceeds, the coder displays progress messages. The

process should complete successfully with the message

### HDL Code Generation Complete.

Observe that the names of generated files in the progress messages are hyperlinked. After code generation completes, you can click these hyperlinks to view the files in the MATLAB Editor.

Page 43

Generating HDL Code Using the Command Line Interface

makehdl compiles the model before generating code. Depending on model

display options (such as port data types, etc.), the appearance of the model may change after code generation.

4 By default, makehdl generates V HDL code. Code files and scripts are

written to a target folder. The default targe t folder is a subfolder of your working folder, named

hdlsrc.

A folder icon for the browser. To view generated code and script files, double-click the

hdlsrc folder is now visible in the Current Folder

hdlsrc

folder icon.

5 The files that makehdl has generated in the hdlsrc folder are

symmetric_fir.vhd: VHDL code. This file contains an entity definition

•

and RTL architecture implementing the

symmetric_fir_compile.do: Mentor Graphics Mod elSim compilation

•

script (

symmetric_fir_synplify.tcl: Synplify synthesis script

•

symmetric_fir_map.txt: M apping file. This report file maps generated

•

vcom command) to compile the generated VHDL code.

symmetric_fir filter.

entities (or modules) to the subsystems that generated them (see “Code Tracing Using the Mapping File” on page 9-30).

6 To view the generated VHDL code in the MATLAB Editor, double-click the

symmetric_fir.vhd file icon in the Current Fo lder browser.

At this point it is suggested that you study the

ENTITY and ARCHITECTURE

definitions while referring to “HDL Code Generation Defaults” on page 18-23 in the

makehdl reference documentation. The reference

documentation describes the default naming conventions and correspondences between the elements of a model (subsystems, ports, signals, etc.) and elements of generated HDL code.

7 Before proceeding to the next section , close any files you have opened in

the editor. Then, click the Go Up One Level button in the Current Folder browser, to set the current folder back to your

8 Leave the sfir_fixed model open and proceed to the next section.

sl_hdlcoder_work folder.

2-11

Page 44

2 Intr oduction to HDL Code Generation

Generating VHDL

In this section, generate a VHDL t the operation o section. A gene

• Stimulus data

test.

• Output data g

this data is c purposes.

• Clock, rese

• A component

• Code to dri

data.

In additi compile a

This exe the prev previou

on,

rcise assumes that your working folder is the same as that used in ious section. This folder now contains an

sly generated code.

you use the test bench generation function,

est bench. The test bench is designed to drive and verify

fthe

symmetric_fir entity that was generated in the previous

rated test bench includes

generated by signal sources connected to the entity under

enerated by the entity under test. During a test bench run,

ompared to the outputs of the VHDL model, for verification

t, and clock enable inputs to drive the entity under test.

instantiation of the entity under test.

ve the entity under test and compare its outputs to the expected

makehdltb generates Mentor Graphics ModelSim scripts to

nd execute the test bench.

Test Bench Code

makehdltb,to

hdlsrc folder containing the

2-12

To gene

1 At the

2 As test bench generation proceeds, the coder displays progress messages.

rate a test bench:

MATLAB prompt, type the com mand

makehdltb('sfir_fixed/symmetric_fir')

command generates a test bench that is designed to interface to and

This

date code generated from

vali

tionally identical interface). By default, VHDL test bench code, as well

func

ripts, are generated in the

as sc

The process should complete successfully with the message

### HDL TestBench Generation Complete.

symmetric_fir (orfromasubsystemwitha

hdlsrc target folder.

Page 45

Generating HDL Code Using the Command Line Interface

3 To view generated test bench and script files, double-click the hdlsrc

folder icon in the Current Folder browser. Alternatively, you can click the hyperlinked names of generated files in the code te st bench generation progress messages.

The files generated by

symmetric_fir_tb.vhd: VHDL test bench code and generated test and

•

makehdltb are:

output data.

•

symmetric_fir_tb_compile.do: Mentor Graphics ModelSim

compilation script ( theentitytobetested( (

symmetric_fir_tb.vhd).

symmetric_fir_tb_sim.do: Mentor Graphics ModelSim script to

•

vcom comm ands). This script compiles and loads both

symmetric_fir.vhd) and the test bench code

initialize the simulator, set up wave windo w signal displays, and run a simulation.

4 If you want to view the generated test bench code in the MATLAB Editor,

double-click the browser. You may want to study the code while referring to the

symmetric_fir.vhd file icon in the Current Folder

makehdltb

reference documentation, which describes the default actions of the test bench generator.

5 Before proceeding to the next section , close any files you have opened in

the editor. Then, click the Go Up One Level button in the Current Folder browser, to set the current folder back to your

sl_hdlcoder_work folder.

Verifying Generated Code

You can now take the previously generated code and test bench to an HDL simulator for simulated execution and verification of results. See “Simulating and Verifying Generated HDL Code” on page 2-34 for an example of how to use generated test bench and script files with the Mentor Graphics ModelSim simulator.

2-13

Page 46

2 Intr oduction to HDL Code Generation

Generating a Ver

The procedures f generating VHDL syntax and the g

or generating Verilog code differ only slightly from those for

code. This section provides an overview of the command

enerated files.

ilog Module and Test Bench

Generating a Verilog Module

By default, ma generate Ver setting the

makehdl('s

The previous command generates Verilog source code, as well as scripts for the simulation and the synthesis tools, in the default target folder,

The files generated by this example command are:

•

symmetric_fir.v: Verilog code. This file contains a Verilog module

implementing the

symmetric_fir_compile.do: Mentor Graphics ModelSim compilation

•

script (

symmetric_fir_synplify.tcl: Synplify synthesis script.

•

kehdl

ilog code, you must pass in a property/value pair to

argetLanguage

vlog command) to compile the generated Verilog code.

generates VHDL code. To override the default and

makehdl,

property to 'verilog',asinthisexample.

fir_fixed/symmetric_fir','TargetLanguage','verilog')

hdlsrc.

symmetric_fir subsystem.

2-14

symmetric_fir_map.txt.: Mapping file. This report file maps generated

•

entities (or modules) to the subsystems that generated them (see “Code Tracing Using the Mapping File” on page 9-30).

Gener

The makehdltb syntaxforoverridingthetargetlanguageisexactlythesame as that for to drive the Verilog module,

The files generated by this example command are

ating and Executing a Verilog Test Bench

makehdl. The following example generates Verilog test bench code

symmetric_fir, in the default target folder.

makehdltb('sfir_fixed/symmetric_fir','TargetLanguage','verilog')

Page 47

Generating HDL Code Using the Command Line Interface

• symmetric_fir_tb.v: Verilog test bench code and generated test and

output data.

•

symmetric_fir_tb_compile.do: Mentor Graphics ModelSim compilation

script ( tested (

symmetric_fir_tb_sim.do: Mentor Graphics ModelSim script to initialize

•

vlog commands). This script compiles and loads both the entity to b e

symmetric_fir.v) and the test bench code (symmetric_fir_tb.v).

the simulator, set up wave window signal displays, and run a simulation.

The following listing shows the commands and responses from a test bench session using the generated scripts:

ModelSim>vlib work

ModelSim> do symmetric_fir_tb_compile.do

# Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004

# -- Compiling module symmetric_fir

# Top level modules:

# symmetric_fir

# Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004

# -- Compiling module symmetric_fir_tb

# Top level modules:

# symmetric_fir_tb

ModelSim>do symmetric_fir_tb_sim.do

# vsim work.symmetric_fir_tb

# Loading work.symmetric_fir_tb

# Loading work.symmetric_fir

# **** Test Complete. ****

# Break at

C:/work/sl_hdlcoder_work/vlog_code/symmetric_fir_tb.v line 142

# Simulation Breakpoint:Break at

C:/work/sl_hdlcoder_work/vlog_code/symmetric_fir_tb.v line 142

# MACRO ./symmetric_fir_tb_sim.do PAUSED at line 14

2-15

Page 48

2 Intr oduction to HDL Code Generation

Generating HDL Code Using the GUI

In this section...

“Simulink®HDL Coder GUI Overview” on page 2-16

“Creating a Folder and Local Model File” on page 2-19

“Viewing Coder Options in the Configuration Parameters Dialog Box” on page 2-20

“Creating a Control File” on page 2-22

“Initializing M odel Parameters with hdlsetup” on page 2-25

“Selecting and Checking a Subsystem for HDL Compatibility” on page 2-27

“Generating VHDL C ode” on page 2-29

“Generating VHDL Test Bench Code” on page 2-32

“Verifying Generated Code” on page 2-33

“Generating Verilog Model and Test Bench Code” on page 2-33

2-16

Simulink HDL Coder GUI Over view

You can view and edit options and parameters that affect HDL code generation in the Configuration Param eters dialog box , or in the Model Explorer.

The following figure shows the top-level HDL Coder options pane as displayed in the Configuration Parameters dialog box.

Page 49

Generating HDL Code Using the GUI

The following figure shows the top-level HDL Coder options pane as displayed in the Model Explorer.

2-17

Page 50

2 Intr oduction to HDL Code Generation

2-18

If you are not familiar w ith Simulink configuration sets and how to view and edit them in the Configuration Parameters dialog box, see the following documentation:

• “Setting Up Configuration Sets”

• “Configuration Parameters Dialog Box”

If you are not familiar with the Model Explorer, see “Exploring, Searching, and Browsing Models”.

Page 51

Generating HDL Code Using the GUI

In the hands-on code generation exercises that follow, you will use the Configuration Parameters dialog box to view and set the coder options and controls. The exercises use the

sfir_fixed demo model (see “The sfir_fixed

Demo Model” on page 2-4) in basic code generation and verification ste ps.

Creating a Folder and Local Model File

In this section you will setup the folder and a local copy of the demo model.

Creating a Folder

Start by setting up a working folder:

1 Start the MATLAB software.

2 Create a folder named sl_hdlcoder_work, for example:

mkdir C:\work\sl_hdlcoder_work

You will use sl_hdlcoder_work to store a local copy of the demo model and to store folders and code generated by the coder. The location of the folder does not matter, except that it should not be within the MATLAB folder tree.

3 Make the sl_hdlcoder_work folder your working folder, for example:

cd C:\work\sl_hdlcoder_work

Making a Local Copy of the Model File

Next, make a copy of the sfir_fixed demo model:

1 To open the demo model, type the following command at the MATLAB

prompt:

demos

The Help window opens.

2-19

Page 52

2 Intr oduction to HDL Code Generation

2 In the Demos pane on the left, click the + for Simulink.Thenclickthe

+ for Simulink HDL Coder. Then double-click the list entry f or the

Symmetric FIR Filter demo.

The

sfir_fixed model opens.

3 Select Save As from the File menu and save a local copy o f

sfir_fixed.mdl to your working folder.

4 Leave the sfir_fixed model open and proceed to the next section.

Viewing Coder Options in the Configuration Parameters Dialog Box

The coder option settings are displayed as a category of the m odel’s active configuration set. You can view and edit these options in the Configuration Parameters dialog box, or in the Model Explorer. This discussion uses the Configuration Parameters dialog box.

To access the coder settings:

2-20

1 Select Configuration Parameters from the Simulation menu in the

sfir_fixed model window.

The Configuration Parameters dialog box opens with the Solver options pane displayed, as shown in the following figure.

Page 53

Generating HDL Code Using the GUI

2 Observe that the Select tree in the left pane of the dialog box includes

an HDL Coder category, as shown.

3 Click the HDL Coder category in the Select tree. The HDL Coder pane

is displayed, as shown in the following figure.

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2 Intr oduction to HDL Code Generation

2-22

The HDL Coder pane contains top-level options and buttons that control the HDL code generation process. Several other catego rie s of options are available under the HDL Coder entry in the Select tree. This exercise uses a small subset of these options, leaving the others at their default settings.

Chapter 3, “Code Generation Options in the Simulink summarizes all the options available in the HDL Coder category.

HDL Coder GUI”

Creating a Control File

Code generation control files (referred to in this document as control files)let you

Page 55

Generating HDL Code Using the GUI

• Save your model’s HDL code generation op tio ns .

• Extend the HDL code generation process and direct its details.

You attach a control file to your model using either the

makehdl command

or the Configuration Parameters dialog box. In this tutorial, you will use a controlfiletosaveHDLcode generation options. This is a required step with most models, because HDL code generation settings are not saved in the

.mdl file like other components of a model’s configuration set. If you want

your HDL code generation settings to persist across sessions with a model, you must save your current settings to a control file. The control file is then linked to the model, and the linkage is preserved when you save the model.

When a control file is linked to a model, the control file name is displayed in the File name field of the top-level HDL Coder options pane. The

sfir_fixed demo model is attached to the control file sfir_fixed_control.m.

This control file is stored within the MATLAB demo folders and should not be overw ritten. For use in this tutorial, you will save the current HDL code generation options to a new control file in the working folder. Later in the tutorial, you will change some options and save them to the control file.

2-23

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2 Intr oduction to HDL Code Generation

2-24

TosavethecurrentHDLcodegeneration options to a new control file:

1 Open the Configuration Parameters dialog box and select the HDL Coder

options pane.

2 Under Cod e generation control file,clicktheSave button. A standard

file dialog box opens.

3 Navigate to your current w orking folder and save the file as

sfir_fixed_control.m.

4 Select Save from th e File menu. When you save the model, the control file

linkage information is written to the

.mdl file, and the control file linkage

persists in futu re sessions with your m od el .

Page 57

Generating HDL Code Using the GUI

This tutorial uses a control file only as a mechanism for saving HDL code generation settings. This simple a pp l ica t ion of a control file does not req u ire knowledge of any internal details about the file. You can also use a control file to direct or customize many details of the code generation process. It is strongly recommended that you read Chapter 5, “Code Generation Control Files”, after completing this tutorial.

Initializing Model Parameters with hdlsetup

To set the model parameters:

1 At the MATLAB comman d prompt, type

hdlsetup('sfir_fixed')

hdlsetup command. The hdlsetup

2 Select Save from the File menu, to save the model with its new settings.

You do not need to update the control file at this point, because

hdlsetup

modifies only the model parameters, not the HDL code generation options.

Before continuing with code generation, consider the settings that

hdlsetup

applies to the model.

hdlsetup configures Solver options that are recommended or required by

the coder. These are

• Type:

under limited conditions. See

• Solver:

Fixed-step. (The coder currently supports variable-step solvers

hdlsetup.)

Discrete (no continuous states). Other fixed-step solvers

couldbeselected,butthisoptionisusually the correct one for simulating discrete systems.

• Tasking mode:

SingleTasking. The coder does not currently support

models that execute in multitasking mode.

Do not set Tasking mode to

Auto.

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2 Intr oduction to HDL Code Generation

hdlsetup also configures the m odel start and stop times and fixed-step size as

follows:

• Start Time:

• Stop Time:

• Fixed step size (fundamental periodic sample tim e):

0.0 s

10 s

auto

The remaining parameters set by

hdlsetup affect error severity levels, data

logging, and model display options. If you want to view the complete set of model parameters affected by

hdlsetup,openhdlsetup.m in the MATLAB

Editor.

The model parameter settings provided by

hdlsetup are intended as useful

defaults, but they may not be appropriate for all your applications. For example, simulation time of 1000 s would be more realistic for a test of the

hdlsetup sets a default Simulation stop time of 10 s. A total

sfir_fixed

demo model. If you would like to ch ange the simulation time, enter the desired value into the Simulation stop time field of the Simulink window.

2-26

See the “Model Parameters” table in the “Model and Block Parameters” section of the Simulink documentation for a summary of user-settable model parameters.

Page 59

Generating HDL Code Using the GUI

Selecting and Checking a S ubsystem for HDL Compatibility

The coder generates code from either the current model or from a subsystem at the root level of the current model. You use the Generate HDL for menu to select the model or subsystem from which code is to be generated. Each entry in the menu shows the full path to the model or one of its subcomponents.

The

sfir_fixed demo model is configured with the sfixed_fir/symmetric_fir

subsystem selected for code generation. If this is not the case, make sure that the

symmetric_fir subsystem is selected for code generation, as follows:

1 Select sfixed_fir/symmetric_fir from the Generate HDL for menu.

2 Click Apply. The dialog box should now appear as shown in the following

figure.

2-27

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2 Intr oduction to HDL Code Generation

2-28

To check HDL compatibility for the subsystem:

1 Click the Run Compatibility Checker button.

2 The HDL compatibility checker examines the system selected in the

Generate HDL for menu for any compatibility problems. In this case, the selected subs ystem is fully HDL-compatible, a nd the compatibility checker displays the following message:

### Starting HDL Check. ### HDL Check Complete with 0 errors, warnings and messages.

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Generating HDL Code Using the GUI

3 The compatibility checker also displays an HTML report in a Web browser,

asshowninthefollowingfigure.

Generating VHDL Code

The top-level HDL Coder options are now set as fo llow s:

• The Generate HDL for field specifies the

sfixed_fir/symmetric_fir

subsystem for code generation.

• The Language field specifies (by default) generation of VHDL code.

• The Folder field specifies a target folder that stores generated code files

and scripts. The default target folder is a subfolder of your working folder, named

hdlsrc.

The following figure shows these settings.

2-29

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2 Intr oduction to HDL Code Generation

2-30

Before generating code, select Current Folder from the Desktop menu in the M ATLAB window. This displays the Current Folder browser, which lets you access your working folder and the files that will be generated within it.

To generate code:

1 Click the Generate button.

2 As code generation proceeds, the coder displays progress messages. The

process should complete successfully with the message

### HDL Code Generation Complete.

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Generating HDL Code Using the GUI

Observe that the names of generated files in the progress messages are hyperlinked. After code generation completes, you can click these hyperlinks to view the files in the MATLAB Editor.

The coder compiles the model befo re generating code. Depending on model display options (such as port data types, etc.), the appearance of the model may change after code generation.

3 A folder icon for the hdlsrc folder is now visible in the Current Folder

browser. To view generated code and script files, double-click the

hdlsrc

folder icon.

4 The files that were generated in the hdlsrc folder are

symmetric_fir.vhd: VHDL code. This file contains an entity definition

•

and RTL architecture implementing the

symmetric_fir_compile.do: Mentor Graphics Mod elSim compilation

•

script (

symmetric_fir_synplify.tcl: Synplify synthesis script.

•

vcom command) to compile the generated VHDL code.

symmetric_fir filter.

symmetric_fir_map.txt: M apping file. This report file maps generated

•

entities (or modules) to the subsystems that generated them (see “Code Tracing Using the Mapping File” on page 9-30).

5 To view the generated VHDL code in the MATLAB Editor, double-click the

symmetric_fir.vhd file icon in the Current Fo lder browser.

At this point it is suggested that you study the

ENTITY and ARCHITECTURE

definitions while referring to “HDL Code Generation Defaults” on page 18-23 in the

makehdl reference documentation. The reference

documentation describes the default naming conventions and correspondences between the elements of a model (subsystems, ports, signals, etc.) and elements of generated HDL code.

6 Before proceeding to the next section , close any files you have opened in

the editor. Then, click the Go Up One Level button in the Current Folder browser, to set the current folder back to your

sl_hdlcoder_work folder.

2-31

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2 Intr oduction to HDL Code Generation

Generating VHDL

At this point, th set as they were i VHDL test bench

sfixed_fir/sy

target folder

To generate a V

1 Click the Tes

Test Bench pa

e Generate HDL for, Language,andFolder fields are

n the previous section. Accordingly, you can now generate

code to drive the VHDL code generated p reviously for the

mmetric_fir

as before.

HDL test b ench:

tBenchentry in the HDL Coder list in the Select tree. The

ne is displayed, as shown in the following figure.

Test Bench Code

subsystem.Thecodewillbewrittentothesame

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Generating HDL Code Using the GUI

2 Select the HDL test bench option.

3 Click the Generate Test bench button.

4 As test bench generation proceeds, the coder displays progress messages.

The process should complete successfully with the message

### HDL TestBench Generation Complete.

5 The files that were generated in the hdlsrc folder are

symmetric_fir_tb.vhd: VHDL test bench code and generated test and

•

output data.

•

symmetric_fir_tb_compile.do: Mentor Graphics ModelSim

compilation script ( theentitytobetested( (

symmetric_fir_tb.vhd).

symmetric_fir_tb_sim.do: Mentor Graphics ModelSim script to

•

vcom comm ands). This script compiles and loads both

symmetric_fir.vhd) and the test bench code

initialize the simulator, set up wave windo w signal displays, and run a simulation.

Verifying Generated Code

You can now take the generated code and test bench to an HDL simulator for simulated execution and verification of results. See “Simulating and Verifying Generated HDL Code” on pag e 2-34 for an example of how to use generated test bench and script files with the Mentor Graphics ModelSim simulator.

Generating Verilog Model and Test Bench Code

The procedure for generating Verilog code is the same as for generating VHDL code (see “Generating a VHDL Entity from a Subsystem” on page 2-10 and “Generating VH D L Test Bench Code” on page 2-12), except that you should select as shown in the following figure.

Verilog from the Language field of the HDL Coder options,

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2 Intr oduction to HDL Code Generation

Simulating and Verifying Generated HDL Code

Note This section requires the use of the Mentor Graphics ModelSim

simulator.

This section assumes that you have generated code from the sfir_fixed demo model as described in either of the following exercises:

• “Generating HDL Code Using the Command Line Interface” on page 2-7

• “Generating HDL Code Using the GUI” on page 2-16

In this section you compile and run a simulation of the previous generated model a nd test bench code. The scripts generate d by the coder let you do this with just a few simple commands. The procedure is the same, whether you generated code in the command line environment or in the GUI.

To run the simulation:

2-34

1 Start the Mentor Graphics ModelSim software.

2 Set the working folder to the folder in which you previously g enerated code.

ModelSim>cd C:/work/sl_hdlcoder_work/hdlsrc

3 Use the generated compilation script to compile and load the generated

model and text bench code. The following listing shows the command and responses.

ModelSim>do symmetric_fir_tb_compile.do

# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004

# -- Loading package standard

# -- Loading package std_logic_1164

# -- Loading package numeric_std

# -- Compiling entity symmetric_fir

# -- Compiling architecture rtl of symmetric_fir

# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004

# -- Loading package standard

# -- Loading package std_logic_1164

Page 67

Simulating and Verifying Generated HDL Code

# -- Loading package numeric_std

# -- Compiling package symmetric_fir_tb_pkg

# -- Compiling package body symmetric_fir_tb_pkg

# -- Loading package symmetric_fir_tb_pkg

# -- Compiling entity symmetric_fir_tb

# -- Compiling architecture rtl of symmetric_fir_tb

# -- Loading entity symmetric_fir

4 Use the generated simulation script to execute the simulation. The

following listing shows the command and responses. The warning mes sag es are benign.

ModelSim>do symmetric_fir_tb_sim.do

# vsim work.symmetric_fir_tb

# Loading C:\Applications\ModelTech_6_0\win32/../std.standard

# Loading C:\Applications\ModelTech_6_0\win32/../ieee.std_logic_1164(body)

# Loading C:\Applications\ModelTech_6_0\win32/../ieee.numeric_std(body)

# Loading work.symmetric_fir_tb_pkg(body)

# Loading work.symmetric_fir_tb(rtl)

# Loading work.symmetric_fir(rtl)

# ** Warning: NUMERIC_STD."<": metavalue detected, returning FALSE

# Time: 0 ns Iteration: 0 Instance: /symmetric_fir_tb

# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

# Time: 0 ns Iteration: 1 Instance: /symmetric_fir_tb

# ** Note: **************TEST COMPLETED **************

# Time: 140 ns Iteration: 1 Instance: /symmetric_fir_tb

The test bench termination message indicates that the simulation has run to completion successfully, without any comparison errors.

# ** Note: **************TEST COMPLETED **************

5 The simulation script displays all inputs and outputs in the model

(including the reference signals

y_out_ref and delayed_x_out_ref)inthe

Mentor Graphics ModelSim wave window. Th e following figure shows the signals displayed in the wave window.

2-35

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2 Intr oduction to HDL Code Generation

6 Exit the Mentor Graphics ModelSim simul ator when you finish vie wi ng

signals.

2-36

7 Close any files you have opened in the MATLAB Editor. Then, click the Go

Up One Level button in the Current Folder browser, to set the current

folder back to your

sl_hdlcoder_work folder.

Page 69

Code Generation Options in the Simulink HDL Coder GUI

• “Viewing and Setting HDL Coder Options” on page 3-2

• “HDL Coder Pane: General” on page 3-8

• “HDL Coder Pane: Global Settings” on page 3-17

• “HDL Coder Pane: Test Bench” on page 3-56

• “HDL Coder Pane: EDA Tool Scripts” on page 3-83

Page 70

3 C ode Generation Options in the Simulink

HDL Coder™ GUI

Viewing and Setting HDL Coder Options

In this section...

“HDL Coder O ptions in the Configuration Parameters Dialog Box” on page 3-2

“HDL Coder Options in the Model Explorer” on page 3-4

“HDL Coder Menu” on page 3-5

HDL Coder Options in the Configuration Parameters Dialog Box

The following figure shows the top-level HDL Coder pane as displayed in the Configuration Parameters dialog box. To open this dialog box, select Simulation > Configuration Parameters in the Simul ink window. Then select HDL Coder from the list on the left.

3-2

Page 71

Viewing and Setting HDL Coder Options

If you are not familiar with Simu l in k configuration sets and how to view a n d edit them in the Configuration Parameters dialog box, see the “Setting Up Configuration Sets” and “Configuration Parameters Dialog Box” sections of the Simulink documentation.

Note When the HDL Coder pane of the Configuration Parameters dialog box is displayed, clicking the Help button displays general help fo r the Configuration Parameters dialog box.

3-3

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3 C ode Generation Options in the Simulink

HDL Coder™ GUI

HDL Coder Option

The following fi Dialog pane of th

To view this dia

1 Select View > M

2 Select your model’s active configuration set in the Model Hierarchy tree

on the left.

3 Select HDL Coder from the list in the Contents pane.

gure shows the top-level HDL Coder pane as displayed in the

e Model Explorer.

log box:

odel Explorer in the Simulink window.

s in the Model Explorer

3-4

Page 73

Viewing and Setting HDL Coder Options

When the HDL Coder pane is selected in the Model Explorer, clicking the Help button displays the documentation specific to the current tab.

If you are not familiar with the Model Explorer, see “Exploring, Searching, and Browsing Models”.

HDL Coder Menu

The HDL Coder submenu of the Tools menu (see the following figure) provides shortcuts to the HDL code generation options. You can also use this menu to initiate code generation.

3-5

Page 74

3 C ode Generation Options in the Simulink

HDL Coder™ GUI

3-6

The HDL C

• HDL Wor

(seeCh

• Optio

dialo

• Gener

butt

• Gene

the G box o

el of the current model in the Generate HDL for menu, the Generate

lev

Tes

oder submenu options are:

kflow Advisor...: Open the HDL Workf low Advisor GUI

apter 14, “Using the HDL Workflow Advisor” ).

ns:OpentheHDL Coder pane in the Configuration Parameters

gbox.

ate HDL: Initiate HDL code generation; equivalent to the Generate

on in the Configuration Parameters dialog box or Model Explorer.

rate Test Bench: Initiate test bench code generation; equivalent to enerate Test Bench button in the Configuration Parameters dialog

r Model Explorer. If you do not select a subsystem from the top (root)

tBenchmenu option is disabled.

Page 75

Viewing and Setting HDL Coder Options

• Add HDL Configuration to Model or Remove HDL Configuration

from Model:TheHDL configuration component is an internal data

structure that the coder creates and attaches to a model. This component lets you view the HDL Coder pane in the Configurations Parameters GUI, and use the HDL Coder pane to set HDL code generation options. In certain circumstances, you may need to add or remove the HDL Coder configuration component to or from a model. Use this option to add or remove the component. See “Adding and Removing the HDL Configuration Component” on page 9-33for further information.

3-7

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3 C ode Generation Options in the Simulink

HDL Coder Pane: General

HDL Coder™ GUI

3-8

In this section...

“HDL Coder Top-Level Pane Overview” on page 3-9

“File name” on page 3-10

“Generate HDL for” on page 3-11

“Language” on page 3-12

“Folder” on page 3-13

“Code Generation Output” on page 3-14

“Generate traceability report” on page 3-15

“Include requirements in block comments” on page 3-16

Page 77

HDL Coder Pane: General

HDL Coder Top-Le

The top-level HD and compatibili of code generat

LCoderpane contains buttons that initiate code generation

ty checking, and sets parameters that affect overall operation

ion.

vel Pane Overview

Buttons in the HDL Coder Top-Level Pane

The b uttons in code generat

Generate: Initiates code generation for the system selected in the Generate HDL for menu. See also

Run Compati

examine the compatibil Browse: Letsyounavigatetoandselectthetargetfoldertowhich generated code and script files are written. The path to the target folder is entered into the Folder field.

Load: Opens a standard file selection dialog box so that you can navigate to and select a control file and load it into memory. See also Using Control Files in the Code Generation Process.

Save: Op HDL code Control Restore Factory Defaults: Clears the File Name field and unlinks the current control file from the model. See also Using Control Files in the Code Generation Process.

the HDL Coder pane perform important functions related to

ion and control file linkage and maintenance. These buttons are:

makehdl.

bility Checker: Invokes the compatibility checker to

system selected in the Generate HDL for menu for any

ity problems. See also

ens a standard file save dialog box so that you can save current

generation settings to a specified control file. See also Using

Files in the Code Generation Process

checkhdl.

3-9

Page 78

3 C ode Generation Options in the Simulink

File name

Displays the fil is a display-onl

Settings

Default: No co

HDL Coder™ GUI

e name of the currently selected control file (if any). This y field.

ntrolfilenamedisplayed.

• To select a co

select it. Th

• To clear the F

Restore Fac

ntrol file, click Load, navigate to the desired control file, and

e File Name field displays the name of the selected file.

ile Name field and unlink the current control file, click the

tory Defaults button.

Command-Line Information

Property: Type: string Value: Pass in a cell array containing a string that specifies a control file

to be attached to the current model.

Default:

HDLControlFiles

No control file is specified.

Generate HDL for

Select the subsystem or model from which code is generated. The list includes the path to the root model and to all root-level subsystems in the model.

Settings

Default: The root model is selected.

Command-Line Information

Pass in the path to the model or subsystem for w hich code is to be generated as the first argument to

Language

Select the language (VHD L or Verilog) in which code is generated. The selected language is referred to as the target language.

Settings

Default: VHDL

VHDL

Generate VHDL code.

Verilog

Generate Verilog code.

Command-Line Information

Property: TargetLanguage Type: string Value: Default: 'VHDL'

'VHDL' | 'Verilog'

HDL Coder™ GUI

3-12

Folder

Enter a path to th Browse to naviga to as the target

Settings

Default: The d named

hdlsrc

Command-Line Information

e folder into which code is generated. Alternatively, click te to and select a folder. The selected folder is referred

folder.

efault target fo lder is a subfolder of your working folder,

HDL Coder Pane: General

Property: T Type: string Value: A valid path to your target folder Default:

argetDirectory

hdlsrc'

Settings

Default: Gene

• Generate HDL

generated mo

• Display gene

generating

• Generate HD

generated

rate HDL code

code: Generate HDL code without displaying the

del.

rated model only: Display the generated model without

HDL code.

L Code and display generated model:Displaythe

model after HDL code generation completes.

Command-Line Information

Property Type: string Value:

'GenerateHDLCodeAndDisplayGeneratedModel' | 'DisplayGeneratedModelOnly'

Default

CodeGenerationOutput

'GenerateHDLCode' |

'GenerateHDLCode'

3-14

Settings

Default: Off

Create and display an HTML code generation report. See

Using a Code Generation Report

Off

Do not create an HTML code generation report.

Command-Line Information

Property: Traceability Type: string Value: Default: 'off'

'on' | 'off'

Settings

Default: On

If the model contains requirements com ments, include them as comments in code or code generation reports.See “Requirements Comments and Hyperlinks” on page 9-20.

Off

Do not include requirements as comments in code or code generation reports.

Command-Line Information

Property: RequirementComments Type: string

on'

| 'off'

Value: Default: 'on'

3-16

HDL Coder Pane: Global Settings

In this section...

“Global Settings Overview” on page 3-19

“Reset type” on page 3-20

“Reset asserted level” on page 3-21

“Clock input port” on page 3-22

“Clock enable input port” on page 3-23

“Oversampling factor” on page 3-24

“Reset input port” on page 3-25

“Comment in header” on page 3-26

“Verilog file extension” on page 3-27

“VHDL file extension” on page 3-28

“Entity conflict postfix” on page 3-29

“Package postfix” on page 3-30

3-17

Page 86

3 C ode Generation Options in the Simulink

In this section...

“Reserved word p ostfix ” on page 3-31

“Split entity and architecture” on page 3-32

“Split entity file postfix” on page 3-34

“Split arch file postfix” on page 3-35

“Clocked process postfix” on page 3-36

“Enable prefix” on page 3-37

“Pipeline postfix” on page 3-3 8

“Complex real part postfix” on page 3-39

“Complex imaginary part postfix” on page 3-40

“Input data type” on page 3-41

“Output data type” on page 3-42

“Clock enable output port” on page 3-44

HDL Coder™ GUI

3-18

“Represent constant values by aggregates” on page 3-45

“Use "rising_edge" for registers” on page 3-46

“Loop unrolling” on page 3-47

“Cast before sum” on page 3-48

“Use Verilog `timescale directives” on page 3-49

“Inline VHDL configuration” on page 3-50

“Concatenate type safe zeros” on page 3-51

“Optimize timing controller” on page 3-52

“Minimize clock enables” on page 3-54

Page 87

HDL Coder Pane: Global Settings

Global Settings

The Global Setti characteristic whether certai

ngs pane lets you set options to specify detailed

s of the generated code, such as HDL element naming and

n optimizations are applied.

Overview

3-19

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3 C ode Generation Options in the Simulink

Reset type

Specify whether to use asynchronous or synchronous reset logic when generating HDL code for registers.

Settings

Default: Asynchronous

Asynchronous

Use asynchronous reset logic.

Synchronous

Use synchronous reset logic.

Command-Line Information

Property: ResetType Type: string Value: Default: 'async'

'async' | 'sync'

HDL Coder™ GUI

3-20

Settings

Default: Acti

Active-high

Asserted (ac

Active-low

Asserted (a

ve-high

tive) leve l of reset input signal is active-high (

ctive) level of reset input signal is active-low (

Command-Line Information

Property: Type: string Value: Default:

ResetAssertedLevel

'active-high' | 'active-low'

'active-high'

Clock input port

Specify the name

Settings

Default: clk

HDL Coder™ GUI

for the clock input port in generated HDL code.

Enter a string code. If you s generator ap Verilog iden resulting n

valuetobeusedastheclocksignalnameingeneratedHDL

pecify a string that is a VHDL or Verilog reserved word, the code

pends a reserved word postfix string to form a valid V HDL or

tifier. For example, if you specify the reserved word

ame string would be

signal_rsvd.

Command-Line Information

Property: Type: string Value: Any identifier that is legal in the target language Default:

ClockInputPort

'clk'

Settings

Default: clk_

Enter a string generated HD reserved wor to form a vali reserved wo

enable

value to be used as the clock enable input port name in

L code. If you specify a string that is a VHDL or Verilog

d, the code generator appends a reserved word postfix string

d VHDL or Verilog identifier. For example, if you specify the

signal, the resulting name string would be signal_rsvd.

Tip

The clock e value must

nable input signal is asserted active-high (1). Thus, the input

be high for the generated entity’s registers to be updated.

Command-Line Information

Property Type: string Value: Any identifier that is legal in the target language Default

ClockEnableInputPort

'clk_enable'

Oversampling factor

Specify frequency of global oversampling clock as a multiple of the model’s base rate.

Settings

Default: 1

Oversampling factor specifies the oversampling factor of a global

oversampling clock. The oversampling factor expresses the desired rate of the global oversampling clock as a multiple of your model’s base rate.

When you specify the Oversampling factor for a global oversampling clock, note these requirements:

• The oversampling factor must be an integer greater than or equal to 1.

• The default value is 1. In the default case, the coder does no t generate a

global oversampling clock is generated.

HDL Coder™ GUI

3-24

• In a multirate DUT, all other rates in the DUT must divide evenly into

the global oversampling rate.

Command-Line Information

Property: Oversampling Type: int Value: integer greater than or equal to 1 Default:

Reset input port

Enter the name for the reset input port in generated HDL code.

Settings

Default: reset

Enterastringvaluetobeusedasthereset input port name in generated HDL code. If you specify a string that is a VHDL or Verilog reserved word, the code generator appends a reserved word postfix string to form a valid VHDL or Verilog identifier. For example, if you specify the reserved word the resulting name string would be

signal_rsvd.

Tip

If the reset asserted level is set to active-high, the reset input signal is asserted active-high (1) and the input value must be high (1) for the entity’s registers to be reset. If the reset asserted level is set to active-low, the reset input signal is asserted active-low (0) and the input value must be low (0) for the entity’s registers to be reset.

signal,

Command-Line Information

Property: ResetInputPort Type: string Value: Default:

Any identifier tha t is legal in the target language

'reset'

Settings

Default: None

Text entered i model and tes characters a are included for each new

n this field generates a comment line in the header of generated

t bench files. The code generator adds leading comment

s appropriate for the target language. W hen newlines or linefeeds

in the string, the code g enerator emits single-line comments

line.

Command-Line Information

Property: Type: string

UserComment

Verilog file extension

Specify the file-n ame extension for generated Verilog files.

Settings

Default: .v

This field specifies the file-name extension for generated Verilog files.

Dependencies

This option is enabled when the target language (specified by the Language option) is Verilog.

Command-Line Information

Property: VerilogFileExtension Type: string Default:

'.v'

VHDL file extension

Specify the file-name extension for generated VHDL files.

Settings

Default: .vhd

This field specifies the file-name extension for generated VHDL files.

Dependencies

This option is enabled when the target language (specified by the Language option) is VHDL.

Command-Line Information

Property: VHDLFileExtension Type: string Default:

HDL Coder™ GUI

'.vhd'

3-28

Entity conflict postfix

Specify the string used to resolve duplicate VHDL entity or Verilog module names in generated code.

Settings

Default: _block

The specified postfix resolves duplicate VHD L entity or Verilog module names. For example, in the default case, if the coder detects two entities with the name instance

Command-Line Information

Property: EntityConflictPostfix Type: string Value: Any string that is legal in the target language Default:

MyFilt, the coder names the f irst entity MyFilt and the second

MyFilt_entity.

'_block'

Package postfix

Specify a string to append to the model or subsystem name to form name of a package file.

Settings

Default: _pkg

Thecoderappliesthisoptiononlyifapackagefileisrequiredforthedesign.

Dependency

This option is enabled when:

The target language (specified by the Language option) is VHDL.

The target language (specified by the Language option) is Verilog, and the Multi-file test bench option is selected.

HDL Coder™ GUI

3-30

Command-Line Information

Property: PackagePostfix Type: string Value: Any string value that is legal in a VHDL package file name Default:

'_pkg'

Reserved word postfix

Specify a string to append to value names, postfix values, or labels that are VHDL or Verilog reserve d words.

Settings

Default: _rsvd

The reserved word postfix is applied to identifiers (for entities, signals, constants, or other model ele m ents) that conflict with VHDL or Verilog reserved words. For example, if your generating model contains a signal named

Command-Line Information

mod, the coder adds the postfix _rsvd to form the name mod_rsvd.

Property: ReservedWordPostfix Type: string Default:

'_rsvd'

Settings

Default: Off

VHDL entity and architecture definitions are written to separate files.

Off

VHDL entity and architecture code is written t o a sin g le VHDL file.

Tips

Thenamesoftheentityandarchitecturefilesderivefromthebasefilename (as specified by the generating model or subsystem name). By default, postfix strings identifying the file as an entity ( appended to the base file name. You can override the default and specify your own postfix string .

For example, instead of all generated code residing in specify that the code reside in

MyFIR_entity.vhd and MyFIR_arch.vhd.

_entity) or architecture (_arch)are

MyFIR.vhd,youcan

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Dependencies

This option is enabled when the target language (specified by the Language option) is Verilog.

Selecting this option enables the following parameters:

• Split entity file postfix

• Split architecture file postfix

Command-Line Information

Property: SplitEntityArch Type: string Value:

'on' | 'off'

Mathworks SIMULINK HDL CODER 1 user guide

Getting Started

Product Overview

Extending the Code Generation Process

Summary of Key Features

Expected Users and Prerequisites

Software Requirements and Installation

Software Requirements

Software Requirements for Demos

VHDL and Verilog Language Support

Installing the Software

Available Help and Demos

Online Help

Demos

Introduction to HDL Code Generation

Before You Generate Code

Overview of Exercises

The sfir_fixed Demo Model

Generating HDL Code Using the Command Line Interface

Overview

Creating a Folder and Local Model File

Initializing Model Parameters with hdlsetup

Generating a VHDL Entity from a S ubsystem

Verifying Generated Code

Generating a Verilog Module

Generating HDL Code Using the GUI

Simulink HDL Coder GUI Over view

Creating a Folder and Local Model File

Creating a Folder

Making a Local Copy of the Model File

Viewing Coder Options in the Configuration Parameters Dialog Box

Creating a Control File

Initializing Model Parameters with hdlsetup

Selecting and Checking a S ubsystem for HDL Compatibility

Generating VHDL Code

Verifying Generated Code

Generating Verilog Model and Test Bench Code

Simulating and Verifying Generated HDL Code

Code Generation Options in the Simulink HDL Coder GUI

Viewing and Setting HDL Coder Options

HDL Coder Options in the Configuration Parameters Dialog Box

HDL Coder Menu

HDL Coder Pane: General

Buttons in the HDL Coder Top-Level Pane

File name

Settings

Command-Line Information

See Also

Generate HDL for

Settings

Command-Line Information

See Also

Language

Settings

Command-Line Information

See Also

Folder

Settings

Command-Line Information

See Also

Settings

Command-Line Information

CodeGenerationOutput

See Also

Settings

Command-Line Information

See Also

Settings

Command-Line Information

See Also

HDL Coder Pane: Global Settings

Reset type

Settings

Command-Line Information

See Also

Settings

Command-Line Information

ResetAssertedLevel

See Also

Clock input port