Mathworks FILTER DESIGN HDL CODER 2 user guide

Filter Design HDL C

User’s Guide

oder™ 2

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Filter Design HDL Coder™ User’s Guide

© COPYRIGHT 2004–20 10 by The MathWorks, Inc.

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Revision History

June 2004 Online only New for V ersion 1.0 (Release 14)
October 2004 Online only Updated for Version 1.1 (Release 14SP1)
March 2005 Online only Updated for Version 1.2 (Release 14SP2)
September 2005 Online only Updated for Version 1.3 (Release 14SP3)
March 2006 Online only Updated for Version 1.4 (Release 2006a)
September 2006 Online only Updated for Version 1.5 (Release 2006b)
March 2007 Online only Updated for Version 2.0 (Release 2007a)
September 2007 Online only Revised for Version 2.1 (Release 2007b)
March 2008 Online only Revised for Version 2.2 (Release 2008a)
October 2008 Online only Revised for Version 2.3 (Release 2008b)
March 2009 Online only Revised for Version 2.4 (Release 2009a)
September 2009 Online only Revised for Version 2.5 (Release 2009b)
March 2010 Online only Revised for Version 2.6 (Release 2010a)

Getting Started

1

Product Overview ................................. 1-2

Automated HDL Code Generation
Expected Users
Key Features and Components
Generate HDL Dialog Box — the GUI
Command-Line Interface
Quantized Filters — the Input
Filter Properties — Input Parameters
Generated HDL Files — the Output

................................... 1-3

........................... 1-6

.................... 1-2

...................... 1-3

................. 1-5

....................... 1-7

................. 1-9

.................. 1-10

Contents

Installation

Checking Product Requirements
Installing the Software

Getting Help

Information Overview
Online Help
Using “What’s This?” Context-Sensitive Help
Demos and Tutorials

Applying HDL Code Generation to the Hardware

Design Process

....................................... 1-11

..................... 1-11

............................. 1-11

...................................... 1-12

.............................. 1-12

...................................... 1-13

........... 1-13

............................... 1-14

.................................. 1-15

Tutorials: Generating HDL Code for Filters

2

Creating a Folder for Your Tutorial Files ............ 2-2

Basic FIR Filter Tutorial

Designing a Basic FIR Filter in FDATool

........................... 2-3

.............. 2-3

v

Quantizing the Basic FIR Filter ...................... 2-5

Configuring and Generating the Basic FIR Filter’s VHDL

Code

.......................................... 2-8

Getting Familiar with the Basic FIR Filter’s Generated

VHDL Code

Verifying the Basic F IR Filter’s Ge ne rate d VHDL Code

.................................... 2-16

.. 2-18

Optimized F IR Filter Tutorial

Designing the FIR Filter in FDATool
Quantizing the FIR Filter
Configuring and Generating the FIR Filter’s Optimized

Verilog Code

Getting Familiar with the FIR Filter’s Optimized Generated

Verilog Code

Verifying the FIR Filter’s O pti m ized Generated Verilog

Code

.......................................... 2-41

IIR Filter Tutorial

Designing an IIR Filter in FDATool
Quantizing the IIR Filter
Configuring and Generating the IIR Filter’s VHDL

Code

.......................................... 2-54

Getting Familiar with the IIR Filter’s Generated VHDL

Code

.......................................... 2-60

Verifying the IIR Filter’s Generated VHDL Code

................................... 2-29

................................... 2-39

................................. 2-48

...................... 2-24

................. 2-24

........................... 2-26

.................. 2-48

........................... 2-50

........ 2-62

Generating HDL Code for a Filter Design

vi Contents

3

Overview of Generating HDL Code for a Filter

Design

Opening the Generate HDL Dialog Box

Opening the Generate HDL Dialog Box from FDATool
Opening the Generate HDL Dialo g Box fr om the

Opening the Generate HDL Dialog Box Using the fdhdltool

.......................................... 3-2

filterbuilder GUI

Command

................................ 3-9

..................................... 3-11

.............. 3-4

... 3-4

What Is Generated by Default? ...................... 3-14

Default S etting s for Gene rate d Files
Default Generation of Script Files
Default Settings for Register Resets
Default S etting s for Gene ral HDL Code
Default Settings for Code Optimizations
Default Setting s for Test Benches

.................. 3-14

.................... 3-15

.................. 3-15

............... 3-15

............... 3-17

.................... 3-17

What Are Your HDL Requirements?

Setting the Target Language

Setting the Names and Location for Generated HDL

Files

Default File Names and Locations
Setting Filter Entity and General File Naming Strings
Setting the Location of Generated Files
SettingthePostfixStringforVHDLPackageFiles
Splitting Entity and Architecture Code into Separate

Customizing Reset Specifications

Setting the Reset Type for Registers
Setting the Asserted Level for the Reset Input Signal
Suppressing Generation of Reset Logic

Customizing the HDL Code

Specifying a Header Comment
Specifying a Prefix for Filter Coefficients
Setting the Postfix String for Resolving E ntity or Module

SettingthePostfixStringforResolvingHDLReserved

Setting the Postfix String for Process Block Labels
Setting a Prefix for Component Instance Names
Setting a Prefix for Vector Names
Naming HDL Ports
Specifying the HDL Data Type for Data Ports
Suppressing Extra Input and Output Registers
Representing Constants with Aggregates
Unrolling and Removing VHDL Loops
Using the VHDL rising_edge Function

............................................ 3-26

Files

.......................................... 3-31

Name Conflicts

Word C onflicts

................................. 3-41

.................................. 3-42

................................ 3-49

........................ 3-25

......................... 3-37

....................... 3-38

................. 3-19

.................... 3-26

............... 3-29

...... 3-30

................... 3-33

.................. 3-33

................ 3-35

.............. 3-39

...... 3-45

........ 3-47

.................... 3-48

.......... 3-50

......... 3-52

.............. 3-53

................ 3-54

................ 3-55

... 3-27

.... 3-34

vii

Suppressing the Generation of VHDL Inline

Configurations
Specifying VHDL Syntax for Concatenated Zeros
Suppressing Verilog Time Scale Directives
Specifying Input Type Treatment for Addition and

Subtraction Operations
Using Complex Data and Coefficients
Specifying Programmable Filter Coefficients for FIR

Filters
Specifying Programmable Filter Coefficients for IIR

Filters

........................................ 3-64

........................................ 3-77

.................................. 3-57

....... 3-58

............. 3-59

.......................... 3-60

................. 3-62

Capturing Code Generation Settings to a Script

Generating Code for Multirate Filters

Supported Multirate Filter Types
Generating Multirate Filte r Code
Code Generation Options for Multirate Filters

Generating Code for Cascade Filters

Supported Cascade Filter Types
Generating Cascade Filter Code

Generating Code for Polyphase Sample Rate

Converters

Overview
HDL Implementation for Polyphase Sample Rate

Converter

Generating Code for Mu ltirate Farrow Sample Rate

Converters

Overview
Generating Code for mfilt.farrowsrc Filters at the Command

Line
Generating Code for mfilt.farrowsrc Filters in the GUI

...................................... 3-97

........................................ 3-97

...................................... 3-97

...................................... 3-101

........................................ 3-101

.......................................... 3-101

..................... 3-93

..................... 3-93

............... 3-86

.................... 3-86

.................... 3-86

................ 3-93

...... 3-85

.......... 3-87

... 3-103

viii Contents

Generating Code for Single-Rate Farrow Filters

Overview
Code Generation Properties for Farrow Filters
GUI Options for Farrow Filters
Farrow F ilter Code Generation Mechanics

........................................ 3-105

.......... 3-105

...................... 3-107

............. 3-110

...... 3-105

Customizing the Test Bench ........................ 3-112

Renaming the Test Bench
Specifying a Test Bench Type
Splitting Test Bench Code a nd Data into Separate Files
Configuring the Clock
Configuring Resets
Setting a Hold Time for Data Input Signals
Setting an Error Margin for Optimized Filter Code
Setting an Initial Value for Test Bench Inputs
Setting Test Bench Stimuli
SettingaPostfixforReferenceSignalNames
Generating HDL Cosimulation Blocks for Use with HDL

Simulators

Generating a Simulink Model for Cosimulation with an

HDL Simulator

..................................... 3-130

................................. 3-133

........................... 3-112

........................ 3-114

.. 3-115

.............................. 3-117

................................ 3-119

............ 3-122

...... 3-125

.......... 3-126

......................... 3-127

........... 3-129

Generating the HDL Code

Generating Scripts for EDA Tools

Overview
Defaults for Script Generation
Custom Script Generation
Properties for Controlling Script Generation
Controlling Script Generation with the EDA Tool Scripts

Dialog Box

Mixed-Language Scripts

........................................ 3-143

..................................... 3-148

.......................... 3-142

................... 3-143

....................... 3-143

.......................... 3-144

........... 3-145

............................ 3-157

Optimizing Generated HDL Code

4

Setting Optimizations .............................. 4-2

Optimizing Generated Code for HDL

Optimizing Coefficient Multipliers

................ 4-3

.................. 4-4

Multiplier Input and Output Pipelining for FIR

Filters

.......................................... 4-6

ix

Optimizing Final Summation for FIR Filters ......... 4-8

Speed vs. Area Optim izations for FIR Filters

Overview o f Speed vs. Area O ptimizations
Parallel and Serial Architectures
Specifying Speed vs. Area Tradeoffs via generatehdl

Properties

Selecting Parallel and Serial Architectures in the Generate

HDL Dialog Box

Distributed Arithmetic for FIR Filters

Distributed Arithmetic Overview
Requirements and Considerations for Generating

Distributed Arithmetic Code
DALUTPartition Property
DARadix Property
Special Cases
Distributed Arithmetic Options in the Generate HDL

Dialog Box

Optimizing the Clock Rate with Pipeline Registers

Setting Optimizations for Synthesis

..................................... 4-15

................................ 4-19

................................. 4-34

..................................... 4-34

..................................... 4-35

..................... 4-11

............... 4-27

..................... 4-27

...................... 4-29

.......................... 4-30

................. 4-42

......... 4-10

............. 4-10

... 4-40

x Contents

Testing a Filter Design

5

TestingwithanHDLTestBench .................... 5-2

Overview
Generating the Filter and Test Bench HDL Code
Starting the Simulator
Compiling the Generated Filter and Test Bench Files
Running the Test Bench Simulation

........................................ 5-2

........ 5-3

............................. 5-6

.................. 5-8

.... 5-7

Property Reference

6

Language Selection Properties ..................... 6-2

File Naming and Location Properties

Reset Properties

Header Comment and General Nam ing Properties

Port Properties

Advanced Coding Properties

Optimization P roperties

Test Bench Properties

Script Generation Properties

................................... 6-2

.................................... 6-4

....................... 6-5

........................... 6-6

............................. 6-7

....................... 6-9

................ 6-2

.... 6-3

xi

Properties — Alphabetical List

7

Function Reference

8

Examples

A

Tutorials .......................................... A-2

Basic FIR Filter Tutorial

Optimized F IR Filter Tutorial

IIR Filter Tutorial

Speed vs. Area Optim izations for FIR Filters

................................. A-2

........................... A-2

...................... A-2

......... A-3

Index

xii Contents

Getting Started

• “Product Overview” on page 1-2

• “Installation” on page 1-11

• “Getting Help” on page 1-12

• “Applying HDL Code Generation to the Hardware Design Process” on page

1-15

1

1 Getting Started

Product Overview

Automated HDL Code Generation

Hardware description language (HDL) code generation accelerates the
development of application-specific integrated circuit (ASIC) and field
programmable gate array (FPGA) designs and bridges the gap between
system-level design and hardware development.

In this section...

“Automated HDL Code Generation” on page 1-2

“Expected Users” on page 1-3

“Key Features and Components” on page 1-3

“GenerateHDLDialogBox—theGUI”onpage1-5

“Command-Line Interface” on page 1-6

“Quantized Filters — the Input” on page 1-7

“Filter Properties — Input Parameters ” on page 1-9

“Generated HDL Files — the Output” on page 1-10

1-2

Traditionally, system designers and hardware developers use HDLs, such as
very high speed integrated circuit (VHSIC) hardware description language
(VHDL) and Verilog, to d evelop hardware designs. Although HDLs provide
a proven method for hardware design, the task of coding filter designs, and
hardware designs in general, is labor intensive and the use of these languages
for algorithm and system-level design is not optimal. Users of the Filter
Design HDL Coder™ p roduct can spend more time on fine-tuning algorithms
and models through rapid prototyping and experimentation and less time
on HDL coding. Architects and designers can efficiently design, analyze,
simulate, and transfer system designs to hardware developers.

In a typical use scenario, an architect or designer uses F ilter Design Toolbox™
GUIs (FDATool or
the Filter Design HDL Coder GUI or command-line interface to configure code
generation options and generate a VHDL or Verilog implementation of the
design and a corresponding test bench. The generated code adheres to a clean
HDL coding style that enables architects and designers to quickly address

filterbuilder) to design a filter. Then, a designer uses

Product Overview

customizations, as needed. The test bench feature increases confidence in
the co rrectness of the generated code and saves potential time spent on test
bench implementation.

Expected Users

The Filter Design HDL Coder software is a tool for system and hardware
architects and designers who dev elop, optimize, and verify hardware signal
filters. These designers are experienced with VHDL or Verilog, but can
benefit greatly from a tool that automates HDL code generation. The Filter
Design HDL Coder interface provides designers with efficient means for
creating test signals and test benches that verify algorithms, validating
models against standard reference designs, and translate legacy HDL
descriptions into syste m -lev el views.

Users are expected to have prerequisite knowledge in the following subject
areas:

• Hardware design and system integration

• VHDL or Verilog

• HDL simulators

Users are also expected to have experience with the following products:

• MATLAB

• Filter Design Toolbox

®

Key Features and Components

Key features of the Filter Design HDL Coder software include the following:

• Graphical user interface (GUI) accessi ble from Filter Design and Analysis

Tool (FDATool),

• MATLAB command-line interface

• Support for the following discrete-time filter structures:

filterbuilder, or MATLAB command line

- Finite impulse response (FIR)

- Antisymmetric FIR

1-3

1 Getting Started

- Transposed FIR

- Symmetric FIR

- Second-order section (SOS) infinite impulse response (IIR) Direct Form I

- SOS IIR Direct Form I transposed

- SOS IIR Direct Form II

- SOS IIR Direct Form II transposed

- Discrete-Time Scalar

- Delay filter

- Farrow (fractional delay) filter

• Support for the following multirate filter structures:

- Cascaded Integrator Comb (C IC ) interpolation

- Cascaded Integrator Comb (CIC) decimation

- Direct-Form Transposed FIR Polyphase Decimator

1-4

- Direct-Form FIR Polyphase Interpolator

- Direct-Form FIR Polyphase Decimator

- FIR Hold Interpolator

- FIR Linear Interpolator

- Direct-Form FIR Polyphase Sample Rate Converter

- Farrow sample rate converter

• Support for cascade filters (multirate and discrete-time)

• Generation of code that adheres to a clean HDL coding style

• Options for optimizing numeric results of generated HDL code

• Options for specifying parallel, serial (fully, partly or casc ade), or

distributed arithm etic architectures for FIR filter realizations

• Options for controlling the contents and style of the generated HDL code

and test bench

• Test bench generation for validating the generated HDL filter code

Product Overview

• Test bench option a ll y partitioned into code, data, and helper function files

• Complex coefficients and com plex input signals supported for fully parallel

FIR, CIC, and some other filter structures

• Support for programmable coefficients for FIR and IIR filter coefficients

• VHDL and Verilog test bench options

• Automatic generation of scripts for third-party simulation and synthesis

tools

• Automatic generation of a script that captures all non-default GUI settings

for HDL code and test bench generation

• Autom atic generation of HDL Cosimulation blocks for use with third-party

HDL simulators

®

• Automatic generation of a Simulink

model that is configured for both
Simulink simulation of your filter design, and cosimulation of your design
with an HDL simulator

Generate HDL Dialog Box — the GUI

You access the Filter Design HDL Coder GUI from the FDATool Targets
menu, the
you have designed a filter object, you can generate HDL code for that filter
with the Generate HDL dialog box. The m ain dialog box displays the filter’s
structure a nd order in the title bar. The following figure indicates that the
input is a Direct Form FIR filter with an order of 50.

filterbuilder GUI, or the MATLAB comma nd line. Given that

1-5

1 Getting Started

1-6

To learn how to use the GUI to customize HDL code generation to meet
project-specific requirements, see Chapter 3, “Generating HDL Code for
a Filter Design”.

Command-Line Interface

You also have the option of generating HDL code for a filter with the
Filter Design HDL Coder command-line interface. You can apply functions
interactively at the MATLAB command line or programmatically in a
MATLAB program. The following table lists available functions with brief
descriptions. For more detail, see Chapter 8, “Function Reference”.

Product Overview

Function

generatehdl

fdhdltool

generatetb

generatetbstimulus

Purpose

Generate HDL code for quantized filter

Open Generate HDL dialog box for quantized filter

Generate test bench f or quantized filter

Generate and return test bench stimuli

Quantized Filters — the Input

The input to the coder is a quantized filter that you design and quantize
using one of the following products:

• Filter Design Toolbox

• Signal Processing Toolbox™

HDL code generation is supported for the following filter structures.

• Discrete-time:

- Finite impulse response (FIR)

- Antisymmetric FIR

- Transposed FIR

- Symmetric FIR

- Second-order section (SOS) infinite impulse response (IIR) Direct Form I

- SOS IIR Direct Form I transposed

- SOS IIR Direct Form II

- SOS IIR Direct Form II transposed

- Discrete-Time Scalar

- Delay filter

- Farrow (fractional delay) filter

• Multirate:

- Cascaded Integrator Comb (C IC ) interpolation

1-7

1 Getting Started

- Cascaded Integrator Comb (CIC) decimation

- Direct-Form Transposed FIR Polyphase Decimator

- Direct-Form FIR Polyphase Interpolator

- Direct-Form FIR Polyphase Decimator

- FIR Hold Interpolator

- FIR Linear Interpolator

- Direct-Form FIR Polyphase Sample Rate Converter

- Farrow sample rate converter

• Cascade filters (multi rate and discrete-time)

Each of these structures (with the exception of the CIC filter structures)
supports fixed-point and floating-point (double) realizations.

The CIC filter types support only fixed-point realizations.

1-8

The FIR structures also support unsigned fixed-point coefficients.

Note The coder does not support zero order filters, both in FIR and IIR
sections.

The quantized filter must have the following data format characteristics:

• Fixed-point

• Double floating-point precision

However, use of complex input data and complex coefficients is supported for
some filter types. (See “Using Complex Data and Coefficients” on page 3-62.)

When designing a filter for HDL code generation, consider how filter
coefficients are specified. If the coefficients for a filter are small in value and
the word size and binary point are large, it is possible for the coder to compute
integer coefficients that are numerically inaccurate. Double-precision
coefficients support up to 53 bits of precision.

Product Overview

For information on how to design filter objects and specify filter coefficients,
see the documentation for the following products:

• Filter Design Toolbox

• Signal Processing Toolbox

Filter Properties — Input Parameters

The coder generates filter and test bench HDL code for a specified quantized
filter based on the settings of a collection of property name and property value
pairs. The properties and their values

• Contribute to the naming of language elements

• Specify port parameters

• Determine the use of advanced HDL coding features

All properties have default settings. However, you can customize the HDL
output to meet project specifications by adjusting the property settings with
the GUI or command-line interface. The GUI enables you to set properties
associated with

• The HDL language specification

• File name and location specifications

• Reset specifications

• HDL code customizations

• HDL code optimizations

• Test bench customizations

• Generation of script files for third-party Electronic Design Automation

(EDA) tools

You can set the same filter properties by specify ing property name and
property value pairs with the functions

generatetbstimulus interactively at the MATLAB command line or in a

MATLAB program.

generatehdl, generatetb,and

1-9

1 Getting Started

The property names and property values are not case sensitive and, when
specifying them, you can abbreviate them to the shortest unique string.

For lists and descriptions of the properties and functions, see Chapter 6,
“Property Reference” and Chapter 8, “Function Reference”, respectively.

Generated HDL Files — the Output

Based on the options and input data you specify, the coder generates filter
and filter test bench HDL files as output. If the filter design requires a VHDL
package, the coder also generates a package file.

The GUI generates all output files at the end of a dialog session. If you choose
to use the command-line interface, you generate the filter and test bench HDL
files separately with calls to the functions

By default, the coder writes output files in a subfolder named hdlsrc, under
the current working folder, and n ames the files as follows, where
value of the

Name property.

generatehdl and generatetb.

name is the

1-10

Language

Verilog Filter

VHDL

File

Filter test bench

Filter

Filter test bench

Filter package (if
required)

Name

name.v

name_tb.v

name.vhd

name_tb.vhd

name_pkg.vhd

Installation

Installation

In this section...

“Checking Product Requirements” on page 1-11

“Installing the Software” on page 1-11

Checking Product Requirements

The coder requires the following software from The M athWorks™:

• MATLAB

• Fixed-Point Toolbox™

• Signal Processing Toolbox

• Filter Design Toolbox

VHDL and Verilog Language Support

The coder generates code that is compatible with HDL compilers, simulators
and other tools that support

• VHDL versions 87, 93, and 02.

Exception: VHDL test benches using double precision data types do not
support VHDL version 87. (See also “Compiling the Generated Filter and
TestBenchFiles”onpage5-7.)

• Verilog-2001 (IEEE 1364-2001) or later.

Installing the Software

For information on installing the required software listed above, and optional
software, see the Installation Guide for your platform.

1-11

1 Getting Started

Getting Help

In this section...

“Information Overview” on page 1-12

“Online Help” on page 1-13

“Using “What’s This?” Context-Sensitive Help” on page 1-13

“Demos and Tutorials” on page 1-14

Information Overv iew

The following information is available with this product:

Chapter 1, “Getting Started”

Chapter 2, “Tutorials:
Generating HDL Code for
Filters”

Chapter 3, “Generating HDL
Code for a Filter Design”

ter 4, “Optimizing

Chap

rated HD L Code”

Gene

Chapter 5, “Testing a Filter
Design”

Chapter 6, “Property
Reference”

Explains what the product is, how to
install it, its applications in the hardware
design process, and how to access product
documentation and online help.

Guides you through the process of
generating HDL code for a sampling of
filters.

ins how to set code generatio n

Expla

ns and generate HDL code for a filter

optio

n.

desig

Explains options and techniques you
can use to optimize generated HDL
code for speed, area, latency, and other
characteristics, and the tradeoffs involved
in the use of optimizations.

Explains how to apply generated test
benches.

Lists f ilter properties by category.

1-12

Getting Help

Chapter 7, “Properties —
Alphabetical List”

Chapter 8, “Function
Reference”

Provides descriptions of properties
organized alphabetically by property
name.

Provides descriptions of the functions
available in the product’s command-line
interface.

Online Help

The following online help is available:

• Online help in the MATLAB Help browser. Click the Filter Design HDL

Coder link in the browser’s Contents pane.

• Context-sensitive “What’s This?” help for options that a ppear in the Filter

Design HDL Coder GUI. Click a GUI Help button or right-click on a GUI
option to display help on that dialog, or item. For more information on using
the context-sensitive help, see “Using “What’s This?” Context-Sensitive
Help” on page 1-13.

• Help for the command-line interface functions

fdhdltool,andgeneratetbstimulus is accessible with the doc and help

commands. For example:

doc generatehdl
help generatehdl

generatehdl, generatetb,

Using “What’s This?” Context-Sensitive Help

“What’s This?” context-sensitive help topicisavailableforeachdialogbox,
pane, and option in the G U I. Use the “What’s This?” help as needed while
using the GUI to configure options that control the contents and style of the
generated HDL code and test bench.

To use the “What’s This?” help, do the following:

1 Place your cursor over the label or controlforanoptionorinthebackground

for a pane or dialog box.

1-13

1 Getting Started

2 Right-click . A What’s This? button appears. The following display shows

the What’s This? button appearing after a right-click on the Folder option
in the Target pane of the G enerate HDL dialog box.

3 Click What’s This? to view context-sensitive help that describes the option,

or dialog box.

Demos and Tutorials

Demos and tutorials provided with the product will help you get started. The
demos give you a quick view of the product’s capabilities and examples of how
you might apply the product. You can run them with limited product exposure.

1-14

The tutorials provide procedural instruction on how to apply product features.
The following to pics, in Chapter 2, “Tutorials: Generating HDL Code for
Filters”, guide you through three tutorials:

• “Basic FIR Filter Tutorial” on page 2-3

• “Optimized FIR Filter Tutorial” on page 2-24

• “IIR Filter Tutorial” on page 2-48

Applying HDL Code Generation to the Hardware Design Process

Applying HDL Code Generation to the Hardware Design
Process

The workflow fo
process requir

1 Design a filte

2 Quantize the filter.

3 Review the default property settings that the co de r applies to generated

r applying HDL code generation to the hardware design

es the following steps:

r.

HDL code.

4 Adjust prop

erty settings to customize the generated HDL code, as

necessary.

5 Generate the filter and test bench code.

6 Consider and, if appropriate, apply optimization options.

7 Test the g

enerated code in a simulation.

1-15

1 Getting Started

The following figure shows these steps in a flow diagram.

Design filter

Set HDL

properties

Quantized?

No

Generate HDL

code for filter and

test bench

Optimize?

Simulate

Yes

HDL

property

defaults

OK?

Yes

No

Done

Yes

No

Quantize filter

Set optimization

properties

1-16

2

Tutorials: Generating HDL Code for Filters

• “Creating a Fo lder for Your Tutorial Files” on page 2-2

• “Basic FIR Filter Tutorial” on page 2-3

• “Optimized FIR Filter Tutorial” on page 2-24

• “IIR Filter Tutorial” on page 2-48

2 Tutorials: Generating HDL Code for Filters

Creating a Folder for Your Tutorial Files

Set up a writable working folder outside your MATLAB installation folder
to store files that will be generated as you complete your tutorial work. The
tutorial instructions assume that you create the folder
on drive C.

hdlfilter_tutorials

2-2

Basic FIR Filter Tutorial

In this section...

“Designing a Basic FIR Filter in FDATool” o n page 2-3

“Quantizing the Basic FIR Filter” on page 2-5

“Configuring and Generating the BasicFIRFilter’sVHDLCode”onpage2-8

“Getting Familiar with the Basic FIR Filter’s Generated VHDL Code” on
page 2-16

“Verifying the Basic FIR Filter’s Generated VHDL Code” on page 2-18

Designing a Basic FIR Filter in FDATool

This tutorial guides you through the steps for designing a basic quantized
discrete-time FIR filter, generating VHDL code for the filter, and verifying
the VHDL code with a generated test bench.

Basic FIR Filter Tutorial

This section assumes you are familiar with the MATLAB user interface and
the Filter Design & Analysis Tool (FDATool). The following instructions
guide you through the procedure of designing and creating a basic FIR filter
using FDATool:

1 Start the MATLAB software.

2 Set your current folder to the folder you created in “Creating a Folder for

Your Tutorial Files” on page 2-2.

2-3

2 Tutorials: Generating HDL Code for Filters

3 Start the FDATool by entering the fdatool command in the MATLAB

Command Window. The Filter Design & Analysis Tool dialog box appears.

2-4

4 In the Filter Design & Analysis Tool dialog box, check that the following

filter options are set:

Basic FIR Filter Tutorial

Option

Response Type

Design Method

Filter Order

Options

Frequency Specifications

Value

Lowpass

FIR Equiripple

Minimum order

Density Factor:

Units:

Hz

20

Fs: 48000

Fpass: 9600

Fstop: 12000

Magnitude Specifications

Units:

dB

Apass: 1

Astop: 80

These settings are for the default filter design that the FDATool cre ates
for you. If you do not need to make any changes and Design Filter is
grayed out, you are done and can skip to “Quantizing the Basic FIR Filter”
on page 2-5.

5 If you modified any of the options listed in step 4, click Design Filter.The

FDATool creates a filter for the specified design and displays the following
message in the FDATool status bar when the task is complete.

Designing Filter... Done

For more information on designing filters with the FDATool, see “Using
FDATool with Filter Design Toolbox Software” in the Filter Design Toolbox
documentation.

Quantizing the Basic FIR Filter

You should quantize filters for HDL code generation. To quantize your filter,

1 Open the basic FIR filter design you created in “Designing a Basic FIR

Filter in FDATool” on page 2-3 if it is not already open.

2-5

2 Tutorials: Generating HDL Code for Filters

2 Click the Set Quantization Parameters button in the left-side toolbar.

The FDATool displays a Filter arithmetic menu in the bottom half of
its dialog box.

2-6

3 Select Fixed-point from the Filter arithmetic list. Then select Specify

from the Filter precision list. The FDATool displays the first of

all

Basic FIR Filter Tutorial

three tabbed panels of quantization parameters across the bottom half
of its dialog box.

You use the quantization options to test the effects of various settings with
a g oa l of optimizing the quantized filter’s performance and accuracy.

4 Set the quantization parameters as follows:

2-7

2 Tutorials: Generating HDL Code for Filters

Tab

Coefficients

Input/Output

Filter
Internals

5 Click Apply.

For more information on quantizing filters with the FDATool, see “Using
FDATool with Filter Design Toolbox Software” in the Filter Design Toolbox
documentation.

Parameter

Numerator word length

Best-precision fraction lengths

Use unsigned representation

Scale the numerator coefficients
to fully utilize the entire dynamic
range

Input word length

Input fraction length

Output word length

Rounding mode

Overflow mode

Accum. word length

Setting

16

Selected

Cleared

Cleared

16

15

16

Floor

Saturate

40

2-8

Configuring and Generating the Basic FIR Filter’s VHDL Code

After you quantize your filter, you are ready to configure coder options
and generate the filter’s VHDL code. This section guides you through the
procedure for starting the Filter Design HD L Coder GUI, setting some options,
and generating the VHDL code and a test bench for the basic FIR filter you
designed and quantized in “Designing a Basic FIR Filter in FDATool” on page
2-3 and “Quantizing the Basic FIR Filter” on page 2-5.

1 Start the Filter Design HDL Coder GUI by selecting Targets > Generate

HDL in the FDATool dialog box. The FDATool displays the Generate

HDL dialog box.

Basic FIR Filter Tutorial

2 Find the Filter Design HDL Coder online help. Use the online help to learn

about product details or to get answers to questions as you work with the
designer.

a In the MATLAB window, click the Help button in the toolbar or click

Help > Product Help.

b In the Help browser’s Contents pane, select the Filter Design HDL

Coder entry.

c Minimize the Help browser.

3 In the Generate HDL dialog box, click the Help button. A small

context-sensitive help window opens. The window displays information
about the dialog box.

2-9

2 Tutorials: Generating HDL Code for Filters

4 Close the Help window.

5 PlaceyourcursorovertheFolder label or text box in the Target pane

of the Generate HDL dialog box, and right-click. A What’s This? button
appears.

6 Click What’s This? The context-sensitive help window displays

information describing the Folder option. Use the con text-sensitive help
as needed while using the GUI to configure the contents and style of the
generated H D L code. A help topicisavailableforeachoption.

2-10

7 In the Nam

basicfir

contain

8 Select the Global settings tab of the GUI. Then select the General tab of

the Addition al settings section of the GUI. Type

Filter

e text box of the Target pane, replace the default name with

. This option names the VHDL entity and the file that is to

the filter’s VHDL code.

Tutorial - Basic FIR

in the Comment in header text box. The coder adds the comment

to the end of the header comment block in each generated file.

Basic FIR Filter Tutorial

9 Select the Ports tab of the Additional settings section of the GUI.

2-11

2 Tutorials: Generating HDL Code for Filters

10 Change the names of the input and output ports. In the Input port text

box, replace
replace

filter_out with data_out.

filter_in with data_in.IntheOutput port text box,

2-12

11 Clear the check box for the Add input register option. T he Ports pane

should now look like th e following.

Basic FIR Filter Tutorial

12 Click on the Test Bench tab in the Generate HDL dialog box. In the File

name text box, replace the default name with

basicfir_tb.Thisoption

names the generated test bench file.

2-13

2 Tutorials: Generating HDL Code for Filters

2-14

13 Click Generate to start the code generation process.

The coder displays messages in the MATLAB Command Window as it
generates the filter and test bench VHDL files:

### Starting VHDL code generation process for filter: basicfir

### Generating: C:\hdlfilter_tutorials\hdlsrc\basicfir.vhd

### Starting generation of basicfir VHDL entity

### Starting generation of basicfir VHDL architecture

### HDL latency is 2 samples

### Successful completion of VHDL code generation process for filter: basic fir

### Starting generation of VHDL T est Bench

### Generating input stimulus

### Done generating input stimulus; length 3429 samples.

### Generating Test bench: C:\hdlfilter_tutorials\hdlsrc\basicfir_tb.vhd

### Please wait ...

Basic FIR Filter Tutorial

### Done generating VHDL Test Ben ch

>>

As the messages indicate, the coder creates the folder hdlsrc under
your current working folder and places the files

basicfir_tb.vhd in that f o l der.

basicfir.vhd and

Observe that the messages include hyperlinks to the generated code and
test bench files. By clicking on these hyperlinks, you can open the code files
directly into the MATLAB Editor.

The generated VHDL code has the following characteristics:

• VHDL entity named

basicfir.

• Registers that use asynchronous resets when the reset signal is active

high (1).

• Ports have the following names:

VHDL Port Name

Input

Output

Clock input

Clock enable

data_in

data_out

clk

clk_enable

input

Reset input

reset

• An extra register for handling filter output.

• Clock input, clock enable input and reset ports are of type

STD_LOGIC

and data input and output ports are of type STD_LOGIC_VECTOR.

• Coefficients are named

coeffn,wheren is the coefficient number,

starting with 1.

• Type safe representation is used when zeros are concatenated:

& '0'...

'0'

• Registers are generated with the statement

clk='1' THEN

rather than with the rising_edge function.

ELSIF clk'event AND

2-15

2 Tutorials: Generating HDL Code for Filters

• The postfix string _process is appended to process names.

The generated test bench:

• Is a portable VHDL file.

• Forces clock, clock enable, and reset input signals.

• Forces the clock enable input signal to active high.

• Drives the clock input signal high (1) for 5 nanoseconds and low (0) for

5 nanoseconds.

• Forces the reset signal for two cycles plus a hold time of 2 nanoseconds.

• Applies a hold time of 2 nanoseconds to data input signals.

• For a FIR filter, applies impulse, step, ramp, chirp, and white noise

stimulus types.

14 When you have finished generating code, click Close to close the Generate

HDL dialog box.

2-16

Getting Familiar with the Basic FIR Filter’s Generated VHDL Code

Get familiar with the filter’s generatedVHDLcodebyopeningandbrowsing
through the file

1 Open the generated VHDL filter file basicfir.vhd.

2 Search for basicfir. This line identifies the VHDL module, using the

string you specified for the Name option in the Target pane. See step 5
in “Configuring and Generating the Basic FIR Filter’s VHDL Code” on
page 2-8.

3 Search for Tutorial. This is where the coder places the text you entered

for the C om ment in header option. See step 10 in “Configuring and
Generating the Basic FIR Filter’s VHDL Code” on page 2-8.

4 Search for HDL Code. This section lists coder options you modified in

“Configuring and G enerating the FIR Filter’s Optimized Verilog Code”
on page 2-29.

basicfir.vhd in an ASCII or HDL simulator editor:

Basic FIR Filter Tutorial

5 Search for Filter Settings. Thissectiondescribesthefilterdesignand

quantization settings as you specified in “Designing a Basic FIR Filter in
FDATool” on page 2-3 and “ Q u antiz ing the Basic FIR Filter” on page 2-5.

6 Search for ENTITY. This line names the VHDL entity, using the string

you specified for the Name option in the Target pane. See step 5 in
“Configuring and Generating the Basic FIR Filter’s VHDL Code” on page
2-8.

7 Search for PORT.ThisPORT declaration defines the filter’s clock, clock

enable, reset, and data input and output ports. The ports for clock, clock
enable, and reset signals are named with default strings. The ports for
data input and output are named with the strings you specified for the
Input port and Output port options on the Ports tab of the Generate
HDLdialog box. See step 12 in “Configu ring and G enerating the Basic FIR
Filter’s VHDL Code” on page 2-8.

8 Search for Constants. This is where the coefficients are defined. They are

named using the default naming scheme,

coeffn,wheren is the coefficient

number, starting with 1.

9 Search for Signals. Thisiswherethefilter’ssignalsaredefined.

10 Search for process.ThePROCES S block name Delay_Pipeline_proc ess

includes the default PROCESS block postfix string _process.

11 Search for IF reset. This is where the reset signa l is asserted. The default,

active high (1), was specified. Also note that the

PROCESS block applies the

default asynchronous reset style when generating VHDL code for registers.

12 Search for ELSIF. This is where the VHDL code checks for rising edges

when the filter operates on registers. The default

ELSIF clk'event

statement is used instead of the optional rising_edge function.

13 Search for Output_Register. This is where filter output is written to an

output register. Code for this register is generated by default. In step
13 in “Configuring and Generating the Basic FIR Filter’s VHDL Code”
on page 2-8, you clea red the Add input register option, but left the
Add output register selected. Alsonotethatthe

Output_Register_process includes the default PROCESS block postfix

string

_process.

PROCESS block name

2-17

2 Tutorials: Generating HDL Code for Filters

14 Search for data_out. This is where the filter writes its output data.

Verifying the Basic FIR Filter’s Generated VHDL Code

This section explains how to verify the basic FIR filter’s generated VHDL code
with the generated VHDL test bench. Although this tutorial uses the Mentor
Graphics
VHDL code, you can use any VHDL simulation tool package.

To verify the filter code, complete the following steps:

1 Start your simulator. When you start the Mentor Graphics ModelSim

®

ModelSim®software as the tool for compiling and simulating the

simulator, a screen display similar to the following appears.

2-18

2 Set th

3 If ne

ecurrentfoldertothefolderthat contains your generated VHDL

. For example:

files

cd c:/hdlfilter_tutorials/hdlsrc

cessary, create a design library to store the compiled VHDL entities,

kages, architectures, and configurations. In the Mentor Graphics

pac

elSim simulator, you can create a design library with the

Mod

mand.

com

vlib work

vlib

Basic FIR Filter Tutorial

4 Compile the generated filter and test bench V HDL files. In the Mentor

Graphics ModelSim simulator, you compile VHDL code with the

vcom

command. The following commands compile the filter and filter test bench
VHDL code.

vcom basicfir.vhd
vcom basicfir_tb.vhd

The following screen display shows this command sequence and
informational m essages displayed during compilation.

5 Load the test bench for simulation. The procedure for doing this varies

depending on the simulator you are using. In the Mentor Graphics
ModelSim simulator, you load the test bench for simulation with the

vsim

command. For example:

m work.basicfir_tb

vsi

2-19

2 Tutorials: Generating HDL Code for Filters

The following figure shows the results of loading work.basicfir_tb with
the

vsim command.

6 Open a d isplay window for m o nitoring the simulation as the test bench

runs. For example, in the Mentor Graphics ModelSim simulator, you can
use the following command to open a wave window to view the results of
the simulation as HDL waveforms:

2-20

addwave*

The following wave window displays.

Basic FIR Filter Tutorial

7 To start running the simulation, issue the appropriate command for your

simulator. For example, in the Mentor Graphics ModelSim simulator, you
can start a simulation with the

run command.

2-21

2 Tutorials: Generating HDL Code for Filters

The following display shows the run -all command being used to start a
simulation.

As your te
error mes
filter d
determi
you spec

Note Th
flaggi
the te
messa

st bench simulation runs, watch for error messages. If any

sages appear, you must interpret them as they pertain to your

esign a nd the H D L code generation options you selected. You must

ne whether the results are expected based on the customizations

ified when gener ati ng the filter VHDL code.

e failure message that appears in the preceding display is not
ng an actual error. If the message includes the string
st bench has successfully run to completion. The

ge is tied to the mechanism that the coder uses to end the simulation.

Test Complete,

Failure part of the

2-22

Basic FIR Filter Tutorial

The following wave window shows the simulation results as HDL
waveforms.

2-23

2 Tutorials: Generating HDL Code for Filters

Optimized FIR Filter Tutorial

In this section...

“Designing the FIR Filter in FDATool” on page 2-24

“Quantizing the FIR Filter” on page 2-26

“Configuring and Generating the FIR Filter’s Optimized Verilog Code”
on page 2-29

“Getting Familiar with the FIR Filter’s Optimized G enerated Verilog Code”
on page 2-39

“Verifying the FIR Filter’s Optimized Generated Verilog Code” on page 2-41

Designing the FIR Filter in FDATool

This tutorial guides you through the steps for designing an optimized
quantized d iscre te -time FIR filter, generating Verilog code for the filter, and
verifying the Verilog code with a generated test bench.

2-24

This section assumes you are familiar with the MATLAB user interface and
the Filter Design & Analysis Tool (FDATool).

1 Start the MATLAB software.

2 Set your current folder to the folder you created in “Creating a Folder for

Your Tutorial Files” on page 2-2.

Optimized FIR Filter Tutorial

3 Start the FDATool by entering the fdatool command in the MATLAB

Command Window. The Filter Design & Analysis Tool dialog box appears.

4 In the Filter Design & Analysis Tool dialog box, set the following filter

options:

2-25

2 Tutorials: Generating HDL Code for Filters

Option

Response Type

Design Method

Filter Order

Options

Frequency Specifications

Magnitude Specifications

These settings are for the default filter design that the FDATool creates for
you. If you do not need to make any changes and Design Filter is grayed
out, you are done and can skip to “Quantizing the FIR Filter” on page 2-26.

5 Click Design Filter. The FDATool creates a filter for the specified design.

The following message appears in the FDATool status bar when the task
is complete.

Value

Lowpass

FIR Equiripple

Minimum order

Density Factor: 20

Units:

Fs: 48000

Fpass: 9600

Fstop: 12000

Units:

Apass: 1

Astop: 80

Hz

dB

2-26

Designing Filter... Done

For more information on designing filters with the FDATool, see “Using
FDATool with Filter Design Toolbox Software” in the Filter Design Toolbox
documentation.

Quantizing the FIR Filter

You should quantize filters for HDL code generation. To quantize your filter,

1 Open the FIR filter design you created in “Optimized FIR Filter Tutorial”

on page 2-24 if it is not already open.

Optimized FIR Filter Tutorial

2 Click the Set Quantization Parameters button in the left-side toolbar.

The FDATool displays a Filter arithmetic menu in the bottom half of
its dialog box.

2-27

2 Tutorials: Generating HDL Code for Filters

3 Select Fixed-point from the list. Then select Specify all from the Filter

precision list. The FDATool d isplays the first of three tabbed panels of
quantization parameters across the bottom half of its dialog box.

2-28

You use the quantization options to test the effects of various settings with
a g oa l of optimizing the quantized filter’s performance and accuracy.

4 Set the quantization parameters as follows:

Optimized FIR Filter Tutorial

Tab

Coefficients

Parameter

Numerator word length

Best-precision fraction lengths

Use unsigned representation

Scale the numerator coefficients

Setting

16

Selected

Cleared

Cleared

to fully utilize the entire dynamic
range

Input/Output

Filter

Input word length

Input fraction length

Output word length

Rounding mode

16

15

16

Floor

Internals

Overflow mode

Accum. word length

5 Click Apply.

Saturate

40

For more information on quantizing filters with the FDATool, see “Using
FDATool with Filter Design Toolbox Software” in the Filter Design Toolbox
documentation.

Configuring and Generating the FIR Filter’s Optimized
Verilog Code

After you quantize your filter, you are ready to configure coder options and
generate the filter’s Verilog code. This section guides you through the process
for starting the GUI, setting some options, and generating the Verilog code
and a test bench for the FIR filter you designed and quantized in “Designing
the FIR Filter in FDATool” on page 2-24 and “Quantizing the FIR Filter”
on page 2-26.

2-29

2 Tutorials: Generating HDL Code for Filters

1 Start the Filter Design HDL Coder GUI by selecting Targets > Generate

HDL in the FDATool dialog box. The FDATool displays the Generate
HDL dialog box.

2-30

2 Select Verilog for the Language option, as shown in the following figure.

Optimized FIR Filter Tutorial

3 In the Name text box of the Target pane, replace the default name with

optfir. This option names the Verilog module and the file that is to

contain the filter’s Verilog code.

4 In the Filter architecture pane, select the Optimize for HDL option.

This option is for generating HDL code that is optimized for performance or
space requirements. When this option is enabled, the coder makes tradeoffs
concerning data types and might ignore your quantization settings to
achieve optimizations. When you use the option, keep in mind that you
do so at the cost of potential numeric differences between filter results
produced by the original filter object and the simulated results for the
optimized HDL code.

5 Select CSD for the Coefficient multipliers option. This option optimizes

coefficient multiplier operations by instructing the coder to replace them
with additions of partial products produced by a canonic signed digit (CSD)
technique. This technique minimizes the number of addition operations
required for constant multiplication by representing binary numbers with
a minimum count of nonzero digits.

6 Select the Add pipeline registers option. For FIR filters, this option

optimizes final summation. The coder creates a final adder that performs
pair-wise addition on successive products and includes a stage of pipeline
registers after each lev el of the tree. When used for FIR filters, this option
also has the potential for producing numeric diffe rences between results
produced by the original filter object and the simulated results for the
optimized HDL code.

7 The Generate HDL dialog box should now appear as shown in the following

figure.

2-31

2 Tutorials: Generating HDL Code for Filters

2-32

8 Select the Global settings tab of the GUI. Then select the General tab of

the Additional settings section.

In the Comment in header text box, type

Filter

block in each generated file.

. The coder adds the comment to the end of the header comment

Tutorial - Optimized FIR

Optimized FIR Filter Tutorial

9 Select the Ports tab of the Additional settings section of the GUI.

2-33

2 Tutorials: Generating HDL Code for Filters

10 Change the names of the input and output ports. In the Input port text

box, replace
replace

filter_out with data_out.

filter_in with data_in.IntheOutput port text box,

2-34

Optimized FIR Filter Tutorial

11 Clear the check box for the Add input register option. T he Ports pane

should now look like th e following.

12 Click on the Test Bench tab in the Generate HDL dialog box. In the File

name te xt box, replace the default n am e with

optfir_tb.Thisoption

names the generated test bench file.

2-35

2 Tutorials: Generating HDL Code for Filters

2-36

13 In the Test Bench pane, click the Configuration tab. Observe that the

Error margin (bits) option is enabled. This option is enabled because

previously selected optimization options (such as Add pipeline registers)
can potentially produce numeric results that differ from the results
produced by the original filter object. You can use this option to adjust
the number of least significant bits th e test bench will ignore during
comparisons before generating a warning.

Optimized FIR Filter Tutorial

14 In the Generate HDL dialog box, click Generate to start the code

generation process. When code generation completes, click Close to close
the dialog box.

The coder displays the following messages in the MATLAB Command
Window as it generates the filter and test bench Verilog files:

### Starting Verilog code generation process for filter: optfir

### Generating: C:\hdlfilter_tutorials\hdlsrc\optfir.v

### Starting generation of optfir Verilog module

### Starting generation of optfir Verilog module body

### HDL latency is 8 samples

### Successful completion of Verilog code generation process for filter: op tfir

### Starting generation of VERILOG Test Bench

### Generating input stimulus

2-37

2 Tutorials: Generating HDL Code for Filters

### Done generating input stimulus; length 3429 samples.

### Generating Test bench: C:\hdlfilter_tutorials\hdlsrc\optfir_tb.v

### Please wait ...

### Done generating VERILOG Test Bench

As the messages indicate, the coder creates the folder hdlsrc under your
current working folder and places the files
that folder.

Observe that the messages include hyperlinks to the generated code and
test bench files. By clicking on these hyperlinks, you can open the code files
directly into the MATLAB Editor.

The generated Verilog code has the following characteristics:

optfir.v and optfir_tb.v in

• Verilog module named

optfir.

• Registers that use asynchronous resets when the reset signal is active

high (1).

• Generated code that optimizes its use of data types and eliminates

redundant operations.

• Coefficient multipliers optimized with the CSD technique.

• Final summations optimized using a pipelined technique.

• Ports that have the following names:

Verilog Port

Input

Output

Clock input

Clock enable input

Reset input

Name

data_in

data_out

clk

clk_enable

reset

• An extra register for handling filter output.

• Coefficients named

coeffn,wheren is the coefficient number, starting

with 1.

2-38

Optimized FIR Filter Tutorial

• Type safe representation is used when zeros are concatenated: '0'

& '0'...

• The postfix string

_process is appended to sequential (begin)block

names.

The generated test bench:

• Is a portable Verilog file.

• Forces clock, clock enable, and reset input signals.

• Forces the clock enable input signal to active high.

• Drives the clock input signal high (1) for 5 nanoseconds and low (0) for

5 nanoseconds.

• Forces the reset signal for two cycles plus a hold time of 2 nanoseconds.

• Applies a hold time of 2 nanoseconds to data input signals.

• Appliesanerrormarginof4bits.

• For a FIR filter, appplies impulse, step, ramp, chirp, and white noise

stimulus types.

Getting Familiar with the FIR Filter’s Optimized
Generated Verilog Code

Get familiar with the filter’s optimized generated Verilog code by opening and
browsing through the file

optfir.v in an ASCII or HDL simulator editor:

1 Open the generated Verilog filter file optcfir.v.

2 Search for optfir. This line identifies the Verilog module, using the

string you specified for the Name option in the Target pane. See step 3
in “Configuring and Generating the FIR F ilter’s Optimized Verilog Code”
on page 2-29.

3 Search for Tutorial. This is where the coder places the text you entered

for the Comment in header option. See step 9 in “Configuring and
Generating the FIR Filter’s Optimized Verilog Code” on page 2-29.

2-39

2 Tutorials: Generating HDL Code for Filters

4 Search for HDL Code. This section lists the coder options you modified in

“Configuring and G enerating the FIR Filter’s Optimized Verilog Code”
on page 2-29.

5 Search for Filter Settings. This section of the VHDL code describes

the filter design and quantization settings a s you specified in “Designing
the F IR Filter in FDATool” on page 2-24 and “Quantizing the FIR Filter”
on page 2-26.

6 Search for module. ThislinenamestheVerilogmodule,usingthestring

you specified for the Name option in the Target pane. This line also
declares the list of ports, as defined by options on the Ports pane of the
Generate HDLdialog b ox. The ports for data input and output are named
with the strings you specified for the Input port and Output port options
on the Ports tab of the Generate HDLdialog box. See steps 3 and 11 in
“Configuring and G enerating the FIR Filter’s Optimized Verilog Code”
on page 2-29.

7 Search for input. This line and the four l in es that follow, declare the

direction mode of each port.

2-40

8 Search for Constants. This is where the coefficients are defined. They are

named using the default naming scheme,

coeffn,wheren is the coefficient

number, starting with 1.

9 Search for Signals. Thisiswherethefilter’ssignalsaredefined.

10 Search for sumvector1. This area of code declares the signals for

implementing an instance of a pipelined final adder. Signal declarations
for four additional pipelined final adders are also included. These signals
areusedtoimplementthepipelinedFIRadderstyleoptimizationspecified
with the Add pipeline registers option. See step 7 in “Configuring and
Generating the FIR Filter’s Optimized Verilog Code” on page 2-29.

11 Search for process.Theblock name Delay_Pipeline_process includes

the default

12 Search for reset. This is where the reset signal is asserted. The default,

active high (1), was specified. Also note that the

block postfix string _process.

process applies the

default asynchronous reset style when g enerating code for registers.

Optimized FIR Filter Tutorial

13 Search for posedge . This Verilog code checks for rising edges when the

filter operates o n registers.

14 Search for sumdelay_pipeline_process1. This block implements the

pipeline register stage of the pipeline FIR adder style you specified in
step 7 of “Configuring and Generating the FIR Filter’s Optimized Verilog
Code” on page 2-29.

15 Search for output_register. This is where filter output is written to an

output register. The code for this register is g enerated by default. In step
12 in “Configuring and Generating the FIR Filter’s Optimized Verilog
Code”onpage2-29,youclearedtheAdd input register option, b ut
left the Add output register selected. A lso note that the process name

Output_Register_process includes the default process postfix string
_process.

16 Search for data_out. This is where the filter writes its output data.

Verifying the FIR F ilter’s Optimized Generated Verilog Code

This section explains how to verify the FIR filte r’s optimized generated
Verilog code w ith the generated Verilog test bench. Although this tutorial
uses the Mentor Graphics ModelSim simulator as the tool for compiling and
simulating the Verilog code, you can use any HDL simulation tool package.

To verify the filter code, complete the following steps:

2-41

2 Tutorials: Generating HDL Code for Filters

1 Start your simulator. When you start the Mentor Graphics ModelSim

simulator, a screen display similar to the following appears.

2 Set the cu

files. Fo

3 If neces

In the M
librar

4 Compi

Graph
comm
Veri

rexample:

cd hdlsrc

sary, create a design library to store the compiled Verilog modules.

entor Graphics ModelSim simulator, you can create a design

ywiththe

vlib work

le the generated filter and test bench Verilog files. In the Mento r
ics ModelSim simulator, you compile Verilog code with the

and. The following commands compile the filter and filter test bench

log code.

vlog optfir.v
vlog optfir_tb.v

rrent folder to the folder that contains your generated Verilog

vlib command.

vlog

2-42

Optimized FIR Filter Tutorial

The following screen display shows this command sequence and
informational m essages displayed during compilation.

5 Load the test bench for simulation. The procedure for doing this varies

depending on the simulator you are using. In the Mentor Graphics
ModelSim simulator, you load the test bench for simulation with the

vsim

command. For example:

vsim optfir_tb

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2 Tutorials: Generating HDL Code for Filters

The following display shows the results of loading optfir_tb with the

vsim command.

2-44

Optimized FIR Filter Tutorial

6 Open a d isplay window for m o nitoring the simulation as the test bench

runs. For example, in the Mentor Graphics ModelSim simulator, you can
use the following command to open a wave window to view the results of
the simulation as HDL waveforms:

addwave*

The following wave window opens:

7 To start running the simulation, issue the appropriate command for your

simulator. For example, in the Mentor Graphics ModelSim simulator, you
can start a simulation with the

run command.

2-45

2 Tutorials: Generating HDL Code for Filters

The following display shows the run -all command being used to start a
simulation.

As your te
error mes
filter d
determi
you spec

esign a nd the H D L code generation options you selected. You must

ne whether the results are expected based on the customizations

ified when generatin g the filter V eri log code.

st bench simulation runs, watch for error messages. If any

sages appear, you must interpret them as they pertain to your

2-46

Optimized FIR Filter Tutorial

The following wave window shows the simulation results as HDL
waveforms.

2-47

2 Tutorials: Generating HDL Code for Filters

IIR Filter Tutorial

In this section...

“Designing an IIR Filter in FDATool” on page 2-48

“Quantizing the IIR Filter” on page 2-50

“Configuring and Generating the IIR Filter’s VHDL Code” on page 2-54

“Getting Familiar with the IIR Filter’s Generated VHDL Code” on page 2-60

“Verifying the IIR Filter’s Generated VHDL Code” on page 2-62

Designing an IIR Filter in FDATool

This tutorial guides you through the steps for designing an IIR filter,
generating Verilog code for the filter, and verifying the Verilog code with a
generated test bench.

This section guides you through the procedure of d esigning and creating
a filter for an IIR filter. This section assumes you are familiar with the
MATLAB user interface and the Filter Design & Analysis Tool (FDATool).

2-48

1 Start the MATLAB software.

2 Set your current folder to the folder you created in “Creating a Folder for

Your Tutorial Files” on page 2-2.

IIR Filter Tutorial

3 Start the FDATool by entering the fdatool command in the MATLAB

Command Window. The Filter Design & Analysis Tool dialog box appears.

4 In the Filter Design & Analysis Tool dialog box, set the following filter

options:

2-49

2 Tutorials: Generating HDL Code for Filters

Option

Response Type

Design Method

Filter Order

Frequency Specifications

5 Click Design Filter. The FDATool creates a filter for the specified design.

The following message appears in the FDATool status bar when the task
is complete.

Designing Filter... Done

For more information on designing filters with the FDATool, see “Using
FDATool with Filter Design Toolbox Software” in the Filter Design Toolbox
documentation.

Value

Highpass

IIR Butterworth

Specify order: 5

Units:

Fs: 48000

Fc: 10800

Hz

Quantizing the IIR Filter

You should quantize filters for HDL code generation. To quantize your filter,

2-50

1 Open the IIR filter design you created in “Designing an IIR Filter in

FDATool” on page 2-48 if it is not already open.

IIR Filter Tutorial

2 Click the Set Quantization Parameters button in the left-side toolbar.

The FDATool displays the Filter arithmetic list in the bottom half of
its dialog box.

2-51

2 Tutorials: Generating HDL Code for Filters

3 Select Fixed-point from the list. The FDATool displays the first of three

tabbed panels of its dialog box.

2-52

You use the quantization options to test the effects of various settings with
a g oa l of optimizing the quantized filter’s performance and accuracy.

4 Select the Filter Internals tab and set Rounding mode to Floor and

Overflow Mode to

Saturate.

5 Click Ap ply. The quantized filter appears as follows.

IIR Filter Tutorial

For more information on quantizing filters with the FDATool, see “Using
FDATool with Filter Design Toolbox Software” in the Filter Design Toolbox
documentation.

2-53

2 Tutorials: Generating HDL Code for Filters

Configuring and Generating the IIR Filter’s VHDL Code

After you quantize your filter, you are ready to configure coder options
and generate the filter’s VHDL code. This section guides you through the
procedure for starting the Filter Design HDL Coder GUI, setting some
options, and generating the VHDL code and a test bench for the IIR filter you
designed and quantized in “Designing an IIR Filter in FDATool” on page 2-48
and “Quantizing the IIR Filter” on page 2-50:

1 Start the Filter Design HDL Coder GUI by selecting Targets > Generate

HDL in the FDATool dialog box. The FDATool displays the Generate

HDL dialog box.

2-54

2 In the Name text box of the Target pane, type iir.Thisoptionnamesthe

VHDL entity and the file that will contain the filter’s VHDL code.

IIR Filter Tutorial

3 Select the Global settings tab of the GUI. Then select the General tab of

the Additional settings section.

In the Comment in header text box, type

Tutorial - IIR Filter.The

coder adds the comment to the end of the header comment block in each
generated file.

4 Select the Ports tab. The Ports pane appears.

5 Clear the check box for the Add output register option. The Ports pane

should now appear as in the following figure.

2-55

2 Tutorials: Generating HDL Code for Filters

2-56

6 Select the Advanced tab. The Advanced pane appears.

IIR Filter Tutorial

7 Select the Use ’rising_edge’ for registers option. The Advanced pane

should now appear as in the following figure.

8 Click on the Test bench tab in the Generate HDL dialog box. In the File

name text box, replace the default name with

iir_tb.Thisoptionnames

the generated tes t bench file.

2-57

2 Tutorials: Generating HDL Code for Filters

2-58

9 In the Generate HDL dialog box, click Generate to start the code

generation process. When code generation completes, click OK to close
the dialog box.

The coder displays the following messages in the MATLAB Command
Window as it generates the filter and test bench VHDL files:

### Starting VHDL code generation process for filter: iir

### Starting VHDL code generation process for filter: iir

### Generating: H:\hdlsrc\iir.vhd

### Starting generation of iir VH DL entity

### Starting generation of iir VH DL architecture

### Second-order section, # 1

### Second-order section, # 2

### First-order section, # 3

### HDL latency is 1 samples

### Successful completion of VHDL code generation process for filter: iir

### Starting generation of VHDL T est Bench

### Generating input stimulus

### Done generating input stimulus; length 2172 samples.

### Generating Test bench: H:\hdlsrc\filter_tb.vhd

### Please wait ...

### Done generating VHDL Test Ben ch

### Starting VHDL code generation process for filter: iir

### Starting VHDL code generation process for filter: iir

### Generating: H:\hdlsrc\iir.vhd

### Starting generation of iir VH DL entity

### Starting generation of iir VH DL architecture

### Second-order section, # 1

### Second-order section, # 2

### First-order section, # 3

### HDL latency is 1 samples

### Successful completion of VHDL code generation process for filter: iir

IIR Filter Tutorial

As the messages indicate, the coder creates the folder hdlsrc under your
current working folder and places the files

iir.vhd and iir_tb.vhd in

that folder.

Observe that the messages include hyperlinks to the generated code and
test bench files. By clicking on these hyperlinks, you can open the code files
directly into the MATLAB Editor.

The generated VHDL code has the following characteristics:

• VHDL entity named

iir.

• Registers that use asynchronous resets when the reset signal is active

high (1).

• Ports have the following default names:

VHDL Port Name

Input

Output

filter_in

filter_out

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2 Tutorials: Generating HDL Code for Filters

VHDL Port Name

Clock input

Clock enable input

Reset input

• An extra register for handling filter input.

clk

clk_enable

reset

• Clock input, clock enable input and reset ports are of type

and data input and output ports are of type STD_LOGIC_VECTOR.

• Coefficients are named

starting with 1.

• Type safe representation is used when zeros are concatenated:

& '0'...

• Registers are generated with the

statement

• The postfix string

The generated test bench:

• Is a portable VHDL file.

• Forces clock, clock enable, and reset input signals.

• Forces the clock enable input signal to active high.

• Drives the clock input signal high (1) for 5 nanoseconds and low (0) for

5 nanoseconds.

• Forces the reset signal for two cycles plus a hold time of 2 nanoseconds.

• Applies a hold time of 2 nanoseconds to data input signals.

• For an IIR filter, appl ies impulse, step, ramp, chirp, and white noise

stimulus types.

ELSIF clk'event AND clk=' 1' THEN.

coeffn,wheren is the coefficient number,

rising_edge function rather than the

_process is appended to process names.

STD_LOGIC

'0'

2-60

Getting Familiar with the IIR Filter’s Generated VHDL Code

Get familiar with the filter’s generatedVHDLcodebyopeningandbrowsing
through the file

iir.vhd inanASCIIorHDLsimulatoreditor:

IIR Filter Tutorial

1 Open the gene rated VHDL filter file iir.vhd.

2 Search for iir. This line identifies the VHDL module, using the string

you specified for the Name option in the Target pane. See step 2 in
“Configuring and Generating the IIR Filter’s VHDL Code” on page 2-54.

3 Search for Tutorial. This is where the coder places the text you entered

for the Comment in header option. See step 5 in “Configuring and
Generating the IIR Filter’s VHDL Code” on page 2-54.

4 Search for HDL Code. This section lists coder options you modified

in“Configuring and Generating the IIR Filter’s VHDL Code” on page 2-54.

5 Search for Filter Settings. This section of the VHDL code describes

the filter design and quantization settings a s you specified in “Designing
an IIR Filter in FDATool” on page 2 -48 and “Quantizing the IIR Filter”
on page 2-50.

6 Search for ENTITY. This line names the VHDL entity, using the string

you specified for the Name option in the Target pane. See step 2 in
“Configuring and Generating the IIR Filter’s VHDL Code” on page 2-54.

7 Search for PORT.ThisPORT declaration defines the filter’s clock, clock

enable, reset, and data input and output ports. The ports for clock, clock
enable, reset, and data input and output signals are named with default
strings.

8 Search for CONSTANT. This is where the coefficients are defined. They are

named using the default naming scheme,

coeff_xm_sectionn,wherex is a

or b, m is the coefficient number, and n is the section number.

9 Search for SIGNAL. This is where the filter’s signals are defined.

10 Search for input_reg_proce ss.ThePROCESS block name

input_reg_process includes the default PROCESS block postfix string
_process. Thisiswherefilterinputisreadfromaninputregister. Code

for this register is generated by default. In step 7 in “Configuring a nd
Generating the Basic FIR Filter’s VHDL Code” on page 2-8, you cleared
the Add output register option, but left the Add input register option
selected.

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2 Tutorials: Generating HDL Code for Filters

11 Search for IF reset. This is where the reset signa l is asserted. The default,

active high (1), was specified. Also note that the
default asynchronous reset style when generating VHDL code for registers.

12 Search for ELSIF. This is where the VHDL code checks for rising edges

when the filter operates on registers. The
as you specified in the Advanced pane of the Generate HDLdialo g box.
See step 10 in “Configuring and Generating the IIR Filter’s VHDL Code”
on page 2-54.

13 Search for Section 1. This is where second-order section 1 data is filtered.

Similar sections of VHDL code apply to another second-order section and
a first-order section.

14 Search for filter_out. Thisiswherethefilterwritesitsoutputdata.

Verifying the IIR Filter’s Generated VHDL Code

This sections explains how to verify the IIR filter’s generated VHDL code
with the generated VHDL test bench. Although this tutorial uses theMentor
Graphics ModelSim simulator as the tool for compiling and simulating the
VHDL code, you can u se any HDL simulation tool package.

PROCESS block applies the

rising_edge function is used

2-62

To verify the filter code, complete the following steps:

1 Start your s imulator. When you start theMentor Graphics ModelSim

simulator, a screen display similar to the following appears.

IIR Filter Tutorial

2 Set the current folder to the folder that contains your generated VHDL

files. For example:

cd hdlsrc

3 If necessary, create a design library to store the compiled VHDL entities,

packages, architectures, and configurations. In theMentor Graphics
ModelSim simulator, you can create a design library with the

vlib

command.

vlib work

4 Compile the generated filter and test bench V HDL files. In the Mentor

Graphics ModelSim simulator, you compile VHDL code with the

vcom

command. The following the commands compile the filter and filter test
bench VHDL code.

vcom iir.vhd
vcom iir_tb.vhd

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2 Tutorials: Generating HDL Code for Filters

The following screen display shows this command sequence and
informational m essages displayed during compilation.

2-64

5 Load the test bench for simulation. The procedure for doing this varies

depending on the simulator you are using. In the Mentor Graphics
ModelSim simulator, you load the test bench for simulation with the
command. For example:

vsim w

ork.iir_tb

vsim

IIR Filter Tutorial

The following display shows the results of loading work.iir_tb with the

vsim command.

6 Open a d isplay window for m o nitoring the simulation as the test bench

runs. For example, in the Mentor Graphics ModelSim simulator, you can
use the following command to open a wave window to view the results of
the simulation as HDL waveforms.

addwave*

2-65

2 Tutorials: Generating HDL Code for Filters

The following wave window displays.

2-66

7 To start running the simulation, issue the appropriate command for your

simulator. For example, in theMentor Graphics ModelSim simulator, you
can start a simulation with the

run command.

IIR Filter Tutorial

The following display shows the run -all command being used to start a
simulation.

As your test bench simulation runs, w atch for error messages. If any
error messages appear, you must interpret them as they pertain to your
filter design and the HDL code generation options you selected. You m ust
determine whether the results are expected based on the customizations
you specified when generating the filter VHDL code.

Note

• The warning messages that note

Time: 0 ns in the p receding display

are not errors and you can ignore them.

• The failure message that appears in the preceding display is not

flagging an error. If the message includes the string
the test bench has successfully run to completion. The

Test Complete,

Failure part of

the message is tied to the mechanism that the coder uses to end the
simulation.

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2 Tutorials: Generating HDL Code for Filters

The following wave window shows the simulation results as HDL
waveforms.

2-68

3

Generating HDL Code for a Filter Design

• “Overview of Generating HDL Code for a Filter Design” on page 3-2

• “Opening the G ene rate HDL Dialog Box” on page 3-4

• “What Is Generated by Default?” on page 3-14

• “What Are Your HDL Requirements?” on page 3-19

• “Setting the Target Language” on page 3-25

• “Setting the Names and Location for Generated HDL Files” on page 3-26

• “Customizing Reset Specifications” on page 3-33

• “Customizing the HDL Code” on page 3-37

• “Capturing Code Generation SettingstoaScript”onpage3-85

• “Generating Code for Multirate Filters” o n page 3-86

• “Generating Code for Cascade Filters” on page 3-93

• “Generating Code for Polyphase Sample Rate Converters” on page 3-97

• “Generating Code for Multirate Farrow Sample Rate Converters” on page

3-101

• “Generating Code for Single-Rate Farrow Filters” on page 3-105

• “Customizing the Test Bench” on page 3-112

• “Generating the HDL Code” on page 3-142

• “Generating Scripts for EDA Tools” on page 3-143

3 Generating HDL Code for a Filter Design

Overview of Generating HDL Code for a Filter Design

ConsiderthefollowingprocessasyoupreparetousetheGenerateHDLdialog
box to generate VHDL code for your quantized filter:

1 Open the Generate HDL dialog box.

2 Review what the coder generates by default.

3 Assess whether the default settings meet your application requirements. If

theydo,skiptostep6.

4 Review the customization checklist available in “What Are Your HDL

Requirements?” on page 3-19 and identify required customizations.

5 Modify the Generate HDL dialog box options to address your application

requirements, as described in the sections beginning with “Settin g the
Target Language” on page 3-25.

6 Generate the filter’s HDL code and test bench.

3-2

Overview of Generating HDL Code for a Filter Design

The following figure shows the steps in a flow diagram.

Open generate

HDL dialog

Review

default output

Meets

requirements?

Yes

Generate HDL filter

code and test bench

Done

No

Review customization

Modify dialog

checklist

settings

3-3

3 Generating HDL Code for a Filter Design

Opening the Generate HDL Dialog Box

In this section...

“Opening the Generate HDL Dialog Box from FDATool” on page 3-4

“Opening the Generate HDL Dialog Box from the filterbuilder GUI” on
page 3-9

“Opening the Generate HDL Dialog B ox Using the fdhdltool Command”
on page 3-11

Opening the Generate HDL Dialog Box from F DATool

To open the initial Generate HDL dialog box from FDATool, do the following:

1 Enter the fdatool command at the MATLAB command prompt. The

FDATool displays its initial dialog box.

3-4