Mathworks EDA SIMULATOR LINK 3 Reference

Download

EDA Simulator Link

Reference

™3

How to Contact The MathWorks

www.mathworks. comp.soft-sys.matlab Newsgroup www.mathworks.com/contact_TS.html T echnical Support

suggest@mathworks.com Product enhancement suggestions bugs@mathwo doc@mathworks.com Documentation error reports service@mathworks.com Order status, license renewals, passcodes info@mathwo

com

rks.com

Web

Bug reports

Sales, prici

ng, and general information

508-647-7000 (Phone)

508-647-7001 (Fax)

The MathWorks, Inc. 3 Apple Hill Drive Natick, MA 01760-2098

For contact information about worldwide offices, see the MathWorks Web site.

EDA Simulator Link™ Reference

The software described in this document is furnished under a license agreement. The software may be used or copied only under the terms of the license agreement. No part of this manual may be photocopied or reproduced in any form without prior written consent from The MathW orks, Inc.

FEDERAL ACQUISITION: This provision applies to all acquisitions of the Program and Documentation by, for, or through the federal government of the United States. By accepting delivery of the Program or Documentation, the government hereby agrees that this software or documentation qualifies as commercial computer software or commercial computer software documentation as such terms are used or defined in FAR 12.212, DFARS Part 227.72, and DFARS 252.227-7014. Accordingly, the terms and conditions of this Agreement and only those rights specified in this Agreement, shall pertain to and govern theuse,modification,reproduction,release,performance,display,anddisclosureoftheProgramand Documentation by the federal government (or other entity acquiring for or through the federal government) and shall supersede any conflicting contractual terms or conditions. If this License fails to meet the government’s needs or is inconsistent in any respect with federal procurement law, the government agrees to return the Program and Docu mentation, unused, to The MathWorks, Inc.

Trademarks

MATLAB and Simulink are registered trademarks of The MathWorks, Inc. See

www.mathworks.com/trademarks for a list of additional trademarks. Other product or brand

names may be trademarks or registered trademarks of their respective holders.

Patents

The MathWorks products are protected by one or more U.S. patents. Please see

www.mathworks.com/patents for more information.

Revision History

August 2003 Online only New for Version 1 (Release 13SP1) February 2004 Online only Updated for Version 1.1 (Release 13SP1) June 2004 Online only Updated for Version 1.1.1 (Release 14) October 2004 Online only Updated for Version 1.2 (Release 14SP1) December 2004 Online only Updated for Version 1.3 (Release 14SP1+) March 2005 Online only Updated for Version 1.3.1 (Release 14SP2) September 2005 Online only Updated for Version 1.4 (Release 14SP3) March 2006 Online only Updated for Version 2.0 (Release 2006a) September 2006 Online only Updated for Version 2.1 (Release 2006b) March 2007 Online only Updated for Version 2.2 (Release 2007a) September 2007 Online only Updated for Version 2.3 (Release 2007b) March 2008 Online only Updated for Version 2.4 (Release 2008a) October 2008 Online only Updated for Version 2.5 (Release 2008b) March 2009 Online only Updated for Version 2.6 (Release 2009a) September 2009 Online only Updated for Version 3.0 (Release 2009b) March 2010 Online only Updated for Version 3.1 (Release 2010a)

Block Reference

HDL Cosimulation ................................. 1-2

Contents

FPGA Implementations

Virtual Platform Simulation

............................ 1-3

........................ 1-4

Blocks — Alphabetical List

Function Reference

HDL Cosimulation ................................. 3-2

FPGA Implementations

Virtual Platform Simulation

............................ 3-4

........................ 3-5

Functions — Alphabetical List

Index

vi Contents

Block Reference

HDL Cosimulation (p. 1-2) Describes the EDA Simulator Link™

FPGA Implementations (p. 1-3) Describes the EDA Simulator

Virtual Platform Simulation (p. 1-4) Describes the EDA Simulator Link

Simulink blocks available for use with HDL cosimulation

Link Simulink blocks available for use with generating FPGA implementations

Simulink blocks available for use with generating Virtual Platform simulations

1 Block Reference

HDL Cosimulation

HDL Cosimulation Cosimulate hardware component by

communicating with HDL module instance executing in HD L simulator

To VCD File Generate value change dump (VCD)

file

1-2

FPGA Implementations

Currently, there are no EDA Simulator Link Simulink blocks available for use with generating FPGA implementations.

FPGA Implementations

1-3

1 Block Reference

Virtual Platform Simulation

Currently, there are no EDA Simulator Link Simulink blocks available for use with generating Virtual P latform simulations.

1-4

Blocks — Alphabetical List

HDL Cosimulation

Purpose Cosimulate hardware component by communicating with HDL module

instance executing in HDL simulator

Library EDA Simulator Link

Description The HDL Cosimulation block cosimulates a hardware component by

applying input signals to and reading output signals from an HDL model under simulation in the HDL simulator. You can use this b lock to model a source or sink device by configuring the block with input or output ports only.

The tabbed panes on the block’s dialog box let you configure:

• Block input and output ports that correspond to signals (including

internal signals) of an HDL module. You must specify a sample time for each output port; you can also specify a data type for each output port.

• Type of communication and communication settings used to exchange

data between simulators.

2-2

• The timing relationship between units of simulation time in Simulink

and the HDL simulator.

• Rising-edge or falling-edge clocks to apply to your model (Incisive and

ModelSim users only; Discovery users see can specify the period for each clock signal.

• Tcl commands to run before and after the simulation (Incisive and

ModelSim users only; Discovery users see

launchDiscovery). You

launchDiscovery).

The HDL Cosimulation Block Panes

The Ports pane provides fields for mapping signals of your HDL design to input and output ports in your block. The signals can be at any level of the HDL design hierarchy.

The Timescales pane lets you choose an optimal timing relationship between Simulink and the HDL simulator. You can configure either of the following timing relationships:

HDL Cos imulation

• Relative timing relationship (Simulink seconds correspond to an HDL

simulator-defined tick interval)

• Absolute timing relationship (Simulink seconds correspond to an

absolute unit of HDL simulator time)

The Connection pane specifies the communications mode used between Simulink and the HDL simulator. If you use TCP socket communication, this pane provides fields for specifying a socket port and for the host name of a remote computer running the HDL simulator. The Connection pane also provides the o ption for bypassing the cosimulation block during Simulink simulation.

The Clocks pane lets you create optional rising-edge and falling-edge clocks that apply stimuli to your cosimulation model.

The Tcl pane provides a way of specifying too ls command language (Tcl) commands to be executed before and after the HDL simulator simulates the HDL component of your Simulink model. You can use the Pre-simulation commands field on this pane for simulation initialization and startup operations, but you cannot use it to change simulation state.

Note You must make sure that signals being used in cosimulation have read/write access. This rule applies to all signals on the Ports,

Clocks,andTcl panes.

Incisive and ModelSim users: Verify such access through the HDL

simulator—see product documentation for details.

Discovery users: A tab file is included in the simulation via the required

launchDiscovery property "AccFile".

2-3

HDL Cosimulation

Dialog Box

The Block Parameters dialog box consists of the following tabbed panes of configuration options:

• “Ports Pane” on page 2-4

• “Connection Pane” on page 2-11

• “Timescales Pane” on pag e 2-15

• “Clocks Pane” on page 2-19 (Incisive and ModelSim users only)

• “Tcl Pane” on page 2-22 (Incisive and ModelSim users only)

Ports Pane

Specify fields for mapping signals of your HDL design to input and output ports in your block. Simulink deposits an input port signal on an HDL simulator signal at the signal’s sample rate. Conversely, Simulink reads an output port signal from a specified HDL simula tor signal at the specified sample rate.

In general, Simulink handles port sample periods as follows:

• If you connect an input port to a signal that has an explicit sample

period, based on forward propagation, Simulink applies that rate to the port.

• If you connect an input port to a signal that does not have an explicit

sample period, Simulink assigns a samp le period that is equal to the least common multiple (LCM) of all identified input port sample periods for the model.

2-4

• After Simulink sets the input port sample periods, it applies

user-specified output sample times to all output ports. You must specify an explicit sample time for each output port.

In addition to specifying output port sample times, you can force the fixed-point data types on output ports. For example, setting the

Data Type property of an 8-bit output port to Fraction Length property to

5 wouldforcethedatatypetosfix8_En5.

Signed and setting its

HDL Cos imulation

You can not force width; the width is always inherited from the HDL simulator.

Note The Data Type and Fraction Length properties apply only to the following signals:

• VHDL signals of any logic type, such as

STD_LOGIC_VECTOR

• Verilog signals of wire or reg type

You can set input/output ports in the Ports panealso. Todoso,specify port as both input and output (example shown for use with ModelSim).

STD_LOGIC or

2-5

HDL Cosimulation

2-6

If your model contains purely combinational paths, you can select Enable direct feedthrough for HDL design with pure combinational datapath to eliminate the on e output-sample delay that occurs with using EDA Simulator Link blocks and Simulink. For more information on block simulation latency and using the direct feedthrough feature to eliminate it, see “Eliminating Block Simulation Latency”.

HDL Cos imulation

Discovery Users You may not enable direct feedthrough if your design

contains mixed HDL (VHDL and Verilog). If you do, EDA Simulator LinkwilldisplayanerrorintheHDLsimulator.

The list at the center of the pane displays HDL signals corresponding to ports on the HDL Cosimulation block. Maintain this list with the buttons on the left of the pane:

• Auto Fill — Transmit a port information request to the HDL

simulator. The port information request returns port names and information from an HDL model (or module) under simulation in the HDL simulator and automatically enters this information into the ports list. See “Obtaining Signal Information Automatically from the HDL Simulator” for a detailed description of this feature.

• New — Add a new signal to the list and select it for editing.

• Delete — Remove a signal from the list.

• Up — Move the selected signal up one position in the list.

• Down — Move the selected signal down one position in the list.

To commit edits to the Simulink model, you must also click Apply after selecting parameter values.

Note When you import VHDL signals from the HDL simulator , EDA Simulator Link returns the signal names in all capitals.

To edit a signal name, double-click on the name. Set the signal properties on the same line and in the appropriate columns. The properties of a signal are as follows.

2-7

HDL Cosimulation

Full HDL Name

Specifies the signal path name, using the HDL simulator path name syntax. For example (for use with Incisive), a path name for aninputportmightbe any level of the HD L design hierarchy. The HDL Cosimulation block port corresponding to the signal is labeled with the Full HDL Name.

For rules on specifying signal/port and module path specifications in Simulink, see “Specifying HDL Signal/Port and Module Paths for Cosimulation”.

Copying Signal Path Names (For Incisive and ModelSim Users) You can copy signal path names directly from the HDL

simulator wave window and paste them into the Full HDL Name field, using the standard copy and paste commands in the

HDL simulator and Simulink. You must use the Path.Name view and not Db::Path.Name view. After pasting a signal path name into the Full HDL Name field, you must click the Apply button to complete the paste operation and update the signal list.

manchester.samp.Thesignalcanbeat

2-8

I/O Mode

Select either and ModelSim users only).

Input designates signals of your HDL module that Simulink

will drive. Simulink deposits values on the specified the HDL simulator signal at the signal’s sample rate.

Input, Output, or both ("both" applies to Incisive

HDL Cos imulation

Note When you define a block input port, make sure that only

one source is set up to drive input to that signal. For example, you should avoid defining an input port that has multiple instances. If m ultiple sources drive input to a single signal, your simulation model may produce unexpected results.

Output designates signals of your HDL module that Simulink

will read. For output signals, you must specify an explicit sample time. You can also specify any data type (except width). For details on specifying a data type, see Date Type and Fraction Length in a following section.

Because Simulink signals do not have the semantic of tri-states (there is no ’Z’ value), you will gain no benefit by connecting to a bidirectional HDL signal directly. To interface with bidirectional signals, you can first interface to the input of the output driver, then the enable of the output driver and the output of the input driver. This approach le av es the actual tri-state buffer in HD L where resolution functions can handle interfacing with other tri-state buffers.

Sample Time

This property becomes available only when you specify an output signal. You must specify an explicit sample time.

Sample Time represents the time interva l between consecutive samples applied to the output port. The default sample time is The exact interpretation of the output port sample time depends on the settings of the Timescales pane of the HDL Cosimulation block.Seealso“Understandingthe Representation of Simulation Time”.

Data Type Fraction Length

These two related parameters apply only to output signals.

2-9

HDL Cosimulation

The Data Type property is enabled only for output signals. You can direct Simulink to determine the data type, or you can assign an explicit data type (with option fraction length). By explicitly assigning a data type, you can force fixed-point data types on output ports of an HDL Cosimulation block.

The Fraction Length property specifies the size, in bits, of the fractional part of the signal in fixed-point representation.

Fraction Length becomes available if you do not set the Data Type property to

The data type specification for an output port depends on the signal width and by the Data Type and Fraction Length properties of the signal.

Note The Data Type and Fraction Length properties apply only to the following signals:

Inherit.

2-10

• VHDL signals of any logic type, such as

STD_LOGIC_VECTOR

• Verilog signals of wire or reg type

To assign a port data type, set the Data Type and Fraction Length properties as follows:

• Select

to determine the data type.

This property defaults to the Fraction Length edit field becomes unavailable.

Simulink always double checks that the word-length back propagated by Simulink matches the word length queried from the H D L simulator. If they do not match, Simulink generates an error message. For example, if you connect a Signal

Inherit from the Data Type list if you want Simulink

Inherit.WhenyouselectInherit,

STD_LOGIC or

HDL Cos imulation

Specification block to an output, Simulink will force the data type specified by Signal Specification block on the output port.

If Simulink cannot determine the data type of the signal connected to the output port, it will query the HDL simulator for the data type of the port. As an exam ple, if the HDL simulator returns the VHDL data type signal of size

N bits, the data type ufixN is forced on the output

port. (The implicit fraction length is 0.)

STD_LOGIC_VECTOR for a

• Select

Signed from the Data Type list if you want to explicitly

assign a signed fixed point data type. When you select the Fraction Length edit field becomes available. EDA Simulator Link assigns the port a fixed-point type where

N is the signal width and F is th e Fraction Length.

For example, if you specify Data Type as Fraction Length of

data type to Type set to forces the data type to

• Select

Unsigned from the Data Type list if you want to

explicitly assign an unsigned fixed point data type When you select

Unsigned,theFraction Length edit field becomes

available. EDA Simulator Link assigns the port a fixed-point type

ufixN_EnF,whereN is the signal width and F is the

Fraction Length.

For example, if you specify Data Type as Fraction Length of data type to Type set to forces the data type to

Connection Pane

Signed,

sfixN_EnF,

Signed and a

5 for a 16-bit signal, Simulink forces the

sfix16_En5. ForthesamesignalwithaData

Signed and Fraction Length of -5, Simulink

sfix16_E5.

Unsigned and a

5 for a 16-bit signal, Simulink forces the

ufix16_En5. ForthesamesignalwithaData

Unsigned and Fraction Length of -5 , Simulink

ufix16_E5.

This figure shows the default configuration of the Connection pane (example shown is for use with Discovery). The block defaults to a

2-11

HDL Cosimulation

shared memory configuration for communication between Simulink and the H DL simulator, when they run on a single computer.

2-12

If you select TCP/IP socket mode communication, the pane displays additional properties, as shown in the following figure.

HDL Cos imulation

Connection Mode

If you want to bypass the HDL simulator when you run a Simulink simulation, use these options to specify what type of simulation connection you want. Select one of the following options:

• Full Simulation: Confirm interface and run HDL simulation

(default).

• Confirm Interface Only : Connect to the HDL simulator and

check for proper signal names, dimensio ns , and data types, but do not run HD L simulation.

• No Connection: Do not communicate with the HDL simulator.

The HDL simulator does not need to be started.

With the second and third options, the EDA Simulator Link cosimulation interface does not communicate with the HDL simulator during Simulink simulation.

2-13

HDL Cosimulation

The HDL Simulator is running on this computer

Connection method

Host name

Select this option if you want to run Simulink and the HDL simulator on the same computer.Whenbothapplicationsrunon the same computer, you have the choice of using shared memory or TCP sockets for the communication channel between the two applications. If y ou do not select this option, only TCP/IP socket mode is available, and the Connection method list becomes unavailable.

This list becomes available when you selectThe HDL Simulator is running on this computer. Select Simulink and the HDL simulator to communicate via a designated TCP/IP socket. Select the HDL simulator to communicate via shared memory. For mor e information on these connection methods, see “Communications for HDL Cosimulation”.

If you run Simulink and the HDL simulator on different computers, this text field becomes available. The field specifies the host name of the computer that is running your HDL simulation in the HDL simulator.

Shared memory if you want Simulink and

Socket if you want

2-14

Port number or service

IndicateavalidTCPsocketportnumberorserviceforyour computer system (if not using shared memory). For information on choosing TCP socket ports, see “Choosing TCP/IP Socket Ports”.

Show connection info on icon

When you select this option, Simulink indicates information about the selected communication method and (if applicable) communication options information on the H DL Cosimulation block icon. If you select shared memory, the icon displays the string icon displays the string Socket and displays the host name and port number in the format

SharedMem. If you select TCP socket communication, the

hostname:port.

HDL Cos imulation

In a model that has multiple HDL Cosimulation blocks, with each communicating to different instances of the HDL simulator in different modes, this information helps to distinguish between different cosimulation sessio ns.

Timescales Pane

The Timescales pane of the HDL Cosimulation block parameters dialog bo x lets you choose a timing relationship between Simulink and the HDL simulator, either manually or automatically. The following figure shows the default settings of the Timescales pane (example shown for use with I ncisive).

The Timescales pane specifies a correspondence between one second of Simulink time and some quantity of HDL simulator time. This quantity of HDL simulator time can be expressed in one of the following ways:

2-15

HDL Cosimulation

• Using relative timing m ode. EDA Simulator Link defaults to relative

timing mode.

• Using absolute timing mode

For more information on calculating relative and absolute timing modes, see “Defining the Simulink and HDL Simulator Timing Relationship”.

For detailed information o n the rel ationship between Simulink and the HDL simulator during cosimulation, and on the operation of relative and absolute timing modes, see “Understanding the Representation of Simulation Time”.

The following sections describe how to specify the timing relationship, either automatically or manually.

Automatically Specifying the Timing Relationship

You can have the E DA Simulator Link software calculate the timing relationship for you by perform ing the following steps:

1 Verify that the HDL simulator is running. EDA Simulator Link

software can get the resolution limit of the HDL simulator only when that simulator is running.

2-16

2 Click on Auto Timescale.

The following graphic shows the result of clicking Auto Timescale in the Timescales pane of the HD L Cosimulation block in the Manchester Receiver demo (example shown for use with ModelSim).

EDA Simulator Link software analyzes all the clock and port signal rates from the HD L Cosimulation block when it calculates the scale factor.

HDL Cos imulation

Note EDA Simulator Link cannot automatically calculate a sample

timescale based on any signals driven via Tcl commands or in the HDL simulator. The link software cannot perform such calculations because it cannot know the rates of these signals.

Thelinksoftwarereturnsthesamplerateineithersecondsor ticks. If the results are in seconds, then the link software was able to resolve the timing differences in favor of fidelity (absolute time). If the results are in ticks, then the link software was best able to resolve the timing differences in favor of efficiency (relative time).

Each time you press Auto Timescale, the EDA Simulator Link software opens an informational GUI display that explains the results of A u t o Timescale. If the link software cannot calculate a timescale for the given sample times, use the information in this dialog box to adjust your sample times.

Click Show Details... for information specific to your model’s signals. Click OK to exit the informational dialog box.

ck Apply to commit your changes.

3 Cli

2-17

HDL Cosimulation

Note EDA Simulator Link does not support Auto Timescale calculated

from frame-based signals.

For more on the timing relationship between the HDL simulator and Simulink, see “Understanding the Representation of Simulation Time”.

Manually Specifying a Relative Timing Relationship

To manually configure relative timing mode for a cosimulation, perform the following steps:

1 Select the Timescales tab of the HDL Cosimulation block

parameters dialog box.

2 Verify that Tick, the default setting, is selected. If it is not, then

select it from the list on the right.

3 Enter a scale factor in the text box on the left. The default scale

factor is 1. For example, the next figure, shows the Timescales pane configured for a relative timing correspondence of 10 HDL simulator ticks to 1 Simulink second.

2-18

4 Click Apply to commit your changes.

Manually Specifying an Absolute Timing Relationship

To manually configure absolute timing mode for a cosimulation, perform the following steps:

1 Select the Timescales tab of the HDL Cosimulation block

parameters dialog box.

2 Select a unit of absolute time from the list on the right. The

units available include

fs (femtoseconds), ps (picoseconds), ns

(nanoseconds), us (microseconds), ms (milliseconds), and s (seconds).

HDL Cos imulation

3 Enter a scale factor in the text box on the left. The default scale

factor is 1. For example, in the next figure, the Timescales pane is configured for an absolute timing correspondence of 1 HDL simulator second to 1 Simulink second.

4 Click Apply to commit your changes.

Clocks Pane

Discovery Users The Clocks pane is not available on the

HDL Cosimulation block for use with Synopsys Discovery. See

launchDiscovery for instructions on adding clocks to your cosimulation

model.

You can create optional rising-edge and falling-edge clocks that apply stimuli to your cosimulation model. To do so, use the Clo cks pane of the HDL Cosimulation blo ck (example shown for use with Incisive).

2-19

HDL Cosimulation

2-20

The scrolling list at the center of the pane displays HDL clocks that drive values to the HDL signals that you are modeling, using the deposit method.

Maintain the list of clock signals with the buttons on the left of the pane:

• New — Add a new clock signal to the list and select it for editing.

• Delete — Remove a clock signal from the list.

• Up — Move the selected clock signal up one position in the list.

• Down — Move the selected clock signal dow n one position in the list.

To commit edits to the Simulink model, you must also click Apply.

A clock signal has the following properties.

HDL Cos imulation

Full HDL Name

Specify each clock as a signal path name, using the HDL simulator path name syntax. For example:

manchester.clk.

For information about and require ments for path specifications in Simulink, see “Specifying HDL Signal/Port and Module Paths for Cosimulation”.

Note You can copy signal path names directly from the HDL simulator wave window and paste them into the Full HDL Name field, using the standard copy and paste commands in the HDL simulator and Simulink. You must use the Path.Name view and not Db::Path.Name view. After pasting a signal path name into the Full HDL Name field, you must click the Apply button to complete the paste operation and update the signal list.

/manchester/clk or

Edge

Select falling-edge clock.

Period

You must either specify the clock period explicitly or accept the default period of

If you specify an explicit clock period, you must enter a sample time equal to or greater than 2 resolution units (ticks).

If the clock period (whether explicitly specified or defaulted) is not an even integer, Simulink cannot create a 50% duty cycle. Instead, the EDA Simulator Link software creates the falling edge at

(rounded down to the nearest integer).

Rising or Falling to specify either a rising-edge clock or a

clockperiod /2

2-21

HDL Cosimulation

Note The Clocks pane does not support vectored signals. Signals

must be logic types with 1 and 0 values.

For instructions on adding and editing clock signals, see “Creating Optional Clocks with the Clocks Pane of the HDL Cosimulation Block”.

Tcl Pane

Discovery Users The Tcl pane is not available on the HDL

Cosimulation block for use with Synopsys Discovery. See

launchDiscovery for instructions on issuing Tcl commands during a

cosimulation session.

Specify tools command language (Tcl)commandstobeexecutedbefore and after the HDL simulator simulates the HDL component of your Simulink model (example shown for use with Mode lSim ).

2-22

HDL Cos imulation

Pre-simulation commands

Contains Tcl commands to be executed before the HDL simulator simulates the HDL component of your Simulink model. You can specify one Tcl command per line in the text box or enter multiple commands per line by appending each command with a semicolon (;), the standard Tcl concatenation operator.

Use of this field can range from something as simple as a one-line echo command to confirm that a simulation is running to a complex script that performs an extensive simulation initialization and startup sequence.

Post-simulation commands

Contains Tcl commands to be executed after the HDL simulator simulates the HDL component of your Simulink model. You can specify one Tcl command per line in the text box or enter multiple commands per line by appending each command with a semicolon (;), the standard Tcl concatenation operator.

2-23

HDL Cosimulation

Creating a Tcl Script as an Alternative to Using the Tcl Pane

You can create a Tcl script that lists the Tcl commands you want to execute on the HDL simulator, either pre- or post-simulation.

Tcl Scripts for ModelSim Users

You can create a ModelSim DO file that lists Tcl commands a nd then specify that file with the ModelSim

do mycosimstartup.do

do mycosimcleanup.do

You can include the quit -f command in an after-simulation Tcl command string or DO file to force ModelSim to shut down at the end of a cosimulation session. To ensure that all other after-simulation Tcl commands specified for the modelwillexecute,specifyallafter simulation Tcl commands in a single cosimulation block and place at the end of the command string or DO file.

do comm and as follows:

quit

2-24

With the exception of

quit,thecommandstringorDOfilethatyou

specify cannot include commands that load a ModelSim project or modify simulator state. For example, they cannot include com mands such as

start, stop,orrestart.

Tcl Scripts for Incisive Users

You can create an HDL simulator Tcl script that lists Tcl commands and then specify that file with the HDL simulator

source command

as follows:

source mycosimstartup.script_extension

source mycosimcleanup.script_extension

HDL Cos imulation

You can include the exit command in an after-simulation Tcl script to force the HDL simulator to shut down at the end of a cosimulation session. To ensure that all other after-simulation Tcl commands specified for the model will execute, specify all after simulation Tcl commands in a single cosimulation block and place the command string or Tcl script.

exit at the end of

With the exception of the script that you specify cannot include commands that load an HDL simulator project or modify simulator state. For example, neither can include comm ands such as

The following example shows a Tcl script when the used with

after 1000 {ncsim -submit exit}

This next example is of a Tcl exit script to use when the -tcl argument was used with

after 1000 {exit}

hdlsimmatlab or hdlsimulink:

exit command, the command string or Tcl

run, stop,orreset.

-gui arg u m en t was

2-25

To VCD File

Purpose Generate value change dump (VCD) file

Library EDA Simulator Link

Description

The To VCD File block generates a VCD file that contains information about changes to signals connected to the block’s input ports and names the file with the specified file name. You can use VCD files during design verification in the following ways:

• For comparing results of multiple simulation runs, using the same or

different simulator environments

• As input to post-simulation analysis tools

2-26

• For porting areas of an existing design to a new design

Using the Block Parameters dialog box, you can specify the following parameters:

• Thefilenametobeusedforthegeneratedfile

• The number of blo ck input ports that are to receive signal data

• The timescale to relate Simulink sample times with HDL simulator

ticks

VCD files can grow very large for larger designs or smaller designs with longer simulation runs. Howev er, the only limitation on the size of a VCD file generated by the To VCD File block is the maximum number of signals (and symbols) supported, which is 9 4

ForadescriptionoftheVCDfileformat,see“VCDFileFormat”on page 2-29.

(830,584).

Dialog Box

To VCD File

Note The To VCD File block is integrated into the Simulink Signal &

Scope Manager. See the Simulink User’s Guide for more information on using the Signal & Scope Manager.

Graphically Displaying VCD File Data

You can graphically display VCD file data or analyze the data with postprocessing tools. For example, the ModelSim aVCDfiletoa window. Other examples of postprocessing include the extraction of data pertaining to a particular section of a design hierarchy or data generated during a specific time interval.

WLF file that you can view in a ModelSim wave

vcd2wlf tool converts

2-27

To VCD File

VCD file name

ThefilenametobeusedforthegeneratedVCDfile. Ifyouspecify afilenameonly,SimulinkplacesthefileinyourcurrentMATLAB folder. Specify a complete path name to place the generated file in a different location. If you specify the same name for multiple To VCD File blocks, Simulink automatically adds a numeric postfix to identify each instance uniquely.

Note If you want the generated file to have a .vcd file type extension, you must specify it explicitly.

Do not give the same file name to different VCD blocks. Doing so results in invalid VCD files.

Number of input ports

The number of block input ports on which signal data is to be collected. The block can handle up to 94 of which maps to a unique symbol in the VCD file.

(830,584) signals, each

2-28

In some cases, a single input port maps to multiple signals (and symbols). This multiple mapping occurs when the input port receives a multidimensional signal.

Because the VCD specification does not include multidim ensional signals, Simulink flattens them to a 1D vector in the file.

Timescale

Choose an optimal timing rel ati onship between Simulink and the HDL simulator.

The timescale options s pe cify a correspondence between one second of Simulink time and some quantity of HDL simulator time. You can express this quantity of HDL simulator time in one of the following ways:

To VCD File

• In relative terms (i.e., as some number of HDL simulator ticks).

In this case, the cosimulation operates in relative timing mode, which is the timing mode default.

VCD File Format

To use relative mode, select label in the HDL simulator, a nd enter the desired number of ticks in the edit box at 1 second in Simulink corresponds to. The default value is 1 Tick.

• In absolute units (such as milliseconds or nanoseconds). In this

case, the cosimulation operates in absolute timing mode.

To use absolute mode, select the desired resolution unit from the pop-up list at the label in the HDL simulator (available units are of resolution units in the edit box at 1 second in Simulink corresponds to. Then, set the value of the HDL simulator tick by selecting Tick is defined as and the resolution unit from the pop-up list at defined as.

The format of generated VCD files adheres to IEEE Std 1364-2001. The following table describes the format.

Generated VCD File Format

File Content

$date 23-Sep-2003 14:38:11 $end

fs, ps, ns, us, ms, s ), and enter the desired number

1, 10,or100 from the pop-up list at 1HDL

Tick from the pop-up list at the

Description

Data and time the file was generated.

$version EDA Simulator Link version 1.0 $ end

Version of the VCD block that generated the file.

2-29

To VCD File

Generated VCD File Format (Continued )

File Content

$timescale 1 ns $ end

$scope module manchestermodel $end

$var wire 1 ! Original Data [0] $end

$var wire 1 " Recovered Clock [0] $end

$var wire 1 # Recovered Data [0] $end

$var wire 1 $ Data Validity [0] $end

$upscope $end

Description

The time scale that was used during the simulation.

Thescopeofthemodule being dumped.

Variable definitions. Each definition associates a signal with character identification code (symbol).

The symbols are derived from printable characters in the ASCII character set from ! to ~.

Variable definitions also include the variable type (wire) and size in bits.

Marks a change to the next higher level in the HDL design hierarchy.

2-30

$enddefinitions $end

Marks the end of the header and definitions section.

Simulation start time.

Generated VCD File Format (Continued )

To VCD File

File Content

$dumpvars

0! 0" 0# 0$

$end

#630

. . . #1160

1# 1$

Description

Lists the values of all defined variables at time equals 0.

The starting point of logged value changes from checks of variable values made at each simulation time increment.

This entry indicates that at 63 nanoseconds, the value of signal

Original Data

changed from 0 to

At 116 nanoseconds the values of signals

Recovered Data

and Data Validity changed from 0 to 1.

$dumpoff

x! x" x# x$

Marks the end of the file by dumping the values of all variables as the value

2-31

To VCD File

Generated VCD File Format (Continued )

File Content

$end

Description

2-32

Function Reference

HDL Cosimulation (p. 3-2) Describes the EDA Simulator Link

MATLAB functions available for use with HDL cosimulation

FPGA Implementations (p. 3-4) Describes the EDA Simulator

Link MATLAB functions available for use with generating FPGA implementations

Virtual Platform Simulation (p. 3-5) Describes the EDA Simulator Link

MATLAB functions available for use with generating Virtual Platform simulations

3 Function Reference

HDL Cosimulation

breakHdlSim

configuremodelsim

dec2mvl

hdldaemon

hdlsimmatlab

hdlsimulink

launchDiscovery

matlabcp

matlabtb

matlabtbeval

mvl2dec

nclaunch

nomatlabtb

Execute stop command in HDL simulator from MATLAB

Configure ModelSim for use with EDA Simulator Link

Convert decimal integer to binary string

Control MATLAB server that supports interactions with HDL simulator

Load instantiated HDL design for verification with Cadence Incisive and MATLAB

Load instantiated HDL design for cosimulation with Cadence Incisive and Simulink

Launch Synopsys Discovery tools for use with Simulink and MATLAB using EDA Simulator Link software

Associate MATLAB component function with instantiated HDL design

Schedule MATLAB test bench session for instantiated HDL module

Call specified MATLAB function once and immediately on behalf of instantiated HDL module

Convert multivalued logic to decimal

Start and configure Cadence Incisive simulators for use with EDA Simulator Link software

End active MATLAB test bench and MATLAB component sessions

3-2

HDL Cosimulation

notifyMatlabServer

pingHdlSim

tclHdlSim

vsim

vsimmatlab

vsimulink

waitForHdlClient

Send HDL simulator event and process ID s to MATLAB server

Block cosimulation until HDL simulatorisreadyforsimulation

Execute Tcl command in Incisive or ModelSim simulator

Start and configure ModelSim for use with EDA Simulator Link

Load instantiated HDL module for verification with ModelSim and MATLAB

Load instantiated HDL module for cosimulation with ModelSim and Simulink

Wait until specified event ID is obtained or time-out occurs

3-3

3 Function Reference

FPGA Implementations

fpgamodelsetup

makefpgaproject

setupxilinxtools

Set Simulink m od el parameters for FPGA workflow

Generate Xilinx®ISE project and FPGA hardware-in-the-loop

Configure MATLAB environment for use with Xilinx FPGA workflow

3-4

Virtual Platform Simulation

Currently, there are no EDA Simulator L ink MATLAB functions available for use with generating Virtual P latform simulations.

Virtual Platform Simulation

3-5

3 Function Reference

3-6

Functions — Alphabetical List

breakHdlSim

Purpose Execute stop command in HDL simulator from MATLAB

Syntax breakHdlSim()

breakHdlSim('portNumber') breakHdlSim('portNumber','hostName')

Description breakHdlSim() executes a stop command on the HDL simulator on the

local host. Use this function to unblock the HDL simulator after the HDL simulator has loaded the simulation but before Simulink starts the simulation. If, after starting the simulation, you decide to add more signals to the waveform window, use this function to unblock the HDL simulator first. When you use the proper co nnection information to the HDL simulator.

breakHdlSim('portNumber') executes a stop command on the HDL

simulator on port portNumber.

breakHdlSim('portNumber','hostName') executes a stop command

on the HDL simulator on host hostName.

breakHdlSim, make sure that you specify

Examples Stop the HDL simulator that is currently running on the local host.

>> breakHdlSim()

Stop the HDL simulator that is currently running on port 1234.

>> breakHdlSim('1234')

Stop the HDL simulator that is currently running on port 1234 and host "mylinux".

>> breakHdlSim('1234', 'mylinux')

Required Properties

'LinkType' , 'appname'

Specifies e ither Simulink or MATLAB. A Simulink link session includes using the HDL Cosimulation block in a Simulink model for cosimulation with the HDL simulator. A MATLAB link session includes using MATLAB functions as callbacks for HDL simulator events.

matlabtb, matlabcp,andmatlabtbeval to employ

launchDiscovery to

4-21

launchDiscovery

'VerilogFiles', 'pathname'

'VhdlFiles', 'pathname'

'TopLevel', 'modulename'

'AccFile', 'filename'

Specifies the full or relative (to "RunDir") path to Verilog files. Specify as single string in double quotes or as cell array of filenames.

Only one of "VerilogFiles" and "VhdlFiles" is required; specify both for mixed language designs.

Specifies the full or relative (to "RunDir") path to VHDL files. Specify as single string in double quotes or as cell array of filenames.

Only one of "VerilogFiles" and "VhdlFiles" is required; specify both for mixed language designs.

Specifies the name of the top-level HDL module.

Specifies the name of the signal access file that gives cosimulated signals read/write/force access to the EDA Simulator Link application. See the Synopsys Discovery documentation (search for "PLI table") on how to create this file.

4-22

Common Optional Properties

'PreSimTcl', 'command'

Specifies Tcl commands to execute before starting the HDL simulation. Use this property for simple waveform generation statements for signals such as clocks, resets, and enables.

'PingTimeout', 'seconds'

For Simulink link sessions only. Specifies the number of seconds to wa it for the HDL simulator to launch before reporting back an error. To avoid waiting for the simulator to start, use the value of ’0’. This property defaults to ’60’ for

Xterm'

run m odes, and ’0’ for 'CLI' and 'GUI' run modes.

'Batch' and 'Batch with

launchDiscovery

'RunDir', 'dirname'

Specifies the folder from which to execute the compilation and launch scripts. This property defaults to an automatically created temporary folder.

'RunMode', 'modetype'

Specifies how to start the HDL simulator. This property accepts the following valid values:

•

'Batch': S tart the HDL simulator in the background with no

window.

•

'Batch with Xterm': Start the H DL simulator in the

background but show session in an Xterm.

•

'CLI': Start the HDL simulator in an interactive shell.

'GUI': Start the HDL simulator in the Synopsys DVE GUI.

•

This value defaults to

'RunTime', 'runtime'

'GUI'.

Amount of time to run the simulation for when running in ’Batch’ or ’B atch with Xterm’ run modes. You can specify a raw number (which uses the time resolution unit value) or a number with a time unit (one of { ’s’,’ms’,’us’,’ns’,’ps’,’fs’}). The default amount of run time is: ’’

For MATLAB link sessions only.

'VlogAnFlags', 'flagnames'

Specifies 'vlogan' flags.

'VhdlAnFlags', 'flagnames'

Specifies 'vhdlan' flags.

'UumCompFlags', 'flagnames'

Sets UUM-compatible compilation flags to 'vcs' .

'UumRunFlags', 'flagnames'

Sets UUM-compatible runtime flags to 'simv' .

4-23

launchDiscovery

Advanced Optional Properties

'CosimBlockList', 'blocklist'

'HostComm','commtype'

For Simulink links only. Specifies a cell array of HDL Cosimulation block instances that are bound to the HDL simulator about to be built and launched. This value defaults to all cosimulation blocks in the current model. Correct syntax is:

'CosimBlockList', { 'block1', block2', ... }

For Simulink link sessions only. Specifies the communications mechanism between Simulink and a local HDL simulator. This property accepts the following valid values:

•

'AutoGenSocketPort': Find an available TCP port on the

current host and program the CosimBlockList w ith that port. This is the default value for HostComm.

•

'SharedPipe': Program the CosimBlockList to use a shared

pipe connection.

4-24

•

'GetFromCosimBlock': Use whichever communication

parameters appear in any existing cosimulation block masks.

•

'<portnumber>': Progra m the CosimBlockList with a num eric

socket port value,

'<servicename>': Program the CosimBlockList with an OS

•

TCP/IP service name,

'<portnumber>',specifiedasastring.

'<servicename>',specifiedasastring.

Note launchDiscovery currently does not directly support remote host execution; see “Examples” on page 4-26 section for help in setting up remote connections.

'HostName', 'name'

Specifies a remote host name for cross-machine co-simulations with Simulink.

launchDiscovery

'SkipCompilation', true|false

When true, instructs the HDL simulator not to execute the compilation script. This value defaults to false.

'SkipLaunch', true|false

When true, instructs the H D L simulator not to execute the launch script. This value defaults to false.

'SkipScriptGeneration', true|false

When true, instructs HDL simulator no t to write the compilation and launch scripts. This value defaults to false.

'UserEnv,' 'arrayname'

Specifies a cell array of VAR=value environment variables for use by the compilation and launch scripts. Correct syntax is:

'UserEnv', { 'VAR1=val1', 'VAR2=val2', ... }

VG_GNU_PACKAGE Properties

The default GCC compiler used is the default VG_ GN U _P ACK AGE from a standard installation in the VCS tree. If you want to compile using a different version of GCC, you must specify the following properties.

'UseDefaultVgGnuPackage', true|false

Specifies using the default VG_GNU_PACKAGE in the VCS installation tree. See Synopsys documentation for the installation instructions. W hen you set the

UseDefaultVgGnuPackage

property to True, the function ignoresVgGnuPackage and

VgGnuGccVersion. To guarantee inter-operability of the link

application with the ModelSim soft wa re, keep this property set to

True. This value defaults to True.

'VgGnuPackage', 'dirpath'

Specifies the full directory path to a nondefault installation (an installation outside of the VCS tree) of VG_GNU_PACKAGE. This value defaults to

'none'.

4-25

launchDiscovery

'VgGnuGccVersion', 'version'

Typical use cases for these properties include:

• Use default GCC version in the default VG_GN U_PACKAGE

• Use default GCC version in a nondefault VG_GNU_PACKAGE

• UsenondefaultGCCversioninthe default VG_GNU_PACKAGE

Specifies the version of GCC to use. Currently, only gcc-4.2.2 is supported.

The default value is ’gcc-4.2.2’.

installation location. You specify nothing. Synopsys and the VG_GNU_PACKAGE distribution determine these d efaults .

installation location. For this property, you must specify:

- 'UseDefaultVgGnuPackage', false

- 'VgGnuPackage', '/path/to/vg/gnu/installation'

installation location. For this property, you must specify:

- 'UseDefaultVgGnuPackage', false

- 'VgGnuGccVersion', 'gcc-4.4.2' (for example)

• Use nondefault GCC version in a nondefault VG_GNU_PACKAGE

installation location. For this property, you must specify:

- 'UseDefaultVgGnuPackage', false

- 'VgGnuPackage', '/path/to/vg/gnu/installation'

- 'VgGnuGccVersion', 'gcc-4.4.2' (for example)

Examples This example compiles and launches a single-file HDL design for

cosimulation with Simulink. The code allows the use of Verilog-2000 syntax in the HDL source. This code launches the Synopsys DVE software.

>> launchDiscovery( ...

'LinkType', 'Simulink', ...

4-26

launchDiscovery

'VerilogFiles', 'myinverter.v', ... 'VlogAnFlags', '+v2k', ... 'TopLevel', 'myinverter', ... 'AccFile', 'myinverter.acc' ...

);

This next ex ample compiles and launches an HDL design in batch mode. In batch mode, the HDL simulator exits after the simulation completes, thus the example relaunches the simulation by calling

launchDiscovery again with the previously returne d property/value

structure.

To run cosimulation a fter HDL simulator has exited:

>> pv = launchDiscovery( ...

'LinkType', 'Simulink', ...

'VhdlFiles', '"mymultiplier.vhd mymultiplier_tb.vhd"', ...

'TopLevel', 'mymultiplier_tb', ...

'AccFile', 'mymultiplier.acc', ...

'RunMode', 'Batch', ...

);

To rerun cosimulation:

>> pv.SkipScriptGeneration = true;

>> pv.SkipCompilation = true;

>> pv = launchDiscovery(pv); % relaunch the simulator

This next example generates scripts for customizing the environment of a specific project (USER_ENV includes some custom environment). Some common reasons to customize the resultant script include:

• You want to run the scripts on a different platform.

• You want to run the scripts on the same platform but on a remote

machine.

• The build and run for the HDL simulator is part of a larger

environment involving Perl scripts, makefiles, or LSF.

4-27

launchDiscovery

• You want to run in 32-bit mode on a 64-bit machine

On remote machine, for example, you might use:

>> srcDir = '/path/to/src';

>> launchDiscovery( ...

'LinkType', 'MATLAB', ...

'VhdlFiles', {[srcDir '/top.vhd'], [srcDir '/dut.vhd']}, ...

'TopLevel', 'top', ...

'AccFile', 'top.acc', ...

'RunDir', '/testruns/myrun', ...

'UserEnv', {'LM_LICENSE_FILE=/path/to/license.dat'}, ...

'SkipCompilation', true, ...

'SkipLaunch', true ...

);

sh> cd /testruns/myrun sh> (edit scripts as needed) sh> . tmwESLDS.compile.sh sh> . tmwESLDS.launch.sh

4-28

After you finalize the scripts, you can execute them from MATLAB:

>> system('rsh linux100 cd /testruns/myrun ; sh tmwESLDS.compile.sh ;

sh tmwESLDS.launch.sh');

This example shows the generated compilation script:

launchDiscovery

# AUTO-GENERATED SH SCRIPT FOR Simulink COSIMULATION

#--- EDA Link Environment ---

LAUNCHER_NAME=tmwESLDS

NUM_BITS=64

LINK_LIB_DIR=/matlab/toolbox/edalink/extensions/discovery/linux64

LINK_SL_FILE=liblfdhdls_vlog_gcc336.so

LINK_ML_FILE=liblfdhdlc_vlog_gcc336.so

BITS_FLAG=-full64

export VG_GNU_PACKAGE=${VCS_HOME}/gnu/linux

COMPILE_SETUP_CMDS=". ${VG_GNU_PACKAGE}/source_me_${NUM_BITS}.sh"

export LD_LIBRARY_PATH=${VG_GNU_PACKAGE}/gcc-${NUM_BITS}/slib64:${LINK_LIB_DIR}:${LD_LIBRARY_PATH}

LOAD_SL_LIB="-load ${LINK_SL_FILE}:simlinkserver"

LOAD_ML_LIB="-load ${LINK_ML_FILE}:matlabclient"

VHPI_SL_LIB="-vhpi ${LINK_SL_FILE}:simlinkserver"

VHPI_ML_LIB="-vhpi ${LINK_ML_FILE}:matlabclient"

export SL_LIB_SOCKET=37592

VLOG_FILES=/matlab/toolbox/edalink/extensions/discovery/discoverydemos/Filter/lowpass_filter.v

VHDL_FILES=

TOP_LEVEL=lowpass_filter

ACC_FILE=/matlab/toolbox/edalink/extensions/discovery/discoverydemos/Filter/lowpass_filter.pli_acc.tab

VHDLAN_FLAGS=

VLOGAN_FLAGS="+v2k"

UUMCOMP_FLAGS=

UUMRUN_FLAGS=

COMP_DEBUG_FLAGS=-debug_all

LAUNCH_DEBUG_FLAGS="-gui -i tmwESLDS.presim.tcl"

#--- User Environment ---

eval ${COMPILE_SETUP_CMDS}

vlogan ${BITS_FLAG} ${VLOGAN_FLAGS} ${VLOG_FILES}

vcs ${COMP_DEBUG_FLAGS} ${UUMCOMP_FLAGS} +vpi +applylearn+${ACC_FILE} ${BITS_FLAG} ${TOP_LEVEL} ${LOAD_ML_LIB}

4-29

launchDiscovery

This example shows the generated launch script:

# AUTO-GENERATED SH SCRIPT FOR Simulink COSIMULATION

#--- EDA Link Environment ---

LAUNCHER_NAME=tmwESLDS

NUM_BITS=64

LINK_LIB_DIR=/matlab/toolbox/edalink/extensions/discovery/linux64

LINK_SL_FILE=liblfdhdls_vlog_gcc336.so

LINK_ML_FILE=liblfdhdlc_vlog_gcc336.so

BITS_FLAG=-full64

export VG_GNU_PACKAGE=${VCS_HOME}/gnu/linux

COMPILE_SETUP_CMDS=". ${VG_GNU_PACKAGE}/source_me_${NUM_BITS}.sh"

LAUNCH_SETUP_CMDS=". ${VG_GNU_PACKAGE}/source_me_${NUM_BITS}.sh"

export LD_LIBRARY_PATH=${VG_GNU_PACKAGE}/gcc-${NUM_BITS}/slib64:${LINK_LIB_DIR}:${LD_LIBRARY_PATH}

LOAD_SL_LIB="-load ${LINK_SL_FILE}:simlinkserver"

LOAD_ML_LIB="-load ${LINK_ML_FILE}:matlabclient"

VHPI_SL_LIB="-vhpi ${LINK_SL_FILE}:simlinkserver"

VHPI_ML_LIB="-vhpi ${LINK_ML_FILE}:matlabclient"

export SL_LIB_SOCKET=37592

VLOG_FILES=/matlab/toolbox/edalink/extensions/discovery/discoverydemos/Filter/lowpass_filter.v

VHDL_FILES=

TOP_LEVEL=lowpass_filter

ACC_FILE=/matlab/toolbox/edalink/extensions/discovery/discoverydemos/Filter/lowpass_filter.pli_acc.tab

VHDLAN_FLAGS=

VLOGAN_FLAGS="+v2k"

UUMCOMP_FLAGS=

UUMRUN_FLAGS=

COMP_DEBUG_FLAGS=-debug_all

LAUNCH_DEBUG_FLAGS="-gui -i tmwESLDS.presim.tcl"

4-30

#--- User Environment ---

eval ${LAUNCH_SETUP_CMDS}

simv ${LAUNCH_DEBUG_FLAGS} ${UUMRUN_FLAGS}

launchDiscovery

4-31

makefpgaproject

Purpose Generate X ilinx ISE project and FPG A hardware-in-the-loop

Syntax makefpgaproject(model/subsystem)

makefpgaproject(model/subsystem,'ParameterName',

ParameterValue)

Description makefpgaproject(model/subsystem) generates a Xilinx ISE project

workflow according to Simulink model parameter settings. specifies the name of the Simulink model, and subsystem specifies the name of a subsystem at the top level of the Simulink model.

makefpgaproject(model/subsystem,'ParameterName',ParameterVa lue)

accepts one or more comma-separated parameter name/v alu e pairs so that you may specify optional build settings such as whether or not to continue build o n warnings and HDL Coder parameters. Specify

ParameterName inside single quotes.

Inputs model/subsystem

Name and path of the top-level subsystem whose generated code is to be used in creating and updating the FPGA project, FPGA HIL, and in generating Tcl script

model

4-32

Parameter Name/Value Pairs

ContinueOnWarning

When ContinueOnWarning is set to ’on’, makefpgaproject continues to run when a warning is encountered, without pausing foruseraction. Forexample,insteadofaskingifyouwantto overwrite an existing ISE project, the project without asking and displays a warning message.

•

'on'

Continue build when it encounters a warning without prompting user.

•

'off'

makefpgaproject overwrites

makefpgaproject

Prompt input from user when build encounters a warning.

Default:

HDLCoderParam

'off'

Specify HDL code generation options in a cell array of property-value pairs.

• (

HDLCoderParam, {HDLCParamName1, HDLCParamValue1,

HDLCParamName2, HDLCParamValue2, …}

)

See Simulink HDL Coder documentation for a list of valid parameters and values for the makehdl command; you can use those same property-value pairs with

makefpgaproject.

For example:

{'TargetLanguage', 'VHDL', ...

'TargetDirectory', 'myhdlsrc'}

You may have to turn on the option "Always generate HD L" in the EDA Link co nfig uration parameters pane for the HDL code generation options to take effect.

Examples Create FPGA project workflow with all defaults from the specified top

level subsystem.

> makefpgaproject('model/subsystem')

Create FPGA project workflow from specified top level subsystem and do not prompt for action when warnings are encountered.

>makefpgaproject('model/subsystem', 'ContinueOnWarning', 'on')

4-33

makefpgaproject

Create FPGA project workflow from specified top level subsystem and use the specified HDL Coder property value pairs when generating HDL code.

>makefpgaproject('model/subsystem', 'HDLCoderParam', ...

See Also fpgamodelsetup

{'TargetLanguage', 'VHDL', 'TargetDirectory', 'myhdlsrc'})

4-34

matlabcp

Purpose Associate M ATLA B component function with instantiated HDL design

Syntax matlabcp <instance>

[<time-specs>] [-socket <tcp-spec>] [-rising <port>[,<port>...]] [-falling <port> [,<port>,...]] [-sensitivity <port>[,<port>,...]] [-mfunc <name>] [-use_instance_obj] [-argument]

Description The matlabcp command has the following characteristics:

• Starts the HDL simulator client component of the EDA Simulator

Link software.

• Associates a specified instance of an HDL design created in the HDL

simulator with a MATLAB function.

• Creates a process that schedules invocations of the specified

MATLAB function.

• Cancels any pending events scheduled by a previous

command that specified the same instance. For example, if you issue the command events initiated by

This command is issued in the HDL simulator.

MATLAB component functions simulate the behavior of modules in the HDL model. A stub module (providing port definitions only) in the HDL model passes its input signals to the MATLAB component function. The MATLAB component processes this data and returns the results to the outputs of the stub module. A MATLAB component typically provides some functionality (such as a filter) that is not yet implemented in the HDL code. See “Replacing an HDL Component with a MATLAB Component Function”.

matlabcp for instance foo, all previously scheduled

matlabcp on foo are canceled.

matlabcp

4-35

matlabcp

Arguments <instance>

Notes The communication mode that you specify for matlabcp must

match the communication mode you specified for established the server connection.

For socket communications, specify the port number you selected for

hdldaemon when you issue a link request with the matlabcp command

in the HDL simulator.

Specifies an instance of an HDL design that is associated with a MATLAB function. By default, to a MATLAB function that has the same name as the instance. For example, if the instance is the instance with the MATLAB function hierarchy names are ignored; for example, if your instance name is

top.myfirfilter, matlabcp would associate only myfirfilter

with the MATLAB function). Alternatively, you can specify a different MATLAB function with

matlabcp associates the instance

myfirfilter, matlabcp associates

-mfunc.

hdldaemon when you

myfirfilter (note that

4-36

Note Do not specify an instance of an HDL module that has already b een associated with a MATLAB function (via or matlabtb). If you do, the new association overwrites the existing one.

<time-specs>

Specifies a combination of time specifications consisting of any or all of the following:

matlabcp

<timen>,...

-repeat <time>

-cancel <time>

Specifies one or more discrete time valu es at which the HDL simulator calls the specified MATLAB function. Each time value is relative to the current simulation time. Even if you do not specify a time, the HDL simulator calls the MATLAB function once at the start of the simulation. Separate multiple time values by a space.For example:

matlabtb vlogtestbench_top 10 ns, 10 ms, 10 sec

The MATLAB function executes when time equals 0 and then 10 nanoseconds, 10 milliseconds, and 10 seconds from time zero.

Note For time-based parameters, you can specify any standard time units (

ns, us, and so on). If yo u do not specify

units, the com mand treats the time value as a value of HDL simulation ticks.

Specifies that the HDL simulator calls the MATLAB function repeatedly based on the specified

<timen>,...

pattern. The time values are relative to the value of tnow at the time the HDL simulator first calls the MATLAB function.

Specifies a time at which the specified MATLAB function stops executing. The time value is relative to the value of

tnow atthetimetheHDLsimulatorfirstcallstheMATLAB

function. If you do not specify a cancel time, the application calls the MATLAB function until you finish the simulation, quit the session, or issue a

nomatlabtb call.

Note The -cancel option works only with the <time-specs> arguments. It does not affect any of the other scheduling arguments for

matlabcp.

4-37

matlabcp

Note Placetimespecificationsafterthematlabcp instance and

before any additional command arguments; otherwise the time specifications are ignored.

All time specifications for the matlabcp functions appear as a number and, optionally, a time unit:

• fs (femtoseconds)

• ps (picoseconds)

• ns (nanoseconds)

• us (microseconds)

• ms (milliseconds)

• sec (seconds)

• no units (tick)

4-38

-socket <tcp_spec>

Specifies TCP/IP socket communication for the link between the HDL simulator and MATLAB. When you provide TCP/IP information for TCP/IP port alias or service name for the < If you are setting up communication between computers, you must also specify the name or Internet address of the remote host that is running the MATLAB server ( TCP/IP Values” for some valid

For more information on choosing TCP/IP socket ports, see “Choosing TCP/IP S ocke t Ports”.

<tcp_spec>

matlabcp, you can choose a TCP/IP port number or

tcp_spec> parameter.

hdldaemon). See “Specifying

tcp_spec examples.

on the command line.

-socket

Note The communication mode that you specify with the

matlabcp command must match what you specify for the

communication mode when you issue the

hdldaemon command in

MATLAB.

For more information on modes of communication, see “Communications f or HDL Cosimulation”. For more information on establishing the MATLAB end of the communication link, see “Starting the HDL Simulator from MATLAB”.

-rising <signal>[, <signal>...]

Indicates that the application calls the specified MATLAB function on the rising edge (transition from the specified signals. Specify

-rising with the path names of

one or more signals defined a s a logic type (

'0' to '1')ofanyof

STD_LOGIC, BIT, X01,

and so on).

For determining signal transition in:

matlabcp

• VHDL:Risingedgeis{0orL}to{1orH}.

• Verilog: Rising edge is the transition from 0 to x, z, or 1, and

from x or z to 1.

Note When specifying signals with the -rising, -falling,and

-sensitivity options, specify them in full path name format. If

you do not specify a full path name, the command applies the HDL simulator rules to resolve signal specifications.

-falling <signal>[, <signal>...]

Indicates that the application calls the specified MATLAB function whenever any of the specified signals experiences a falling edge—changes from

'1' to '0'.Specify-falling with

4-39

matlabcp

the path n ames of one or more signals defined as a logic type (

STD_LOGIC, BIT, X01,andsoon).

For determining signal transition in:

• VHDL: Falling edge is {1 or H} to {0 or L}.

• Verilog: Falling edge is the transition from 1 to x, z, or 0, and

from x or z to 0.

Note When specifying signals with the -rising, -falling,and

-sensitivity options, specify them in full path name format. If

you do not specify a full path name, the command applies the HDL simulator rules to resolve signal specifications.

-sensitivity <signal>[, <signal>...]

Indicates that the application calls the specified MATLAB function whenever any of the specified signals changes state. Specify

-sensitivity with the path names of one or more signals.

Signals of any type can appear in the sensitivity list and can be positioned at any level in the HDL model hierarchy.

4-40

Note When specifying signals with the -rising, -falling,and

-sensitivity options, specify them in full path name format. If

you do not specify a full path name, the command applies the HDL simulator rules to resolve signal specifications.

-mfunc <name>

The name of the MATLAB function that is associated with the HDL module instance you specify for

instance.Bydefault,the

EDA Simulator Link software invokes a MATLAB function that has the same name as the specified HDL instance. Thus, if the names are the same, you can omit the are not the same, use this argument when you call

-mfunc option. If the names matlabcp.If

you omit this argument and matlabcp does not find a MATLAB function with the same name, the command generates an error message.

-use_instance_obj

Instructs the function specified with the argument -mfunc to use an HDL instance object passed by EDA Simulator Link to the function. You include the -use_instance_obj argument with

matlabcp in the following format:

matlabcp modelname -mfunc funcname -use_instance_obj

When you call matlabcp with the use_instance_obj argument, the function has the following signature:

function MyFunctionName(hdl_instance_obj)

The HDL instance object (hdl_instance_obj) has the fields shown in the following table.

matlabcp

Field Read/Write

Access

tnext

userdata

Write only Used to schedule a callback during the set time value.

Read/Write

Description

This field is equivalent to old tnext. For ex ample:

hdl_instance_obj.tnext = hdl_instance_obj.tnow + 5e-9

will schedule a callback at time equals 5 nanoseconds from tnow.

Stores state variables of the current

matlabcp instance.

You can retrieve the variables the next time the callback of this instance is schedul ed .

4-41

matlabcp

Field Read/Write

Access

simstatus

instance

Read only

Description

Stores the status of the HDL simulator. The EDA Simulator Link software sets this field to ’Init’ during the first c a llb ack for this particular instance an d to ’Running’ thereafter. simstatus is a read-only property.

>> hdl_instance_obj.simstatus

ans=

Init

Stores the full path of the Verilog/VHDL instance associated with the callback. instance is a read-only property. The value of this field equals that of the module instance specified with the function call. For example:

In the HDL simulator:

hdlsim> matlabcp osc_top -mfunc oscfilter use_instance_obj

In MATLAB:

>> hdl_instance_obj.instance

ans=

osc_top

4-42

matlabcp

Field Read/Write

Access

argument

portinfo

Read only

Description

Stores the argument set by the -argument option of

matlabcp. For example:

matlabtb osc_top -mfunc oscfilter -use_instance_obj -argument foo

The link software supports the -argument option only when it is used with -use_instance_obj, otherwise the argument is ignored. argument is a read-only property.

>> hdl_instance_obj.argument

ans=

foo

Stores information about the VHDL and Verilog ports associated with this instance. portinfo is a read-only property, which has a field structure that describes the ports defined for the associated HDL module. For each port, the portinfo structure passes information such as the port’s type, direction, and size. For more information on port data, see “Gaining Access to and Applying Port Information”.

hdl_instance_obj.portinfo.field1.field2.field3

Note When you use use_instance_obj, you access tscale through the HDL instance object. If you do not use use_instance_obj, you can still access tscale through portinfo.

4-43

matlabcp

Field Read/Write

Access

tscale

tnow

portvalues

Read only

Read/Write

Description

Stores the resolution limit (tick) in seconds of the H D L simulator. tscale is a read-only property.

>> hdl_instance_obj.tscale

ans=

1.0000e-009

Note When you use use_instance_obj, you access tscale through the HDL instance object. If you do not use use_instance_obj, you can still access tscale through portinfo.

Stores the current time. tnow is a read-only property.

hdl_instance_obj.tnext = hld_instance_obj.tnow + fastestrate;

Stores the current values of and sets new values for the output and input ports for a

matlabcp instance. For

example:

4-44

>> hdl_instance_obj.portvalues

ans = Read Only Input ports:

clk_enable: [] clk: [] reset: []

Read/Write Output ports:

sine_out: [22x1 char]

matlabcp

Field Read/Write

Description

Access

linkmode

Read only

Stores the status of the callback. The EDA Simulator Link software sets this field to ’testbench’ if the callback is associated with is associated with

matlabtb and ’component’ if the callback

matlabcp.linkmodeisaread-only

property.

>> hdl_instance_obj.linkmode

ans=

component

-argument

Used to pass user-defined arguments from the matlabcp invocation on the HDL side to the MATLAB function callbacks. Supported with under the

-use_instance_obj only. See the field listing

-use_instance_obj property.

Examples The following examples demonstrate some ways you might use the

matlabcp function.

Using matlabcp with the -mfunc option to Associate a n HDL Component with a MATLAB Function of a Different Name

This example exp licitly associates the Verilog module vlogtestbench_top.u_matlab_component with the MATLAB function

vlogmatlabc using the -mfunc option. The '-socket' option specifies

using socket communication on port 4449.

matlabcp vlogtestbench_top.u_matlab_component -mfunc vlogmatlabc -socket 4449

Using matlabcp with Explicit Times and the -cancel Option

This example implicitly associates the Verilog module, vtestbench_top, with the MATLAB function vlogtestbench_top, and includes explicit times with the -cancel option.

matlabcp vlogtestbench_top 1e6 fs 3 2e3 ps -repeat 3 ns -cancel 7ns

4-45

matlabcp

Using matlabcp with Rising and Falling Edges

This ex ample implicitly associates the Verilog module, vlogtestbench_top, with the MATLAB function vlogtestbench_top, and also uses rising and falling edges.

hldsim> matlabcp vlogtestbench_top 1 2 34567-rising outclk3

-falling u_matlab_component/inoutclk

Using matlabcp and the HDL Instance Object

In this example, the HDL simulator makes repeated calls to matlabcp to bind multiple HDL instances to the same MATLAB function. Each call contains

-argument as a constructor parameter to differentiate

behavior.

> matlabcp u1_filter1x -mfunc osc_filter -use_instance_obj -argument oversample=1

> matlabcp u1_filter8x -mfunc osc_filter -use_instance_obj -argument oversample=8

> matlabcp u2_filter8x -mfunc osc_filter -use_instance_obj -argument oversample=8

4-46

The MATLAB function callback, osc_filter.m, sets up user instance-based state using obj.userdata, queries port and simulation context using other obj fields, and uses the passed in obj.argument to differentiate behavior.

function osc_filter(obj)

if (strcmp(obj.simstatus,'Init'))

ud = struct('Nbits', 22, 'Norder', 31, 'clockperiod', 80e-9, 'phase', 1));

eval(obj.argument);

if (~exist('oversample','var'))

error('HdlLinkDemo:UseInstanceObj:BadCtorArg', ...

'Bad constructor arg to osc_filter callback. Expecting

''oversample=value''.');

end

ud.oversample = oversample;

ud.oversampleperiod = ud.clockperiod/ud.oversample;

ud.InDelayLine = zeros(1,ud.Norder+1);

centerfreq = 70/256;

passband = [centerfreq-0.01, centerfreq+0.01];

b = fir1((ud.Norder+1)*ud.oversample-1, passband./ud.oversample);

ud.Hresp = ud.oversample .* b;

obj.userdata = ud;

end

...

matlabcp

4-47

matlabtb

Purpose Schedule MATLAB test bench session for instantiated HDL module

Syntax matlabtb <instance>

[<time-specs>] [-socket <tcp-spec>] [-rising <port>[,<port>...]] [-falling <port> [,<port>,...]] [-sensitivity <port>[,<port>,...]] [-mfunc <name>] [-use_instance_obj] [-argument]

Description The matlabtb command has the following characteristics:

• Starts the HDL simulator client component of the EDA Simulator

Link software.

• Associates a specified instance of an HDL design created in the HDL

simulator with a MATLAB function.

4-48

• Creates a process that schedules invocations of the specified

MATLAB function.

• Cancels any pending events scheduled by a previous

command that specified the same instance. For example, if you issue the command events initiated by

This command is issued in the HDL simulator.

MATLAB test bench functions mimic stimuli passed to e ntities in the HDL model. You force stimulus from MATLAB or H D L scheduled with

matlabtb.

matlabtb for instance foo, all previously scheduled

matlabtb on foo are canceled.

matlabtb

Notes The communication mode that you specify for matlabtb must match the communication mode you specified for established the server connection.

For socket communications, specify the port number you selected for

hdldaemon when you issue a link request with the matlabtb command

in the HDL simulator.

Arguments <instance>

Specifies the instance of an HDL module that the EDA Simulator Link software associates with a MATLAB test bench function. By default, function that has the same name as the instance. For example, if the instance is with the MATLAB function names are ignored; for example, if your instance name is

top.myfirfilter, matlabtb would associate only myfirfilter

with the MATLAB function). Alternatively, you can specify a different MATLAB function with

matlabtb

hdldaemon when you

matlabtb associates the instance with a MATLAB

myfirfilter, matlabtb associates the instance

myfirfilter (note that hierarchy

-mfunc.

Note Do not specify an instance of an HDL module that has already b een associated with a MATLAB function (via or matlabtb). If you do, the new association overwrites the existing one.

<time-specs>

Specifies a combination of time specifications consisting of any or all of the following:

matlabcp

4-49

matlabtb

<timen>,...

-repeat <time>

matlabtb vlogtestbench_top 10 ns, 10 ms, 10 sec

The MATLAB function executes when time equals 0 and then 10 nanoseconds, 10 milliseconds, and 10 seconds from time zero.

Note For time-based parameters, you can specify any standard time units (

ns, us, and so on). If yo u do not specify

units, the com mand treats the time value as a value of HDL simulation ticks.

Specifies that the HDL simulator calls the MATLAB function repeatedly based on the specified

<timen>,...

pattern. The time values are relative to the value of tnow at the time the HDL simulator first calls the MATLAB function.For example:

-cancel <time>

4-50

matlabtb vlogtestbench_top 5 ns -repeat 10 ns

The M AT LAB function executes at time equals 0 ns, 5 ns, 15 ns, 25 n s, and so on.

Specifies a time at which the specified MATLAB function stops executing. The time value is relative to the value of

tnow atthetimetheHDLsimulatorfirstcallstheMATLAB

function. If you do not specify a cancel time, the application calls the MATLAB function until you finish the simulation, quit the session, or issue a

nomatlabtb call.

matlabtb

Note The -cancel option works only with the <time-specs>

arguments. It does not affect any of the other scheduling arguments for

Note Placetimespecificationsafterthematlabtb instance and before any additional command arguments; otherwise the time specifications are ignored.

All time specifications for the matlabtb functions appear as a number and, optionally, a time unit:

• fs (femtoseconds)

• ps (picoseconds)

• ns (nanoseconds)

matlabtb.

• us (microseconds)

• ms (milliseconds)

• sec (seconds)

• no units (tick)

-socket <tcp_spec>

matlabtb, you can choose a TCP/IP port number or

tcp_spec> parameter.

hdldaemon). See “Specifying

tcp_spec examples.

4-51

matlabtb

For more information on choosing TCP/IP socket ports, see “Choosing TCP/IP S ocke t Ports”.

<tcp_spec>

Note The communication mode that you specify with the

matlabtb command must match what you specify for the

communication mode when you issue the MATLAB. For more information on modes of communication, see “Communications for HDL Cosimulation”. For more information on establishing the MATLAB end of the communication link, see “Starting the HDL Simulator from MATLAB”.

on the command line.

hdldaemon command in

-socket

4-52

-rising <signal>[, <signal>...]

Indicates that the application calls the specified MATLAB function on the rising edge (transition from the specified signals. Specify one or more signals defined a s a logic type ( and so on).

For determining signal transition in:

• VHDL:Risingedgeis{0orL}to{1orH}.

• Verilog: Rising edge is the transition from 0 to x, z, or 1, and

from x or z to 1.

-rising with the path names of

'0' to '1')ofanyof

STD_LOGIC, BIT, X01,

Mathworks EDA SIMULATOR LINK 3 Reference

Specifications and Main Features

Frequently Asked Questions

User Manual

Block Reference

HDL Cosimulation

FPGA Implementations

Virtual Platform Simulation

Blocks — Alphabetical List

Tcl Scripts for ModelSim Users

Tcl Scripts for Incisive Users

Generated VCD File Format

Function Reference

HDL Cosimulation

FPGA Implementations

Virtual Platform Simulation

Functions — Alphabetical List

Required Properties

Common Optional Properties

Advanced Optional Properties

VG_GNU_PACKAGE Properties