Marvel Group 88F6281 User Manual

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Marvell. Moving Forward Faster

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88F6281

Integrated Controller

Hardware Specifications

Doc. No. MV-S104859-U0, Rev. E December 2, 2008, Preliminary

Document Classification: Proprietary Information

Page 2

88F6281 Hardware Specifications

Document Conventions

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Doc Status: Preliminary Technical Publication: 0.xx

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Sheeva™ CPU Core

16 KB-I, 16 KB-D

Up to 1.5 GHz

AES/DES/

3DES

SHA-1/MD5

Processor

Memory

Security Engin e

Cache

256 KB

DDR

SDRAM

Controller

JTAG Interface

PCI Express

SATA

USB 2.0

High Speed I/0

PCI Express x1

Dual SATA ports

USB 2.0 port

88F6281 Functional Block Diagram

External DDR

800 MHz

Misc

FXS / FXO

SPI, NAND, SDIO

Slow Bus

TDM

UART x2 GPIO, TWSI Flash, SDIO

4 XOR/DMA channels

XOR Engine

Internal Bus

Gigabit Ethernet IEEE 1588AVB support

MPEG2-TS

S / S/PDIF

Media Interfaces

MPEG TS

Audio

PRODUCT OVERVIEW

88F6281

Integrated Controller

Hardware Specifications

The Marvell® 88F6281 is a high-performance, highly integrated controller. The 88F6281 is based on the Marvell proprietary, ARMv5TE-compliant, high-speed Sheeva

™

CPU core. The CPU core integrates a 256 KB L2 cache.

Page 4

FEATURES

88F6281 Hardware Specifications

 The 88F6281 includes:

• High-performance CPU core, running at up to

1.5 GHz, with integrated, four-way, set-associative L1 16-KB I-cache/16-KB D-cache and unified, 256-KB, four-way, set-associative L2 cache

• High-bandwidth dual-port DDR2 memory interface

(16-bit DDR2 SDRAM @ up to 800 MHz data rate)

• PCI Express (x1) port with integrated PHY

• Two Gigabit Ethernet (10/100/1000 Mbps) MACs

• USB 2.0 port with integrated PHY

• Two SATA 2.0 ports w ith inte grated 3 Gbp s SATA II

PHY

• Security Cryptographic engine

• S/PDIF (Sony/Philips Digital Interconnect Format) /

S (Integrated Interchip Sound) Audio in/out

I interface

• SD/SDIO/MMC interface

• TDM SLIC/SLAC Codec interface

• Two XOR engines, each containing two XOR/DMA

channels (a total of four XOR/DMA channels)

• MPEG Transport Stream (TS) interface

• SPI port with SPI flash boot support

• 8-bit NAND flash interface with boot support

• Two 16550 compatible UART interfaces

• TWSI port

• 50 multi-purpose pins

• Internal Real Time Clock (RTC)

• Interrupt controller

• Timers

• 128-bit eFuse (one-time programmable memory)

 Sheeva

™

CPU core

• Up to 1.5 GHz

• 32-bit and 16-bit RISC architecture

• Compliant with v5TE architecture, as published in

the ARM Architect Reference Manual, Second Edition

• Includes MMU to support virtual memory features

• 256-KB, four-way, set-associative L2 unified cache

• 16-KB, four-way, set-associative I-cache

• 16-KB, four-way, set-associative D-cache

• 64-bit internal data bus

• Branch Prediction Unit

• Supports JTAG/ARM ICE

• Supports both Big and Little Endian modes

 DDR2 SDRAM controller

• 16-bit interface

• Up to 400 MHz clock frequency (800 MHz data

rate)

• DDR SDRAM with a clock ratio of 1:N and 2:N

between the DDR SDRAM and the CPU core, respectively

• SSTL 1.8V I/Os

• Auto calibration of I/Os output impedance

• Supports four DRAM chip selects

• Supports all DDR devices densities up to 2 Gb

• Supports up to 32 open pages (page per bank)

• Up to 2 GB total address space

• Supports on-board DDR designs (no DIMM

support)

• Supports 2T mode, to enable high-frequency

operation under heavy load configuration

• Supports DRAM bank interleaving

• Supports up to a 128-byte burst per single memory

access

 PCI Express interface (x1)

• PCI Express Base 1.1 compatible

• Integrated low-power SERDES PHY, based on

proven Marvell

SERDES technology

• Serves as a Root Complex or an Endpoint port

• x1 link width

• 2.5 Gbps data rate

• Lane polarity reversal support

• Maximum payload size of 128 bytes

• Single Virtual Channel (VC-0)

• Replay buffer support

• Extended PCI Express configuration space

• Advanced Error Reporting (AER) support

• Power management: L0s and software L1 support

• Interrupt emulation message support

• Error message support

 PCI Express master specific features

• Single outstanding read transaction

• Maximum read request of up to 128 bytes

• Maximum write request of up to 128 bytes

• Up to four outstanding read transactions in

Endpoint mode

 PCI Express target specific features

• Supports up to eight read request transactions

• Maximum read request size of 4 KB

• Maximum write request of 128 bytes

• Supports PCI Express access to all of the

controller’s internal registers

 Two Integrated GbE (10/100/1000) MAC ports

• Supports 10/100/1000 Mbps

• Dedicated DMA for data movement between

memory and port

Page 5

Features

• Priority queuing on receive based on Destination

Address (DA), VLAN Tag, and IP TOS

• Layer 2/3/4 frame encapsulation detection

• TCP/IP checksum on receive and transmit

• Supports proprietary 200 Mbps Marvell MII (MMII)

interface

• Supports four modes:

- Port 0 RGMII, Port 1 RGMII

- Port 0 RGMII, Port 1 MII/MMII

- Port 0 MII/MMII, port 1 RGMII

- Port 0 GMII, Port 1 N/A

•DA filtering

 Precise Timing Protocol (PTP)

• Supports precise time stamping for packets, as

defined in IEEE 1588 PTP v1 and v2 and IEEE

802.1AS draft standards

• Supports Flexible Time Application interface to

distribute PTP clock and time to other devices in the system

• Optionally accepts an external clock input for time

stamping

 Audio Video Bridging networks

• Supports IEEE 802.1Qav draft Audio Video

Bridging networks

• Supports time- and priority-aware egress pacing

algorithm to prevent bunching and bursting effects—suitable for audio/video applications

• Supports Egress Jitter Pacer for AVB-Class A and

AVB-Class B traffic and strict priority for legacy traffic queues

 USB 2.0 port

• Serves as a peripheral or host

• USB 2.0 compliant

• Integrated USB 2.0 PHY

• Enhanced Host Controller Interface (EHCI)

compatible as a host

• As a host, supports direct connection to all

peripheral types (LS, FS, HS)

• As a peripheral, connects to all host types (HS, FS)

and hubs

• Up to four independent endpoints, supporting

control, interrupt, bulk, and isochronous data transfers

• Dedicated DMA for data movement between

memory and port

 T wo Integrated Marvell 3 Gbps (Gen2i) SA T A PHYs

• Compliant with SATA II Phase 1 specifications

- Supports SATA II Native Command Queuing

(NCQ), up to 128 outstanding commands per port

- Fully supports first party DMA (FPDMA)

- Backwards compatible with SATA I devices

• Supports SATA II Phase 2 advanced features

- 3 Gbps (Gen2i) SATA II speed

- Port Multiplier (PM)—Performs FIS-based

switching, as defined in SAT A working group PM definition

- Port Selector (PS)—Issues the protocol-bas ed

Out-Of-Band (OOB) sequence for selecting the active host port

• Supports device 48-bit addressing

• Supports ATA Tag Command Queuing

 SATA II Host Controller

• Enhanced-DMA (EDMA) for the SATA ports

• Automatic command execution, without host

intervention

• Command queuing support, for up to 32

outstanding commands

• Separate SATA request/response queues

• 64-bit addressing support for descriptors and data

buffers in system memory

• Read ahead

• Advanced interrupt coalescing

• Target mode operation—supports attaching two

88F6281 controllers through their Serial-ATA ports, enabling data communication between the 88F6281 controllers

• Advanced drive diagnostics via the ATA SMART

command

 Cryptographic engine

• Hardware implementation on encryption and

authentication engines, to boost packet processing speed

• Dedicated DMA to feed the hardware engines with

data from the internal SRAM memory or from the DDR memory

• Implements AES, DES, and 3DES encryption

algorithms

• Implements SHA1 and MD5 authentication

algorithms

 S/PDIF / I

• Either S/PDIF or I

• Both S/PDIF and I

 S/PDIF-specific features

S Audio In/Out interface

time

simultaneously active, transferring the same PCM data

S inputs can be active at one

S outputs can be

• Compliant with 60958-1, 60958-3, and IEC61937

specifications

• Sample rates of 44.1/48/96 kHz

• 16/20/24-bit depths

Page 6

88F6281 Hardware Specifications

 I

S-specific features

• Sample rates of 44.1/48/96 kHz

• I

S input and I2S output operate at the same

sample rate

• 16/24-bit depths

• I

S in and I2S out support independent bit depths

(16 bit/24 bit)

• Supports plain I

S, right-justified and left-justified

formats

 SD/SDIO/MMC host interface

• 1-bit/4-bit SDmem, SDIO, and MMC cards

• Up to 50 MHz

• Hardware generate/check CRC, on all command

and data transactions on the card bus

 TDM SLIC/SLAC Codec interface

• Generic interface to standard SLIC/SLAC codec

devices

• Compatible with standard PCM highway formats

• TDM protocol support for two channels, up to

128 time slots

• Dedicated SPI interface for codec management

• Integrated DMA to transfer voice data to/from

memory buffer

 Two XOR engines and DMA

• Two XOR/DMA channels per XOR engine (for a

total of four XOR/DMA channels)

• Chaining via linked-lists of descriptors

• Moves data from source interface to destination

interface

• Supports increment or hold on both Source and

Destination Addresses

• Supports XOR operation, on up to eight source

blocks—useful for RAID applications

• Supports iSCSI CRC-32 calculation

 NAND flash controller

• 8-bit NAND flash interface

• Glueless interface to CE Care and CE Don’t Care

NAND flash devices

• Boot support

 Serial Peripheral Interface (SPI) controller

• Up to 50 MHz clock

• Supports direct boot from external SPI serial flash

memory

 MPEG Transport Stream (TS) interface

• ISO/IEC 13818-1 standard compliant

• Supports any one of the following modes:

- Parallel (8 bit) input

- Parallel output

- Two independent serial interfaces

• Data rate up to 80 Mbps

 Two UART Interfaces

• 16550 UART compatible

• Two pins for transmit and receive operations

• Two pins for mode m control functions

 Two-Wire Serial Interface (TWSI)

• General purpose TWSI master/slave port

• Can also be used for serial ROM initialization

 50 dedicated Multi-Purpose Pins (MPPs) for

peripheral functions and general purpose I/O

• Each pin can be configured independently.

• GPIO inputs can be used to register interrupts from

external devices, and to generate maskable interrupts.

• Only two of the following multiplexed interfaces

may be configured simultaneously:

- Audio

- TS

- TDM

- GbE Port 0 in GMII mode or GbE Port 1

 Interrupt Controller

Maskable interrupts to CPU core (and PCI Express for a PCI Express endpoint)

 Two general purpose 32-bit timers/counters  Internal architecture

• Mbus-L bus for high-performance, low-latency CPU

core to DDR SDRAM connectivity

• Advanced Mbus architecture

• Dual port DDR SDRAM controller connectivity to

both CPU and Mbus

 Bootable from

• SPI flash

• SATA device

• NAND flash

• PCI Express

• UART (for debug purpose)

 288-pin HSBGA package, 19 x 19 mm, 1 mm ball

pitch

Page 7

Features

x16

TDM

Usage Model Example: VoIP Gateway

PCI Express

Mini Card Wi-Fi

SD Card

USB Host

SATA Port

Multiplier

HDD

Audio

A/D – D/A

GbE PHY FXS FXO

NAND Flash

SPI Flash (op.)

On Board DDR2

88F6281

Page 8

88F6281 Hardware Specifications

Product Overview.......................................................................................................................................3

Features.......................................................................................................................................................4

Preface.......................................................................................................................................................15

About this Document.......................................................................................................................................15

Related Documentation...................................................................................................................................15

Document Conventions...................................................................................................................................16

1 Pin and Signal Descriptions.......................................................................................................17

1.1 Pin Logic .........................................................................................................................................................18

1.2 Pin Descriptions..............................................................................................................................................19

1.3 Internal Pull-up and Pull-down Pins................................................................................................................48

2 Unused Interface Strapping........................................................................................................49

3 88F6281 Pin Map and Pin List .......... ... ... ... .... ... ............................................. ... .... ... ... ... .............50

4 Pin Multiplexing...........................................................................................................................51

4.1 Multi-Purpose Pins Functional Summary........................................................................................................51

4.2 Gigabit Ethernet (GbE) Pins Multiplexing on MPP..........................................................................................57

4.3 TSMP (TS Multiplexing Pins) on MPP.............................................................................................................59

5 Clocking .......................................................................................................................................60

5.1 Spread Spectrum Clock Generator (SSCG)....................................................................................................62

6 System Power Up/Down and Reset Settings............................................................................63

6.1 Power-Up/Down Sequence Requirements......................................................................................................63

6.2 Hardware Reset ..............................................................................................................................................64

6.3 PCI Express Reset.......................................... ... ... ..........................................................................................66

™

6.4 Sheeva

6.5 Pins Sample Configuration..............................................................................................................................66

6.6 Serial ROM Initialization..................................................................................................................................70

6.7 Boot Sequence................................................................................................................................................71

CPU TAP Controller Reset..............................................................................................................66

7 JTAG Interface.............................................................................................................................73

7.1 TAP Controller.................................................................................................................................................73

7.2 Instruction Register.........................................................................................................................................73

7.3 Bypass Register..............................................................................................................................................74

7.4 JTAG Scan Chain ............... ............................................................................... .. ...........................................74

7.5 ID Register........................................ ..............................................................................................................74

Page 9

Table of Contents

8 Electrical Specifications (Preliminary) ......................................................................................75

8.1 Absolute Maximum Ratings ............................................................................................................................75

8.2 Recommended Operating Conditions.............................................................................................................77

8.3 Thermal Power Dissipation .............................................................................................................................79

8.4 Current Consumption......................................................................................................................................80

8.5 DC Electrical Specifications............................................................................................................................81

8.6 AC Electrical Specifications ............................................................................................................................86

8.7 Differential Interface Electrical Characteristics..............................................................................................118

9 Thermal Data (Preliminary).......................................................................................................129

10 Package......................................................................................................................................130

11 Part Order Numbering/Package Marking ................................................................................132

11.1 Part Order Numbering........................................ ... ... ............................................... ......................................132

11.2 Package Marking ..........................................................................................................................................133

A Revision History ........................................................................................................................134

Page 10

88F6281 Hardware Specifications

List of Tables

1 Pin and Signal Descriptions ............................................................................................................17

Table 1: Pin Functions and Assignments Table Key......................................................................................19

Table 2: Interface Pin Prefix Codes................................. ................................................ ...............................19

Table 3: Power Pin Assignments....................................................................................................................21

Table 4: Miscellaneous Pin Assignments .......................................................................................................23

Table 5: DDR SDRAM Interface Pin Assignments.........................................................................................24

Table 6: PCI Express Interface Pin Assignments...........................................................................................26

Table 7: SATA Port Interface Pin Assignment................................................................................................27

Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments .......................................................................28

Table 9: Serial Management Interface (SMI) Pin Assignments......................................................................32

Table 10: USB 2.0 Interface Pin Assignments..................................................................................................33

Table 11: JTAG Pin Assignment......................................................... ..............................................................34

Table 12: RTC Interface Pin Assignments........................................................................................................35

Table 13: NAND Flash Interface Pin Assignment.............................................................................................36

Table 14: MPP Interface Pin Assignment.........................................................................................................37

Table 15: Two-Wire Serial Interface (TWSI) Interface Pin Assignment............................................................38

Table 16: UART Port 0/1 Interface Pin Assignment .........................................................................................39

Table 17: Audio (S/PDIF / I

Table 18: Serial Peripheral Interface (SPI) Interface Signal Assignment ...................................................... ...41

Table 19: Secure Digital Input/Output (SDIO) Interface Signal Assignment.....................................................42

Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment .......................................................43

Table 21: Transport Stream (TS) Interface Signal Assignment........................................................................45

Table 22: Precise Timing Protocol (PTP) Interface Signal Assignment............................................................47

Table 23: Internal Pull-up and Pull-down Pins..................................................................................................48

S) Interface Signal Assignment....................................... ... ... ...............................40

2 Unused Interface Strapping.............................................................................................................49

Table 24: Unused Interface Strapping ..............................................................................................................49

3 88F6281 Pin Map and Pin List ......................................... ... ... ... ............................................. ..........50

4 Pin Multiplexing ................................................................................................................................51

Table 25: MPP Functionality.............................................................................................................................52

Table 26: MPP Function Summary...................................................................................................................53

Table 27: Ethernet Ports Pins Multiplexing.......................................................................................................57

Table 28: TS Port Pin Multiplexing .................................................................................................................59

5 Clocking.............................................................................................................................................60

Table 29: 88F6281Clocks.................................................................................................................................60

Table 30: Supported Clock Combinations........................................................................................................61

6 System Power Up/Down and Reset Settings .................................................................................63

Table 31: I/O and Core Voltages......................................................................................................................63

Table 32: Reset Configuration..........................................................................................................................67

Page 11

List of Tables

7 JTAG Interface ..................................................................................................................................73

Table 33: Supported JTAG Instructions............................................................................................................73

Table 34: IDCODE Register Map .....................................................................................................................74

8 Electrical Specifications (Preliminary) ...........................................................................................75

Table 35: Absolute Maximum Ratings..............................................................................................................75

Table 36: Recommended Operating Conditions...............................................................................................77

Table 37: Thermal Power Dissipation...............................................................................................................79

Table 38: Current Consumption........................................................................................................................80

Table 39: General 3.3V Interface (CMOS) DC Electrical Specifications...........................................................81

Table 40: RGMII 1.8V Interface (CMOS) DC Electrical Specifications.............................................................82

Table 41: SDRAM DDR2 Interface DC Electrical Specifications......................................................................83

Table 42: TWSI Interface 3.3V DC Electrical Specifications.............................................................................84

Table 43: SPI Interface 3.3V DC Electrical Specifications................................................................................84

Table 44: TDM Interface 3.3V DC Electrical Specifications..............................................................................85

Table 45: Reference Clock AC Timing Specifications ......................................................................................86

Table 46: SDRAM DDR2 Interface AC Timing Table .......................................................................................88

Table 47: SDRAM DDR2 Interface Address Timing Table...............................................................................89

Table 48: SDRAM DDR2 Clock Specifications.................................................................................................90

Table 49: RGMII 10/100/1000 AC Timing Table at 1.8V ..................................................................................93

Table 50: RGMII 10/100 AC Timing Table at 3.3V...........................................................................................93

Table 51: GMII AC Timing Table......................................................................................................................95

Table 52: MII/MMII MAC Mode AC Timing Table.............................................................................................97

Table 53: SMI Master Mode AC Timing Table..................................................................................................99

Table 54: JTAG Interface AC Timing Table....................................................................................................101

Table 55: TWSI Master AC Timing Table.......................................................................................................103

Table 56: TWSI Slave AC Timing Table.........................................................................................................103

Table 57: S/PDIF AC Timing Table ................................................................................................................105

Table 58: Inter-IC Sound (I2S) AC Timing Table............................................................................................107

Table 59: TDM Interface AC Timing Table .....................................................................................................109

Table 60: SPI (Master Mode) AC Timing Table..............................................................................................111

Table 61: SDIO Host in High Speed Mode AC Timing Table .........................................................................113

Table 62: Transport Stream Output Interface AC Timing Table ....................................................................115

Table 63: Transport Stream Input Interface AC Timing Table........................................................................115

Table 64: PCI Express Interface Differential Reference Clock Characteristics ..............................................118

Table 65: PCI Express Interface Spread Spectrum Requirements.................................................................119

Table 66: PCI Express Interface Driver and Receiver Characteristics ...........................................................120

Table 67: SATA-I Interface Gen1i Mode Driver and Receiver Characteristics...............................................123

Table 68: SATA-II Interface Gen2i Mode Driver and Receive

Table 69: USB Low Speed Driver and Receiver Characteristics....................................................................125

Table 70: USB Full Speed Driver and Receiver Characteristics.....................................................................126

Table 71: USB High Speed Driver and Receiver Characteristics...................................................................127

r Ch

aracteristics..............................................124

9 Thermal Data (Preliminary)............................................................................................................129

Table 72: Thermal Data for the 88F6281 in the BGA 19 x 19 mm Package (Preliminary) .............................129

Page 12

88F6281 Hardware Specifications

10 Package ...........................................................................................................................................130

Table 73: HSBGA 288-pin Package Dimensions ...........................................................................................131

11 Part Order Numbering/Package Marking......................................................................................132

Table 74: 88F6281 Part Order Options ..........................................................................................................132

A Revision History .............................................................................................................................134

Table 75: Revision History..............................................................................................................................134

Page 13

List of Figures

1 Pin and Signal Descriptions ........................................................................................................... 17

Figure 1: 88F6281 Pin Logic Diagram ............................................................................................................18

2 Unused Interface Strapping............................................................................................................ 49

3 88F6281 Pin Map and Pin List ......................................... ... ... ... ............................................. ......... 50

4 Pin Multiplexing ............................................................................................................................... 51

5 Clocking............................................................................................................................................ 60

6 System Power Up/Down and Reset Settings ................................................................................ 63

Figure 2: Power-Up Sequence Example..........................................................................................................64

Figure 3: Serial ROM Data Structure ...............................................................................................................70

Figure 4: Serial ROM Read Example...............................................................................................................71

7 JTAG Interface ................................................................................................................................. 73

8 Electrical Specifications (Preliminary) .......................................................................................... 75

Figure 5: SDRAM DDR2 Interface Test Circuit................................................................................................91

Figure 6: SDRAM DDR2 Interface Write AC Timing Diagram .........................................................................91

Figure 7: SDRAM DDR2 Interface Address and Control AC Timing Diagram.................................................92

Figure 8: SDRAM DDR2 Interface Read AC Timing Diagram.........................................................................92

Figure 9: RGMII Test Circuit ................. ... ... .....................................................................................................94

Figure 10: RGMII AC Timing Diagram...............................................................................................................94

Figure 11: GMII Test Circuit...............................................................................................................................95

Figure 12: GMII Output AC Timing Diagram............................................. ... ......................................................96

Figure 13: GMII Input AC Timing Diagram.........................................................................................................96

Figure 14: MII/MMII MAC Mode Test Circuit......................................................................................................97

Figure 15: MII/MMII MAC Mode Output Delay AC Timing Diagram...................................................................97

Figure 16: MII/MMII MAC Mode Input AC Timing Diagram................................................................................98

Figure 17: MDIO Master Mode Test Circuit.......................................................................................................99

Figure 18: MDC Master Mode Test Circuit ......................................................................................................100

Figure 19: SMI Master Mode Output AC Timing Diagram...............................................................................100

Figure 20: SMI Master Mode Input AC Timing Diagram..................................................................................100

Figure 21: JTAG Interface Test Circuit ............................................................................................................101

Figure 22: JTAG Interface Output Delay AC Timing Diagram .........................................................................102

Figure 23: JTAG Interface Input AC Timing Diagram ......................................................................................102

Figure 24: TWSI Test Circuit............................................................................................................................104

Figure 25: TWSI Output Delay AC Timing Diagram.........................................................................................104

Figure 26: TWSI Input AC Timing Diagram .....................................................................................................104

Figure 27: S/PDIF Test Circuit............................................................. ... .. ................................ .......................106

Page 14

88F6281 Hardware Specifications

Figure 28: Inter-IC Sound (I2S) Test Circuit ....................................................................................................107

Figure 29: Inter-IC Sound (I2S) Output Delay AC Timing Diagram .................................................................108

Figure 30: Inter-IC Sound (I2S) Input AC Timing Diagram ..............................................................................108

Figure 31: TDM Interface Test Circuit..............................................................................................................109

Figure 32: TDM Interface Output Delay AC Timing Diagram...........................................................................110

Figure 33: TDM Interface Input Delay AC Timing Diagram..............................................................................110

Figure 34: SPI (Master Mode) Test Circuit ......................................................................................................111

Figure 35: SPI (Master Mode) Output AC Timing Diagram .............................................................................112

Figure 36: SPI (Master Mode) Input AC Timing Diagram ................................................................................112

Figure 37: Secure Digital Input/Output (SDIO) Test Circuit.............................................................................113

Figure 38: SDIO Host in High Speed Mode Output AC Timing Diagram.........................................................114

Figure 39: SDIO Host in High Speed Mode Input AC Timing Diagram............................................................114

Figure 40: Transport Stream Interface Test Circuit..........................................................................................116

Figure 41: Transport Stream Output Interface AC Timing Diagram ................................................................116

Figure 42: Transport Stream Input Interface AC Timing Diagram ...................................................................117

Figure 43: PCI Express Interface Test Circuit..................................................................................................121

Figure 44: Low/Full Speed Data Signal Rise and Fall Time ............................................................................127

Figure 45: High Speed TX Eye Diagram Pattern Template............................ ... ... ...........................................128

Figure 46: High Speed RX Eye Diagram Pattern Template.............................................................................128

9 Thermal Data (Preliminary)........................................................................................................... 129

10 Package .......................................................................................................................................... 130

Figure 47: HSBGA 288-pin Package and Dimensions ...................................................................................130

11 Part Order Numbering/Package Marking..................................................................................... 132

Figure 48: Sample Part Number......................................................................................................................132

Figure 49: Commercial Package Marking and Pin 1 Location.........................................................................133

Page 15

Preface

About this Document

This datasheet provides the hardware specifications for the 88F6281 integrated controller. The hardware specifications include detailed pin information, configuration settings, electrical characteristics and physical specifications.

This datasheet is intended to be the basic source of information for designers of new systems. In this document, the “88F6281” is often referred to as the “device”.

1 Pin and Signal Descriptions

This section provides the pin logic diagram for the 88F6281 device and a detailed description of the pin assignments and their functionality.

Pin and Signal Descriptions

Page 18

Misc.

REF_CLK_XIN

Power

XOUT

SYSRSTn

USB

USB_DM

USB_DP

Gigabit Ethernet

GE_TXCLKOUT

GE_TXCTL

GE_TXD[3 :0 ]

GE_RXD [3:0 ] GE_RXCTL GE_RXCLK GE_MDC GE_MDIO

SDRAM

M_CLKOUT M_CLKOUTn M_CKE M_RASn M_CASn M_WEn M_A[14:0] M_BA[2:0] M_CSn[3:0] M_DQ[15:0] M_DQS[1:0] M_DQS n[1:0 ]

M_STARTBURST M_STARTBURST_IN M_PCAL M_NCAL

M_DM[1:0] M_ODT[1:0]

RTC

RTC_XIN

RTC_XOUT

SATA0/1

SATA0_T_P

SATA0_R_P SATA0_R_N

SATA0_T_N

SATA1_T_P SATA1_T_N SATA1_R_P SATA1_R_N

JTAG

JT_CLK

JT_TDI

JT_TDO

JT_TMS_CORE

JT_RSTn

JT_TMS_CPU

NAND Flash

NF_CLE NF_ALE NF_CEn NF_REn

NF_WEn

NF_IO[7:0]

MPP

MPP[49:0]

RESERVED

ISET

MRn

CPU_PLL_AVDD

CORE_PLL_AVDD

XTAL_AVDD

SATA0_AVDD SATA1_AVDD

CPU_PLL_AVSS

CORE_PLL_AVSS

XTAL_AVSS

VDD_M

VSS

VDDO

VDD_CPU

VDD

VDD_GE_A

PEX_AVDD

RTC_AVDD

USB_AVDD

SSCG_AVDD

SSCG_AVSS

RTC_AVSS

VHV

PCI Express

PEX_TX_P PEX_TX_N PEX_RX_P PEX_RX_N PEX_ISET

PEX_CLK_N

PEX_CLK_P

VDD_GE_B

88F6281 Hardware Specifications

1.1 Pin Logic

Figure 1: 88F6281 Pin Logic Diagram

NOTE: The GE_TXCLKOUT pin is an input only when used as the MII/MMII Transmit Clock.

For details about MPP configuration options see Section 4.1, Multi-Purpose Pins Functional

Summary, onpage 51.

Page 19

1.2 Pin Descriptions

This section details all the pins for the different interfaces providing a functional description of each pin and pin attributes.

Table 1<Default ¬¹ Font> defines the abbreviations and acronyms used in the pin description tables.

Table 1: Pin Functions and Assignments Table Key

Term Definition

[n] n - Represents the SERDES pair number <n> Represents port number when there are more than one ports Analog Analog Driver/Receiver or Power Supply Calib Calibration pad type CML Common Mode Logic CMOS Complementary Metal-Oxide-Semiconductor DDR Double Data Rate GND Ground Supply HCSL High-speed Current Steering Logic I Input I/O Input/Output O Output o/d Open Drain pin

The pin allows multiple drivers simultaneously (wire-OR conn ection).

A pull-up is required to sustain the inactive value. Power VDD Power Supply SSTL Stub Series Terminated Logic for 1.8V t/s Tri-State pin XXXn n - Suffix represents an Active Low Signal

Pin and Signal Descriptions

Pin Descriptions

Table 2: Interface Pin Prefix Codes

Interface Prefix

Misc N/A DDR SDRAM M_ PCI Express PEX_ SATA SATA0_

SATA1_ Gigabit Ethernet GE_ USB 2.0 USB_ JTAG JT_

Page 20

88F6281 Hardware Specifications

Table 2: Interface Pin Prefix Codes (Continued)

Interface Prefix

RTC RTC_ NAND Flash NF_ MPP N/A TWSI TW_ UART UA0_

UA1_ Audio AU_ SPI SPI_ SDIO SD_ TDM TDM_ PTP PTP_

Page 21

1.2.1 Power Supply Pins

Table 3 provides the voltage levels for the various interface pins. These do not include the analog

power supplies for the PLLs or PHYs which are explicitly mentioned in the other pin description tables.

Table 3: Power Pin Assignments

Pin and Signal Descriptions

Pin Descriptions

Pin Name I/O Pin

Description

Type

VDD I Power 1.0V Digital core voltage VDD_CPU I Power 1.1V Digital CPU voltage VDDO I Power 3.3V I/O power for MPP[49:36],MPP[19:0] and JTAG pins VDD_GE_A I Power 1.8V or 3.3V I/O supply voltage for RGMII and SMI interfaces

3.3V I/O supply voltage for GMII, MII/MMII, and SMI interfaces

VDD_GE_B I Power I/O power for MPP[35:20]

1.8V or 3.3V I/O supply voltage for RGMII interfaces

3.3V I/O supply voltage for GMII and MII/MMII interfaces

VDD_M I Power 1.8V I/O supply voltage for the DDR2 SDRAM interface VSS I GND VSS CPU_PLL_AVDD I Power 1.8V analog quiet power to CPU PLL

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide

for power supply filtering recommendations.

CPU_PLL_AVSS I GND CPU PLL ground CORE_PLL_AVDD I Power 1.8V analog quiet power to Core PLL

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendations.

CORE_PLL_AVSS I GND Core PLL ground SSCG_AVDD I Power 1.8V quiet power supply to the internal Spread Spectrum Clock

Generator SSCG_AVSS I GND Ground for the internal Spread Spectrum Clock Generator XTAL_ AVDD I Power 1.8V analog quiet power to on-chip clock inverter for supporting external

crystal, and on-chip current reference for SATA and USB PHYs

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendations.

XTAL_ A VSS I GND Ground for supporting external crystal, and on-chip current reference for

SATA and USB PHYs VHV I Power I/O supply voltage for eFuse:

• 2.5V for eFuse burning only

• 1.0V for eFuse reading only

Page 22

88F6281 Hardware Specifications

Table 3: Power Pin Assignments (Continued)

Pin Name I/O Pin

Description

Type

PEX_AVDD I Power PCI Express PHY quiet power supply 1.8V

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendations.

SATA0_AVDD SATA1_AVDD

I Power SATA II port0/1 quiet 3.3V power supply

NOTE: See 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide

for power supply filtering recommendation.

USB_AVDD I Power USB 2.0 PHY quiet 3.3V power supply

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendation.

RTC_AVDD I Power 1.5V (via battery) or 1.8V (via the board) RTC interface voltage RTC_AVSS I GND RTC ground

Page 23

1.2.2 Miscellaneous Pin Assignment

The Miscellaneous signal list contains clock and reset, test, and related signals.

Table 4: Miscellaneous Pin Assignments

Pin and Signal Descriptions

Pin Descriptions

Pin Name I/O Pin

Type

Power Rail

Description

REF_CLK_XIN I Analog XTAL_AVDD Reference clock input from external oscillator or input from

external crystal. Used as input to core , CPU, SATA, and USB PLLs.

XOUT O Analog XTAL_AVDD XTAL_OUT

Feedback signal to external crystal. When not used, leave this pin floating.

SYSRSTn I CMOS VDDO System reset

Main reset signal of the device clock. Used to reset all units to their initial state. When in the reset state, most output pins are in Tri-State.

SYSRST_OUTn O CMOS VDDO Reset request from the device to the board reset logic.

This pin is multiplexed on the MPP pins (see Section 4, Pin

Multiplexing, on page 51).

PEX_RST_OUTn O CMOS VDDO Optional PCI Express Endpoint card reset output

This pin is multiplexed on the MPP pins (see Section 4, Pin

Multiplexing, on page 51).

TP O Analog Analog Test Point for SATA, USB, and PCI Express

interfaces For internal use. Leave this pin unconnected.

ISET I Analog Current reference for both the USB and SATA PHYs.

Terminate this pin with a 6.04 k

Ω resistor, pulled down.

MRn I CMOS VDD_GE_A Active-Low, Manual Reset Input

SYSRST_OUTn is asserted low as long as the MRn input signal is asserted low, and for additional 20 ms after MRn (manual reset) de-assertion This pin is internally pulled up.

RESERVED Reserved for Marvell

¬Æ

future usage.

Leave unconnected externally.

NC Reserved for Marvell

¬Æ

future usage.

Leave unconnected externally.

Page 24

88F6281 Hardware Specifications

1.2.3 DDR SDRAM Interface Pin Assignments

Table 5: DDR SDRAM Interface Pin Assignments

Pin Name I/O Pin

Type

M_CLKOUT

O SSTL VDD_M SDRAM Differential Clock Pair

Power Rail

Description

M_CLKOUTn M_CKE O SSTL VDD_M Driven high to enable SDRAM clock.

Driven low when setting the SDRAM to Self-refresh mode.

M_RASn O SSTL VDD_M SDRAM Row Address Select

Asserted to indicate an active ROW address driven on the SDRAM address lines.

M_CASn O SSTL VDD_M SDRAM Column Address Select

Asserted to indicate an active column address driven on the SDRAM address lines.

M_WEn O SSTL VDD_M SDRAM Write Enable

Asserted to indicate a write command to the SDRAM.

M_A[14:0] O SSTL VDD_M SDRAM Address

Driven with M_BA[2:0] during RASn and CASn cycles to generate the SDRAM address.

M_BA[2:0] O SSTL VDD_M Driven during M_RASn and M_CASn cycles to select one of

the eight SDRAM virtual banks. NOTE: If an SDRAM device does not support the BA[2] pin,

leave the M_BA[2] unconnected.

M_CSn[3:0] O SSTL VDD_M SDRAM Chip Selects

Asserted to select a specific SDRAM Physical bank.

M_DQ[15:0] t/s

SSTL VDD_M SDRAM Data Bus

I/O

Driven during write. Driven by SDRAM during reads.

M_DQS[1:0], M_DQSn[1:0]

t/s

SSTL VDD_M SDRAM Data Strobe

I/O

Driven by the 88F6281 during write. Driven by SDRAM during reads.

M_DM[1:0] O SSTL VDD_M SDRAM Data Mask

Asserted by the 88F6281 to select the specific byte out of the 16-bit data to be written to the SDRAM.

M_ODT[1:0] O SSTL VDD_M SDRAM On Die Termination control

Driven high to connect the SDRAM on die termination. Driven low to disconnect the SDRAM’s termination.

NOTE: For the recommended setting, refer to the 88F6180,

88F6190, 88F6192, and 88F6281 Design Guide.

Page 25

Table 5: DDR SDRAM Interface Pin Assignments (Continued)

Pin and Signal Descriptions

Pin Descriptions

Pin Name I/O Pin

Type

Power Rail

Description

M_STARTBURST O SSTL VDD_M Start Burst

88F6281 indication of starting a burst read transaction. Asserted with the first M_CASn cycle of SDRAM access. NOTE: Must be routed on board to the SDRAM, and back to

the 88F6281 as M_STARTBURST_IN. For the recommended length calculation for this routing and termination requirements, see the 8 8F6180, 88F619 0, 88F6192, and 88F6281 Design Guide.

M_START

I SSTL VDD_M Start Burst Input

BURST_IN M_PCAL I Calib SDRAM interface P channel output driver calibration. Connect

to VSS through a resistor. The resistor value can vary between 30–70 ohm.

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281

Design Guide for the recommended values of the

calibration resistors.

M_NCAL I Calib SDRAM interface N channel output driver calibration. Connect

to M_VDD through a resistor. The resistor value can vary between 30–70 ohm.

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281

Design Guide for the recommended values of the

calibration resistors.

Page 26

88F6281 Hardware Specifications

1.2.4 PCI Express Interface Pin Assignments

Table 6: PCI Express Interface Pin Assignments

Pin Name I/O Pin

Type

Power Rail

Description

PEX_CLK_P/N I/O HCSL PEX_AVDD PCI Express Reference Clock

100 MHz, differential This clock can be configured as input or output according to the reset strap (see Table 32, Reset Configuration, on page 67). NOTE: For Output mode, 50-ohm, pull-down resistors are

required.

PEX_TX_P/N O CML PEX_AVDD Transmit Lane

Differential pair of PCI Express transmit data

PEX_RX_P/N I CML PEX_AVDD Receive Lane

Differential pair of PCI Express receive data

PEX_ISET I Analog Current reference. Pull down to VSS through a 5 k

See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for the recommended resistor value.

Ω resistor .

Page 27

1.2.5 SATA Interface Pin Assignments

Table 7: SATA Port Interface Pin Assignment

Pin and Signal Descriptions

Pin Descriptions

Pin Name I/O Pin

Type

SATA0_T_P/N

O CML SATA0/1_AVDD Transmit Data: Differential analog output of SATA II

SATA1_T_P/N SATA0_R_P/N

I CML SATA0/1_AVDD Receive Data: Differential analog input of SATA II port0/1

SATA1_R_P/N SATA0_PRESENTn

O CMOS VDDO/

SATA1_PRESENTn

SATA0_ACTn

O CMOS VDDO/

SATA1_ACTn

Power Rail Description

port0/1

When this signal is asserted there is an active link

VDD_GE_B

between the SATA II port and the external device (disk). NOTE: These signals are multiplexed on the MPP pins

(see Section 4, Pin Multiplexing, on page 51).

When this signal is asserted, there is an active and used

VDD_GE_B

link between the SATA II port and the external device (disk). NOTE: These signals are multiplexed on the MPP pins

(see Section 4, Pin Multiplexing, on page 51).

Page 28

88F6281 Hardware Specifications

1.2.6 Gigabit Ethernet Port Interface Pin Assignments

For additional information about the Gigabit Ethernet port pin functions refer to Section 4.2, Gigabit

Ethernet (GbE) Pins Multiplexing on MPP, on page 57.

Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments

Pin Name I/O Pin

Type

Power Rail

Description

Port0—Dedicated GbE Pins

GE_TXCLKOUT t/s OCMOS VDD_GE_A RGMII Transmit Clock

RGMII transmit reference output clock for GE_TXD[3:0] and GE_TXCTL. Provides 125 MHz, 25 MHz or 2.5 MHz clock. Not used in MII/MMII mode.

I MII/MMII Transmit Clock

MII/MMII transmit reference clock fro m PHY. Provides the timing reference for the transmission of the MII transmit clock, transmit enable, and GE_TXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

t/s O

GMII Transmit Clock Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz.

GE_TXD[3:0] t/s OCMOS VDD_GE_A RGMII Transmit Data

Contains the transmit data nibble outp ut s that run at doubl e dat a rate with bits [3:0] driven on the rising edge of GE_TXCLKOUT and bits [7:4] driven on the falling edge.

MII/MMII Transmit Data Contains the transmit data nibble outputs that are synchronous to the transmit clock input.

GMII Transmit Data Contains the transmit data nibble outputs.

GE_TXCTL t/s OCMOS VDD_GE_A RGMII Transmit Control

Transmit control synchronous to the GE_TXCLKOUT output rising/falling edge. GE_TXEN is driven on the rising edge of GE_TXCLKOUT. A logical derivative of transmit enable and transmit error is driven on the falling edge of GE_TXCLKOUT.

MII/MMII Transmit Enable Indicates that the packet is being transmitted to the PH Y. It Is synchronous to transmit clock.

GMII Transmit Enable Indicates that the packet is being transmitted to the PH Y. It Is synchronous to GE_TXCLKOUT.

Page 29

Pin and Signal Descriptions

Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)

Pin Descriptions

Pin Name I/O Pin

Type

Power Rail

Description

GE_RXD[3:0] I CMOS VDD_GE_A RGMII Receive Data

Contains the receive data nibble inputs that are synchronous to GE_RXCLK input rising/falling edge.

MII/MMII Receive Data Contains the receive data nibble inputs that are synchronous to GE_RXCLK input.

GMII Receive Data Contains the receive data nibble inputs.

GE_RXCTL I CMOS VDD_GE_A RGMII Receive Control

GE_RXCTL is presented on the rising edge of GE_RXCLK. A logical derivative of receive data vali d and receive d ata error is presented on the falling edge of RXCLK.

MII/MMII Receive Data Valid GMII Receive Data Valid.

GE_RXCLK I CMOS VDD_GE_A RGMII Receive Clock

The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock derived from the received data stream.

MII/MMII Receive Clock Provides the timing reference for the reception of the receive data valid, receive error, and GE_RXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

GMII Receive Clock Provides the timing reference for the reception of the GE_RXDV, receive error and receive data signals. This clock operates at 125 MHz

Port1—Multiplexed GbE Pins

MPP[23:20]/ GE1[3:0]

t/s OCMOS VDD_GE_B RGMII Transmit Data

Contains the transmit data nibble outp ut s that run at doubl e dat a rate with bits [3:0] presented on the rising edge of GE_TXCLKOUT and bits [7:4] presented on the falling edge.

MII/MMII Transmit Data Contains the transmit data nibble outputs that are synchronous to the transmit clock input.

GMII Transmit Data Contains the transmit data nibble outputs.

Page 30

88F6281 Hardware Specifications

Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)

Pin Name I/O Pin

Type

MPP[27:24]/

I CMOS VDD_GE_B RGMII Receive Data

GE1[7:4]

Power Rail

Description

Contains the receive data nibble inputs that are synchronous to GE_RXCLK input rising/falling edge.

MII/MMII Receive Data Contains the receive data nibble inputs that are synchronous to GE_RXCLK input.

GMII Receive Data Contains the receive data nibble inputs.

MPP[28]/GE1[8] I CMOS VDD_GE _ B MII/MMII Coll ision Det e ct

Indicates a collision has been detected on the wire. This input is ignored in full-duplex mode. Collision detect is not synchronous to any clock.

GMII Collision Detect

MPP[29]/GE1[9] I CMOS VDD_GE _B MII/MMII Transmit Clock

t/s O

GMII Transmit Clock Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz.

MPP[30]/GE1[10] I CMOS VDD_GE_B RGMII Receive Control

GE_RXCTL is presented on the rising edge of GE_RXCLK. A logical derivative of receive data vali d and receive d ata error is presented on the falling edge of RXCLK.

MII/MMII Receive Data Valid GMII Receive Error

MPP[31]/GE1[11] I CMOS VDD_GE_B RGMII Receive Clock

The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock derived from the received data stream.

MII/MMII Receive Clock Provides the timing reference for the reception of the receive data valid, receive error, and GE_RXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

Page 31

Pin and Signal Descriptions

Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)

Pin Descriptions

Pin Name I/O Pin

Type

Power Rail

Description

MPP[32]/GE1[12] I/O CMOS VDD_GE_B RGMII Transmit Clock

RGMII transmit reference output clock for GE_TXD[3:0] and GE_TXCTL Provides 125 MHz, 25 MHz or 2.5 MHz clock. Not used in MII/MMII mode.

MII/MMII Carrier Sense Indicates that the receive medium is non-idle. In half-duplex mode, GE_CRS is also asserted during transmission. Carrier sense is not synchronous to any clock.

GMII Carrier Sense

MPP[33]/GE1[13] t/s OCMOS VDD_GE_B RGMII Transmit Control

Transmit control synchronous to the GE_TXCLKOUT output rising/falling edge. GE_TXEN is presented on the rising edge of GE_TXCLKOUT. A logical derivative of transmit enabl e transmit error i s presented on the falling edge of GE_TXCLKOUT.

MII/MMII Transmit Error It is synchronous to transmit clock. NOTE: Multiplexed on MPP.

GMII Transmit Error It Is synchronous to GE_TXCLKOUT. NOTE: Multiplexed on MPP.

MPP[34]/GE1[14] O CMOS VDD_GE_B MII/MMII Transmit Enable

Indicates that the packet is being transmitted to the PH Y. It Is synchronous to transmit clock.

MPP[35]/GE1[15] I CMOS VDD_GE_B MII/MMII Receive Error

Indicates that an error symbol, a false carrier, or a carrier extension symbol is detected on the cable. It is synchronous to GE_RXCLK input. NOTE: Multiplexed on MPP.

Page 32

88F6281 Hardware Specifications

1.2.7 Serial Management Interface (SMI) Interface Pin Assignments

Table 9: Serial Management Interface (SMI) Pin Assignments

Pin Name I/O Pin

Type

Power Rail

Description

GE_MDC t/s OCMOS/ VDD_GE_A Management Data Clock

MDC is derived from TCLK divided by 128. Provides the timing reference for the transfer of the MDIO si gnal .

GE_MDIO t/s

CMOS VDD_GE_A Management Data In/Out

I/O

Used to transfer control and status information between PHY devices and the GbE controller. NOTE: An external pullup is requi red.

Page 33

1.2.8 USB 2.0 Interface Pin Assignments

Table 10: USB 2.0 Interface Pin Assignments

Pin and Signal Descriptions

Pin Descriptions

Pin Name I/O Pin

Type

USB_DP

I/O CML USB_AVDD USB 2.0 Data Differential Pair

USB_DM

Power Rail

Description

Page 34

88F6281 Hardware Specifications

1.2.9 JTAG Interface Pin Assignment

Table 11: JTAG Pin Assignment

Pin Name I/O Pin

Type

Power Rail

Description

JT_CLK I CMOS VDDO JTAG Clock

Clock input for the JTAG controller. NOTE: This pin is internally pulled down to 0.

JT_RSTn I CMOS VDDO JTAG Reset

When asserted, resets the JTAG controller. NOTE: This pin is internally pulled down to 0.

JT_TMS_CPU I CMOS VDDO CPU JTAG Mode Select

Controls CPU JTAG controller state. Sampled with the rising edge of JT_CLK. NOTE: This pin is internally pulled up to 1.

JT_TMS_CORE I CMOS VDDO Core JTAG Mode Select

Controls the Core JTAG controller state. Sampled with the rising edge of JT_CLK. NOTE: This pin is internally pulled up to 1.

JT_TDO O CMOS VDDO JTAG Data Out

Driven on the falling edge of JT_CLK.

JT_TDI I CMOS VDDO JTAG Data In

JTAG serial data input. Sampled with the JT_CLK rising edge. NOTE: This pin is internally pulled up to 1.

1. If this pull-down conflicts with other devices, the JTAG tool must not use this signal. This signal is not mandatory for the JTAG interface, since the TAP (Test Access Port) can be reset by driving the JT_TMS signal HIGH for 5 JT_CLK cycles.

Page 35

Pin and Signal Descriptions

1.2.10 Real Time Clock (RTC) Interface Pin Assignments

Table 12: RTC Interface Pin Assignments

Pin Name I/O Pin

Type

RTC_XIN I Analog RTC_AVDD RTC Crystal Clock Input RTC_XOUT O Analog RTC_AVDD RTC Crystal Clock Feedback

Power Rail

Description

Pin Descriptions

Page 36

88F6281 Hardware Specifications

1.2.11 NAND Flash Interface Pin Assignment

Table 13: NAND Flash Interface Pin Assignment

Pin Name I/O Pin

Type

Power Rail

Description

NF_IO[7:0] I/O CMOS VDDO Data Input/Output

Used to output command, address and data, and to input data during read operations. NOTE: All of the NF_IO pins are multiplexed on the MPP pins

(see Section 4, Pin Multiplexing, on page 51)

NF_CLE O CMOS VDDO Command Latch Enable

Controls the activating path for commands sent t o the command register.

NF_ALE O CMOS VDDO Address Latch Enable

Controls the activating path for the address to the internal address registers.

NF_CEn O CMOS VDDO Chip Enable

Controls the device selection.

NF_REn O CMOS VDDO Read Enable

Controls the serial data-in.

NF_WEn O CMOS VDDO Write Enable

Controls writes to the NF_IO[7:0] ports.

Page 37

1.2.12 MPP Interface Pin Assignment

Note

Table 14: MPP Interface Pin Assignment

Pin and Signal Descriptions

Pin Descriptions

Pin Name I/O Pin

Type

MPP[19:0] t/s

CMOS VDDO Multi Purpose Pin

I/O

MPP[35:20] t/s

CMOS VDD_GE_B Multi Purpose Pin

I/O

MPP[49:36] t/s

CMOS VDDO Multi Purpose Pin

I/O

The various functionalities of the MPP pins are detailed in Section 4, Pin Multiplexing,

on page 51

Power Rail

Description

Various functionalities

Page 38

Note

88F6281 Hardware Specifications

1.2.13 Two-Wire Serial Interface (TWSI) Interface

All of the TWSI signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing,

on page 51

Table 15: Two-Wire Serial Interface (TWSI) Interface Pin Assignment

Pin Name I/O Pin

Type

TW_SDA o/d

TW_SCK o/d

CMOS VDDO TWSI Port Serial Data

I/O

CMOS VDDO TWSI Port Serial Clock

I/O

Power Rail

Description

Address or write data driven by the TWSI master or read response data driven by the TWSI slave. NOTE: Requires a pull-up resistor to VDDO.

Serves as output when acting as an TWSI master. Serves as input when acting as an TWSI slave. NOTE: Requires a pull-up resistor to VDDO.

Page 39

1.2.14 UART Interface

Note

All of the UART signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing,

on page 51

Table 16: UART Port 0/1 Interface Pin Assignment

Pin Name I/O Pin

Type

UA0/1_RXD I CMOS VDDO UART Port 0/1 RX Data UA0/1_TXD O CMOS VDDO UART Port 0/1 TX Data UA0/1_CTS I CMOS VDDO Clear to Send UA0/1_RTS O CMOS VDDO Request to Send

Power Rail

Description

Pin and Signal Descriptions

Pin Descriptions

Page 40

Note

88F6281 Hardware Specifications

1.2.15 Audio (S/PDIF / I2S) Interface

 All of the Audio signals are multiplexed on the MPP pins (see Section 4, Pin

Multiplexing, on page 51).

 If the Audio interface is not used, leave all of the signals unconnected.  The Audio signals are powered on VDDO or on VDD_GE_B, based on the pin

multiplexing option.

Table 17: Audio (S/PDIF / I2S) Interface Signal Assignment

Pin Name I/O Pin

Type

AU_SPDIFI I CMOS VDDO/

AU_SPDIFO O CMOS VDDO/

AU_

O CMOS VDDO/

SPDFRMCLK

AU_I2SBCLK O CMOS VDDO/

AU_I2SDO O CMOS VDDO/

AU_I2SLRCLK O CMOS VDDO/

AU_I2SMCLK O CMOS VDDO/

AU_I2SDI I CMOS VDDO/

AU_EXTCLK I CMOS VDDO/

Power Rail

VDD_GE_B

Description

S/PDIF In

S/PDIF Out

S/PDIF Recovered Master Clock (256 x F For the frequency of this clock, see the Audio External Reference Clock section of Table 45, Reference Clock AC

Timing Specifications, on page86.

S Bit Clock (64 x Fs)

Transmitter Data Out

S Left/Right Clock (1 x Fs)

S Master Clock (256 x Fs)

S Receiver Data In

External Audio Clock For the frequency of this clock, see the Audio External Reference Clock section of Table 45, Reference Clock AC

Timing Specifications, on page86.

)

1. Fs is the audio sample rate.

Page 41

Pin and Signal Descriptions

Note

1.2.16 Serial Peripheral Interface (SPI) Interface

All of the SPI signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing,

on page 51

Table 18: Serial Peripheral Interface (SPI) Interface Signal Assignment

Pin Name

SPI_MOSI

SPI_MISO

SPI_SCK SPI_CSn

1. MOSI = Master Out Slave In.

2. MISO = Master In Slave Out.

I/O

Pin Type Power Rail

O CMOS VDDO SPI Data Output

I CMOS VDDO SPI Data Input

O CMOS VDDO SPI Clock O CMOS VDDO SPI Chip Select

Description

Data is output from the master and input to the slave.

Data is input to the master and output from the slave.

NOTE: This pin requires an external pull up.

Pin Descriptions

Page 42

Note

88F6281 Hardware Specifications

1.2.17 Secure Digital Input/Output (SDIO) Interface

All of the SDIO signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing,

on page 51

Table 19: Secure Digital Input/Output (SDIO) Interface Signal Assignment

Pin Name

SD_CLK O CMOS VDDO SDIO Clock SD_CMD I/O CMOS VDDO SDIO Command

SD_D[3:0] I/O CMOS VDDO SDIO Data Input/Output

I/O

Pin Type Power Rail

Description

Used to transfer a command serially from the SDIO host to the SDIO device. Used to transfer a command response serially from the SDIO device to the SDIO host. NOTE: This pin requires a pull up on board.

Used to transfer data from the SDIO host to the SDIO device or vice versa. NOTE: These pins require a pull up on board.

Page 43

Pin and Signal Descriptions

Note

1.2.18 Time Division Multiplexing (TDM) Interface

 All of the TDM signals are multiplexed on the MPP pins (see Section 4, Pin

Multiplexing, on page 51).

 The TDM signals are powered on VDDO or on VDD_GE_B, based on the pin

multiplexing option (see Section 4, Pin Multiplexing, on page 51).

Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment

Pin Name

I/O

Pin Type Power Rail

TDM_CH0_TX_QLO CMOS VDDO/

VDD_GE_B

TDM_CH2_TX_QLO CMOS VDDO/

VDD_GE_B

TDM_CH0_RX_QLO CMOS VDDO/

VDD_GE_B

TDM_CH2_RX_QLO CMOS VDDO/

VDD_GE_B

TDM_CODEC_ INTn

TDM_CODEC_ RSTn

I CMOS VDDO/

VDD_GE_B

O CMOS VDDO/

VDD_GE_B

TDM_PCLK I/O CMOS VDDO/

VDD_GE_B

TDM_FS I/O CMOS V DDO/

VDD_GE_B

TDM_DRX I CMOS VDDO/

VDD_GE_B

TDM_DTX O CMOS VDDO/

VDD_GE_B

TDM_SPI_CS[1:0]

O CMOS VDDO/

VDD_GE_B

TDM_SPI_SCK O CMOS VDDO/

VDD_GE_B

Description

TDM Channel0 Transmit Qualifier

TDM Channel2 Transmit Qualifier

TDM Channel0 Receive Qualifier

TDM Channel2 Receive Qualifier

Interrupt Signal FROM the SLIC/codec

SLIC/codec

Reset Signal

PCM Audio Bit Clock

TDM Frame Sync Signal

PCM Audio Input Data (for recording)

PCM Audio Output Data (for playback)

Active low SPI chip selects driven by the host to the codec for register access. Always asserted for eight SCLK cycles at a time. Only Byte-by-Byte mode codec register read/write is supported.

Serial SPI clock from the host to the codec for register acce ss. This is an RTO (return to one) clock. It toggles for eight cycles at a time (for 1 byte transfer) during codec register access, then it returns to high. The host drives write data on TDM_SPI_MOSI on the negative edge of TDM_SPI_SCK, and captures read data from the codec on the positive edge of TDM_SPI_SCK.

Pin Descriptions

Page 44

88F6281 Hardware Specifications

Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment (Continued)

Pin Name

I/O

Pin Type Power Rail

TDM_SPI_MOSI O CMOS VDDO/

VDD_GE_B

TDM_SPI_MISO I CMOS VDDO/

VDD_GE_B

Description

Serial SPI data from the host to the codec for register access. When TDM_SPI_CS is asserted low, the data is driven from the host on the negative edge of TDM_SPI_SCK. It is always driven for eight TDM_SPI_SCK cycles at a time. In a byte, the data can be driven MSB or LSB first.

Serial SPI read data from the CODEC to the host for register access. When TDM_SPI_CS is asserted low, this data is driven from CODEC on negative edge of TDM_SPI_SCK. It is always driven for eight TDM_SPI_SCK cycles at a time. The CODEC drives data on this line only for a read o peration, when it ge ts command and address in previous bytes from the host on TDM_SPI_MOSI In a byte, the data can be driven MSB or LSB first.

Page 45

1.2.19 Transport Stream (TS) Interface

Note

 All of the TS signals are multiplexed on the MPP pins (see Section 4, Pin

Multiplexing, on page 51).

 The TS signals are powered on VDDO or on VDD_GE_B based on the pin

multiplexing option (see Section 4, Pin Multiplexing ).

Table 21: Transport Stream (TS) Interface Signal Assignment

Pin Name

I/O

Pin Type Power Rail

TSMP[0] I CMOS VDDO/

VDD_GE_B

TSMP[1] I/O CMOS VDDO/

VDD_GE_B

TSMP[2] I/O CMOS VDDO/

VDD_GE_B

TSMP[3] I/O CMOS VDDO/

VDD_GE_B

TSMP[4] I/O CMOS VDDO/

VDD_GE_B

TSMP[5] I/O CMOS VDDO/

VDD_GE_B

TSMP[6] I/O CMOS VDDO/

VDD_GE_B

Description

EXT_CLK External clock that can be used to drive the TS0_CLK and TS1_CLK

TS0_CLK Port0 TS clock.

• If TS0_VA L is used, the clock may be continuous.

• If TS0_VAL is not used, the clock may toggle onl y when valid data is available on TS0_DATA.

TS0_SYNC Port0 Sync/Frame Start Indicator or Packet Clock. The TS0_SYNC in parallel mode is a pulse that is active during the first (Sync) byte of the TS packet. In serial mode, the TS0_SYNC pulse may be active for the entire byte or only for the first bit. The polarity is programmable to be eit her active high or active low.

TS0_VAL Port0 V alid Data Indicator When this signal is used and is valid, it indicates that valid dat a is present on TS0_DATA. TS0_VAL is active during the TS frame packet data and inactive when there is no TS synchronization. In output mode, the polarity of TS0_VAL is programmable to be either active high or active low.

TS0_ERR Port0 Uncorrectable Packet Error When this signal is used, an error indicates that the packet contains an uncorrectable error, and therefore should not be used. In output mode, the TS0_ERR is active during the entire TS frame.

TS0_DATA[0] Port0 TS Data bit 0 in both parallel and serial modes. In Serial mode TS0_DATA[0] is used as data input or output.

• Parallel Mode: TS0_DATA[1]: Port0 TS Data bit 1

• Serial Mode: TS1_CLK: Port1 TS clock.

- If TS1_VAL is used, the clock may be continuous.

- If TS1_VAL is not used, the clock may toggle only when valid data is available on TS1_DATA

Pin and Signal Descriptions

Pin Descriptions

Page 46

88F6281 Hardware Specifications

Table 21: Transport Stream (TS) Interface Signal Assignment (Continued)

Pin Name

I/O

Pin Type Power Rail

TSMP[7] I/O CMOS VDDO/

VDD_GE_B

TSMP[8] I/O CMOS VDDO/

VDD_GE_B

TSMP[9] I/O CMOS VDDO/

VDD_GE_B

TSMP[10] I/O CMOS VDDO/

VDD_GE_B

TSMP[11] I/O CMOS VDDO/

VDD_GE_B

TSMP[12] I/O CMOS VDDO/

VDD_GE_B

Description

• Parallel Mode: TS0_DATA[2]: Port0 TS Data bit 2

• Serial Mode: TS1_SYNC: Port1 Sync/Frame Start Indicator or Packet Clock. The TS1_SYNC pulse may be active for the entire byte or only for the first bit. The p olarity i s programmable to be e ither active high or active low

• Parallel Mode: TS0_DATA[3]: Port0 TS Data bit 3

• Serial Mode: TS1_VAL: Port1Valid Data Indicator When this signal is used and is valid, it indicates that valid data is present on TS1_DATA[0]. TS1_VAL is active during the TS frame packet data and inactive when there is no TS synchronization. In output mode, the polarity of TS1_VAL is programmable to be either active high or active low.

• Parallel Mode: TS0_DATA[4]: Port0 TS Data bit 4

• Serial Mode: TS1_ERR: Port1 Uncorrectable Packet Error When this signal is used, an error indicates that the packet contains an uncorrectable error, and, therefore, should not be used. In output mode the TS1_ERR is active during the entire TS frame.

• Parallel Mode: TS0_DATA[5]: Port0 TS Data bit 5

• Serial Mode: TS1_DATA[0]: Port1 TS Data bit 0, used as data input or output.

TS0_DATA[6] Port0 TS Data bit 6 This pin is only valid in Parallel mode.

TS0_DATA[7] Port0 TS Data bit 7 This pin is only valid in Parallel mode.

Page 47

Pin and Signal Descriptions

Note

1.2.20 Precise Timing Protocol (PTP) Interface

All of the PTP signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing,

on page 51

Table 22: Precise Timing Protocol (PTP) Interface Signal Assignment

Pin Name

PTP_CLK I CMOS VDDO PTP Clock PTP_EVENT_REQ I CMOS VDDO Trigger generation to the PTP core. PTP_TRIG_GEN O CMOS VDDO Trigger generated by the PTP core.

I/O

Pin Type Power Rail

Description

Pin Descriptions

Page 48

88F6281 Hardware Specifications

1.3 Internal Pull-up and Pull-down Pins

Some pins of the device package are connected to internal pull-up and pull-down resistors. When these pins are Not Connected (NC) on the system board, these resistors set the default value for input and sample at reset configuration pins.

The internal pull-up and pull-down resistor value is 50 kΩ. An external resistor with a lower value can override this internal resistor.

Table 23: Internal Pull-up and Pull-down Pins

Pin Name Pin Number Pull up/Pull down

GE_TXD[0] H02 Pull down GE_TXD[1] H01 Pull down GE_TXD[2] H03 Pull up GE_TXD[3] H04 Pull up GE_TXCTL J04 Pull down GE_MDC L03 Pull up JT_TMS_CORE T14 Pull up JT_RSTn T15 Pull down JT_TDI R14 Pull up JT_TMS_CPU V15 Pull up NF_ALE R10 Pull up

NF_REn U11 Pull down NF_CLE R11 Pull down NF_CEn V11 Pull up NF_WEn V12 Pull up MRn F04 Pull up MPP[1] V08 Pull down MPP[2] V07 Pull down MPP[3] V09 Pull down MPP[4] T09 Pull up MPP[5] T10 Pull up MPP[7] R06 Pull up MPP[10] R07 Pull down MPP[11] T07 Pull up MPP[12] U12 Pull down MPP[14] V13 Pull up MPP[18] V10 Pull up MPP[19] U10 Pull up MPP[33] N03 Pull down

Page 49

Unused Interface Strapping

2 Unused Interface Strapping

Table 24 lists the signal strapping to be used for systems in which some of the device interfaces are unused (not

connected).

Table 24: Unused Interface Strapping

Unused Interface Strapp ing

Ethernet SMI Pull up GE_MDIO. MPP Configure any unused MPP pin to GPIO output.

Leave the power supply connected.

• If the related power supply is VDDO, leave it connected to 3.3V.

• If the related power supply is VDD_GE_B, leave it connected to either 3.3V or 1.8V.

USB Discard the power filter.

Leave USB_AVDD connected to 3.3V. All other signals can be left unconnected.

PCI Express Discard the analog power filters.

Leave PEX_AVDD connected to 1.8V. Pull down the PEX_CLK_N signal through a 50 k Pull up the PEX_CLK_P signal through a 16 k All other signals can be left unconnected. Configure the PEX_CLK_P and PEX_CLK_N signals as inputs, as indicated in Table 32,

Reset Configuration, on page 67.

SATA Discard the analog power filters.

SATA0_AVDD/SATA1_AVDD can be left unconnected. RTC Connect RTC_AVDD, RTC_AVSS, RTC_XIN, and RTC_XOUT to GND. SSCG Discard the power filter.

Leave SSCG_AVDD connected to 1.8V. eFuse Connect VHV to VDD

Ω resistor to GND.

Ω resistor to 1.8V.

Page 50

Note

88F6281 Hardware Specifications

3 88F6281 Pin Map and Pin List

The 88F6281 pin list is provided as an Excel file attachment.

To open the attached Excel pin list file, double-click the pin icons below:

88F6281 Pin Map and Pin List.xls

File attachments are only supported by Adobe Reader 6.0 and above. To download the latest version of free Adobe Reader go to http://www.adobe.com.

Page 51

Multi-Purpose Pins Functional Summary

4 Pin Multiplexing

4.1 Multi-Purpose Pins Functional Summary

The 88F6281 device contains 50 Multi-Purpose Pins (MPP). Each one can be assigned to a different functionality through the MPP Control register.

 General Purpose pins: MPP[5:0] and MPP[49:7]:

• GPIO (input/output): MPP[0], MPP[4], MPP[9:8], MPP[11], MPP[17:13], MPP[32:20], and

MPP[49:34]

• GPO (output): MPP[3:1], MPP[5], MPP[7], MPP[10], MPP[12], MPP[19:18], and MPP[33]

 SYSRST_OUTn: Reset request from the device to the board reset logic. This pin is an output.

SYSRST_OUTn is the default setting for MPP[6].

 PEX_RST_OUTn: Optional PCI Express Endpoint card reset output.  MII/MMII/GMII/RGMII interface signals  SATA0/1_ACTn/SATA0/1_PRESENTn (port 0 and port 1): SATA active and SATA present

indications—see the SATA section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

 NF_IO[7:0] (NAND Flash data [7:0])  SPI interface: SPI_MOSI, SPI_MISO, SPI_SCK, SPI_CSn  UART interface (port 0 and port 1): Transmit and receive functions: UA0_TXD, UA0_RXD,

UA1_TXD, UA1_RXD, and Modem control functions: UA0_RTSn, UA0_CTSn, UA1_RTSn, UA1_CTSn

 SDIO interface: SD_CLK, SD_CMD, SD_D[3:0]  Audio interface signals: AU_SPDIFI, AU_SPDIFO, AU_SPDIFRMCLK, AU_I2SBCLK,

AU_I2SDO, AU_I2SLRCLK, AU_I2SMCLK, AU_I2SDI, AU_EXTCLK

 TS (Transport Stream) interface signals: TSMP[12:0]  TDM/SPI interface signals: TDM_CH0/2_TX_QL, TDM_CH0/2_RX_QL, TDM_SPI_CS0/1,

TDM_SPI_SCK, TDM_SPI_MOSI, TDM_SPI_MISO, TDM_CODEC_INTn, TDM_CODEC_RSTn, TDM_PCLK, TDM_FS, TDM_DRX, TDM_DTX

 PTP signals: PTP_EVENT_REQ, PTP_TRIG_GEN, PTP_CLK  TWSI signals: TW_SDA, TW_SCK

Pin Multiplexing

Page 52

88F6281 Hardware Specifications

MPP pins can be assigned to different functionalities through the MPP Control register, as shown in

Table 25.

Table 25: MPP Functionality

MPP[19:0]: MPP[35:20]: MPP[49:36]:

GPIO GPIO GPIO SATA LEDs SATA LEDs Audio NAND flash GbE TDM TWSI Audio TS UART TDM SPI TS PTP PTP SDIO

Table 26 lists the functionality of the MPP pins, as determined by the MPP Multiplex register, see the

Pins Multiplexing Interface Registers section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

Page 53

Pin Multiplexing

Pin nam e 0x0 0x1 0x 2 0x3 0x4 0x5 0xC 0xD

MPP[0]

GPIO[0]

(in/out)

NF_IO[2]

(in/out)

SPI_SCn

(out)

-----

MPP[1]

only)

NF_IO[3]

(in/out)

SPI_MOSI

(out)

-----

MPP[2]

only)

NF_IO[4]

(in/out)

SPI_SCK

(out)

-----

MPP[3]

only)

NF_IO[5]

(in/out)

SPI_MISO

(in)

-----

MPP[4]

GPIO[4]

(in/out)

NF_IO[6]

(in/out)

UA0_RX D

(in)

SATA1_AC

Tn (out)

PTP_CLK

(in)

MPP[5]

only)

NF_IO[7]

(in/out)

UA0_TXD

(out)

PTP_TRIG_

GEN (out)

SATA0_AC

Tn (out)

MPP[6] -

SYSRST_O

UTn (out)

SPI_MOSI

(out)

PTP_TRIG_

GEN (out)

----

MPP[7]

only)

PEX_RST_ OUTn (out)

SPI_SCn

(out)

PTP_TRIG_

GEN (out)

----

MPP[8]

GPIO[8]

(in/out)

TW_SDA

(in/out)

UA0_RTS

(out)

UA1_RTS

(out)

MII0_RXER

R (in)

SATA1_PR

ESE NTn

(out)

PTP_CLK

(in)

MII0_COL

(in)

MPP[9]

GPIO[9]

(in/out)

TW_SCK

(in/out)

UA0_CTS

(in)

UA1_CTS

(in)

SATA0_PR

ESE NTn

(out)

PTP_EVEN

T_R EQ (in )

MII0_CRS

(in)

MPP[10]

GPO [10] (out only)

SPI_SCK

(out)

UA0_TXD

(out)

SATA1_AC

Tn (out)

PTP_TRIG_

GEN (out)

MPP[11]

GPIO[11]

(in/out)

SPI_MISO

(in)

UA0_RX D

(in)

PTP_EVEN

T_R EQ (in )

SATA0_AC

Tn (out)

PTP_TRIG_

GEN (out)

PTP_clk

(in)

MPP[12]

GPO[12]

(out only)

SD_CLK

(out)

------

MPP[13]

GPIO[13]

(in/out)

SD_CMD

(in/out)

UA1_TXD

(out)

----

MPP[14]

GPIO[14]

(in/out)

SD_D[0]

(in/out)

UA1_RX D

(in)

SATA1_PR

ESE NTn

(out)

MII0_COL

(in)

PP[15

]

GPIO[15]

(in/out)

SD_D[1]

(in/out)

UA0_RTS

(out)

UA1_TXD

(out)

SATA0_AC

Tn (out)

---

MPP[16]

GPIO[16]

(in/out)

SD_D[2]

(in/out)

UA0_CTS

(in)

UA1_RX D

(in)

SATA1_AC

Tn (out)

MII0_CRS

(in)

MPP[17]

GPIO[17]

(in/out)

SD_D[3]

(in/out)

SATA0_PR

ESE NTn

(out)

---

Multi-Purpose Pins Functional Summary

Table 26: MPP Function Summary

GPO[ 1] (out

GPO[ 2] (out

GPO[ 3] (out

GPO[ 5] (out

GPO[ 7] (out

Page 54

MPP[18]

GPO[18]

(out only)

NF_IO[0]

(in/out)

------

MPP[19]

GPO[19]

(out only)

NF_IO[1]

(in/out)

------

MPP[20]

GPIO[20]

(in/out)

TSMP[0]

(in/out)

TDM_CH0_ TX_QL (out )

GE1[0]

AU_SPDIFI

(in)

SATA1_AC

Tn (out)

MPP[21]

GPIO[21]

(in/out)

TSMP[1]

(in/out)

TDM_CH0_

RX_QL (out)

GE1[1]

AU_SPDIF

O (out)

SATA0_AC

Tn (out)

MPP[22]

GPIO[22]

(in/out)

TSMP[2]

(in/out)

TDM_CH2_

TX_QL (out )

GE1[2]

AU_SPDIF

RMCLK(out

)

SATA1_PR

ESENTn

(out)

MPP[23]

GPIO[23]

(in/out)

TSMP[3]

(in/out)

TDM_CH2_

RX_QL (out)

GE1[3]

AU_I2SBCL

K (out)

SATA0_PR

ESENTn

(out)

MPP[24]

GPIO[24]

(in/out)

TSMP[4]

(in/out)

TDM_SPI_

CS0 (out)

GE1[4]

AU_I2SDO

(out)

---

MPP[25]

GPIO[25]

(in/out)

TSMP[5]

(in/out)

TDM_SPI_

SCK (out)

GE1[5]

AU_I2SLRC

LK (out)

---

MPP[26]

GPIO[26]

(in/out)

TSMP[6]

(in/out)

TDM_SPI_

MISO (in)

GE1[6]

AU_I2SMC

LK (out)

---

MPP[27]

GPIO[27]

(

in/

out)

TSMP[7]

(in/out)

TDM_SPI_

MOSI (out )

GE1[7]

AU_I2SDI

(in)

---

MPP[28]

GPIO[28]

(in/out)

TSMP[8]

(in/out)

TDM_COD

EC_INTn

(in)

GE1[8]

AU_EXTCL

K (in)

---

MPP[29]

GPIO[29]

(in/out)

TSMP[9]

(in/out)

TDM_COD

EC_RSTn

(out)

GE1[9]----

MPP[30]

GPIO[30]

(in/out)

TSMP[10]

(in/out)

GE1[10]----

MPP[31]

GPIO[31]

(in/out)

TSMP[11]

(in/out)

TDM_FS

(in/out)

GE1[11]----

MPP[32]

GPIO[32]

(in/out)

TSMP[12]

(in/out)

TDM_DRX

(in)

GE1[12]----

MPP[33]

GPO[33]

(out only)

TDM_DTX

(out)

GE1[13]----

MPP[34]

GPIO[34]

(in/out)

TDM_SPI_

CS1 (out)

GE1[14] -

SATA1_AC

Tn (out)

MPP[35]

GPIO[35]

(in/out)

TDM_CH0_

TX_QL (out )

GE1[15] -

SATA0_AC

Tn (out)

MII0_RXER

R (in)

Pin nam e 0x0 0x1 0x 2 0x 3 0x 4 0x 5 0xC 0xD

88F6281 Hardware Specifications

Table 26: MPP Function Summary (Continued)

TDM_PCLK

Page 55

Pin Multiplexing

MPP[36]

GPIO[36]

(in/out)

TSMP[0]

(in/out)

TDM_SPI_

CS1 (out)

(in)

---

MPP[37]

GPIO[37]

(in/out)

TSMP[1]

(in/out)

TDM_CH2_

TX_QL (out )

AU_SPDIF

O (out)

---

MPP[38]

GPIO[38]

(in/out)

TSMP[2]

(in/out)

TDM_CH2_

RX_QL (out)

AU_SPDIF

RMCLK

(out)

---

MPP[39]

GPIO[39]

(in/out)

TSMP[3]

(in/out)

TDM_SPI_

CS0 (out)

AU_I2SBCL

K (out)

---

MPP[40]

GPIO[40]

(in/out)

TSMP[4]

(in/out)

TDM_SPI_

SCK (out)

AU_I2SDO

(out)

---

MPP[41]

GPIO[41]

(in/out)

TSMP[5]

(in/out)

TDM_SPI_

MISO (in)

AU_I2SLRC

LK (out)

---

MPP[42]

GPIO[42]

(in/out)

TSMP[6]

(in/out)

TDM_SPI_

MOSI (out )

AU_I2SMC

LK (out)

---

MPP[43]

GPIO[43]

(in/out)

TSMP[7]

(in/out)

TDM_COD

EC_INTn

(in)

AU_I2SDI

(in)

---

MPP[44]

GPIO[44]

(in/out)

TSMP[8]

(in/out)

TDM_COD

EC_RSTn

(out)

AU_EXTCL

K (in)

---

MPP[45]

GPIO[45]

(in/out)

TSMP[9]

(in/out)

-----

MPP[46]

GPIO[46]

(in/out)

TSMP[10]

(in/out)

TDM_FS

(in/out)

-----

MPP[47]

GPIO[47]

(in/out)

TSMP[11]

(in/out)

TDM_DRX

(in)

-----

MPP[48]

GPIO[48]

(in/out)

TSMP[12]

(in/out)

TDM_DTX

(out)

-----

MPP[49]

GPIO[49]

(in/out)

TDM_CH0_

RX_QL (out)

PTP_CLK

(in)

Pin nam e 0x0 0x1 0x 2 0x 3 0x 4 0x 5 0xC 0xD

Multi-Purpose Pins Functional Summary

Table 26: MPP Function Summary (Continued)

AU_SPDIFI

TDM_PCLK

Page 56

Note

88F6281 Hardware Specifications

 For MPPs assigned as NAND flash and SPI flash, wake-up mode after reset

depends on Boot mode (see the Boot Device field in Table 32, Reset

Configuration, on page 67):

• When Boot mode is NAND Flash, MPP[5:0] and MPP[19:18] wake up after reset

in NAND Flash mode.

• When Boot mode is SPI Flash, either MPP[3:0] or {MPP[3:1] and MPP[7]} wake

up after reset in SPI mode, (according to boot mode configured by reset strap pins).

 Pin MPP[6] wakes up after reset in 0x1 mode (SYSRST_OUTn)  Pin MPP[7] wakes up after reset:

• As SPI_CSn, if the boot device—selected according to boot device reset

strapping—is 0x2 (boot from SPI flash, SPI_CSn on MPP[7]).

• As PEX_RST_OUTn, if the boot device—selected according to boot device

reset strapping—is any option other than 0x2.

 When TWSI serial ROM initialization is enabled (see TWSI Serial ROM

Initialization in Table 32, Reset Configuration, on page 67), MPP[8] and MPP[9]

wake up as TWSI data and clock pins, respectively.

 All other MPP interface pins wake up after reset in 0x0 mode (GPIO/GPO) and are

default set to Data Output disabled (Tri-State). Therefore, those MPPs that are GPIO are in fact inputs, and those that are GPO are Tri-State.

 The SPI interface can be configured using one of the following sets of MPP pins:

• MPP[3:0]

• MPP[11], MPP[10], MPP[7], and MPP[6]

• MPP[3:1] and MPP[7]

 Do not configure both MPP[3] and MPP[11] as SPI_MISO.  UART0 and UART1 signals are duplicated on a few MPPs. The UART0 or UART1

signals must not be configured to more than one MPP.

 When selecting the MII/MMII interface (MPP[35:20]) and the TDM interface

(MPP[49:35]), the TDM signal TDM_CH0_TX_QL and the MII/MMII signal MII1_RXERR are both multiplexed on MPP[35]. However, MPP[35] can only be configured to one of these functions at a time.

 Some of the MPP pins are sampled during SYSRSTn de-assertion to set the

device configuration. These pins must be set to the correct value during reset (see

Section 6.5, Pins Sample Configuration, on page 66).

 Pins that are left as GPIO and are not connected should be set to output after

SYSRSTn de-assertion.

Page 57

Pin Multiplexing

Gigabit Ethernet (GbE) Pins Multiplexing on MPP

4.2 Gigabit Ethernet (GbE) Pins Multiplexing on MPP

The 88F6281 has 14 dedicated pins for its GbE port. (12 RGMII pins, an MDC pin, and an MDIO pin).

For the 88F6281, additional GbE interface pins are multiplexed on the MPPs, to serve as the following interfaces to an external PHY or switch.

 Two RGMII ports  One RGMII port and one MMII/MII port

(either port 0 as RGMII and port 1 as MMII/MII or port 0 as MMII/MII and port 1 as RGMII)

 One GMII port (port 0)

Table 27 summarizes the GbE port pins multiplexing.

Table 27: Ethernet Ports Pins Multiplexing

Pin Name 1xGMII RGMII0 +MII1/

MMII1

GE_TXCLKOUT GMII0_TXCLKOUT

(out)

GE_TXD[3:0] GMII0_TXD[3:0] (out) RGMII0_TXD[3:0]

GE_TXCTL GMII0_TXEN (out) RGMII0_TXCTL (out) RGMII0_TXCTL (out) MII0_TXEN (out) GE_RXD[3:0] GMII0_R XD [3 :0 ] (in ) RGMII0_RXD[3:0] (in) RGMII0_R X D[3 :0 ] (in ) MII0_RXD[3:0] (in) GE_RXCTL GMII0_RXDV (in) RGMII0_RXCTL (in) RGMII0_RXCTL (in) MII0_RXDV (in) GE_RXCLK GMII0_RXCLK (in) RGMII0_RXCLK (in) RGMII0_RXCLK (in) MII0_RXCLK (in) MPP[8] or

MPP[35] MPP[8] or

MPP[14] MPP[9] or

MPP[16] MPP [23:20] /

GE1[3:0] MPP_[27:24] /

GE1[7:4] MPP_28 /

GE1[8] MPP_29 /

GE1[9] MPP_30 /

GE1[10] MPP_31 /

GE1[11] MPP_32 /

GE1[12] MPP_33 /

GE1[13]

NA NA NA MII0_RXERR (in)

NA NA NA MII0_COL (in)

NA NA NA MII0_CRS (in)

GMII0_TXD[7:4] (out) MII1_TXD[3:0] (out) RGMII1_TXD[3:0]

GMII0_RXD[7:4] (in) MII1_RXD[3:0] (in) RGMII1 _ RX D [3 :0] (in ) RGMII1_RXD[3:0] (in)

GMII0_COL (in) MII1_COL (in) NA NA

GMII0_TXCLK (in) MII1_TXCLK (in) NA NA

GMII0_RXERR (in) MII1_RXDV (in) RGMII1_RXCTL (in) RGMII1_RXCTL (in)

NA MII1_RXCLK (in) RGMII1_RXCLK (in) RGMII1_RXCLK (in)

GMII0_CRS (in) MII1_CRS (in) RGMII1_TXCLKOUT

GMII0_TXERR (out) MII1_TXERR (out) RGMII1_TXCTL (out) RGMII1_TXCTL (out)

RGMII0_TXCLKOUT (out)

(out)

2xRGMII MII0/MMII0+

RGMII1

RGMII0_TXCLKOUT (out)

RGMII0_TXD[3:0] (out)

(out)

MII0_TXCLK (in)

MII0_TXD[3:0] (out)

RGMII1_TXD[3:0] (out)

RGMII1_TXCLKOUT (out)

Page 58

Note

88F6281 Hardware Specifications

Table 27: Ethernet Ports Pins Multiplexing (Continued)

Pin Name 1xGMII RGMII0 +MII1/

MMII1

MPP_34 /

NA MII1_TXEN (out) NA NA

GE1[14] MPP_35 /

NA MII1_RXERR (in) NA NA

GE1[15]

When using Gigabit Ethernet signals on MPPs, all relevant Gigabit Ethernet signals (except those marked as NA) must be implemented. For example, if using MII, and the chosen PHY does not have an MII_RXERR out signal, the MII_RX_ERR (in) (MPP[35]) must still be configured accordingly and must have a pull-down resistor.

2xRGMII MII0/MMII0+

RGMII1

Page 59

TSMP (TS Multiplexing Pins) on MPP

4.3 TSMP (TS Multiplexing Pins) on MPP

The TS interface can be configured to one of five modes:

 One or two serial in interfaces  One or two serial out interfaces  Serial in and serial out interface  Parallel in interface  Parallel out interface

In parallel in or serial in mode, all TS signals are inputs. In parallel out or serial out mode, all TS signals are outputs. Table 28 summarizes the TS port pins multiplexing.

Table 28: TS Port Pin Multiplexing

Pin Multiplexing

Pin Name

TSMP[0] EXT_CLK (in) EXT_CLK (in) TSMP[1] TS0_CLK (in/out)) TS0_CLK (in/out)) TSMP[2] TS0_SYNC(in/out)) TS0_SYNC(in/out)) TSMP[3] TS0_VAL (in/out)) TS0_VAL (in/out)) TSMP[4] TS0 _E RR (in/out)) TS0_ERR (in/out)) TSMP[5] TS0_DATA[0] (in/out) TS0_DATA[0] (in/out) TSMP[6] TS1_CLK (in/out)) TS0_DATA[1] (in/out)) TSMP[7] TS1_SYNC(in/out)) TS0_DATA[2] (in/out)) TSMP[8] TS1_VAL (in/out)) TS0_DATA[3] (in/out)) TSMP[9] TS1_ERR (in/out)) TS0_DATA[4] (in/out)) TSMP[10] TS1_DATA[0] (in/out) TS0_DATA[5] (in/out)) TSMP[11] NA TS0_DATA[6] (in/out)) TSMP[12] NA TS0_DATA[7] (in/out))

Functionality in TS serial modes 2x in/2x out/in+out

Functionality in TS parallel in/out mode

Page 60

88F6281 Hardware Specifications

5 Clocking

Table 29 lists the clocks in the 88F6281.

Table 29: 88F6281Clocks

Clock Type Description

CPU PLL

Core PLL

• Reference clock: REF_CLK_XIN (25 MHz)

• Derivative clocks:

- CPU clock

- L2 cache clock

- DDR Clock (the Mbus-L uses the DDR clock.)

NOTE: See Table 32, Reset Configuration, on page 67 for CPU, L2 cache and

DDR frequency configuration.

L2 cache clock frequency must be equal or higher then DDR clock frequency.

If the SSCG enable bit in the Sampled at Reset register is set, then the SSCG circuit is applied for the CPU PLL reference clock (refer to the Sampled at Reset register in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications).

• Reference clock: REF_CLK_XIN (25 MHz)

• Derivative clocks:

- TCLK (core clock, 200 MHz)

- SDIO Clock (100 MHz)

- Gigabit Ethernet Clock (125 MHz)

- TS unit Clock(100/91/83/77MHz)

- SPI clock (TCLK/30–TCLK/4 MHz)

- SMI clock (TCLK/128 MHz)

- TWSI clock (up to TCLK/1600)

NOTE: See Table 32, Reset Configuration, on page 67 for TCLK frequency

configuration.

NOTE: See the TS Interface Configuration re gister in the 88F6180, 88F6190,

88F6192, and 88F6281 Functional Specifications for TS clock frequency

configuration.

PEX PHY

USB PHY PLL

There are two options for the ref erence c lock configur a tion, depending on the PCI Express clock 100 MHz differential clock:

• The device uses an external source for PCI Express clock. The PEX_CLK_P pin is an input.

• The device uses an internal generated clock for PCI Express clock. The PEX_CLK_P pin is an output, driving out the PCI Express differential clock.

• Reference clock: REF_CLK_XIN (25 MHz)

Page 61

Table 29: 88F6281Clocks (Continued)

Clock Type Description

Clocking

SATA PHY PLL

RTC

PTP

• Reference clock: REF_CLK_XIN (25 MHz)

• Derivative clock: SATA Clock (150 MHz)

• Reference clock: RTC_XIN (32.768 kHz)

Used for real time clock functionality, see the Real Time Clock section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

• Reference clock: PTP_CLK (125 MHz)

The PTP_CLK can be used for the following functions:

• PTP time stamp clock Two options for reference clock:

- PTP_CLK

- Gigabit Ethernet Clock (125 MHz)

• TS unit clock Two options for reference clock:

- PTP_CLK/2

- Core PLL

• Audio unit clock Two options for reference clock:

- PTP_CLK

- REF_CLK_XIN (25 MHz)

For clocking configuration registers, see the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

The following table lists the supported combinations of the CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio, and to CPU_CLK to CPU L2 clock ratio (see Section 6.5, Pins Sample

Configuration, on page 66).

Table 30: Supported Clock Combinations

DDR Clock (MHz)

333 250 200

400 300 267 200

375 4:1 1500 3:1 500

CPU to DDR Clock Ratio

3:1 4:1 5:1

3:1 4:1

4.5:1 6:1

CPU Clock (MHz)

CPU to L2 Clock Ratio

1000 3:1 333

1200 3:1 400

L2 Clock (MHz)

Page 62

88F6281 Hardware Specifications

5.1 Spread Spectrum Clock Generator (SSCG)

The SSCG (Spread S pectrum Clock Generator) may be used to generate the spread spectrum clock for the PLL input. See SSCG Disable in Table 32, Reset Configuration, on page 67, for SSCG enable/bypass configuration settings.

The SSCG block can be configured to perform up spread, down spread and center spread. The modulation frequency is configurable. Typical frequency is 30 kHz. The spread percentage can also be configured up to 1%. For additional details, see the SSCG Configuration Register description in the 88F6180, 88F6190,

88F6192, and 88F6281 Functional Specifications.

Page 63

System Power Up/Down and Reset Settings

Power-Up/Down Sequence Requirements

6 System Power Up/Down and Reset

Settings

This section provides information about the device power-up/down sequence and configuration at reset.

6.1 Power-Up/Down Sequence Requirements

6.1.1 Power-Up Sequence Requirements

These guidelines must be applied to meet the 88F6281 device power-up requirements:

 The non-core voltages (I/O and Analog) as listed in Table 31 must reach 70% of their voltage

level before the core voltages reach 70% of their voltage level. The order of the power-up sequence between the non-core voltages is unimportant so long as the non-core voltages power up before the core voltages reach 70% of their voltage level (shown in Figure 2). The order of the power-up sequence between the core voltages (VDD and VDD_CPU) is unimportant.

 The reset signal(s) must be asserted before the core voltages reach 70% of their voltage level

(shown in Figure 2).

 The reference clock(s) inputs must toggle with their respective voltage levels before the core

voltages reach 70% of their voltage level (shown in Figure 2).

 If VHV is set to burning mode (2.5V), which is a higher voltage than the VDD voltage, VDD must

be powered before VHV, to prevent the fuse from being accidentally burned.

Table 31: I/O and Core Voltages

Non-Core Voltages Core Voltages

I/O Voltages Analog Power Supplies

VDD_GE_A VDD_GE_B VDD_M VDDO

CPU_PLL_AVDD CORE_PLL_AVDD PEX_AVDD RTC_AVDD SATA0_AVDD SATA1_AVDD SSCG_AVDD XTAL_AVDD USB_AVDD

VDD VDD_CPU

Page 64

Note

70% of Core

Voltage

70% of

Non-Core

Voltage

Reset(s)

Clock(s)

Non-Core Voltage

Core Voltage

88F6281 Hardware Specifications

Figure 2: Power-Up Sequence Example

 It is the designer's responsibility to verify that the power sequencing requirements

of other components are also met.

 Although the non-core voltages can be powered up any time before the core

voltages, allow a reasonable time limitation (for example, 100 ms) between the

first non-core voltage power-up and the last core voltage power-up.

6.1.2 Power-Down Sequence Requirements

There are no special requirements for the core supply to go down before non-core power, or for reset assertion when powering down (except for VHV, as described below). However, allow a reasonable time limitation (no more than 100 ms) between the first and last voltage power-down.

When using the eFuse in Burning mode, VHV must be po wered down before VDD.

6.2 Hardware Reset

The device has one reset input pin—SYSRSTn. When asserted, the entire chip is placed in its initial state. Most outputs are placed in high-z, except for the following output pins, that are still active during SYSRSTn assertion:

 M_CLKOUT, M_CLKOUTn  M_CKE  M_ODT[1:0]  M_STARTBURST  SYSRST_OUTn

Page 65

Note

Reset (SYSRSTn signal) must be active for a minimum length of 5 ms. core power, I/O power, and analog power must be stable (VDD +/- 5%) during that time and onward.

6.2.1 Reset Out Signal

The device has an optional SYSRST_OUTn output signal, multiplexed on an MPP pin, that is used as a reset request from the device to the board reset logic. SYSRST_OUTn is the default option for that MPP pin.

This signal is asserted low for 20 ms, when one of the following maskable events occurs:

 Received hot reset indication from the PCI Express link (only relevant when used as a PCI

Express endpoint), and bit <PexRstOutEn> is set to 1 in the RSTOUTn Mask Register (see the Reset register section of the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications).

 PCI Express link failure (only relevant when used as a PCI Express endpoint), and bit

<PexRstOutEn> is set to 1 in the RSTOUTn Mask Register.

 Watchdog timer expiration and bit <WDRstOutEn> is set to 1 in the RSTOUTn Mask Register.  Bit <SystemSoftRst> is set to 1 in System Soft Reset Register and bit <SoftRstOutEn> is set

to 1 in RSTOUTn Mask Register.

This signal is asserted low for 20 ms, when one of the following non-maskable events occurs:

 Power on reset (The device includes a power-on-reset (POR) circuit for VDD power.)  SYSRST_OUTn is asserted low as long as the MRn input signal is asserted low and for an

additional 20 ms after MRn de-assertion. (This is useful for implementations that include a manual reset button.)

System Power Up/Down and Reset Settings

Hardware Reset

6.2.2 Power On Reset (POR)

The SYSRST_OUTn output signal is asserted low for 20 ms, when the power-on-reset (POR) circuit is triggered.

POR is triggered when VDD power up (digital core voltage) reaches a VDD threshold (threshold maximum value 0.8V).

Hysteresis: Another trigger will only occur after the power first drops to 50 mV, and then a power up occurs.

6.2.3 SYSRSTn Duration Counter

When SYSRSTn is asserted low, a SYSRSTn duration counter is running.

 The counter clock is the 25 MHz reference clock.  It is a 29-bit counter, yielding a maximum counting duration of 2^29/25 MHz (21.4 seconds).  The host software can read the counter value and reset the counter.  When the counter reach its maximum value, it remains at this value until counter reset is

triggered by software.

The SYSRSTn duration counter is useful for implementing manufacturer/factory reset. Upon a long reset assertion, greater than a pre-configured threshold, the host software may reset all settings to the factory default values.

Page 66

88F6281 Hardware Specifications

6.3 PCI Express Reset

6.3.1 PCI Express Root Complex Reset

As a Root Complex, the device may generate a Hot Reset to the PCI Express port. Upon CPU setting the PCI Express Control register’s <conf_mstr_hot_reset> bit, the PCI Express unit sends a Hot Reset indication to the Endpoint, see the PCI Express Interface section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

6.3.2 PCI Express Endpoint Reset

When a Hot Reset packet is received:

 A maskable interrupt is asserted.  If the <conf_dis_hot_rst_reg_rst> field in the PCI Express Debug Control register is cleared, the

device also resets the PCI Express regist er fi l e to its default values.

 The device triggers an internal reset, if not masked by the <conf_msk_hot_reset> field in the

PCI Express Debug Control register.

Link failure is detected if the PCI Express link was up (LTTSSM L0 state) and dropped back to an inactive state (LTSSM Detect state). When Link failure is detected:

 A maskable interrupt is asserted.  If the <conf_dis_link_fail_reg_rst> field in the PCI Express Debug Control register is cleared,

the device also resets the PCI Express register file to its default values.

 The device triggers an internal reset, if the <conf_msk_link_fail> field is not masked by PCI

Express Debug Control register.

Both link fail and hot reset conditions trigger a chip internal reset (if not masked in the PCI Express interface). All the chip logic is reset to the default values, except for sticky registers and the sample on reset logic. In addition, these events can trigger reset to the board, using one of the following:

 PEX_RST_OUTn signal (multiplexed on MPP).  SYSRST_OUTn output (multiplexed on MPP)—if not masked by the <PexRstOutEn> bit.

The external reset logic (on the board) may assert the SYSRSTn input pin and reset the entire chip.

6.4 Sheeva™ CPU TAP Controller Reset

The Sheeva™ CPU Test Access Port (TAP) controller is reset when JT_RSTn is set and JT_TMS_CPU is active.

6.5 Pins Sample Configuration

The following pins are sampled during SYSRSTn de-assertion:

 Internal pull up/down resistors set the default mode (see Section 1.3, Internal Pull-up and

Pull-down Pins, on page 48).

 Higher value, external pull up/down resistors are required to change the default mode of

operation.

These signals must remain pulled up or down until SYSRSTn de-assertion (zero hold time in respect to SYSRSTn de-assertion).

Page 67

Note

 If external logic is used instead of pull-up and pull-down resistors, the logic must

drive all of these signals to the desired values during SYSRSTn assertion. To prevent bus contention on these pins, the external logic must float the bus no later than the third TCLK cycle after SYSRSTn de-assertion.

 All reset sampled values are registered in the Sample at Reset register (see the

MPP Registers in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications). This is useful for board debug purposes and identification of board

and system settings for the host software.

 If a signal is pulled up on the board, it must be pulled to the proper voltage level.

Certain reset configuration pins are powered by VDD_GE_A and VDD_GE_B. Those pins have multiple voltage options (see Table 36, Recommended Operating

Conditions, on page 77).

In each row of Table 32, the order of the pins is from MSb to LSb (e.g., for in the row CPU_CLK Frequency Select, MPP[2] is the MSB and MPP[10] is the LSB).

Table 32: Reset Configuration

Pin Configuration Function

System Power Up/Down and Reset Settings

Pins Sample Configuration

MPP[1] TWSI Serial ROM Initialization

0 = Disabled 1 = Enabled NOTE: Internally pulled down to 0x0.

When this pin is set to 0x1, MPP[8] and MPP[9] wake up as TWSI data and clock pins, respectively (see Section 4.1, Multi-Purpose Pins Functional Summary, on page 51).

MPP[2],MPP[5],

CPU_CLK Frequency Select MPP[19], MPP[10]

0x0–0x6 = Reserved

0x7 = 1000 MHz

0x8 = Reserved

0x9 = 1200 MHz

0xA–0xB = Reserved

0xC = 1500 MHz

0xD–0xF = Reserved

NOTE: Internally pulled to 0x6.

The supported combination for CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio, and CPU_CLK to CPU L2 clock ratio are listed in Table 30, Supported Clock Combinations,

on page 61.

Page 68

88F6281 Hardware Specifications

Table 32: Reset Configuration (Continued)

Pin Configuration Function

MPP[33], NF_ALE, NF_REn, NF_CLE

MPP[3], MPP[12], NF_WEn

CPU_CLK to DDR CLK Ratio

0x0–0x3 = Reserved

0x4 = 3:1

0x5 = Reserved

0x6 = 4:1

0x7 = 4.5:1

0x8 = 5:1

0x9 = 6:1

0xA–0xF = Reserved

NOTE: Internally pulled to 0x4.

The supported combination for CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio, and CPU_CLK to CPU L2 clock ratio are listed in Table 30, Supported Clock Combinations,

on page 61.

CPU_CLK to CPU L2 Clock Ratio 0x0 = Reserved

0x1 = 2:1 0x2 = Reserved 0x3 = 3:1 0x4–0x7 = Reserved NOTE: Internally pulled to 0x1.

The supported combination for CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio,

and CPU_CLK to CPU L2 clock ratio are listed in Table 30, Supported Clock Combinations,

on page 61.

Page 69

Table 32: Reset Configuration (Continued)

Pin Configuration Function

GE_TXD[2:0] Boot Device

0x0 = Reserved 0x1 = Reserved 0x2 = Boot from SPI flash (SPI_CSn on MPP[7]) 0x3 = Reserved 0x4 = Boot from SPI flash (SPI_CSn on MPP[0]) 0x5 = Boot from NAND flash 0x6 = Boot from SATA 0x7 = Boot from the PCI Express port

NOTE:

• Internally pulled to 0x4.

• Only SPI signals configured on pins MPP[3:0] or on pins MPP[7] and MPP[3:1] can be used for booting from SPI. SPI signals that are multiplexed on other MPPs can only be used after booting (see Section 4.1,

Multi-Purpose Pins Functional Summary, on page 51).

• When GE_TXD[2:0] is set to 0x4, MPP[3:0] wake up as SPI signals.

• When GE_TXD[2:0] is set to 0x2, MPP[7] and MPP[3:1] wake up as SPI signals.

• When GE_TXD[2:0] is set to 0x5, MPP[5:0] and MPP[19:18] wake up as NAND Flash signals.

• For a more detailed descripti on of the bootROM, see the BootROM section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

• For a more detailed description of the boot from SPI flash or NAND flash, see the SPI Interface and NAND Flash Interface sections in the 88F6180, 88F6190, 88F6192, a nd 88F6281 Functional Specifications.

• There is an option to boot from UART when GE_ TXD[2:0] = 0x2–0x7. For a more detailed description of the boot from UART, see the BootROM section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

System Power Up/Down and Reset Settings

Pins Sample Configuration

GE_TXD[3] SSCG Disable

0 = Enable 1 = Disable NOTE: Internally pulled to 0x1.

GE_MDC PCI Express Clock (100 MHz Differential Clock) Configuration

0x0 = The device use external source for PCI Express clock. Pins PEX_CLK_P/PEX_CLK_N are

inputs.

0x1 = The device uses internal generated clock for PCI Express clock. Pins

PEX_CLK_P/PEX_CLK_N pins are outputs, driving out the PCI Express differential clock.

NOTE: Internally pulled to 0x1.

GE_TXCTL Used for internal testing

Must be 0x0 during reset. Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset.

MPP[7] Reserved

Must be 0x1 during reset. Either leave th e signal float ing (internally pulled up to 0x1) or pull t he signal to 0x1 during reset.

Page 70

Start

address0[31:24] address0[23:16]

address0[15:8]

address0[7:0]

data0[31:24] data0[23:16]

data0[15:8]

data0[7:0] address1[31:24] address1[23:16]

address1[15:8]

address1[7:0]

data1[31:24] data1[23:16]

data1[15:8]

data1[7:0]

MSB LSB

88F6281 Hardware Specifications

Table 32: Reset Configuration (Continued)

Pin Configuration Function

MPP[18] Reserved

NOTE: MUST be externally pulled down to 0x0 during reset.

6.6 Serial ROM Initialization

The device supports initialization of ALL of its internal and configuration registers through the TWSI master interface. If serial ROM initializa ti o n is e nabled, the device TWSI master starts reading initialization data from serial ROM and writes it to the appropriate registers, upon de-assertion of SYSRSTn.

When using Serial ROM Initialization, the MPP[9:8] pins must be configured to as TW_SCK (MPP[9]) and TW_SDA (MPP[8]).

6.6.1 Serial ROM Data Structure

Serial ROM data structure consists of a sequence of 32-bit address and 32-bit data pairs, as shown in Figure 3.

Figure 3: Serial ROM Data Structure

Page 71

System Power Up/Down and Reset Settings

0 00 00 1s 1 0 0 00 00 00 0

x xx xx xx x p

Lower Byte Offset

Last Data

from ROM

a c k

n a c k

r t

ROM

Address

t o p

w r i t e

0 00 00 1s 1 1

s t a r t

ROM

Address

r e a d

A AA AA AA A

c k

a c k

A AA A

Data from

ROM

1 11 11 11 1

a c k

1 11 11 11 1

a c k

1 11 11 11 1

c k

1 11 11 11 1

a c k

0 00 00 00 0

Upper Byte Offset

a c k

The serial ROM initialization logic reads eight bytes at a time. It performs address decoding on the 32-bit address being read, and based on address decoding result, writes the next four bytes to the required target.

The Serial Initialization Last Data Register contains the expected value of last serial data item (default value is 0xFFFFFFFF). When the device reaches last data, it stops the initialization sequence.

6.6.2 Serial ROM Initialization Operation

On SYSRSTn de-assertion, the device starts the initialization process. It first performs a dummy write access to the serial ROM, with data byte(s) of 0x0, to set the ROM byte offset to 0x0. Then, it performs the sequence of reads, until it reaches last data item, as shown in Figure 4.

Figure 4: Serial ROM Read Example

Boot Sequence

For a detailed description of TWSI implementation, see the Two-Wire Serial Interface section in the

88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

 Initialization data must be programmed in the serial ROM starting at offset 0x0.  The device assumes 7-bit serial ROM address of ‘b1010000.  After receiving the last data identifier (default value is 0xFFFFFFFF), the device receives an

additional byte of dummy data. It responds with no-ack and then asserts the stop bit.

 The serial EEPROM must contain two address offset bytes (It must not be less than a 256 byte

ROM.).

6.7 Boot Sequence

The device requires that SYSRSTn stay asserted for at least 300 μs after power and clocks are stable. The following procedure describes the boot sequence starting with the reset assertion:

1. While SYSRSTn is asserted, the CPU PLL and the core PLL are locked.

2. Upon SYSRSTn de-assertion, the pad drive auto-calibration process starts. It takes 512 TCLK cycles.

3. If Serial ROM initialization is enabled, an initialization sequence is started.

4. If configured to boot from NAND flash (and BootROM is disabled), the device also performs a NAND Flash boot sequence to prepare page 0 in the NAND fl ash device for read.

Page 72

88F6281 Hardware Specifications

Upon completing the above sequence, the internal CPU reset is de-asserted, and the CPU starts executing boot code from the boot device (SPI flash, NAND flash, or internal Boot ROM), according to sample at reset setting, see Table 32, Reset Configuration, on page 67.

For bootROM details, see the BootROM section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

As part of the CPU boot code, the CPU typically performs the following:

 Configures the PCI Express address map.  Configures the proper SDRAM controller parameters, and then triggers SDRAM initialization

(sets <InitEn> bit [0] to 1 in the SDRAM Initialization Control register).

 Sets the <PEXEn> bits in the CPU Control and Status register to wake up the PCI Express link.

Page 73

7 JTAG Interface

To enable board testing, the device supports a test mode operation through its JTAG boundary scan interface.

The JTAG interface is IEEE 1149.1 standard compliant. It supports mandatory and optional boundary scan instructions.

7.1 TAP Controller

The Test Access Port (T AP) is constructed with a 5-pin interface and a 16-state Finite State Machine (FSM), as defined by IEEE JTAG standard 1149.1.

To place the device in a functional mode, reset the JTAG state machine to disable the JTAG interface.

According to the IEEE 1149.1 standard, the JTAG state machine is not reset when the 88F6281 SYSRSTn is asserted. The JTAG state machine can only be reset by one of the following methods:

 Asserting JT_RSTn.  Setting JT_TMS_CORE for at least five JT_CLK cycles.

To place the device in one of the boundary scan test mode, the JT AG state machine must be moved to its control states. JT_TMS_CORE and JT_TDI inputs control the state transitions of the JTAG state machine, as specified in the IEEE 1149.1 standard. The JTAG state machine will shift instructions into the Instruction register while in SHIFT-IR state and shift data into and from the various data registers when in SHIFT-DR state.

JTAG Interface

TA P Co ntroller

7.2 Instruction Register

The Instruction register (IR) is a 4-bit, two-stage register. It contains the command that is shifted in when the TAP FSM is in the Shift-IR state. When the TAP FSM is in the Capture-IR state, the IR outputs all four bits in parallel.

Table 33 lists the instructions supported by the device.

Table 33: Supported JTAG Instructions

Instruction Code Description

HIGHZ 0011 Select the single bit Bypass register between TDI and TDO.

Sets the device output pins to high-impedance state.

IDCODE 0010 Selects the Identification register between TDI and TDO. This 32-bit

EXTEST 0000 Selects the Boundary Scan register between TDI and TDO. Outputs the

boundary scan register cells to drive the output pins of the devi ce. Inputs the boundary scan register cell to sample the input pin of the device.

SAMPLE/PRE LOAD

BYPA SS 1111 Selects the single bit Bypass register between TDI and TDO. This allows

0001 Selects the Boundary Scan register between TDI and TDO. Samples

input pins of the device to input boundary scan register cells. Preloads the output boundary scan register ce lls with the Boundary Scan register value.

for rapid data movement through an untested device.

Page 74

88F6281 Hardware Specifications

7.3 Bypass Register

The Bypass register (BR) is a single bit serial shift register that connects TDI to TDO, when the IR holds the Bypass command, and the TAP FSM is in Shift-DR state. Data that is driven on the TDI input pin is shifted out one cycle later on the TDO output pin. The Bypass register is loaded with 0 when the TAP FSM is in the Capture-DR state.

7.4 JTAG Scan Chain

The JTAG Scan Chain is a serial shift register used to sample and drive all of the device pins during the JTAG tests. It is a 2-bit per pin shift register in th e de vi ce , th ere b y allo w i ng th e sh ift register to sequentially access all of the data pins both for driving and strobing data. For further details, refer to the BSDL Description file for the device.

7.5 ID Register

The ID register is a 32-bit deep serial shift register. The ID register is loaded with vendor and device information when the TAP FSM is in the Capture-DR state. The Identification code format of the ID register is shown in Table 34, which describes the various ID Code fields.

Table 34: IDCODE Register Map

Bits Va l ue Description

31:28 0x0 Version (4'b0010 for version A0, 4'b0011 for A1, etc.) 27:12 0x6281 Part number

11:1 0x1AB Manufacturer ID 0 1 Mandatory

Page 75

Electrical Specifications (Preliminary)

Note

Absolute Maximum Ratings

8 Electrical Specifications (Preliminary)

The numbers specified in this section are PRELIMINARY and SUBJECT TO CHANGE.

8.1 Absolute Maximum Ratings

Table 35: Absolute Maximum Ratings

Parameter Min Max Units Comments

VDD -0.5 1.2 V Core voltage VDD_CPU -0.5 1.32 V CPU interface CPU_PLL_AVDD

CORE_PLL_AVDD SSCG_AVDD -0.5 2.2 V Analog supply for:

VDD_GE_A VDD_GE_B

VDD_M -0.5 2.2 V I/O voltage for:

VDDO -0.5 4.0 V I/O voltage for:

VHV -0.5 3.0 V I/O voltage for eFuse burning PEX_AVDD -0.5 2.2 V Analog supply for:

USB_AVDD -0.5 4.0 V Analog supply for:

SATA0_AVDD SATA1_AVDD

-0.5 2.2 V Analog supply for the internal PLL

Internal Spread Spectrum Clock Generator

-0.5 4.0 V I/O voltage for: RGMII/GMII/MII/MMII/SMI in terfa c e

SDRAM interface

MPP, TWSI, JTAG, SDIO, I TDM interfaces

PCI Express interface

USB interface

-0.5 4.0 V Analog supply for: SATA interface

S, SPI, TS, and

XTAL_AVDD -0.5 2.2 V Analog supply for internal clock inverter for

crystal support and current source for SATA and USB PHYs

Page 76

Caution

88F6281 Hardware Specifications

Table 35: Absolute Maximum Ratings (Continued)

Parameter Min Max Units Comments

RTC_AVDD -0.5 2.2 V Analog supply for:

RTC interface

-40 125 ° C Case temperature

STG

-40 125 ° C Storage temperature

 Exposure to conditions at or beyond the maximum rating may damage the device.  Operation beyond the recommended operating conditions (Table 36) is neither

recommended nor guaranteed.

Page 77

Electrical Specifications (Preliminary)

Recommended Operating Conditions

8.2 Recommended Operating Conditions

Table 36: Recommended Operating Conditions

Parameter Min Ty p Max Units Comments

VDD 0.95 1.0 1.05 V Core voltage VDD_CPU 1.05 1.1 1.15 V CPU interface CPU_PLL_AVDD

1.7 1.8 1.9 V Analog supply for the internal PLL

CORE_PLL_AVDD SSCG_AVDD 1.7 1.8 1.9 V Analog supply for:

Internal Sp read Spectrum Clock Generator

VDD_GE_A VDD_GE_B

3.15 3.3 3.45 V I/O voltage for: RGMII(10/100 RGMII only)/ GMII/MII/MMII/SMI interfaces

1.7 1.8 1.9 V I/O voltage for: RGMII/SMI interfaces

VDD_M 1.7 1.8 1.9 V I/O voltage for:

SDRAM interface

VDDO 3.15 3.3 3.45 V I/O voltage for:

MPP, TWSI, JTAG, SDIO, I TS, and TDM interfaces

VHV (during eFuse Burning mode)

2.375 2.5 2.625 V I/O voltage for eFuse burning NOTE: If the VHV voltage is high er

than VDD voltage (burning mode), VDD must be powered before VHV, to prevent the fuse from being accidentally burned.

S, SPI,

VHV (during eFuse Reading mode)

0.95 1.0 1.05 V I/O voltage for eFuse reading NOTE: It is recommended that if

only a read operation is required, VHV would be connected to the device VDD power.

PEX_AVDD 1.7 1.8 1.9 V Analog supply for:

PCI Express interface

USB_AVDD 3.15 3.3 3.45 V Analog supply for:

USB interface

SATA0_AVDD SATA1_AVDD

3.15 3.3 3.45 V Analog supply for: SATA interface

Page 78

Caution

88F6281 Hardware Specifications

Table 36: Recommended Operating Conditions (Continued)

Parameter Min Ty p Max Units Comments

XTAL_AVDD 1.7 1.8 1.9 V Analog supply for:

Internal clock inverter for crystal support and current source for SATA and USB PHYs

RTC_AVDD 1.7 1.8 1.9 V Analog supply for RTC in Regular

mode

1.3 1.5 1.7 V Analog supply for RTC in Battery Back-up mode

TJ 0 105 ° C Junction Temperature

Operation beyond the recommended operating conditions is neither recommended nor guaranteed.

Page 79

Electrical Specifications (Preliminary)

Note

Thermal Power Dissipation

8.3 Thermal Power Dissipation

Before designing a system, Marvell recommends reading application note AN-63: Thermal Management for Marvell Technology Products. This application note presents

basic concepts of thermal management for integrated circuits (ICs) and includes guidelines to ensure optimal operating conditions for Marvell Technology's products.

The purpose of the Thermal Power Dissipation table is to support system engineering in thermal design.

Table 37: Thermal Power Dissipation

Interface Symbol Test Conditions Typ Units

Core (VDD 1.0V) P Embedded CPU (VDD_CPU 1.1V) P

RGMII 1.8V interface P RGMII (10/100 RGMII only) 3.3V interface P GMII 3.3V interface P MII/MMII 3.3V interface P Miscellaneous interfaces

(JTAG, TWSI, UART, NAND flash, Audio, SDIO, TDM, TS, and SPI)

DDR2 SDRAM interface (On-board, 16-bit, 400 MHz)

eFuse during Burning mode NOTE: Since the eFuse burn is pe rformed

only once, there is no thermal effect after the burn has finished.

VDD

VDD_CPU

RGMII

GMII

MII

MISC

DDR2

FUSE

TCLK @ 200 MHz 280 mW

CPU @ 1000 MHz,

790 mW

L2 @ 333 MHz

CPU @ 1200 MHz,

870 mW

L2 @ 400 MHz CPU @ 1500 MHz,

1050 mW

L2 @ 500 MHz

30 mW 50 mW 50 mW 10 mW 50 mW

Four on board devices, 75 ohm

250 mW

ODT termination

50 mW

eFuse during Reading mode P PCI Express interface P USB interface P SATA interface P

FUSE

PEX

USB

SATA

Both SATA ports 410 mW

25 mW 100 mW 120 mW

Notes:

1. The values are for nominal voltage.

2. Power in mW is calculated using the typical recommended VDDIO specification for each power rail.

Page 80

88F6281 Hardware Specifications

8.4 Current Consumption

The purpose of the Current Consumption table is to support board power design and power module selection.

Table 38: Current Consumption

Interface Symbol Test Conditions Max Units

Core (VDD 1.0V) I Embedded CPU (VDD_CPU 1.1V) I

RGMII 1.8V or 3.3V interface I GMII 3.3V interface I MII/MMII 3.3V interface I Miscellaneous interfaces

(JTAG, TWSI, UART, NAND flash, Audio, SDIO, TDM, TS, and SPI)

DDR2 SDRAM interface (16-bit 400 MHz) I

eFuse during Burning mode I eFuse during Reading mode I PCI Express interface I

VDD

VDD_CPU

RGMII

GMII

MII_MMII

MISC

DDR2

FUSE

PEX

TCLK @ 200 MHz 600 mA

CPU @ 1000 MHz,

1920 mA

L2 @ 333 MHz

CPU @ 1200 MHz,

2010 mA

L2 @ 400 MHz CPU @ 1500 MHz,

2100 mA

L2 @ 500 MHz

25 mA 25 mA 25 mA 25 mA

Four on board devices, 75 ohm

550 mA

ODT termination

20 mA 25 mA

50 mA USB interface I SATA interface I

USB

SATA

Both SATA ports 130 mA

40 mA

Notes:

1. Current in mA is calculated using maximum recommended VDDIO specification for each power rail.

2. All output clocks toggling at their specified rate.

3. Maximum drawn current from the power supply.

Page 81

Electrical Specifications

Note

Parameter Symbol Test Condition Min Typ Max Units Notes

Input low level VIL -0.3 0.8 V Input high level VIH 2.0 VDDIO+0.3 V Output low level VOL IOL = 2 mA - 0.4 V Output high level VOH IOH = -2 mA 2.4 - V Input leakage current IIL 0 < VIN < VDDIO -10 10 uA 1, 2 Pin capacitance Cpin 5 pF -

Notes :

General comment: See the Pin Description section for internal pullup/pul ldown.

1. While I/O is in High-Z.

2. This current does not include the current flowing through the pullup/pulldown resistor.

DC Electrical Specifications

8.5 DC Electrical Specifications

See Section 1.3, Internal Pull-up and Pull-down Pins, on page 48 for internal pullup/pulldown information.

8.5.1 General 3.3V (CMOS) DC Electrical Specifications

The DC electrical specifications in Table 39 are applicable for the following interfaces and signals:

 JTAG  RGMII (10/100 Mbps)/GMII/MII/MMII  Secure Digital Input/Output (SDIO)  S/PDIF / I  Transport Stream (TS)  NAND flash  UART  MPP  PTP  SYSRSTn

In the following table, for the JTAG, SDIO, S/PDIF / I interfaces, VDDIO means the VDDO power rail. For the RGMII/GMII/MII/MMII interface, VDDIO means the VDD_GE_A and VDD_GE_B power rails.

Table 39: General 3.3V Interface (CMOS) DC Electrical Specifications

S (Audio)

S, TS, NAND flash, UART, PTP, and MPP

Page 82

Parameter Symbol Test Condition Min Typ Max Units Notes

Input low level VIL -0.3 0.35*VDDIO V Input high level VIH 0.65*VDDIO VDDIO+0.3 V Output low level VOL IOL = 2 mA - 0.45 V Output high level VOH IOH = -2 mA VDDIO-0.45 - V I nput leakage current IIL 0 < VIN < VDDIO -10 10 uA 1, 2 Pin capacitance Cpin 5 pF -

Notes :

General comment: See the Pin D escription section for internal pullup/pulldown.

1. While I/O is in High-Z.

2. This current does not include the current flowing through the pullup/pulldown resistor.

88F6281 Hardware Specifications

8.5.2 RGMII, SMI and REF_CLK_XIN 1.8V (CMOS) DC Electrical Specifications

In the following table, for the RGMII interface, VDDIO means the VDD_GE_A power rail. In the following table, for the REF_CLK_XIN pin, VDDIO means the XTAL_AVDD power rail.

Table 40: RGMII 1.8V Interface (CMOS) DC Electrical Specifications

Page 83

Electrical Specifications

Pa rameter Sy mbol Test Condition Min Typ Max Uni ts Notes

Input low level VI L - -0.3 VREF - 0.125 V Input high level VIH - VREF + 0.125 VDDIO + 0.3 V Output low level VOL IO L = 13.4 mA 0.28 V Output high level VOH IOH = -13.4 mA 1.42 V -

120 150 180 ohm 1 , 2

60 75 90 ohm 1 , 2

40 50 60 ohm 1 , 2 Deviation of VM with respect to VDDQ/2 dVm See note 3 -6 6 % 3 Input l eakage current II L 0 < VIN < VDD IO -10 10 uA 4, 5 Pin capacitance Cpin - 5 pF -

Notes:

General com ment: See the Pin D escription section for internal pullup/pul ldown.

1. See SDR AM functional description section for ODT configuration.

2. M easureme nt definition for RTT: Apply VREF +/- 0.25 to input pin separately, then measure current I

(VREF + 0.25)

and I

(VREF - 0.25)

respectively.

3. M easureme nt definition for VM: Measured voltage (VM) at input pin (midp oi nt) with no load.

4. While I/O i s in High-Z.

5. This current does not include the current flowing through the pullup/pull down resistor.

Rtt effective impedance value RTT See note 2

)25.0()25.0(

5.0

−+

−

VRE FVREF

RTT

%10 012×

⎟ ⎠

⎞

⎜ ⎝

⎛

−

VDDIO

dVM

DC Electrical Specifications

8.5.3 SDRAM DDR2 Interface DC Electrical Specifications

In the following table, VREF is VDD_M/2 and VDDIO means the VDD_M power rail.

Table 41: SDRAM DDR2 Interface DC Electrical Specifications

Page 84

Parameter Sy mbol Test Condition Min Typ Max Units N otes

Input low level VIL -0.5 0.3*VDDIO V Input high level VIH 0.7*VDDIO VDDIO+0.5 V Output low level VOL IOL = 3 mA - 0.4 V Input leakage current IIL 0 < VIN < VDDIO -10 10 uA 1, 2 Pin capacitance Cpin 5 pF -

Notes :

General comment: See the Pin Description section for internal pullup/pul ldown.

1. While I/O is in High-Z.

2. This current does not include the current flowing through the pullup/pulldown resistor.

Parameter Sy mbol Test Condition Min Typ Max Units N otes

Input low level VIL -0.5 0.3*VDDIO V Input high level VIH 0.7*VDDIO VDDIO+0.5 V Output low level VOL IOL = 4 m A - 0.4 V Output high level VOH IOH = -4 mA VDDI O-0.6 - V Input leakage current IIL 0 < VIN < VDDIO -10 10 uA 1, 2 Pin capacitance Cpin 5 pF -

Notes :

General comment: See the Pin Description section for internal pullup/pulldown.

1. While I/O is in High-Z.

2. This current does not include the current flowing through the pullup/pulldown resistor.

88F6281 Hardware Specifications

8.5.4 Two-Wire Serial Interface (TWSI) 3.3V DC Electrical Specifications

In the following table, VDDIO means the VDDO power rail.

Table 42: TWSI Interface 3.3V DC Electrical Specifications

8.5.5 Serial Peripheral Interface (SPI) 3.3V DC Electrical Specifications

In the following table VDDIO means the VDDO power rail.

Table 43: SPI Interface 3.3V DC Electrical Specifications

Page 85

Electrical Specifications

Parameter Sy mbol Test Condition Min Typ Max Units N otes

Notes :

General comment: See the Pin Description section for internal pullup/pulldown.

1. While I/O is in High-Z.

2. This current does not include the current flowing through the pullup/pulldown resistor.

DC Electrical Specifications

8.5.6 Time Division Multiplexing (TDM) 3.3V DC Electrical Specifications

In the following table VDDIO means the either the VDDO or the VDD_GE_B power rail, depending on which MPP pins are configured for the TDM interface.

Table 44: TDM Interface 3.3V DC Electrical Specifications

Page 86

88F6281 Hardware Specifications

8.6 AC Electrical Specifications

See Section 8.7, Differential Interface Electrical Characteristics, o n page 118 for differential interface specifications.

8.6.1 Reference Clock AC Timing Specifications

Table 45: Reference Clock AC Timing Specifications

Description Symbol Min Max Units Notes CPU and Core Reference Clock

Frequency F

Clock duty cycle DC Slew rate SR Pk-Pk jitter JR

REF_CLK_XIN

Ethernet Reference Clock

Frequency in MII/MMII-MAC mode F

MII/MMII-MAC mode clock duty cycle DC

Slew rate SR

GE_TXCLK_OUT

GE_RXCLK

GE_TXCLK_OUT

GE_RXCLK

GE_TXCLK_OUT

GE_RXCLK

Audio External Reference Clock

Audio external reference clock F

AU_EXTCLK

S/PDIF Recovered Master Clock

S/PDIF recovered master clock F

S Reference Clock

S clock F

AU_SPDFRMCLK

I2S_BCLK

SPI Output Clock

SPI output clock F

SPI_SCK

RTC Reference Clock

RTC_XIN crystal frequency F

RTC_XIN

Transport Stream (TS) Output Mode Reference Clock

TS output clock in parallel mode F TS output clock in serial mode F

TS0_CLK, FTS1_CLK TS0_CLK, FTS1_CLK

Transport Stream Input Mode Reference Clock

TS input clock in parallel mode F TS input clock in serial mode F

TS0_CLK, FTS1_CLK TS0_CLK, FTS1_CLK

Transport Stream External Reference Clock

TS external clock in parallel mode F TS external clock in serial mode F

EXT_CLK EXT_CLK

25 -

50 ppm

25 + 50 ppm

40 60 %

0.7 V/ns 1 200 ps

2.5 -

100 ppm

50 + 100 ppm

35 65 % 7

0.7 V/ns 1, 7

256 X F

64 X F

TCLK/30 TCLK/4 MHz 2

32.768 kHz 4

9.61 12.5 MHz 5

9.61 83 MHz 5

13.5 MHz 83 MHz

9.61 12.5 MHz 5

9.61 83 MHz 5

MHz

MHz 7

kHz 3

Page 87

Electrical Specifications

AC Electrical Specifications

Table 45: Reference Clock AC Timing Specifications (Continued)

Description Symbol Min Max Units Notes TDM_SPI Output Clock

TDM_SPI output clock F

SMI Master Mode Reference Clock

SMI output MDC clock F

TWSI Master Mode Reference Clock

SCK output clock F

PTP Reference Clock

Frequency F

Clock duty cycle DC Slew rate SR Pk-Pk jitter JR

Notes:

1. Slew rate is defined from 20% to 80% of the reference clock signal.

2. For additional information regarding configuring this clock, see the Serial Memory Interface Control Register in the

88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

3. Fs is the audio sample rate, which can be configured to 44.1 kHz, 48 kHz, or 96 kHz (see the Audio (I

S / S/PDIF) Interface section in the 88F6180, 88F6190, 88F6192, and 88F6281

Functional Specifications).

4. The RTC design was optimized for a standard CL = 12.5 pF crystal. No passive components are provided internally. Connect the crystal and the passive network as recommended by the crystal manufacturer.

5. The frequency can be set using the TS Interface Configuration register (see the 88F6180,

88F6190, 88F6192, and 88F6281

6. For the minimum value refer to the Baud Rate Register section of the 88F6180, 88F6190,

88F6192, and 88F6281

Functional Specifications.

7. The Ethernet Reference Clock parameters refer both to the reference clock for an Ethernet port configured using the dedicated port pins and for an Ethernet port configured using the multiplexed port pins.

TDM_SPI_SCK

GE_MDC

TW_SCK

PTP_CLK

Functional Specifications).

8.192 MHz

TCLK/128 MHz

TCLK/

kHz 6

1600

125 -

100 ppm

125 +

100 ppm

MHz

40 60 %

0.7 V/ns 1 100 ps

Page 88

Min Max

Clock frequency fCK MHz DQ and DM valid output time before DQS transition tDOVB 0.40 - ns DQ and DM valid output time after DQS transition tDOVA 0.40 - ns DQ and DM output pulse w idth tDIPW 0.35 - tCK(avg) DQS output high pulse width tDQSH 0.35 - tCK(avg) DQS output low pulse width tDQSL 0.35 - tCK(avg) DQS falling edge to CLK-CLKn rising edge tDSS 0.34 - tCK(avg) 1 DQS falling edge from CLK-CLKn rising edge tDSH 0.34 - tC K(avg) 1 DQS latching rising transitions to associated clock edges tDQSS -0.11 0.11 tCK (avg) DQS write preamble tWPRE 0.35 - tCK(avg) DQS write postamble tWPST 0.40 - tC K(avg) Average CLK-CLK n high-level w idth tCH(avg) 0.48 0.52 tCK(avg) 1, 2, 3 Average CLK-CLK n low-level w idth tCL(avg) 0.48 0.52 tC K(avg) 1, 2, 4 DQ input setup time relative to DQS in transition tDSI -0.42 - ns DQ input hold time relative to DQS in transition tDH I 0.70 - ns Address and control output pulse width tIPW 0.60 - tCK(avg) -

Note s:

General comment: All timing values are defined from Vref to Vref, unless otherw ise specified. General comment: All input timing values assum e minimum slew rate of 1 V/ns (slew rate defined from Vref +/-125 mV). General comment: tCK(avg) is calculated as the average clock period across any consecutive 200 cycle w indow. General comment: All timing parameters with DQS signal are defined on DQS -DQSn crossing point. General comment: For Address and Control output tim ing parameters, refer to the Address Ti ming table. General comment: For all signals, the load is CL = 14 pF.

1. This timing value is defined on CLK / CLKn crossing point.

2. Refer to SDRAM DD R2 clock specifications table for more information.

3. tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.

4. tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.

400.0

Note sDes cription Symbol

400 MH z @ 1.8V

Units

88F6281 Hardware Specifications

8.6.2 SDRAM DDR2 Interface AC Timing

8.6.2.1 SDRAM DDR2 Interface AC Timing Table

Table 46: SDRAM DDR2 Interface AC Timing Table

Page 89

Table 47: SDRAM DDR2 Interface Address Timing Table

Min Max

Address and Control valid output time before CLK-CLkn rising edge tAOVB 0.65 - ns 1, 2 Address and Control valid output time after CLK-CLKn rising edge tAOVA 0.65 - ns 1, 2 Address and Control valid output time before CLK-CLkn rising edge tAOVB 2.95 - ns 1, 3 Address and Control valid output time after CLK-CLKn rising edge tAOVA 0.65 - ns 1, 3

Notes :

General comment: All timing values were measured from vref to vref, unless otherw ise specified. General comment: For all signals, the load is CL = 14 pF.

1. This timing value is defined on CLK / CLKn crossing point.

2. This timing value is defined when Address and Control signals are output on CLK-CLKn falling edge. For more inform ation, see register settings.

3. This timing value is defined when Address and Control signals are output on CLK-CLKn falling edge. and 2T mode is enabled. For more information, see register settings. Except for ODT, CKE and CS signals.

Note sDes cription Sym bol

400 MHz @ 1.8V

Units

Electrical Specifications

AC Electrical Specifications

Page 90

Des cription Sym bol Min M ax Units Notes

Clock period jitter tJIT(per) -100 100 ps 1 Clock perior jitter during DLL locking period tJIT(per,lck) -80 80 ps 2 Cycle to cycle clock period ji tter tJIT(cc) -200 200 ps 3 Cycle to cycle clock period ji tter during DLL locking period tJIT(cc,lck) -160 160 ps 4 Cumulative error acros s 2 cycles tERR( 2per) -150 150 ps 5 Cumulative error acros s 3 cycles tERR( 3per) -175 175 ps 5 Cumulative error acros s 4 cycles tERR( 4per) -200 200 ps 5 Cumulative error acros s 5 cycles tERR( 5per) -200 200 ps 5 Cumulative error acros s n cycles, n=6...10, i nclusive tERR(6-10per) -300 300 ps 5 Cumulative error acros s n cycles, n=11…50, inclusive tERR(11- 50per) -450 450 ps 5 Duty cycle jitter tJIT(duty) -100 100 ps 6 Absolute clock period tCK(abs) ps 7 Absolute clock high pulse w idth tCH(abs) ps 8 Absolute clock low pulse w idth tCL(abs) ps 9

Notes:

General comment: All timing values are defined on CLK / CLK n crossing point, unless otherwise specified.

1. tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = Mi n/max of {tCKi- tCK(avg) where i=1 to 200}. tJIT(per) defines the single period jitter when the DLL is already locked.

2. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.

3. tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of |tCKi+1 – tCKi|. tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.

4. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.

5. tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg). Please refer to JEDEC Standard No. 79-2C (DDR2 SDRAM Specification), Chapter 5 (page 100) for more information.

6. tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg). tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)} where, tJIT(CH) = {tCHi- tCH (avg) w here i=1 to 200}; tJIT(CL) = {tCLi- tC L(avg) w here i=1 to 200}.

7. tCK(abs),min = tCK(avg),min + tJIT(per),min; tCK(abs),max = tCK(avg),max + tJIT(per),max.

8. tCH(abs),min = tCH (avg),min x tC K(avg),mi n + tJIT(duty),min; tCH(abs),max = tC H(avg),max x tCK (avg),max + tJIT(duty),max.

9. tCL(abs),min = tCL(avg),min x tCK(avg),min + tJI T(duty),m in; tCL(abs),max = tCL(avg),max x tC K(avg),max + tJIT(duty),max.

See note 7 See note 8 See note 9

88F6281 Hardware Specifications

8.6.2.2 SDRAM DDR2 Clock Specifications

Table 48: SDRAM DDR2 Clock Specifications

Page 91

8.6.2.3 SDRAM DDR2 Interface Test Circuit

50 ohm

VTT

Test Point

tDSStDSH

DQS

tWPRE

tDQSH tDQSL tWPST

tDIPW

tDOVB tDOVA

CLKn

CLK

tCLtCH

DQSn

Figure 5: SDRAM DDR2 Interface Test Circuit

8.6.2.4 SDRAM DDR2 Interface AC Timing Diagrams

Figure 6: SDRAM DDR2 Interface Write AC Timing Diagram

Electrical Specifications

AC Electrical Specifications

Page 92

ADDRESS/

CONTROL

tIPW

tAOVB tAOVA

CLKn

CLK

tCLtCH

tDHI

tDSI

DQS

DQSn

88F6281 Hardware Specifications

Figure 7: SDRAM DDR2 Interface Address and Control AC Timing Diagram

Figure 8: SDRAM DDR2 Interface Read AC Timing Diagram

Page 93

Electrical Specifications

Description Sym bol Min Max Units Notes

Clock frequency fCK MHz Data to Clock output skew TskewT -0.50 0.50 ns 2 Data to Clock inpu t skew TskewR 1.00 2.60 ns Clock cycle duration Tcyc 7.20 8.80 n s 1 , 2 Duty cycle fo r Gigabi t Duty_G 0.45 0.55 tCK 2 Duty cycle fo r 10/100 Megabit Duty_T 0.40 0.60 tCK 2

Notes:

General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified. General comment: tCK = 1/fCK. General comment: If the PHY does not support internal-delay mode, the PC board design requires routing clocks so that an additional trace delay of greater than 1.5 ns and less than 2.0 ns is added to the associated clock signal. For 10/100 Mbps RG MII, the Max value is unspecified.

1. For RGMII at 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns +/-40 ns and 40 ns +/-4 ns, respectively.

2. For all signals, the load is CL = 5 pF.

125.0

Description Sym bol Min Max Units Notes

Clock frequency fCK MHz Data to Clock output skew Tskew T -0.50 0.50 ns 2 Data to Clock inpu t skew TskewR 1.00 2.60 ns Clock cycle duration Tcyc 7.20 8.80 ns 1 , 2 Duty cycle fo r G igabit Duty_G 0.45 0.55 tCK 2 Duty cycle fo r 10/100 Megabit Duty_T 0.40 0.60 tCK 2

Notes :

General comment: All values w ere measured from vddio/2 to vddio/2, unless otherwise specified. General comment: tCK = 1/fCK. General comment: If the PHY does not support internal-delay mode, the PC board design requires routing clocks so that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. For 10/100 Mbps RGMII, the Max value is unspecified.

1. For RGMII at 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns +/-40 ns and 40 ns +/-4 ns, respectively.

2. For all signals, the load is C L = 5 pF.

25.0

AC Electrical Specifications

8.6.3 Reduced Gigabit Media Independent Interface (RGMII) AC Timing

8.6.3.1 RGMII AC Timing Table

Table 49: RGMII 10/100/1000 AC Timing Table at 1.8V

Table 50: RGMII 10/100 AC Timing Table at 3.3V

Page 94

Test Point

(At Transmitter)

DATA

CLOCK

DATA

CLOCK (At Receiver)

TskewT

TskewR

88F6281 Hardware Specifications

8.6.3.2 RGMII Test Circuit

Figure 9: RGMII Test Circuit

8.6.3.3 RGMII AC Timing Diagram

Figure 10: RGMII AC Timing Diagram

Page 95

Electrical Specifications

Min Max

GTX_CLK cycle time tCK 7.5 8.5 ns RX_CLK cycle ti me tCKrx 7.5 - ns GTX_CLK and RX_CLK high level width tHIGH 2.5 - ns 1 GTX_CLK and RX_CLK low level width tLOW 2.5 - ns 1 GTX_C LK and RX_CLK rise time tR - 1.0 ns 1, 2 GTX_C LK and RX_CLK fall time tF - 1.0 ns 1, 2 Data input setup time relative to RX_CLK rising edge tSETUP 2.0 - ns Data input hold time relative to RX_CLK rising edge tHOLD 0.0 - ns Data output valid before GTX_CLK rising edge tOVB 2.5 - ns 1 Data output valid after GTX_CLK rising edge tOVA 0.5 - ns 1

Notes :

General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.

1. For all signals, the load is C L = 5 pF.

2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(m in) to VIL(max).

Note s

125 MHz

Description Sym bol Units

Test Point

AC Electrical Specifications

8.6.4 Gigabit Media Independent Interface (GMII) AC Timing

8.6.4.1 GMII AC Timing Table

Table 51: GMII AC Timing Table

8.6.4.2 GMII Test Circuit

Figure 11: GMII Test Circuit

Page 96

GTX_CLK

TXD, TX_EN, TX_ER

VIH(min) VIL(max)

tOVB

tLOW tHIGH

tOVA

VIH(min) VIL(max)

VIH(min)

VIL(max)

tSETUP

RX_CLK

RXD, RX_EN, RX_ER

tHOLD

tLOW tHIGH

88F6281 Hardware Specifications

8.6.4.3 GMII AC Timing Diagrams

Figure 12: GMII Output AC Timing Diagram

Figure 13: GMII Input AC Timing Diagram

Page 97

Electrical Specifications

Des cription Symbol Min Max Units Notes

Data input setup relative to RX _CLK rising edge tSU 3.5 - ns Data input hold relative to RX_CLK rising edge tHD 2.0 - ns Data output delay relative to M II_TX_CLK rising edge tOV 0.0 10.0 ns 1

Notes :

General comment: All values were measured from VIL(max) to VIH(min), unless otherw ise specified.

1. For all signals, the load is CL = 5 pF.

Test Point

MII_TX_CLK

TXD, TX_EN, TX_ER

Vih(min) Vil(max)

TOV

AC Electrical Specifications

8.6.5 Media Independent Interface/Marvell Media Independent Interface (MII/MMII) AC Timing

8.6.5.1 MII/MMII MAC Mode AC Timing Table

Table 52: MII/MMII MAC Mode AC Timing Table

8.6.5.2 MII/MMII MAC Mode Test Circuit

Figure 14: MII/MMII MAC Mode Test Circuit

8.6.5.3 MII/MMII MAC Mode AC Timing Diagrams

Figure 15: MII/MMII MAC Mode Output Delay AC Timing Diagram

Page 98

tHD

Vih(min)

Vih(min) Vil(ma x )

tSU

RX_CLK

RXD, RX_EN, RX_ER

88F6281 Hardware Specifications

Figure 16: MII/MMII MAC Mode Input AC Timing Diagram

Page 99

Electrical Specifications

Description Symbol Min Max Units Notes

MDC clock frequency fCK MHz 2 MDC cl ock duty cycle tDC 0.4 0.6 tCK MDIO input setup time relative to MDC rise time tSU 40.0 - ns MDIO input hold time relative to MDC rise time tHO 0.0 - ns MDIO output valid before MDC rise time tOVB 15.0 - ns 1 MDIO output valid after MDC rise time tOVA 15.0 - ns 1

Notes :

General comment: All timing values were measured from VIL(max) and VIH(mi n) levels, unless otherw ise specified. General comment: tCK = 1/fCK.

1. For MDC signal, the load is CL = 390 pF, and for MDIO signal, the load is CL = 470 pF .

2. See "Reference Cl ocks" table for more details.

See note 2

2 kilohm

VDDIO

Test Point

MDIO

AC Electrical Specifications

8.6.6 Serial Management Interface (SMI) AC Timing

8.6.6.1 SMI Master Mode AC Timing Table

Table 53: SMI Master Mode AC Timing Table

8.6.6.2 SMI Master Mode Test Circuit

Figure 17: MDIO Master Mode Test Circuit

Page 100

Test Point

MDC

MDIO

VIH(min)

VIH(min) VIL(max)

tOVAtOVB

MDC

MDIO

VIH(min)

VIL(max)

tSU

tHO

88F6281 Hardware Specifications

Figure 18: MDC Master Mode Test Circuit

8.6.6.3 SMI Master Mode AC Timing Diagrams

Figure 19: SMI Master Mode Output AC Timing Diagram

Figure 20: SMI Master Mode Input AC Timing Diagram

Marvel Group 88F6281 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Cover

PRODUCT OVERVIEW

FEATURES

Table of Contents

List of Tables

List of Figures

Preface

1 Pin and Signal Descriptions

1.1 Pin Logic

1.2 Pin Descriptions

1.2.1 Power Supply Pins

1.2.2 Miscellaneous Pin Assignment

1.2.3 DDR SDRAM Interface Pin Assignments

1.2.4 PCI Express Interface Pin Assignments

1.2.5 SATA Interface Pin Assignments

1.2.6 Gigabit Ethernet Port Interface Pin Assignments

1.2.7 Serial Management Interface (SMI) Interface Pin Assignments

1.2.8 USB 2.0 Interface Pin Assignments

1.2.9 JTAG Interface Pin Assignment

1.2.10 Real Time Clock (RTC) Interface Pin Assignments

1.2.11 NAND Flash Interface Pin Assignment

1.2.12 MPP Interface Pin Assignment

1.2.13 Two-Wire Serial Interface (TWSI) Interface

1.2.14 UART Interface

1.2.15 Audio (S/PDIF / I2S) Interface

1.2.16 Serial Peripheral Interface (SPI) Interface

1.2.17 Secure Digital Input/Output (SDIO) Interface

1.2.18 Time Division Multiplexing (TDM) Interface

1.2.19 Transport Stream (TS) Interface

1.2.20 Precise Timing Protocol (PTP) Interface

1.3 Internal Pull-up and Pull-down Pins

2 Unused Interface Strapping

3 88F6281 Pin Map and Pin List

4 Pin Multiplexing

4.1 Multi-Purpose Pins Functional Summary

4.2 Gigabit Ethernet (GbE) Pins Multiplexing on MPP

4.3 TSMP (TS Multiplexing Pins) on MPP

5 Clocking

5.1 Spread Spectrum Clock Generator (SSCG)

System Power Up/Down and Reset Settings

6.1 Power-Up/Down Sequence Requirements

6.1.1 Power-Up Sequence Requirements

6.1.2 Power-Down Sequence Requirements

6.2 Hardware Reset

6.2.1 Reset Out Signal

6.2.2 Power On Reset (POR)

6.2.3 SYSRSTn Duration Counter

6.3 PCI Express Reset

6.3.1 PCI Express Root Complex Reset

6.3.2 PCI Express Endpoint Reset

6.4 Sheeva™ CPU TAP Controller Reset

6.5 Pins Sample Configuration

6.6 Serial ROM Initialization

6.6.1 Serial ROM Data Structure

6.6.2 Serial ROM Initialization Operation

6.7 Boot Sequence

7 JTAG Interface

7.1 TAP Controller

7.2 Instruction Register

7.3 Bypass Register

7.4 JTAG Scan Chain

7.5 ID Register

8 Electrical Specifications (Preliminary)

8.1 Absolute Maximum Ratings

8.2 Recommended Operating Conditions

8.3 Thermal Power Dissipation

8.4 Current Consumption

8.5 DC Electrical Specifications

8.5.1 General 3.3V (CMOS) DC Electrical Specifications

8.5.2 RGMII, SMI and REF_CLK_XIN 1.8V (CMOS) DC Electrical Specifications

8.5.3 SDRAM DDR2 Interface DC Electrical Specifications

8.5.4 Two-Wire Serial Interface (TWSI) 3.3V DC Electrical Specifications

8.5.5 Serial Peripheral Interface (SPI) 3.3V DC Electrical Specifications

8.5.6 Time Division Multiplexing (TDM) 3.3V DC Electrical Specifications

8.6 AC Electrical Specifications

8.6.1 Reference Clock AC Timing Specifications