Marvel Group 88F6281 User Manual

Marvell. Moving Forward Faster

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88F6281

Integrated Controller

Hardware Specifications

Doc. No. MV-S104859-U0, Rev. E December 2, 2008, Preliminary

Document Classification: Proprietary Information

88F6281 Hardware Specifications

Document Conventions

Note: Provides related information or information of special importance.

Caution: Indicates potential damage to hardware or software, or loss of data.

Warning: Indicates a risk of personal injury.

Document Status

Doc Status: Preliminary Technical Publication: 0.xx

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Sheeva™ CPU Core

16 KB-I, 16 KB-D

Up to 1.5 GHz

AES/DES/

3DES

SHA-1/MD5

Processor

Memory

Security Engin e

Cache

256 KB

DDR

SDRAM

Controller

JTAG Interface

PCI Express

SATA

USB 2.0

High Speed I/0

PCI Express x1

Dual SATA ports

USB 2.0 port

88F6281 Functional Block Diagram

External DDR

800 MHz

Misc

FXS / FXO

SPI, NAND, SDIO

Slow Bus

TDM

UART x2 GPIO, TWSI Flash, SDIO

4 XOR/DMA channels

XOR Engine

Internal Bus

Gigabit Ethernet IEEE 1588AVB support

MPEG2-TS

S / S/PDIF

Media Interfaces

MPEG TS

Audio

PRODUCT OVERVIEW

88F6281

Integrated Controller

Hardware Specifications

The Marvell® 88F6281 is a high-performance, highly integrated controller. The 88F6281 is based on the Marvell proprietary, ARMv5TE-compliant, high-speed Sheeva

™

CPU core. The CPU core integrates a 256 KB L2 cache.

FEATURES

88F6281 Hardware Specifications

 The 88F6281 includes:

• High-performance CPU core, running at up to

1.5 GHz, with integrated, four-way, set-associative L1 16-KB I-cache/16-KB D-cache and unified, 256-KB, four-way, set-associative L2 cache

• High-bandwidth dual-port DDR2 memory interface

(16-bit DDR2 SDRAM @ up to 800 MHz data rate)

• PCI Express (x1) port with integrated PHY

• Two Gigabit Ethernet (10/100/1000 Mbps) MACs

• USB 2.0 port with integrated PHY

• Two SATA 2.0 ports w ith inte grated 3 Gbp s SATA II

PHY

• Security Cryptographic engine

• S/PDIF (Sony/Philips Digital Interconnect Format) /

S (Integrated Interchip Sound) Audio in/out

I interface

• SD/SDIO/MMC interface

• TDM SLIC/SLAC Codec interface

• Two XOR engines, each containing two XOR/DMA

channels (a total of four XOR/DMA channels)

• MPEG Transport Stream (TS) interface

• SPI port with SPI flash boot support

• 8-bit NAND flash interface with boot support

• Two 16550 compatible UART interfaces

• TWSI port

• 50 multi-purpose pins

• Internal Real Time Clock (RTC)

• Interrupt controller

• Timers

• 128-bit eFuse (one-time programmable memory)

 Sheeva

™

CPU core

• Up to 1.5 GHz

• 32-bit and 16-bit RISC architecture

• Compliant with v5TE architecture, as published in

the ARM Architect Reference Manual, Second Edition

• Includes MMU to support virtual memory features

• 256-KB, four-way, set-associative L2 unified cache

• 16-KB, four-way, set-associative I-cache

• 16-KB, four-way, set-associative D-cache

• 64-bit internal data bus

• Branch Prediction Unit

• Supports JTAG/ARM ICE

• Supports both Big and Little Endian modes

 DDR2 SDRAM controller

• 16-bit interface

• Up to 400 MHz clock frequency (800 MHz data

rate)

• DDR SDRAM with a clock ratio of 1:N and 2:N

between the DDR SDRAM and the CPU core, respectively

• SSTL 1.8V I/Os

• Auto calibration of I/Os output impedance

• Supports four DRAM chip selects

• Supports all DDR devices densities up to 2 Gb

• Supports up to 32 open pages (page per bank)

• Up to 2 GB total address space

• Supports on-board DDR designs (no DIMM

support)

• Supports 2T mode, to enable high-frequency

operation under heavy load configuration

• Supports DRAM bank interleaving

• Supports up to a 128-byte burst per single memory

access

 PCI Express interface (x1)

• PCI Express Base 1.1 compatible

• Integrated low-power SERDES PHY, based on

proven Marvell

SERDES technology

• Serves as a Root Complex or an Endpoint port

• x1 link width

• 2.5 Gbps data rate

• Lane polarity reversal support

• Maximum payload size of 128 bytes

• Single Virtual Channel (VC-0)

• Replay buffer support

• Extended PCI Express configuration space

• Advanced Error Reporting (AER) support

• Power management: L0s and software L1 support

• Interrupt emulation message support

• Error message support

 PCI Express master specific features

• Single outstanding read transaction

• Maximum read request of up to 128 bytes

• Maximum write request of up to 128 bytes

• Up to four outstanding read transactions in

Endpoint mode

 PCI Express target specific features

• Supports up to eight read request transactions

• Maximum read request size of 4 KB

• Maximum write request of 128 bytes

• Supports PCI Express access to all of the

controller’s internal registers

 Two Integrated GbE (10/100/1000) MAC ports

• Supports 10/100/1000 Mbps

• Dedicated DMA for data movement between

memory and port

Features

• Priority queuing on receive based on Destination

Address (DA), VLAN Tag, and IP TOS

• Layer 2/3/4 frame encapsulation detection

• TCP/IP checksum on receive and transmit

• Supports proprietary 200 Mbps Marvell MII (MMII)

interface

• Supports four modes:

- Port 0 RGMII, Port 1 RGMII

- Port 0 RGMII, Port 1 MII/MMII

- Port 0 MII/MMII, port 1 RGMII

- Port 0 GMII, Port 1 N/A

•DA filtering

 Precise Timing Protocol (PTP)

• Supports precise time stamping for packets, as

defined in IEEE 1588 PTP v1 and v2 and IEEE

802.1AS draft standards

• Supports Flexible Time Application interface to

distribute PTP clock and time to other devices in the system

• Optionally accepts an external clock input for time

stamping

 Audio Video Bridging networks

• Supports IEEE 802.1Qav draft Audio Video

Bridging networks

• Supports time- and priority-aware egress pacing

algorithm to prevent bunching and bursting effects—suitable for audio/video applications

• Supports Egress Jitter Pacer for AVB-Class A and

AVB-Class B traffic and strict priority for legacy traffic queues

 USB 2.0 port

• Serves as a peripheral or host

• USB 2.0 compliant

• Integrated USB 2.0 PHY

• Enhanced Host Controller Interface (EHCI)

compatible as a host

• As a host, supports direct connection to all

peripheral types (LS, FS, HS)

• As a peripheral, connects to all host types (HS, FS)

and hubs

• Up to four independent endpoints, supporting

control, interrupt, bulk, and isochronous data transfers

• Dedicated DMA for data movement between

memory and port

 T wo Integrated Marvell 3 Gbps (Gen2i) SA T A PHYs

• Compliant with SATA II Phase 1 specifications

- Supports SATA II Native Command Queuing

(NCQ), up to 128 outstanding commands per port

- Fully supports first party DMA (FPDMA)

- Backwards compatible with SATA I devices

• Supports SATA II Phase 2 advanced features

- 3 Gbps (Gen2i) SATA II speed

- Port Multiplier (PM)—Performs FIS-based

switching, as defined in SAT A working group PM definition

- Port Selector (PS)—Issues the protocol-bas ed

Out-Of-Band (OOB) sequence for selecting the active host port

• Supports device 48-bit addressing

• Supports ATA Tag Command Queuing

 SATA II Host Controller

• Enhanced-DMA (EDMA) for the SATA ports

• Automatic command execution, without host

intervention

• Command queuing support, for up to 32

outstanding commands

• Separate SATA request/response queues

• 64-bit addressing support for descriptors and data

buffers in system memory

• Read ahead

• Advanced interrupt coalescing

• Target mode operation—supports attaching two

88F6281 controllers through their Serial-ATA ports, enabling data communication between the 88F6281 controllers

• Advanced drive diagnostics via the ATA SMART

command

 Cryptographic engine

• Hardware implementation on encryption and

authentication engines, to boost packet processing speed

• Dedicated DMA to feed the hardware engines with

data from the internal SRAM memory or from the DDR memory

• Implements AES, DES, and 3DES encryption

algorithms

• Implements SHA1 and MD5 authentication

algorithms

 S/PDIF / I

• Either S/PDIF or I

• Both S/PDIF and I

 S/PDIF-specific features

S Audio In/Out interface

time

simultaneously active, transferring the same PCM data

S inputs can be active at one

S outputs can be

• Compliant with 60958-1, 60958-3, and IEC61937

specifications

• Sample rates of 44.1/48/96 kHz

• 16/20/24-bit depths

88F6281 Hardware Specifications

 I

S-specific features

• Sample rates of 44.1/48/96 kHz

• I

S input and I2S output operate at the same

sample rate

• 16/24-bit depths

• I

S in and I2S out support independent bit depths

(16 bit/24 bit)

• Supports plain I

S, right-justified and left-justified

formats

 SD/SDIO/MMC host interface

• 1-bit/4-bit SDmem, SDIO, and MMC cards

• Up to 50 MHz

• Hardware generate/check CRC, on all command

and data transactions on the card bus

 TDM SLIC/SLAC Codec interface

• Generic interface to standard SLIC/SLAC codec

devices

• Compatible with standard PCM highway formats

• TDM protocol support for two channels, up to

128 time slots

• Dedicated SPI interface for codec management

• Integrated DMA to transfer voice data to/from

memory buffer

 Two XOR engines and DMA

• Two XOR/DMA channels per XOR engine (for a

total of four XOR/DMA channels)

• Chaining via linked-lists of descriptors

• Moves data from source interface to destination

interface

• Supports increment or hold on both Source and

Destination Addresses

• Supports XOR operation, on up to eight source

blocks—useful for RAID applications

• Supports iSCSI CRC-32 calculation

 NAND flash controller

• 8-bit NAND flash interface

• Glueless interface to CE Care and CE Don’t Care

NAND flash devices

• Boot support

 Serial Peripheral Interface (SPI) controller

• Up to 50 MHz clock

• Supports direct boot from external SPI serial flash

memory

 MPEG Transport Stream (TS) interface

• ISO/IEC 13818-1 standard compliant

• Supports any one of the following modes:

- Parallel (8 bit) input

- Parallel output

- Two independent serial interfaces

• Data rate up to 80 Mbps

 Two UART Interfaces

• 16550 UART compatible

• Two pins for transmit and receive operations

• Two pins for mode m control functions

 Two-Wire Serial Interface (TWSI)

• General purpose TWSI master/slave port

• Can also be used for serial ROM initialization

 50 dedicated Multi-Purpose Pins (MPPs) for

peripheral functions and general purpose I/O

• Each pin can be configured independently.

• GPIO inputs can be used to register interrupts from

external devices, and to generate maskable interrupts.

• Only two of the following multiplexed interfaces

may be configured simultaneously:

- Audio

- TS

- TDM

- GbE Port 0 in GMII mode or GbE Port 1

 Interrupt Controller

Maskable interrupts to CPU core (and PCI Express for a PCI Express endpoint)

 Two general purpose 32-bit timers/counters  Internal architecture

• Mbus-L bus for high-performance, low-latency CPU

core to DDR SDRAM connectivity

• Advanced Mbus architecture

• Dual port DDR SDRAM controller connectivity to

both CPU and Mbus

 Bootable from

• SPI flash

• SATA device

• NAND flash

• PCI Express

• UART (for debug purpose)

 288-pin HSBGA package, 19 x 19 mm, 1 mm ball

pitch

Features

x16

TDM

Usage Model Example: VoIP Gateway

PCI Express

Mini Card Wi-Fi

SD Card

USB Host

SATA Port

Multiplier

HDD

Audio

A/D – D/A

GbE PHY FXS FXO

NAND Flash

SPI Flash (op.)

On Board DDR2

88F6281

88F6281 Hardware Specifications

Product Overview.......................................................................................................................................3

Features.......................................................................................................................................................4

Preface.......................................................................................................................................................15

About this Document.......................................................................................................................................15

Related Documentation...................................................................................................................................15

Document Conventions...................................................................................................................................16

1 Pin and Signal Descriptions.......................................................................................................17

1.1 Pin Logic .........................................................................................................................................................18

1.2 Pin Descriptions..............................................................................................................................................19

1.3 Internal Pull-up and Pull-down Pins................................................................................................................48

2 Unused Interface Strapping........................................................................................................49

3 88F6281 Pin Map and Pin List .......... ... ... ... .... ... ............................................. ... .... ... ... ... .............50

4 Pin Multiplexing...........................................................................................................................51

4.1 Multi-Purpose Pins Functional Summary........................................................................................................51

4.2 Gigabit Ethernet (GbE) Pins Multiplexing on MPP..........................................................................................57

4.3 TSMP (TS Multiplexing Pins) on MPP.............................................................................................................59

5 Clocking .......................................................................................................................................60

5.1 Spread Spectrum Clock Generator (SSCG)....................................................................................................62

6 System Power Up/Down and Reset Settings............................................................................63

6.1 Power-Up/Down Sequence Requirements......................................................................................................63

6.2 Hardware Reset ..............................................................................................................................................64

6.3 PCI Express Reset.......................................... ... ... ..........................................................................................66

™

6.4 Sheeva

6.5 Pins Sample Configuration..............................................................................................................................66

6.6 Serial ROM Initialization..................................................................................................................................70

6.7 Boot Sequence................................................................................................................................................71

CPU TAP Controller Reset..............................................................................................................66

7 JTAG Interface.............................................................................................................................73

7.1 TAP Controller.................................................................................................................................................73

7.2 Instruction Register.........................................................................................................................................73

7.3 Bypass Register..............................................................................................................................................74

7.4 JTAG Scan Chain ............... ............................................................................... .. ...........................................74

7.5 ID Register........................................ ..............................................................................................................74

Table of Contents

8 Electrical Specifications (Preliminary) ......................................................................................75

8.1 Absolute Maximum Ratings ............................................................................................................................75

8.2 Recommended Operating Conditions.............................................................................................................77

8.3 Thermal Power Dissipation .............................................................................................................................79

8.4 Current Consumption......................................................................................................................................80

8.5 DC Electrical Specifications............................................................................................................................81

8.6 AC Electrical Specifications ............................................................................................................................86

8.7 Differential Interface Electrical Characteristics..............................................................................................118

9 Thermal Data (Preliminary).......................................................................................................129

10 Package......................................................................................................................................130

11 Part Order Numbering/Package Marking ................................................................................132

11.1 Part Order Numbering........................................ ... ... ............................................... ......................................132

11.2 Package Marking ..........................................................................................................................................133

A Revision History ........................................................................................................................134

88F6281 Hardware Specifications

List of Tables

1 Pin and Signal Descriptions ............................................................................................................17

Table 1: Pin Functions and Assignments Table Key......................................................................................19

Table 2: Interface Pin Prefix Codes................................. ................................................ ...............................19

Table 3: Power Pin Assignments....................................................................................................................21

Table 4: Miscellaneous Pin Assignments .......................................................................................................23

Table 5: DDR SDRAM Interface Pin Assignments.........................................................................................24

Table 6: PCI Express Interface Pin Assignments...........................................................................................26

Table 7: SATA Port Interface Pin Assignment................................................................................................27

Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments .......................................................................28

Table 9: Serial Management Interface (SMI) Pin Assignments......................................................................32

Table 10: USB 2.0 Interface Pin Assignments..................................................................................................33

Table 11: JTAG Pin Assignment......................................................... ..............................................................34

Table 12: RTC Interface Pin Assignments........................................................................................................35

Table 13: NAND Flash Interface Pin Assignment.............................................................................................36

Table 14: MPP Interface Pin Assignment.........................................................................................................37

Table 15: Two-Wire Serial Interface (TWSI) Interface Pin Assignment............................................................38

Table 16: UART Port 0/1 Interface Pin Assignment .........................................................................................39

Table 17: Audio (S/PDIF / I

Table 18: Serial Peripheral Interface (SPI) Interface Signal Assignment ...................................................... ...41

Table 19: Secure Digital Input/Output (SDIO) Interface Signal Assignment.....................................................42

Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment .......................................................43

Table 21: Transport Stream (TS) Interface Signal Assignment........................................................................45

Table 22: Precise Timing Protocol (PTP) Interface Signal Assignment............................................................47

Table 23: Internal Pull-up and Pull-down Pins..................................................................................................48

S) Interface Signal Assignment....................................... ... ... ...............................40

2 Unused Interface Strapping.............................................................................................................49

Table 24: Unused Interface Strapping ..............................................................................................................49

3 88F6281 Pin Map and Pin List ......................................... ... ... ... ............................................. ..........50

4 Pin Multiplexing ................................................................................................................................51

Table 25: MPP Functionality.............................................................................................................................52

Table 26: MPP Function Summary...................................................................................................................53

Table 27: Ethernet Ports Pins Multiplexing.......................................................................................................57

Table 28: TS Port Pin Multiplexing .................................................................................................................59

5 Clocking.............................................................................................................................................60

Table 29: 88F6281Clocks.................................................................................................................................60

Table 30: Supported Clock Combinations........................................................................................................61

6 System Power Up/Down and Reset Settings .................................................................................63

Table 31: I/O and Core Voltages......................................................................................................................63

Table 32: Reset Configuration..........................................................................................................................67

List of Tables

7 JTAG Interface ..................................................................................................................................73

Table 33: Supported JTAG Instructions............................................................................................................73

Table 34: IDCODE Register Map .....................................................................................................................74

8 Electrical Specifications (Preliminary) ...........................................................................................75

Table 35: Absolute Maximum Ratings..............................................................................................................75

Table 36: Recommended Operating Conditions...............................................................................................77

Table 37: Thermal Power Dissipation...............................................................................................................79

Table 38: Current Consumption........................................................................................................................80

Table 39: General 3.3V Interface (CMOS) DC Electrical Specifications...........................................................81

Table 40: RGMII 1.8V Interface (CMOS) DC Electrical Specifications.............................................................82

Table 41: SDRAM DDR2 Interface DC Electrical Specifications......................................................................83

Table 42: TWSI Interface 3.3V DC Electrical Specifications.............................................................................84

Table 43: SPI Interface 3.3V DC Electrical Specifications................................................................................84

Table 44: TDM Interface 3.3V DC Electrical Specifications..............................................................................85

Table 45: Reference Clock AC Timing Specifications ......................................................................................86

Table 46: SDRAM DDR2 Interface AC Timing Table .......................................................................................88

Table 47: SDRAM DDR2 Interface Address Timing Table...............................................................................89

Table 48: SDRAM DDR2 Clock Specifications.................................................................................................90

Table 49: RGMII 10/100/1000 AC Timing Table at 1.8V ..................................................................................93

Table 50: RGMII 10/100 AC Timing Table at 3.3V...........................................................................................93

Table 51: GMII AC Timing Table......................................................................................................................95

Table 52: MII/MMII MAC Mode AC Timing Table.............................................................................................97

Table 53: SMI Master Mode AC Timing Table..................................................................................................99

Table 54: JTAG Interface AC Timing Table....................................................................................................101

Table 55: TWSI Master AC Timing Table.......................................................................................................103

Table 56: TWSI Slave AC Timing Table.........................................................................................................103

Table 57: S/PDIF AC Timing Table ................................................................................................................105

Table 58: Inter-IC Sound (I2S) AC Timing Table............................................................................................107

Table 59: TDM Interface AC Timing Table .....................................................................................................109

Table 60: SPI (Master Mode) AC Timing Table..............................................................................................111

Table 61: SDIO Host in High Speed Mode AC Timing Table .........................................................................113

Table 62: Transport Stream Output Interface AC Timing Table ....................................................................115

Table 63: Transport Stream Input Interface AC Timing Table........................................................................115

Table 64: PCI Express Interface Differential Reference Clock Characteristics ..............................................118

Table 65: PCI Express Interface Spread Spectrum Requirements.................................................................119

Table 66: PCI Express Interface Driver and Receiver Characteristics ...........................................................120

Table 67: SATA-I Interface Gen1i Mode Driver and Receiver Characteristics...............................................123

Table 68: SATA-II Interface Gen2i Mode Driver and Receive

Table 69: USB Low Speed Driver and Receiver Characteristics....................................................................125

Table 70: USB Full Speed Driver and Receiver Characteristics.....................................................................126

Table 71: USB High Speed Driver and Receiver Characteristics...................................................................127

r Ch

aracteristics..............................................124

9 Thermal Data (Preliminary)............................................................................................................129

Table 72: Thermal Data for the 88F6281 in the BGA 19 x 19 mm Package (Preliminary) .............................129

88F6281 Hardware Specifications

10 Package ...........................................................................................................................................130

Table 73: HSBGA 288-pin Package Dimensions ...........................................................................................131

11 Part Order Numbering/Package Marking......................................................................................132

Table 74: 88F6281 Part Order Options ..........................................................................................................132

A Revision History .............................................................................................................................134

Table 75: Revision History..............................................................................................................................134

List of Figures

1 Pin and Signal Descriptions ........................................................................................................... 17

Figure 1: 88F6281 Pin Logic Diagram ............................................................................................................18

2 Unused Interface Strapping............................................................................................................ 49

3 88F6281 Pin Map and Pin List ......................................... ... ... ... ............................................. ......... 50

4 Pin Multiplexing ............................................................................................................................... 51

5 Clocking............................................................................................................................................ 60

6 System Power Up/Down and Reset Settings ................................................................................ 63

Figure 2: Power-Up Sequence Example..........................................................................................................64

Figure 3: Serial ROM Data Structure ...............................................................................................................70

Figure 4: Serial ROM Read Example...............................................................................................................71

7 JTAG Interface ................................................................................................................................. 73

8 Electrical Specifications (Preliminary) .......................................................................................... 75

Figure 5: SDRAM DDR2 Interface Test Circuit................................................................................................91

Figure 6: SDRAM DDR2 Interface Write AC Timing Diagram .........................................................................91

Figure 7: SDRAM DDR2 Interface Address and Control AC Timing Diagram.................................................92

Figure 8: SDRAM DDR2 Interface Read AC Timing Diagram.........................................................................92

Figure 9: RGMII Test Circuit ................. ... ... .....................................................................................................94

Figure 10: RGMII AC Timing Diagram...............................................................................................................94

Figure 11: GMII Test Circuit...............................................................................................................................95

Figure 12: GMII Output AC Timing Diagram............................................. ... ......................................................96

Figure 13: GMII Input AC Timing Diagram.........................................................................................................96

Figure 14: MII/MMII MAC Mode Test Circuit......................................................................................................97

Figure 15: MII/MMII MAC Mode Output Delay AC Timing Diagram...................................................................97

Figure 16: MII/MMII MAC Mode Input AC Timing Diagram................................................................................98

Figure 17: MDIO Master Mode Test Circuit.......................................................................................................99

Figure 18: MDC Master Mode Test Circuit ......................................................................................................100

Figure 19: SMI Master Mode Output AC Timing Diagram...............................................................................100

Figure 20: SMI Master Mode Input AC Timing Diagram..................................................................................100

Figure 21: JTAG Interface Test Circuit ............................................................................................................101

Figure 22: JTAG Interface Output Delay AC Timing Diagram .........................................................................102

Figure 23: JTAG Interface Input AC Timing Diagram ......................................................................................102

Figure 24: TWSI Test Circuit............................................................................................................................104

Figure 25: TWSI Output Delay AC Timing Diagram.........................................................................................104

Figure 26: TWSI Input AC Timing Diagram .....................................................................................................104

Figure 27: S/PDIF Test Circuit............................................................. ... .. ................................ .......................106

88F6281 Hardware Specifications

Figure 28: Inter-IC Sound (I2S) Test Circuit ....................................................................................................107

Figure 29: Inter-IC Sound (I2S) Output Delay AC Timing Diagram .................................................................108

Figure 30: Inter-IC Sound (I2S) Input AC Timing Diagram ..............................................................................108

Figure 31: TDM Interface Test Circuit..............................................................................................................109

Figure 32: TDM Interface Output Delay AC Timing Diagram...........................................................................110

Figure 33: TDM Interface Input Delay AC Timing Diagram..............................................................................110

Figure 34: SPI (Master Mode) Test Circuit ......................................................................................................111

Figure 35: SPI (Master Mode) Output AC Timing Diagram .............................................................................112

Figure 36: SPI (Master Mode) Input AC Timing Diagram ................................................................................112

Figure 37: Secure Digital Input/Output (SDIO) Test Circuit.............................................................................113

Figure 38: SDIO Host in High Speed Mode Output AC Timing Diagram.........................................................114

Figure 39: SDIO Host in High Speed Mode Input AC Timing Diagram............................................................114

Figure 40: Transport Stream Interface Test Circuit..........................................................................................116

Figure 41: Transport Stream Output Interface AC Timing Diagram ................................................................116

Figure 42: Transport Stream Input Interface AC Timing Diagram ...................................................................117

Figure 43: PCI Express Interface Test Circuit..................................................................................................121

Figure 44: Low/Full Speed Data Signal Rise and Fall Time ............................................................................127

Figure 45: High Speed TX Eye Diagram Pattern Template............................ ... ... ...........................................128

Figure 46: High Speed RX Eye Diagram Pattern Template.............................................................................128

9 Thermal Data (Preliminary)........................................................................................................... 129

10 Package .......................................................................................................................................... 130

Figure 47: HSBGA 288-pin Package and Dimensions ...................................................................................130

11 Part Order Numbering/Package Marking..................................................................................... 132

Figure 48: Sample Part Number......................................................................................................................132

Figure 49: Commercial Package Marking and Pin 1 Location.........................................................................133

Preface

About this Document

This datasheet provides the hardware specifications for the 88F6281 integrated controller. The hardware specifications include detailed pin information, configuration settings, electrical characteristics and physical specifications.

This datasheet is intended to be the basic source of information for designers of new systems. In this document, the “88F6281” is often referred to as the “device”.

1 Pin and Signal Descriptions

This section provides the pin logic diagram for the 88F6281 device and a detailed description of the pin assignments and their functionality.

Pin and Signal Descriptions

Misc.

REF_CLK_XIN

Power

XOUT

SYSRSTn

USB

USB_DM

USB_DP

Gigabit Ethernet

GE_TXCLKOUT

GE_TXCTL

GE_TXD[3 :0 ]

GE_RXD [3:0 ] GE_RXCTL GE_RXCLK GE_MDC GE_MDIO

SDRAM

M_CLKOUT M_CLKOUTn M_CKE M_RASn M_CASn M_WEn M_A[14:0] M_BA[2:0] M_CSn[3:0] M_DQ[15:0] M_DQS[1:0] M_DQS n[1:0 ]

M_STARTBURST M_STARTBURST_IN M_PCAL M_NCAL

M_DM[1:0] M_ODT[1:0]

RTC

RTC_XIN

RTC_XOUT

SATA0/1

SATA0_T_P

SATA0_R_P SATA0_R_N

SATA0_T_N

SATA1_T_P SATA1_T_N SATA1_R_P SATA1_R_N

JTAG

JT_CLK

JT_TDI

JT_TDO

JT_TMS_CORE

JT_RSTn

JT_TMS_CPU

NAND Flash

NF_CLE NF_ALE NF_CEn NF_REn

NF_WEn

NF_IO[7:0]

MPP

MPP[49:0]

RESERVED

ISET

MRn

CPU_PLL_AVDD

CORE_PLL_AVDD

XTAL_AVDD

SATA0_AVDD SATA1_AVDD

CPU_PLL_AVSS

CORE_PLL_AVSS

XTAL_AVSS

VDD_M

VSS

VDDO

VDD_CPU

VDD

VDD_GE_A

PEX_AVDD

RTC_AVDD

USB_AVDD

SSCG_AVDD

SSCG_AVSS

RTC_AVSS

VHV

PCI Express

PEX_TX_P PEX_TX_N PEX_RX_P PEX_RX_N PEX_ISET

PEX_CLK_N

PEX_CLK_P

VDD_GE_B

88F6281 Hardware Specifications

1.1 Pin Logic

Figure 1: 88F6281 Pin Logic Diagram

NOTE: The GE_TXCLKOUT pin is an input only when used as the MII/MMII Transmit Clock.

For details about MPP configuration options see Section 4.1, Multi-Purpose Pins Functional

Summary, onpage 51.

1.2 Pin Descriptions

This section details all the pins for the different interfaces providing a functional description of each pin and pin attributes.

Table 1<Default ¬¹ Font> defines the abbreviations and acronyms used in the pin description tables.

Table 1: Pin Functions and Assignments Table Key

Term Definition

[n] n - Represents the SERDES pair number <n> Represents port number when there are more than one ports Analog Analog Driver/Receiver or Power Supply Calib Calibration pad type CML Common Mode Logic CMOS Complementary Metal-Oxide-Semiconductor DDR Double Data Rate GND Ground Supply HCSL High-speed Current Steering Logic I Input I/O Input/Output O Output o/d Open Drain pin

The pin allows multiple drivers simultaneously (wire-OR conn ection).

A pull-up is required to sustain the inactive value. Power VDD Power Supply SSTL Stub Series Terminated Logic for 1.8V t/s Tri-State pin XXXn n - Suffix represents an Active Low Signal

Pin and Signal Descriptions

Pin Descriptions

Table 2: Interface Pin Prefix Codes

Interface Prefix

Misc N/A DDR SDRAM M_ PCI Express PEX_ SATA SATA0_

SATA1_ Gigabit Ethernet GE_ USB 2.0 USB_ JTAG JT_

88F6281 Hardware Specifications

Table 2: Interface Pin Prefix Codes (Continued)

Interface Prefix

RTC RTC_ NAND Flash NF_ MPP N/A TWSI TW_ UART UA0_

UA1_ Audio AU_ SPI SPI_ SDIO SD_ TDM TDM_ PTP PTP_

1.2.1 Power Supply Pins

Table 3 provides the voltage levels for the various interface pins. These do not include the analog

power supplies for the PLLs or PHYs which are explicitly mentioned in the other pin description tables.

Table 3: Power Pin Assignments

Pin and Signal Descriptions

Pin Descriptions

Pin Name I/O Pin

Description

Type

VDD I Power 1.0V Digital core voltage VDD_CPU I Power 1.1V Digital CPU voltage VDDO I Power 3.3V I/O power for MPP[49:36],MPP[19:0] and JTAG pins VDD_GE_A I Power 1.8V or 3.3V I/O supply voltage for RGMII and SMI interfaces

3.3V I/O supply voltage for GMII, MII/MMII, and SMI interfaces

VDD_GE_B I Power I/O power for MPP[35:20]

1.8V or 3.3V I/O supply voltage for RGMII interfaces

3.3V I/O supply voltage for GMII and MII/MMII interfaces

VDD_M I Power 1.8V I/O supply voltage for the DDR2 SDRAM interface VSS I GND VSS CPU_PLL_AVDD I Power 1.8V analog quiet power to CPU PLL

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide

for power supply filtering recommendations.

CPU_PLL_AVSS I GND CPU PLL ground CORE_PLL_AVDD I Power 1.8V analog quiet power to Core PLL

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendations.

CORE_PLL_AVSS I GND Core PLL ground SSCG_AVDD I Power 1.8V quiet power supply to the internal Spread Spectrum Clock

Generator SSCG_AVSS I GND Ground for the internal Spread Spectrum Clock Generator XTAL_ AVDD I Power 1.8V analog quiet power to on-chip clock inverter for supporting external

crystal, and on-chip current reference for SATA and USB PHYs

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendations.

XTAL_ A VSS I GND Ground for supporting external crystal, and on-chip current reference for

SATA and USB PHYs VHV I Power I/O supply voltage for eFuse:

• 2.5V for eFuse burning only

• 1.0V for eFuse reading only

88F6281 Hardware Specifications

Table 3: Power Pin Assignments (Continued)

Pin Name I/O Pin

Description

Type

PEX_AVDD I Power PCI Express PHY quiet power supply 1.8V

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendations.

SATA0_AVDD SATA1_AVDD

I Power SATA II port0/1 quiet 3.3V power supply

NOTE: See 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide

for power supply filtering recommendation.

USB_AVDD I Power USB 2.0 PHY quiet 3.3V power supply

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendation.

RTC_AVDD I Power 1.5V (via battery) or 1.8V (via the board) RTC interface voltage RTC_AVSS I GND RTC ground

1.2.2 Miscellaneous Pin Assignment

The Miscellaneous signal list contains clock and reset, test, and related signals.

Table 4: Miscellaneous Pin Assignments

Pin and Signal Descriptions

Pin Descriptions

Pin Name I/O Pin

Type

Power Rail

Description

REF_CLK_XIN I Analog XTAL_AVDD Reference clock input from external oscillator or input from

external crystal. Used as input to core , CPU, SATA, and USB PLLs.

XOUT O Analog XTAL_AVDD XTAL_OUT

Feedback signal to external crystal. When not used, leave this pin floating.

SYSRSTn I CMOS VDDO System reset

Main reset signal of the device clock. Used to reset all units to their initial state. When in the reset state, most output pins are in Tri-State.

SYSRST_OUTn O CMOS VDDO Reset request from the device to the board reset logic.

This pin is multiplexed on the MPP pins (see Section 4, Pin

Multiplexing, on page 51).

PEX_RST_OUTn O CMOS VDDO Optional PCI Express Endpoint card reset output

This pin is multiplexed on the MPP pins (see Section 4, Pin

Multiplexing, on page 51).

TP O Analog Analog Test Point for SATA, USB, and PCI Express

interfaces For internal use. Leave this pin unconnected.

ISET I Analog Current reference for both the USB and SATA PHYs.

Terminate this pin with a 6.04 k

Ω resistor, pulled down.

MRn I CMOS VDD_GE_A Active-Low, Manual Reset Input

SYSRST_OUTn is asserted low as long as the MRn input signal is asserted low, and for additional 20 ms after MRn (manual reset) de-assertion This pin is internally pulled up.

RESERVED Reserved for Marvell

¬Æ

future usage.

Leave unconnected externally.

NC Reserved for Marvell

¬Æ

future usage.

Leave unconnected externally.

88F6281 Hardware Specifications

1.2.3 DDR SDRAM Interface Pin Assignments

Table 5: DDR SDRAM Interface Pin Assignments

Pin Name I/O Pin

Type

M_CLKOUT

O SSTL VDD_M SDRAM Differential Clock Pair

Power Rail

Description

M_CLKOUTn M_CKE O SSTL VDD_M Driven high to enable SDRAM clock.

Driven low when setting the SDRAM to Self-refresh mode.

M_RASn O SSTL VDD_M SDRAM Row Address Select

Asserted to indicate an active ROW address driven on the SDRAM address lines.

M_CASn O SSTL VDD_M SDRAM Column Address Select

Asserted to indicate an active column address driven on the SDRAM address lines.

M_WEn O SSTL VDD_M SDRAM Write Enable

Asserted to indicate a write command to the SDRAM.

M_A[14:0] O SSTL VDD_M SDRAM Address

Driven with M_BA[2:0] during RASn and CASn cycles to generate the SDRAM address.

M_BA[2:0] O SSTL VDD_M Driven during M_RASn and M_CASn cycles to select one of

the eight SDRAM virtual banks. NOTE: If an SDRAM device does not support the BA[2] pin,

leave the M_BA[2] unconnected.

M_CSn[3:0] O SSTL VDD_M SDRAM Chip Selects

Asserted to select a specific SDRAM Physical bank.

M_DQ[15:0] t/s

SSTL VDD_M SDRAM Data Bus

I/O

Driven during write. Driven by SDRAM during reads.

M_DQS[1:0], M_DQSn[1:0]

t/s

SSTL VDD_M SDRAM Data Strobe

I/O

Driven by the 88F6281 during write. Driven by SDRAM during reads.

M_DM[1:0] O SSTL VDD_M SDRAM Data Mask

Asserted by the 88F6281 to select the specific byte out of the 16-bit data to be written to the SDRAM.

M_ODT[1:0] O SSTL VDD_M SDRAM On Die Termination control

Driven high to connect the SDRAM on die termination. Driven low to disconnect the SDRAM’s termination.

NOTE: For the recommended setting, refer to the 88F6180,

88F6190, 88F6192, and 88F6281 Design Guide.

Table 5: DDR SDRAM Interface Pin Assignments (Continued)

Pin and Signal Descriptions

Pin Descriptions

Pin Name I/O Pin

Type

Power Rail

Description

M_STARTBURST O SSTL VDD_M Start Burst

88F6281 indication of starting a burst read transaction. Asserted with the first M_CASn cycle of SDRAM access. NOTE: Must be routed on board to the SDRAM, and back to

the 88F6281 as M_STARTBURST_IN. For the recommended length calculation for this routing and termination requirements, see the 8 8F6180, 88F619 0, 88F6192, and 88F6281 Design Guide.

M_START

I SSTL VDD_M Start Burst Input

BURST_IN M_PCAL I Calib SDRAM interface P channel output driver calibration. Connect

to VSS through a resistor. The resistor value can vary between 30–70 ohm.

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281

Design Guide for the recommended values of the

calibration resistors.

M_NCAL I Calib SDRAM interface N channel output driver calibration. Connect

to M_VDD through a resistor. The resistor value can vary between 30–70 ohm.

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281

Design Guide for the recommended values of the

calibration resistors.

88F6281 Hardware Specifications

1.2.4 PCI Express Interface Pin Assignments

Table 6: PCI Express Interface Pin Assignments

Pin Name I/O Pin

Type

Power Rail

Description

PEX_CLK_P/N I/O HCSL PEX_AVDD PCI Express Reference Clock

100 MHz, differential This clock can be configured as input or output according to the reset strap (see Table 32, Reset Configuration, on page 67). NOTE: For Output mode, 50-ohm, pull-down resistors are

required.

PEX_TX_P/N O CML PEX_AVDD Transmit Lane

Differential pair of PCI Express transmit data

PEX_RX_P/N I CML PEX_AVDD Receive Lane

Differential pair of PCI Express receive data

PEX_ISET I Analog Current reference. Pull down to VSS through a 5 k

See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for the recommended resistor value.

Ω resistor .

1.2.5 SATA Interface Pin Assignments

Table 7: SATA Port Interface Pin Assignment

Pin and Signal Descriptions

Pin Descriptions

Pin Name I/O Pin

Type

SATA0_T_P/N

O CML SATA0/1_AVDD Transmit Data: Differential analog output of SATA II

SATA1_T_P/N SATA0_R_P/N

I CML SATA0/1_AVDD Receive Data: Differential analog input of SATA II port0/1

SATA1_R_P/N SATA0_PRESENTn

O CMOS VDDO/

SATA1_PRESENTn

SATA0_ACTn

O CMOS VDDO/

SATA1_ACTn

Power Rail Description

port0/1

When this signal is asserted there is an active link

VDD_GE_B

between the SATA II port and the external device (disk). NOTE: These signals are multiplexed on the MPP pins

(see Section 4, Pin Multiplexing, on page 51).

When this signal is asserted, there is an active and used

VDD_GE_B

link between the SATA II port and the external device (disk). NOTE: These signals are multiplexed on the MPP pins

(see Section 4, Pin Multiplexing, on page 51).

88F6281 Hardware Specifications

1.2.6 Gigabit Ethernet Port Interface Pin Assignments

For additional information about the Gigabit Ethernet port pin functions refer to Section 4.2, Gigabit

Ethernet (GbE) Pins Multiplexing on MPP, on page 57.

Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments

Pin Name I/O Pin

Type

Power Rail

Description

Port0—Dedicated GbE Pins

GE_TXCLKOUT t/s OCMOS VDD_GE_A RGMII Transmit Clock

RGMII transmit reference output clock for GE_TXD[3:0] and GE_TXCTL. Provides 125 MHz, 25 MHz or 2.5 MHz clock. Not used in MII/MMII mode.

I MII/MMII Transmit Clock

MII/MMII transmit reference clock fro m PHY. Provides the timing reference for the transmission of the MII transmit clock, transmit enable, and GE_TXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

t/s O

GMII Transmit Clock Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz.

GE_TXD[3:0] t/s OCMOS VDD_GE_A RGMII Transmit Data

Contains the transmit data nibble outp ut s that run at doubl e dat a rate with bits [3:0] driven on the rising edge of GE_TXCLKOUT and bits [7:4] driven on the falling edge.

MII/MMII Transmit Data Contains the transmit data nibble outputs that are synchronous to the transmit clock input.

GMII Transmit Data Contains the transmit data nibble outputs.

GE_TXCTL t/s OCMOS VDD_GE_A RGMII Transmit Control

Transmit control synchronous to the GE_TXCLKOUT output rising/falling edge. GE_TXEN is driven on the rising edge of GE_TXCLKOUT. A logical derivative of transmit enable and transmit error is driven on the falling edge of GE_TXCLKOUT.

MII/MMII Transmit Enable Indicates that the packet is being transmitted to the PH Y. It Is synchronous to transmit clock.

GMII Transmit Enable Indicates that the packet is being transmitted to the PH Y. It Is synchronous to GE_TXCLKOUT.

Pin and Signal Descriptions

Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)

Pin Descriptions

Pin Name I/O Pin

Type

Power Rail

Description

GE_RXD[3:0] I CMOS VDD_GE_A RGMII Receive Data

Contains the receive data nibble inputs that are synchronous to GE_RXCLK input rising/falling edge.

MII/MMII Receive Data Contains the receive data nibble inputs that are synchronous to GE_RXCLK input.

GMII Receive Data Contains the receive data nibble inputs.

GE_RXCTL I CMOS VDD_GE_A RGMII Receive Control

GE_RXCTL is presented on the rising edge of GE_RXCLK. A logical derivative of receive data vali d and receive d ata error is presented on the falling edge of RXCLK.

MII/MMII Receive Data Valid GMII Receive Data Valid.

GE_RXCLK I CMOS VDD_GE_A RGMII Receive Clock

The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock derived from the received data stream.

MII/MMII Receive Clock Provides the timing reference for the reception of the receive data valid, receive error, and GE_RXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

GMII Receive Clock Provides the timing reference for the reception of the GE_RXDV, receive error and receive data signals. This clock operates at 125 MHz

Port1—Multiplexed GbE Pins

MPP[23:20]/ GE1[3:0]

t/s OCMOS VDD_GE_B RGMII Transmit Data

Contains the transmit data nibble outp ut s that run at doubl e dat a rate with bits [3:0] presented on the rising edge of GE_TXCLKOUT and bits [7:4] presented on the falling edge.

MII/MMII Transmit Data Contains the transmit data nibble outputs that are synchronous to the transmit clock input.

GMII Transmit Data Contains the transmit data nibble outputs.

88F6281 Hardware Specifications

Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)

Pin Name I/O Pin

Type

MPP[27:24]/

I CMOS VDD_GE_B RGMII Receive Data

GE1[7:4]

Power Rail

Description

Contains the receive data nibble inputs that are synchronous to GE_RXCLK input rising/falling edge.

MII/MMII Receive Data Contains the receive data nibble inputs that are synchronous to GE_RXCLK input.

GMII Receive Data Contains the receive data nibble inputs.

MPP[28]/GE1[8] I CMOS VDD_GE _ B MII/MMII Coll ision Det e ct

Indicates a collision has been detected on the wire. This input is ignored in full-duplex mode. Collision detect is not synchronous to any clock.

GMII Collision Detect

MPP[29]/GE1[9] I CMOS VDD_GE _B MII/MMII Transmit Clock

t/s O

GMII Transmit Clock Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz.

MPP[30]/GE1[10] I CMOS VDD_GE_B RGMII Receive Control

GE_RXCTL is presented on the rising edge of GE_RXCLK. A logical derivative of receive data vali d and receive d ata error is presented on the falling edge of RXCLK.

MII/MMII Receive Data Valid GMII Receive Error

MPP[31]/GE1[11] I CMOS VDD_GE_B RGMII Receive Clock

The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock derived from the received data stream.

MII/MMII Receive Clock Provides the timing reference for the reception of the receive data valid, receive error, and GE_RXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

+ 110 hidden pages

Marvel Group 88F6281 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Cover

PRODUCT OVERVIEW

FEATURES

Table of Contents

List of Tables

List of Figures

Preface

1 Pin and Signal Descriptions

1.1 Pin Logic

1.2 Pin Descriptions

1.2.1 Power Supply Pins

1.2.2 Miscellaneous Pin Assignment

1.2.3 DDR SDRAM Interface Pin Assignments

1.2.4 PCI Express Interface Pin Assignments

1.2.5 SATA Interface Pin Assignments

1.2.6 Gigabit Ethernet Port Interface Pin Assignments