Manley Labs PSD User Manual

µ

PSD

It’s All You Need.

Feb 2003 www.st.com/micropsd

1

ST’s New 8051--

ST’s New 8051

!

W

E

N

E

Q303

µPSD

Turbo

Performance

8051 World

ST5

NOW

8051 World

µPSD

-

8

ST7

m

o

C

m

S

t

s

y

ST6

S

i

m

p

F

u

i

d

e

M

l

o

r

t

n

o

C

e

l

n

u

s

n

o

i

t

c

based MCU Family

ST40 &

STPC

t

i

b

-

2

3

r

o

f

r

e

S

e

t

s

y

)

.

P

h

g

i

H

t

s

n

,

n

a

n

h

C

…

l

e

s

b

e

p

m

ST10

t

i

b

-

6

1

ST9

t

i

y

t

i

x

e

l

s

c

i

l

p

A

p

r

M

(

o

m

e

t

x

E

o

i

t

a

O

,

I

/

y

1

e

m

i

T

-

l

a

e s

q

m

g

n

i

s

e

m

e

r

i

u

t

a

i

n

o

i

n

u

c

R

e

v

i

s

P

C

r

R

o

c

m

e

n

,

s

m

e

c

n

a

s

www.st.com/micropsd

2

What is

• Standard 8032 MCU Core

– (3) 16 bit timers

µ

PSD

µ

PSD

?

– (2) Ext Interrupts

• Large Dual Bank Flash

• Large SRAM

• Programmable Logic

• USB, Dual UARTs, I2C

• PWM, ADC, DDC

• Many I/O

• Built-in Supervisor

8032

CORE:

w/UART&

WDOG TMR

DECODE &

MEM MNGR

MEM MNG R

JTAG ISP

PROGRAMMABLE

Vcc

PWR

MNG

Vcc

MON

2K, 8K, or

32K Byte SRAM

64K, 128K, or

256K Byte

MAIN FLASH

16K or 32K Byte

nd

FLASH

DDC

LOGIC

ADC

2

I2C

I/O

PWM

USB

1.1

nd

2

UART

• ISP

– In-System Programming

• IAP

– In-Application Programming

www.st.com/micropsd

Just add power

and crystal!

3

What makes

• PSD Architecture … enhances capability of 8051

– PSD = Programmable System Device – Dual bank Flash Memory … Superior IAP – Memory Management … Seamless paging and memory placement – Programmable Logic … Consolidate external logic chips – JTAG ISP … perfect for lab and manufacturing

• Some µPSDs have Big Memory up to 288K bytes…

When is larger Flash and SRAM needed?

– The use of C language

µ

PSD

µ

PSD

different?

– Elaborate user interfaces … menus, graphics, screens – Multiple languages and fonts, data tables – Faster data transfers – Data recording

• Low Cost

– Save $ compared to other 8051 and 8-bit MCU devices with

www.st.com/micropsd

larger SRAM and Flash Memories

4

Unique

• Excellent Memory Management

• Flexible Memory Allocation

• Remote Field Updates

• JTAG In System Programming

µ

PSD

µ

PSD

features

www.st.com/micropsd

• Programmable Logic

PSD

Architecture !!!

5

Excellent Memory Management

• Built-in Address Decoding PLD

– Map any µPSD memory sector to any address – Easily convert existing 8051 designs into µPSD – Total memory mapping flexibility for new designs

8032

MCU

• Memory Paging is Easy using Decode PLD

– Break traditional 8051 64K Byte address limit imposed by only 16 address lines – 8-bit page register is built into Decode PLD … it’s like having 8 more address lines – Paging (or banking) is directly supported by most 8051 C compilers

FFFF

Page 0

Page 1

Page 2

Address

Page 3

Page

Register

DECODE

PLD

Sector

Selects

Sector

Selects

SRAM

MAIN FLASH

MA I N FLAS H

MAIN FLASH

nd

FLASH

2

FLASH

2

2ndFLASH

Page 7

1

Sector

8

Sectors

4

Sectors

64K

0000

www.st.com/micropsd

32K Main

Flash

32K Main

Flash

Map here: SRAM, 2ndFlash, I/O, etc

32K Main

Flash

32K Main

Flash

Common to All Pages

32K Main

Flash

6

Flexible Memory Allocation

• 8051 Architecture uses a separate address space for code and for data

• Allocate dual banks of Flash to meet A pplicat ion De mands

– The Decode PLD controls where Flash memory resides

• You decide how to split the Flash memory

Can use

EEPROM

Emulation

Big Code

(complex

algorithms)

nd

FLASH

2

FLASH

2

FLASH

2

DATA

MAIN FLASH

CODE

-OR -

Big Data

(printers, big

GUI, tables)

nd

FLASH

2

FLASH

2

FLASH

2

CODE

MAIN FLASH

DATA

-OR -

All Code

(like typical

flash 8051s)

nd

FLASH

2

FLASH

2

FLASH

2

CODE

MAIN FLASH

CODE

www.st.com/micropsd

7

Remote Field Updates with IAP

1. Before IAP

READ &

WRITE

8032

MCU

READ

READ ONLY

ONLY

• MCU reading program from Main Flash

Updated

Program

nd

2

Flash

2

Flash

DATA

MAIN

FLASH

OLD

CODE

USB, UART,

2

I

C, Modem…

• 8051s typically cannot write to “code” space

– Special µPSD register eliminates this limitation

• Typical Flash memory cannot be read and written

at the same time

– Dual Banks of Flash eliminate this limitation – Read program from one bank while writing to the other bank

2. During IAP

READ &

WRITE

READ

READ ONLY

ONLY

8032

MCU

ONLY

READ &

WRITE

READ

READ ONLY

ONLY

• Special Register temporarily reclassifies Main Flash as Data

• MCU now reads IAP program from 2ndFlash while receiving bytes of new program from USB, UART, Modem, I2C, etc. and writes the new program to Main Flash

nd

Flash

2

Flash

2

CODE

MAIN

FLASH

TREAT

AS DATA

• Special Register classifies Main Flash as Code again

• MCU now reading new program from Main Fla sh

3. After IAP

READ &

WRITE

8032

MCU

WRITE

READ

READ ONLY

ONLY

nd

Flash

2

Flash

2

DATA

MAIN

FLASH

NEW

CODE

www.st.com/micropsd

8

In--

In

• Program blank device, no interaction of 8032 MCU required

• Entire chip programs in 10-25 seconds

• JTAG serial connection is industry standard

• Speedy lab development and manufacturing

System Programming (ISP)

µ

PSD

µ

PSD

µ

PSD

µ

PSD

g

n

E

a

h

C

n

No soc kets or

pre-programmed

parts needed

g

n

i

r

e

n

i

O

e

g

r

e

d

r

Last minute

www.st.com/micropsd

JIT

changes are

OK

Just-In-Time

Inventory

Management

9

Manley Labs PSD User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual