General Description
The MAX9316A is a low-skew, 1-to-5 differential driver
designed for clock and data distribution. This device
allows selection between two inputs: one differential
and one single ended. The selected input is reproduced at five differential outputs. The differential input
can be adapted to accept a single-ended input by connecting the on-chip VBBsupply to one input as a reference voltage.
The MAX9316A features low output-to-output skew
(20ps), making it ideal for clock and data distribution
across a backplane or board. For interfacing to differential HSTL and (LV)PECL signals, this device operates over
a 3.0V to 5.5V supply range, allowing high-performance
clock or data distribution in systems with a nominal 3.3V
or 5.0V supply. For differential (LV)ECL operation, this
device operates with a -3.0V to -5.5V supply.
The MAX9316A is offered in a 20-pin wide SO package.
Applications
Precision Clock Distribution
Low-Jitter Data Repeaters
Data and Clock Drivers and Buffers
Central-Office Backplane Clock Distribution
DSLAM Backplane
Base Stations
ATE
Features
♦ Guaranteed 400mV Differential Output at 1.5GHz
♦ Selectable Single-Ended or Differential Input
♦ 130ps (max) Part-to-Part Skew at +25°C
♦ 20ps Output-to-Output Skew
♦ 365ps Propagation Delay
♦ Synchronous Output Enable/Disable
♦ On-Chip Reference for Single-Ended Inputs
♦ Input Biased to Low when Open
♦ Pin Compatible with MC100EL14
MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2648; Rev 0; 10/02
EVALUATION KIT
AVAILABLE
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE
PIN-PACKAGE
MAX9316AEWP -40°C to +85°C 20 Wide SO
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
V
CC
EN
V
CC
N.C.Q1
Q1
Q0
QO
TOP VIEW
SCLK
CLK
CLK
V
BB
Q3
Q3
Q2
Q2
12
11
9
10
SEL
V
EE
Q4
Q4
MAX9316A
D
Q
WIDE SO
Pin Configuration
50Ω 50Ω
MAX9316A
ZO = 50Ω
Z
O
= 50Ω
RECEIVER
Q_
Q_
VTT = VCC - 2.0V
Typical Application Circuit
Functional Diagram appears at end of data sheet.
MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC- VEE= 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC- 2V, SEL = high or low, EN = low, unless otherwise noted. Typical
values are at V
CC
- VEE= 5.0V, V
IHD
= VCC- 1V, V
ILD
= VCC- 1.5V.) (Notes 1, 2, 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC- VEE...............................................................................6.0V
Single-Ended Inputs (SCLK, SEL, EN, CLK, CLK)
For V
CC
- VEE≤ 4.2V.........................VEE- 0.3V to VCC+ 0.3V
For V
CC
- VEE> 4.2V ........................VEE- 4.2V to VCC+ 0.3V
CLK to CLK ........................................................................±3.0V
Continuous Output Current .................................................50mA
Surge Output Current........................................................100mA
V
BB
Sink/Source Current ...............................................±0.65mA
Continuous Power Dissipation (T
A
= +70°C)
Single-Layer PC Board
20-Pin Wide SO (derate 10mW/°C above +70°C) ......800mW
Junction-to-Ambient Thermal Resistance in Still Air
Single-Layer PC Board
20-Pin Wide SO…...................................................+100°C/W
Junction-to-Ambient Thermal Resistance with
500LFPM Airflow
Single-Layer PC Board
20-Pin Wide SO….....................................................+58°C/W
Junction-to-Case Thermal Resistance
20-Pin Wide SO…......................................................+20°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (Inputs and Outputs) .........................2kV
Lead Temperature (soldering, 10s) .................................+300°C
-40°C
+25°C
+85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
SINGLE-ENDED INPUTS (SCLK, SEL, EN)
Input High Voltage
V
IH
VCC -
VCC -
VCC -
V
(VCC - VEE) ≤ 4.2
VCC -
VCC -
VCC -
Input Low Voltage V
IL
VCC -
VCC -
VCC -
VCC -
VCC -
VCC -
V
Input Current I
IN
V
IL(MIN), VIH(MAX)
µA
DIFFERENTIAL INPUTS (CLK, CLK)
Single-Ended Input
High Voltage
V
IH
CLK connected to
V
BB
, Figure 1
V
CC
-
VCC -
VCC -
V
CLK connected to
V
BB
, Figure 1
VCC -
VCC -
VCC -
Single-Ended Input
Low Voltage
V
IL
CLK connected to
V
BB
, Figure 1
VCC -
VCC -
VCC -
VCC -
VCC -
VCC -
V
High Voltage of
Differential Input
V
IHD
VEE +
VEE +
VEE +
V
Low Voltage of
Differential Input
V
ILD
VCC -
VCC -
VCC -
V
MIN TYP MAX MIN TYP MAX MIN TYP MAX
(VCC - VEE) > 4.2V
(VCC - VEE) ≤ 4.2V
(VCC - VEE) > 4.2V
1.095
V
EE
4.2
V
CC
1.495
1.495
1.125
V
EE
4.2
V
CC
1.495
1.495
1.125
V
EE
4.2
V
1.575
1.575
-300 +300 -300 +300 -300 +300
1.095
V
EE
4.2
1.2
V
EE
V
CC
1.495
1.495
V
CC
0.095
1.125
V
EE
4.2
1.2
V
EE
V
CC
1.495
1.495
V
CC
0.095
1.125
V
EE
4.2
1.2
V
EE
V
1.575
1.575
V
0.095
CC
CC
CC
MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC- VEE= 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC- 2V, SEL = high or low, EN = low, unless otherwise noted. Typical
values are at V
CC
- VEE= 5.0V, V
IHD
= VCC- 1V, V
ILD
= VCC- 1.5V.) (Notes 1, 2, 3)
-40°C
+25°C
+85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
Differential Input
Voltage
V
IHD
-
V
ILD
V
Input Current I
IN
µA
OUTPUTS (Q_, Q_)
Single-Ended
Output High
Voltage
V
OH
Figure 1
V
CC
-
VCC -
VCC -
VCC -
VCC -
VCC -
V
Single-Ended
Output Low
Voltage
V
OL
Figure 1
V
CC
-
VCC -
VCC -
VCC -
VCC -
VCC -
V
Differential Output
Voltage
VOH -
V
OL
Figure 1
mV
REFERENCE (VBB)
Reference Voltage
Output (Note 4)
V
BB
IBB = ±0.5mA
V
CC
-
VCC -
VCC -
VCC -
VCC -
VCC -
V
POWER SUPPLY
Supply Current
(Note 5)
I
EE
mA
VIH, VIL, V
MIN TYP MAX MIN TYP MAX MIN TYP MAX
0.095 3.0 0.095 3.0 0.095 3.0
IHD
, V
-300 +300 -300 +300 -300 +300
ILD
1.085
1.910
550 910 550 910 550 910
1.40
30 40 32 40 34 43
0.865
1.555
1.19
1.025
1.840
1.40
0.865
1.620
1.22
1.025
1.810
1.48
0.865
1.620
1.22
MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
4 _______________________________________________________________________________________
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at T
A
= +25°C and guaranteed by design over the full operating temperature range.
Note 4: Use V
BB
only for inputs that are on the same device as the VBBreference.
Note 5: All pins are open except V
CC
and VEE.
Note 6: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 7: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 8: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 9: Device jitter added to a jitter-free input signal.
AC ELECTRICAL CHARACTERISTICS
(VCC- VEE= 3.0V to 5.5V, outputs are loaded with 50Ω ±1% to VCC- 2V, input frequency ≤ 1.5GHz, input transition time = 125ps
(20% to 80%), SEL = high or low, EN = low, V
IHD
= VEE+ 1.2V to VCC, V
ILD
= VEEto VCC- 0.15V, V
IHD
- V
ILD
= 0.15V to 3V, unless
otherwise noted. Typical values are at V
CC
- VEE= 5.0V.) (Notes 1, 6)
PARAMETER
CONDITIONS
UNITS
CLK to Q_ Delay
(Differential)
t
PLHD1
,
Figure 2
ps
SCLK to Q_ Delay
t
PLHD3
,
VIL = VCC - 1.55V,
V
IH
= VCC - 1.09V,
Figure 3
ps
Output-to-Output
Skew (Note 7)
5
ps
Part-to-Part Skew
(Note 8)
ps
Added Random
Jitter (Note 9)
t
RJ
p s ( RM S )
Added
Deterministic Jitter
(Note 9)
t
DJ
1.5Gbps 2E
23
- 1
PRBS pattern
Ps
P-P
Switching
Frequency
f
MAX
( V
OH
- V OL)
≥ 400m V ,
Figure 2
GHz
Output Rise/Fall
Time (20% to 80%)
Figure 2
ps
SYMBOL
MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C +25°C +85°C
t
PHLD1
t
PHLD3
t
SKOO
t
SKPP
fIN = 1.5GHz clock 0.8 1.2 0.8 1.2 0.8 1.2
tR, t
F
290 400 310 440 300 520
290 400 310 440 300 520
30 20 40 20 50
110 130 220
50 70 50 70 50 70
1.5 1.5 1.5
80 120 90 130 90 145
MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
_______________________________________________________________________________________ 5
20
24
32
28
36
40
-40 10-15 35 60 85
SUPPLY CURRENT vs.TEMPERATURE
MAX9316A toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
ALL PINS ARE OPEN
EXCEPT V
CC
AND V
EE
0
200
100
500
400
300
800
700
600
900
0 1.00.5 1.5 2.0 2.5 3.0
DIFFERENTIAL OUTPUT VOLTAGE
(V
OH
- VOL) vs. FREQUENCY
MAX9316A toc02
FREQUENCY (GHz)
DIFFERENTIAL OUTPUT VOLTAGE (mV)
80
100
90
120
110
130
140
-40 10-15 35 60 85
TRANSITION TIME vs. TEMPERATURE
MAX9316A toc03
TEMPERATURE (°C)
TRANSITION TIME (ps)
t
R
t
F
320
340
380
360
400
420
-40 10-15 35 60 85
PROPAGATION DELAY vs. TEMPERATURE
MAX9316A toc05
TEMPERATURE (°C)
PROPAGATION DELAY (ps)
DIFFERENTIAL CLK
SCLK MEASUREMENT AT
V
IH
= 2.12V,
V
CC
= +1.82V
Typical Operating Characteristics
(VCC= 5.0V, V
IHD
= V
CC
- 1V, V
ILD
= V
CC
- 1.15V, input transition time = 125ps (20% to 80%), fIN= 1.5GHz, outputs loaded with
50Ω to (VCC- 2V), TA= +25°C, unless otherwise noted.)
MAX9316A
Detailed Description
The MAX9316A is a low-skew, 1-to-5 differential driver
designed for clock or data distribution. A 2-to-1 MUX
selects one of the two clock inputs, CLK, CLK and
SCLK. The CLK and CLK inputs are differential while the
SCLK is single ended. The MUX is switched by the single-ended SEL input. A logic low selects the CLK input
and a logic high selects the SCLK input. The SEL logic
threshold is set by the internal voltage reference VBB.
SEL input can be driven by VCCand VEEor by a singleended (LV)PECL/(LV)ECL signal. The selected input is
reproduced at five differential outputs, Q0 to Q4.
Synchronous Enable
The MAX9316A is synchronously enabled and disabled
with outputs in the low state to eliminate shortened
clock pulses. EN is connected to the input of an edgetriggered D flip-flop. After power-up, drive EN low and
toggle the selected clock input to enable the outputs.
The outputs are enabled on the falling edge of the
selected clock input after EN goes low. The outputs are
disabled to a low state on the falling edge of the selected clock input after EN goes high. The threshold for EN
is equal to VBB.
Power Supply
For interfacing to differential HSTL and (LV)PECL signals, the VCCrange is from 3.0 to 5.5V (with V
EE
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
6 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 Q0 Noninverting Q0 Output. Typically terminate with 50Ω resistor to (VCC - 2V).
2 Q0 Inverting Q0 Output. Typically terminate with 50Ω resistor to (VCC - 2V).
3 Q1 Noninverting Q1 Output. Typically terminate with 50Ω resistor to (VCC - 2V).
4 Q1 Inverting Q1 Output. Typically terminate with 50Ω resistor to (VCC - 2V).
5 Q2 Noninverting Q2 Output. Typically terminate with 50Ω resistor to (VCC - 2V).
6 Q2 Inverting Q2 Output. Typically terminate with 50Ω resistor to (VCC - 2V).
7 Q3 Noninverting Q3 Output. Typically terminate with 50Ω resistor to (VCC - 2V).
8 Q3 Inverting Q3 Output. Typically terminate with 50Ω resistor to (VCC - 2V).
9 Q4 Noninverting Q4 Output. Typically terminate with 50Ω resistor to (VCC - 2V).
10 Q4 Inverting Q4 Output. Typically terminate with 50Ω resistor to (VCC - 2V).
11 V
EE
Negative Supply Voltage
12 SEL
Clock Select Input (Single Ended). Drive low to select the CLK, CLK input. Drive high to select the
SCLK input. The SEL threshold is equal to V
BB
. Internal 30kΩ pulldown to VEE and 30kΩ pullup to
V
CC
.
13 V
BB
Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a
reference for single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to V
CC
;
otherwise, leave it unconnected.
14 CLK Inverting Differential Clock Input. Internal 45kΩ pullup to VCC and 45kΩ pulldown to VEE.
15 CLK Noninverting Differential Clock Input. Internal 30kΩ pulldown to VEE and 45kΩ pullup to VCC.
16 SCLK Single-Ended Clock Input. Internal 30kΩ pulldown to VEE and 45kΩ pullup to VCC.
17 N.C. Not Internally Connected. Solder to PC board for package thermal dissipation.
18, 20 V
CC
Positive Supply Voltage. Bypass VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
19 EN
Output Enable Input. Outputs are synchronously enabled on the falling edge of the clock input
when EN is low. Outputs are synchronously set to low on the falling edge of the clock input when
EN is high. Internal 30kΩ pulldown to V
EE
and 30kΩ pullup to VCC.
grounded), allowing high-performance clock or data
distribution in systems with a nominal 5.0V supply. For
interfacing to differential (LV)ECL, the VEErange is
-3.0V to -5.5V (with VCCgrounded). Output levels are
referenced to VCCand are considered (LV)PECL or
(LV)ECL, depending on the level of the VCCsupply.
With VCCconnected to a positive supply and VEEconnected to ground, the outputs are (LV)PECL. The outputs are (LV)ECL when VCCis connected to ground
and VEEis connected to a negative supply.
Input Bias Resistors
When the CLK and CLK inputs are open, the internal
bias resistors set the inputs to differential low state. The
inverting input (CLK) is biased with a 45kΩ pullup to
VCCand a 45kΩ pulldown to VEE. The noninverting
input (CLK) and SCLK are biased with a 45kΩ pullup to
VCCand a 30kΩ pulldown to VEE. The single-ended
inputs (SEL, EN) are each biased with a 30kΩ pulldown
to VEEand a 30kΩ pullup to VCC.
Differential Clock Input Limits
The maximum magnitude of the differential signal applied
to the differential clock input is 3.0V. This limit also
applies to the difference between any reference voltage
input and a single-ended input. Specifications for the high
and low voltages of a differential input (V
IHD
and V
ILD
)
and the differential input voltage (V
IHD
- V
ILD
) apply
simultaneously.
Single-Ended Clock Input and V
BB
The differential clock input can be configured to accept
a single-ended input. This is accomplished by connecting the on-chip reference voltage, VBB, to the inverting
or noninverting input of the differential input as a reference. For example, the differential CLK, CLK input is
converted to a noninverting, single-ended input by connecting VBBto CLK and connecting the single-ended
input signal to CLK. Similarly, an inverting configuration
is obtained by connecting VBBto CLK and connecting
the single-ended input to CLK. With a differential input
configured as single ended (using VBB), the singleended input can be driven to VCCand VEEor with a
single-ended (LV)PECL/(LV)ECL signal. Note that the
single-ended input must be least VBB±95mV or a differential input of at least 95mV to switch the outputs to
the V
OH
and VOLlevels specified in the DC Electrical
Characteristics table.
When using the VBBreference output, bypass it with a
0.01µF ceramic capacitor to VCC. If the VBBreference
is not used, leave it open. The VBBreference can
source or sink 0.5mA. Use VBBonly for an input that is
on the same device as the VBBreference.
Applications Information
Supply Bypassing
Bypass VCCto VEEwith high-frequency, surface-mount,
ceramic, 0.1µF and 0.01µF capacitors in parallel as
close to the device as possible, with the 0.01µF capacitor closest to the device. Use multiple parallel vias to
minimize parasitic inductance. When using the V
BB
reference output, bypass it with a 0.01µF ceramic capacitor to VCC(if the VBBreference is not used, it can be
left open).
Controlled-Impedance Traces
Input and output trace characteristics affect the performance of the MAX9316A. Connect input and output
signals with 50Ω characteristic impedance traces.
Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω
characteristic impedance through cables and connectors. Reduce skew within a differential pair by matching
the electrical length of the traces.
Output Termination
Terminate outputs with 50Ω to VCC- 2V or use an
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if Q0 is used as a single-ended
output, terminate both Q0 and Q0.
Chip Information
TRANSISTOR COUNT: 616
PROCESS: Bipolar
MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
_______________________________________________________________________________________ 7
MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
8 _______________________________________________________________________________________
CLK
Q_
V
OH
V
OL
V
IH
V
IL
V
BB
(CLK IS CONNECTED TO VBB)
VOH - V
OL
CLK
Q_
Figure 1. MAX9316A Switching Characteristics with Single-Ended Input
CLK
CLK
Q_
Q_
t
PLHD1
t
PHLD1
VOH - V
OL
V
IHD
- V
ILD
V
IHD
V
ILD
Q_ - Q_
0V (DIFFERENTIAL) 0V (DIFFERENTIAL)
20%
80%
20%
80%
t
R
t
F
V
OL
V
OH
Figure 2. MAX9316A Timing Diagram
MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
_______________________________________________________________________________________ 9
SCLK
Q_
Q_
Q_ - Q_
t
PLHD3
t
PHLD3
VOH - V
OL
V
IHD
V
ILD
0V (DIFFERENTIAL) 0V (DIFFERENTIAL)
20%
80%
20%
t
R
t
F
V
OL
V
OH
80%
Figure 3. MAX9316A Timing Diagram for SCLK
t
S
t
H
t
S
t
PLHD
OUTPUTS ARE LOW OUTPUTS STAY LOW
EN
SCLK OR CLK
CLK
Q_
Q_
Figure 4. MAX9316A ENTiming Diagram
MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
10 ______________________________________________________________________________________
Functional Diagram
MAX9316A
CLK
CLK
SCLK
SEL
EN
V
BB
V
CC
V
EE
V
EE
V
EE
V
EE
V
EE
V
CC
0
1
Q
D
30kΩ
45kΩ
45kΩ
V
CC
45kΩ
30kΩ
30kΩ
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
30kΩ
V
CC
45kΩ
V
CC
30kΩ
V
CC
30kΩ
MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
SOICW.EPS
PACKAGE OUTLINE, .300" SOIC
1
1
21-0042
B
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
TOP VIEW
FRONT VIEW
MAX
0.012
0.104
0.019
0.299
0.013
INCHES
0.291
0.009
E
C
DIM
0.014
0.004
B
A1
MIN
0.093A
0.23
7.40 7.60
0.32
MILLIMETERS
0.10
0.35
2.35
MIN
0.49
0.30
MAX
2.65
0.050
0.016L
0.40 1.27
0.5120.496D
D
MINDIM
D
INCHES
MAX
12.60 13.00
MILLIMETERS
MIN
MAX
20
AC
0.447 0.463 AB11.7511.35 18
0.398 0.413 AA10.5010.10 16
N MS013
SIDE VIEW
H 0.4190.394 10.00 10.65
e 0.050 1.27
D 0.6140.598 15.20 2415.60 AD
D 0.7130.697 17.70 2818.10 AE
H
E
N
D
A1
B
e
A
0-8
C
L
1
VARIATIONS:
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
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