General Description
The MAX9316A is a low-skew, 1-to-5 differential driver
designed for clock and data distribution. This device
allows selection between two inputs: one differential
and one single ended. The selected input is reproduced at five differential outputs. The differential input
can be adapted to accept a single-ended input by connecting the on-chip VBBsupply to one input as a reference voltage.
The MAX9316A features low output-to-output skew
(20ps), making it ideal for clock and data distribution
across a backplane or board. For interfacing to differential HSTL and (LV)PECL signals, this device operates over
a 3.0V to 5.5V supply range, allowing high-performance
clock or data distribution in systems with a nominal 3.3V
or 5.0V supply. For differential (LV)ECL operation, this
device operates with a -3.0V to -5.5V supply.
The MAX9316A is offered in a 20-pin wide SO package.
Applications
Precision Clock Distribution
Low-Jitter Data Repeaters
Data and Clock Drivers and Buffers
Central-Office Backplane Clock Distribution
DSLAM Backplane
Base Stations
ATE
Features
♦ Guaranteed 400mV Differential Output at 1.5GHz
♦ Selectable Single-Ended or Differential Input
♦ 130ps (max) Part-to-Part Skew at +25°C
♦ 20ps Output-to-Output Skew
♦ 365ps Propagation Delay
♦ Synchronous Output Enable/Disable
♦ On-Chip Reference for Single-Ended Inputs
♦ Input Biased to Low when Open
♦ Pin Compatible with MC100EL14
MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2648; Rev 0; 10/02
EVALUATION KIT
AVAILABLE
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE
PIN-PACKAGE
MAX9316AEWP -40°C to +85°C 20 Wide SO
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
V
CC
EN
V
CC
N.C.Q1
Q1
Q0
QO
TOP VIEW
SCLK
CLK
CLK
V
BB
Q3
Q3
Q2
Q2
12
11
9
10
SEL
V
EE
Q4
Q4
MAX9316A
D
Q
WIDE SO
Pin Configuration
50Ω 50Ω
MAX9316A
ZO = 50Ω
Z
O
= 50Ω
RECEIVER
Q_
Q_
VTT = VCC - 2.0V
Typical Application Circuit
Functional Diagram appears at end of data sheet.
MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC- VEE= 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC- 2V, SEL = high or low, EN = low, unless otherwise noted. Typical
values are at V
CC
- VEE= 5.0V, V
IHD
= VCC- 1V, V
ILD
= VCC- 1.5V.) (Notes 1, 2, 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC- VEE...............................................................................6.0V
Single-Ended Inputs (SCLK, SEL, EN, CLK, CLK)
For V
CC
- VEE≤ 4.2V.........................VEE- 0.3V to VCC+ 0.3V
For V
CC
- VEE> 4.2V ........................VEE- 4.2V to VCC+ 0.3V
CLK to CLK ........................................................................±3.0V
Continuous Output Current .................................................50mA
Surge Output Current........................................................100mA
V
BB
Sink/Source Current ...............................................±0.65mA
Continuous Power Dissipation (T
A
= +70°C)
Single-Layer PC Board
20-Pin Wide SO (derate 10mW/°C above +70°C) ......800mW
Junction-to-Ambient Thermal Resistance in Still Air
Single-Layer PC Board
20-Pin Wide SO…...................................................+100°C/W
Junction-to-Ambient Thermal Resistance with
500LFPM Airflow
Single-Layer PC Board
20-Pin Wide SO….....................................................+58°C/W
Junction-to-Case Thermal Resistance
20-Pin Wide SO…......................................................+20°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (Inputs and Outputs) .........................2kV
Lead Temperature (soldering, 10s) .................................+300°C
-40°C
+25°C
+85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
SINGLE-ENDED INPUTS (SCLK, SEL, EN)
Input High Voltage
V
IH
VCC -
VCC -
VCC -
V
(VCC - VEE) ≤ 4.2
VCC -
VCC -
VCC -
Input Low Voltage V
IL
VCC -
VCC -
VCC -
VCC -
VCC -
VCC -
V
Input Current I
IN
V
IL(MIN), VIH(MAX)
µA
DIFFERENTIAL INPUTS (CLK, CLK)
Single-Ended Input
High Voltage
V
IH
CLK connected to
V
BB
, Figure 1
V
CC
-
VCC -
VCC -
V
CLK connected to
V
BB
, Figure 1
VCC -
VCC -
VCC -
Single-Ended Input
Low Voltage
V
IL
CLK connected to
V
BB
, Figure 1
VCC -
VCC -
VCC -
VCC -
VCC -
VCC -
V
High Voltage of
Differential Input
V
IHD
VEE +
VEE +
VEE +
V
Low Voltage of
Differential Input
V
ILD
VCC -
VCC -
VCC -
V
MIN TYP MAX MIN TYP MAX MIN TYP MAX
(VCC - VEE) > 4.2V
(VCC - VEE) ≤ 4.2V
(VCC - VEE) > 4.2V
1.095
V
EE
4.2
V
CC
1.495
1.495
1.125
V
EE
4.2
V
CC
1.495
1.495
1.125
V
EE
4.2
V
1.575
1.575
-300 +300 -300 +300 -300 +300
1.095
V
EE
4.2
1.2
V
EE
V
CC
1.495
1.495
V
CC
0.095
1.125
V
EE
4.2
1.2
V
EE
V
CC
1.495
1.495
V
CC
0.095
1.125
V
EE
4.2
1.2
V
EE
V
1.575
1.575
V
0.095
CC
CC
CC
MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC- VEE= 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC- 2V, SEL = high or low, EN = low, unless otherwise noted. Typical
values are at V
CC
- VEE= 5.0V, V
IHD
= VCC- 1V, V
ILD
= VCC- 1.5V.) (Notes 1, 2, 3)
-40°C
+25°C
+85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
Differential Input
Voltage
V
IHD
-
V
ILD
V
Input Current I
IN
µA
OUTPUTS (Q_, Q_)
Single-Ended
Output High
Voltage
V
OH
Figure 1
V
CC
-
VCC -
VCC -
VCC -
VCC -
VCC -
V
Single-Ended
Output Low
Voltage
V
OL
Figure 1
V
CC
-
VCC -
VCC -
VCC -
VCC -
VCC -
V
Differential Output
Voltage
VOH -
V
OL
Figure 1
mV
REFERENCE (VBB)
Reference Voltage
Output (Note 4)
V
BB
IBB = ±0.5mA
V
CC
-
VCC -
VCC -
VCC -
VCC -
VCC -
V
POWER SUPPLY
Supply Current
(Note 5)
I
EE
mA
VIH, VIL, V
MIN TYP MAX MIN TYP MAX MIN TYP MAX
0.095 3.0 0.095 3.0 0.095 3.0
IHD
, V
-300 +300 -300 +300 -300 +300
ILD
1.085
1.910
550 910 550 910 550 910
1.40
30 40 32 40 34 43
0.865
1.555
1.19
1.025
1.840
1.40
0.865
1.620
1.22
1.025
1.810
1.48
0.865
1.620
1.22
MAX9316A
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
4 _______________________________________________________________________________________
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at T
A
= +25°C and guaranteed by design over the full operating temperature range.
Note 4: Use V
BB
only for inputs that are on the same device as the VBBreference.
Note 5: All pins are open except V
CC
and VEE.
Note 6: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 7: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 8: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 9: Device jitter added to a jitter-free input signal.
AC ELECTRICAL CHARACTERISTICS
(VCC- VEE= 3.0V to 5.5V, outputs are loaded with 50Ω ±1% to VCC- 2V, input frequency ≤ 1.5GHz, input transition time = 125ps
(20% to 80%), SEL = high or low, EN = low, V
IHD
= VEE+ 1.2V to VCC, V
ILD
= VEEto VCC- 0.15V, V
IHD
- V
ILD
= 0.15V to 3V, unless
otherwise noted. Typical values are at V
CC
- VEE= 5.0V.) (Notes 1, 6)
PARAMETER
CONDITIONS
UNITS
CLK to Q_ Delay
(Differential)
t
PLHD1
,
Figure 2
ps
SCLK to Q_ Delay
t
PLHD3
,
VIL = VCC - 1.55V,
V
IH
= VCC - 1.09V,
Figure 3
ps
Output-to-Output
Skew (Note 7)
5
ps
Part-to-Part Skew
(Note 8)
ps
Added Random
Jitter (Note 9)
t
RJ
p s ( RM S )
Added
Deterministic Jitter
(Note 9)
t
DJ
1.5Gbps 2E
23
- 1
PRBS pattern
Ps
P-P
Switching
Frequency
f
MAX
( V
OH
- V OL)
≥ 400m V ,
Figure 2
GHz
Output Rise/Fall
Time (20% to 80%)
Figure 2
ps
SYMBOL
MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C +25°C +85°C
t
PHLD1
t
PHLD3
t
SKOO
t
SKPP
fIN = 1.5GHz clock 0.8 1.2 0.8 1.2 0.8 1.2
tR, t
F
290 400 310 440 300 520
290 400 310 440 300 520
30 20 40 20 50
110 130 220
50 70 50 70 50 70
1.5 1.5 1.5
80 120 90 130 90 145
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