The MAX14802/MAX14803/MAX14803A provide highvoltage switching on 16 channels for ultrasonic imaging
and printer applications. The devices utilize HVCMOS
process technology to provide 16 high-voltage lowcharge-injection SPST switches, controlled by a digital
interface. Data is clocked into an internal 16-bit shift
register and retained by a programmable latch with
enable and clear inputs. A power-on reset function
ensures that all switches are open on power-up.
The MAX14802/MAX14803/MAX14803A operate with a
wide range of high-voltage supplies including VPP/V
NN
= +100V/-100V, +200V/0V, or +40V/-160V. The digital
interface operates from a separate +2.7V to +5.5V V
DD
supply. Digital inputs DIN, CLK, LE, and CLR operate
on the V
DD
supply voltage.
The MAX14803/MAX14803A provide integrated 35kΩ
bleed resistors on each switch terminal to discharge
capacitive loads. The MAX14802/MAX14803/
MAX14803A provide integrated clamping diodes for
overvoltage protection against positive overshoot.
The MAX14802 is available in a 48-pin TQFP package
and is specified for commercial 0°C to +70°C and
extended -40°C to +85°C temperature ranges.
The MAX14803 is available in a 48-pin TQFP package
and is specified for the commercial 0°C to +70°C temperature range.
The MAX14803A is available in the 110-bump wafer level
package (WLP) and is specified at the -40°C to +85°C
temperature range.
(VDD= +2.7V to +5.5V, VPP= +40V to VNN+ 250V, VNN= -40V to -160V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial
.
(All voltages referenced to GND.)
V
DD
Logic-Supply Voltage .......................................-0.3V to +7V
V
PP
- VNNSupply Voltage ....................................................230V
V
PP
Positive-Supply Voltage.................................-0.3V to +220V
V
NN
Negative-Supply Voltage ...............................-0.3V to -220V
Logic Inputs (LE, CLR, CLK, DIN, DOUT)................-0.3V to +7V
COM_, NO_...............................(-0.3V + V
NN
) to the minimum of
[(V
NN
+ 220V) or (VPP+ 0.3V)]
Peak Analog Signal Current Per Channel ................................3A
The MAX14802/MAX14803/MAX14803A provide highvoltage switching on 16 channels for ultrasound imaging and printer applications. The devices utilize
HVCMOS process technology to provide 16 high-voltage low-charge-injection SPST switches, controlled by
a digital interface. Data is clocked into an internal 16bit shift register and retained by a programmable latch
with enable and clear inputs. A power-on-reset function
ensures that all switches are open on power-up.
The MAX14802/MAX14803/MAX14803A operate with a
wide range of high-voltage supplies including: VPP/V
NN
= +100V/-100V, +200V/0V, or +40V/-160V. The digital
interface operates from a separate +2.7V to +5.5V V
DD
supply. Digital inputs DIN, CLK, LE, and CLR operate
on the VDDsupply voltage. The MAX14803/MAX14803A
provide integrated 35kΩ bleed resistors on each switch
terminal to discharge capacitive loads. The MAX14802/
MAX14803/MAX14803A feature clamping diodes (at
the COM_). These clamping diodes provide overvoltage protection against positive overshoot.
Analog Switch
The MAX14802/MAX14803/MAX14803A allow a peak-topeak analog signal range from VNNto the minimum of
either VNN+ 200V or (VPP- 10V). Analog switch inputs
must be unconnected, or satisfy VNN≤ (V
COM_
, V
NO_
) ≤
VPPduring power-up and power-down.
High-Voltage Supplies
The MAX14802/MAX14803/MAX14803A allow a wide
range of high-voltage supplies. The devices operate
with VNNfrom -160V to 0 and VPPfrom +40V to VNN+
250V. When VNNis connected to GND (single-supply
applications), the devices operate with V
PP
up to
+200V. The VPPand VNNhigh-voltage supplies are not
required to be symmetrical, but the voltage difference
(VPP- VNN) must not exceed 250V.
Bleed Resistors (MAX14803/MAX14803A)
The MAX14803/MAX14803A feature integrated 35kΩ
bleed resistors to discharge capacitive loads such as
piezoelectric transducers. Each analog switch terminal
is connected to GND with a bleed resistor.
Overvoltage Protection
The MAX14802/MAX14803/MAX14803A feature clamping diodes (at the COM_). These clamping diodes provide overvoltage protection against positive overshoot.
Serial Interface
The MAX14802/MAX14803/MAX14803A are controlled
by a serial interface with a 16-bit serial shift register
and transparent latch. Each of the 16 data bits controls
a single analog switch (Table 1). Data on DIN is
clocked with the most significant bit (MSB) first into the
shift register on the rising edge of CLK. Data is clocked
out of the shift register onto DOUT on the rising edge of
CLK. DOUT reflects the status of DIN, delayed by 16
clock cycles (Figures 1 and 2).
Latch Enable (LE)
Drive LE logic-low to change the contents of the latch
and update the state of the high-voltage switches
(Figure 2). Drive LE logic-high to freeze the contents of
the latch and prevent changes to the switch states. To
reduce noise due to clock feedthrough, drive LE logichigh while data is clocked into the shift register. After
the data shift register is loaded with valid data, pulse
LE logic-low to load the contents of the shift register
into the latch.
Latch Clear (CLR)
The MAX14802/MAX14803/MAX14803A feature a latch
clear input. Drive CLR logic-high to reset the contents
of the latch to zero and open all switches. CLR does
not affect the contents of the data shift register. Pulse
LE logic-low to reload the contents of the shift register
into the latch.
Power-On Reset
The MAX14802/MAX14803/MAX14803A feature a
power-on-reset circuit to ensure all switches are open
at power-on. The internal 16-bit serial shift register and
latch are set to zero on power-up.
Table 1. Serial Interface Programming (Notes 5–10) (continued)
X = Don’t care.
Note 5: The 16 switches operate independently.
Note 6: Serial data is clocked in on the rising edge of CLK.
Note 7: The switches go to a state retaining their present condition on the rising edge of LE. When LE is low, the shift register data
flows through the latch.
Note 8: DOUT is high when switch 15 is on.
Note 9: Shift register clocking has no effect on the switch states if LE is high.
Note 10: The CLR input overrides all other inputs.
For medical ultrasound applications, see Figures 4, 5,
and 6.
Logic Levels
The MAX14802/MAX14803/MAX14803A digital interface inputs CLK, DIN, LE, and CLR operate on the V
DD
supply voltage.
Daisy-Chaining Multiple Devices
Digital output DOUT is provided to allow the connection
of multiple MAX14802/MAX14803/MAX14803A devices
by daisy-chaining (Figure 3). Connect each DOUT to the
DIN of the subsequent device in the chain. Connect CLK,
LE, and CLR inputs of all devices, and drive LE logic-low
to update all devices simultaneously. Drive CLR high to
open all the switches simultaneously. Additional shift registers can be included anywhere in series with the
MAX14802/MAX14803/MAX14803A data chain.
Supply Sequencing and Bypassing
The MAX14802/MAX14803/MAX14803A do not require
special sequencing of the VDD, VPP, and VNNsupply
voltages; however, analog switch inputs must be
unconnected, or satisfy VNN≤ (V
COM_
, V
NO_
) ≤ V
PP
during power-up and power-down. Bypass VDD, VPP,
and VNNto GND with a 0.1µF ceramic capacitor as
close as possible to the device.
Application Diagrams
MAX14802
MAX14803
MAX14803A
MAX14802
MAX14803
MAX14803A
MAX14802
MAX14803
MAX14803A
MAX14802
MAX14803
MAX14803A
MAX14802
MAX14803
MAX14803A
MAX14802
MAX14803
MAX14803A
CLK
DIN
CLK
LE
CLR
U10
U11
U1n
U20
U21
U2n
DOUT
DIN1
LE
CLR
DIN2
DIN
CLK
LE
CLR
DOUT
DIN
CLK
LE
CLR
DOUT
DIN
CLK
LE
CLR
DOUT
DIN
CLK
LE
CLR
DOUT
DIN
CLK
LE
CLR
DOUT
Figure 3. Interfacing Multiple Devices by Daisy-Chaining
MAX14802/MAX14803/MAX14803A
Low-Charge Injection, 16-Channel,
High-Voltage Analog Switches
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages
. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
TOP VIEW
(BUMPS ON BOTTOM)
+
A
B
C
D
E
F
G
H
J
K
1
N.C.
N.C.
N.C.
NO1
N.C.
COM3
N.C.
NO4
N.C.
N.C.
MAX14803A
234567891011
V
N.C.
V
N.C.
CLK
DOUT
N.C.
N.C.
V
PP
N.C.
NO0
N.C.
COM2
N.C.
NO2
N.C.
COM4
N.C.
N.C.
N.C.
COM1
N.C.
NO3
N.C.
COM5
N.C.
NO5
NN
N.C.
COM0
N.C.
N.C.
N.C.
NO6
N.C.
COM6
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
COM7
N.C.
NO7
GND
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DIN
N.C.
N.C.
N.C.
N.C.
N.C.
COM8
N.C.
NO8
LE
COM15
N.C.
N.C.
N.C.
NO9
N.C.
COM9
N.C.
CLR
N.C.
COM14
N.C.
NO12
N.C.
COM10
N.C.
NO10
COM13
COM11
DD
N.C.
NO15
N.C.
N.C.
NO13
N.C.
N.C.
N.C.
N.C.
N.C.
NO14
N.C.
COM12
N.C.
NO11
N.C.
N.C.
0.31 mm
0.5 mm
(5.81mm x 5.43mm)
WLP
0.5 mm
MAX14802/MAX14803/MAX14803A
Low-Charge Injection, 16-Channel,
High-Voltage Analog Switches
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
3 8/11 Added extended temperature information; added MAX14802ECM+ to data sheet 1
REVISION
DATE
DESCRIPTION
Corrected two specifications in the Absolute Maximum Ratings section,
changed the minimum of the peak-to-peak analog signal range to “either VNN + 200V
– 10V)”
or (V
PP
Deleted the MAX14800/MAX14801 from the entire data sheet and added the
MAX14803A; added the WLP part to the Ordering Information, Pin Configurations, Pin Descriptions, and Package Information sections
PAGES
CHANGED
2, 9
1–19
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