MagTek TRIPLE TRACK Delta ASIC User Manual
TRIPLE TRACK Delta ASIC
WITH SHIFT-OUT
ROHS COMPLIANT
SPECIFICATIONS
Specification Part Number 99875336 Rev 1
DECEMBER 2005
An ISO 9001 Registered Company
1710 Apollo Court
Seal Beach, CA 90740
Phone: (562) 546-6400
FAX: (562) 546-6301
Technical Support: (651) 415-6800
www.magtek.com
Copyright© 2001-2005
MagTek®, Inc.
All Rights Reserved
Printed in the United States of America
Information in this document is subject to change without notice. No part of this document may be
reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose,
without the express written permission of MagTek, Inc.
MagTek is a registered trademark of MagTek, Inc.
TM
MLF is a trademark of Amkor
, Inc.
REVISIONS
Rev Date Notes
1 8 Dec 05 Initial Release based on 99875259-12. Corrected example connector part
numbers. Added specification for head cleanliness. Added notes about additional
head loading, unused tracks, and head load for sensitivity measurements. Further
clarified WDT operation. Basically removed errata section. Removed
“Considerations for New Designs…” section.
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TABLE OF CONTENTS
INTRODUCTION .................................................................................................................................................1
FEATURES..........................................................................................................................................................1
CONFIGURATIONS ............................................................................................................................................2
SHIFT-OUT PROTOCOL – ISO FORMAT CARDS AND MOST OTHERS........................................................3
SHIFT-OUT TIMING............................................................................................................................................7
PREAMBLE KEY.................................................................................................................................................9
SHIFT-OUT PROTOCOL– CARDS ALLOWING 13 OR MORE CONSECUTIVE ZERO-BITS IN
THE DATA FIELD..............................................................................................................................................10
RECOMMENDATIONS AND PRECAUTIONS FOR MECHANICAL DESIGN .................................................12
Technical Specifications................................................................................................................................13
PACKAGING AND DRAWINGS........................................................................................................................14
Packaging and Pin Assignments...................................................................................................................14
Mechanical Drawings ....................................................................................................................................14
PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS AND SCHEMATICS......................................17
General Guidelines........................................................................................................................................17
IntelliHead......................................................................................................................................................17
MLFTM-14 with Provision for Shift-Out IntelliHeadTM......................................................................................19
Recommended PCB Land Pattern for the MLFTM-14 Package.....................................................................21
ERRATA.............................................................................................................................................................22
Products Affected ..........................................................................................................................................22
Details............................................................................................................................................................22
TABLE OF FIGURES AND TABLES
Figure 1. Timing................................................................................................................................................7
Table 1. Signal and Pin Assignments – Triple Track ASIC ............................................................................14
Figure 2. Package Marking for 21006529.......................................................................................................15
Figure 3. Package Marking for 21006539.......................................................................................................16
Figure 4. PCB Layout......................................................................................................................................19
Figure 5. Schematic........................................................................................................................................20
Figure 6. Recommended PCB Land Pattern.................................................................................................. 21
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INTRODUCTION
MagTek is pleased to offer a high-performance low-cost three-channel fully integrated magnetic str ipe
decoder chip or ASIC (Application Specific Integrated Circuit). This innovative, yet low-cost car d
reading solution offers many important advantages over the conventional less-integrated approach.
Packaged in a 14 pin MLF
TM
(MicroLeadFrameTM), this miniaturized Triple-Track Delta ASIC provides
a “Shift-Out” protocol for extracting data that significantly simplifies the card-reader to micro-controller
interface.
In addition to the 14 pin MLF
TM
Packaged Triple-Track ASIC as a stand-alone chip, MagTek also offers
the Shift-Out IntelliHead, a magnetic head with the chip actually built-in. The Shift-Out IntelliHead uses
the same Triple-Track ASIC, but completely encapsulated in a low-profile magnetic head, offering further
integration and excellent noise immunity by shielding the low-level analog signals inside the head.
Unless your application dictates the use of a particular separate or custom magnetic head, MagTek
recommends the Shift-Out IntelliHead for best performance, best miniaturization, and best economy. See
MagTek specification 99875258 for information on the Shift-Out IntelliHead product family.
For applications that can limit the supply voltage to the ASIC to 3.6V, the 21006540/41 ASIC is
recommended instead of the 21006529/39 ASIC described in this manual. The 21006540/41 ASIC is a
newer chip that will provide reduced power consumption and additional features at a reduced cost. It is
also available integrated into a head as part of the Shift-Out IntelliHead product family. See MagTek
specification 99875337 for information on this newer ASIC.
FEATURES
• Low cost solution for single, dual, or triple track readers – one triple-track chip works for all
• Compact design – 4 mm x 5mm 14 pin MLFTM (also called QFN) surface mount package
• Minimal external components – only a decoupling capacitor is required. Only 2 signals, DATA,
and STROBE, to connect to your micro-controller for up to 3 tracks
• Data buffer with Shift-Out – allows full card data to be locally stored on ASIC. Retrieve when
desired. Use a low-cost controller with no interrupts, limited memory, low-speed, low pin-count,
etc.
• High noise immunity – with proper PCB layout, the ASIC can withstand noisy PC monitors, cell
phones, switching power supplies, etc.
• High performance decoding – reads badly damaged cards; compensates for poor head mounting
• Low voltage operation – 2.8 Vdc to 5.5 Vdc
• Low operating current – less than 4 mA maximum total current at 3.3V (for up to 3 tracks) while
card is being swiped
• Ultra-low Sleep current – less than 75 μA maximum total current when no card is being swiped
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Triple Track ASIC
• AGC (Automatic Gain Control) – reads cards from 30% - 200% of International Standards
Organization (ISO) 7811 amplitude standard
• Wide operational temperature range – -40° C to +85° C
• Wide range of card swipe speeds – from 2.5 to 100 in/s (6.3 to 254 cm/s) for the standard 75 to
210 bits per inch (bpi) data density1
• RoHS Compliant – “lead (Pb) free” component
CONFIGURATIONS
Part Number Description
21006529 ASIC, Triple Track, F/2F Decode, MLF14, RoHS-compliant, Tube
21006539 ASIC, Triple Track, F/2F Decode, MLF14, RoHS-compliant, Tape and Reel
Note: The 21006529 and 21006539 are equivalent to the now obsolete 21006536 and 21006537
respectively, except the newer parts are RoHS-compliant (“Pb-free”).
1
The actual minimum instantaneous card speed allowed is 4.7cm/s (1.85ips) using zero-jitter 75bpi data; however, there is a
whole card timeout of 1.35s minimum, yielding a whole card average speed lower limit of approximately 6.3cm/s (2.5ips).
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Triple Track ASIC
SHIFT-OUT PROTOCOL – ISO FORMAT CARDS AND MOST OTHERS
The magnetic-stripe card formats most commonly used, including the ISO format, do not allow 13
consecutive zero-bits to occur in the actual data field. This section of the specification applies to only
these commonly occurring cards. If your application requires the reading of custom-data-formats that do
allow 13 consecutive zero-bits to appear in the data-field (excluding the “leading” and “trailing” zerobits), then refer to the “SHIFT-OUT PROTOCOL – CARDS ALLOWING 13 OR MORE
CONSECUTIVE ZERO-BITS IN THE DATA FIELD” section located near the end of this specification.
DATA is the sole output of the ASIC and is normally held high. Once the ASIC has qualified a head
signal as a magnetic stripe card, it begins to store data from the card in its buffer. In general, after the
card is read, the DATA line transitions from high to a low level (ZEROES FLAG) indicating the BufferReady state. This falling edge of DATA is the signal to a micro-controller that the on-chip memory of the
ASIC contains data to be read. After a “handshake” sequence, the data is extracted (read from the buffer
memory) by pulsing the STROBE input low to advance the data pointer that steers the data to the DATA
pin. During data extraction and when the STROBE input is low, a low on DATA represents a “one” bit
and a high represents a “zero” bit. The state of DATA is indeterminate after each rising edge of the
controller-issued STROBE, until the next falling edge of STROBE.
STROBE is a digital input to the ASIC and should be normally held high. When the DATA line goes
low at the end of a card swipe, STROBE should be pulsed low twice to complete the required
“handshake” and shift out stored data in the ASIC buffer to the DATA output. The STROBE pin is a
Schmitt-trigger input.
The on-chip buffer (memory) is fixed at a size of 608 bits for each of the three magnetic stripe tracks,
1824 bits total. The storage of each track begins with the first “one-bit” obtained from the card. The
zero-bits that precede the first one-bit will not be stored. After detecting the first one-bit, the ASIC stores
up to 608 bits per track; any bits exceeding this amount will be lost. These lost bits are guaranteed to be
zero-bits for ISO-encoded cards.
Note that some damaged cards may have one or more initial zero-bits with media scratches that may
appear as one-bits to some types of readers. This ASIC is highly immune to misinterpreting even deeply
scratched zero-bits, and thus the full 608 bits will be available for real data, starting from the first encoded
one-bit encountered on the card. Also note that in the case of a backwards swipe, the ISO Longitudinal
Redundancy Check (LRC) may have trailing zero-bits that are not stored in the chip’s buffer. These
missing bits are easily reconstructed with proper firmware.
Extraction of the data, as initiated by STROBE, proceeds in the order it was received for track ‘A’, ‘B’,
and then ‘C’. When the data pointer reaches the last position of the 1824 bit/3-track memory, it cycles
back through the data in opposite order. To clarify, the data is shifted out first in the order it was received
for track ’A’ ‘B’ and then track ’C’. The ASIC does not determine “which end of the data is which”, but
simply reports the data as it was received. Next, the opposite direction data Shift-Out also occurs in the
order of track ‘C’, ‘B’, and then ‘A’, as if an audio tape were being “rewound”. This process of data
output in alternating order will occur for maximum of four (4) forward-and-back cycles (total path =
ABCCBAABCCBAABCCBAABCCBA) as long as the micro-controller provides pulses to the STROBE
pin that meet the timing requirements and the ASIC is not reset.
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Triple Track ASIC
Prior to issuing track ‘A’ data for the first time following a card swipe, the ASIC issues a “preamble” of
16 bits. This preamble indicates the revision of the ASIC. See PREAMBLE KEY. The preamble is the
first “data” issued following a card swipe and is issued only once per data-extraction routine; it is not
repeated until the chip has been reset, and another swipe is completed.
The ASIC provides two indications for end-of-card (the initial Buffer-Ready state). The primary
indication normally occurs first and is triggered when all awakened tracks have each issued thirteen
consecutive zero-bits starting from 32 bit-cells after the first one-bit for a given track. This primary
indication of end-of-card is the ZEROES FLAG, a high to low transition on the DATA line. The
ZEROES FLAG indication on the DATA line should elicit a response of two low-going pulses from the
user’s controller on the STROBE line. The first of these low-going STROBE pulses is designated the
CLEAR signal, indicating a clearing of the ZEROES FLAG. The second STROBE is designated the
STOP signal, indicating a stopping of analog data collection. After a period of “Tss” (see timing chart
that follows) the ASIC will acknowledge the second low-going pulse of the STROBE by pulling DATA
low (if not already low) to the BUFFER-READY state. This is the “handshake” mentioned earlier. At
this point the ASIC is ready to accept a low-going STROBE pulse for extraction of the first bit of the 16bit “preamble”.
Issuing the two “handshake” STROBE pulses upon receiving the ZEROES FLAG allows the user to
begin extracting data as soon as possible, even before the card has finished its swipe past the magnetic
head. This practice combined with a high speed data extraction routine will minimize the tim e required to
re-arm the ASIC for reading – critical in some applications.
If the card is so badly damaged such that 13 consecutive zero-bits do not exist at the end of the data on all
utilized tracks, then there will be no ZEROES FLAG issued. However, the DATA line will still transition
from high to low to indicate the card’s end. This transition is called the AUXILIARY FLAG and is the
secondary end-of-card indication. In this case, the two low-going STROBE pulses must still be issued as
the “handshake” before data can be extracted. There will be no acknowledgement of either STROBE
pulse on the DATA line in this case. Note that if such a damaged card has one or more 75 bpi tracks and
is used in a high ambient noise environment, under some unlikely conditions the time required to receive
the AUXILIARY FLAG may be as much as from 1.35 to 3.1 seconds from the start of the card swipe.
With the exception of this rare case or a swipe that is so slow as to cause an internal timeout, the ASIC
will issue the AUXILIARY FLAG coincident with the encoded portion of the magnetic stripe losing
contact with the magnetic head gap. If an internal timeout occurs because of an extremely slow swipe, the
buffer will not be cleared, but will contain all data up to the point of the timeout. An internal timeout may
occur because of too slow of a swipe speed for a single bit, or for the aggregate time elapsed for the
swipe.
If the card being decoded has less than 13 consecutive zero-bits at the end of the swipe as described
above, then there may be some extraneous noise bits at the end of the ASIC’s buffer. Firmware should
anticipate the possibility of these extraneous bits.
The STROBE pin is edge triggered. Thus, for example, if the controller for some reason is holding
STROBE low when DATA indicates the ZEROES FLAG, the controller must take STROBE high and
then low again to issue the first of the two handshake STROBE signals required. It is recommended that
STROBE be kept high when not in the state of “BUFFER-READY” to maintain compatibility with future
products. It is also recommended that STROBE be held in a high state at power-up.
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