查询HMS87C1404B供应商
MAGNACHIP SEMICONDUCTOR LTD.
8-BIT SINGLE-CHIP MICROCONTROLLERS
HMS87C1808B/16B
HMS87C1708B/16B
HMS87C1608B/16B
HMS87C1508B/16B
HMS87C1404B/08B/16B
User’s Manual (Ver. 1.03)
REVISION HISTORY
VERSION 1.03 (SEP. 2004) This book
The company name, Hynix Semiconductor Inc. changed to MagnaChip Semiconductor Ltd.
VERSION 1.02 (MAR. 2004)
Correct the external RC oscillation characteristics
Fixed some errata.
VERSION 1.01 (MAY. 2003)
Fixed some errata.
Version 1.03
Published by
MCU Application Team
2004 MagnaChip Semiconductor Ltd. All right reserved.
Additional information of this manual may be served by MagnaChip Semiconductor offices in Korea or Distributors and Representatives.
MagnaChip Semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, MagnaChip Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
HMS87C1X04B/08B/16B
1. OVERVIEW .........................................................1
Description .........................................................1
Features .............................................................1
Development Tools ............................................2
Ordering Information ...................................3
2. BLOCK DIAGRAM .............................................4
3. PIN ASSIGNMENT .............................................5
4. PACKAGE DRAWING ........................................7
5. PIN FUNCTION .................................................10
6. PORT STRUCTURES .......................................12
7. ELECTRICAL CHARACTERISTICS ................17
Absolute Maximum Ratings .............................17
Recommended Operating Conditions ..............17
A/D Converter Characteristics .........................17
DC Electrical Characteristics ...........................18
AC Characteristics ...........................................19
Typical Characteristics .....................................20
8. MEMORY ORGANIZATION .............................23
Registers ..........................................................23
Program Memory .............................................25
Data Memory ...................................................28
Addressing Mode .............................................32
9. I/O PORTS ........................................................36
RA and RAIO registers ....................................36
RB and RBIO registers ....................................37
RC and RCIO registers ....................................39
RD and RDIO registers ....................................40
RE and REIO registers ....................................40
10. CLOCK GENERATOR ...................................41
Oscillation Circuit .............................................41
11. Basic Interval Timer .....................................43
12. TIMER / COUNTER ........................................44
8-bit Timer/Counter Mode ............................... 45
16-bit Timer/Counter Mode ............................. 46
8-bit Compare Output (16-bit) ......................... 47
8-bit Capture Mode ......................................... 47
16-bit Capture Mode ....................................... 50
PWM Mode ..................................................... 50
13. Serial Peripheral Interface ........................... 53
14. Buzzer Output function ................................ 55
15. ANALOG TO DIGITAL CONVERTER ........... 56
16. INTERRUPTS ................................................ 59
Interrupt Sequence .......................................... 61
BRK Interrupt .................................................. 62
Multi Interrupt .................................................. 62
External Interrupt ............................................. 64
17. WATCHDOG TIMER ...................................... 66
18. Power Saving Mode ..................................... 67
Stop Mode ....................................................... 67
STOP Mode using Internal RCWDT ............... 69
Wake-up Timer Mode ...................................... 70
Minimizing Current Consumption .................... 71
19. RESET ........................................................... 73
20. POWER FAIL PROCESSOR ......................... 75
21. COUNTERMEASURE OF NOISE ................. 77
Oscillation Noise Protector .............................. 77
Oscillation Fail Processor ................................ 78
Device Configuration Area .............................. 78
Examples of ONP ............................................ 79
22. OTP PROGRAMMING ................................... 80
EPROM Mode ................................................. 80
23. APPENDIX ........................................................ i
A. INSTRUCTION MAP ......................................i
B. INSTRUCTION SET ......................................ii
SEP. 2004 Ver 1.03
HMS87C1X04B/08B/16B
HMS87C1808B / 16B
HMS87C1708B / 16B
HMS87C1608B / 16B
HMS87C1508B / 16B
HMS87C1404B / 08B / 16B
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
1. OVERVIEW
1.1 Description
The HMS87C1X04B/08B/16B is an advanced CMOS 8-bit microcontroller with 4K/8K/16K bytes of ROM. The MagnaChip semiconductor’s HMS87C1X04B/08B/16B is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. The HMS87C1X04B/08B/16B provides the following standard features: 4K/8K/16K bytes of ROM, 448
bytes of RAM, 8-bit timer/counter, 8-bit A/D converter, 10-bit high speed PWM output, programmable buzzer driving port, 8-bit serial
communication port, on-chip oscillator and clock circuitry. In addition, the HMS87C1X04B/08B/16B support power saving modes to reduce power consumption.
This document is only explained for the base HMS87C1816B, the other’s eliminated functions are same as below.
Device name EPROM RAM EXT.INT BUZ
HMS87C14XXB 4,8,16K bytes
HMS87C15XXB
HMS87C16XXB 35 40 PDIP
HMS87C17XXB 37 42 SDIP
HMS87C18XXB 39 44 QFP
8,16K bytes
448bytes 4 O 2.3 ~ 5.5V
Operating
Voltage
I/O Package
23 28 SKDIP or SOP
27 32 PDIP
1.2 Features
• 4K/8K/16 Bytes On-chip Program Memory
• 448 Bytes of On-chip Data RAM
(Included stack memory)
• Instruction Cycle Time:
- 250nS at 8MHz
• Programmable I/O pins
(LED direct driving can be source and sink)
- HMS87C14XXB : 23
- HMS87C15XXB : 27
- HMS87C16XXB : 35
- HMS87C17XXB : 37
- HMS87C18XXB : 39
• Operating Voltage & Frequency
- 2.3V ~ 5.5V (at 1 ~ 4.2MHz)
- 4.5V ~ 5.5V (at 1 ~ 8.0MHz)
• Eight 8-bit A/D Converter
• Four External Interrupt Ports.
• One 8-bit Basic Interval Timer
• Four 8-bit Timer / Counters
• Two 10-bit High Speed PWM Outputs
• Watchdog timer (can be operate with internal
RC-oscillation)
• One 8-bit Serial Peripheral Interface
• Twelve Interrupt sources
- External input: 4
- A/D Conversion: 1
SEP. 2004 Ver 1.03 1
HMS87C1X04B/08B/16B
- Serial Peripheral Interface: 1
- Timer: 6
• One Programmable Buzzer Driving port
- 500Hz ~ 130kHz
• Noise Immunity Circuit
- Power Fail Processor
- Oscillation Noise Protector
- Oscillation Fail Processor
1.3 Development Tools
The HMS87C1X04B/08B/16B is supported by a full-featured
macro assembler, C compiler and an in-circuit emulator
CHOICE-Dr
The macro assembler and C compiler operate under the MS-Windows 95/98, 2000, XPTM.
The OTP programmer can be supplied three types of programmer
such as emulator add-on board type single programmer (PGMplus
(CHOICE-SIGMATM) and gang type programmer (CHOICEGANG4TM).
TM
and OTP programmers.
TM
), universal stand-alone type single programmer
• Oscillator Type
- Crystal
- Ceramic Resonator
- RC Oscillator ( C can be omitted )
- Internal Oscillator ( approx. 4MHz )
• Power Down Mode
- STOP mode
- Wake-up Timer mode
In Circuit
Emulators
Assembler
OTP
Programmer
CHOICE-Dr.
MagnaChip Macro Assembler
Single Programmer : PGM-plus
Universal Programmer : CHOICE-
SIGMA
Gang Programmer : CHOICE-GANG4
TM
TM
TM
TM
Figure 1-2 OTP Single Programmer PGM-plus
TM
Figure 1-1 In Circuit Emulator CHOICE-Dr.
TM
Figure 1-3 OTP Gang Programmer CHOICE-GANG4
TM
2 SEP. 2004 Ver 1.03
1.4 Ordering Information
ROM Size Package Type Ordering Device Code Operating Temperature
4K bytes (OTP) 28 SKDIP HMS87C1404B SK
8K bytes (OTP)
16K bytes (OTP)
28 SOP HMS87C1404B D
28 SKDIP HMS87C1408B SK
28 SOP HMS87C1408B D
32 PDIP HMS87C1508B
40 PDIP HMS87C1608B
42 SDIP HMS87C1708B K
44 MQFP HMS87C1808B Q
28 SKDIP HMS87C1416B SK
28 SOP HMS87C1416B D
32 PDIP HMS87C1516B
40 PDIP HMS87C1616B
42 SDIP HMS87C1716B K
44 MQFP HMS87C1816B Q
HMS87C1X04B/08B/16B
-40 ~ +85°C
SEP. 2004 Ver 1.03 3
HMS87C1X04B/08B/16B
2. BLOCK DIAGRAM
RESET
Xin
Xout
V
DD
V
SS
Power
Supply
PSW
System controller
System
Clock Controller
Timing generator
Clock Generator
Watch-dog
Timer
ALU
8-bit Basic
Interval
Timer
8-bit
A/D
Converter
RA RB RC
RA0 / EC0
RA1 / AN1
RA2 / AN2
RA3 / AN3
RA4 / AN4
RA5 / AN5
RA6 / AN6
RA7 / AN7
Accumulator Stack Pointer
8-bit
Timer/
Counter
High
Speed
PWM
RB0 / AN0 / Avref
RB1 / BUZ
RB2 / INT0
RB3 / INT1
RB4 / CMP0 / PWM0
RB5 / CMP1 / PWM1
RB6 / EC1
RB7 / TMR2OV
Interrupt Controller
Buzzer
Driver
Data
Memory
SPI
RC0
RC1
RC2
RC3 / SRDY
RC4 / SCK
RC5 / SIN
RC6 / SOUT
RC7
PC
Program
Memory
Data Table
Instruction
Decoder
RD
RD0 / INT2
RD1 / INT3
RD2
RD3
RD4
RD5
RD6
RD7
RE
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
4 SEP. 2004 Ver 1.03
3. PIN ASSIGNMENT
HMS87C1X04B/08B/16B
HMS87C14XXB SK
AN5 / RA5
AN6 / RA6
AN7 / RA7
V
DD
AN0 / AV
PWM0 / COMP0 / RB4
PWM1 / COMP1 / RB5
SRDYIN / SRDYOUT / RC3
/ RB0
REF
BUZ / RB1
INT0 / RB2
INT1 / RB3
EC1 / RB6
TMR2OV / RB7
HMS87C15XXB
HMS87C14XXB D
28 SKDIP
2
27
3
26
4
25
5
24
23
6
22
7
8
21
9
20
10
19
11
18
12
17
13 16
14 15
RA3 / AN3AN4 / RA4 1 28
RA2 / AN2
RA1 / AN1
RA0 / EC0
RD1 / INT3
RD0 / INT2
V
SS
RESET
X
OUT
X
IN
RD2
RC6 / SOUT
RC5 / SIN
RC4 / SCK
AN4 / RA4
AN5 / RA5
AN6 / RA6
AN7 / RA7
V
AN0 / AV
PWM0 / COMP0 / RB4
PWM1 / COMP1 / RB5
SRDYIN / SRDYOUT / RC3
/ RB0
REF
BUZ / RB1
INT0 / RB2
INT1 / RB3
EC1 / RB6
TMR2OV / RB7
DD
28 SOP
1
28
2
27
3
26
4
25
5
24
23
6
22
7
8
21
9
20
10
19
11
18
12
17
13
16
14
15
HMS87C16XXB
32 PDIP 40 PDIP
RA3 / AN3
RA2 / AN2
RA1 / AN1
RA0 / EC0
RD1 / INT3
RD0 / INT2
V
SS
RESET
X
OUT
X
IN
RD2
RC6 / SOUT
RC5 / SIN
RC4 / SCK
AN4 / RA4
AN5 / RA5
AN6 / RA6
AN7 / RA7
V
AN0 / AV
PWM0 / COMP0 / RB4
PWM1 / COMP1 / RB5
/ RB0
REF
BUZ / RB1
INT0 / RB2
INT1 / RB3
EC1 / RB6
TMR2OV / RB7
RC0
RC1
RC2
1
2
3
4
DD
5
6
7
8
9
10
11
12
13
14
15
16
31
30
29
28
27
26
25
24
23
22
21
20
19
17
RA3 / AN332
RA2 / AN2
RA1 / AN1
RA0 / EC0
V
SS
RESET
X
OUT
X
IN
RD2
RD1 / INT3
RD0 / INT2
RC7
RC6 / SOUT
RC5 / SIN
RC4 / SCK18
SRDYIN / SRDYOUT / RC3
SRDYIN / SRDYOUT / RC3
AN4 / RA4
AN5 / RA5
AN6 / RA6
AN7 / RA7
V
AN0 / AV
PWM0 / COMP0 / RB4
PWM1 / COMP1 / RB5
/ RB0
REF
BUZ / RB1
INT0 / RB2
INT1 / RB3
EC1 / RB6
TMR2OV / RB7
RE2
RE1
RE0
RC0
RC1
RC2
1
2
3
4
DD
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39
38
37
36
35
34
33
32
31
30
29
28
27
25
23
21
RA3 / AN340
RA2 / AN2
RA1 / AN1
RA0 / EC0
V
SS
RESET
X
OUT
X
IN
RD7
RD6
RD5
RD4
RD3
RD2
RD1 / INT326
RD0 / INT2
RC724
RC6 / SOUT
RC5 / SIN22
RC4 / SCK
SEP. 2004 Ver 1.03 5
HMS87C1X04B/08B/16B
HMS87C17XXB K
HMS87C18XXB Q
AN4 / RA4
AN5 / RA5
AN6 / RA6
AN7 / RA7
AN0 / AV
PWM0 / COMP0 / RB4
PWM1 / COMP1 / RB5
TMR2OV / RB7
V
/ RB0
REF
BUZ / RB1
INT0 / RB2
INT1 / RB3
EC1 / RB6
RE4
RE3
RE2
RE1
RE0
RC0
RC1
RC2
42 SDIP
1
2
3
4
DD
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
RA3 / AN3
RA2 / AN2
RA1 / AN1
RA0 / EC0
V
SS
RESET
X
OUT
X
IN
RD7
RD6
RD5
RD4
RD3
RD2
RD1 / INT3
RD0 / INT2
RC7
RC6 / SOUT
RC5 / SIN
RC4 / SCK
SRDYIN / SRDYOUT / RC3
44 MQFP
AN0 / AV
V
RA0 / EC0
RA1 / AN1
RA2 / AN2
RA3 / AN3
AN4 / RA4
AN5 / RA5
AN6 / RA6
AN7 / RA7
V
/ RB0
REF
OUTXIN
RESET
X
RD7
RD6
SS
DD
3332313029282726252423
34
35
36
37
38
39
40
41
42
43
44
1234567891011
BUZ / RB1
INT0 / RB2
INT1 / RB3
PWM0 / COMP0 / RB4
PWM1 / COMP1 / RB5
RD5
EC1 / RB6
RD4
TMR2OV / RB7
RD3
RE6
RD2
RE5
RD1 / INT3
RE4
RD0 / INT2
22
21
20
19
18
17
16
15
14
13
12
RE3
RC7
RC6 / SOUT
RC5 / SIN
RC4 / SCK
SRDYIN / SRDYOUT / RC3
RC2
RC1
RC0
RE0
RE1
RE2
6 SEP. 2004 Ver 1.03
4. PACKAGE DRAWING
HMS87C1X04B/08B/16B
28 SKINNY DIP
MAX 0.180
0.021
0.015
1.375
1.355
0.055
0.045
TYP 0.100
0.140
MIN 0.020
0.120
0 ~ 15°
unit: inch
MAX
MIN
TYP 0.300
0.300
0.275
4
1
0
.
0
8
0
0
.
0
28 SOP
0.104
0.093
0.020
0.0138
0.713
0.697
TYP 0.050
0.299
0.004
0.0118
0.292
0.419
0.0125
0.398
0.009
0.042
0 ~ 8°
0.016
SEP. 2004 Ver 1.03 7
HMS87C1X04B/08B/16B
32 PDIP
MAX 0.190
1.665
1.645
unit: inch
MAX
MIN
TYP 0.600
0.550
0.530
MIN 0.015
40 PDIP
MAX 0.200
0.022
0.015
2.075
2.045
0.065
0.045
0.140
TYP 0.100
0.120
0 ~ 15°
TYP 0.600
0.550
0.530
MIN 0.015
2
1
0
.
0
8
0
0
.
0
2
1
0
.
0
8
0
0
.
0
0.022
0.015
0.065
0.045
TYP 0.100
0.120
0.140
0 ~ 15°
8 SEP. 2004 Ver 1.03
42 SDIP
MAX 0.190
1.470
1.450
HMS87C1X04B/08B/16B
unit: inch
MAX
MIN
TYP 0.600
0.550
0.530
MIN 0.015
44 MQFP
0.020
0.016
2
1
0
.
0
8
0
0
.
0
0.045
TYP 0.070
0.140
0.120
0 ~ 15°
0.035
13.45
12.95
10.10
09.90
unit: mm
MAX
MIN
13.45
12.95
10.10
09.90
0-7°
SEE DETAIL “A”
0.25
0.10
1.03
0.73
0.25
REF
2.35 max.
0.45
0.30
0.80 Typ.
1.60
REF
DETAIL “A”
SEP. 2004 Ver 1.03 9
HMS87C1X04B/08B/16B
5. PIN FUNCTION
VDD: Supply voltage.
V
: Circuit ground.
SS
RESET: Reset the MCU.
XIN: Input to the inverting oscillator amplifier and input to the in-
ternal main clock operating circuit.
X
: Output from the inverting oscillator amplifier.
OUT
RA0~RA7: RA is an 8-bit, CMOS, bidirectional I/O port. RA
pins can be used as outputs or inputs according to “1” or “0” written the their Port Direction Register(RAIO).
Port pin Alternate function
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
EC0 ( Event Counter Input Source )
AN1 ( Analog Input Port 1 )
AN2 ( Analog Input Port 2 )
AN3 ( Analog Input Port 3 )
AN4 ( Analog Input Port 4 )
AN5 ( Analog Input Port 5 )
AN6 ( Analog Input Port 6 )
AN7 ( Analog Input Port 7 )
Table 5-1 RA Port
In addition, RA serves the functions of the various special features in Table 5-1 .
RB0~RB7: RB is an 8-bit, CMOS, bidirectional I/O port. RB
pins can be used as outputs or inputs according to “1” or “0” written the their Port Direction Register (RBIO).
RB serves the functions of the various following special features
Table 5-2
in
Port pin Alternate function
RB0
AN0 ( Analog Input Port 0 )
AVref ( External Analog Reference Pin )
RB1
RB2
RB3
RB4
BUZ ( Buzzer Driving Output Port )
INT0 ( External Interrupt Input Port 0 )
INT1 ( External Interrupt Input Port 1 )
PWM0 (PWM0 Output)
COMP0 (Timer1 Compare Output)
RB5
PWM1 (PWM1 Output)
COMP1 (Timer3 Compare Output)
RB6
RB7
EC1 (Event Counter Input Source)
TMR2OV (Timer2 Overflow Output)
RC0~RC7: RC is an 8-bit, CMOS, bidirectional I/O port. RC
pins can be used as outputs or inputs according to “1” or “0” written the their Port Direction Register (RCIO).
RC serves the functions of the serial interface following special
features in Table 5-3 .
Port pin Alternate function
RC0
RC1
RC2
RC3
SRDYIN
(SPI Ready Input)
SRDYOUT (SPI Ready Output)
RC4
SCKI (SPI CLK Input)
SCKO (SPI CLK Output)
RC5
RC6
SIN (SPI Serial Data Input)
SOUT (SPI Serial Data Output)
RC7
Table 5-3 RC Port
RD0~RD7: RD is an 8-bit, CMOS, bidirectional I/O port. RC
pins can be used as outputs or inputs according to “1” or “0” written the their Port Direction Register (RDIO).
RD serves the functions of the external interrupt following special features in Table 5-4
Port pin Alternate function
RD0
RD1
INT2 (External Interrupt Input Port 2)
INT3 (External Interrupt Input Port 3)
RD2
RD3
RD4
RD5
RD6
RD7
Table 5-4 RD Port
RE0~RE6: RE is a 7-bit, CMOS, bidirectional I/O port. RC pins
can be used as outputs or inputs according to “1” or “0” written
the their Port Direction Register (REIO).
Table 5-2 RB Port
PIN NAME Pin No. In/Out Function
V
DD
V
SS
43
34
-
-
Supply voltage
Circuit ground
Table 5-5 Pin Description
10 SEP. 2004 Ver 1.03
HMS87C1X04B/08B/16B
PIN NAME Pin No. In/Out Function
RESET 33
X
X
IN
OUT
31
32
RA0 (EC0) 35
RA1 (AN1) 36 Analog Input Port 1
RA2 (AN2) 37 Analog Input Port 2
RA3 (AN3) 38 Analog Input Port 3
RA4 (AN4) 39 Analog Input Port 4
RA5 (AN5) 40 Analog Input Port 5
RA6 (AN6) 41 Analog Input Port 6
RA7 (AN7) 42 Analog Input Port 7
RB0 (AVref/AN0) 44
RB1 (BUZ) 1
RB2 (INT0) 2
RB3 (INT1) 3
RB4 (PWM0/COMP0) 4
RB5 (PWM1/COMP1) 5
RB6 (EC1) 6
RB7 (TMR2OV) 7
RC0 ~ RC2 15 ~ 17
RC3 (SRDYIN/SRDYOUT)18
RC4 (SCK) 19
RC5 (SIN) 20
RC6 (SOUT) 21
RC7 22
RD0 (INT2) 23
RD1 (INT3) 24
RD2 25
RD3 ~ RD7 26 ~ 30
RE0 ~ RE6 14 ~8
I
I
O
I/O (Input)
I/O (Input/Input)
I/O (Output)
I/O (Input)
I/O (Input)
I/O (Output/Output)
I/O (Output/Output)
I/O (Input)
I/O (Output)
I/O
I/O (Input/Output)
I/O (Input/Output)
I/O (Input)
I/O (Output)
I/O
I/O (Input)
I/O (Input)
I/O
Reset signal input
Oscillation Input
Oscillation Output
Normal I/O Ports
External Event Counter input 0
Analog Reference / Analog Input Port 0
Buzzer Driving Output
External Interrupt Input 0
External Interrupt Input 1
PWM0 Output or Timer1 Compare Output
PWM1 Output or Timer3 Compare Output
External Event Counter input 1
Timer2 Overflow Output
SPI READY Input/Output
SPI CLK Input/Output
SPI DATA Input
SPI DATA Output
External Interrupt Input 2
External Interrupt Input 3
Table 5-5 Pin Description
SEP. 2004 Ver 1.03 11
HMS87C1X04B/08B/16B
6. PORT STRUCTURES
• RESET
Internal RESET
• Xin, Xout (Crystal or Ceramic Resonator)
V
SS
STOP
To System CLK
• Xin, Xout (RC or R oscillation)
Internal Cap = 6.0pF
RC
OSC
V
V
DD
V
DD
DD
V
DD
Xout
V
SS
Xin
V
DD
V
DD
Xout
V
SS
STOP
To System CLK
Xin
12 SEP. 2004 Ver 1.03
• RA0/EC0, RB6/EC1
• RA1/AN1 ~ RA7/AN7
Data Bus
Data Bus
Data Bus
Data Bus
EC0, EC1
Direction Reg.
Data Reg.
Data Reg.
Read
HMS87C1X04B/08B/16B
V
DD
Direction Reg.
Data Bus
Data Bus
Read
To A/D Converter
Analog Input Mode
(ANSEL7 ~ 1)
Analog CH. Selection
(ADCM.4 ~ 2)
• RB1/BUZ, RB4/PWM0/COMP0, RB5/PWM1/
V
SS
SEP. 2004 Ver 1.03 13
HMS87C1X04B/08B/16B
COMP1, RB7/TMR2OV, RC6/SOUT
PWM/COMP
BUZ,TMR2OV,SOUT
Data Reg.
Data Bus
V
1
0
DD
Function
Select
Data Bus
• RB0 / AN0 / AVref
Data Bus
AVREFS
Data Bus
Data Bus
To A/D Converter
Data Bus
Direction Reg.
Read
Read
Data Reg.
Direction Reg.
V
SS
V
DD
V
SS
Analog Input Mode
(ANSEL0)
Analog CH0 Selection
(ADCM.4 ~ 2)
To Vref of A/D
1
0
AVREFS
Internal V
DD
14 SEP. 2004 Ver 1.03
• RB2/INT0, RB3/INT1, RD0/INT2, RD1/INT3
Pull-up
Select
HMS87C1X04B/08B/16B
Weak Pull-up
• RC5/SIN
Data Bus
Function
Select
Data Bus
Data Bus
INT0, INT1
INT2, INT3
Data Bus
Function
Select
Data Bus
Data Reg.
Direction Reg.
Data Reg.
Direction Reg.
Read
Schmitt Trigger
V
DD
V
SS
V
DD
Data Bus
SIN
Read
Schmitt Trigger
V
SS
SEP. 2004 Ver 1.03 15
HMS87C1X04B/08B/16B
• RC0~2, RC7, RD2~7, RE0~6
Data Bus
Data Bus
Data Bus
Data Reg.
Direction Reg.
Read
V
DD
V
SS
• RC3 / SRDYIN
Data Bus
Function
Select
Data Bus
Data Bus
/ SRDYOUT, RC4 / SCKIN / SCK- OUT
SRDYOUT
SCKOUT
Data Reg.
Direction Reg.
SCKIN
SRDYIN
1
0
Read
Schmitt Trigger
V
DD
V
SS
16 SEP. 2004 Ver 1.03
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage......................................................-0.3 to +6.0 V
Storage Temperature .......................................... -40 to +125 °C
Voltage on any pin with respect to Ground (V
.......................................................................... -0.3 to VDD+0.3
Maximum current out of V
pin.................................. 200 mA
SS
Maximum current into VDD pin.................................... 150 mA
Maximum current sunk by (I
Maximum output current sourced by (I
......................................................................................... 15 mA
Maximum current (ΣI
OL
per I/O Pin) .................. 25 mA
OL
OH
) .............................................. 150 mA
7.2 Recommended Operating Conditions
)
SS
per I/O Pin)
HMS87C1X04B/08B/16B
Maximum current (ΣI
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
).............................................. 100 mA
OH
Parameter Symbol Condition
T
V
f
XIN
OPR
DD
Supply Voltage
Operating Frequency
Operating Temperature
7.3 A/D Converter Characteristics
(TA=25°C, VSS=0V, VDD=5.12V @f
Parameter Symbol Condition
Analog Input Voltage Range
Analog Power Supply Input Voltage Range
Overall Accuracy
Non-Linearity Error
Differential Non-Linearity Error
Zero Offset Error
Full Scale Error
Gain Error
Conversion Time
AV
Input Current
REF
=8MHz, VDD=3.072V @f
XIN
f
=8MHz
XIN
f
=4.2MHz
XIN
VDD=4.5~5.5V
VDD=2.3~5.5V
XIN
V
AIN
V
REF
N
ACC
N
NLE
N
DNLE
N
ZOE
N
FSE
N
NLE
T
CONV
I
REF
Specifications
Unit
Min. Max.
4.5 5.5 V
2.3 5.5 V
18MHz
14.2MHz
-40 85 °C
=4MHz)
Specifications
Unit
Min. Typ. Max.
AVREFS=0
AVREFS=1
VDD=5V
V
=3V
DD
V
SS
V
SS
-
-
3-
2.4 -
V
DD
V
REF
V
DD
V
DD
- ±0.7 ±1.5 LSB
- ±0.8 ±1.5 LSB
- ±1.0 ±1.5 LSB
- ±1.0 ±1.5 LSB
- ±0.25 ±0.5 LSB
- ±1.0 ±1.5 LSB
f
f
XIN
XIN
=8MHz
=4MHz
--10
--20
AVREFS=1 - 0.5 1.0 mA
V
V
V
µS
SEP. 2004 Ver 1.03 17
HMS87C1X04B/08B/16B
7.4 DC Electrical Characteristics
(TA=-40~85°C, VDD=2.3~5.5V, VSS=0V),
Parameter Symbol Pin Condition
Min. Typ. Max.
V
Input High Voltage
V
V
V
Input Low Voltage
V
V
Output High Voltage
Output Low Voltage
V
V
Input Pull-up Current
Input High
Leakage Current
Input Low
Leakage Current
Hysteresis
PFD Voltage
Internal RC WDT
Period
Operating Current
Wake-up Timer
Mode Current
2
I
I
I
I
| V
V
T
RCWDT
I
I
WKUP
RCWDT Mode
Current at STOP
I
RCWDT
Mode
Stop Mode Current
INT Input Noise
Cancel Time
External RC
Oscillator Frequency
1. Hysteresis Input: RA0, RB2, RB3, RB6, RC3, RC4, RC5, RD0, RD1
2. This parameter is measured in internal EPROM operation at the all I/O port defined input mode.
I
STOP
T
INT_NC
f
RC-OSC
f
R-OSC
XIN, RESET
IH1
Hysteresis Input
IH2
Normal Input
IH3
XIN, RESET 0-
IL1
Hysteresis Input
IL2
Normal Input 0 -
IL3
All Output Port VDD=5V, IOH=-5mA
OH
All Output Port VDD=5V, IOL=10mA
OL
I
RB2, RB3, RD0, RD1 VDD=5V -150 - -70 µA
P
All Pins (except XIN)VDD=5V - - 5 µA
IH1
X
IH2
IL1
IL2
T
PFD
DD
IN
All Pins (except XIN)VDD=5V -5 - - µA
X
IN
|
Hysteresis Input
V
DD
X
OUT
V
DD
V
DD
1
1
VDD=5V - - 15 µA
VDD=5V -15 - - µA
1
VDD=5V 0.5 - - V
VDD=5.5V 30 - 100
=3.0V 60 - 180
V
DD
VDD=5.5V, f
=3.0V, f
V
DD
VDD=5.5V, f
V
=3.0V, f
DD
=8MHz - 4 6.5
XIN
=4MHz - 2 3
XIN
=8MHz - 1 2
XIN
=4MHz - 0.3 1
XIN
VDD=5.5V - 30 70
V
DD
V
DD
RB2, RB3, RD0, RD1
f
XOUT
f
XOUT
= f
= f
RC-OSC
R-OSC
/ 4
/ 4
V
=3.0V - 5 50
DD
VDD=5.5V, f
=3.0V, f
V
DD
=8MHz - 0.5 3
XIN
=4MHz - 0.2 1
XIN
VDD=5V 0.2 - 0.5 µS
V
=5.5V
DD
R=30kΩ, C=10pF
V
=5.5V
DD
R=30kΩ
0.8 V
0.8 V
0.7 V
V
Specifications
Unit
DD
DD
DD
-
-
-
0-
DD
-1
-
--V
-1V
V
V
V
0.2 V
0.2 V
0.3 V
DD
DD
DD
DD
DD
DD
V
V
2.1 - 3.1 V
µS
mA
mA
µA
µA
0.7 - 1.5 MHz
2-4MHz
18 SEP. 2004 Ver 1.03
7.5 AC Characteristics
(TA=-40~+85°C, VDD=5V±10%, VSS=0V)
HMS87C1X04B/08B/16B
Parameter Symbol Pins
Operating Frequency
External Clock Pulse Width
External Clock Transition Time
Oscillation Stabilizing Time
External Input Pulse Width
RESET Input Width
X
IN
f
CP
t
CPW
t
RCP,tFCP
t
ST
t
EPW
t
RST
X
IN
X
IN
X
IN
XIN, X
OUT
INT0, INT1, INT2, INT3
EC0, EC1
RESET 8- -
t
t
1/f
SYS
CP
t
RCP
CPW
t
FCP
t
Specifications
Min. Typ. Max.
1-8MHz
50 - - nS
--20nS
--20mS
2--
CPW
V
0.5V
DD
-0.5V
Unit
t
SYS
t
SYS
RESET
INT0, INT1
INT3
INT2,
EC0,
EC1
t
RST
t
EPW
t
EPW
Figure 7-1 Timing Chart
0.2V
0.2V
DD
DD
0.8V
DD
SEP. 2004 Ver 1.03 19
HMS87C1X04B/08B/16B
7.6 Typical Characteristics
These graphs and tables provided in this section are for design
guidance only and are not tested or guaranteed.
In some graphs or tables the data presented are outside specified operating range (e.g. outside specified
range). This is for information only and devices
V
DD
are guaranteed to operate properly only within the
specified range.
The data presented in this section is a statistical summary of data
collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or
“min” represents (mean + 3σ) and (mean − 3σ) respectively
where σ is standard deviation
Operating Area
f
XIN
(MHz)
Ta= 25°C
10
8
6
4
2
0
23
I
DD
(µA)
0.8
0.6
0.4
45
STOP Mode
I
STOP−VDD
f
= 8MHz
XIN
Normal Operation
IDD−V
Ta=25°C
f
XIN
23
DD
= 8MHz
4MHz
45
V
DD
(V)
6
I
DD
(mA)
8
6
4
2
0
V
DD
(V)
6
Wake-up Timer Mode
I
WKUP−VDD
I
-25°C
25°C
85°C
DD
(mA)
2.0
1.5
1.0
Ta=25°C
f
XIN
= 8MHz
0.2
0
23
45
V
DD
(V)
6
0.5
0
23
4MHz
45
V
DD
(V)
6
RC-WDT in Stop Mode
I
RCWDT−VDD
I
DD
(µA)
Ta=25°C
20
15
T
= 80uS
5
RCWDT
23
45
V
DD
(V)
6
10
0
20 SEP. 2004 Ver 1.03
HMS87C1X04B/08B/16B
V
(V)
IH1
4
3
2
IOL−VOL, VDD=5V
I
OL
(mA)
40
30
20
10
0
12 345
VDD−V
f
=4MHz
XIN
Ta=25°C
IH1
XIN, RESET
IOH−VOH, VDD=5V
I
OH
-25°C
25°C
85°C
V
OL
(V)
VDD−V
IH2
V
IH2
f
=4kHz
XIN
(V)
Ta=25°C
4
3
2
(mA)
-20
-15
-10
-5
0
23 456
Hysteresis input
V
(V)
IH3
4
3
2
VDD−V
f
=4kHz
XIN
Ta=25°C
IH3
V
OH
(V)
-25°C
25°C
85°C
Normal input
V
IL1
(V)
1
0
1
VDD−V
f
XIN
Ta=25°C
4
3
2
1
0
1
23
IL1
XIN, RESET
=4MHz
23
45
45
1
V
(V)
0
IL2
4
3
2
1
0
23
VDD−V
f
=4kHz
XIN
Ta=25°C
23
45
IL2
Hysteresis input
45
V
DD
(V)
6
V
DD
(V)
6
V
DD
(V)
6
V
DD
(V)
6
V
(V)
1
0
IL3
4
3
2
1
0
23
VDD−V
f
=4kHz
XIN
Ta=25°C
23
IL3
Normal input
45
45
V
DD
(V)
6
V
DD
(V)
6
SEP. 2004 Ver 1.03 21
HMS87C1X04B/08B/16B
F
OSC
(MHz)
F
OSC
(MHz)
Typical RC Oscillator
Frequency vs V
6
No Cap
Ta = 25°C
5
4
R = 10K
3
2
1
0
2.5 3.0 3.5 4.0 4.5
Typical RC Oscillator
Frequency vs V
6
C
= 20p
EXT
Ta = 25°C
5
DD
R = 20K
R = 30K
DD
R = 51K
5.0 5.5
Typical RC Oscillator
Frequency vs V
F
OSC
6
(MHz)
V
DD
(V)
C
= 10p
EXT
Ta = 25°C
5
4
3
2
1
0
2.5 3.0 3.5 4.0 4.5
R = 10K
DD
R = 20K
R = 30K
R = 51K
5.0 5.5
V
DD
(V)
Typical RC Oscillator
F
OSC
(MHz)
6
5
Frequency vs V
C
= 30p
EXT
Ta = 25°C
DD
4
3
R = 10K
2
R = 20K
1
0
2.5 3.0 3.5 4.0 4.5
R = 30K
R = 51K
5.0
5.5
V
DD
(V)
Note: The external RC oscillation frequencies shown in
above are provided for design guidance only and not tested
or guaranteed. The user needs to take into account that the
external RC oscillation frequencies generated by the same
circuit design may be not the same. Because there are variations in the resistance and capacitance due to the tolerance of external R and C components. The parasitic
capacitance difference due to the different wiring length
and layout may change the external RC oscillation frequencies.
4
3
R = 10K
2
1
0
2.5 3.0 3.5 4.0 4.5
R = 20K
R = 30K
R = 51K
5.0
5.5
V
DD
(V)
Note: The external RC oscillation frequencies of the
HMS87C1X04B/08B/16B may be different from that of the
HMS81C1X04B/08B/16B. The user should modify the value of R and C components to get the proper frequency in
exchanging OTP device to mask device.
22 SEP. 2004 Ver 1.03
8. MEMORY ORGANIZATION
HMS87C1X04B/08B/16B
The HMS87C1X04B/08B/16B has separate address spaces for
Program memory and Data Memory. The Program memory can
only be read, not written to. It can be up to 4K /8K /16K bytes of
8.1 Registers
This device has six registers that are the Program Counter (PC),
a Accumulator (A), two index registers (X, Y), the Stack Pointer
(SP), and the Program Status Word (PSW). The Program Counter
consists of 16-bit register.
A
X
Y
SP
PCLPCH
PSW
Figure 8-1 Configuration of Registers
Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving,
and conditional judgement, etc.
The Accumulator can be used as a 16-bit register with Y Register
as shown below.
Y
A
Two 8-bit Registers can be used as a “YA” 16-bit Register
Figure 8-2 Configuration of YA 16-bit Register
X, Y Registers: In the addressing mode which uses these index
registers, the register contents are added to the specified address,
which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The
index registers also have increment, decrement, comparison and
data transfer functions, and they can be used as simple accumulators.
Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer
identifies the location in the stack to be accessed (save or restore).
ACCUMULATOR
X REGISTER
Y REGISTER
STACK POINTER
PROGRAM COUNTER
PROGRAM STATUS
WORD
Y A
Program memory. The Data memory can be read and written to
up to 448 bytes including the stack area.
Generally, SP is automatically updated when a subroutine call is
executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating
configuration, the user-processed data may be lost.
The stack can be located at any position within 00
to BFH of the
H
internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use
of the stack starts) by using the initialization routine. Normally,
the initial value of “BF
15 087
” is used.
H
Stack Address (00
00
Hardware fixed
~ BFH)
H
SP
Note: The Stack Pointer must be initialized by software because its value is undefined after RESET.
Example: To initialize the SP
LDX #0BFH
TXSP ; SP ← BFH
Program Counter: The Program Counter is a 16-bit wide which
consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset
state, the program counter has reset routine address (PC
PC
:0FEH).
L
:0FFH,
H
Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The
PSW is described in Figure 8-3 . It contains the Negative flag, the
Overflow flag, Direct page select flag, the Break flag, the Half
Carry (for BCD operation), the Interrupt enable flag, the Zero
flag, and the Carry flag.
[Carry flag C]
This flag stores any carry or borrow from the ALU of CPU after
an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction.
[Zero flag Z]
This flag is set when the result of an arithmetic operation or data
transfer is “0” and is cleared by any other result.
SEP. 2004 Ver 1.03 23
HMS87C1X04B/08B/16B
NEGATIVE FLAG
OVERFLOW FLAG
PSW
MSB LSB
N
V G B H I Z C
RESET VALUE: 00
CARRY FLAG RECEIVES
CARRY OUT
ZERO FLAG
H
DIRECT PAGE SELECT FLAG
BRK FLAG
Figure 8-3 PSW (Program Status Word) Register
[Interrupt disable flag I]
This flag enables/disables all interrupts except interrupt caused
by Reset or software BRK instruction. All interrupts are disabled
when cleared to “0”. This flag immediately becomes “0” when an
interrupt is served. It is set by the EI instruction and cleared by
the DI instruction.
[Half carry flag H]
After operation, this is set when there is a carry from bit 3 of ALU
or there is no borrow from bit 4 of ALU. This bit can not be set
or cleared except CLRV instruction with Overflow flag (V).
[Break flag B]
This flag is set by software BRK instruction to distinguish BRK
from TCALL instruction with the same vector address.
[Direct page select flag G]
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS
This flag assigned direct page for direct addressing mode. In the
direct addressing mode, addressing area is within zero page 00
to FFH when this flag is “0”. If it is set to “1”, addressing area is
100H to 1FFH.
It is set by SETG instruction, and cleared by CLRG instruction.
[Overflow flag V]
This flag is set to “1” when an overflow occurs as the result of an
arithmetic operation involving signs. An overflow occurs when
the result of an addition or subtraction exceeds +127(7F
) or -
H
128(80H). The CLRV instruction clears the overflow flag. There
is no set instruction. When the BIT instruction is executed, bit 6
of memory is copied to this flag.
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the result of
a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
H
24 SEP. 2004 Ver 1.03
8.2 Program Memory
A 16-bit program counter is capable of addressing up to 64K
bytes, but these devices have 4K/8K/16K bytes program memory
space only physically implemented. Accessing a location above
will cause a wrap-around to 0000H.
FFFF
H
Figure 8-4 , shows a map of Program Memory. After reset, the
CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-5 .
As shown in Figure 8-4 , each area is assigned a fixed location in
Program Memory. Program Memory area contains the user program.
C000H
HMS87C1X16B
E000H
Example: Usage of TCALL
LDA #5
TCALL 0FH ;
:;
:;
;
;TABLE CALL ROUTINE
;
FUNC_A: LDA LRG0
RET
;
FUNC_B: LDA LRG1
RET
;
;TABLE CALL ADD. AREA
;
ORG 0FFC0H ;
DW FUNC_A
DW FUNC_B
HMS87C1X04B/08B/16B
1BYTE INSTRUCTION
INSTEAD OF 3 BYTES
NORMAL CALL
1
2
TCALL ADDRESS AREA
HMS87C1X08B
F000H
HMS87C1X04B
FEFFH
FF00H
FFC0H
FFDFH
FFE0H
FFFFH
TCALL
AREA
INTERRUPT
VECTOR AREA
PROGRAM
MEMORY
PCALL
AREA
Figure 8-4 Program Memory Map
Page Call (PCALL) area contains subroutine program to reduce
program byte length by using 2 bytes PCALL instead of 3 bytes
CALL instruction. If it is frequently called, it is more useful to
save program byte length.
Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine.
The Table Call service area spaces 2-byte for every TCALL:
0FFC0
for TCALL15, 0FFC2H for TCALL14, etc., as shown in
H
Figure 8-6 .
The interrupt causes the CPU to jump to specific location, where
it commences the execution of the service routine. The External
interrupt 0, for example, is assigned to location 0FFFA
. The in-
H
terrupt service locations spaces 2-byte interval: 0FFF8H and
0FFF9H for External Interrupt 1, 0FFFAH and 0FFFBH for External Interrupt 0, etc.
As for the area from 0FF00H to 0FFFFH, if any area of them is not
going to be used, its service location is available as general purpose Program Memory.
Address Vector Area Memory
0FFE0
H
E2
E4
Serial Peripheral Interface Interrupt Vector Area
E6
E8
EA
EC
EE
F0
F2
F4
F6
F8
FA
FC
FE
Basic Interval Interrupt Vector Area
Watchdog Timer Interrupt Vector Area
A/D Converter Interrupt Vector Area
Timer/Counter 3 Interrupt Vector Area
Timer/Counter 2 Interrupt Vector Area
External Interrupt 3 Vector Area
External Interrupt 2 Vector Area
Timer/Counter 1 Interrupt Vector Area
Timer/Counter 0 Interrupt Vector Area
External Interrupt 1 Vector Area
External Interrupt 0 Vector Area
-
-
-
RESET Vector Area
NOTE:
“-” means reserved area.
Figure 8-5 Interrupt Vector Area
SEP. 2004 Ver 1.03 25
HMS87C1X04B/08B/16B
Address PCALL Area Memory
0FF00
H
0FFFF
H
PCALL Area
(256 Bytes)
Address Program Memory
0FFC0
H
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
TCALL 15
TCALL 14
TCALL 13
TCALL 12
TCALL 11
TCALL 10
TCALL 9
TCALL 8
TCALL 7
TCALL 6
TCALL 5
TCALL 4
TCALL 3
TCALL 2
TCALL 1
TCALL 0 / BRK *
Figure 8-6 PCALL and TCALL Memory Area
PCALL→ rel
4F35 PCALL 35H
~
~
0FF00H
0FF35H
0FFFFH
4F
35
NEXT
~
~
TCALL→ n
4A TCALL 4
4A
~
~
0F125H
0FF00H
0FFD6H
0FFD7H
0FFFFH
NEXT
25
F1
01001010
~
~
PC:
11111111
FHFHDH6
3
Reverse
1
11010110
2
H
26 SEP. 2004 Ver 1.03
Example: The usage software example of Vector address and the initialize part.
ORG 0FFE0H
DW NOT_USED; (0FFEO)
DW NOT_USED; (0FFE2)
DW SPI_INT; (0FFE4) Serial Peripheral Interface
DW BIT_INT; (0FFE6) Basic Interval Timer
DW WDT_INT; (0FFE8) Watchdog Timer
DW AD_INT; (0FFEA) A/D
DW TMR3_INT; (0FFEC) Timer-3
DW TMR2_INT; (0FFEE) Timer-2
DW INT3; (0FFF0) Int.3
DW INT2; (0FFF2) Int.2
DW TMR1_INT; (0FFF4) Timer-1
DW TMR0_INT; (0FFF6) Timer-0
DW INT1; (0FFF8) Int.1
DW INT0; (0FFFA) Int.0
DW NOT_USED; (0FFFC)
DW RESET; (0FFFE) Reset
ORG 0F000H
;********************************************
; MAIN PROGRAM *
;*******************************************
;
RESET: DI ;Disable All Interrupts
LDX #0
RAM_CLR: LDA #0;RAM Clear(!0000H->!00BFH)
STA {X}+;0-page Clear
CMPX #0C0H
BNE RAM_CLR
HMS87C1X04B/08B/16B
SETG
RAM_CL1: LDA #0;RAM Clear(!0100H->!01FFH)
;
;
;
LDX #0
STA {X}+;1-page Clear
CMPX #0
BNE RAM_CL1
CLRG
LDX #0BFH;Stack Pointer Initialize
TXSP
CALL INITIAL;
LDM RA, #0;Normal Port A
LDM RAIO,#1000_0010B;Normal Port Direction
LDM RB, #0;Normal Port B
LDM RBIO,#1000_0010B;Normal Port Direction
:
:
LDM PFDR,#0;Enable Power Fail Detector
:
SEP. 2004 Ver 1.03 27
HMS87C1X04B/08B/16B
8.3 Data Memory
Figure 8-7 shows the internal Data Memory space available.
Data Memory is divided into two groups, a user RAM (including
Stack) and control registers.
0000H
USER MEMORY
included STACK area
(192Bytes)
00BFH
00C0H
00FFH
0100H
01FFH
CONTROL
REGISTERS
USER MEMORY
(256Bytes)
Figure 8-7 Data Memory Map
User Memory
The HMS87C1X04B/08B/16B have 448 × 8 bits for the user
memory (RAM).
Control Registers
The control registers are used by the CPU and Peripheral function
blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt
system, the timer/ counters, analog to digital converters and I/O
ports. The control registers are in address range of 0C0
Note that unoccupied addresses may not be implemented on the
chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
More detailed informations of each register are explained in each
peripheral section.
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction.
PAG E0
PAG E1
to 0FFH.
H
Address
0C0H
0C1H
0C2H
0C3H
0C4H
0C5H
0C6H
0C7H
0C8H
0C9H
0CAH
0CBH
0CCH
0CDH
0D0H
0D1H
0D1H
0D1H
0D2H
0D3H
0D3H
0D4H
0D4H
0D4H
0D5H
0D6H
0D7H
0D7H
0D7H
0D8H
0D9H
0D9H
0DAH
0DAH
0DAH
0DBH
0DEH
0E0H
0E1H
Symbol R/W
RA
R/W
RAIO
RB
R/W
RBIO
RC
R/W
RCIO
RD
R/W
RDIO
RE
R/W
REIO
RAFUNC
RBFUNC
PUPSEL
RDFUNC
TM0
R/W
T0
TDR0
CDR0
TM1
R/W
TDR1
T1PPR
T1
CDR1
T1PDR
R/W
PWM0HR
TM2
R/W
T2
TDR2
CDR2
TM3
R/W
TDR3
T3PPR
T3
CDR3
T3PDR
R/W
PWM1HR
BUR
SIOM
SIOR
R/W
R/W
W
W
W
W
W
W
W
W
W
R
W
R
W
W
R
R
W
R
W
R
W
W
R
R
W
W
RESET
Value
Undefined
0000_0000
Undefined
0000_0000
Undefined
0000_0000
Undefined
0000_0000
Undefined
-000_0000
0000_0000
0000_0000
----_0000
----_--00
--00_0000
0000_0000
1111_1111
0000_0000
0000_0000
1111_1111
1111_1111
0000_0000
0000_0000
0000_0000
----_0000
--00_0000
0000_0000
1111_1111
0000_0000
0000_0000
1111_1111
1111_1111
0000_0000
0000_0000
0000_0000
----_0000
1111_1111
0000_0001
Undefined
Table 8-1 Control Registers
Addressing
mode
byte, bit
2
byte
byte, bit
byte
byte, bit
byte
byte, bit
byte
byte, bit
byte
byte
byte
byte
byte
byte, bit
byte
byte
byte
byte, bit
byte
byte
byte
byte
byte
byte
byte, bit
byte
byte
byte
byte, bit
byte
byte
byte
byte
byte
byte
byte
byte, bit
byte, bit
1
Example; To write at CKCTLR
LDM CKCTLR,#09H ;Divide ratio ÷16
28 SEP. 2004 Ver 1.03
HMS87C1X04B/08B/16B
0E2H
0E3H
0E4H
0E5H
0E6H
0EAH
0EBH
0ECH
0ECH
0EDH
0EDH
0EFH
IENH
IENL
IRQH
IRQL
IEDS
ADCM
ADCR
BITR
CKCTLR
WDTR
WDTR
PFDR
R/W
R/W
R/W
R/W
R/W
R/W
R
R
W
R
W
R/W
0000_0000
0000_---0000_0000
0000_---0000_0000
--00_0001
Undefined
0000_0000
-001_0111
0000_0000
0111_1111
----_0100
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte
byte
byte
byte
byte
byte, bit
Table 8-1 Control Registers
1. “byte, bit” means that register can be addressed by not only bit
but byte manipulation instruction.
2. “byte” means that register can be addressed by only byte
manipulation instruction. On the other hand, do not use any
read-modify-write instruction such as bit manipulation for
clearing bit.
Note: Several names are given at same address. Refer to
below table.
When read When write
Addr.
Timer
Mode
Capture
Mode
PWM
Mode
Timer
Mode
PWM
Mode
D1H T0 CDR0 - TDR0 -
D3H - TDR1 T1PPR
D4H T1 CDR1 T1PDR - T1PDR
D7H T2 CDR2 - TDR2 -
D9H - TDR3 T3PPR
DAH T3 CDR3 T3PDR - T3PDR
ECH BITR CKCTLR
Table 8-2 Various Register Name in Same Address
Stack Area
The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an
interrupt.
When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return
instruction [RETI] restores the contents of the program counter
and flags.
The save/restore locations in the stack are determined by the
stack pointed (SP). The SP is automatically decreased after the
saving, and increased before the restoring. This means the value
of the SP indicates the stack location number for the next save.
SEP. 2004 Ver 1.03 29
HMS87C1X04B/08B/16B
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
C0H RA RA Port Data Register
C1H RAIO RA Port Direction Register
C2H RB RB Port Data Register
C3H RBIO RB Port Direction Register
C4H RC RC Port Data Register
C5H RCIO RC Port Direction Register
C6H RD RD Port Data Register
C7H RDIO RD Port Direction Register
C8H RE RE Port Data Register
C9H REIO RE Port Direction Register
CAH RAFUNC ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0
CBH RBFUNC TMR2OV EC1I PWM1O PWM0O INT1I INT0I BUZO AVREFS
CCH PUPSEL - - - - PUPSEL3 PUPSEL2 PUPSEL1 PUPSEL0
CDH RDFUNC - - - - - - INT3I INT2I
D0H TM0 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST
D1H
D2H TM1 POL 16BIT PWM0E CAP1 T1CK1 T1CK0 T1CN T1ST
D3H
D4H
D5H PWM0HR PWM0 High Register
D6H TM2 - - CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST
D7H
D8H TM3 POL 16BIT PWM1E CAP3 T3CK1 T3CK0 T3CN T3ST
D9H
DAH
DBH PWM1HR PWM1 High Register
DEH BUR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0
E0H SIOM POL SRDY SM1 SM0 SCK1 SCK0 SIOST SIOSF
E1H SIOR SPI DATA REGISTER
E2HIENH INT0EINT1ET0E T1EINT2EINT3ET2E T3E
E3HIENL ADEWDTEBITESPIE----
E4H IRQH INT0IF INT1IF T0IF T1IF INT2IF INT3IF T2IF T3IF
T0/TDR0/
CDR0
TDR1/
T1PPR
T1/CDR1/
T1PDR
T2/TDR2/
CDR2
TDR3/
T3PPR
T3/CDR3/
T3PDR
Timer0 Register / Timer0 Data Register / Capture0 Data Register
Timer1 Data Register / PWM0 Period Register
Timer1 Register / Capture1 Data Register / PWM0 Duty Register
Timer2 Register / Timer2 Data Register / Capture2 Data Register
Timer3 Data Register / PWM1 Period Register
Timer3 Register / Capture3 Data Register / PWM1Duty Register
Table 8-3 Control Registers of HMS87C1X04B/08B/16B
These registers of shaded area can not be accessed by bit manipulation instruction as “SET1, CLR1”, but should be accessed by
register operation instruction as “LDM dp, #imm”.
30 SEP. 2004 Ver 1.03
HMS87C1X04B/08B/16B
E5HIRQL ADIFWDTIFBITIFSPIF----
E6H IEDS IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L
EAH ADCM - - ADEN ADS2 ADS1 ADS0 ADST ADSF
EBH ADCR ADC Result Data Register
ECH BITR
ECH CKCTLR
EDH WDTR WDTCL 7-bit Watchdog Counter Register
EFH PFDR
These registers of shaded area can not be accessed by bit manipulation instruction as “SET1, CLR1”, but should be accessed by
register operation instruction as “LDM dp, #imm”.
1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR.
2.The register PFDR only be implemented on devices, not on In-circuit Emulator.
1
2
Basic Interval Timer Data Register
1
- WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0
----PFDOPRPFDISPFDMPFDS
Table 8-3 Control Registers of HMS87C1X04B/08B/16B
SEP. 2004 Ver 1.03 31
HMS87C1X04B/08B/16B
8.4 Addressing Mode
The HMS87C1X04B/08B/16B uses six addressing modes;
• Register addressing
• Immediate addressing
• Direct page addressing
• Absolute addressing
(3) Direct Page Addressing → dp
In this mode, a address is specified within direct page.
Example;
C535 LDA 35H ;A ←RAM[35H]
• Indexed addressing
• Register-indirect addressing
(1) Register Addressing
Register addressing accesses the A, X, Y, C and PSW.
(2) Immediate Addressing → #imm
In this mode, second byte (operand) is accessed as a data immediately.
Example:
0435 ADC #35H
MEMORY
04
35
A+35H+C → A
0035
0F550
0F551
H
H
H
data
2
~
~
C5
35
~
~
1
data → A
(4) Absolute Addressing → !abs
Absolute addressing sets corresponding memory data to Data, i.e.
second byte(Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address.
With 3 bytes command, it is possible to access to whole memory
area.
ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR,
SBC, STA, STX, STY
Example;
0735F0 ADC !0F035H ;A ←ROM[0F035H]
E45535 LDM 35H,#55H
data
~
~
07
35
F0
~
~
2
1
A+data+C → A
address: 0F035
0035
0F100
0F101
0F102
0F035
H
H
data
~
~
1
H
H
H
E4
55
35
data ← 55H
~
~
0F100
H
0F101
H
0F102
2
H
32 SEP. 2004 Ver 1.03
HMS87C1X04B/08B/16B
The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR
Example; Addressing accesses the address 0035H.
983500 INC !0035H ;A ←RAM[035H]
0035
0F100
0F101
0F102
H
H
H
H
data
~
~
98
35
00
~
~
3
2
data+1 → data
1
address: 0035
(5) Indexed Addressing
X indexed direct page (no offset) → {X}
In this mode, a address is specified by the X register.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
Example; X=15
D4 LDA {X} ;ACC←RAM[X].
H
X indexed direct page, auto increment→ {X}+
In this mode, a address is specified within direct page by the X
register and the content of X is increased by 1.
LDA, STA
Example; X=35
H
DB LDA {X}+
35
H
data
~
~
DB
~
~
1
2
data → A
36H → X
X indexed direct page (8 bit offset) → dp+X
This address value is the second byte (Operand) of command plus
the data of X-register. And it assigns the memory in Direct page.
ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY,
XMA, ASL, DEC, INC, LSR, ROL, ROR
Example; X=015
C645 LDA 45H+X
H
15
0E550
H
H
data
~
~
D4
2
~
~
data → A
1
5A
0E550
0E551
H
data
3
data → A
~
~
H
H
C6
45
~
~
2
1
45H+15H=5AH
SEP. 2004 Ver 1.03 33
HMS87C1X04B/08B/16B
Y indexed direct page (8 bit offset) → dp+Y
This address value is the second byte (Operand) of command plus
the data of Y-register, which assigns Memory in Direct page.
This is same with above (2). Use Y register instead of X.
Y indexed absolute →!abs+Y
Sets the value of 16-bit absolute address plus Y-register data as
Memory. This addressing mode can specify memory in whole area.
Example; Y=55
H
D500FA LDA !0FA00H+Y
0F100
0F101
0F102
0FA55
H
H
H
~
~
H
D5
00
FA
data
1
0FA00H+55H=0FA55H
~
~
2
data → A
3
(6) Indirect Addressing
3F35 JMP [35H]
0E30A
0FA00
35
H
36
H
~
~
H
~
~
H
0A
E3
NEXT
3F
35
jump to address 0E30A
2
~
~
~
~
1
H
X indexed indirect → [dp+X]
Processes memory data as Data, assigned by 16-bit pair memory
which is determined by pair data [dp+X+1][dp+X] Operand plus
X-register data in Direct page.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; X=10
1625 ADC [25H+X]
H
Direct page indirect → [dp]
Assigns data address to use for accomplishing command which
sets memory data (or pair memory) by Operand.
Also index can be used with Index register X,Y.
JMP, CALL
Example;
0E005
0FA00
35
H
36
H
~
~
H
~
~
H
05
E0
data
16
25
0E005
2
~
~
~
~
H
25 + X(10) = 35
1
H
3 A + data + C → A
34 SEP. 2004 Ver 1.03
HMS87C1X04B/08B/16B
Y indexed indirect → [dp]+Y
Processes memory data as Data, assigned by the data [dp+1][dp]
of 16-bit pair memory paired by Operand in Direct page plus Yregister data.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; Y=10
1725 ADC [25H]+Y
0E015
0FA00
H
25
H
26
H
~
~
H
~
~
H
05
E0
data
17
25
0E005H + Y(10) = 0E015
2
~
~
H
1
~
~
3 A + data + C → A
Absolute indirect → [!abs]
The program jumps to address specified by 16-bit absolute address.
JMP
Example;
1F25E0 JMP [!0C025H]
PROGRAM MEMORY
0E025
H
0E026
H
~
~
0E725
0FA00
H
~
~
H
1
25
E7
NEXT
1F
25
E0
~
~
~
address 0E30A
H
jump to
2
~
SEP. 2004 Ver 1.03 35
HMS87C1X04B/08B/16B
9. I/O PORTS
The HMS87C1816B has five ports, RA, RB, RC,RD and RE.
These ports pins may be multiplexed with an alternate function
for the peripheral features on the device. In general, when initial
reset state, all ports are used as a general purpose input port.
All pins have data direction registers which can set these ports as
output or input. A “1” in the port direction register defines the
corresponding port pin as output. Conversely, write “0” to the
corresponding bit to specify as an input pin. For example, to use
the even numbered bit of RA as output ports and the odd numbered bits as input ports, write “55
” to address C1H (RA direc-
H
tion register) during initial setting as shown in Figure 9-1 .
Reading data register reads the status of the pins whereas writing
9.1 RA and RAIO registers
RA is an 8-bit bidirectional I/O port (address C0H). Each port can
be set individually as input and output through the RAIO register
(address C1
RA7~RA1 ports are multiplexed with Analog Input Port
(AN7~AN1) and RA0 port is multiplexed with Event Counter Input Port (EC0).
RA Data Register
RA
RA Direction Register
RAIO
RA Function Selection Register
RAFUNC
ANSEL7 ANSEL1ANSEL2ANSEL3ANSEL4ANSEL5ANSEL6
).
H
ADDRESS : C0H
RESET VALUE : Undefined
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
INPUT / OUTPUT DATA
ADDRESS : C1H
RESET VALUE : 0000_0000
DIRECTION SELECT
0 : INPUT PORT
1 : OUTPUT PORT
ADDRESS : CAH
RESET VALUE : 0000_0000
ANSEL0
0 : RB0
1 : AN0
0 : RA1
1 : AN1
0 : RA7
1 : AN7
0 : RA6
1 : AN6
0 : RA4
1 : AN4
0 : RA5
1 : AN5
0 : RA3
1 : AN3
0 : RA2
1 : AN2
Figure 9-2 Registers of Port RA
to it will write to the port latch.
WRITE “55H” TO PORT RA DIRECTION REGISTER
C0H
C1H
C2H
C3H
RA DATA
RA DIRECTION
RB DATA
RB DIRECTION
0 1 0 1 0 1 0 1
76543210 BIT
I O I O I O I O
76543210PORT
I: INPUT PORT
O: OUTPUT PORT
Figure 9-1 Example of port I/O assignment
The control register RAFUNC (address CA
) controls to select
H
alternate function. After reset, this value is “0”, port may be used
as general I/O ports. To select alternate function such as Analog
Input or External Event Counter Input, write “1” to the corresponding bit of RAFUNC.Regardless of the direction register
RAIO, RAFUNC is selected to use as alternate functions, port pin
can be used as a corresponding alternate features (RA0/EC0 is
controlled by T0CK2~0 of TM0)
PORT RAFUNC.7~0 Description
RA7/AN7
0 RA7 (Normal I/O Port)
1 AN7 (ADS2~0=111)
RA6/AN6
0 RA6 (Normal I/O Port)
1 AN6 (ADS2~0=110)
RA5/AN5
0 RA5 (Normal I/O Port)
1 AN5 (ADS2~0=101)
RA4/AN4
0 RA4 (Normal I/O Port)
1 AN4 (ADS2~0=100)
RA3/AN3
0 RA3 (Normal I/O Port)
1 AN3 (ADS2~0=011)
RA2/AN2
0 RA2 (Normal I/O Port)
1 AN2 (ADS2~0=010)
RA1/AN1
0 RA1 (Normal I/O Port)
1 AN1 (ADS2~0=001)
RA0/EC0
1. This port is not an Analog Input port, but Event Counter clock
source input port. ECO is controlled by setting TOCK2~0 =
111. The bit RAFUNC.0 (ANSEL0) controls the RB0/AN0/AVref
port (Refer to Port RB).
1
RA0 (Normal I/O Port)
EC0 (T0CK2~0=111)
36 SEP. 2004 Ver 1.03
9.2 RB and RBIO registers
RB is an 8-bit bidirectional I/O port (address C2H). Each pin can
be set individually as input and output through the RBIO register
(address C3
special features. The control register RBFUNC (address CBH)
). In addition, Port RB is multiplexed with various
H
HMS87C1X04B/08B/16B
controls to select alternate function. After reset, this value is “0”,
port may be used as general I/O ports. To select alternate function
such as External interrupt or Timer compare output, write “1” to
the corresponding bit of RBFUNC.
RB Data Register
RB
RB5
RB6RB7
RB Direction Register
RBIO
ADDRESS : C2H
RESET VALUE : Undefined
RB4 RB3 RB2 RB1 RB0
INPUT / OUTPUT DATA
ADDRESS : C3H
RESET VALUE : 0000_0000
DIRECTION SELECT
0 : INPUT PORT
1 : OUTPUT PORT
RB Function Selection Register
RBFUNC
Pull-up Selection Register
PUPSEL
-
Interrupt Edge Selection Register
IEDS
ADDRESS : CBH
RESET VALUE : 0000_0000
--
-
RB3 / INT1 Pull-up
0 : No Pull-up
1 : With Pull-up
IED2LIED2HIED3LIED3H
INT2INT3
ADDRESS : CCH
RESET VALUE : ----_0000
PUP0
PUP1
PUP2PUP3
RB2 / INT0 Pull-up
0 : No Pull-up
1 : With Pull-up
ADDRESS : E6H
RESET VALUE : 0000_0000
IED0L
IED0HIED1LIED1H
INT0INT1
External Interrupt Edge Select
00 : Normal I/O port
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
11 : Both (Rising & Falling)
0 : RB7
1 : TMR2OV
0 : RB6
1 : EC1
0 : RB5
1 : PWM1 Output or
Compare Output
0 : RB4
1 : PWM0 Output or
Compare Output
TMR2OV
EC1I
PWM1O
AVREFS
BUZOINT0IINT1IPWM0O
0 : RB0 when ANSEL0 = 0
AN0 when ANSEL0 = 1
1 : AVref
0 : RB1
1 : BUZ Output
0 : RB2
1 : INT0
0 : RB3
1 : INT1
Figure 9-3 Registers of Port RB
Regardless of the direction register RBIO, RBFUNC is selected
ing alternate features.
to use as alternate functions, port pin can be used as a correspond-
SEP. 2004 Ver 1.03 37
HMS87C1X04B/08B/16B
PORT RBFUNC.4~0 Description
RB7/
TMR2OV
0 RB7 (Normal I/O Port)
1 Timer2 Overflow Output
0 RB6 (Normal I/O Port)
RB6/EC1
RB5/
PWM1/
COMP1
RB4/
PWM0/
COMP0
1 Event Counter 1 Input
0 RB5 (Normal I/O Port)
1
PWM1 Output /
Timer3 Compare Output
0 RB4 (Normal I/O Port)
1
PWM0 Output /
Timer1 Compare Output
0 RB3 (Normal I/O Port)
RB3/INT1
RB2/INT0
RB1/BUZ
1 External Interrupt Input 1
0 RB2 (Normal I/O Port)
1 External Interrupt Input 0
0 RB1 (Normal I/O Port)
1 Buzzer Output
1
RB0/AN0/
AVref
1. When ANSEL0 = “0”, this port is defined for normal I/O port
(RB0).
When ANSEL0 = “1” and ADS2~0 = “000”, this port
can be used Analog Input Port (AN0).
2. When this bit set to “1”, this port defined for AVref, so it can
not be used Analog Input Port AN0 and Normal I/O
Port RB0.
0
2
1
RB0 (Normal I/O Port)/
AN0 (ANSEL0=1)
External Analog Reference
Voltage
38 SEP. 2004 Ver 1.03
9.3 RC and RCIO registers
RC is an 8-bit bidirectional I/O port (address C4H). Each pin can
be set individually as input and output through the RCIO register
(address C5
In addition, Port RC is multiplexed with Serial Peripheral Interface (SPI).
).
H
HMS87C1X04B/08B/16B
The control register SIOM (address E0
Peripheral Interface function.
After reset, the RCIO register value is “0”, port may be used as
general I/O ports. To select Serial Peripheral Interface function,
write “1” to the corresponding bit of SIOM.
) controls to select Serial
H
RC Data Register
RC
RC6 RC5 RC4 RC3RC7 RC2 RC1 RC0
PORT Function
RC6/
SOUT
RC5/
SIN
RC4/
SCK
RC3/
SRDY
SRDYIN
SRDYOUT
ADDRESS : C4H
RESET VALUE : Undefined
INPUT / OUTPUT DATA
RC Direction Register
RCIO
ADDRESS : C5H
RESET VALUE : 0000_0000
DIRECTION SELECT
0 : INPUT PORT
1 : OUTPUT PORT
Figure 9-4 Registers of Port RC
SIOM
SRDY SM [1:0] SCK [1:0]
Description
RC6 X X:0 X:X RC6 (Normal I/O Port)
SOUT X X:1 X:X SPI Serial Data Output
RC5 X 0:X X:X RC5 (Normal I/O Port)
SIN X 1:X X:X SPI Serial Data Input
RC4 X 0:0 X:X RC4 (Normal I/O Port)
SCKO X 0:0 00, 01, 10 SPI Synchronous Clock Output
SCKI X 0:0 1:1 SPI Synchronous Clock Input
RC3 0 X:X X:X RC3 (Normal I/O Port)
1 X:X 00, 01, 10 SPI Ready Input (Master Mode)
1 X:X 1:1 SPI Ready Output (Slave Mode)
Table 9-1 Serial Communication Functions in RC Port
SEP. 2004 Ver 1.03 39
HMS87C1X04B/08B/16B
9.4 RD and RDIO registers
RD is an 8-bit bidirectional I/O port (address C6H). Each pin can
be set individually as input and output through the RDIO register
(address C7H).
RD Data Register
RD
INPUT / OUTPUT DATA
RD Direction Register
RDIO
DIRECTION SELECT
0 : INPUT PORT
1 : OUTPUT PORT
ADDRESS : C6H
RESET VALUE : Undefined
RD2 RD1 RD0
RD3RD4RD5RD6RD7
ADDRESS : C7H
RESET VALUE : 0000_0000
RD Function Selection Register
RDFUNC
Pull-up Selection Register
PUPSEL
-
Interrupt Edge Selection Register
IEDS
ADDRESS : CDH
RESET VALUE : 0000_0000
INT3I
--
RD1 / INT3 Pull-up
0 : No Pull-up
1 : With Pull-up
IED2LIED2HIED3LIED3H
INT2INT3
INT2I
0 : RD0
1 : INT2
0 : RD1
1 : INT3
-
ADDRESS : CCH
RESET VALUE : ----_0000
PUP0
PUP1
PUP2PUP3
RD0 / INT2 Pull-up
0 : No Pull-up
1 : With Pull-up
ADDRESS : E6H
RESET VALUE : 0000_0000
IED0L
IED0HIED1LIED1H
INT0INT1
External Interrupt Edge Select
00 : Normal I/O port
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
1 1: Both (Rising & Falling)
Figure 9-5 Registers of Port RD
In addition, Port RD is multiplexed with external interrupt input
function. The control register RDFUNC (address CD
) controls
H
to select alternate function. After reset, this value is “0”, port may
be used as general I/O ports. To select alternate function, write
“1” to the corresponding bit of RDFUNC.
9.5 RE and REIO registers
RE is a 7-bit bidirectional I/O port (address C8H). Each pin can
be set individually as input and output through the REIO register
RE Data Register
RE
-
INPUT / OUTPUT DATA
ADDRESS : C8H
RESET VALUE : Undefined
RE2 RE1 RE0
RE3RE4RE5RE6
Figure 9-6 Registers of Port RE
Regardless of the direction register RDIO, RDFUNC is selected
to use as external interrupt input function, port pin can be used as
a interrupt input feature.
(address C9H).
RE Direction Register
REIO
ADDRESS : C9H
RESET VALUE : -000_0000
DIRECTION SELECT
0 : INPUT PORT
1 : OUTPUT PORT
40 SEP. 2004 Ver 1.03
10. CLOCK GENERATOR
HMS87C1X04B/08B/16B
The clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and peripheral
hardware. The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator connected to the Xin and
fxin
÷1
÷2 ÷4 ÷8 ÷16 ÷128 ÷256 ÷512 ÷1024÷32 ÷64
STOP
WAKEUP
OSCILLATION
CIRCUIT
Figure 10-1 Block Diagram of Clock Pulse Generator
10.1 Oscillation Circuit
XIN and X
amplifier which can be set for use as an on-chip oscillator, as
shown in Figure 10-2 .
are the input and output, respectively, a inverting
OUT
Xout pins. External clocks can be input to the main system clock
oscillator. In this case, input a clock signal to the Xin pin and
open the Xout pin.
CLOCK PULSE
GENERATOR
Peripheral clock
PRESCALER
Internal system clock
÷2048
nents.
OPEN
Xout
C1
C2
Recommended: C1, C2 = 30pF±10pF for Crystals
Xout
Xin
Vss
Figure 10-2 Oscillator Connections
To drive the device from an external clock source, Xout should
be left unconnected while Xin is driven as shown in Figure 10-3
. There are no requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is through
a divide-by-two flip-flop, but minimum and maximum high and
low times specified on the data sheet must be observed.
Oscillation circuit is designed to be used either with a ceramic
resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the
crystal manufacturer for appropriate values of external compo-
External
Clock
Source
Xin
Vss
Figure 10-3 External Clock Connections
Note: When using a system clock oscillator, carry out wiring in the broken line area in Figure 10-2 to prevent any effects from wiring capacities.
- Minimize the wiring length.
- Do not allow wiring to intersect with other signal conductors.
- Do not allow wiring to come near changing high current.
- Set the potential of the grounding position of the oscillator
capacitor to that of V
SS. Do not ground to any ground pat-
tern where high current is present.
- Do not fetch signals from the oscillator.
In addition, the HMS87C1X04B/08B/16B has an ability for the
external RC oscillated operation. It offers additional cost savings
for timing insensitive applications. The RC oscillator frequency
is a function of the supply voltage, the external resistor (R
and capacitor (C
) values, and the operating temperature.
EXT
EXT
)
SEP. 2004 Ver 1.03 41
HMS87C1X04B/08B/16B
The user needs to take into account variation due to tolerance of
external R and C components used.
Figure 10-4 shows how the RC combination is connected to the
HMS87C1X04B/08B/16B.
Vdd
R
EXT
C
EXT
f
÷4
XIN
X
IN
Cint ≈ 6pF
X
OUT
Figure 10-4 RC Oscillator Connections
External capacitor (C
) can be omitted for more cost saving.
EXT
However, the characteristics of external R only oscillation are
more variable than external RC oscillation.
V
DD
R
EXT
X
IN
The oscillator frequency, divided by 4, is output from the Xout
pin, and can be used for test purpose or to synchronize other logic.
To set the RC oscillation, it should be programmed RC_osc bit of
the configuration memory (CONFIG : 707Fh) to "1". ( Refer to
Section "21.3". )
In addition to external crystal/resonator and external RC/R oscillation, the HMS81C1X04B/08B/16B provides the internal 4MHz
oscillation. The internal 4MHz oscillation needs no external
parts.
Figure 10-6 shows the pin connections in case of using the internal 4MHz oscillation as the system clock.
V
DD
X
IN
f
÷4
XIN
X
OUT
Figure 10-6 Internal 4MHz Connections
f
÷4
XIN
X
OUT
Figure 10-5 R Oscillator Connections
C
≈ 6pF
INT
To use the internal 4MHz oscillation, it should be programmed
ONPb bit and IN_CLK bit of the configuration memory (CONFIG : 707FH) to “0” and “1” respectively. ( Refer to Section
"21.3". )
42 SEP. 2004 Ver 1.03
11. Basic Interval Timer
HMS87C1X04B/08B/16B
The HMS87C1X04B/08B/16B has one 8-bit Basic Interval Timer that is free-run, can not stop. Block diagram is shown in Figure
11-1 .The 8-bit Basic interval timer register (BITR) is increased
every internal count pulse which is divided by prescaler. Since
prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/
1024 of the oscillator frequency. As the count overflows from
to 00H, this overflow causes to generate the Basic interval
FF
H
timer interrupt. The BITIF is interrupt request flag of Basic interval timer.
When write “1” to bit BTCL of CKCTLR, BITR register is
cleared to “0” and restart to count-up. The bit BTCL becomes “0”
after one machine cycle by hardware.
If the STOP instruction executed after writing “1” to bit WAKEUP of CKCTLR, it goes into the wake-up timer mode. In this
mode, all of the block is halted except the oscillator, prescaler
RCWDT
BTS[2:0]
÷ 8
÷ 16
3
÷ 32
fxin
÷ 64
÷ 128
8
MUX
0
÷ 256
÷ 512
1
÷ 1024
(only fxin÷2048) and Timer0.
If the STOP instruction executed after writing “1” to bit RCWDT
of CKCTLR, it goes into the internal RC oscillated watchdog timer mode. In this mode, all of the block is halted except the internal
RC oscillator, Basic Interval Timer and Watchdog Timer. More
detail informations are explained in Power Saving Function. The
bit WDTON decides Watchdog Timer or the normal 7-bit timer
Note: All control bits of Basic interval timer are in CKCTLR
register which is located at same address of BITR (address
). Address ECH is read as BITR, written to CKCTLR.
EC
H
Therefore, the CKCTLR can not be accessed by bit manipulation instruction.
.
BTCL
Clear
BITR (8BIT)
BITIF
To Watchdog Timer
Basic Interval Timer
Interrupt
Internal RC OSC
Figure 11-1 Block Diagram of Basic Interval Timer
Clock Control Register
CKCTLR
Symbol Function Description
WAKEUP
RCWDT
WDTON
BTCL
- WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0
1 : Enables Wake-up Timer
0 : Disables Wake-up Timer
1 : Enables Internal RC Watchdog Timer
0 : Disables Internal RC Watchdog Time
1 : Enables Watchdog Timer
0 : Operates as a 7-bit Timer
1 : BITR is cleared and BTCL becomes “0” automatically
after one machine cycle, and BITR continue to count-up
Figure 11-2 CKCTLR: Clock Control Register
ADDRESS : ECH
RESET VALUE : -001_0111
Bit Manipulation Not Available
Basic Interval Timer Clock Selection
000 : fxin
001 : fxin
010 : fxin
011 : fxin
100 : fxin
101 : fxin
110 : fxin
111 : fxin
÷ 8
÷ 16
÷ 32
÷ 64
÷ 128
÷ 256
÷ 512
÷ 1024
SEP. 2004 Ver 1.03 43
HMS87C1X04B/08B/16B
12. TIMER / COUNTER
The HMS87C1X04B/08B/16B has four Timer/Counter registers.
Each module can generate an interrupt to indicate that an event
has occurred (i.e. timer match).
Timer 0 and Timer 1 can be used either the two 8-bit Timer/Counter or one 16-bit Timer/Counter by combining them. Also Timer
2 and Timer 3 are same. In this document, explain Timer 0 and
Timer 1 because Timer2 and Timer3 same with Timer 0 and Timer 1.
In the “timer” function, the register is increased every internal
clock input. Thus, one can think of it as counting internal clock
input. Since the least clock consists of 2 and the most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of
the oscillator frequency in Timer0. And Timer1 can use the same
clock source too. In addition, Timer1 has more fast clock source
(1/1 to 1/8).
In the “counter” function, the register is increased in response to
a 0-to-1 (rising edge) transition at its corresponding external input
pin, EC0(Timer 0) or EC1(Timer 2).
Timer 0(2) Mode Register
TM0(2)
CAP0
CAP2
T0CK[2:0]
T2CK[2:0]
- - CAPx TxCK2 TxCK1 TxCK0 TxCN TxST
Capture mode selection bit
0 : Disables Capture
1 : Enables Capture
Input clock selection
000 : fxin ÷ 2, 100 : fxin ÷ 128
001 : fxin
010 : fxin
011 : fxin
÷ 4, 101 : fxin ÷ 512
÷ 8, 110 : fxin ÷ 2048
÷ 32, 111 : External Event ( EC0(1) )
.
Note: In the external event counter function, the RA0/EC0
pin has not a schmitt trigger, but a normal input port. Therefore, it may be count more than input event signal if the
noise interfere in slow transition input signal .
In addition the “capture” function, the register is increased in response external interrupt same with timer function. When external interrupt edge input, the count register is captured into capture
data register CDRx.
Timer1 and Timer 3 are shared with “PWM” function and “Compare output” function
It has seven operating modes: “8-bit timer/counter”, “16-bit timer/counter”, “8-bit capture”, “16-bit capture”, “8-bit compare
output”, “16-bit compare output” and “10-bit PWM” which are
selected by bit in Timer mode register TMx as shown in Figure
12-1 and Table 12-1 .
ADDRESS : D0H (D6H for TM2)
RESET VALUE : --00_0000
T0CN
T2CN
T0ST
T2ST
Continue control bit
0 : Stop counting
1 : Start counting continuously
Start control bit
0 : Stop counting
1 : Counter register is cleared and start again
Timer 1(3) Mode Register
TM1(3)
POL PWM Output Polarity
16BIT 16-bit mode selection
PWM0E
PWM1E
CAP1
CAP3
POL 16BIT PWMxE CAPx TxCK1 TxCK0 TxCN TxST
0 : Duty active low
1 : Duty active high
0 : 8-bit mode
1 : 16-bit mode
PWM enable bit
0 : Disables PWM
1 : Enables PWM
Capture mode selection bit
0 : Disables Capture
1 : Enables Capture
T1CK[2:0]
T3CK[2:0]
T1CN
T3CN
T1ST
T3ST
.
Input clock selection
00 : fxin 10 : fxin ÷ 8
÷ 2 11 : using the Timer 0 clock
01 : fxin
Continue control bit
0 : Stop counting
1 : Start counting continuously
Start control bit
0 : Stop counting
1 : Counter register is cleared and start again
ADDRESS : D2H (D8H for TM3)
RESET VALUE : 0000_0000
Figure 12-1 Timer Mode Register (TMx, x = 0~3)
44 SEP. 2004 Ver 1.03
HMS87C1X04B/08B/16B
16BIT CAP0 CAP1 PWME T0CK[2:0] T1CK[1:0] PWMO TIMER 0 TIMER1
0 0 0 0 XXX XX 0 8-bit Timer 8-bit Timer
0 0 1 0 111 XX 0 8-bit Event Counter 8-bit Capture
0 1 0 0 XXX XX 1 8-bit Capture 8-bit Compare output
0X
1
0 1 XXX XX 1 8-bit Timer/Counter 10-bit PWM
1 0 0 0 XXX 11 0 16-bit Timer
1 0 0 0 111 11 0 16-bit Event Counter
1 1 X 0 XXX 11 0 16-bit Capture
1 0 0 0 XXX 11 1 16-bit Compare output
Table 12-1 Operating Modes of Timer 0 and Timer 1
1. X: The value “0” or “1” corresponding your operation.
12.1 8-bit Timer/Counter Mode
The HMS87C1X04B/08B/16B has four 8-bit Timer/Counters,
Timer 0, Timer 1, Timer 2 and Timer 3, as shown in Figure 12-2 .
The “timer” or “counter” function is selected by mode registers
TMx as shown in Figure 12-1 and Table 12-1 . To use as an 8-bit
timer/counter mode, bit CAP0 of TM0 is cleared to “0” and bits
16BIT of TM1 should be cleared to “0”(Table 12-1 ).
TM1
EC0
fxin
TM0
- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST
--0 XXXXX
POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST
X 000XXXX
X: The value “0” or “1” corresponding your operation.
T0ST
0 : Stop
1 : Clear and Start
T0 (8-bit)
CLEAR
Edge Detector
÷ 2
T0CK[2:0]
1
MUX
÷ 4
÷ 8
÷ 32
÷ 128
÷ 512
÷ 2048
÷
1
÷
2
÷
8
T1CK[1:0]
MUX
T0CN
TDR0 (8-bit)
T1ST
1
T1 (8-bit)
T1CN
TDR1 (8-bit)
COMPARATOR
0 : Stop
1 : Clear and Start
CLEAR
COMPARATOR
ADDRESS : D0H
RESET VALUE : --00_0000
ADDRESS : D2H
RESET VALUE : 0000_0000
T0IF
TIMER 0
INTERRUPT
F/F
T1IF
COMP0 PIN
TIMER 1
INTERRUPT
Figure 12-2 8-bit Timer / Counter Mode
These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock in-
SEP. 2004 Ver 1.03 45
HMS87C1X04B/08B/16B
put. The internal clock has a prescaler divide ratio option of 2, 4,
8, 32,128, 512, 2048 (selected by control bits T0CK2, T0CK1
and T0CK0 of register TM0) and 1, 2, 8 (selected by control bits
T1CK1 and T1CK0 of register TM1). In the Timer 0, timer register T0 increases from 00
until it matches TDR0 and then reset
H
to 00H. The match output of Timer 0 generates Timer 0 interrupt
(latched in T0F bit). As TDRx and Tx register are in same ad-
TDR1
t
8
7
6
5
Timer 1 (T1IF)
Interrupt
coun
~
~
0
Occur interrupt Occur interrupt Occur interrupt
-
up
4
3
2
1
dress, when reading it as a Tx, written to TDRx.
In counter function, the counter is increased every 0-to 1 (rising
edge) transition of EC0 pin. In order to use counter function, the
bit RA0 of the RA Direction Register RAIO is set to “0”. The
Timer 0 can be used as a counter by pin EC0 input, but Timer 1
can not.
n
n-1
~
~
9
P
CP
Interrupt period
= P
x (n+1)
CP
~
~
TIME
TDR1
Timer 1 (T1IF)
Interrupt
T1ST
Start & Stop
T1CN
Control count
Figure 12-3 Counting Example of Timer Data Registers
disable
clear & start
stop
~
~
Occur interrupt Occur interrupt
T1ST = 0
T1ST = 1
enable
~
~
T1CN = 0 T1CN = 1
up-count
Figure 12-4 Timer Count Operation
TIME
12.2 16-bit Timer/Counter Mode
The Timer register is being run with 16 bits. A 16-bit timer/coun- ter register T0, T1 are increased from 0000H until it matches
46 SEP. 2004 Ver 1.03
HMS87C1X04B/08B/16B
TDR0, TDR1 and then resets to 0000H. The match output generates Timer 0 interrupt not Timer 1 interrupt.
The clock source of the Timer 0 is selected either internal or external clock by bit T0CK2, T0CK1 and T0SL0.
- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST
--0 XXXXX
POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST
X 10011XX
T0CK[2:0]
1
MUX
T1 (8-bit)
TM1
EC0
TM0
Edge Detector
÷ 2
÷ 4
÷ 8
fxin
÷ 32
T0CN
÷ 128
÷ 512
÷ 2048
TDR1 (8-bit)
In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to “1” respectively.
ADDRESS : D0H
RESET VALUE : --00_0000
ADDRESS : D2H
RESET VALUE : 0000_0000
X: The value “0” or “1” corresponding your operation.
T0ST
0 : Stop
1 : Clear and Start
T0 (8-bit)
COMPARATOR
TDR0 (8-bit)
CLEAR
T0IF
F/F
TIMER 0
INTERRUPT
COMP0 PIN
Figure 12-5 16-bit Timer / Counter Mode
12.3 8-bit Compare Output (16-bit)
The HMS87C1X04B/08B/16B has a function of Timer Compare
Output. To pulse out, the timer match can goes to port
pin(COMP0) as shown in Figure 12-2 and Figure 12-5 . Thus,
pulse out is generated by the timer match. These operation is implemented to pin, RB4/COMP0/PWM.
This pin output the signal having a 50: 50 duty square wave, and
12.4 8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as
shown in Figure 12-6 .
As mentioned above, not only Timer 0 but Timer 1 can also be
used as a capture mode.
The Timer/Counter register is increased in response internal or
external input. This counting function is same with normal timer
mode, and Timer interrupt is generated when timer register T0
output frequency is same as below equation.
Oscillation Frequency
f
COMP
---------------------------------------------------------------------------------
=
2 Prescaler Value TD R 1 )+(××
In this mode, the bit PWMO of RB function register (RBFUNC)
should be set to “1”, and the bit PWME of timer1 mode register
(TM1) should be set to “0”.
In addition, 16-bit Compare output mode is available, also.
(T1) increases and matches TDR0 (TDR1).
In the capture mode, the timer interrupt is very useful when the
pulse width of captured signal is more wider than the maximum
period of Timer.
For example, in Figure 12-8 , the pulse width of captured signal
is wider than the timer data value (FFH) over 2 times. When external interrupt is occurred, the captured value (13H) is more little
than wanted value. It can be obtained correct value by counting
SEP. 2004 Ver 1.03 47
HMS87C1X04B/08B/16B
the number of timer overflow occurrence.
Timer/Counter still does the above, but with the added feature
that a edge transition at external input INTx pin causes the current
value in the Timer x register (T0,T1), to be captured into registers
CDRx (CDR0, CDR1), respectively. After captured, Timer x register is cleared and restarts by hardware.
It has three transition modes: “falling edge”, “rising edge”, “both
edge” which are selected by interrupt edge selection register
IEDS (Refer to External interrupt section). In addition, the transi-
TM0
TM1
EC0
- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST
--1 XXXXX
POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST
X 001XXXX
T0CK[2:0]
Edge Detector
1
÷ 2
MUX
÷ 4
÷ 8
fxin
÷ 32
T0CN
÷ 128
÷ 512
CAPTURE
÷ 2048
INT0
IEDS[1:0]
tion at INTx pin generate an interrupt.
Note: The CDRx, TDRx and Tx are in same address. In
the capture mode, reading operation read the CDRx, not Tx
because the reading path is opened to the CDRx, and
TDRx is read while writing operation executed.
ADDRESS : D0H
RESET VALUE : --00_0000
ADDRESS : D2H
RESET VALUE : 0000_0000
T0ST
0 : Stop
1 : Clear and Start
T0 (8-bit)
CDR0 (8-bit)
T0ST
TDR0 (8-bit)
0 : Stop
1 : Clear and Start
CLEAR
COMPARATOR
INT0IF
T0IF
INT 0
INTERRUPT
TIMER 0
INTERRUPT
1
T1CN
IEDS[3:2]
CAPTURE
T1 (8-bit)
CDR1 (8-bit)
TDR1 (8-bit)
CLEAR
COMPARATOR
INT1IF
T1IF
INT 1
INTERRUPT
TIMER 1
INTERRUPT
INT1
÷
1
÷
2
÷
8
MUX
T1CK[1:0]
Figure 12-6 8-bit Capture Mode
48 SEP. 2004 Ver 1.03
T0
Ext. INT0 Pin
Interrupt Request
(INT0F)
HMS87C1X04B/08B/16B
This value is loaded to CDR0
n
n-1
~
~
9
t
n
-cou
p
u
4
~
~
3
2
1
0
8
7
6
5
Interrupt Interval Period
~
~
TIME
Ext. INT0 Pin
Interrupt Request
(INT0F)
Ext. INT0 Pin
Interrupt Request
(INT0F)
Interrupt Request
(T0F)
T0
Delay
Capture
Clear & Start
(Timer Stop)
Figure 12-7 Input Capture Operation
Interrupt Interval Period = FFH + 01H + FFH +01H + 13H = 213H
00
FF
H
H
00
FF
H
H
13
H
Figure 12-8 Excess Timer Overflow in Capture Mode
SEP. 2004 Ver 1.03 49
HMS87C1X04B/08B/16B
12.5 16-bit Capture Mode
16-bit capture mode is the same as 8-bit capture, except that the
Timer register is being run will 16 bits.
The clock source of the Timer 0 is selected either internal or external clock by bit T0CK2, T0CK1 and T0CK0.
In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to “1” respectively.
TM0
TM1
EC0
fxin
INT0
- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST
--1 XXXXX
POL 16BIT PWME CAP1 T1CK1 T1CK0 T1CN T1ST
X 10X 11XX
X: The value “0” or “1” corresponding your operation.
Edge Detector
÷ 2
÷ 4
÷ 8
÷ 32
÷ 128
÷ 512
÷ 2048
T0CK[2:0]
MUX
IEDS[1:0]
1
T0CN
CAPTURE
CDR1
(8-bit)
T0ST
0 : Stop
1 : Clear and Start
T0 + T1 (16-bit)
TDR1
CDR0
(8-bit)
(8-bit)
COMPARATOR
TDR0
(8-bit)
Figure 12-9 16-bit Capture Mode
CLEAR
ADDRESS : D0H
RESET VALUE : --00_0000
ADDRESS : D2H
RESET VALUE : 0000_0000
T0IF
INT0IF
TIMER 0
INT 0
INTERRUPT
INTERRUPT
12.6 PWM Mode
The HMS87C1X04B/08B/16B has a two high speed PWM
(Pulse Width Modulation) functions which shared with Timer1
(Timer 3). In this document, it will be explained only PWM0.
In PWM mode, pin RB4/COMP0/PWM0 outputs up to a 10-bit
resolution PWM output. This pin should be configure as a PWM
output by setting “1” bit PWM0O in RBFUNC register. (PWM1
output by setting “1” bit PWM1O in RBFUNC)
The period of the PWM output is determined by the T1PPR
(PWM0 Period Register) and PWM0HR[3:2] (bit3,2 of PWM0
High Register) and the duty of the PWM output is determined by
the T1PDR (PWM0 Duty Register) and PWM0HR[1:0] (bit1,0 of
PWM0 High Register).
The user writes the lower 8-bit period value to the T1PPR and the
higher 2-bit period value to the PWM0HR[3:2]. And writes duty
value to the T1PDR and the PWM0HR[1:0] same way.
The T1PDR is configure as a double buffering for glitchless
PWM output. In Figure 12-10 , the duty data is transferred from
the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle)
PWM Period = [PWM0HR[3:2]T1PPR] X Source Clock
PWM Duty = [PWM0HR[1:0]T1PDR] X Source Clock
The relation of frequency and resolution is in inverse proportion.
Table 12-1 shows the relation of PWM frequency vs. resolution.
50 SEP. 2004 Ver 1.03
HMS87C1X04B/08B/16B
If it needed more higher frequency of PWM, it should be reduced
resolution.
Frequency
Resolution
T1CK[1:0] =
00(125nS)
T1CK[1:0] =
01(250nS)
T1CK[1:0] =
10(1uS)
10-bit 7.8KHz 3.9KHz 0.98KHZ
9-bit 15.6KHz 7.8KHz 1.95KHz
8-bit 31.2KHz 15.6KHz 3.90KHz
7-bit 62.5KHz 31.2KHz 7.81KHz
Table 12-1 PWM Frequency vs. Resolution at 8MHz
The bit POL of TM1 decides the polarity of duty cycle.
If the duty value is set same to the period value, the PWM output
is determined by the bit POL (1: High, 0: Low). And if the duty
value is set to “00H”, the PWM output is determined by the bit
POL (1: Low, 0: High).
It can be changed duty value when the PWM output. However the
changed duty value is output after the current period is over and
TM1
POL
16BIT
PWME
CAP1
T1CK1 T1CK0
it can be maintained the duty value at present output when
changed only period value shown as Figure 12-12 . As it were, the
absolute duty time is not changed in varying frequency. But the
changed period value must greater than the duty value.
Note: If changing the Timer1 to PWM function, the
timer should be stop and set to PWM mode (PWME
= 1) firstly, and then set period and duty register value. When user writes register values while timer is in
operation, these register could be set with certain values. If user sets the T1PPR, T1PDR register value
with PWM mode being disabled, the T1PPR and
T1PDR can not be accessed because these registers
act as TDR1 and T1/CDR1 register in non-PWM
mode.
Ex) LDM TM1,#0010_0000b
LDM T1PPR,#0EH
LDM T1PDR,#05H
LDM PWM0HR,#00H
LDM RBFUNC,#0001_1100B
LDM TM1,#1010_1011B
T1CN
T1ST
ADDRESS : D2H
RESET VALUE : 0000_0000
PWM0HR
fxin
X010
- - -
----
PWM0HR[3:2]
T1ST
T0 clock source
÷
1
÷
2
÷
8
T1CK[1:0]
MUX
0 : Stop
1 : Clear and Start
1
T1CN
Slave
PWM0HR[1:0]
Master
XXXX
-
PWM0HR3 PWM0HR2 PWM0HR1 PWM0HR0
XXXX
Period High
X: The value “0” or “1” corresponding your operation.
T1PPR(8-bit)
COMPARATOR
CLEAR
T1 (8-bit)
COMPARATOR
T1PDR(8-bit)
T1PDR(8-bit)
Duty High
SQ
R
POL
ADDRESS : D5H
RESET VALUE : ----_0000
Bit Manipulation Not Available
RB4/
PWM0
PWM0O
[RBFUNC.4]
Figure 12-10 PWM Mode
SEP. 2004 Ver 1.03 51
HMS87C1X04B/08B/16B
fxin
T1
PWM
POL=1
PWM
POL=0
01 02 03 04 05 7F 80 81 3FF 02 03
00
~
~
~
~
~
~
~
~
~
~
Duty Cycle [80H x 125nS = 16uS]
Period Cycle [3FFH x 125nS = 127.875uS, 7.8KHz]
~
~
~
~
~
~
~
~
~
~
0100
T1CK[1:0] = 00 (fxin)
PWM0HR = 0CH
T1PPR = FFH
T1PDR = 80H
T1CK[1:0] = 10 (1uS)
PWM0HR = 00H
T1PPR = 0EH
T1PDR = 05H
Source
clock
T1
PWM
POL=1
01
[05H x 1uS = 5uS]
02 03 04 05
Duty Cycle
Period
Duty
PWM0HR3 PWM0HR2
PWM0HR1 PWM0HR0
Figure 12-11 Example of PWM at 8MHz
Write T1PPR to 0AH
08 09 0B 0C 0D
06
T1PPR (8-bit)
1 1 FFH
T1PDR (8-bit)
00 80H
Period changed
0E
02 03 04 05 06
01
Duty Cycle
[05H x 1uS = 5uS]
07 08 09 0A0102 03 0407 0A
05
Duty Cycle
[05H x 1uS = 5uS]
Period Cycle [0EH x 1uS = 14uS, 71KHz]
Period Cycle [0AH x 1uS = 10uS, 100KHz]
Figure 12-12 Example of Changing the Period in Absolute Duty Cycle (@8MHz)
52 SEP. 2004 Ver 1.03
13. Serial Peripheral Interface
HMS87C1X04B/08B/16B
The Serial Peripheral Interface (SPI) module is a serial interface
useful for communicating with other peripheral of microcontrol-
SPI Mode Control Register
SIOM
POL Serial Clock Polarity Selection bit
SRDY Serial Ready Enable bit
SM[1:0] Serial Operation Mode Selection bits
SPI Data Register
SIOR
POL SRDY SM1 SM0 SCK1 SCK0 SIOST SIOSF
0 : Data Transmission at falling edge
(Received data latch at rising edge)
1 : Data Transmission at rising edge
(Received data latch at falling edge)
0 : Disable (RC3)
1 : Enable (SRDYIN
00 : Normal Port (RC4, RC5, RC6)
01 : Transmit Mode (SCK, RC5, SOUT)
10 : Receive Mode (SCK, SIN, RC6)
11 : Transmit & Receive Mode (SCK, SIN, SOUT)
/ SRDYOUT)
.
ler devices. These peripheral devices may be serial EEPROMs,
shift registers, display drivers, A/D converters, etc.
ADDRESS : E0H
RESET VALUE : 0000_0001
SCK[1:0] Serial Clock Selection bits
SIOST Serial Transmit Start bit
SIOSF Serial Transmit Status bit
00 : fxin ÷ 4
01 : fxin
÷ 16
10 : TMR2OV (Overflow of Timer 2)
11 : External Clock
0 : Disable
1 : Start (After one SCK, becomes “0”)
0 : During Transmission
1 : Finished
ADDRESS : E1H
RESET VALUE : Undefined
SOUT
SIN
SCK
SRDY
SM0
SM1
MSB LSB
SIOR
Octal Counter
POL
Polarity
SM1
SM0
SRDY
SCK1
SCK0
SPIF (Interrupt Request)
00
01
10
11
SCK[1:0]
R
Q
S
SIOST
fxin ÷ 4
fxin ÷ 16
TMR2OV
External Clock
2
From Control Circuit
To Control Circuit
Figure 13-1 SPI Registers and Block Diagram
SEP. 2004 Ver 1.03 53
HMS87C1X04B/08B/16B
The SPI allows 8-bits of data to be synchronously transmitted and
received. To accomplish communication, typically three pins are
used:
- Serial Data In RC5/SIN
- Serial Data Out RC6/SOUT
- Serial Clock RC4/SCK
In addition to those pins, a fourth pin may be used when in a master or a slave mode of operation:
- Serial Transfer Ready RC3/SRDYIN/SRDYOUT
SIOST
SCK
(POL=1)
SCK
(POL=0)
SOUT
SIN
SPIF
(SPI Int. Req)
D1 D2 D3 D4 D6 D7D0 D5
D1 D2 D3 D4 D6 D7D0 D5
The serial data transfer operation mode is decided by setting the
SM1 and SM0 of SPI Mode Control Register, and the transfer
clock rate is decided by setting the SCK1 and SCK0 of SPI Mode
Control Register as shown in Figure 13-1 . And the polarity of
transfer clock is selected by setting the POL.
The bit SRDY is used for master / slave selection. If this bit is set
to “1” and SCK[1:0] is set to “11”, the controller is performed to
slave controller. As it were, the port RC3 is served for SRDYOUT.
SRDY
SIOST
SCK
(POL=1)
SCK
(POL=0)
SOUT
SIN
SPIF
(SPI Int. Req)
Figure 13-2 SPI Timing Diagram (without SRDY
D1 D2 D3 D4 D6 D7D0 D5
D1 D2 D3 D4 D6 D7D0 D5
Figure 13-3 SPI Timing Diagram (with SRDY
control)
control)
54 SEP. 2004 Ver 1.03
14. Buzzer Output function
HMS87C1X04B/08B/16B
The buzzer driver consists of 6-bit binary counter, the buzzer register BUR and the clock selector. It generates square-wave which
is very wide range frequency (480 Hz~250 KHz at fxin = 4 MHz)
by user programmable counter.
Pin RB1 is assigned for output port of Buzzer driver by setting the
bit BUZO of RBFUNC to “1”.
The 6-bit buzzer counter is cleared and start the counting by writing signal to the register BUR. It is increased from 00H until it
matches 6-bit register BUR.
BUR
BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0
Input clock selection
00 : fxin
÷ 8
÷ 16
01 : fxin
÷ 32
10 : fxin
÷ 64
11 : fxin
Buzzer Period Data
÷ 8
fxin MUX
÷ 16
÷ 32
COUNTER (6-bit)
÷ 64
BUCK[1:0]
BUR (6-bit)
Also, it is cleared by counter overflow and count up to output the
square wave pulse of duty 50%.
The bit 0 to 5 of BUR determines output frequency for buzzer
driving. Frequency calculation is following as shown below.
f
BUZ
=
2 Prescaler Ratio BUR 1+()××
Oscillator Frequency
-----------------------------------------------------------------------------------
Hz()
The bits BUCK1, BUCK0 of BUR selects the source clock from
prescaler output.
ADDRESS : DEH
RESET VALUE : 1111_1111
Bit Manipulation Not Available
F/F
COMPARATOR
BUZO
[RBFUNC.1]
RB1/BUZ PIN
Figure 14-1 Buzzer Driver
SEP. 2004 Ver 1.03 55
HMS87C1X04B/08B/16B
15. ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion of an
analog input signal to a corresponding 8-bit digital value. The A/
D module has eight analog inputs, which are multiplexed into one
sample and hold. The output of the sample and hold is the input
into the converter, which generates the result via successive approximation.
The analog reference voltage is selected to V
or AVref by set-
DD
ting of the bit AVREFS in RBFUNC register. If external analog
reference AVref is selected, the bit ANSEL0 should not be set to
“1”, because this pin is used to an analog reference of A/D converter.
The A/D module has two registers which are the control register
ADCM and A/D result register ADCR. The ADCM register,
shown in Figure 15-2 , controls the operation of the A/D converter module. The port pins can be configure as analog inputs or digital I/O.
ADS[2:0]
RA7/AN7
ANSEL7
RA6/AN6
ANSEL6
RA5/AN5
111
110
101
To use analog inputs, each port is assigned analog input port by
setting the bit ANSEL[7:0] in RAFUNC register. And selected
the corresponding channel to be converted by setting ADS[2:0].
The processing of conversion start when the start bit ADST is set
to “1”. After one cycle, it is cleared by hardware. The register
ADCR contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCR, the A/
D conversion status bit ADSF is set to “1”, and the A/D interrupt
flag ADIF is set. The block diagram of the A/D module is shown
in Figure 15-1 . The A/D status bit, ADSF is set automatically
when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 10 uS (at
fxin=8 MHz).
A/D Result Register
ADCR(8-bit)
ADDRESS : EBH
RESET VALUE : Undefined
RA4/AN4
RA3/AN3
RA2/AN2
RA1/AN1
RB0/AN0/AVref
VDD Pin
ANSEL5
ANSEL4
ANSEL3
ANSEL2
ANSEL1
ANSEL0 (RAFUNC.0)
1
0
AVREFS (RBFUNC.0)
100
011
010
001
000
ADEN
Sample & Hold
S/H
Resistor
Ladder
Circuit
Figure 15-1 A/D Converter Block Diagram
Successive
Approximation
Circuit
ADIF
A/D Interrupt
56 SEP. 2004 Ver 1.03
ADCM
A/D Control Register
- - ADEN ADS2 ADS1 ADS0 ADST ADSF
HMS87C1X04B/08B/16B
ADDRESS : EAH
RESET VALUE : --00_0001
Reserved
A/D Result Data Register
ADCR
ADCR7 ADCR6 ADCR5 ADCR4 ADCR3 ADCR2 ADCR1 ADCR0
ENABLE A/D CONVERTER
A/D INPUT CHANNEL SELECT
ANALOG REFERENCE SELECT
A/D START (ADST = 1)
Analog Channel Select
000 : Channel 0 (RB0/AN0)
001 : Channel 1 (RA1/AN1)
010 : Channel 2 (RA2/AN2)
011 : Channel 3 (RA3/AN3)
100 : Channel 4 (RA4/AN4)
101 : Channel 5 (RA5/AN5)
110 : Channel 6 (RA6/AN6)
111 : Channel 7 (RA7/AN7)
A/D Enable bit
1 : A/D Conversion is enable
0 : A/D Converter module shut off
and consumes no operation current
Figure 15-2 A/D Converter Registers
A/D Converter Cautions
(1) Input range of AN0 to AN7
The input voltage of AN0 to AN7 should be within the specification range. In particular, if a voltage above VDD (or AVref) or below VSS is input (even if within the absolute maximum rating
range), the conversion value for that channel can not be determinate. The conversion values of the other channels may also be affected.
(2) Noise countermeasures
In order to maintain 8-bit resolution, attention must be paid to
noise on pins AVref (or VDD) and AN0 to AN7. Since the effect
increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 15-4 in order to reduce noise.
A/D Status bit
0 : A/D Conversion is in process
1 : A/D Conversion is completed
A/D Start bit
1 : A/D Conversion is started
After 1 cycle, cleared to “0”
0 : Bit force to zero
ADDRESS : EBH
RESET VALUE : Undefined
NOP
ADSF = 1
YES
READ ADCR
NO
Analog
Input
100~1000pF
AN0~AN7
Figure 15-4 Analog Input Pin Connecting Capacitor
(3) Pins AN0/RB0 and AN1/RA1 to AN7/RA7
Figure 15-3 A/D Converter Operation Flow
The analog input pins AN0 to AN7 also function as input/output
SEP. 2004 Ver 1.03 57
HMS87C1X04B/08B/16B
port (PORT RA and RB0) pins. When A/D conversion is performed with any of pins AN0 to AN7 selected, be sure not to execute a PORT input instruction while conversion is in progress,
as this may reduce the conversion resolution.
Also, if digital pulses are applied to a pin adjacent to the pin in the
process of A/D conversion, the expected A/D conversion value
may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion.
(4) AVref
pin input impedance
A series resistor string of approximately 10KΩ is connected between the AVref pin and the VSS pin.
Therefore, if the output impedance of the reference voltage
source is high, this will result in parallel connection to the series
resistor string between the AVref
pin and the VSS pin, and there
will be a large reference voltage error.
58 SEP. 2004 Ver 1.03
16. INTERRUPTS
HMS87C1X04B/08B/16B
The HMS87C1X04B/08B/16B interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of
IRQH, IRQL, Interrupt Edge Selection Register (IEDS), priority
circuit and Master enable flag(“I” flag of PSW). The configuration of interrupt circuit is shown in Figure 16-1 and Interrupt priority is shown in Table 16-1 .
The External Interrupts INT0, INT1, INT2 and INT3 can each be
transition-activated (1-to-0, 0-to-1 and both transition).
The flags that actually generate these interrupts are bit INT0IF,
INT1IF, INT2IF and INT3IF in Register IRQH. When an external interrupt is generated, the flag that generated it is cleared by
Internal bus line
IENH
External Int. 0
External Int. 1
External Int. 2
External Int. 3
IEDS
Timer 0
Timer 1
IEDS
Timer 2
Timer 3
IRQH
INT0IF
INT1IF
T0IF
T1IF
INT2IF
INT3IF
T2IF
T3IF
7
6
5
4
3
2
1
0
the hardware when the service routine is vectored to only if the
interrupt was transition-activated.
The Timer 0, Timer 1, Timer 2 and Timer 3 Interrupts are generated by T0IF, T1IF, T2IF and T3IF, which are set by a match in
their respective timer/counter register. The AD converter Interrupt is generated by ADIF which is set by finishing the analog to
digital conversion. The Watch dog timer Interrupt is generated by
WDTIF which set by a match in Watch dog timer register (when
the bit WDTON is set to “0”). The Basic Interval Timer Interrupt
is generated by BITIF which is set by a overflowing of the Basic
Interval Timer Register(BITR).
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction.When it goes interrupt service,
I-flag is cleared by hardware, thus any other
Interrupt Enable
Register (Higher byte)
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
I Flag
Priority Control
Interrupt Master
Enable Flag
Release STOP
To CPU
A/D Converter
WDT
BIT
SPI
IRQL
ADIF
WDTIF
BITIF
SPIF
7
6
5
5
IENL
Interrupt Enable
Register (Lower byte)
Internal bus line
Interrupt
Vector
Address
Generator
Figure 16-1 Block Diagram of Interrupt Function
SEP. 2004 Ver 1.03 59
HMS87C1X04B/08B/16B
The interrupts are controlled by the interrupt master enable flag
I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL)
and the interrupt request flags (in IRQH, IRQL) except Power-on
reset and software BRK interrupt.
Interrupt enable registers are shown in Figure 16-2 . These registers are composed of interrupt enable flags of each interrupt
source, these flags determines whether an interrupt will be accepted or not. When enable flag is “0”, a corresponding interrupt
source is prohibited. Note that PSW contains also a master enable
bit, I-flag, which disables all interrupts at once.
Interrupt Enable Register High
IENH
IENL
INT0E INT1E T0E T1E INT2E INT3E T2E T3E
Interrupt Enable Register Low
ADE WDTE BITE SPIE - - - -
Reset/Interrupt Symbol Priority Vector Addr.
Hardware Reset
External Interrupt 0
External Interrupt 1
Timer 0
Timer 1
External Interrupt 2
External Interrupt 3
Timer 2
Timer 3
A/D Converter
Watch Dog Timer
Basic Interval Timer
Serial Interface
RESET
INT0
INT1
Timer 0
Timer 1
INT2
INT3
Timer 2
Timer 3
A/D C
WDT
BIT
SPI
10
11
12
1
2
3
4
5
6
7
8
9
FFFE
FFFA
FFF8
FFF6
FFF4
FFF2
FFF0
FFEE
FFEC
FFEA
FFE8
FFE6
FFE4
Table 16-1 Interrupt Priority
ADDRESS : E2H
RESET VALUE : 0000_0000
ADDRESS : E3H
RESET VALUE : 0000_----
H
H
H
H
H
H
H
H
H
H
H
H
H
Enables or disables the interrupt individually
If flag is cleared, the interrupt is disabled.
0 : Disable
1 : Enable
Interrupt Request Register High
IRQH
IRQL
INT0IF INT1IF T0IF T1IF INT2IF INT3IF T2IF T3IF
Interrupt Request Register Low
ADIF WDTIF BITIF SPIF - - - -
Shows the interrupt occurrence
0 : Not occurred
1 : Interrupt request is occurred
Figure 16-2 Interrupt Enable Registers and Interrupt Request Registers
When an interrupt is occurred, the I-flag is cleared and disable
any further interrupt, the return address and PSW are pushed into
the stack and the PC is vectored to. Once in the interrupt service
routine the source(s) of the interrupt can be determined by polling
the interrupt request flag bits.
ADDRESS : E4H
RESET VALUE : 0000_0000
ADDRESS : E5H
RESET VALUE : 0000_----
The interrupt request flag bit(s) must be cleared by software before re-enabling interrupts to avoid recursive interrupts. The Interrupt Request flags are able to be read and written.
60 SEP. 2004 Ver 1.03
16.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the
interrupt latch is cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 8 f
OSC
(2 µs at f
after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt
return instruction [RETI].
XIN
=4MHz)
HMS87C1X04B/08B/16B
2. Interrupt request flag for the interrupt source accepted is
cleared to “0”.
3. The contents of the program counter (return address)
and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.
Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to
“0” to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following
interrupts is temporarily disabled.
System clock
Instruction Fetch
Address Bus
Data Bus
Internal Read
Internal Write
PC
Not used
SP SP-1
PCH PCL
Interrupt Processing Step Interrupt Service Task
4. The entry address of the interrupt service program is
read from the vector table address and the entry address
is loaded to the program counter.
5. The instruction stored at the entry address of the interrupt service program is executed.
SP-2 V.H. New PC
PSW ADL OP codeADH
V.L.
V.L.
V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.
Figure 16-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
Basic Interval Timer
Vector Table Address
0FFE6
0FFE7
Correspondence between vector table address for BIT interrupt
and the entry address of the interrupt service program.
012
0E3
H
H
H
H
0E312
0E313
Entry Address
0E
H
2E
H
H
H
A interrupt request is not accepted until the I-flag is set to “1”
even if a requested interrupt has higher priority than that of the
current interrupt being serviced.
When nested interrupt service is required, the I-flag should be set
to “1” by “EI” instruction in the interrupt service program. In this
case, acceptable interrupt sources are selectively enabled by the
individual interrupt enable flags.
Saving/Restoring General-purpose Register
During interrupt acceptance processing, the program counter and
the program status word are automatically saved on the stack, but
accumulator and other registers are not saved itself. These registers are saved by the software if necessary. Also, when multiple
interrupt services are nested, it is necessary to avoid using the
same data memory area for saving registers.
The following method is used to save/restore the general-purpose
registers.
SEP. 2004 Ver 1.03 61
HMS87C1X04B/08B/16B
Example: Register save using push and pop instructions
INTxx: PUSH A
PUSH X
PUSH Y
interrupt processing
POP Y
POP X
POP A
RETI
;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.
;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN
General-purpose register save/restore using push and pop instructions;
16.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which has
the lowest priority order.
Interrupt vector address of BRK is shared with the vector of
TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from
TCALL 0.
Each processing step is determined by B-flag as shown in Figure
16-4 .
BRK or
TCALL0
main task
acceptance of
interrupt
interrupt return
INTERRUPT
ROUTINE
interrupt
service task
B-FLAG
=1
BRK
RETI
saving
registers
restoring
registers
=0
TCALL0
ROUTINE
RET
Figure 16-4 Execution of BRK/TCALL0
16.3 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time
simultaneously, an internal polling sequence determines by hardware which request is serviced.
However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the Iflag is cleared to disable any further interrupt. But as user sets Iflag in interrupt routine, some further interrupt can be serviced
even if certain interrupt is in progress.
62 SEP. 2004 Ver 1.03
Main Program
service
Occur
TIMER1 interrupt
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable “EI” in the TIMER1 routine.
Occur
INT0
TIMER 1
service
enable INT0
disable other
EI
enable INT0
enable other
INT0
service
HMS87C1X04B/08B/16B
Example: Even though Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend.
TIMER1: PUSH A
PUSH X
PUSH Y
LDM IENH,#80H ;Enable INT0 only
LDM IENL,#0 ;Disable other
EI ;Enable Interrupt
:
:
:
:
:
:
LDM IENH,#0FFH ;Enable all interrupts
LDM IENL,#0F0H
POP Y
POP X
POP A
RETI
Figure 16-5 Execution of Multi Interrupt
SEP. 2004 Ver 1.03 63
HMS87C1X04B/08B/16B
16.4 External Interrupt
The external interrupt on INT0, INT1, INT2 and INT3 pins are
edge triggered depending on the edge selection register IEDS (address 0E6
) as shown in Figure 16-6 .
H
The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge.
INT0 pin
INT1 pin
INT2 pin
INT3 pin
Ext. Interrupt Edge Selection
Register
IESR
WW
WWWWWW
INT2 edge select
00 : Int. disable
01 : falling
10 : rising
11 : both
INT3 edge select
00 : Int. disable
01 : falling
10 : rising
11 : both
Noise Canceller
Noise Canceller
[0E6
edge selection
]
H
Noise Canceller
Noise Canceller
IEDS
Figure 16-6 External Interrupt Block Diagram
Example: To use as an INT0 and INT2
ADDRESS : 0E6
RESET VALUE : 0000_0000
H
;**** Set port as an input port RB2,RD0
;**** Set port as an interrupt port
INT0 edge select
00 : Int. disable
01 : falling
10 : rising
11 : both
INT1 edge select
00 : Int. disable
01 : falling
10 : rising
11 : both
;**** Set Falling-edge Detection
Response Time
The INT0, INT1,INT2 and INT3 edge are latched into INT0IF,
INT1IF, INT2IF and INT3IF at every machine cycle. The values
are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service
routine will be the next instruction to be executed. The DIV itself
takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the
service routine.
INT0IF
INT1IF
INT2IF
INT3IF
INT0 INTERRUPT
INT1 INTERRUPT
INT2 INTERRUPT
INT3 INTERRUPT
:
:
LDM RBIO,#1111_1011B
LDM RDIO,#1111_1110B
;
LDM RBFUNC,#04H
LDM RDFUNC,#01H
;
LDM IEDS,#0001_0001B
:
:
:
64 SEP. 2004 Ver 1.03
shows interrupt response timings.
HMS87C1X04B/08B/16B
Interrupt
goes
active
max. 12 f
Interrupt
latched
8 f
OSC
OSC
Interrupt
processing
Interrupt
routine
Figure 16-7 Interrupt Response Timing Diagram
SEP. 2004 Ver 1.03 65
HMS87C1X04B/08B/16B
17. WATCHDOG TIMER
The purpose of the watchdog timer is to detect the malfunction
(runaway) of program due to external noise or other causes and
return the operation to the normal condition.
The watchdog timer has two types of clock source.
The first type is an on-chip RC oscillator which does not require
any external components. This RC oscillator is separate from the
external oscillator of the Xin pin. It means that the watchdog timer will run, even if the clock on the Xin pin of the device has been
stopped, for example, by entering the STOP mode.
The other type is a prescaled system clock.
The watchdog timer consists of 7-bit binary counter and the
watchdog timer data register. When the value of 7-bit binary
counter is equal to the lower 7 bits of WDTR, the interrupt request flag is generated. This can be used as WDT interrupt or reset the CPU in accordance with the bit WDTON.
Note: Because the watchdog timer counter is enabled after clearing Basic Interval Timer, after the bit WDTON set to
“1”, maximum error of timer is depend on prescaler ratio of
Basic Interval Timer.
The 7-bit binary counter is cleared by setting WDTCL(bit7 of
Clock Control Register
CKCTLR
Watchdog Timer Register
WDTR
- WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0
- 0X1XXXX
WDTCL 7-bit Watchdog Counter Register
WDTR) and the WDTCL is cleared automatically after 1 machine cycle.
The RC oscillated watchdog timer is activated by setting the bit
RCWDT as shown below.
:
LDM CKCTLR,#3FH; enable the RC-osc WDT
LDM WDTR,#0FFH; set the WDT period
STOP ; enter the STOP mode
NOP
NOP ; RC-osc WDT running
:
The RC oscillation period is vary with temperature, V
DD
and
process variations from part to part (approximately, 40~120uS).
The following equation shows the RC oscillated watchdog timer
time-out.
T
RCWDT
=CLK
×28×[
WDTR.6~0]+(CLK
RC
RC
×28)/2
where, CLKRC = 40~120uS
In addition, this watchdog timer can be used as a simple 7-bit timer by interrupt WDTIF. The interval of watchdog timer interrupt
is decided by Basic Interval Timer. Interval equation is as below.
T
= [WDTR.6~0] × Interval of BIT
WDT
ADDRESS : ECH
RESET VALUE : -001_0111
Bit Manipulation Not Available
ADDRESS : EDH
RESET VALUE : 0111_1111
Bit Manipulation Not Available
3
MUX
RCWDT
0
1
BTCL
Clear
BITR (8-bit)
WDTR (8-bit)
7-bit Counter
BITIF
WDTCL WDTON
OFD
Overflow Detection
Basic Interval Timer
Interrupt
1
0
CPU RESET
Watchdog Timer
Interrupt Request
fxin
÷ 8
÷ 16
÷ 32
÷ 64
8
÷ 128
÷ 256
÷ 512
÷ 1024
Internal RC OSC
BTS[2:0]
Figure 17-1 Block Diagram of Watchdog Timer
66 SEP. 2004 Ver 1.03
18. Power Saving Mode
HMS87C1X04B/08B/16B
For applications where power consumption is a critical factor,
this device provides two kinds of power saving functions, STOP
mode and Wake-up Timer mode.
The power saving function is activated by execution of STOP in-
Peripheral STOP Wake-up Timer
RAM Retain Retain
Control Registers Retain Retain
I/O Ports Retain Retain
CPU Stop Stop
Timer0, Timer2 Stop Operation
Oscillation Stop Oscillation
Prescaler Stop ÷ 2048 only
Entering Condition
[WAKEUP]
Release Sources
RESET, RCWDT, INT0~3,
01
EC0~1, SPI
Table 18-1 Power Saving Mode
18.1 Stop Mode
In the Stop mode, the on-chip oscillator is stopped. With the clock
frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their
respective port data register, port direction registers. Oscillator
stops and the systems internal operations are all held up.
• The states of the RAM, registers, and latches valid
immediately before the system is put in the STOP
state are all held.
• The program counter stop the address of the
instruction to be executed after the instruction
“STOP” which starts the STOP operating mode.
The Stop mode is activated by execution of STOP instruction
after clearing the bit WAKEUP of CKCTLR to “0”. (This
register should be written by byte operation. If this register is
set by bit manipulation instruction, for example “set1” or
“clr1” instruction, it may be undesired operation)
In the Stop mode of operation, V
power consumption. Care must be taken, however, to ensure that
is not reduced before the Stop mode is invoked, and that
V
DD
VDD is restored to its normal operating level, before the Stop
mode is terminated.
can be reduced to minimize
DD
struction after setting the corresponding status (WAKEUP) of
CKCTLR.
Table 18-1 shows the status of each Power Saving Mode.
RESET, RCWDT, INT0~3,
EC0~1, SPI, TIMER0, TIMER2
The reset should not be activated before VDD is restored to its
normal operating level, and must be held active long enough to
allow the oscillator to restart and stabilize.
Note: After STOP instruction, at least two or more NOP instruction should be written
Ex) LDM CKCTLR,#0000_1110B
STOP
NOP
NOP
In the STOP operation, the dissipation of the power associated
with the oscillator and the internal hardware is lowered; however,
the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point
should be little current flows when the input level is stable at the
power voltage level (V
gets higher than the power voltage level (by approximately 0.3 to
0.5V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor,
requiring to fix the level by pull-up or other means.
); however, when the input level
DD/VSS
SEP. 2004 Ver 1.03 67
HMS87C1X04B/08B/16B
Release the STOP mode
The exit from STOP mode is hardware reset or external interrupt.
Reset re-defines all the Control registers but does not change the
on-chip RAM. External interrupts allow both on-chip RAM and
Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution starting with the instruction following the STOP
instruction. It will not vector to interrupt service routine. (refer to
Figure 18-1 )
By reset, exit from Stop mode is shown in Figure 18-3 .When exit
from Stop mode by external interrupt, enough oscillation stabilization time is required to normal operation. Figure 18-2 shows
the timing diagram. When release the Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00
. The count overflow is set to start normal operation. There-
FF
H
fore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec).
This guarantees that oscillator has started and stabilized..
until
H
STOP
INSTRUCTION
Corresponding Interrupt
Enable Bit (IENH, IENL)
Enable Bit PSW[2]
Master Interrupt
STOP Mode
Interrupt Request
IEXX
=1
STOP Mode Release
I-FLAG
=1
Interrupt Service Routine
=0
=0
Oscillator
(X
pin)
IN
Internal
Clock
External
Interrupt
BIT
Counter
N-1
N-2
Normal Operation
Next
INSTRUCTION
Figure 18-1 STOP Releasing Flow by Interrupts
~
~
~
~
~
~
STOP Instruction Execution
N+1NN+2
STOP Mode Normal Operation
Clear Basic Interval Timer
~
~
~
~
~
~
~
~
~
~
00 01 FE FF 00 00
Stabilizing Time
> 20mS
t
ST
~
~
Figure 18-2 Timing of STOP Mode Release by External Interrupt
68 SEP. 2004 Ver 1.03
HMS87C1X04B/08B/16B
STOP Mode
Oscillator
(X
pin)
IN
Internal
Clock
RESET
Internal
RESET
STOP Instruction Execution
Time can not be control by software
~
~
~
~
~
~
~
~
Figure 18-3 Timing of STOP Mode Release by RESET
18.2 STOP Mode using Internal RCWDT
In the STOP mode using Internal RC-Oscillated Watchdog Timer, the on-chip oscillator is stopped. But internal RC oscillation
circuit is oscillated in this mode. The on-chip RAM and Control
registers are held. The port pins out the values held by their respective port data register, port direction registers.
The Internal RC-Oscillated Watchdog Timer mode is activated by setting the bit RCWDT of CKCTLR to “1”. ( This register should be written by byte operation. If this register is set
by bit manipulation instruction, for example “set1” or “clr1”
instruction, it may be undesired operation )
Note: After STOP instruction, at least two or more NOP instruction should be written
Ex) LDM WDTR,#1111_1111B
LDM CKCTLR,#0010_1110B
STOP
NOP
NOP
Release the STOP mode using internal RCWDT
The exit from STOP mode using Internal RC-Oscillated Watchdog Timer is hardware reset or external interrupt. Reset re-defines all the Control registers but does not change the on-chip
RAM. External interrupts allow both on-chip RAM and Control
~
~
~
~
~
~
~
~
~
~
Stabilizing Time
= 64mS @4MHz
t
ST
registers to retain their values.
If I-flag = 1, the normal interrupt response takes place. In this
case, if the bit WDTON of CKCTLR is set to “0” and the bit
WDTE of IENH is set to “1”, the device will execute the watchdog timer interrupt service routine.(Figure 18-4 ) However, if the
bit WDTON of CKCTLR is set to “1”, the device will generate
the internal RESET signal and execute the reset processing. (Figure 18-5 )
If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.( refer to Figure 18-1 )
When exit from STOP mode using Internal RC-Oscillated
Watchdog Timer by external interrupt, the oscillation stabilization time is required to normal operation. Figure 18-4 shows the
timing diagram. When release the Internal RC-Oscillated Watchdog Timer mode, the basic interval timer is activated on wake-up.
It is increased from 00
until FFH . The count overflow is set to
H
start normal operation. Therefore, before STOP instruction, user
must be set its relevant prescaler divide ratio to have long enough
time (more than 20msec). This guarantees that oscillator has
started and stabilized.
By reset, exit from STOP mode using internal RC-Oscillated
Watchdog Timer is shown in Figure 18-5 .
SEP. 2004 Ver 1.03 69
HMS87C1X04B/08B/16B
Oscillator
(X
pin)
IN
Internal
RC Clock
Internal
Clock
External
Interrupt
(or WDT Interrupt)
BIT
Counter
N-2
N-1
~
~
~
~
~
~
STOP Instruction Execution
N+1NN+2
Clear Basic Interval Timer
~
~
~
~
~
~
~
~
~
~
00 01 FE FF 00 00
~
~
Figure 18-4 STOP Mode Releasing by External Interrupt or WDT Interrupt(using RCWDT)
Oscillator
(X
pin)
IN
Internal
RC Clock
Internal
Clock
RESET
RESET by WDT
Internal
RESET
Normal Operation
STOP Mode Normal Operation
STOP Mode
~
~
~
~
~
~
~
~
STOP Instruction Execution
Time can not be control by software
Stabilizing Time
t
> 20mS
ST
~
~
~
Stabilizing Time
t
= 64mS @4MHz
ST
~
~
~
~
~
~
~
Figure 18-5 STOP Mode Releasing by RESET(using RCWDT)
18.3 Wake-up Timer Mode
In the Wake-up Timer mode, the on-chip oscillator is not stopped.
Except the Prescaler(only 2048 devided ratio), Timer0 and
Timer2, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their
respective port data register, port direction registers.
The Wake-up Timer mode is activated by execution of STOP
instruction after setting the bit WAKEUP of CKCTLR to
“1”. (This register should be written by byte operation. If this
register is set by bit manipulation instruction, for example
“set1” or “clr1” instruction, it may be undesired operation)
70 SEP. 2004 Ver 1.03
HMS87C1X04B/08B/16B
Note: After STOP instruction, at least two or more NOP instruction should be written
Ex) LDM TDR0,#0FFH
LDM TM0,#0001_1011B
LDM CKCTLR,#0100_1110B
STOP
NOP
NOP
In addition, the clock source of timer0 and timer2 should be selected to 2048 devided ratio. Otherwise, the wake-up function can
not work. And the timer0 and timer2 can be operated as 16-bit
timer with timer1 and timer3(refer to timer function). The period
of wake-up function is varied by setting the timer data register0,
TDR0 or timer data register2, TDR2.
~
Oscillator
(X
pin)
IN
CPU
Clock
Interrupt
Request
STOP Instruction
Execution
Normal Operation
~
~
~
~
~
~
~
Wake-up Timer Mode
(stop the CPU clock)
Release the Wake-up Timer mode
The exit from Wake-up Timer mode is hardware reset,
Timer0(Timer2) overflow or external interrupt. Reset re-defines
all the Control registers but does not change the on-chip RAM.
External interrupts and Timer0(Timer2) overflow allow both onchip RAM and Control registers to retain their values.
If I-flag = 1, the normal interrupt response takes place. If I-flag =
0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service
routine.(refer to Figure 18-1 )
When exit from Wake-up Timer mode by external interrupt or
timer0(Timer2) overflow, the oscillation stabilizing time is not
required to normal operation. Because this mode do not stop the
on-chip oscillator shown as Figure 18-6 .
Normal Operation
Do not need Stabilizing Time
Figure 18-6 Wake-up Timer Mode Releasing by External Interrupt or Timer0(Timer2) Interrupt
18.4 Minimizing Current Consumption
The Stop mode is designed to reduce power consumption. To
minimize current drawn during Stop mode, the user should turnoff output drivers that are sourcing or sinking current, if it is practical.
Note: In the STOP operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation
of the STOP feature. This point should be little current flows
when the input level is stable at the power voltage level
(V
); however, when the input level becomes higher
DD/VSS
than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the highimpedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means.
It should be set properly that current flow through port doesn't
exist.
First conseider the setting to input mode. Be sure that there is no
current flow after considering its relationship with external
circuit. In input mode, the pin impedance viewing from external
MCU is very high that the current doesn’t flow.
But input voltage level should be V
or VDD. Be careful that if
SS
unspecified voltage, i.e. if uncertain voltage level (not VSSor
) is applied to input pin, there can be little current (max. 1mA
V
DD
at around 2V) flow.
If it is not appropriate to set as an input mode, then set to output
mode considering there is no current flow. Setting to High or Low
is decided considering its relationship with external circuit. For
example, if there is external pull-up resistor then it is set to output
mode, i.e. to High, and if there is external pull-down register, it is
set to low.
SEP. 2004 Ver 1.03 71
HMS87C1X04B/08B/16B
INPUT PIN
V
DD
i
GND
X
Weak pull-up current flows
INPUT PIN
i
Very weak current flows
internal
pull-up
V
DD
V
DD
O
V
DD
X
OPEN
O
Figure 18-7 Application Example of Unused Input Port
When port is configure as an input, input level should
be closed to 0V or 5V to avoid power consumption.
OPEN
i=0
i=0
O
O
V
DD
GND
OUTPUT PIN
ON
ON
OFF
i
GND
X
In the left case, much current flows from port to GND.
OFF
O
ON
OFF
Figure 18-8 Application Example of Unused Output Port
O
OPEN
V
DD
OUTPUT PIN
V
DD
ON
OFF
X
In the left case, Tr. base current flows from port to GND.
To avoid power consumption, there should be low output
to the port.
L
OFF
i
GND
ON
O
i=0
GND
V
DD
L
72 SEP. 2004 Ver 1.03
19. RESET
HMS87C1X04B/08B/16B
The reset input is the RESET pin, which is the input to a Schmitt
Trigger. A reset is accomplished by holding the RESET pin low
for at least 8 oscillator periods, while the oscillator running. After
reset, 64ms (at 4 MHz) add with 7 oscillator periods are required
to start execution as shown in Figure 19-1 .
~
Oscillator
pin)
(X
IN
~
RESET
~
ADDRESS
BUS
?
~
~
DATA
BUS
?
~
Stabilizing Time
= 64mS at 4MHz
t
ST
Internal RAM is not affected by reset. When V
is turned on,
DD
the RAM content is indeterminate. Therefore, this RAM should
be initialized before reading or testing it.
Initial state of each register is shown as Table 8-1 .
~
1 2 3 4 5 6 7
~
~
??
~
?
FFFE FFFF
Start
~
OP
~
??
RESET Process Step
FE?ADL
ADH
MAIN PROGRAM
Figure 19-1 Timing Diagram after RESET
A power-up example where RESET
is connected to external reset
circuit is shown in Figure 19-2 . VDD is allowed to rise and stabi-
V
DD
RESET
INTERNAL
RESET
Stabilizing Time
Basic Interval Timer Start
Figure 19-2 Time-out Sequence On Power-up
Note: When the device starts normal operation (exits the
reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be meet to ensure operation. If these conditions are not met, the device must be
held in reset until the operating conditions are met
lize before bringing RESET high. The chip will actually come out
of reset and start the Basic Interval Timer after RESET goes high.
SEP. 2004 Ver 1.03 73
HMS87C1X04B/08B/16B
V
V
DD
DD
D
R
C
Figure 19-3 EXTERNAL POWERON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
R1
RESET
- External Power-On Reset circuit is required only if VDD
power-up is too slow. The diode D helps discharge the
capacitor quickly when VDD powers down.
- R < 40 kΩ is recommended to make sure that voltage
drop across R does not violate the device electrical specifi-
.
cation
- R1 = 100Ω to 1kΩ will limit any current flowing into
RESET from external capacitor C in the event of RESET
pin breakdown due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).
• Address Fail Reset
The Address Fail Reset is the function to reset the system by
checking abnormal address or unwished address cauased by external noise, which couldn’t be returned to normal operation and
External RESET
ADDRESS FAIL RESET
WDT RESET
WDT RESETen
PFD RESET
PFD RESETen
Execution
Address Fail is occurred
Address Fail RESET
Internal RESET
would be malfunction state. If the CPU fetch the instruction from
beyond area not in main user area address C000
~FFFFH, in that
H
case the address fail reset is occurred.
Internal RESET
~
~
~
~
~
~
Figure 19-4 The opreation of Address Fail RESET
74 SEP. 2004 Ver 1.03
20. POWER FAIL PROCESSOR
HMS87C1X04B/08B/16B
The HMS87C1X04B/08B/16B has an on-chip power fail detection circuitry to immunize against power noise. A configuration
register, PFDR, can enable (if clear/programmed) or disable (if
set) the Power-fail Detect circuitry. If V
falls below 2.1~3.0V
DD
range for longer than 50 nS, the Power fail situation may reset
Power Fail Detector Register
PFDR
- - - - PFDOPR PFDIS PFDM PFS
Reserved
Figure 20-1 Power Fail Detector Register
MCU according to PFS bit of PFDR.
As below PFDR register is not implemented on the in-circuit emulator, user can not experiment with it. Therefore, after final development of user program, this function may be experimented..
ADDRESS : EFH
RESET VALUE : ----0100
Power Fail Status
0 : Normal Operate
1 : This bit force to “1” when
Power fail was detected
Operation Mode
0 : System Clock Freeze during power fail
1 : MCU will be reset during power fail
Disable Flag
0 : Power fail detection enable
1 : Power fail detection disable
PFD Operation Disable Flag
0 : PFD operation enable
1 : PFD operation disable
RESET VECTOR
PFS =1
NO
RAM CLEAR
INITIALIZE RAM DATA
INITIALIZE ALL PORTS
INITIALIZE REGISTERS
FUNTION
EXECUTION
YES
Skip the
initial routine
Figure 20-2 Example S/W of RESET by Power fail
SEP. 2004 Ver 1.03 75
HMS87C1X04B/08B/16B
V
DD
Internal
RESET
V
DD
When PFDM = 1
When PFDM = 0
Internal
RESET
V
DD
Internal
RESET
V
DD
System
Clock
V
DD
System
Clock
t < 64mS
64mS
64mS
64mS
PFVDDMAX
PFV
MIN
DD
MAX
PFV
DD
PFV
MIN
DD
PFV
MAX
DD
MIN
PFV
DD
PFVDDMAX
PFV
MIN
DD
PFV
MAX
DD
PFV
MIN
DD
Figure 20-3 Power Fail Processor Situations
76 SEP. 2004 Ver 1.03
21. COUNTERMEASURE OF NOISE
21.1 Oscillation Noise Protector
The Oscillation Noise Protector(ONP) is used to supply stable internal system clock by excluding the noise which could be entered into oscillator and recovery the oscillation fail. This
function could be enabled or disabled by the bit[5] of Configuration Memory (707Fh).
The ONP function is like below.
- Recovery the oscillation wave crushed or loss caused
HMS87C1X04B/08B/16B
by high frequency noise.
- Change system clock to the internal oscillation clock
when the high frequency noise is continuing.
- Change system clock to the internal oscillation clock
when the X
IN/XOUT
oscillation is stopped except by stop instruction and
the low frequency noise is entered.
is shorted or opened, the main
XIN
ONPb = 0
LF_on = 1
IN_CLK = 0
XIN
XIN_NF
HF Noise
Observer
Xin_opt
ONPb
LF_on
High Frq. Noise
Noise Cancel
HF Noise
Canceller
1
OFP
Mux
0
S
LF Noise
Observer
en
PS10
INT_CLK 8 periods
(250ns × 8 =2us)
~
~
Low Frq. Noise or
Oscillation Fail
~
~
XIN_NF
Internal
OSC
CLK_CHG
o/f
CK
en
0
CLK
Changer
1
S
INT_CLK
en
OFP
(8-Bit counter)
PS10(INT_CLK/512) 256 periods
(250ns × 512 × 256 =33 ms)
~
~
~
~
F
INTERNAL
ONPb
IN_CLK
INT_CLK reset
INT_CLK
~
~
~
~
~
~
~
~
~
~
OFP_EN
~
CHG_END
~
~
~
CLK_CHG
Clock Change End(INT_CLK to XIN))
~
~
f
INTERNAL
Clock Change Start(XIN to INT_CLK)
~
~
Figure 21-1 Block Diagram of ONP & OFP and Respective Wave Forms
SEP. 2004 Ver 1.03 77
HMS87C1X04B/08B/16B
21.2 Oscillation Fail Processor
The oscillation fail processor (OFP) can change the clock source
from external to internal oscillator when the osicllation fail occured. This function could be enabled or disabled by the bit[3] of
Configuration Memory (707Fh).
And this function can recover the external clock source when the
external clock is recovered to normal state.
Xin_opt Option
The XIN_opt is the function to control the amount of noise to be
cancelled which entered into noise canceller in ONP, according
to external oscillator frequency. If the amount of noise to be cancelled is selected to 40nS by X
cancels the clock over 12.5MHz as a noise. And if the amount of
noise to be cancelled is selected to 80nS by X
_opt, the noise canceller in ONP
IN
_opt, the noise
IN
21.3 Device Configuration Area
The Program Memory is consisted of configuration memory and
user program memory. The configration memory is used to set
the environment of system. The device configuration area can be
programmed or left unprogrammed to select device configuration
canceller in ONP cancels the clock over 6.25MHz as a noise.
IN_CLK Option
The IN_CLK Option is the function to operate the device by using the internal oscillator clock in ONP block as system clock.
There is no need to connect the x-tal, resonator, RC and R externaly. The user only to connect the X
could be selected by the bit[4] of Configuration Memory
(707Fh). The characteristics of internal oscillator clock has the
period of 250ns±5% at V
=5V and 250ns±10% at whole oper-
DD
ating voltage. After selecting the IN_CLK Option, the period of
internal oscillator clock could be checked by X
clock divided the internal oscillator clock by 4.
such as oscillation noise protector, internal 4MHz, amount of
noise to be cancelled,security, RC-oscillation select bits. This
area is not accessible during normal execution but is readable and
writable during program / verify.
pin to VDD. This function
IN
outputting
OUT
CONFIG
ADDRESS
CONFIG
AFR1
AFR0 ONPb IN_CLK
LF_on
Xin_opt Lock RC_osc
Figure 21-2 Device Configuration Area
Option Bit Data Operation Remark
AFR1,0
ONPb
IN_CLK
LF_on
Xin_opt
Lock
RC_osc
01 or 10 Address Fail RESET Disable
00 or 11 Address Fail RESET Enable
0 OSC Noise Protector Enable
1 OSC Noise Protector Disable
0 Use the Inter 4MHz clock as the Device Osc Disable
1 Use the Inter 4MHz clock as the Device Osc Enable
0 ONP Low Pass Filter (clock changer) Disable
1 ONP Low Pass Filter (clock changer) Enable
0 40nS noise cancel (Xin : 8MHz)
1 80nS noise cancel (Xin : 4MHz)
0 EPROM Data Read/Pgm Enable
1 EPROM Data Read/Pgm Disable
0 X-tal or Ceramic Oscillation
RESET the system when illegal
address generated
OSC Noise Protector(ONP)
Operation En/Disable Bit
Using the internal 4MHz clock
without external clock
Change the Inter clock when
oscillation failed
To select the amount of noise of
to be cancelled in ONP OSC.
Unlock or lock EPROM data
Select oscillation source
1 External RC/ R Oscillation
707F
H
Table 21-1 Explanation of configration bits
78 SEP. 2004 Ver 1.03
21.4 Examples of ONP
ONPb IN_CLK LF_on Xin_opt Description
0 0 0 0 40ns noise canceller
0 0 0 1 80ns noise canceller
HMS87C1X04B/08B/16B
0010
0011
0 1 X X using internal 4MHz oscillator regardless of external oscillator
1 X X X ONP disable
40ns noise canceller + change the clock source from external to internal
4MHz clock when oscillation failure occured.
80ns noise canceller + change the clock source from external to internal
4MHz clock when oscillation failure occured
Table 21-1 Examples of ONP
SEP. 2004 Ver 1.03 79
HMS87C1X04B/08B/16B
22. OTP PROGRAMMING
22.1 EPROM Mode
Mode
A_D7~A_D0 CTL0 CTL1 CTL2
Pin Description
EPROM
Enable
Remarks
PP
V
DD
V
Program
Read
Write
Verify
High Addr.
(A15~A8)
Low Addr.
(A7~A0)
Data In
(D7~D0)
Data Out
(D7~D0)
High Addr.
(A15~A8)
Low Addr.
(A7~A0)
Data Out
(D7~D0)
V
DD
0 0 0 H 11.5V 5.0V
0 0 1 H 11.5V 5.0V
0 1 1 H 11.5V 5.0V
0 1 0 H 11.5V 5.0V
0 0 0 H 11.5V 5.0V
0 0 1 H 11.5V 5.0V
0 1 0 H 11.5V 5.0V
Table 22-1 Description of EPROM mode
A_D4
A_D5
A_D6
A_D7
CTL0
CTL1
CTL2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
NC
20
19
18
17
16
15
A_D3
A_D2
A_D1
A_D0
V
SS
V
PP
EPROM Enable
Figure 22-1 Pin Assignment
80 SEP. 2004 Ver 1.03
HMS87C1X04B/08B/16B
Pin No. User Mode EPROM MODE
14XXB 15XXB 16XXB 17XXB 18XXB Pin Name Pin Name Description
1 1 1 1 39 RA4 (AN4) A_D4
2 2 2 2 40 RA5 (AN5) A_D5 A13 A5 D5
3 3 3 3 41 RA6 (AN6) A_D6 A14 A6 D6
Address Input
Data Input/Output
4 4 4 4 42 RA7 (AN7) A_D7 A15 A7 D7
555543
V
DD
V
DD
Connect to V
DD
6 6 6 6 44 RB0 (AVref/AN0) CTL0
77771RB1 (BUZ) CTL1
Read/Write Control
Address/Data Control
88882RB2 (INT0) CTL2
19 25 33 35 31 X
20 26 34 36 32 X
IN
OUT
21 27 35 37 33 RESET
22 28 36 38 34 V
SS
EPROM Enable High Active, Latch Address in falling edge
NC No connection
V
PP
V
SS
Programming Power (0V, 11.5V)
Connect to V
SS
25 29 37 39 35 RA0 (EC0) A_D0
26 30 38 40 36 RA1 (AN1) A_D1 A9 A1 D1
27 31 39 41 37 RA2 (AN2) A_D2 A10 A2 D2
Address Input
Data Input/Output
28 32 40 42 38 RA3 (AN3) A_D3 A11 A3 D3
Other Pins - V
DD
Connect to V
DD
A12 A4 D4
(5.0V)
(0V)
A8 A0 D0
(5.0V)
Table 22-2 Pin Description in EPROM Mode
SEP. 2004 Ver 1.03 81
HMS87C1X04B/08B/16B
T
SET1
EPROM
Enable
T
VPPS
V
PP
T
VDDS
T
T
V
VPPR
HLD1
IHP
T
DLY1
T
SET1
T
HLD2
~
~
~
~
T
DLY2
~
~
~
~
CTL0
CTL1
CTL2
A_D7~
A_D0
V
DD
EPROM
Enable
0V
0V
0V
V
DD1H
T
~
~
~
~
V
T
CD1
HA
High 8bit
Address
Input
T
CD1
V
DD1H
LA
Low 8bit
Address
Input
~
~
~
~
DATA IN
~
~
Write Mode
DD1H
T
CD1
DATA
OUT
Verify
T
CD1
Low 8bit
Address
Input
Figure 22-2 Timing Diagram in Program (Write & Verify) Mode
After input a high address,
output data following low address input
SET1
T
HLD1
V
IHP
T
DLY1
T
VPPS
~
~
~
~
~
~
~
~
LA DATA IN
~
~
Write Mode
Another high address step
DATA
OUT
Verify
V
PP
CTL0
CTL1
CTL2
A_D7~
A_D0
V
DD
T
0V
0V
0V
V
VDDS
DD2H
T
VPPR
T
CD1
HA
High 8bit
Address
Input
T
CD2
V
DD2H
LA
Low 8bit
Address
Input
V
DD2H
T
CD1
DATA
DATA
Output
T
CD2
LA DATA
Low 8bit
Address
Input
DATA
Output
HA
High 8bit
Address
Input
LA
Low 8bit
Address
Input
DATA
DATA
Output
Figure 22-3 Timing Diagram in READ Mode
82 SEP. 2004 Ver 1.03
Parameter Symbol MIN TYP MAX Unit
Programming Supply Current
Supply Current in EPROM Mode
Level during Programming
V
PP
Level in Program Mode
V
DD
VDD Level in Read Mode
CTL2~0 High Level in EPROM Mode
CTL2~0 Low Level in EPROM Mode
A_D7~A_D0 High Level in EPROM Mode
A_D7~A_D0 Low Level in EPROM Mode
Saturation Time
V
DD
Setup Time
V
PP
VPP Saturation Time
EPROM Enable Setup Time after Data Input
EPROM Enable Hold Time after T
EPROM Enable Delay Time after T
SET1
HLD1
EPROM Enable Hold Time in Write Mode
EPROM Enable Delay Time after T
HLD2
CTL2,1 Setup Time after Low Address input and Data input
CTL1 Setup Time before Data output in Read and Verify Mode
Table 22-3 AC/DC Requirements for Program/Read Mode
I
I
VDDP
V
V
DD1H
V
DD2H
V
V
V
V
T
VDDS
T
VPPR
T
VPPS
T
T
T
T
T
T
T
VPP
IHP
IHC
ILC
IHAD
ILAD
SET1
HLD1
DLY1
HLD2
DLY2
CD1
CD2
HMS87C1X04B/08B/16B
--50mA
--20mA
11.25 11.5 11.75 V
4.75 5 5.25 V
-3.0-V
0.8V
DD
--
0.9V
DD
--
1--mS
--1mS
1--mS
--V
0.2V
DD
V
--V
0.1V
DD
V
200±10% nS
500±10% nS
200±10% nS
50±10% nS
200±10% nS
100±10% nS
100±10% nS
SEP. 2004 Ver 1.03 83
HMS87C1X04B/08B/16B
START
Next address location
Set VDD=5.0V
Set VPP=11.5V
Verify blank
First Address Location
N=1
EPROM Write
50uS program time
Verify pass
NO
Last address
DD1H
IHP
NO
YES
Report
Programming failure
NO
YES
N ≤ 5
N=N+1
NO
YES
YES
EPROM Write
50uS program time
READ @VDD=3.0V
READ pass
YES
END
NO
Figure 22-4 Programming Flow Chart
84 SEP. 2004 Ver 1.03
START
HMS87C1X04B/08B/16B
Next address location
Set VDD=V
Set VPP=V
First Address Location
NO
Last address
Report Read OK
VDD=0V
V
=0V
PP
END
DD2H
IHP
YES
Figure 22-5 Reading Flow Chart
Verify for all address
SEP. 2004 Ver 1.03 85
APPENDIX
APPENDIX
A. INSTRUCTION MAP
0000000000010100010020001103001000400101050011006001110701000080100109010100A010110B011000C011010D011100E01111
LOW
HIGH
000 -
001 CLRC
010 CLRG
011 DI
100 CLRV
101 SETC
110 SETG
111 EI
SET1
dp.bit
BBS
A.bit,rel
BBS
dp.bit,rel
ADC
ADCdpADC
#imm
SBC
#imm
CMP
#imm
OR
#immORdpORdp+XOR!abs
AND
#imm
EOR
#imm
LDA
#imm
LDM
dp,#imm
dp+X
SBCdpSBC
dp+X
CMPdpCMP
dp+X
ANDdpAND
dp+X
EORdpEOR
dp+X
LDAdpLDA
dp+X
STAdpSTA
dp+X
ADC
ASLAASLdpTCALL0SETA1
!abs
SBC
ROLAROLdpTCALL2CLRA1
!abs
CMP
LSRALSRdpTCALL4NOT1
!abs
RORARORdpTCALL6OR1
AND
EOR
INCAINCdpTCALL8AND1
!abs
DECADECdpTCALL10EOR1
!abs
LDA
!abs
STA
!abs
LDYdpTCALL12LDC
TXA
STYdpTCALL14STC
TAX
HMS87C1X04B/08B/16B
BITdpPOPAPUSH
.bit
COMdpPOPXPUSHXBRA
.bit
TSTdpPOPYPUSHYPCALL
M.bit
OR1B
AND1B
EOR1B
LDCB
M.bit
CMPXdpPOP
CMPYdpCBNE
DBNEdpXMA
LDXdpLDX
STXdpSTX
PSW
dp+X
dp+X
dp+Y
dp+Y
PUSH
PSW
TXSP
TSPX
XCN DAS
XAX STOP
0F
BRK
A
rel
Upage
RET
INC
X
DEC
X
HIGH
100001010001111001012100111310100141010115101101610 11117110 0018110 0119110101A110 111B1110 01C1110 11D111101E11111
LOW
ADC
ADC
ADC
ADC
ASL
ASL
000
001
010
011
100
101
110
111
BPL
rel
BVC
rel
BCC
rel
BNE
rel
BMI
rel
BVS
rel
BCS
rel
BEQ
rel
CLR1
dp.bit
BBC
A.bit,rel
BBC
dp.bit,rel
{X}
!abs+Y
[dp+X]
[dp]+Y
SBC
SBC
SBC
CMP
AND
EOR
LDA
STA
SBC
[dp]+Y
CMP
[dp]+Y
AND
[dp]+Y
EOR
[dp]+Y
LDA
[dp]+Y
STA
[dp]+Y
{X}
!abs+Y
[dp+X]
CMP
CMP
{X}
!abs+Y
[dp+X]
OR
{X}OR!abs+YOR[dp+X]OR[dp]+Y
AND
AND
{X}
!abs+Y
[dp+X]
EOR
EOR
{X}
!abs+Y
[dp+X]
LDA
LDA
{X}
!abs+Y
[dp+X]
STA
STA
{X}
!abs+Y
[dp+X]
!abs
ROL
!abs
LSR
!abs
ROR
!abs
INC
!abs
DEC
!abs
LDY
!abs
STY
!abs
TCALL1JMP
dp+X
ROL
TCALL3CALL
dp+X
LSR
TCALL
dp+X
ROR
dp+X
INC
dp+X
DEC
dp+X
LDY
dp+X
STY
dp+X
5
TCALL7DBNEYCMPX
TCALL
9
TCALL11XMA
TCALL13LDA
TCALL15STA
MUL
BIT
!abs
!abs
TEST
!abs
!abs
TCLR1
!abs
!abs
CMPY
DIV
!abs
XMAdpDECWdpDEC
{X}
LDX
{X}+
!abs
STX
{X}+
!abs
ADDWdpLDX
SUBWdpLDY
CMPWdpCMPX
LDYAdpCMPY
INCWdpINC
STYA
dp
CBNE
dp
1F
#imm
#imm
#imm
#imm
JMP
[!abs]
JMP
[dp]
CALL
[dp]
RETI
TAY
Y
TYA
Y
XAY DAA
XYX NOP
SEP. 2004 Ver 1.03 i
HMS87C1X04B/08B/16B
B. INSTRUCTION SET
1. ARITHMETIC/ LOGIC OPERATION
OP
NO. MNEMONIC
1 ADC #imm 04 2 2 Add with carry.
2ADC dp 05 2 3
3 ADC dp + X 06 2 4
4 ADC !abs 07 3 4
5 ADC !abs + Y 15 3 5
6 ADC [ dp + X ] 16 2 6
7 ADC [ dp ] + Y 17 2 6
8ADC { X } 14 1 3
9 AND #imm 84 2 2 Logical AND
AND dp
10
11 AN D dp + X 86 2 4
12 AND !abs 87 3 4
13 AND !abs + Y 95 3 5
14 AND [ dp + X ] 96 2 6
15 AND [ dp ] + Y 97 2 6
16 AND { X } 94 1 3
17 ASL A 08 1 2 Arithmetic shift left
18 ASL dp 09 2 4
19 ASL dp + X 19 2 5
20 ASL !abs 18 3 5
21 CMP #imm 44 2 2 Compare accumulator contents with memory contents
22 CMP dp 45 2 3 ( A ) - ( M )
23 CMP dp + X 46 2 4
24 CMP !abs 47 3 4 N-----ZC
25 CMP !abs + Y 55 3 5
26 CMP [ dp + X ] 56 2 6
27 CMP [ dp ] + Y 57 2 6
28 CMP { X } 54 1 3
29 CMPX #imm 5E 2 2 Compare X contents with memory contents
30 CMPX dp 6C 2 3 ( X ) - ( M ) N-----ZC
31 CMPX !abs 7C 3 4
32 CMPY #imm 7E 2 2 Compare Y contents with memory contents
33 CMPY dp 8C 2 3 ( Y ) - ( M ) N-----ZC
34 CMPY !abs 9C 3 4
35 COM dp 2C 2 4 1’S Complement : ( dp ) ← ~( dp ) N-----Z-
36 DAA DF 1 3 Decimal adjust for addition N-----ZC
37 DAS CF 1 3 Decimal adjust for subtraction N-----ZC
38 DEC A A8 1 2 Decrement N-----Z-
39 DEC dp A9 2 4 M ← ( M ) - 1
40 DEC dp + X B9 2 5 N-----Z-
41 DEC !abs B8 3 5
42 DEC X AF 1 2
43 DEC Y BE 1 2
44 DIV 9B 1 12 Divide : YA / X Q: A, R: Y NV--H-Z-
BYTENOCYCLE
CODE
85 2 3
NO
A ← ( A ) + ( M ) + C
A ← ( A ) ∧ ( M )
OPERATION
C 7654321
FLAG
NVGBHIZC
NV--H-ZC
N-----Z-
0
“0”
N-----ZC
ii SEP. 2004 Ver 1.03
OP
NO. MNEMONIC
BYTENOCYCLE
CODE
45 EOR #imm A4 2 2
46 EOR dp A5 2 3
47 EOR dp + X A6 2 4
48 EOR !abs A7 3 4
49 EOR !abs + Y B5 3 5
50 EOR [ dp + X ] B6 2 6
51 EOR [ dp ] + Y B7 2 6
52 EOR { X } B4 1 3
53 INC A 88 1 2
54 INC dp 89 2 4
55 INC dp + X 99 2 5
56 INC !abs 98 3 5
57 INC X 8F 1 2
58 INC Y 9E 1 2
59 LSR A 48 1 2
60 LSR dp 49 2 4
61 LSR dp + X 59 2 5
62 LSR !abs 58 3 5
63 MUL 5B 1 9
64 OR #imm 64 2 2
65 OR dp 65 2 3
66 OR dp + X 66 2 4
67 OR !abs 67 3 4
68 OR !abs + Y 75 3 5
69 OR [ dp + X ] 76 2 6
70 OR [ dp ] + Y 77 2 6
71 OR { X } 74 1 3
72 ROL A 28 1 2
73 ROL dp 29 2 4
74 ROL dp + X 39 2 5
75 ROL !abs 38 3 5
76 ROR A 68 1 2
77 ROR dp 69 2 4
78 ROR dp + X 79 2 5
79 ROR !abs 78 3 5
80 SBC #imm 24 2 2
81 SBC dp 25 2 3
82 SBC dp + X 26 2 4
83 SBC !abs 27 3 4
84 SBC !abs + Y 35 3 5
85 SBC [ dp + X ] 36 2 6
86 SBC [ dp ] + Y 37 2 6
87 SBC { X } 34 1 3
88 TST dp 4C 2 3
89 XCN CE 1 5
NO
OPERATION
Exclusive OR
A ← ( A ) ⊕ ( M )
Increment
M ← ( M ) + 1
Logical shift right
“0”
Multiply : YA ← Y × A
Logical OR
A ← ( A ) ∨ ( M )
Rotate left through carry
Rotate right through carry
Subtract with carry
A ← ( A ) - ( M ) - ~( C )
Test memory contents for negative or zero
( dp ) - 00
H
Exchange nibbles within the accumulator
A
↔ A3~A
7~A4
0
HMS87C1X04B/08B/16B
NVGBHIZC
0
C7654321
0C 7654321
0C7654321
N-----ZC
N-----ZC
N-----ZC
NV--HZC
FLAG
N-----Z-
N-----Z-
N-----Z-
N-----Z-
N-----Z-
N-----Z-
N-----Z-
SEP. 2004 Ver 1.03 iii
HMS87C1X04B/08B/16B
2. REGISTER / MEMORY OPERATION
OP
NO. MNEMONIC
1 LDA #imm C4 2 2
2 LDA dp C5 2 3
3 LDA dp + X C6 2 4
4 LDA !abs C7 3 4
5 LDA !abs + Y D5 3 5
6 LDA [ dp + X ] D6 2 6
7 LDA [ dp ] + Y D7 2 6
8LDA { X } D4 1 3
9 LDA { X }+ DB 1 4
10 LDM dp,#imm E4 3 5
11 LDX #imm 1E 2 2
12 LDX dp CC 2 3
13 LDX dp + Y CD 2 4
14 LDX !abs DC 3 4
15 LDY #imm 3E 2 2
16 LDY dp C9 2 3
17 LDY dp + X D9 2 4
18 LDY !abs D8 3 4
19 STA dp E5 2 4
20 STA dp + X E6 2 5
21 STA !abs E7 3 5
22 STA !abs + Y F5 3 6
23 STA [ dp + X ] F6 2 7
24 STA [ dp ] + Y F7 2 7
25 STA { X } F4 1 4
26 STA { X }+ FB 1 4
27 STX dp EC 2 4
28 STX dp + Y ED 2 5
29 STX !abs FC 3 5
30 STY dp E9 2 4
31 STY dp + X F9 2 5
32 STY !abs F8 3 5
33 TAX E8 1 2
34 TAY 9F 1 2
35 TSPX AE 1 2
36 TXA C8 1 2
37 TXSP 8E 1 2
38 TYA BF 1 2
39 XAX EE 1 4
40 XAY DE 1 4
41 XMA dp BC 2 5
42 XMA dp+X AD 2 6
43 XMA {X} BB 1 5
44 XYX FE 1 4
BYTENOCYCLE
CODE
NO
Load accumulator
A ← ( M )
X- register auto-increment : A ← ( M ) , X ← X + 1
Load memory with immediate data : ( M ) ← imm
Load X-register
X ← ( M )
Load Y-register
Y ← ( M )
Store accumulator contents in memory
( M ) ← A
X- register auto-increment : ( M ) ← A, X ← X + 1
Store X-register contents in memory
( M ) ← X
Store Y-register contents in memory
( M ) ← Y
Transfer accumulator contents to X-register : X ← A
Transfer accumulator contents to Y-register : Y ← A
Transfer stack-pointer contents to X-register : X ← sp
Transfer X-register contents to accumulator: A ← X
Transfer X-register contents to stack-pointer: sp ← X
Transfer Y-register contents to accumulator: A ← Y
Exchange X-register contents with accumulator :X ↔ A
Exchange Y-register contents with accumulator :Y ↔ A
Exchange memory contents with accumulator
( M ) ↔ A
Exchange X-register contents with Y-register : X ↔ Y
OPERATION
FLAG
NVGBHIZC
N-----Z-
--------
N-----Z-
N-----Z-
--------
--------
--------
N-----Z-
N-----Z-
N-----Z-
N-----Z-
N-----Z-
N-----Z-
--------
--------
N-----Z-
--------
iv SEP. 2004 Ver 1.03
3. 16-BIT OPERATION
NO. MNEMONIC
1ADDW dp 1D 2 5
2CMPW dp 5D 2 4
3 DECW dp BD 2 6
4 INCW dp 9D 2 6
5LDYA dp 7D 2 5
6STYA dp DD 2 5
7SUBW dp 3D 2 5
4. BIT MANIPULATION
NO. MNEMONIC
1
AND1 M.bit
2
AND1B M.bit
3
BIT dp
4
BIT !abs
5
CLR1 dp.bit
6
CLRA1 A.bit
7
CLRC
8
CLRG
9
CLRV
10
EOR1 M.bit
11
EOR1B M.bit
12
LDC M.bit
13
LDCB M.bit
14
NOT1 M.bit
15
OR1 M.bit
16
OR1B M.bit
17
SET1 dp.bit
18
SETA1 A.bit
19
SETC
20
SETG
21
STC M.bit
22
TCLR1 !abs
23 TSET1 !abs 3C 3 6
HMS87C1X04B/08B/16B
OP
BYTENOCYCLE
CODE
OP
BYTENOCYCLE
CODE
8B 3 4 Bit AND C-flag : C ← ( C ) ∧ ( M .bit )
8B 3 4 Bit AND C-flag and NOT : C ← ( C ) ∧ ~( M .bit )
0C 2 4 Bit test A with memory :
1C 3 5
y1 2 4 Clear bit : ( M.bit ) ← “0”
2B 2 2 Clear A bit : ( A.bit )← “0”
20 1 2 Clear C-flag : C ← “0”
40 1 2 Clear G-flag : G ← “0”
80 1 2 Clear V-flag : V ← “0”
AB 3 5 Bit exclusive-OR C-flag : C ← ( C ) ⊕ ( M .bit )
AB 3 5 Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕ ~(M .bit)
CB 3 4 Load C-flag : C ← ( M .bit )
CB 3 4 Load C-flag with NOT : C ← ~( M .bit )
4B 3 5 Bit complement : ( M .bit ) ← ~( M .bit )
6B 3 5 Bit OR C-flag : C ← ( C ) ∨ ( M .bit )
6B 3 5 Bit OR C-flag and NOT : C ← ( C ) ∨ ~( M .bit )
x1 2 4 Set bit : ( M.bit ) ← “1”
0B 2 2 Set A bit : ( A.bit ) ← “1”
A0 1 2 Set C-flag : C ← “1”
C0 1 2 Set G-flag : G ← “1”
EB 3 6 Store C-flag : ( M .bit ) ← C
5C 3 6
NO
16-Bits add without carry
YA ← ( YA ) + ( dp +1 ) ( dp )
Compare YA contents with memory pair contents :
(YA) − (dp+1)(dp)
Decrement memory pair
( dp+1)( dp) ← ( dp+1) ( dp) - 1
Increment memory pair
( dp+1) ( dp) ← ( dp+1) ( dp ) + 1
Load YA
YA ← ( dp +1 ) ( dp )
Store YA
( dp +1 ) ( dp ) ← YA
16-Bits substact without carry
YA ← ( YA ) - ( dp +1) ( dp)
NO
Z ← ( A ) ∧ ( M ) , N ← ( M
Test and clear bits with A :
A - ( M ) , ( M ) ← ( M ) ∧ ~( A )
Test and set bits with A :
A - ( M ) , ( M ) ← ( M ) ∨ ( A )
OPERATION
OPERATION
) , V ← ( M6 )
7
FLAG
NVGBHIZC
NV--H-ZC
N-----ZC
N-----Z-
N-----Z-
N-----Z-
--------
NV--H-ZC
FLAG
NVGBHIZC
-------C
-------C
MM----Z-
--------
--------
-------0
--0-----
-0--0---
-------C
-------C
-------C
-------C
--------
-------C
-------C
--------
--------
-------1
--1-----
--------
N-----Z-
N-----Z-
SEP. 2004 Ver 1.03 v
HMS87C1X04B/08B/16B
5. BRANCH / JUMP OPERATION
NO. MNEMONIC
1
BBC A.bit,rel
2
BBC dp.bit,rel
3
BBS A.bit,rel
4
BBS dp.bit,rel
5
BCC rel
6
BCS rel
7
BEQ rel
8
BMI rel
9
BNE rel
10
BPL rel
11
BRA rel
12
BVC rel
13
BVS rel
14
CALL !abs
15
CALL [dp]
16
CBNE dp,rel
17
CBNE dp+X,rel
18
DBNE dp,rel
19
DBNE Y,rel
20
JMP !abs
21
JMP [!abs]
22
JMP [dp]
23
PCALL upage
24
TCALL n
CODE
OP
BYTENOCYCLE
NO
y2 2 4/6
y3 3 5/7
x2 2 4/6
x3 3 5/7
50 2 2/4
D0 2 2/4
F0 2 2/4
90 2 2/4
70 2 2/4
10 2 2/4
2F 2 4
30 2 2/4
B0 2 2/4
3B 3 8
5F 2 8
FD 3 5/7
8D 3 6/8
AC 3 5/7
7B 2 4/6
1B 3 3
1F 3 5
3F 2 4
4F 2 6
nA 1 8
OPERATION
Branch if bit clear :
if ( bit ) = 0 , then pc ← ( pc ) + rel
Branch if bit set :
if ( bit ) = 1 , then pc ← ( pc ) + rel
Branch if carry bit clear
if ( C ) = 0 , then pc ← ( pc ) + rel
Branch if carry bit set
if ( C ) = 1 , then pc ← ( pc ) + rel
Branch if equal
if ( Z ) = 1 , then pc ← ( pc ) + rel
Branch if minus
if ( N ) = 1 , then pc ← ( pc ) + rel
Branch if not equal
if ( Z ) = 0 , then pc ← ( pc ) + rel
Branch if minus
if ( N ) = 0 , then pc ← ( pc ) + rel
Branch always
pc ← ( pc ) + rel
Branch if overflow bit clear
if (V) = 0 , then pc ← ( pc) + rel
Branch if overflow bit set
if (V) = 1 , then pc ← ( pc ) + rel
Subroutine call
M( sp)←( pc
if !abs, pc← abs ; if [dp], pc
), sp←sp - 1, M(sp)← (pcL), sp ←sp - 1,
H
← ( dp ), pcH← ( dp+1 ) .
L
Compare and branch if not equal :
if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel.
Decrement and branch if not equal :
if ( M ) ≠ 0 , then pc ← ( pc ) + rel.
Unconditional jump
pc ← jump address
U-page call
M(sp) ←( pc
sp ← sp - 1, pc
Table call : (sp) ←( pc
M(sp) ← ( pc
← (Table vector L), pcH ← (Table vector H)
pc
L
), sp ←sp - 1, M(sp) ← ( pcL ),
H
← ( upage ), pcH ← ”0FFH” .
L
), sp ← sp - 1,
H
),sp ← sp - 1,
L
FLAG
NVGBHIZC
--------
--------
--------
--------
--------
--------
--------
--------
--------
--------
--------
--------
--------
--------
--------
--------
--------
vi SEP. 2004 Ver 1.03
6. CONTROL OPERATION & etc.
NO. MNEMONIC
1
BRK
2
DI
3
EI
4
NOP
5
POP A
6
POP X
7
POP Y
8
POP PSW
9
PUSH A
10
PUSH X
11
PUSH Y
12
PUSH PSW
13
RET
14
RETI
15
STOP
OP
CODE
BYTENOCYCLE
0F 1 8
60 1 3
E0 1 3
FF 1 2
0D 1 4
2D 1 4
4D 1 4
6D 1 4
0E 1 4
2E 1 4
4E 1 4
6E 1 4
6F 1 5
7F 1 6
EF 1 3
NO
OPERATION
Software interrupt : B ← ”1”, M(sp) ← (pc
M(s) ← (pc
pc
L
), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1,
L
← ( 0FFDEH ) , pcH ← ( 0FFDFH) .
Disable interrupts : I ← “0”
Enable interrupts : I ← “1”
No operation
sp ← sp + 1, A ← M( sp )
sp ← sp + 1, X ← M( sp )
sp ← sp + 1, Y ← M( sp )
sp ← sp + 1, PSW ← M( sp )
M( sp ) ← A , sp ← sp - 1
M( sp ) ← X , sp ← sp - 1
M( sp ) ← Y , sp ← sp - 1
M( sp ) ← PSW , sp ← sp - 1
Return from subroutine
sp ← sp +1, pc
← M( sp ), sp ← sp +1, pcH ← M( sp )
L
Return from interrupt
sp ← sp +1, PSW ← M( sp ), sp ← sp + 1,
pc
← M( sp ), sp ← sp + 1, pcH ← M( sp )
L
Stop mode ( halt CPU, stop oscillator )
HMS87C1X04B/08B/16B
FLAG
), sp ←sp-1,
H
NVGBHIZC
---1-0--
-----0--
-----1--
--------
--------
restored
--------
--------
restored
--------
SEP. 2004 Ver 1.03 vii
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