Macronix MX25L4005AM2C-12G, MX25L4005AM2I-12G, MX25L4005AMC-12G, MX25L4005AMI-12G, MX25L4005APC-12G Schematics

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MX25L4005A

4M-BIT [x 1] CMOS SERIAL FLASH

FEATURES

GENERAL

• Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3

• 4,194,304 x 1 bit structure

• 128 Equal Sectors with 4K byte each

- Any Sector can be erased individually

• 8 Equal Blocks with 64K byte each

- Any Block can be erased individually

• Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program operations

• Latch-up protected to 100mA from -1V to Vcc +1V

• Low Vcc write inhibit is from 1.5V to 2.5V

PERFORMANCE

• High Performance

- Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load)

- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)

- Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/block (64K-byte per block)

• Low Power Consumption

- Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and 4mA(max.) at 33MHz

- Low active programming current: 15mA (max.)

- Low active erase current: 15mA (max.)

- Low standby current: 10uA (max.)

- Deep power-down mode 1uA (typical)

• Minimum 100,000 erase/program cycles

• 10 years data retention

SOFTWARE FEATURES

• Input Data Format

- 1-byte Command code

• Block Lock protection

- The BP0~BP2 status bit defines the size of the area to be software protected against Program and Erase instructions

• Auto Erase and A uto Pro gram Algo rithm

- Automatically erases and verifies data at selected secto r

- Automatically programs and verifies data at selected page by an inter nal algorithm that automatically times the

progr am pulse widths (Any page to be pro gramed sho uld hav e page in the erased state first)

• Status Register Feature

• Electronic Identification

- JEDEC 2-byte Device ID

- RES command, 1-b yte De vice ID

HARDWARE FEATURES

• SCLK Input

- Serial clo ck input

• SI Input

- Serial Data Input

• SO Output

- Serial Data Output

• WP# pin

- Hardware write protectio n

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MX25L4005A

• HOLD# pin

- pause the chip without diselecting the chip

• PACKAGE

- 8-pin SOP (150mil)

- 8-pin SOP (200mil)

- 8-pin PDIP (300mil)

- 8-land SON (6x5mm, 1.0mm package height), which is no t recommended f o r new design

- 8-land WSON (6x5mm, 0.8mm package height)

- 8-land USON (4x4mm) in develo pment

- All Pb-free devices are RoHS Compliant

GENERAL DESCRIPTION

The MX25L4005A is a CMOS 4,194,304 bit serial Flash memory, which is configured as 524,288 x 8 internally. The MX25L4005A feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS# input.

The MX25L4005A provide sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified

page or byte /sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase command is executes on chip or sector(4K-bytes) or block(64K-bytes).

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.

When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC current. The MX25L4005A utilize MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000

program and erase cycles.

PIN CONFIGURATIONS

8-PIN SOP (150/200mil)

8-PIN PDIP (300mil)

PIN DESCRIPTION

SYMBOL DESCRIPTION

CS # Chip Select

VCC

HOLD#

SCLK

CS#

2 SO

WP#

GND

CS#

SO WP# GND

1 2 3 4

VCC

HOLD#

SCLK

SI Serial Data Input SO Serial Data Output SCLK Clock Input HOLD# Hold, to pause the device without

deselecting the device WP# Write Protection VC C + 3.3V Power Supply GND Ground

*8-LAND SON (6x5mm), WSON (6x5mm), USON (4x4mm)

CS#

SO WP# GND

1 2 3 4

VCC

HOLD#

SCLK

Note: 8-land SON is not recommended for new design

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BLOCK DIAGRAM

MX25L4005A

Address

Generator

Data

SRAM

Buffer

CS#

Mode Logic

SCLK Clock Generator

X-Decoder

State

Machine

Memory Array

Page Buffer

Y-Decoder

Generator

Sense

Amplifier

Output

Buffer

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MX25L4005A

DATA PROTECTION

The MX25L4005A are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.

• Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset and tPUW (internal timer) may protect the Flash.

• Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation:

- Power-up

- Write Disable (WRDI) command completion

- Write Status Register (WRSR) command completion

- Page Program (PP) command completion

- Sector Erase (SE) command completion

- Block Erase (BE) command completion

- Chip Erase (CE) command completion

• Software Protection Mode (SPM): by using BP0-BP2 bits to set the part of Flash protected from data change.

• Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP2 bits and SRWD bit from data change.

• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing

all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES).

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Table 1. Protected Area Sizes

Status bit Protect level 4Mb

BP2 BP1 BP0

0 0 0 0 (none) None 0 0 1 1 (1 block) Block 7 0 1 0 2 (2 blocks) Block 6-7 0 1 1 3 (4 blocks) Block 4-7 1 0 0 4 (8 blocks) All 1 0 1 5 (All) All 1 1 0 6 (All) All 1 1 1 7 (All) All

MX25L4005A

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HOLD FEATURE

HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress.

The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1.

Figure 1. Hold Condition Operation

CS#

SCLK

HOLD#

Hold

Condition

(standard)

Hold

Condition

(non-standard)

The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.

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Table 2. COMMAND DEFINITION

COMMAND WREN WRDI RDID RDSR WRSR READ Fast Read (byte) (write (write (read ident- (read status (write status (read data) (fast read

Enable) disable) ification) register) register) data )

1st 06 Hex 04 Hex 9F Hex 05 Hex 01 Hex 03 Hex 0B Hex 2nd AD1 AD1 3rd AD2 AD2 4th AD3 AD3 5th x Action sets the reset the output the to read out to write new n bytes

(WEL) (WEL) manufacturer the status values to the read out write write ID and 2-byte register status register until enable enable device ID CS# goes latch bit latch bit high

COMMAND SE B E CE PP DP RDP RES REMS (Read (byte) (Sector (Block (Chip (Page (Deep (Release (Read Electronic

Erase) Erase) Erase) Program) Power from Deep Electronic Manufacturer

Down) Power-down) ID) & Device ID)

1st 20 Hex 52 or 60 or 02 Hex B9 Hex AB Hex AB Hex 90 Hex

D8 Hex C7 Hex 2nd AD1 AD1 AD1 x x 3rd AD2 AD2 AD2 x x 4th AD3 AD3 AD3 x ADD(1) 5th Action Output the

manufacturer ID and device ID

(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. (2) It is not recommended to adopt any other code which is not in the above command definition table.

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Table 3. Memory Organization

MX25L4005A

Block Sector

127 07F000h 07FFFFh

112 070000h 070FFFh 111 06F000h 06FFFFh

96 060000h 060FFFh 95 05F000h 05FFFFh

80 050000h 050FFFh 79 04F000h 04FFFFh

64 040000h 040FFFh 63 03F000h 03FFFFh

48 030000h 030FFFh 47 02F000h 02FFFFh

32 020000h 020FFFh 31 01F000h 01FFFFh

16 010000h 010FFFh 15 00F000h 00FFFFh

Address Range

……..

…….

……..

3 003000h 003FFFh 2 002000h 002FFFh

001000h 001FFFh 000000h 000FFFh

…….

……..

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DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.

2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.

3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge.

4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of SPI mode 0 and mode 3 is shown as Figure 2.

5. For the following instructions: RDID, RDSR, READ, FAST_READ, RES and REMS the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.

6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase.

Figure 2. SPI Modes Supported

CPHA shift in shift out

CPOL

SCLK

0(SPI mode 0)

(SPI mode 3)

SCLK

MSB

Note: CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is supported.

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COMMAND DESCRIPTION (1) Write Enable (WREN)

The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit.

The sequence of issuing WREN instruction is: CS# goes low-> sending WREN instruction code-> CS# goes high. (see Figure 11)

(2) Write Disable (WRDI)

The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low-> sending WRDI instruction code-> CS# goes high. (see Figure

12)

The WEL bit is reset by following situations:

- Power-up

- Write Disable (WRDI) instruction completion

- Write Status Register (WRSR) instruction completion

- Page Program (PP) instruction completion

- Sector Erase (SE) instruction completion

- Block Erase (BE) instruction completion

- Chip Erase (CE) instruction completion

(3) Read Identification (RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte ID is as followings: 13(hex) for MX25L4005A.

The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data out on SO

-> to end RDID operation can use CS# to high at any time during data out. (see Figure. 13)

While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.

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(4) Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress.

The sequence of issuing RDSR instruction is: CS# goes low-> sending RDSR instruction code-> Status Register data out on SO (see Figure. 14)

The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status

register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.

WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction.

BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed)

SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SRWD BP2 BP1 BP0 WEL WIP Status 0 0 the level of the level of the level of (write enable (write in progress

Protect block block block

1= status (note 1) (note 1) (note 1) 1=write enable 1=write operation

disable enable operation

Note: 1. See the table "Protected Area Sizes".

2. The endurance cycles of protect bits are 100,000 cycles; however, the tW time out spec of protect bits is relaxed as tW = N x 15ms (N is a multiple of 10,000 cycles, ex. N = 2 for 20,000 cycles) after 10,000 cycles on those bits.

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(5) Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP2, BP1, BP0) bits to define the protected area of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.

The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register data on SI-> CS# goes high. (see Figure 15)

The WRSR instruction has no effect on b6, b5, b1, b0 of the status register. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-

timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

Table 4. Protection Modes

Mode Status register condition

Software protection mode(SPM)

Hardware protection mode (HPM)

Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP2 bits can be changed

The SRWD, BP0-BP2 of status register bits cannot be changed

Note:

1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.

As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM):

- When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0, is at software protected mode (SPM).

- When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP2, BP1, BP0. The protected area, which is defined by BP2, BP1, BP0, is at software protected mode (SPM).

WP# and SRWD bit status Memory

WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1

WP#=0, SRWD bit=1

The protected area cannot be program or erase.

Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed.

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Hardware Protected Mode (HPM):

- When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP2, BP1, BP0 and hardware protected mode by the WP# to against data modification.

Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP2, BP1, BP0.

(6) Read Data Bytes (READ)

The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached.

The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address on SI

-> data out on SO-> to end READ operation can use CS# to high at any time during data out. (see Figure. 16)

(7) Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached.

The sequence of issuing FAST_READ instruction is: CS# goes low-> sending FAST_READ instruction code-> 3-byte address on SI-> 1-dummy byte address on SI->data out on SO-> to end FAST_READ operation can use CS# to high at any time during data out. (see Figure. 17)

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.

(8) Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS#

goes high. (see Figure 19) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.

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(9) Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing BE instruction is: CS# goes low -> sending BE instruction code-> 3-byte address on SI -> CS# goes high. (see Figure 20)

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.

(10) Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table

3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing CE instruction is: CS# goes low-> sending CE instruction code-> CS# goes high. (see Figure

20) The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress

(WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP2, BP1, BP0 all set to "0".

(11) Page Program (PP)

The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page.

The sequence of issuing PP instruction is: CS# goes low-> sending PP instruction code-> 3-byte address on SI-> at least 1-byte on data on SI-> CS# goes high. (see Figure 18)

The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.

The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.

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