Datasheet TTSI1K16T3TL Datasheet (Lucent Technologies)

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Preliminary Data Sheet February 1999

1024-Channel, 16-Highway Time-Slot Interchanger

TTSI1K16T

Features

■

Sixteen full-duplex, serial time-division multiplexed (TDM) highways.

■

Full availability, nonblocking 1024-channel time/ space switch.

■

2.048 Mbits/s (32 time slots), 4.096 Mbits/s (64 time slots), or 8.192 Mbits/s (128 time slots) data rates, independently progr am mab le per high way.

■

64 kbits/s granularity with optional 32 kbits/s (4-bit) and 16 kbits/s (2-bit) subrate switching, selectable per highway.

■

Low-latency mode for voice channels.

■

Frame integrity for wideband data applications.

■

Concentration highway interface (CHI) compatible with the IOM2, GCI, K2, SLD, SC-Bus, and H.100.

■

Single highway clock and frame synchronization input.

■

Independently programmable bit and byte offsets with 1/4 bit resolution for all highways.

■

Capable of broadcasting data to the transmit highways from a variety of sources including host data.

■

High-impedance control per time slot.

■

Software-compatible family of 1K, 2K, and 4K timeslot interchangers.

■

Sixteen independent high-impedance indicators (output enables) for transmit highways, allowing external drivers.

■

Direct access to device registers, connection store, and data store via microprocessor interface.

■

†

IEEE

1149.1 boundary scan (JTAG). Test-pattern generation and checking for on-line system testing (PRBS, QRSS, or user- defined byte).

■

User-accessible BIST for data and connection stores.

■

3.3 V power supply with 5 V tolerant I/O.

■

Low-power, high-density CMOS technology, and TTL compatible switching thresholds.

■

144-pin TQFP package.

■

–40 °C to +85 °C operating temperature range.

MVIP

is a registered trademark of Natural Microsystems Corpo-

ration.

†

IEEE

is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

MVIP

*, ST-Bus,

Applications

■

Small and medium digital switch matrices.

■

Computer telephony integration (CTI).

■

Access concentrators.

■

PABX.

■

Cellular infrastructure.

■

ISP modem banks.

■

T1/E1 multiplexers.

■

Digital cross connects.

■

Digital loop carriers.

■

Multiport DS1/E1 service cards.

■

LAN/WAN gateways.

■

TDM highway data rate adaptation.

Description

The TTSI1K16T Time-Slot Interchanger (TSI) switches data between 16 full- dupl ex, ser ial, tim edivision multiplexed highways. The TTSI1K16T can make any connection between 1024 input and output time slots.

Each of the 16 transmit and 16 receive highways can be independently programmed for data rate (2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s) and offset. The offset can range from 0 bits to 127 bytes and 7 3/4 bits on a 8.192 Mbits/s highway. The TTSI1K16T can perform rate adaptation between varying speed highways as well.

The TTSI1K16T is configured via a microprocessor interface with a demultiplexed address and data bus. In addition to accessing the registers and connection store, this interface can also be used to read received time slots and specify user data for transmission.

The TTSI1K16T ensures that interchanged time slots retain their frame integrity. Frame integrity is required for applications that switch wideband data (i.e., ISDN H-channels). For voice applications where low delay is important, a low-latency mode can be selected.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Table of Contents

Contents Page

Features .................................................................................................................................................................. 1

Applications ............................................................................................................................................................. 1

Description............................................................................................................................................................... 1

Functional Description............................................................................................................................................. 5

Pin Information ........................................................................................................................................................ 7

Typical TSI Application.......................................................................................................................................... 13

Interchange Fabric................................................................................................................................................. 14

Small and Large TSIs............................................................................................................................................ 15

Microprocessor Interface....................................................................................................................................... 16

Asynchronous Mode (MM = 0)........................................................................................................................... 16

Synchronous Mode (MM = 1) ............................................................................................................................ 17

Highway Data Rate Selection................................................................................................................................ 18

Mixed-Highway Data Rates................................................................................................................................... 19

TDM Highway Interface Timing............................................................................................................................. 20

Virtual and Physical Frames.............................................................................................................................. 20

TDM Highway Alignment at Zero Offset ............................................................................................................ 21

TDM Highway Offsets............................................................................................................................................ 21

Reset Sequence.................................................................................................................................................... 22

Low-Latency and Frame-Integrity Modes.............................................................................................................. 23

Low Latency....................................................................................................................................................... 23

Frame Integrity................................................................................................................................................... 24

Test-Pattern Generation........................................................................................................................................ 27

Test-Pattern Checking........................................................................................................................................... 27

Error Injection........................................................................................................................................................ 28

Error Checking....................................................................................................................................................... 28

JTAG Boundary-Scan Specification...................................................................................................................... 29

Principle of the Boundary Scan.......................................................................................................................... 29

Test Access Port Controller............................................................................................................................... 30

Instruction Register............................................................................................................................................ 32

Boundary-Scan Register.................................................................................................................................... 33

BYPASS Register ........... ...... ....... ...... ....... ...... .............................................................................. ...... ....... ...... .. 33

IDCODE Register............................................................................................................................................... 33

3-State Procedures............................................................................................................................................ 33

Register Architecture............................................................................................................................................. 34

Configuration Register Architecture....................................................................................................................... 36

Transmit Highway 3-State Options.................................................................................................................... 49

Data Store Memory ............................................................................................................................................... 50

Connection Store Memory..................................................................................................................................... 50

Absolute Maximum Ratings................................................................................................................................... 53

Operating Conditions................ ..................................................................................................................... ...... .. 53

Handling Precautions ............... ....... ...... ....... ...... ....... ...... ....... ............................................................................... 53

Electrical Characteristics ....................................................................................................................................... 54

Timing Characteristics........................................................................................................................................... 54

Outline Diagram..................................................................................................................................................... 61

144-Pin TQFP.................................................................................................................................................... 61

Ordering Information.............................................................................................................................................. 62

DS99-177PDH Replaces DS98-290TIC to Incorporate the Following Updates.................................................... 62

2 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

List of Figures

Figures Page

Figure 1. Block Diagram of the TTSI1K16T .............................................................................................................6

Figure 2. 144-Pin TQFP Pin Assignment (Top View)...............................................................................................7

Figure 3. A Typical TSI Application........................................................................................................................13

Figure 4. An 8K Time-Slot Switch Made from 4K TSIs ..........................................................................................15

Figure 5. Asynchronous Read................................................................................................................................16

Figure 6. Asynchronous Write................................................................................................................................16

Figure 7. Synchronous Read .................................................................................................................................17

Figure 8. Synchronous Write..................................................................................................................................17

Figure 9. Mixed-Highway Data Rates ....................................................................................................................19

Figure 10. Virtual and Physical Frames .................................................................................................................20

Figure 11. Synchronization to FSYNC ...................................................................................................................21

Figure 12. Highway Offsets....................................................................................................................................22

Figure 13. Mixed Low-Latency and Frame-Integrity Modes...................................................................................26

Figure 14. Block Diagram of the TTSI1K16T's Boundary-Scan Test Logic ...........................................................29

Figure 15. BS TAP Controller State Diagram.........................................................................................................30

Figure 16. Asynchronous Read Cycle Timing Using DT Figure 17. Asynchronous Write Cycle Timing Using DT Figure 18. Asynchronous Read Cycle Timing Using Only CS Figure 19. Asynchronous Write Cycle Timing Using Only CS

Figure 20. Synchronous Read Cycle Timing..........................................................................................................57

Figure 21. Synchronous Write Cycle Timing..........................................................................................................57

Figure 22. TDM Highway Timing............................................................................................................................59

Figure 23. JTAG Interface Timing..........................................................................................................................60

Handshake.....................................................................55

...............................................................................56

3Lucent Technologies Inc.

TTSI2K32T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

List of Tables

Tables Page

Table 1. Data Rate and Switch Size Examples....................................................................................................... 5

Table 2. Pin Assignments for a 144-Pin TQFP—Pin Number Order....................................................................... 8

Table 3. Pin Assignments for a 144-Pin TQFP—Signal Name Order ..................................................................... 9

Table 4. TTSI1K16T Pin Descriptions................................................................................................................... 10

Table 5. The TSI Family ........................................................................................................................................ 15

Table 6. Rx Highway Data Rate Options............................................................................................................... 18

Table 7. Tx Highway Data Rate Options ............................................................................................................... 18

Table 8. Time-Slot Separation Required for Transmission with Minimum Latency (0 Offsets)............................. 23

Table 9. Offset Difference and Its Effect on Frame for Transmission.................................................................... 25

Table 10. Offset Difference Boundaries ................................................................................................................ 25

Table 11. TAP Controller States in the Data Register Branch............................................................................... 31

Table 12. TAP Controller States in the Instruction Register Branch...................................................................... 31

Table 13. TTSI1K16T’s Boundary-Scan Instructions ............................................................................................ 32

Table 14. TTSI1K16T Register Summary ............................................................................................................. 34

Table 15. General Command Register (0x00) ...................................................................................................... 36

Table 16. Software Reset Register (0x01) ............................................................................................................ 37

Table 17. BIST Command Register (0x02) ........................................................................................................... 37

Table 18. Idle Code 1 Register (0x03)................................................................................................................... 38

Table 19. Idle Code 2 Register (0x04)................................................................................................................... 38

Table 20. Idle Code 3 Register (0x05)................................................................................................................... 38

Table 21. Global Interrupt Mask Register (0x06)................................................................................................... 38

Table 22. Interrupt Status Register (0x07) ............................................................................................................ 39

Table 23. Interrupt Mask Register (0x08).............................................................................................................. 40

Table 24. Test Command Register (0x09) ............................................................................................................ 41

Table 25. Test-Pattern Style Register (0x0A)........................................................................................................ 42

Table 26. Test-Pattern Checker Highway Register (0x0B).................................................................................... 43

Table 27. Test-Pattern Checker Upper Time-Slot Register (0x0C)....................................................................... 43

Table 28. Test-Pattern Checker Lower Time-Slot Register (0x0D)....................................................................... 43

Table 29. Test-Pattern Checker Data Register (0x0E).......................................................................................... 43

Table 30. Test-Pattern Error Injection Register (0x0F).......................................................................................... 43

Table 31. Test-Pattern Error Counter (Byte 0) (0x10) ........................................................................................... 44

Table 32. Test-Pattern Error Counter (Byte 1) (0x11) ........................................................................................... 44

Table 33. Test-Pattern Generator Data Register (0x12) ....................................................................................... 44

Table 34. Version Register (0x13)......................................................................................................................... 44

Table 35. Transmit Highway Configuration Register (Byte 0) (0x1000 + 4i) ......................................................... 45

Table 36. Transmit Highway Configuration Register (Byte 1) (0x1001 + 4i) ......................................................... 46

Table 37. Transmit Highway Configuration Register (Byte 2) (0x1002 + 4i) ......................................................... 46

Table 38. Receive Highway Configuration Register (Byte 0) (0x1800 + 4i) .......................................................... 47

Table 39. Receive Highway Configuration Register (Byte 1) (0x1801 + 4i) .......................................................... 48

Table 40. Receive Highway Configuration Register (Byte 2) (0x1802 + 4i) .......................................................... 48

Table 41. Transmit Highway 3-State Options........................................................................................................ 49

Table 42. Address Scheme for Data Store Memory ............................................................................................. 50

Table 43. Address Scheme for Connection Store Memory .................................................................................. 50

Table 44. Connection Store Memory (Byte 0) ....................................................................................................... 51

Table 45. Connection Store Memory (Byte 1) ....................................................................................................... 51

Table 46. Clock Specifications .............................................................................................................................. 54

Table 47. Asynchronous Read and Write Interface Timing Using DT Table 48. Asynchronous Microprocessor Interface Timing Using Only CS

Table 49. Synchronous Microprocessor Interface Timing ..................................................................................... 58

Table 50. TDM Highway Timing ............................................................................................................................ 59

Table 51. JTAG Interface Timing........................................................................................................................... 60

Handshake................................................ 55

..................................... ..................... 56

4 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Functional Description

The TTSI1K16T is a 1024 time-slot switch that can be used in a variety of ways, with some or all of the highways active and running at different data rates. The table below lists a few of the possible combinations of switch size and data rates. By selecting different rates for receive and transmit highways, rate adaptation can be performed also. Each one of the 32 (16 transmit and 16 receive) highways can be independently programmed for data rate (2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s) as well as a full range of bit (0—7.75) and byte (0—127) offsets.

Table 1. Data Rate and Switch Size Examples

Number of

Receive

Highways

Used

Receive

Highway Data

Rates (Mbits/s)

Receive

Time Slots

per Frame

Total

Switch

Size

Number of

Transmit

Highways

Used

Transmit

Highway Data

Rates (Mbits/s)

Transmit

Time Slots

per Frame

16 4.096 64 1024 16 4.096 64

8 8.192 128 1024 8 8.192 128 8 8.192 128 1024 16 4.096 64 8

and 4

4.096

8.192

128

1024

and 5

4.096

8.192

128

This device uses a single clock (CK) and frame synchronization (FSYNC) signal for all highways. The CK rate can be 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz, and this speed is indicated to the device via the CKSPD [0—2] strap pins. A pulse is expected on the FSYNC pin once every 125 µs.

Each one of the 1024 time slots can be independently programmed in any one of the data modes listed below:

■

Low latency

■

Frame integrity

■

Host data substitution

■

Idle code substitution

■

Test-pattern substitution (PRBS, QRSS, or a fixed byte)

■

High impedance

The low-latency mode causes a receive highway time slot to be transmitted as soon as possible, which is dependent on the relative offset of the input and output time slots. This mode is useful for voice channels where it is important to keep the transmission delay to a minimum.

The frame integrity mode will guarantee that all selected time slots received in a common frame will be transmitted together in a common frame. This mode is useful for wideband data (e.g., ISDN H-channels) where multiple time slots received in a single frame cannot be split across two transmit frames.

The TTSI1K16T is a nonblocking DS0 (64 kbits/s channel) switch where a time slot is 8 bits. Since each Rx and Tx highway data rate can be individually selected, the TTSI1K16T can also be used to switch time slots that are smaller than 8 bits.

■

32 kbits/s channels (4-bit time slots) such as in compressed voice (ADPCM) applications. The TTSI1K16T will be configured to sample the data at twice the data rate for highways carrying traffic at 2.048 Mbits/s or

4.096 Mbits/s.

■

16 kbits/s channels (2-bit time slots) such as in cellular (GSM) applications. The TTSI1K16T will be set to sample the data at four times the data rate on a 2.048 Mbits/s highway carrying such traffic.

■

8 kbits/s channels (1-bit time slots) such as in half-rate GSM applications. This can be done by looping the data through the TSI multiple times, thus oversampling the same data multiple times. However, in this configuration, the total switching capacity of the device will drop and the latency will go up.

The TTSI1K16T is one in a family of 1K, 2K, and 4K TSIs. The high-impedance control per time-slot feature allows four of the 4K devices to be connected to make an 8K time-slot switch.

If external drivers are needed on the transmit highway pins, support for 16 output enables, corresponding to the 16 transmit highways, is provided.

5Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Functional Description

(continued)

The device capabilities include several test features for board and device diagnostics.

■

Test-pattern checking on input time slots (PRBS, QRSS, or a fixed byte).

■

Test-pattern generation on output time slots (PRBS, QRSS, or a fixed byte).

■

JT AG on all I/O.

■

Software-controlled BIST of data store and connection store memory.

■

TEST pin for isolating the TTSI1K16T during board test. The microprocessor interface supports two modes of operation, synchronous and asynchronous. These modes are

selected based on the MM input pin. Both modes provide an 8-bit demultiplexed address and data bus. Fifteen address pins allow direct access to the 32 Kbyte address space. This interface provides direct access to the control registers and data store and connection store memories.

The TTSI1K16T is fabricated using a low-power, high-density, CMOS process that nominally operates at 3.3 V with TTL switching thresholds and 5 V tolerance on the inputs and outputs. A basic block diagram of the architecture is shown in Figure 1.

RXD0 RXD1 RXD2 RXD3

RECEIVE

HIGHWAYS

TDM

DATA

STORE

TDM

DATA

TRANSMIT

HIGHWAYS

TXD0 TXOE0 TXD1 TXOE1

RXD14 RXD15

FSYNC

CK CKSPD0 CKSPD1 CKSPD2

PLL

AND

LOGIC

DATA STORE ADDRESS

CONNECTION

STORE

HOST ADDRESS/DATA BUS

MICROPROCESSOR INTERFACE

A[14—0] D[7—0] CS AS DS R/W DT

PCLK

JTAG

TXD15

TXOE15

TCK TDI TMS TRST TDO

RESET TEST

INT

5-5780(F).c

Figure 1. Block Diagram of the TTSI1K16T

6 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Pin Information

The TTSI1K16T is available in a 144-pin TQFP with 0.5 mm (19.7 mil) pin pitch.

TXD2

TXOE2

VDD

TXD1

VSS

TXOE1

TXOE15

VDD

TXD15

141

140

139

138

137

136

VSS

VDD

VSSPLLNCVDDPLLCKVDD

135

134

133

132

131

130

129

VSS

CKSPD0

CKSPD1

VDD

CKSPD2NCTXOE3

TXD3

TXOE4

VSS

TXD4

VDDNCNC

VSS

VDD

VSS

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

VSS

107

RESET

106

VDD

105

TEST

104

TDI

103

TDO

102

TCK

101

TMS

100

TRST

VSS

FSYNC

TXOE5

TXD5

TXOE8

VDD

TXD8

TXOE9

TXD9

VSS

TXOE10

VDD

TXD10

TXOE6

TXD6

VSS

TXOE7

TXD7

VSS

INT

VDD

TXOE11

VDD

R/W

VSS

RXD14

RXD7

VDD

RXD13

RXD6

VDD VSS

RXD12

RXD5 RXD4

VDD

VSS RXD3 RXD2

VDD

VDD RXD1 RXD0

RXD11 RXD10

RXD9 RXD8

VDD

VSS

A10 A11

VSS

A12 A13 A14

VDD

TXOE0

TXD0

VSS

144

143 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21 22 23 24 25 26 27

29 30 31 32 33 34 35 36

142

3839404142434445464748495051525354555657585960616263646566676869707172

VDD

RXD15

A4A5A6

VSS

VDD

VSS

TXD14

TXOE14

PCLK

VDD

D4D5D6

VSS

VDD

VSS

TXD13

VDD

TXD12

TXOE13

TXD11

TXOE12

5-4712(F).dr.2

Figure 2. 144-Pin TQFP Pin Assignment (Top View)

7Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Pin Information

(continued)

Table 2. Pin Assignments for a 144-Pin TQFP—Pin Number Order

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

2 RXD14 40 A1 78 V 3RXD7 41V 4V

39 A0 77 TXOE11 115 TXD4

79 INT 117 TXOE4

42 A2 80 V

116 V

118 TXD3

5 RXD13 43 A3 81 TXD7 119 TXOE3 6 RXD6 44A4 82TXOE7 120NC 7V 8V

DD SS

9RXD12 47V

10 RXD5 48 V

45 A5 83 V 46 A6 84 V

DD SS

85 TXD6 123 CKSPD1

86 TXOE6 124 CKSPD0 11 RXD4 49 TXD14 87 TXD10 125 V 12 V 13 V

DD SS

50 TXOE14 88 V

51 DS 89 TXOE10 127 CK 14 RXD3 52 PCLK 90 V 15 RXD2 53 DT 16 V 17 V

DD DD

54 D0 92 TXOE9 130 VSSPLL

55 D1 93 TXD8 131 V 18 RXD1 56 V

91 TXD9 129 NC

94 V

SS SS

121 CKSPD2 122 V

126 V

SS DD

128 VDDPLL

132 V

19 RXD0 57 D2 95 TXOE8 133 TXD2 20 A7 58 V 21RXD11 59D3 97TXOE5 135V 22 RXD10 60 V 23 RXD9 61 D4 99 V

96 TXD5 134 TXOE2

98 FSYNC 136 TXD1

137 V

24 RXD8 62 D5 100 TRST 138 TXOE1 25 V 26 V

DD SS

27 A8 65 V 28 A9 66 D7 104 TDI 142 V

63 D6 101 TMS 139 TXD15

64 V

SS SS

102 TCK 140 V 103 TDO 141 TXOE15

29 A10 67 TXD13 105 TEST 143 TXD0 30 A11 68 TXOE13 106 V 31 V

69 TXD12 107 RESET 32 A12 70 TXOE12 108 V 33 A13 71 V

109 V 34 A14 72 TXD11 110 V 35 V

73 R/W 111 V

SS SS DD SS

144 TXOE0

36 MM 74 AS 112 NC 37 RXD15 75 V 38 V

76 CS 114 V

113 NC

8 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Pin Information

(continued)

Table 3. Pin Assignments for a 144-Pin TQFP—Signal Name Order

Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Pin

A0 39 PCLK 52 TXD13 67 V A1 40 R/W A2 42 RESET

73 TXD14 49 V

107 TXD15 139 V A3 43 RXD0 19 TXOE0 144 V A4 44 RXD1 18 TXOE1 138 V A5 45 RXD2 15 TXOE2 134 V A6 46 RXD3 14 TXOE3 119 V A7 20 RXD4 11 TXOE4 117 V A8 27 RXD5 10 TXOE5 97 V A9 28 RXD6 6 TXOE6 86 V A10 29 RXD7 3 TXOE7 82 V A11 30 RXD8 24 TXOE8 95 V A12 32 RXD9 23 TXOE9 92 V A13 33 RXD10 22 TXOE10 89 V A14 34 RXD11 21 TXOE11 77 V AS

74 RXD12 9 TXOE12 70 V CK 127 RXD13 5 TXOE13 68 V CKSPD0 124 RXD14 2 TXOE14 50 V CKSPD1 123 RXD15 37 TXOE15 141 V CKSPD2 121 TCK 102 V CS

76 TDI 104 V D0 54 TDO 103 V D1 55 TEST

105 V D2 57 TMS 101 V D3 59 TRST

100 V D4 61 TXD0 143 V D5 62 TXD1 136 V D6 63 TXD2 133 V D7 66 TXD3 118 V DS DT

51 TXD4 115 V

53 TXD5 96 V FSYNC 98 TXD6 85 V INT 79 TXD7 81 V MM 36 TXD8 93 V NC 112 TXD9 91 V NC 113 TXD10 87 V NC 120 TXD11 72 V NC 129 TXD12 69 V

DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD

7V 16 V 25 V 35 V 38 V 47 V 56 V 60 V 71 V 75 VSSPLL 130 78 88 94

106 110 114 122 126

DD DD DD DD DD DD

PLL 128

SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS

131 135 140

12 17

8 13 26 31 41 48 58 64 65 80 83 90 99

108

111 116 125 132 137 142

109

9Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Pin Information

Table 4. TTSI1K16T Pin Descriptions

Symbol Type

RESET

TEST

MM I

—

PCLK I

*Iu indicates internal 100 kΩ pull-up resistor, and Id indicates 17.5 kΩ pull-down resistor.

(continued)

Reset (Active-Low).

any other clock or input signal. All flip-flops will be cleared when RESET counters, state machines, and configuration registers will be set to the default state following a reset.

T est (Active-Low).

TTSI1K16T device to be in a high-impedance state. This pin has an internal pull-up resistor.

Microprocessor Mode.

handshake (equal to mode 1 of the Lucent dual T1/E1 terminator devices). When MM = 1, the TTSI1K16T uses a synchronous type handshake which requires a host processor clock (PCLK) input. Both modes use a demultiplexed address and data bus.

Host Processor Clock.

0 MHz to 65 MHz.

Address Valid (Active-Low).

one PCLK cycle. Indicates the start of a processor access.

Chip Select (Active-Low).

asserted low to enable any transfers through the microprocessor interface. CS and cycle type signals defining the memory map location of the TTSI1K16T.

Not Used.

Data Transfer Acknowledge (ActiveLow).

cates that data has been written during processor writes. Indicates that read data is valid during processor reads.

An external pull-up is required on this output.

Description

A low on this pin resets the TTSI1K16T. It is asynchronous to

When low, TEST

When MM = 0, the TTSI1K16T uses an asynchronous type

Synchronous Mode

should be a decode of all address

Must be tied high.

Active for one PCLK cycle. Indi-

(MM = 1)

Valid from

Valid for

This pin is

causes the output and bidirectional pins of the

is low. All

Asynchronous Mode

Unused.

Address Valid (Active-Low).

a valid address for a processor access. Must be held low for the duration of the access.

Chip Select (Active-Low).

asserted low to enable any transfers through the microprocessor interface. CS and cycle type signals defining the memory map location of the TTSI1K16T. In this mode, CS tristating of DT The input timing requirement of CS tive to AS Characteristics section on page 54.

Data Valid (Active-Low).

data during processor writes. The TTSI1K16T will start driving D[7—0] when this signal is asserted during processor reads.

Data Transfer Acknowledge (ActiveLow).

ten during processor writes. Indicates that read data is valid during processor reads. Once driven active, this signal is held active until AS removed.

An external pull-up is required on this output.

Must be either tied high or low.

should be a decode of all address

is used to control the

at the end of the cycle.

is described in the Timing

Indicates that data has been writ-

, DS, or CS is

(MM = 0)

Indicates

This pin is

rela-

Indicates valid

10 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Pin Information

Table 4. TTSI1K16T Pin Descriptions

Symbol Type

D[7—0] I/O

A[14—0] I

R/W

INT O

RXD[0—15]

FSYNC I

CK I

CKSPD[2—0] I

(continued)

Host Processor Data Bus.

provide an 8-bit, bidirectional data bus. Read data is valid for one PCLK cycle coincident with the assertion of DT data must be held throughout the access.

Host Processor Address Bus.

processor access. A0 is the least significant address signal and is used to select byte locations.

Read/Write

a logic 1; a write cycle is indicated with a logic 0.

Interrupt.

occurred. This output will remain active until the interrupt status register has been cleared (read). The polarity of this output is controlled through the INTP bit (bit 3) of the general command register. The default value of this register is 0, which indicates active-high. This output is tristated until INTOE (bit 4) of the general command register is set to 1. The polarity of this output should be selected before the pin is enabled.

Receive Data Highways 0—15.

2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s.

Frame Synchronization.

125 µs (8 kHz). FSYNC can be active-low or active-high, but its polarity is the same for all highways. FSYNC can be sampled on a positive or negative CK edge. Timeslot numbers and bit offsets are assigned relative to the detection of FSYNC. There are no restrictions on the duty cycle of FSYNC as long as the setup and hold timing requirements relative to CK are met.

Clock.

frequency can be 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz. The frequency selection for CK must be set equal to or greater than the fastest highway data rate.

Clock Speed Select for CK Pin.

This input is the clock reference for all the transmit and receive highways. Its

(continued)

Description

These pins

. Write

A14—A0 must remain valid throughout the entire

This signal indicates a read or write cycle. Read cycle is indicated with

This pin will be asserted to indicate that an interrupt condition has

Serial TDM highways receiving data at rates of

This signal indicates the beginning of a frame every

These strap pins indicate the frequency of CK:

Host Processor Data Bus.

provide an 8-bit, bidirectional data bus. Write data must be valid for the duration of DS

. Read data is valid while DT is

asserted.

These pins

CKSPD2

0002.048

0014.096

0108.192

01116.384 1 X X Reserved

TXD[0—15] O

*Iu indicates internal 100 kΩ pull-up resistor, and Id indicates 17.5 kΩ pull-down resistor.

T ransmit Data Highways 0—15.

2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. During external driver mode, the TXD[0—15] outputs will be continuously driven. The only exception to this is when the TEST tristated on a per-time-slot basis.

See Table 41, Transmit Highway 3-State Options, on page 49 for a detailed description of all methods for 3-stating the transmit highways.

CKSPD1 CKSP D0 CK (MHz)

Serial TDM highway transmitting data at rates of

input is asserted. When not in external driver mode, this highway can be

11Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Pin Information

Table 4. TTSI1K16T Pin Descriptions

Symbol Type

TXOE[0—15] O

(continued)

Transmit Output Enables 0—15.

(continued)

Description

These output pins reflect the active/high-impedance status for the corresponding transmit highways. They are continuously driven to reflect the status of the output enables of the transmit highways, regardless of whether or not external driver mode is enabled via the ED (bit 6) in the general command register. The external driver for transmit highway [i] should be enabled when TXOE[i] is a 1.

Also see Table 41, Transmit Highway 3-State Options, on page 49 for other methods of 3-stating the transmit highways.

TDI

TCK I TMS

TRST

JTAG Test Data Input.

JTAG Test Clock.

JTAG Test Mode Select.

JTAG Test Reset (Active-Low).

Maximum 10 MHz.

To disable the JTAG interface, tie TRST

leave unconnected.

TDO O

PLL P

Test Data Output.

3.3 V Supply.

Ground.

3.3 V PLL Supply.

All VDD leads must be connected to the 3.3 V supply.

VSSPLL and VDDPLL should be decoupled with a high-speed

capacitor with a value in the range of 2 µF—5 µF.

PLL P

PLL Ground.

VSSPLL and VDDPLL should be decoupled with a high-speed capaci-

tor with a value in the range of 2 µF—5 µF.

NC —

*Iu indicates internal 100 kΩ pull-up resistor, and Id indicates internal 17.5 kΩ pull-down resistor.

No Connect.

This pin must be left unconnected.

low or

12 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Typical TSI Application

DS0 SERVICE

COMPLEX

HDLC

SYSTEM

BACKPLANE

(8.192 Mbits/s)

T1/E1 LIU AND FRAMER ICs

T7630/T7633

FORMATTERS

ECHO

CANCELLERS

V.90 MODEMS

(DSPs)

T1/E1

FRAMERS

T7230A

TFRA08C13

TSI

HIGHWAYS

MICROPROCESSOR BUS

HIGHWAYS

5-7074(F)r.2

T1/E1

LINES

T1/E1

LIUs

T7698 T7693

MICROPROCESSOR

Figure 3. A Typical TSI Application

A typical application that requires a TSI is where TDM highways that are carrying different types of data in 8-bit time slots (64 kbits/s channels) need to be switched and sent to different destinations. For example, TDM highways may contain time slots that are carrying voice, Internet traffic, signaling information, etc.

The TSI could be programmed to select all the time slots, carrying Internet data from different Rx highways to be put on a another Tx highway that is connected to a bank of V.90 modems. Return data from these modems would be sent via another set of Rx highways back to the TSI, which could send the data back out over a Tx highway and to a T1 line via a T1 framer and LIU.

Similarly, time slots containing signaling information which is HDLC formatted can be sent to a bank of HDLC formatters. Voice channels that have echo on them could be selectively sent to echo cancellers. Data that needs to be sent to another card in the system could be put on the system backplane via optional bus drivers.

13Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Interchange Fabric

The time-slot interchanger core has a memory-based architecture. The received time slots are converted from serial to parallel by the receive highways block and stored in an internal dual-ported memory called the data store, see Figure 1, Block Diagram of the TTSI1K16T on page 6. These time slots are then read out of the data store in the order specified by the connection store, converted from parallel to serial by the transmit highways section, and sent out on the transmit highways.

All the time slots (bytes) coming into the device are stored in the data store. Each TDM highway can bring in up to 32 valid time slots at 2.048 Mbits/s, 64 time slots at 4.096 Mbits/s, or 128 time slots on an 8.192 Mbits/s highway, during a 125 µs frame. With 8 Rx highways running at the maximum rate of 8.192 Mbits/s, the maximum capacity of the switch will be utilized. The addresses used to retreive the data from the data store are stored in the connection store. If host substituted data is to be transmitted instead of data that was received on a TDM highway, then it is stored in the connection store .

Note that this device can switch any 1024 time slots from the 2048 possible recieve time-slot positions, restricted only by the data rate selection criteria for the Rx highways (see Table 6, Rx Highway Data Rate Options, on page

18). Similarily on the Tx side, this device can place the 1024 switched time slots into any of the 2048 possible transmit time-slot positions, restricted only by the Tx data rate selection criteria (see Table 7, Tx Highway Data Rate Options, on page 18).

Any mode that is selected on a time-slot basis is typically made via the connection store. There are 4096 bytes in the connection store, two for each time slot that can be selected for transmission. Each one of the 2048 possible transmit time slots can be individually 3-stated. This is useful when multiple devices need to drive the same TDM highway as a bus or backplane. For extra drive, 16 individual output enables (TXOE pins) are also provided to individually control an external bus or backplane driver, one for each transmit highway. A low latency (send as soon as possible) or frame integrity (keep tagged time slots from the same highway together in the same frame) can also be selected on a time-slot basis. The user also has the option to send one of 13 predefined test patterns, a userdefined byte, or one of three user-defined idle codes, on any time slot of any Tx highway.

Time slots received on any TDM highway can be easily broadcasted on any transmit highway using the connection store. If, for example, the entire connection store is filled with all zeros, this then implies low-latency mode and that the source for all transmitted data is Rx highway 0, time slot 0. Thus, the data received on RXD0 time slot 0 will end up being broadcasted on all outgoing time slots.

14 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Small and Large TSIs

The TTSI1K16T is one in a family of time-slot interchanger (TSI) devices offered by Lucent Technologies Microelectronics Group. This family of devices are all software compatible since they all have similar register maps. The larger devices of course have extra registers to configure the extra highways and also have larger connection and data stores. However, software written for a smaller TSI will run without alterations with a larger device. The TTSI2K32T and TTSI4K32T are also pin compatible, since they are in the same package.

Table 5. The TSI Family

Device Time-Slot Capacity Number of Rx/Tx Highways Package

TTSI1K16T 1024 16/16 144-pin TQFP TTSI2K32T 2048 32/32 217-pin PBGA TTSI4K32T 4096 32/32 217-pin PBGA

The capacity of the TTS I1K16T can be fully utilized by receiving and/or transmitting data on all 16 highwa ys at

4.096 Mbits/s or eight highways at 8.192 Mbits/s. Similarly, the TTSI2K32T can be fully utilized by receiving and/or transmitting data on all 32 highways at 4.096 Mbits/s or 16 highways at 8.192 Mbits/s. Other combinations of different data rates on different highways can also be used to fully utilize the TTSI1K16T and TTSI2K32T. The capacity of the TTSI4K32T is fully utilized only when data is being received and/or transmitted on all 32 highways at

8.192 Mbits/s. The TTSI4K32T can be used to make even larger switches; for example, an 8192 time-slot switch with 64 Rx and

64 Tx highways. The Rx and Tx highways of the 8K switch are labeled LRXD[0—63] and LTXD[0—63], respectively, in the figure below.

TTSI4K32T

LRXD[0—31]

LRXD[32—63] LTXD[32—63]

TTSI4K32T

LTXD[0—31]

TTSI4K32T

5-7076(F)r.1

Figure 4. An 8K Time-Slot Switch Made from 4K TSIs

LRXD[0—31] are sent to both TSI #1 and #2. Similarly, LRXD[32—63] are sent to both TSI #3 and #4. The TXD[0—31] of TSI #1 are wire-ORed with the TXD[0—31] of TSI #3, to make LTXD[0—31]. Similarly, the TXD[0—31] of TSI #2 are wire-ORed with the TXD[0—31] of TSI #4, to make LTXD[32—63].

Now, if time slots on highway LRXD0 need to be switched to LTXD63, it can be done via TSI #2. The connection stores of TSI #2 and #4 must be programmed such that they both never drive their TXD31 simultaneously. The 3-state per time-slot feature of the TSI allows this to be accomplished easily.

15Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Microprocessor Interface

The host interface is designed to connect directly to a typical synchronous or asynchronous host bus. The interface to the TTSI1K16T includes a separate clock, PCLK, which is used only in the synchronous interface mode. This device will be a slave on the host bus and will provide the host microprocessor with the capability to read and write the TTSI1K16T address space in a minimal number of clock cycles. There is no posting of writes in the host interface, and all registers and the data and connection stores are directly accessible.

Asynchronous Mode (MM = 0)

The following two timing diagrams show read and write in the asynchronous mode.

D[7—0]

A[14—0]

R/W

D[7—0]

A[14—0]

READ DATA

TSI READ ADDRESS

183 ns MAX

HIGH IMPEDANCE

5-6954(F).r3

Figure 5. Asynchronous Read

TSI WRITE DATA

TSI WRITE ADDRESS

R/W

183 ns MAX

HIGH IMPEDANCE

5-6955(F)r.3

Figure 6. Asynchronous Write

The presence of AS retrieved or written, DT to be asserted until AS

, CS, and DS being asserted will start the TTSI1K16T internal access. Once data has been

will be asserted indicating the TTSI1K16T is ready to terminate the access. DT will continue , CS, or DS is negated.

The duration of an asynchronous read or write cycle will be a maximum of 183 ns. This duration is measured from when AS

, CS, and DS are all asserted low until DT is asserted low by the TTSI1K16T.

16 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Microprocessor Interface

(continued)

Synchronous Mode (MM = 1)

The following two timing diagrams show read and write in the synchronous mode.

PCLK

D[7—0]

A[14—0]

R/W

HIGH IMPEDANCE

Figure 7. Synchronous Read

READ ADDRESS

READ DATA

5-6956(F)r.4

PCLK

D[7—0]

A[14—0]

R/W

HIGH IMPEDANCE

WRITE DATA

WRITE ADDRESS

5-6957(F)r.3

Figure 8. Synchronous Write

The synchronous write or read cycle is started when AS for the TTSI1K16T to respond, CS

must be active during the first or second cycle of an access depending on the

value of CSV (bit 7) of the general command register. Once data has been retrieved or written, DT

is sampled active with the rising edge of PCLK. In order

will be asserted

for one clock, terminating the access. The duration of a synchronous read or write cycle is a combination of two periods of time. One period is the dura-

tion of the internal cycle, which will be a maximum of 160 ns. The other time period is the initiation, termination, and synchronization of activity on the processor bus, which will be a maximum of six PCLK cycles. The total duration of the cycle, from the assertion of AS

to the removal of DT, will be the sum of these two periods of time.

Note:

The number of processor clock cycles can be reduced by one PCLK cycle if the CS delivered soon enough to be sampled with AS

and CSV (bit 7) of the general command register is set to a 1.

input signal can be

17Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Highway Data Rate Selection

The highway data rate for a particular transmit or receive highway is selected by setting HDR[1—0] (bits 1—0) in byte 2 of the highway configuration registers. All of the highways in the TTSI1K16T are grouped into pairs. RXD0 is paired with RXD1, RXD2 is paired with RXD3, . . . , and RXD14 is paired with RXD15. Similarly, TXD0 is paired with TXD1, TXD2 is paired with TXD3, . . . , and TXD14 is paired with TXD15.

The maximum combined bandwidth that each pair can handle is 8.192 Mbits/s. If the programmed bandwidth of a pair exceeds 8.192 Mbits/s, one or both highways will be set to idle automatically. The register contents will not be altered to reflect this, but that particular receive or transmit highway will not carry any traffic.

Table 6 shows the valid Rx highway data rate options for a particular Rx highway pair.

Table 6. Rx Highway Data Rate Options

RXD[2i] Data Rate (Mbits/s)

0.000 0.000

0.000 2.048

0.000 4.096

0.000 8.192

2.048 0.000

2.048 2.048

2.048 4.096

4.096 0.000

4.096 2.048

4.096 4.096

8.192 0.000

* i = 0, 1, 2, . . . , 7.

Table 7 shows the valid Tx highway data rate options for a particular Tx highway pair.

Table 7. Tx Highway Data Rate Options

TXD[2i] Data Rate (Mbits/s)

0.000 0.000

0.000 2.048

0.000 4.096

0.000 8.192

2.048 0.000

2.048 2.048

2.048 4.096

4.096 0.000

4.096 2.048

4.096 4.096

8.192 0.000

* i = 0, 1, 2, . . . , 7.

RXD[2i + 1] Data Rate (Mbits/s)

TXD[2i + 1] Data Rate (Mbits/s)

To meet the 8.192 Mbits/s bandwidth requirement for a transmit highway pair, a transmit highway may have to be disabled. This is done by setting its data rate to 0.000 Mbits/s and not by setting its XE bit to 0 in the transmit configuration register.

18 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Mixed-Highway Data Rates

Each receive (Rx) highway can be selected to sample at a rate of either 2.048 Mbits/s, 4.096 Mbits/s, or

8.192 Mbits/s. This rate selection is made via the HDR[1—0] field in the receive highways configuration register (byte 2). Similarly, each transmit (Tx) highway can be programmed to clock the data out at 2.048 Mbits/s,

4.096 Mbits/s, or 8.192 Mbits/s via the transmit highway configuration register (byte 2). Thus, 32 independent data rate selections can be made: 16 on the Rx side and 16 on the Tx side. Highways can also be selected to be idle, i.e., neither receiving nor transmitting data.

The data rate on a receive highway does not have to match that on its corresponding transmit highway either, e.g., RXD0 and TXD0 data rates can be different. Data received on a 2.048 Mbits/s highway can be transmitted on a

4.096 Mbits/s or 8.192 Mbits/s highway too. All of this flexibility allows this device to be used to solve a variety of design problems such as data rate adaptation, etc. Many slow-speed highways can also be combined and sent out on a single high-speed highway.

The figure below depicts an example where time slots are being received on different highways at different data rates and are being switched and sent out at a slower, same, or faster data rate. Each rectangle, labeled A—N, represents an 8-bit time slot.

FSYNC

RXD0 (2 Mbits/s) A

RXD1 (4 Mbits/s)

TXD2 (2 Mbits/s)

TXD3 (4 Mbits/s)

TXD4 (8 Mbits/s)

C D E F

G H I J K L M NRXD2 (8 Mbits/s)

Figure 9. Mixed-Highway Data Rates

LN M

5-7077(F)

19Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

TDM Highway Interface Timing

Virtual and Physical Frames

Figure 10 below shows a virtual frame offset from the physical frame. The FSYNC pulse marks the beginning of the physical frame, but the TSI can be programmed to interpret the location of time slot 0 at any point in a frame. Several parameters are available to make up the offset for a virtual frame with various levels of granularity. There is XTSOFF/RTSOFF for transmit/receive time-slot offsets. This offset can be up to 31 time slots for a 2.048 Mbits/s highway, 63 time slots for a 4.096 Mbits/s highway, or 127 time slots for an 8.192 Mbits/s highway. XBITOFF/ RBITOFF allow the setting of up to a 7-bit offset for transmit/receive frames. XFBOFF/RFBOFF allow fractional bit offsets of 0, 1/4, 1/2, or 3/4 bits. All of these offsets mentioned above can be independently programmed for each one of the transmit and receive highways. The maximum offset that can be introduced on an 8.192 Mbits/s highway is 127 time slots, 7 3/4 bits. The maximum offset on a 4.096 Mbits/s highway is 63 time slots and 7 3/4 bits. The maximum offset on a 2.048 Mbits/s highway is 31 time slots, 7 3/4 bits.

The following examples indicate how virtual offsets can be used to simplify system designs. For example, data that is being sent to the TSI on a particular Rx highway may have incurred a several time-slot delay due to processing by HDLC formatters, echo cancellers, communication protocol processors, etc. Rather than adding an external buffer to realign all the highway data to the next FSYNC, an offset to create a virtual frame on that Rx highway can be used instead. On a transmit highway, for example, there may be a device downstream that has a processing latency of N time slots. An offset of (32 – N) time slots can be added beforehand on a 2.048 Mbits/s highway so that after processing, the TDM data is aligned to FSYNC again.

Fractional bit offsets are handy for adjusting the sampling point on a Rx highway . With a 1/4-bit resolution possible, setup and hold time requirements on the Rx TDM highways for the TSI should be easily met. On transmit highways, fractional bit offsets can be used to shift the outgoing highway data slightly, so the destination device’s setup and hold times can be met with adequate margins. Note that the time slot, bit, and fractional bit offsets are relative to the highway data rate and imply different durations on different speed highways. For example, a 1/4-bit offset on a 2.048 Mbits/s highway means 122 ns, on a 4.096 Mbits/s highway, it is 61 ns, and on an 8.192 Mbits/s highway, it implies a 30.5 ns offset.

FSYNC

Rx HIGHWAY

Tx HIGHWAY

Rx OFFSET

PHYSICAL FRAME, N

VIRTUAL Rx FRAME, N VIRTUAL Rx FRAME, N + 1

VIRTUAL Tx FRAME, N VIRTUAL Tx FRAME, N + 1Tx OFFSET

PHYSICAL FRAME, N + 1

5-7464(F)r.2

Figure 10. Virtual and Physical Frames

20 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

TDM Highway Interface Timing

(continued)

TDM Highway Alignment at Zero Offset

The TDM highway interface logic is designed to make interconnection to the TTSI1K16T as simple as possible. Consider the timing diagram shown in Figure 11 below. Assume the following configuration register settings:

■

FSYNC is active-high, FSP (bit 2) is set to 1 in the general command register.

■

FSYNC is sampled by the rising edge of CK, FSSE (bit 1) is set to 1 in the general command register.

■

The Tx and Rx highways are all set for zero bit and time-slot offset.

■

The input CK speed is equal to the highway data rate. One can see that time slot 0 of a frame coincides with the sampling of an active FSYNC. At that edge:

■

Bit 0 of time slot 0 is latched from the Rx highway with the coincident clock.

■

Bit 0 of time slot 0 is transmitted starting with the coincident clock.

HIGHWAY

FSYNC

Rx TIME SLOT 0, BIT 0 Rx TIME SLOT 0, BIT 0

FSYNC SAMPLED ACTIVE Rx TIME SLOT 0 BIT 0 SAMPLE POINT

TX HIGHWAY

Tx TIME SLOT 0, BIT 0 Tx TIME SLOT 0, BIT 1

5-6958(F)r.2

Figure 11. Synchronization to FSYNC

TDM Highway Offsets

An offset may be added to the sampling of Rx time slot 0, bit 0 or the transmission of Tx time slot 0, bit 0. This can be done on any of the receive and/or transmit highways, totally independent from one another. This is done by setting the time-slot offset number, bit offset number, and fractional bit offset number on a per-highway basis using the receive and transmit highway configuration registers. To illustrate this point, consider the timing diagram shown in Figure 12 on page 22. Assume the following configuration register programming:

■

The input CK speed is set to 8.192 MHz.

■

FSYNC is active-high, FSP (bit 2) is set to 1 in the general command register.

■

FSYNC is sampled by the rising edge of CK, FSSE (bit 1) is set to 1 in the general command register.

■

The RXD0 highway is set for 3/4-bit offset and a highway data rate of 4.096 Mbits/s.

■

The TXD0 highway is set for 1-bit offset and a highway data rate of 2.048 Mbits/s. One can see that bit 0 of the receiv e time slot 0 is sa mpled 1 and 1/2 CK cycles aft er FSYNC is sampl ed active.

Since CK is set for 8.192 MHz and RXD0 is set for 4.096 Mbits/s, then 1 and 1/2 CK cycles equals 3/4 of a

4.096 Mbits/s bit period.

21Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

TDM Highway Offsets

(continued)

One can also see that bit 0 of the transmit time slot 0 is driven four CK cycles after FSYNC is sampled active. Since CK is set for 8.192 MHz and TXD0 is set for 2.048 Mbits/s, then four CK cycles equals one 2.048 Mbits/s bit period.

FSYNC

CK—8.192 MHz

RXD0—4.096 Mbits/s

(3/4-bit OFFSET)

TXD0—2.048 Mbits/s

(1-bit OFFSET)

TIME SLOT 63, BIT 7

TIME SLOT 31, BIT 6 TIME SLOT 31, BIT 7 TIME SLOT 0, BIT 0

FSYNC SAMPLED ACTIVE

Rx TIME SLOT 0 BIT 0 SAMPLE POINT

TIME SLOT 0, BIT 0

TIME SLOT 0, BIT 1

5-7062(F)r .2

Figure 12. Highway Offsets

Reset Sequence

The reset sequence of the TTSI1K16T is related to the PLL operation. In order for the chip to be properly reset, the PLL must have already established a lock on the CK input signal. That event will occur 250 µs after the CK input is functioning. After the PLL is locked onto the input clock, the TTSI1K16T will be in a reset state within 200 ns. This results in a reset time of 250.2 µs. Subsequent resets will take 200 ns, provided CK is not interrupted.

RESET

is an asynchronous signal and requires no setup or hold margins relative to any other input clock or signal.

After a reset, BIST must be run on the TTSI1K16T to bring all the memories in the device to a known state. This is required for correct operation of the chip. See the description below Table 17, BIST Command Register (0x02), on page 37, on how to run BIST.

22 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Low-Latency and Frame-Integrity Modes

Transmit time slots can be selected for low-latency (minimum delay) or for frame-integrity modes using the connection store memory.

Low Latency

Low latency causes a received time slot to be transmitted as soon as possible. This mode is useful for voice channels where minimum delay through the network is desirable. If the transmit (Tx) time slot is very close or before the receive (Rx) time slot, then the data will be transmitted in the next frame. If a particular transmit time slot is physically later in time than the receive time slot by a certain duration (time-slot separation), then the data will be transmitted in the current frame. The latency will be equal to the separation of the two time slots involved. The maximum latency that data can encounter through the TSI in low-latency mode is 134 µs. If this latency is sufficient for a particular application, disregard any of the following details.

The required separation that will cause the time slot to be transmitted in the current frame is as follows: the Tx time-slot position in the physical frame must be greater than or equal to the Rx time-slot position in the physical frame, by a duration of 2 Rx time slots + (4 + i) x 30.5176 ns, where i is the Tx highway number.

When Rx and Tx highway data rates are equal and the Rx and Tx highway offsets are set to zero, the following table shows the result of the above relationship for various Tx highways.

Table 8.

Rx Highway

Time-Slot Separation Required for Transmission with Minimum Latency (0 Offsets)

Data Rate

(Mbits/s)

Tx Highway

Data Rate

(Mbits/s)

Time-Slot (ts) Separation Required for Transmission in

Current Frame on Highway

TXD0 TXD4 TXD8 TXD15

2.048 2.048 2 ts, 1/4 bit 2 ts, 1/2 bit 2 ts, 3/4 bit 2 ts, 1 1/4 bits

4.096 4.096 2 ts, 1/2 bit 2 ts, 1 bit 2 ts, 1 1/2 bits 2 ts, 2 1/2 bits

8.192 8.192 2 ts, 1 bit 2 ts, 2 bits 2 ts, 3 bits 2 ts, 4 3/4 bits

For example:

■

If data is received in time slot 0 at 2.048 Mbits/s, it could be passed through the device

transmitted on time slot 3 at 2.048 Mbits/s

■

If data is received in time slot 1 at 4.096 Mbits/s, it could be passed through the device

transmitted on time slot 4 at 4.096 Mbits/s

■

If data is received in time slot 2 at 8.192 Mbits/s, it could be passed through the device

transmitted on time slot 5 at 8.192 Mbits/s

of TXD0.

of TXD8.

of TXD15.

with minimum latency if

If the Rx highway has an offset, then the relationship can be updated. The Rx_time-slot_position is defined as the Rx_time-slot_number + Rx_highway offset. The new relationship will determine the transmit time-slot position in the physical frame at which the received data can be transmitted with minimum delay. The new relationship is (i = Tx highway number)

Tx_time-slot_position ≥ Rx_time-slot_number + Rx highway offset + 2 Rx time slots +

If the Tx highway also has an offset, then the relationship becomes (i = Tx highway number):

Tx_time-slot_number + Tx highway offset ≥

Rx_time-slot_number + Rx highway offset + 2 Rx time slots +

(4 + i) x 30.5176 ns

23Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Low-Latency and Frame-Integrity Modes

Low Latency

For example, consider any Rx highway running at 4.096 Mbits/s using time slot 5 to receive data, with an Rx highway offset of 3 time slots. It is to be transmitted on TXD6. The right hand side of the relationship evaluates to:

5 time slots @ 4.096 Mbits/s + 3 time slots @ 4.096 Mbits/s + 2 time slots @ 4.096 Mbits/s +

(4 + 6) x 30.5176 ns

19,836.426 ns

The results of the calculation show that the received data can be transmitted with minimum delay using a Tx time slot located number for transmission with minimum delay

Tx time slot 21 @ 8.192 Mbits/s Tx time slot 11 @ 4.096 Mbits/s Tx time slot 6 @ 2.048 Mbits/s

(continued)

19,836.426

ns (or later) into the physical frame on TXD6. With a zero offset on TXD6, the time-slot

would be:

(continued)

Frame Integrity

Frame integrity is applied to multiple transmit time slots in order to force data received in the same frame to be transmitted together in a subsequent frame. This rule causes added delay, but it is useful for wideband data. Such data could be ISDN BRI (2B channels) that take up two time slots on a receive highway. It could also be an ISDN H0 channel (six contiguous time slots) that is being used to carry video.

The maximum latency through the device for any time slot marked for frame integrity mode is 378 µs. If that latency is sufficient for a particular application, disregard any of the following details.

To understand the latency involved with frame-integrity mode, consider the following information. The definition of frame integrity states that integrity is maintained between a particular Rx and Tx highway pair. This pair can be made up of any Rx highway and any Tx highway.

Latency due to frame integrity mode is a function of the highway offsets of the Rx and Tx pair rather than the relative position of the time slots. Latency in this mode will be expressed in terms of physical frames. Whether time slots received in virtual Rx frame N will end up going out in virtual Tx frame N + 1, N + 2, or N + 3 is dependent on the relative highway Rx and Tx highway offsets. For a description of virtual frames, see Figure 10, Virtual and Physical Frames on page 20.

Consider the following example. Assume RXD0 is switched to TXD1 with all Tx time slots marked for frame integrity (FI) on TXD1. If it is desirable to have the lowest possible latency for the data received on RXD0, then TXD1 must have a highway offset which is 3.90625 µs (1 time slot @ 2.048 Mbits/s) greater than the highway offset selected for RXD0. In that case, time slots received in the virtual Rx frame (frame N) will be transmitted in the next virtual Tx frame (frame N + 1).

The greatest latency will be incurred when the RXD0 offset is at least 121.09375 µs (31 time slots @

2.048 Mbits/s) greater than the offset selected for TXD1. In that case, time slots received in the current virtual Rx frame (frame N) will be transmitted three frames later, i.e., in virtual Tx frame N + 3.

For all other RXD0 and TXD1 offset values, time slots received in the current virtual Rx frame will be transmitted two frames later, i.e., in virtual Tx frame N + 2.

24 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Low-Latency and Frame-Integrity Modes

Frame Integrity

The range of Rx and Tx offsets can be independently selected from 0 µs to (125 – ∆)µs via the Rx and Tx highway configuration registers, bytes 0 and 1, where ∆ = 1/4 bit. The offset difference (Tx highway offset – Rx highway offset) can therefore take the range from transmission for the various cases of offset difference.

Table 9.

* The values for A, B, C, and D are specified in Table 10 below.

Table 10. Offset Difference Boundaries

Difference

Offset Difference and Its Effect on Frame for Transmission

Offset Difference = (Tx Highway Offset – Rx Highway Offset) Virtual Frame for Transmission

Offset

Boundary

A −(125 − ∆) −(31 ts, 7 3/4 bits) −(63 ts, 7 3/4 bits) −(127 ts, 7 3/4 bits) B −121.09375 −31 ts −62 ts −124 ts C +3.90625 1 ts 2 ts 4 ts D +(125 − ∆) 31 ts, 7 3/4 bits 63 ts, 7 3/4 bits 127 ts, 7 3/4 bits

(continued)

A ≤ offset difference < B* B ≤ offset difference < C* C ≤ offset difference ≤ D*

Boundary

Value

(µs)

Boundary Value in Terms of Time Slots (ts) and Bits, at Different Data Rates

(125 – ∆)µs to +(125 – ∆)µs. The table below shows the virtual frame for

−

2.048 Mbits/s 4.096 Mbits/s 8.192 Mbits/s

(continued)

N + 3 N + 2 N + 1

Table 9 and Table 10 can be used to determine the latency of time slots through the TSI in a frame integrity situation. Keep in mind that the offset difference is the major factor in determining which virtual Tx frame the time slots will go out in. The boundary values given in Table 10 are accurate to within ±1 time slot @ 8.192 Mbits/s (= ±4 bits @ 4.096 Mbits/s = ±2 bits @ 2.048 Mbits/s) and will depend on your particular register settings.

This example can be used to determine the latency of a frame integrity situation. Keep in mind that only the Tx and Rx highway offsets are relevant when determining the number of physical frames that the transmit data will incur. However, there is a small range of offset separation where the data will go out in either virtual Tx frame N + 2 or N + 3, depending on the actual Rx and Tx offsets chosen.

There may be many Rx/Tx highway pairs performing frame integrity simultaneously, but the definition of frame integrity states that integrity is maintained between each Rx and Tx pair and not across multiple receive highways. However, in practice, if a Tx highway contains FI time slots from multiple Rx highways and those Rx highways have the same highway offset, then all of the FI time slots will incur equal delay with frame integrity through the switch.

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TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Low-Latency and Frame-Integrity Modes

Frame Integrity

(continued)

In the example shown below in Figure 13, a receive and transmit highway are both running at 2.048 Mbits/s. There are 32 time slots for each 125 µs frame. The Rx and Tx highway offsets are zero. This makes the offset difference zero. Therefore, time slots selected for FI will be transmitted two frames later.

The TSI is configured to perform the following switching function:

Tx time slot 31 is sourced from Rx time slot 0 in low-latency mode. It goes out in frame N. Tx time slot 2 is sourced from Rx time slot 2 in low-latency mode. It goes out in frame N + 1. Tx time slot 30 is source from Rx time slot 1 in frame-integrity mode. It goes out in frame N + 2. Tx time slot 0 is sourced from Rx time slot 3 in frame-integrity mode. It goes out in frame N + 2.

FRAME B FRAME C FRAME D FRAME E

FSYNC

HIGHWAY

B1B2B

B29B30B

Z1B

C1C2C

C29C30C

A1C

D1D

D29D30D

0B1

E1E

Figure 13. Mixed Low-Latency and Frame-Integrity Modes

5-7075(F)r.1

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Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Test-Pattern Generati on

Test-pattern generation involves selecting outgoing time slots on a particular transmit highway for use in transmitting one of 15 patterns of data. The patterns available are selected using TPS[3—0] (bits 7—4) of the Test-Pattern Style Register (0x0A), Table 25 on page 42. The transmit highway and time slots involved are selected using the connection store.

Using the connection store, time slots can be set for test-pattern mode and the on-chip test-pattern generator will be the source for that transmitted data. The type of test pattern used is determined by the values in the Test-Pattern Style Register (0x0A), Table 25 on page 42. Test-pattern data can be applied to any number of time slots on only one highway at a time. Any highway may be selected to transmit test-pattern data. The only restrictions for selecting the time slots set for test-pattern mode are that the time slots must be from the same highway and they must be contiguous.

The sequence for enabling test-pattern generation is as follows:

1. Set TSDSM[2—0] (bits 7—5) in byte 1 of the connection store locations which correspond to the time slots involved in test-pattern substitution mode. Any range of time slots may be selected for test-pattern substitution mode, starting at any time-slot position. The remaining time slots of that highway will be unaffected.

2. Set TPS[3—0] (bits 7—4) of the Test-Pattern Style Register (0x0A), Table 25 on page 42 to select the test pattern to be sent. If a fixed user-defined byte is selected for transmission via the TPS[3—0] bits, then the TestPattern Generator Data Register (0x12), Table 33 on page 44 must also be programmed.

3. Select the data rate of the test-pattern generator via GENHDR[1—0] (bits 5—4) and set STTPG (bit 7) to 1 in the Test Command Register (0x09), Table 24 on page 41 to start transmitting a good test pattern on the selected time slots.

In order for data to be transmitted, highways need to be enabled using XE (bit 2) of the Transmit Highway Configuration Register (Byte 2) (0x1002 + 4i), Table 37 on page 46 and GXE (bit 0) of the General Command Register (0x00), Table 15 on page 36. This can be done before or after the above sequence.

The Tx highway that has been selected for test-pattern generation must be the only highway that has time slots selected for test-pattern substitution mode (i.e., TSDSM[2—0] = 110) in the connection store. No time slots on any other Tx highway may be selected for test-pattern substitution mode. If the Tx highway selected for test-pattern generation is changed, then the previous highway must have all its time slots that were in the TSDSM[2—0] = 110 mode, to be changed to a non-test-pattern substitution mode.

Test-Pattern Checking

Test-pattern checking involves selecting incoming time slots on a particular receive highway for reception of one of 15 test patterns. The patterns available are selected by setting CPS[3—0] (bits 3—0) of the Test-Pattern Style Register (0x0A), Table 25 on page 42. The input highway and time slots involved are selected using the following registers:

■

Test-Pattern Checker Highway Register (0x0B), Table 26 on page 43

■

Test-Pattern Checker Upper Time-Slot Register (0x0C), Table 27 on page 43

■

Test-Pattern Checker Lower Time-Slot Register (0x0D), Table 28 on page 43

Test-pattern data can be checked on any number of time slots on only one highway at a time. Any receive highway may be selected to check for test-pattern data. The only restriction on selecting the time slots set for testpattern checking is that the time slots must be from the same highway and they must be contiguous.

The sequence for enabling test-pattern checking is as follows:

1. Set Test-Pattern Checker Highway Register (0x0B), Table 26 on page 43 to select a highway for receiving the test data.

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TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Test-Pattern Checking

2. Set the Test-Pattern Checker Upper Time-Slot Register (0x0C), Table 27 on page 43 and the Test-Pattern Checker Lower Time-Slot Register (0x0D), Table 28 on page 43 to indicate the range of input time slots which will be carrying test data. The range is inclusive of the time slots indicated in both registers. If only one time slot is to be selected, then the upper and lower registers should be set to the same value.

3. Set CPS[3—0] (bits 3—0) of the Test-Pattern Style Register (0x0A), Table 25 on page 42 to select the test pattern to detect. If a fixed, user-defined byte is to be detected, the CTP[7—0] bits in the Test-Pattern Checker Data Register (0x0E), Table 29 on page 43 should also be programmed with the user-defined pattern.

4. Select the data rate of the test-pattern checker via CHKHDR[1—0] (bits 3—2) and set STTPC (bit 6) in the Test Command Register (0x09), Table 24 on page 41 to prompt the checker to attempt to lock onto the selected test-pattern style.

If there is a need to restart the checker (i.e., the test-pattern style has changed), then STTPC (bit 6) of the Test Command Register (0x09), Table 24 on page 41 must first be cleared to 0, and then steps 3 and 4 should be repeated.

There is an interrupt register status bit related to the test-pattern checker. TPD (bit 5) of the Interrupt Status Register (0x07), T able 22 on page 39 is used to determine when, if ever, the pattern is detected. The TPD interrupt status bit will remain 0 until the pattern has been detected. This bit is cleared when read. Once TPD is set, it will not be set again until the checker is instructed to relock on the test pattern by clearing and then setting STTPC (bit 6) in the test command register.

(continued)

Error Injection

The error injection feature provides the capability to inject errors into the outgoing test-pattern data. The number of errors injected is set using the Test-Pattern Error Injection Register (0x0F), Table 30 on page 43.

If error injection is required, the process should start by setting up the test-pattern generator using steps 1—3 in the T est-Pattern Generation section on page 27. In order to start injecting errors into the outgoing test pattern, write the T est-Pattern Error Injection Register (0x0F), T able 30 on page 43 with the number of errors desired. When all of the errors have been injected into the outgoing data stream, the interrupt status bit BEI (bit 0) will be set in the Interrupt Status Register (0x07), Table 22 on page 39. Errors will be injected at the rate of one per time slot. Test Command Register (0x09), Table 24 on page 41 will be cleared to 0 when BEI is set.

Error Checking

Errors are checked on time slots marked for test-pattern data once the checker has locked onto the test pattern. Every time an error is detected, the ERD (bit 3) interrupt status bit is set and the test-pattern error counter register contents are incremented. There are two registers Test-Pattern Error Counter (Byte 0) (0x10), Table 31 on page 44 and Test-Pattern Error Counter (Byte 1) (0x11), Table 32 on page 44, that are used to track the number of errors detected on incoming test patterns.

The error counter registers are reset after both have been read. In order to ensure that the correct value is read from these registers, byte 0 must be read first followed by byte 1. This action will latch the counter value and allow the counter logic to be reset and then continue recording.

28 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

JTAG Boundary-Scan Specification

Principle of t he Boundary Scan

The boundary scan (BS) is a test aid for chip, module, and system testing. The key aspects of BS are as follows:

1. Testing the connections between ICs on a particular board.

2. Observation of signals to the IC pins during normal operating functions.

3. Controlling the built-in self-test (BIST) of an IC. TTSI1K16T does not support BS-BIST. Designed according to the

test access port (TAP). The TAP is made up of four signal pins assigned solely for test purposes. The fifth test pin ensures that the test logic is initialized asynchronously. The BS test logic also comprises a 16-state TAP controller, an instruction register with a decoder, and several test data registers (BS register, BYPASS register, and IDCODE register). The main component is the BS register that links all the chip pins to a shift register by means of special logic cells. The test logic is designed in such a way that it is operated independently of the application logic of the TTSI1K16T (the mode multiplexer of the BS output cells may be shared). Figure 14 illustrates the block diagram of the TTSI1K16T’s BS test logic.

IEEE

Std. 1149.1-1990 standard, the BS test logic consists of a defined interface: the

BOUNDARY-SCAN REGISTER

TDI

TRST

TMS

TCK

CHIP KERNEL

MUX

OUT

TDO

CONTROLLER

(UNAFFECTED BY BOUNDARY-SCAN TEST)

IDCODE REGISTER

BYPASS REGISTER

INSTRUCTION REGISTER

TAP

INSTRUCTION

DECODER

Figure 14. Block Diagram of the TTSI1K16T's Boundary-Scan Test Logic

5-3923(F)r.4

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TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

JTAG Boundary-Scan Specification

(continued)

Test Access Port Controller

The test access port controller is a synchronous sequence controller with 16 states. The state changes are preset by the TMS, TCK, and TRST TCK edge rises. Figure 15 shows the TAP controller state diagram.

signals and by the previous state. The state changes always take place when the

TRST = 0

TEST LOGIC

RESET

RUN TEST/

IDLE

SELECT DR

CAPTURE DR

SHIFT DR

SELECT IR

CAPTURE IR

SHIFT IR

EXIT1 DR

PAUSE DR

EXIT2 DR

UPDATE DR

EXIT1 IR

PAUSE IR

EXIT2 IR

UPDATE IR

5-3924(F)r.5

Figure 15. BS TAP Controller State Diagram

The value shown next to each state transition in Figure 15 represents the signal present at TMS at the time of a rising edge at TCK.

The description of the TAP controller states is given in

IEEE

Std. 1149.1-1990 Section 5.1.2 and is reproduced in

Table 11 and Table 12.

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Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

JTAG Boundary-Scan Specification

Test Access Port Controller

Table 11. TAP Controller States in the Data Register Branch

Name Description

TEST LOGIC RESET The BS logic is switched in such a way that normal operation of the ASIC is

adjusted. The IDCODE instruction is initialized by TEST LOGIC RESET. Irrespective of the initial state, the TAP controller has achieved TEST LOGIC RESET after five control pulses at the latest when TMS = 1. The TAP controller then remains in this state. This state is also achieved when TRST

RUN TEST/IDLE Using the appropriate instructions, this state can activate circuit parts or initiate

a test. All of the registers remain in their present state if other instructions are used.

SELECT DR This state is used for branching to the test data register control.

CAPTURE DR The test data is loaded in the test data register parallel to the rising edge of TCK

in this state.

SHIFT DR The test data is clocked by the test data register serially to the rising edge of TCK

in the state. The TDO output driver is active.

EXIT (1/2) DR This temporary state causes a branch to a subsequent state.

PAUSE DR The input and output of test data can be interrupted in this state.

UPDATE DR The test data is clocked into the second stage of the test data register parallel to

the falling edge of TCK in this state.

(continued)

= 0.

Table 12. TAP Controller States in the Instruction Register Branch

Name Description

SELECT IR This state is used for branching to the instruction register control.

CAPTURE IR The instruction code 0001 is loaded in the first stage of the instruction register

parallel to the rising edge of TCK in this state.

SHIFT IR The instructions are clocked into the instruction register serially to the rising edge

of TCK in the state. The TDO output driver is active.

EXIT (1/2) IR This temporary state causes a branch to a subsequent state.

PAUSE IR The input and output of instructions can be interrupted in this state.

UPDATE IR The instruction is clocked into the second stage of the instruction register parallel

to the falling edge of TCK in this state.

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TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

JTAG Boundary-Scan Specification

(continued)

Instruction Register

The instruction register (IR) is 4 bits in length. Table 13 shows the BS instructions implemented by the TTSI1K16T.

Table 13. TTSI1K16T’s Boundary-Scan Instructions

Instruction Code Act. Register

TDI→TDO

EXTEST 0000 Boundary Scan TEST Test external

IDCODE 0001 Identification NORMAL Read Manuf.

HIGHZ 0100 BYPASS X 3-state Output—High Impedance

SAMPLE/PRELOAD 0101 Boundary Scan NORMAL Sample/load Core Logic

BYPASS 1111 BYPASS NORMAL Min shift path Core Logic

EVERYTHING ELSE — BYPASS X — Output—High Impedance

The instructions not supported in TTSI1K16T are INTEST, RUNBIST, and TOGGLE. A fixed binary 0001 pattern (the 1 into the least significant bit) is loaded into the IR in the CAPTURE IR controller state. The IDCODE instruction (binary 0001) is loaded into the IR during the test-logic-reset controller state and at powerup.

Mode Function Output Defined Via

BS Register

connections

Core Logic

The following is an explanation of the instructions supported by TTSI1K16T and their effect on the devices' pins. EXTEST: This instruction enables the path cells, the pins of the ICs, and the connections between ASICs to be tested via the

circuit board. The test data can be loaded in the chosen position of the BS register by means of the SAMPLE/PRELOAD instruction. The EXTEST instruction selects the BS register as the test data register. The data at the function inputs is clocked into the BS register on the rising edge of TCK in the CAPTURE DR state. The contents of the BS register can be clocked out via TDO in the SHIFT DR state. The value of the function outputs is solely determined by the contents of the data clocked into the BS register and only changes in the UPDATE DR state on the falling edge of TCK.

IDCODE: Information regarding the manufacturer’s ID for Lucent, the IC number, and the version number can be read out

serially by means of the IDCODE instruction. The IDCODE register is selected, and the BS register is set to normal mode in the UPDATE IR state. The IDCODE is loaded at the rising edge of TCK in the CAPTURE DR state. The IDCODE register is read out via TDO in the SHIFT DR state.

HIGHZ: All 3-statable outputs are forced to a high-impedance state, and all bidirectional ports are forced to an input state

by means of the HIGHZ instruction. The impedance of the outputs is set to high in the UPDATE IR state. The function outputs are only determined in accordance with another instruction if a different instruction becomes active in the UPDATE IR state. The BYP ASS register is selected as the test data register. The HIGHZ instruction is implemented in a similar manner to that used for the BYPASS instruction.

SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction enables all the input and output pins to be sampled during operation (SAM-

PLE) and the result to be output via the shift chain. This instruction does not impair the internal logic functions. Defined values can be serially loaded in the BS cells via TDI while the data is being output (PRELOAD).

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Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

JTAG Boundary-Scan Specification

Instruction Register

BYPASS: This instruction selects the BYPASS register. A minimal shift path exists between TDI and TDO. The BYPASS reg-

ister is selected after the UPDATE IR. The BS register is in normal mode. A 0 is clocked into the BYPASS register during CAPTURE DR state. Data can be shifted by the BYPASS register during SHIFT DR. The contents of the BS register do not change in the UPDATE DR state. Please note that a 0 that was loaded during CAPTURE DR appears first when the data is being read out.

(continued)

Boundary-Scan Register

The boundary-scan register is a shift register, whereby one or more BS cells are assigned to every digital TTSI1K16T pin. The TTSI1K16T’s boundary-scan register bit-to-pin assignment is defined in the BSDL file, which is available upon request.

BYPASS Register

The BYPASS register is a one-stage shift register that enables the shift chain to be reduced to one stage in the TTSI1K16T.

IDCODE Register

The IDCODE register identifies the TTSI1K16T by means of a parallel, loadable, 32-bit shift register. The code is loaded on the rising edge of TCK in the CAPTURE DR state. The contents of this register is indicated in the BSDL file.

3-State Procedures

The 3-state input participates in the boundary scan. It has a BS cell, but buffer blocking via this input is suppressed for the EXTEST instruction. The 3-state input is regarded as a signal input that is to participate in the connection test during EXTEST. The buffer blocking function should not be active during EXTEST to ensure that the update pattern at the TTSI1K16T outputs does not become corrupted.

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TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Register Architecture

Table 14 is an overview of the register architecture. The table is a summary of the register function and address. Complete detail of each register is given in the following sections.

Table 14. TTSI1K16T Register Summary

Address (Hex)

Reserved 5000—7FFF Connection Store Memory 4000—4FFF Reserved 2800—3FFF Data Store Memory 2000—27FF Reserved 1840—1FFF Receive Highway 15—Reserved 183F Receive Highway 15 Configuration Byte 2 183E Receive Highway 15 Configuration Byte 1 183D Receive Highway 15 Configuration Byte 0 183C

. . . . . .

Receive Highway 0—Reserved 1803 Receive Highway 0 Configuration Byte 2 1802 Receive Highway 0 Configuration Byte 1 1801 Receive Highway 0 Configuration Byte 0 1800 Reserved 1040—17FF Transmit Highway 15—Reserved 103F Transmit Highway 15 Configuration Byte 2 103E Transmit Highway 15 Configuration Byte 1 103D Transmit Highway 15 Configuration Byte 0 103C

. . . . . .

Transmit Highway 0—Reserved 1003 Transmit Highway 0 Configuration Byte 2 1002 Transmit Highway 0 Configuration Byte 1 1001 Transmit Highway 0 Configuration Byte 0 1000 Reserved 0014—0FFF Version Register 0013 Test-Pattern Generator Data Register 0012 Test-Pattern Error Counter Byte 1 0011 Test-Pattern Error Counter Byte 0 0010

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Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Table 14. TTSI1K16T Register Summary

Test-Pattern Error Injection Register 000F Test-Pattern Checker Data Register 000E Test-Pattern Checker Lower Time-Slot Register 000D Test-Pattern Checker Upper Time-Slot Register 000C Test-Pattern Checker Highway Register 000B Test-Pattern Style Register 000A Test Command Register 0009 Interrupt Mask Register 0008 Interrupt Status Register 0007 Global Interrupt Mask Register 0006 Idle Code 3 Register 0005 Idle Code 2 Register 0004 Idle Code 1 Register 0003 BIST Command Register 0002 Software Reset Register 0001 General Command Register 0000

(continued)

Address (Hex)

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TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Configuration Register Architecture

: All registers’ bits default to 0 upon reset, unless noted otherwise.

Note

All TDM highway data, which is stored in the TSI, will have the following convention. Bit 7 is first transmitted and first received; bit zero is last transmitted and last received. This convention applies to the data read from the data store, the host data transmitted via the connection store, and any other configuration register which stores highway data, such as the idle code registers and the test-pattern generator data register.

Table 15. General Command Register (0x00)

Bit Symbol Name/Description

7CSV

6ED

Chip Select Valid.

cessor interface mode only. When this bit is programmed to be 1, the chip select input pin is sampled when AS active.

External Drivers.

indicates that no external buffers are being used; therefore, the TXD pins will become 3-stated for time slots that are programmed as such. A 1 indicates that the TXD output highways are connected to external drivers; thus, the TXD pins will always be driven to prevent floating nodes at the inputs of the external drivers. The TXOE[0—15] outputs always reflect the high-impedance status of the corresponding TXD[0—15] highways, regardless of the ED bit setting. The only exception to this is when TEST asserted, which 3-states all outputs.

This bit is valid while the TTSI1K16T is in synchronous micropro-

is active. When 0, chip select is latched one PCLK after AS is

Used to select the use of external drivers on transmit highways. A 0

See Table 41, Transmit Highway 3-State Options, on page 49 for other methods of

3-stating the transmit highways. 5— 4INTOE

3INTP

2FSP

1FSSE

0GXE

Reserved.

Interrupt Output Enable.

be driven based on the status of the internal interrupts and their corresponding individ-

ual mask bits. When 0, the output will remain 3-stated.

Interrupt Polarity.

A 1 selects an active-low interrupt output (INT

output (INT), and is the default polarity.

Frame Sync Polarity.

which designates the beginning of the frame. A 1 selects an active-high frame syn-

chronization (FSYNC). A 0 selects an active-low frame synchronization (FSYNC

Frame Sync Sample Edge.

used to sample the frame synchronization input. A 1 selects the rising edge; and a 0

selects the falling edge of CK.

Global Transmit Enable.

defaults to 0 so that all outputs can be held in a high-impedance state until they have

been configured and individually enabled.

For other methods of 3-stating transmit highways, see Table 41, Transmit Highway

3-State Options, on page 49.

Read as 0.

This bit, when set to a 1, enables the INT output signal to

This bit defines the polarity of INT, as output from the TTSI1K16T.

). A 0 selects an active-high interrupt

This bit defines the polarity of FSYNC, as sampled by CK,

This bit selects the clock edge of the CK input that is

When 0, all 16 transmit highways are 3-stated. GXE

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Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Configuration Register Architecture

Table 16. Software Reset Register (0x01)

Bit Symbol Name/Description

7—1 —

0SR

Table 17. BIST Command Register (0x02)

Bit Symbol Name/Description

7RB

6BD

5 BPF

4—0 —

Reserved. Software Reset.

similar to the RESET tialized to their default values except the software reset register. A 0 must be written to this bit in order to clear and release the software reset. The microprocessor interface will not be affected by the software reset, and the write to this bit will terminate normally.

Run BIST.

ory blocks (i.e., the data and connection stores). This bit must be cleared by writing a 0 when BIST is complete. That event is indicated via the BIST complete (BC) bit in the interrupt status register, as well as the BIST done (BD) bit in the BIST command register. Writing a 0 to this bit position will also clear the BD bit. A software reset should be performed after the BIST testing sequence is complete.

BIST Done (Read Only).

bit is used for polling to determine the completion of the BIST test. The real-time duration of the TSI BIST test is 2.8 seconds. This bit will remain set to a 1 reflecting the fact that the BIST is complete until the RB bit is written to a 0.

BIST Pass

results. A 0 indicates that no errors were detected.

Reserved.

Read as 0.

Writing a 1 to this bit begins the built-in self-test for all internal mem-

/Fail (Read Only).

Read as 0.

(continued)

Writing a 1 to this bit resets the chip. This bit has a function

pin. When set to 1, all registers and control logic will be ini-

This bit indicates when the BIST test is complete. This

This bit indicates the status of the BIST test

The BIST test sequence is performed as follows:

1. Set RB (bit 7) in the BIST command register to 1 in order to initiate the internal BIST test.

2. Wait for the BIST complete (BC) (bit 1 of the interrupt status register) interrupt to occur via the interrupt status register, if it is not masked via the interrupt mask register MASKBC bit (bit 1). Alternatively, the host can poll the BD bit in the BIST command register which will also indicate the completion of BIST.

3. Once the BIST interrupt occurs or the BD bit is set, the BPF bit in the BIST command register will reflect the BIST pass/fail result. A BPF set to 0 indicates a pass.

4. Set RB (bit 7) in the BIST command register to a 0 in order to end the internal BIST test.

5. Issue a software reset via the SR bit in the software reset register.

During BIST, the TTSI1K16T will corrupt traffic and the contents of the connection store memory. The TTSI1K16T should, therefore, be taken off-line prior to running BIST and reprogrammed afterwards.

37Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Configuration Register Architecture

Table 18. Idle Code 1 Register (0x03)

Bit Symbol Name/Description

7—0 IC1

Table 19. Idle Code 2 Register (0x04)

Bit Symbol Name/Description

7—0 IC2

Table 20. Idle Code 3 Register (0x05)

Bit Symbol Name/Description

7—0 IC3

Idle Code 1[7—0].

outgoing time slot marked for idle code 1 transmission. Idle code transmission is enabled via the time-slot data select mode bits. See Table 45, Connection Store Memory (Byte 1), on page 51.

Idle Code 2[7—0].

outgoing time slot marked for idle code 2 transmission. Idle code transmission is enabled via the time-slot data select mode bits. See Table 45, Connection Store Memory (Byte 1), on page 51.

Idle Code 3[7—0].

outgoing time slot marked for idle code 3 transmission. Idle code transmission is enabled via the time-slot data select mode bits. See Table 45, Connection Store Memory (Byte 1), on page 51.

(continued)

This register is used to identify the data to be sent on any

Table 21. Global Interrupt Mask Register (0x06)

Bit Symbol Name/Description

7—1 —

0GIE

Reserved. Global Interrupt Enable.

asserted as a result of the possible interrupt conditions. This is in addition to the mask bits in the interrupt mask register. When 0, the INT output is blocked independent of the programming of the interrupt mask register. When 1, the INT output is enabled and will be asserted based on the interrupt status and mask bits.

Read as 0.

This bit must be written to a 1 in order for INT to be

38 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Configuration Register Architecture

Table 22. Interrupt Status Register* (0x07)

Bit Symbol Name/Description

7— 6FSERR

5TPD

4— 3ERD

2— 1BC

0BEI

* Read-only register.

Reserved. Frame Sync Error .

sync has occurred. This error could be a result of a missing FSYNC or a misaligned FSYNC.

Test Pattern Detected.

checker. When TPD = 0, the test-pattern checker selected test pattern. When TPD = 1, the test-pattern checker selected test pattern. Test-pattern data must be error-free for 32 time slots before it is considered detected. If 32 or more time slots are selected for test-pattern checking, this event could occur within one 125 µs frame. If only two time slots are selected for test-pattern checking, then the test pattern will be detected after 16 frames.

Reserved. Error Detected.

test pattern once the test pattern has first been detected.

Reserved. BIST Complete.

complete.

Bit Errors Inserted.

insert bit errors into the outgoing test pattern is complete.

(continued)

Read as 0.

When set to 1, this bit indicates that an error related to frame

The TPD bit indicates the state of the test-pattern

Read as 0 or 1.

This bit is set to 1 each time an error has been detected in the

Read as 0.

When set to 1, this status bit indicates that the BIST sequence is

When set to 1, this status bit indicates that the request to

has not

yet located the

located the

has

This register is clear on read. Once the status bits are read, they will remain cleared until the next interrupt event occurs. The interrupt mask register in combination with the global interrupt enable GIE (bit 0) in the global interrupt mask register determines when the INT pin gets asserted when an interrupt status bit gets set. In general, the interrupt status register bits will update regardless of the mask bits. The exception to this is the FSERR bit, which will not be set if the corresponding mask bit is set.

39Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Configuration Register Architecture

Table 23. Interrupt Mask Register (0x08)

Bit Symbol Name/Description

7— 6 MASKFS

5 MASKTPD

4— 3 MASKERD

2— 1 MASKBC

0 MASKBEI

Reserved. Mask Frame Sync Error Interrupt.

an interrupt as a result of a frame sync error. Resets to a 1, which prevents the status bit from generating an interrupt. Setting this bit to a 1 also prevents the detection of a frame sync error and, thus, the setting of the FSERR bit in the interrupt status register. This is done to prevent an unintended interrupt at the first FSYNC pulse after the reset sequence.

Mask Test-Pattern Detection Interrupt.

tion of an interrupt as a result of a test-pattern detection. Resets to a 1, which prevents the status bit from generating an interrupt.

Reserved. Mask Error Detected Interrupt.

interrupt as a result of a single bit error detected in the incoming test pattern. Resets to a 1, which prevents the status bit from generating an interrupt.

Reserved. Mask BIST Complete Interrupt.

interrupt as a result of completing the memory BIST. Resets to a 1, which prevents the status bit from generating an interrupt.

Mask Bit Errors Inserted Interrupt.

an interrupt as a result of completing the insertion of all requested bit errors. Resets to a 1, which prevents the status bit from generating an interrupt.

(continued)

Read as 0.

Read as 1. Always write a 1 to this bit when writing this register.

Set this bit to a 1 to mask the generation of an

Read as 1. Always write a 1 to this bit when writing this register.

Set this bit to a 1 to mask the generation of an

Set this bit to a 1 to mask the generation of

Set this bit to a 1 to mask the genera-

Set this bit to a 1 to mask the generation of

40 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Configuration Register Architecture

Table 24. Test Command Register (0x09)

Bit Symbol Name/Description

7 STTPG

6STTPC

5—4 GENHDR

[1—0]

3—2 CHKHDR

[1—0]

Start Test-Pattern Generator.

tor to start generating a test pattern based on the pattern indicated in the testpattern style register. Writing a 0 to this register will stop the test-pattern generation and provide the opportunity to change the test-pattern style.

Start Test-Pattern Checker.

start locking on to a test pattern based on the pattern indicated in the testpattern style register. Writing a 0 to this register will stop the test-pattern checking and provide the opportunity to change the test-pattern style.

Test-Pattern Generator Highway Data Rate.

the highway data rate of the transmit highway selected for test-pattern generation. It must match the Tx highway data rate which was set in transmit highway configuration register (byte 2), HDR[1—0] bits. The transmit highway selection for test-pattern generation is done using the connection store. Only one highway at a time can be involved with test-pattern generation. Test-pattern generation and checking does not affect the operation of other time slots or highways.

GENHDR1

0 0 2.048 Mbits/s (default) 0 1 4.096 Mbits/s 1 0 8.192 Mbits/s 1 1 0.000 Mbits/s (idle, not transmitting data)

Test-Pattern Checker Highway Data Rate.

highway data rate of the receive highway selected for test-pattern checking. It must match the Rx highway data rate which was set in receive highway configuration register (byte 2), HDR[1—0] bits. The transmit highway selection for testpattern generation is done using the test-pattern checker highway register. Only one highway at a time can be involved with test-pattern checking. Test-pattern generation and checking does not affect the operation of other time slots or highways.

(continued)

Writing a 1 to this register will cause the genera-

Writing a 1 to this register will cause the checker to

These bits are used to indicate

GENHDR0

These bits are used to indicate the

1—0 —

CHKHDR1

0 0 2.048 Mbits/s (default) 0 1 4.096 Mbits/s 1 0 8.192 Mbits/s 1 1 0.000 Mbits/s (idle, not receiving data)

Reserved.

CHKHDR0

Read as 0.

41Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Configuration Register Architecture

(continued)

Table 25. Test-Pattern Style Register (0x0A)

Bit Symbol Name/Description

7—4 TPS[3—0]

Generator Test-Pattern Style[3—0].

These 4 bits determine the type of test pattern

that will be generated by the on-line maintenance test-pattern generator.

TPS3

TPS2 TPS1 TPS0 Test-Pattern Description 0000MARK (all 1s)(AIS - red alarm) 0001QRSS (2 001031(2 001163(2 0100511(2 0101511(2 01102047(2 01112047(2 10002 10012 10102 10112

– 1 PRBS (O.151) (noninverted)

– 1 PRBS (O.153)

– 1 PRBS (reversed)

– 1 PRBS (V.33) (noninverted) 11001:1 (alternating 1s and 0s). 1101Reserved. 1110Reserved. 1111Fixed. User-defined byte, stored in the test-

pattern generator data register will be sent.

– 1 with zero suppression) (O.151)

– 1) PRBS

– 1) PRBS (O.153)

– 1) PRBS (reversed)

– 1) P R BS (O.152)

– 1) PRBS (reversed)

3—0 CPS[3—0]

PRBS = pseudorandom binary sequence. QRSS = quasi-random signal source.

Checker Test-Pattern Style[3—0].

These 4 bits determine the type of test pattern

that will be detected by the on-line maintenance test-pattern checker.

CPS3

CPS2 CPS1 CPS0 Test-Pattern Description 0000MARK (all 1s) (AIS - red alarm) 0001QRSS (2 001031(2 001163(2 0100511(2 0101511(2 01102047(2 01112047(2 10002 10012 10102 10112

15 20 20 23

– 1 with zero suppression) (O.151)

– 1) PRBS

– 1) PRBS (O.153)

– 1) PRBS (reversed)

– 1) P R BS (O.152)

– 1) PRBS (reversed) – 1 PRBS (O.151) (noninverted) – 1 PRBS (O.153) – 1 PRBS (reversed) – 1 PRBS (V.33) (noninverted)

11001:1 (alternating 1s and 0s). 1101Reserved. 1110Reserved. 1111Fixed. The checker will compare against the user-

defined byte, stored in the test-pattern checker data register.

PRBS = pseudorandom binary sequence. QRSS = quasi-random signal source.

42 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Configuration Register Architecture

Table 26. Test-Pattern Checker Highway Register (0x0B)

Bit Symbol Name/Description

7—4 — 3—0 CHS[3—0]

Table 27. Test-Pattern Checker Upper Time-Slot Register (0x0C)

Bit S ymbol Name/Description

7—

6—0 CKRUP[6—0]

Table 28. Test-Pattern Checker Lower Time-Slot Register (0x0D)

Reserved. Checker Highway Select[3—0].

which the test-pattern checker is connected.

Reserved. Checker Upper Time-Slot Select[6—0].

slot in the input highway to which the test-pattern checker is connected. All contiguous time slots that lie between the lower and upper time-slot boundaries inclusive are monitored for the test pattern. The range of time slots that can be monitored is from 1 time slot to the entire span (32, 64, and 128 time slots for a

2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s highway, respectively). If one time slot is to be monitored, then CKRUP and CKRLOW should be set to the same value.

(continued)

Must be written to 0.

These 4 bits determine the receive highway to

These 7 bits determine the upper time

Bit S ymbol Name/Description

7—

6—0 CKRLOW

[6—0]

Table 29. Test-Pattern Checker Data Register (0x0E)

Bit S ymbol Name/Description

7—0 CTP[7—0]

Table 30. Test-Pattern Error Injection Register (0x0F)

Bit S ymbol Name/Description

7—0 BEC[7—0]

Reserved. Checker Lower Time-Slot Select[6—0].

2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s highway, respectively). If one time slot is to be monitored, then CKRUP and CKRLOW should be set to the same value.

Checker Test Pattern[7—0].

when the fixed mode is programmed into the test-pattern style register.

Bit Error Count[7—0].

errors that are to be injected into the outgoing test pattern (QRSS, PRBS, or fixed user-defined byte). This register can be programmed to inject up to 255 bit errors. The BEI bit in the interrupt status register will indicate when all of the errors have been injected. BEC[7—0] will automatically be reset when BEI is set. In order to send out additional errors, BEC[7—0] should be rewritten. Errors are injected at the rate of one per time slot.

These 7 bits determine the lower time

The data written here will be used for comparison

This register is used to indicate the number of single bit

43Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Configuration Register Architecture

Table 31. Te st-Pattern Error Counter (Byte 0) (0x10)

(continued)

Bit Symbol Name/Description

7—0 EC[7—0]

Error Counter[7—0].

Least significant bits of 16-bit error counter. See note

below for resetting counter.

* Read-only register.

Table 32. Te st-Pattern Error Counter (Byte 1) (0x11)

Bit Symbol Name/Description

7—0 EC[15—8]

Error Counter[15—8].

Most significant bits of 16-bit error counter. See note

below for resetting counter.

* Read-only register.

The error counter will be incremented each time a bit error is detected by the pattern checker.

Note:

In order to ensure that the correct value is read from these registers, byte 0 must be read first followed by byte 1. This action will latch the error counter value and allow the counter to be reset and continue recording as time proceeds.

Table 33. Test-Pattern Generator Data Register (0x12)

Bit Symbol Name/Description

7—0 GTP[7—0]

Generator Test Pattern[7—0].

The data written here will be sent out repeatedly

if the fixed data test-pattern mode is selected in the test-pattern style register.

Table 34. Version Register (0x13)

Bit Symbol Name/Description

7—2 — 1—0 VER[1—0]

* Read-only register. † Reading a 00 from this register indicates version number 1.0.

Reserved. Version Number.

†

Read as 00

44 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Configuration Register Architecture

Table 35. Transmit Highway Configuration Register (Byte 0) (0x1000 + 4i)

Bit Symbol Name/Description

7—

6—4 XBITOFF

[2—0]

3—2 XFBOFF

[1—0]

Reserved. Transmit Highway Bit Offset[2—0].

an outgoing frame by the indicated number of bit times. If no bit offsets are required, these bits should be set to 000. The following list shows the effect of setting these bits.

000 = no bit offset 001 = 1-bit offset 010 = 2-bit offset . . . 111 = 7-bit offset

Bit periods are relative to the highway data rate set for each highway.

Note:

XTSOFF, XBITOFF, and XFBOFF are used in conjunction to define the start of the outgoing frame. The values are added together to position the sampling of time slot 0, bit 0 for each highway.

Transmit Highway Fractional Bit Offset[1—0].

beginning of an outgoing frame by the indicated number of fractional bit times. If no fractional bit offsets are required, these bits should be set to 00. The following list shows the effect of these bits.

(continued)

Read as 0.

XBITOFF is used to offset the beginning of

XFBOFF is used to offset the

1—0 —

* i = the transmit highway number.

00 = no fractional bit offset 01 = 1/4-bit fractional offset 10 = 1/2-bit fractional offset 11 = 3/4-bit fractional offset

Bit periods are relative to the highway data rate set for each highway.

Note:

XTSOFF, XBITOFF, and XFBOFF are used in conjunction to define the start of the outgoing frame. The values are added together to position the sampling of time slot 0, bit 0 for each highway.

Reserved.

Must be written to 00.

45Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Configuration Register Architecture

Table 36. Transmit Highway Configuration Register (Byte 1) (0x1001 + 4i)*

Bit Symbol Name/Description

7—

6—0 XTSOFF

[6—0]

* i = the transmit highway number.

Table 37. Transmit Highway Configuration Register (Byte 2) (0x1002 + 4i)

Reserved. Transmit Highway Time-Slot Offset[6—0].

beginning of an outgoing frame by the indicated number of time slots (bytes). If no time-slot offsetting is required, these bits should be set to zero. The following table shows the range of offsets for the different highway data rates.

Highway Data Rate

2.048 Mbits/s 0—31

4.096 Mbits/s 0—63

8.192 Mbits/s 0—127 A time slot is always 8 bits. A bit period is relative to the highway data rate

Note:

set for each highway. XTSOFF, XBITOFF, and XFBOFF are used in conjunction to define the start of

the outgoing frame. The values are added together to position the transmission of time slot 0, bit 0.

(continued)

Read as 0.

Time-Slot Offset Range

XTSOFF is used to offset the

Bit Symbol Name/Description

7—3 —

2XE

1—0 HDR[1—0]

* i = the transmit highway number.

: During CK input interruptions (e.g., clock switching), the transmit highways should be 3-stated by clearing

Note

the GXE (bit 0) of the general command register. The highways can be enabled by writing a 1 to the GXE bit once the PLL has regained lock (250 µs later).

Reserved. T r ansmit Highway 3-St ate Enable

impedance when this bit is 0 (default after reset). When this bit is set to 1, the output driver is enabled. The effect of this bit is dependent on the status of the external drive bit of the general command register. See Table 15, General Command Register (0x00), on page 36 for details. For other methods of 3-stating transmit highways, see Table 41, Transmit Highway 3-State Options, on page 49.

Transmit Highway Data Rate[1—0].

HDR1

All of the transmit highways are grouped into pairs. TXD0 with TXD1, TXD2 with TXD3, . . . , and TXD14 with TXD15. The maximum combined bandwidth for each pair is 8.192 Mbits/s. Refer to T able 7, Tx Highway Data Rate Options, on page 18 for highway rate combination.

Read as 0.

. The associated output highway is high

HDR0 0 0 2.048 Mbits/s (default) 0 1 4.096 Mbits/s 1 0 8.192 Mbits/s 1 1 0.000 Mbits/s (idle, not transmitting data)

46 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Configuration Register Architecture

Table 38. Receive Highway Configuration Register (Byte 0) (0x1800 + 4i)*

Bit S ymbol Name/Description

7—

6—4 RBITOFF

[2—0]

3—2 RFBOFF

[1—0]

Reserved. Receive Highway Bit Offset[2—0].

of an incoming frame by the indicated number of bit times. If no bit offsets are required, these bits should be set to 000. The following list shows the effect of setting these bits.

000 = no bit offset 001 = 1-bit offset 010 = 2-bit offset . . . 111 = 7-bit offset

Bit periods are relative to the highway data rate set for each highway.

Note:

RTSOFF, RBITOFF, and RFBOFF are used in conjunction to define the start of the incoming frame. The values are added together to position the sampling of time slot 0, bit 0 for each highway.

Receive Highway Fractional Bit Offset[1—0].

beginning of an incoming frame by the indicated number of fractional bit times. If no fractional bit offsets are required, these bits should be set to 00. The following list shows the effect of these bits.

(continued)

Read as 0.

RBITOFF is used to offset the beginning

RFBOFF is used to offset the

1—0 —

* i = the receive highway number.

00 = no fractional bit offset 01 = 1/4-bit fractional offset 10 = 1/2-bit fractional offset 11 = 3/4-bit fractional offset

Bit periods are relative to the highway data rate set for each highway.

Note:

RTSOFF, RBITOFF, and RFBOFF are used in conjunction to define the start of the incoming frame. The values are added together to position the sampling of time slot 0, bit 0 for each highway.

Reserved.

(Read/Write) Must be written to 00.

47Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Configuration Register Architecture

Table 39. Receive Highway Configuration Register (Byte 1) (0x1801 + 4i)

Bit Symbol Name/Description

7—

6—0 RTSOFF

[6—0]

* i = the receive highway number.

Table 40. Receive Highway Configuration Register (Byte 2) (0x1802 + 4i)

Reserved. Receive Highway Time-Slot Offset[6—0].

ning of an incoming frame by the indicated number of time slots (bytes). If no time-slot offsetting is required, these bits should be set to zero. The following table shows the range of offsets for the different highway data rates.

Highway Data Rate

2.048 Mbits/s 0—31

4.096 Mbits/s 0—63

8.192 Mbits/s 0—127 A time slot is always 8 bits. A bit period is relative to the highway data rate

Note:

set for each highway.

RTSOFF, RBITOFF, and RFBOFF are used in conjunction to define the start of the incoming frame. The values are added together to position the sampling of time slot 0, bit 0.

(continued)

Read as 0.

Time-Slot Offset Range

RTSOFF is used to offset the begin-

Bit Symbol Name/Description

7—3 —

2LC

1—0 HDR[1—0]

* i = the receive highway number.

Reserved. Loopback Control.

highway to the corresponding RXD highway. When set to 1, the TXD highway as input to this RXD highway. The transmit highway involved will be internally looped back to the matching receive highway so that the TXD[i] output is now the input to RXD[i]. When a particular highway is in this mode, the receive highway offset must be 1/2-bit greater than the corresponding transmit highway offset. When LC is cleared to 0, the RXD pin is the source of highway data (default).

Receive Highway Data Rate[1—0].

HDR1

All of the receive highways are grouped into pairs. RXD0 with RXD1, RXD2 with RXD3, . . . , and RXD14 with RXD15. The maximum combined bandwidth for each pair is 8.192 Mbits/s. Refer to Table 6, Rx Highway Data Rate Options, on page 18 for highway rate combination.

Read as 0.

This bit is used to control the internal loopback of the TXD

HDR0 0 0 2.048 Mbits/s (default) 0 1 4.096 Mbits/s 1 0 8.192 Mbits/s 1 1 0.000 Mbits/s (idle, not receiving data)

48 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Configuration Register Architecture

(continued)

Tr a nsmit Highway 3-State Options

There are several ways of 3-stating the transmit highways:

(active-low) is the input pin that 3-states all outputs and bidirectional pins of the device.

TEST GXE (bit 0) (active-high) is the global transmit enable bit in the general command register. It applies to all transmit

highways. XE (bit 2) (active-high) is the transmit highway 3-state enable bit in the transmit highway configuration register

(byte 2). There is a separate XE bit for each one of the 16 transmit highways. ED (bit 6) (active-high) is the external drivers bit in the general command register. This bit applies to all the transmit

highways. It affects the 3-stating of the transmit highways. Time slots that are selected to be 3-stated, by setting the TSDSM[2—0] bits to 0x7 in byte 2 of the connection store, will be driven with random data if ED = 1. Otherwise, these time slots will be 3-stated.

Table 41. Transmit Highway 3-State Options

TEST

(Input

Pin)

GXE

(Cfg

Bit)

(Cfg

Bit)

XE for

Transmit

Highway [i]

(Cfg Bit)

0XX X 100 X 101 X 110 0 110 1

111 0 111 1

according to connection store pro-

TXD[i] is driven with random data. TXOE[i] = 0.

TXD[i] = 0 or 1 reflecting the correct

transmit data. Time slots which are

selected for high-impedance mode

TXD[0—15] Pins TXOE[0—15] Pins

All high impedance. All high impedance. All high impedance. All 0.

All driven with random data. All 0.

TXD[i] = high impedance. TXOE[i] = 0.

TXD[i] = 0, 1, or high impedance

gramming.

via the connection store will be

driven with random data and not

3-stated.

TXOE[i] = 0 or 1, representing high-imped-

ance state according to connection store

programming.

TXOE[i] = 0 or 1, representing high-imped-

ance state according to connection store

programming.

49Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Data Store Memory

Microprocessor access to the incoming highway data is provided by directly reading the data store memory. Each one of the time slots is addressable by constructing the address in the following way address space will occur immediately. Microprocessor writes to this address space will not change the contents of the data store. If user data is to be sent out on a particular time slot, the host data substitution mode in the connection store should be used.

Table 42. Address Scheme for Data Store Memory

Microprocessor reads to this

Data Store

Memory Address

To illustrate the addressing scheme, consider the following examples: To read the data received in time slot 7 on RXD6, the following address is used to access the TSI data store mem-

ory location.

All TDM highway data which is stored in the TSI will have the following convention. The most significant bit

Note:

of a byte is first transmitted and first received, the least significant bit is last transmitted and last received. This convention applies to the data read from the data store, the host data transmitted via the connection store, and any other configuration register that stores highway data.

14131211109876543210

0100Receive Highway

Number (0—15)

A[14—0] = 010_00110_0000111 = 0x2307

Receive Time-Slot Address

(0—127)

Connection Store Memory

The connection store memory is primarily used to set up the switching matrix and selects the transmit data source for each one of the outgoing time slots. There are two connection store byte locations associated with each one of the outgoing time slots. The address for each of the corresponding connection store memory locations is constructed in the following way.

Table 43. Address Scheme for Connection Store Memory

Connection Store

Memory Address

If any particular transmit highway is not programmed to use the total available bandwidth (8.192 Mbits/s), then the connection store memory locations representing the unused time slots are not used. For example, assume highway 7 is set for a highway data rate of 4.096 Mbits/s. This translates to a total of 64 time slots being transmitted on highway 7. In that case, addresses A[14—0] = 0x4700—0x477F must be set. Addresses A[14—0] = 0x4780— 0x47FF are irrelevant for a 4.096 Mbits/s highway and need not be set.

The connection store memory does not have a default state. Therefore, after powerup, the relevant locations in the connection store must be programmed. However, the connection store contents are not affected by a software or hardware reset of the TTSI1K16T.

50 Lucent Technologies Inc.

1413121110987654321 0

1 0 0 Transmit Highway

Number (0—15)

Transmit Time-Slot Address

(0—127)

Byte 0, 1

Select

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Connection Store Memory

Table 44. Connection Store Memory (Byte 0)

Bit S ymbol Name/Description

7—0 RTSA[6—0]/

HSD[7—0]

Table 45. Connection Store Memory (Byte 1)

Bit Symbol Name/Description

7—5 TSDSM[2—0]

4—

3—0 RXHWY

[3—0]

(continued)

Receive Time-Slot Address[6—0]/Host Substituted Data[7—0].

latency or frame-integrity time-slot data select modes are selected for the particular transmit time slot being configured, then these bits are used to indicate the receive time-slot address from which the transmit time-slot data is sourced. Bit 7 should be set to 0.

If the host data substitution mode is selected for the particular transmit time slot being configured, then these 8 bits will represent the data byte to be transmitted.

These bits are not valid for time-slot data select modes 3—7.

Time-Slot Data Select Mode[2—0]

0 0 0 Low-latency mode. 0 0 1 Frame-integrity mode. 0 1 0 Host data substitution mode. 0 1 1 Idle code 1 substitution mode. 1 0 0 Idle code 2 substitution mode. 1 0 1 Idle code 3 substitution mode. 1 1 0 Test-pattern substitution mode—test pattern is

1 1 1 High-impedance mode.

Reserved. Receive Highway Number.

outgoing time-slot data is sourced. These bits are only valid for time-slot data select modes 0 and 1.

Must be written to 0.

If low-

selected via test-pattern style register.

Used to select the receive highway from which the

To illustrate the connection store programming scheme, consider the following example: To configure the transmission of time slot 7 on TXD6, the following addresses are used to access the relevant TSI

connection store memory locations.

A[14—0] = 10_00110_0000111_0 = 0x460E—to access byte 0 A[14—0] = 10_00110_0000111_1 = 0x460F—to access byte 1

Now, if it is desired to send Rx time slot 4 from RXD3 to time slot 7 on TXD6 in frame integrity mode, then the following data should be written to the above addresses.

Data byte 0 = 0_0000100 = 0x04 Data byte 1 = 001_00011 = 0x23

Thus, to map Rx time slot 4 from RXD3 to Tx time slot 7 on TXD6, in frame integrity mode, the following two TSI writes must be performed.

Write location 0x460E with 0x04 Write location 0x460F with 0x23

51Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Connection Store Memory

TSDSM[5—0] (bits 7—5) of byte 1 of the connection store select the source of data for each of the time slots being transmitted by the TTSI1K16T. The configuration can be divided into three groups.

Group 1 Low-Latency Mode.

the data store based on the programming of TSA[6—0] (bits 6—0) of byte 0 and RXHWY[4—0] (bits 4—0) of byte 1. Bit 7 of byte 0 is ignored. When each of the individual transmit time slots are retrieved from the data store memory for transmission, the most recent copy of the receive time slot will be fetched resulting in a latency that never exceeds 134 µs. This is the maximum latency for lowlatency mode independent of highway configurations (e.g., highway speed, clock speed, offsets, etc.). Refer to the Low-Latency and Frame-Integrity Modes section on page 23 for a detailed description of the latency calculation.

Frame-Integrity Mode.

from the data store based on the programming of TSA[6—0] (bits 6—0) of byte 0 and RXHWY[4—0] (bits 4—0) of byte 1. Bit 7 of byte 0 is ignored. Any number of time slots from any number of transmit highways can be marked for frame integrity. When each of the individual transmit time slots marked for frame integrity are retrieved from the data-store memory for transmission, the internal controller ensures that they are chosen from a receive frame which has already been entirely stored in the data store, thereby ensuring frame integrity.

Refer to the Low-Latency and Frame-Integrity Modes section on page 23 for a detailed description of the actual latency incurred through the device.

Group 2 Host-Data Substitution Mode.

repeatedly onto any or all of the 1024 transmit time slots; however, the data to be substituted is stored in HSD[7—0] (bits 7—0) of byte 0 for each transmit time slot. RXHWY[3—0] (bits 3—0) of byte 1 are ignored in this mode. Host-data mode can be used to customize the data for each of the 1024 transmit time slots. When a time slot is configured for host-data substitution mode, the data written to byte 0 of the connection store will have the following convention. Bit 7 is first transmitted, and bit 0 is last transmitted.

(continued)

For the time slots marked as low latency, the transmit data will be retrieved from

For the time slots marked as frame integrity, the transmit data will be retrieved

This mode also provides the means to transmit host-supplied data

Idle-Code Substitution Mode.

mit microprocessor data repeatedly onto any or all of the 1024 transmit time slots. Three idle-code registers (separate from the connection store memory) provide the capability to repeatedly broadcast three different programmed values to any or all time slots set for idle-code substitution mode. When programming idle- cod e sub sti tuti on m ode , onl y t he TS DSM [2—0 ] (b its 7 —5) of by te 1 for all of t he t ran smit ti me slots involved needs to be written. Byte 0 and RXHWY[3—0] (bits 3—0) of byte 1 are both ignored.

Test-Pattern Substitution Mode.

than use the receive time slots being stored in the data store. Since the test-pattern selection is done outside of the connection store, only TSDSM[2—0] (bits 7—5) of byte 1 for each of the time slots involved needs to be programmed. Byte 0 and RXHWY[3—0] (bits 3—0) of byte 1 are both ignored. The test-pattern selection and usage rules are described in the Test-Pattern Generation section on page 27.

Group 3 High-Impedance Mode.

ual basis. For example, consider the case where an 8.192 Mbits/s highway is shared by four devices, each having one-fourth of the total bandwidth. If the TTSI1K16T were allocated time slots 64—95, then high-impedance mode would be set for time slots 0—63 and 96—127. Time slots 64—95 could be set to any combination of the eight possible modes. When programming the high-impedance mode, only TSDSM[2—0] (bits 7—5) of byte 1 for all of the transmit time slots involved needs to be written. Connection store byte 0 and RXHWY[3—0] (bits 3—0) of byte 1 are both ignored.

These three idle-code substitution modes provide the means to trans-

This mode is also used to substitute alternative transmit data rather

This mode is used to 3-state any of the 1024 transmit time slots on an individ-

52 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. External leads can be safely soldered or bonded at temperatures up to 300 °C.

Parameter Symbol Min Max Unit

Storage Temperature T Voltage on Any Pin with Respect to Ground V Power Dissipation P

* This maximum rating only applies when the device is powered up with VDD.

stg

–65 125 °C

–0.5 5.8* V

— 400 mW

Operating Conditions

Parameter Symbol Min Max Unit

Power Supply V Low-level Input Voltage V High-level Input Voltage V Ambient Operating Temperature Range T

IL IH A

2.97 3.63 V —0.8V

2.1 5.8 V

–40 85 °C

Handling Precautions

Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely used and, therefore, can be used for comparison. The HBM ESD threshold presented here was obtained by using these circuit parameters:

Human-Body Model ESD Threshold

Device Voltage

TTSI1K16T >1000 V

53Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Electrical Characteristics

TA = –40 °C to +85 °C; VDD = 3.3 V ± 10%; VSS = 0 V

Parameter Symbol Test Conditions Min Typ Max Unit

Input Leakage Current:

Non-pull-up Pins Pull-up Pins Non-pull-up I/O Pins Pull-down Pins

Output Voltage:

Low:

, D[7—0] TXD[15—0], TXOE[15—0] TDO, INT

High:

, D[7—0] TXD[15—0], TXOE[15—0] TDO, INT

Load Capacitance:

, D[7—0], INT TXD[15—0] TXOE[15—0] TDO

VSS < VIN < VDD ± 10%

= VSS

< VIN < VDD ± 10%

= VDD ± 10%

IOL = –10 mA

= –6 mA

= –2 mA

= 10 mA

= 6 mA

= 2 mA

— — — —

— — —

2.4

— — — —

— — —

— — — —

10 60 70

300

0.4

0.4 —

— —

50 25 20 70

µA µA µA µA

V V V

pF pF pF pF

Timing Characteristics

TA = –40 °C to +85 °C; VDD = 3.3 V ± 10%; VSS = 0 V The following timing characteristics are generated for the TTL input and output levels.

Table 46. Clock Specifications

Pin Name Frequency Duty Cycle Clock Period

Stability

PCLK 0 MHz—65 MHz 50% ± 10% — — —

CK 2.048 MHz

4.096 MHz

8.192 MHz

16.384 MHz

50% ± 10% 50% ± 10% 50% ± 10% 50% ± 10%

±64 ns ±32 ns ±16 ns

±8 ns

TCK 10 MHz 50% ± 10% — — —

Rise Time

(max)

10 ns 10 ns 10 ns 10 ns

Fall Time

(max)

10 ns 10 ns 10 ns 10 ns

54 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Timing Characteristics

A[14—0]

R/W

HIGH IMPEDANCE

D[7—0]

Figure 16. Asynchronous Read Cycle Timing Using DT Handshake

A[14—0]

R/W

HIGH IMPEDANCE

(continued)

READ ADDRESS

READ DATA

5-7063(F)r.2

WRITE ADDRESS

D[7—0]

WRITE DATA

5-7064(F)r.2

Figure 17. Asynchronous Write Cycle Timing Using DT Handshake

Table 47. Asynchronous Read and Write Interface Timing Using DT

Handshake

Symbol Description Min Max Unit

t1 A[14—0] or R/W t2 A[14—0] or R/W t3 CS t4 DT t5 DT

Hold from AS or DS 4* — ns Output Delay from AS or DS (CL = 50 pF) 3* 8* ns or D[7—0] High-impedance from CS (CL = 50 pF) — 8.5* ns

t6 D[7—0] Input Setup to DS t7 D[7—0] Input Hold from DS t8 D[7—0] Output Setup Prior to DT

*CS asynchronously controls the output enable of D[7—0] and DT. The delay from CS to the output enable of DT is equivalent to the delay

from AS

or DS to DT. Therefore, in order to guarantee that DT is driven high before being 3-stat ed, a CS hold time is required (t3). If this timing cannot be met, then there are two options. One, disconnect DT be completed by the device 183 ns after the start of the cycle, which is defined by CS use an external pull-up on DT

Setup to AS 0—ns Hold from AS 0—ns

(CL = 50 pF) 0 — ns

Output (CL = 50 pF) 0 — ns

and rely on wait-states to terminate the cycle. The read or write cycle will

, AS, and DS all being active. The second option is to

to pull DT high within the timing requirements of the microprocessor.

55Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Timing Characteristics

A[14—0]

R/W

D[7—0]

Figure 18. Asynchronous Read Cycle Timing Using Only CS

A[14—0]

(continued)

t13

READ ADDRESS

t11

t10

t14

READ DATA

5-7065(F)r.3

WRITE ADDRESS

t11

R/W

D[7—0]

t12

WRITE DATA

t10

Figure 19. Asynchronous Write Cycle Timing Using Only CS

Ta ble 48. Asynchronous Microproces sor Interface Timing Using Only CS

Symbol Description Min Max Unit

t9 A[14—0], R/W t10 A[14—0] , R/W t11 Pulse Width of CS t12 Pulse Width of CS t13 D[7—0] Output Delay from CS t14 D[7—0] Output Hold from CS

, D[7—0] Input Setup to CS 0—ns , D[7—0] Input Hold from CS 0—ns

Inactive 100 — ns Active 200 — ns

(CL = 50 pF) — 200 ns

(CL = 50 pF) 0 — ns

5-7066(F)r.3

56 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Timing Characteristics

PCLK

t15

t17

R/W

t22

D[7—0]

A[14—0]

PCLK

t15

t17

R/W

D[7—0]

A[14—0]

(continued)

t15

t18

t22 t22

t19

READ ADDRESS

t24

Figure 20. Synchronous Read Cycle Timing

t15

t18

t22

t19

WRITE DATA

t20

WRITE ADDRESS

t22

t16

t21

HIGH IMPEDANCE

t23

t25

t21

t16

t21

t22

HIGH IMPEDANCE

t23

t21

5-7067(F)r.3

5-7068(F)r.2

Figure 21. Synchronous Write Cycle Timing

57Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Timing Characteristics

(continued)

Table 49. Synchronous Microprocessor Interface Timing

Symbol Description Min Ma x Unit

t15 CS t16 CS t17 AS t18 AS t19 R/W t20 D[7—0] Input Setup to Rising PCLK Edge 0 t21 R/W t22 DT t23 DT t24 D[7—0] Output Delay from Rising PCLK Edge (C t25 D[7—0] Output High Impedance from Rising PCLK Edge

* The CS setup timing requirement relative to PCLK can be programmed for either the first or second clock cycle of a microprocessor access

using CSV (bit 7) of the general command register.

† The input setup timing requirement assumes a PCLK frequency of at least 25 MHz. For frequencies slower than 25 MHz, the D[7—0] propa-

gation delay must be less than 40 ns from the rising edge of PCLK which samples AS

‡ When data is driven by the TSI during a synchronous read cycle, good data is driven prior to DT

Setup to Rising PCLK Edge 10* — ns Hold from Rising PCLK Edge 0 — ns Setup to Rising PCLK Edge 6 — ns Hold from Rising PCLK Edge 0 — ns

, A[14—0] Input Setup to Rising PCLK Edge 0 — ns

†

—ns

, A[14—0], D[7—0] Input Hold from Rising PCLK Edge 0 — ns Output Delay from Rising PCLK Edge (CL = 10 pF to 50 pF) 2.6 10 ns High Impedance from Falling PCLK Edge (CL = 50 pF) — 7 ns

= 50 pF) — 0

‡

412ns

= 10 pF to 50 pF)

being asserted.

58 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Timing Characteristics

(continued)

TDM highway timing is shown below for the following scenario (i = 0, 1, 2 . . . 15; j = 0, 1, 2 . . . 15):

■

The input CK speed is set to 8.192 MHz.

■

FSYNC is programmed to be active-high and sampled by a rising edge of CK.

■

The RXD[i] highway is set for 0-bit offset and a highway data rate of 4.096 Mbits/s.

■

The TXD[j] highway is set for 0-bit offset and a highway data rate of 8.192 Mbits/s.

FSYNC SAMPLED ACTIVE

FSYNC

t26 t27

(8.192 MHz)

(4.096 Mbits/s)

(8.192 Mbits/s)

RXD[i]

TXD[j]

TXOE[j]

t27t26

BIT 0

BIT 1 BIT 2 BIT 5 BIT 6 BIT 5

t29

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

t30

t28

t29

t30

5-7465(F)r.3

Figure 22. TDM Highway Timing

Table 50. TDM Highway Timing

Symbol Description Min Max Unit

t26 FSYNC, RXD[0—15] Setup to Active CK Edge 10 — ns t27 FSYNC, RXD[0—15] Hold from Active CK Edge 5 — ns

t28 TXD[0—15] Delay from Active CK Edge (C

t29 TXD[0—15] High Impedance (C

= 25 pF) — 15 ns

t30 TXOE[0—15] Delay from Active CK Edge (C

= 25 pF) 5 15 ns

= 20 pF) 5 15 ns

The TDM highway timing numbers, t26—t30, also apply for all other cases as well, i.e.,

■

CK speed is 2.048 MHz, 4.096 MHz, or 16.384 MHz.

■

FSYNC is sampled on the falling edge of CK.

■

FSYNC is active-low.

■

RXD[i] is sampled on the falling edge of CK.

■

RXD[i] data rate is 2.048 Mbits/s or 8.192 Mbits/s.

■

TXD[j] is driven on the falling edge of CK.

■

TXD[j] data rate is 2.048 Mbits/s or 4.096 Mbits/s.

■

TXOE[j] is driven on the falling edge of CK. TXOE[j] is driven on the same edge as TXD[j].

59Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Timing Characteristics

TCK

TMS

TDI

TDO

(continued)

t33

t31

t32

t34

HIGH IMPEDANCE

Figure 23. JTAG Interface Timing

Table 51. JTAG Interface Timing

Symbol Description Min Max Unit

t31 TDI, TMS Setup to Rising TCK Edge 10 — ns t32 TDI, TMS Hold from Rising TCK Edge — 10 ns

t33 TDO Delay from Falling TCK Edge (C t34 TDO High Impedance from Falling TCK Edge (C

= 70 pF) 5 35 ns

= 70 pF) — 35 ns

5-7070(F)r.2

60 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Outline Diagram

144-Pin TQFP

Dimensions are in millimeters.

22.00 ± 0.20

20.00 ± 0.20

PIN #1 IDENTIFIER ZONE

109144

108

20.00

0.20

22.00

0.20

37 72

DETAIL A DETAIL B

0.50 TYP

1.00 REF

0.25

GAGE PLANE

SEATING PLANE

0.45/0.75

0.05/0.15

0.19/0.27

1.40 ± 0.05

1.60 MAX

0.08

SEATING PLANE

0.08

0.106/0.200

5-3815(F)r.6

61Lucent Technologies Inc.

TTSI1K16T Preliminary Data Sheet 1024-Channel, 16-Highway Time-Slot Interchanger February 1999

Ordering Information

Device Code Package Temperature Comcode

(Ordering Number)

TTSI1K16T3TL 144-pin TQFP –40 °C to +85 °C 108269762

DS99-177PDH Replaces DS98-290TIC to Incorporate the Following Updates

1. Page 18, Highway Data Rate Selection section, added paragraph on meeting the 8.192 Mbits/s bandwidth requirement for a transmit highway pair at the bottom of the page.

2. Page 20, updated Figure 10, Virtual and Physical Frames on page 20.

3. Page 22, Reset Sequence section, added paragraph on BIST requirement.

4. Page 23—page 26, Low-Latency and Frame-Integrity Modes section updated.

5. Page 27, Test-Pattern Generation section updated.

6. Page 27 and page 28, Test-Pattern Checking section updated.

7. Page 36, Table 15, General Command Register (0x00), removed last sentence in description of bit 2 and bit 1.

8. Page 36, Table 15, General Command Register (0x00), updated bit 0 symbol from GXEN to GXE.

9. Page 37, Table 16, Software Reset Register (0x01), updated bit 0, software reset description.

10. Page 39, Table 22, Interrupt Status Register (0x07), updated bit 4 and bit 2 to reserved status.

11. Page 40, Table 23, Interrupt Mask Register (0x08), updated bit 4 and bit 2 to reserved status.

12. Page 40, Table 23, Interrupt Mask Register (0x08), bit 3 symbol changed from MASKED to MASKERD.

13. Page 42, Table 25, Test-Pattern Style Register (0x0A), updated test-pattern descriptions.

14. Page 43, Table 26, Test-Pattern Checker Highway Register (0x0B), updated bit 4 to reserved status.

15. Page 43, Table 27, Test-Pattern Checker Upper Time-Slot Register (0x0C), updated description.

16. Page 43, Table 28, Test-Pattern Checker Lower Time-Slot Register (0x0D), updated description.

17. Page 43, Table 30, Test-Pattern Error Injection Register (0x0F), changed register name from test-pattern error

selection register to test-pattern error injection register and added sentence to end of description.

18. Page 45, Table 35, Transmit Highway Configuration Register (Byte 0) (0x1000 + 4i), updated bit 3—bit 2 sym-

bol from XCEOFF to XFBOFF.

19. Page 46, Table 37, Transmit Highway Configuration Register (Byte 2) (0x1002 + 4i), updated bit 2 symbol name

from XEN to XE.

20. Page 47, T able 38, Receive Highway Configuration Register (Byte 0) (0x1800 + 4i), updated bit 3—bit 2 symbol

from RCEOFF to RFBOFF.

21. Page 49, Transmit Highway 3-State Options section and Table 41, Transmit Highway 3-State Options updated.

22. Page 50, Data Store Memory section updated.

23. Page 51, Table 44, Connection Store Memory (Byte 0), changed TSA symbol to RTSA and updated

description.

24. Page 51, Table 45, Connection Store Memory (Byte 1), changed PORTNUM[4—0] symbol to RXHWY[3—0].

25. Page 51, Table 45, Connection Store Memory (Byte 1), updated bit 4 to reserved status.

26. Page 50—page 52, Connection Store Memory section updated.

27. Page 54, Table 46, Clock Specifications, updated clock period stability for CK.

28. Page 59, Timing Characteristics section, updated Figure 22, TDM Highway Timing and text.

29. Page 59, Table 50, TDM Highway Timing, timing parameter t26, minimum changed from 15 ns to 10 ns.

62 Lucent Technologies Inc.

Preliminary Data Sheet TTSI1K16T February 1999 1024-Channel, 16-Highway Time-Slot Interchanger

Notes

63Lucent Technologies Inc.

TTSI2K32T Preliminary Data Sheet

)

(65)

(81)

(

)

2048-Channel, 32-Highway Time-Slot Interchanger February 1999

For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technolo

ASIA PACIFIC:Microe le ctron ics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 CHINA: Microelectroni cs Gr oup, Luce nt Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE:

Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.

http://www.lucent.com/micro docmaster@micro.lucent.com

1-800-372-2447 Tel. (65) 778 8833

200233 P. R. China

Tel. (81) 3 5421 1600

Technical Inquiries: GERMANY:

, FAX 610-712-4106 (In CANADA:

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February 1999 DS99-177PDH (Replaces DS98-290TIC and AY98-029TIC)

Helsinki),

Datasheet TTSI1K16T3TL Datasheet (Lucent Technologies)

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Applications

Description

Functional Description

Table 1. Data Rate and Switch Size Examples

Figure 1. Block Diagram of the TTSI1K16T

Pin Information

Figure 2. 144-Pin TQFP Pin Assignment (Top View)

Table 2. Pin Assignments for a 144-Pin TQFP—Pin Number Order

Table 3. Pin Assignments for a 144-Pin TQFP—Signal Name Order

Table 4. TTSI1K16T Pin Descriptions

Typical TSI Application

Figure 3. A Typical TSI Application

Interchange Fabric

Small and Large TSIs

Table 5. The TSI Family

Figure 4. An 8K Time-Slot Switch Made from 4K TSIs

Microprocessor Interface

Asynchronous Mode (MM = 0)

Figure 5. Asynchronous Read

Figure 6. Asynchronous Write

Synchronous Mode (MM = 1)

Figure 7. Synchronous Read

Figure 8. Synchronous Write

Highway Data Rate Selection

Table 6. Rx Highway Data Rate Options

Table 7. Tx Highway Data Rate Options

Mixed-Highway Data Rates

Figure 9. Mixed-Highway Data Rates

TDM Highway Interface Timing

Virtual and Physical Frames

Figure 10. Virtual and Physical Frames

TDM Highway Alignment at Zero Offset

Figure 11. Synchronization to FSYNC

TDM Highway Offsets

Figure 12. Highway Offsets

Reset Sequence

Low-Latency and Frame-Integrity Modes

Low Latency

Frame Integrity

Table 10. Offset Difference Boundaries

Figure 13. Mixed Low-Latency and Frame-Integrity Modes

Test-Pattern Generati on

Test-Pattern Checking

Error Injection

Error Checking

JTAG Boundary-Scan Specification

Principle of t he Boundary Scan

Figure 14. Block Diagram of the TTSI1K16T's Boundary-Scan Test Logic

Test Access Port Controller

Figure 15. BS TAP Controller State Diagram

Table 11. TAP Controller States in the Data Register Branch

Table 12. TAP Controller States in the Instruction Register Branch

Instruction Register

Table 13. TTSI1K16T’s Boundary-Scan Instructions

Boundary-Scan Register

BYPASS Register

IDCODE Register

3-State Procedures

Register Architecture

Table 14. TTSI1K16T Register Summary

Configuration Register Architecture

Table 15. General Command Register (0x00)

Table 16. Software Reset Register (0x01)

Table 17. BIST Command Register (0x02)

Table 18. Idle Code 1 Register (0x03)

Table 19. Idle Code 2 Register (0x04)

Table 20. Idle Code 3 Register (0x05)

Table 21. Global Interrupt Mask Register (0x06)

Table 22. Interrupt Status Register* (0x07)

Table 23. Interrupt Mask Register (0x08)

Table 24. Test Command Register (0x09)

Table 25. Test-Pattern Style Register (0x0A)

Table 26. Test-Pattern Checker Highway Register (0x0B)

Table 27. Test-Pattern Checker Upper Time-Slot Register (0x0C)

Table 28. Test-Pattern Checker Lower Time-Slot Register (0x0D)