Datasheet TTRN012G73XE1, TTRN012G7, TTRN012G53XE1, TTRN012G5 Datasheet (Lucent Technologies)
Preliminary Data Sheet
August 2000
TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s)
Clock Synthesizer, 16:1 Data Multiplexer
Features
■
TTRN012G5 supports OC-48/STM-16 data rate
■
TTRN012G7 supports:
— OC-48/STM-16 data rate
— RS (255, 239) forward error correction (FEC)
OC-48/STM-16 data rate
■
Fully integrated clock synthesizer and 16:1 data
multiplexer
■
Supports clockless data transfer into the 16:1
multiplexer
■
Parity checking and valid data indication
■
Data inversion option
■
Additional high-speed CML serial data output for
system loopback
■
Loss of lock indication
■
Single 3.3 V supply
■
Available in either MBIC 025 BiCMOS technology
or lower-power MBIC 025 silicon germanium
BiCMOS technology
■
LVPECL 155.52 Mbits/s digital I/O
■
Jitter generation and jitter transfer compliant with
the following:
—
Telcordia Technologies
* GR-253
— ITU-T G.825
— ITU-T G.958
Applications
■
SONET/SDH line origination equipment
■
SONET/SDH add/drop multiplexers
Description
The Lucent Technologies Microelectronics Group
TTRN012G5 operates at the OC-48/STM-16 data
rate of 2.5 Gbits/s. The TTRN012G7 device operates
at either 2.5 Gbits/s or the RS FEC OC-48/STM-16
data rate of 2.7 Gbits/s. For clarity, this data sheet
refers to the TTRN012G5 serial data rate as
2.5 Gbits/s and the parallel data and reference clock
frequency as 155 MHz. (The precise rates are
2.48832 Gbits/s and 155.52 MHz.) When using the
TTRN012G7 at the FEC rate, the 2.5 Gbits/s data
rate should be interpreted as 2.7 Gbits/s and the parallel and clock frequency should be interpreted as
166 MHz. (The precise rates are 2.66606 Gbits/s and
166.62 MHz.)
The devices provide a 16:1 multiplexer and clock
multiplier unit. Both a high-speed serial clock and
data output are generated. The devices accept 16
differential PECL data inputs and a low-speed reference clock. A unique feature of the multiplexer is that
no clock is required to feed in the 16 data lines, as
long as the upstream data chip clock is synchronous
with the device REFCLKP/N input.
Alternatively, contra-clocking may be used, whereby
the device provides one of four phases of a
155.52 MHz or 166.62 MHz clock output back
upstream to the data chip.
Other features include a parity bit input and parity
check on the 16 input data lines, a second
2.5 Gbits/s or 2.7 Gbits/s data output for loopback
toward the TRCV012G5 or TRCV012G7 device, and
a user-configurable PLL bandwidth. Both devices are
available in either BiCMOS or in SiGe BiCMOS technology for lower power operation.
■
SONET/SDH cross connects
■
SONET/SDH test equipment
■
Digital video transmission
*
Telcordia Technologies
munications Research, Inc.
is a registered trademark of Bell Com-
TTRN012G5 and TTRN012G7 Preliminary Data Sheet
Clock Synthesizer, 16:1 Data Multiplexer August 2000
Table of Contents
Contents Page
Features ....................................................................................................................................................................1
Applications ...............................................................................................................................................................1
Description.................................................................................................................................................................1
Pin Information ..........................................................................................................................................................4
Functional Overview..................................................................................................................................................9
Clock Synthesizer Operation ..................................................................................................................................9
Multiplexer Operation....... ...... ....... ...... ....... ...... ....... ...... ............................................. ....... .. .... ....... ...... ....... ...... ....11
Clocking Modes and Timing Adjustments ...............................................................................................................12
Clockless Transfer Mode (CLKMODE, EXTADJN, MONAPAP/N).......................................................................12
Contra-Directional Clocking Mode (CLKMODE, PHADJ[1:0])..............................................................................13
CML Output Structure (Used on Pins D2G5P/N, CK2G5P/N).................................................................................14
Choosing the Value of the External CML Reference Resistors (RREF1, RREF2) ...............................................14
Absolute Maximum Ratings.....................................................................................................................................15
Handling Precautions ............... ....... ...... ....... ...... ....... ...... ....... ............................................. ...... ....... ...... .................15
Operating Conditions................ ....... ...... ....... ...... ............................................. ....... ...... ....................................... ....15
Electrical Characteristics .........................................................................................................................................16
Reference Frequency (REFCLKP/N) Specifications.............................................................................................16
LVPECL, CMOS, CML Input and Output Pins......................................................................................................17
Timing Characteristics.............................................................................................................................................19
Transmit Timing ....................................................................................................................................................19
Outline Diagram.......................................................................................................................................................21
128-Pin QFP .........................................................................................................................................................21
Ordering Information................................................................................................................................................22
DS00-375HSPL Replaces DS00-155HSPL to Incorporate the Following Updates.................................................22
2 Lucent Technologies Inc.
Preliminary Data Sheet TTRN012G5 and TTRN012G7
August 2000 Clock Synthesizer, 16:1 Data Multiplexer
Description
RESETN TO DIGITAL LOGIC
D0P
D0N
D1P
D1N
D15P
D15N
PARITYP
PARITYN
CLKMODE
MONAPAP
MONAPAN
CK155P
CK155N
(continued)
PARITY
CHECK
0
1
1
0
MANUAL
PHASE
ADJUST
AUTO
PHASE
ADJUST
LOAD
01
INVDAT
DATA
RETIME
16:1 MULTIPLEXER
PARITY
REGISTER
DIVIDE
BY 16
INVDATN
ENLBDN
LBDP
LBDN
D2G5P
D2G5N
ENCK2G5
CK2G5P
CK2G5N
VALIDP
VALIDN
RREF2
RREF1
PHADJ[1:0]
EXTADJN
REFCLKP
REFCLKN
LCKLOSSN
Note: Diagram is representative of device functionality and conceptual signal flow. I nternal implementation details may be different than shown.
ACQUISITION
INDICATOR
PHASE/
FREQ.
DETECTOR
CHARGE
PUMP
LFP LFN
VCO
VCPVCN
0
TEST
1
TESTN
TSTCKP
TSTCKN
5-8060(F)r.3
Figure 1. Functional Block Diagram
3Lucent Technologies Inc.
TTRN012G5 and TTRN012G7 Preliminary Data Sheet
Clock Synthesizer, 16:1 Data Multiplexer August 2000
Pin Information
GND
V
CCD
V
CCD
GND
V
CCD
TSTCKP
V
CCD
TSTCKN
V
CCD
TESTN
INVDATN
V
CCD
GND
D2G5P
D2G5N
GND
CK2G5P
CK2G5N
GND
V
CCD
ENCK2G5
RREF2
RREF1
V
CCD
GND
LBDN
LBDP
GND
V
CCD
ENLBDN
GND
GND
LCKLOSSN
V
CCD
V
CCD
NC
GND
GND
REFCLKN
106
REFCLKP
105
CCD
V
104
63
GND
103
64
102
101
100
GND
GND
GND
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
D15P
D15N
D14P
D14N
GND
D13P
D13N
D12P
D12N
V
CCD
D11P
D11N
D10P
D10N
GND
D9P
D9N
D8P
D8N
V
CCD
D7P
D7N
D6P
D6N
GND
D5P
D5N
D4P
D4N
V
CCD
D3P
D3N
D2P
D2N
GND
CCA
CCA
V
GND
V
128
127
1
126
NC
125
GND
124
GND
123
GND
122
GND
121
GND
120
GND
119
GND
118
GND
117
NC
116
NC
115
CCA
V
114
VCP
113
LFP
112
LFN
111
VCN
110
CCA
V
109
V
108
107
CCAVCCD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
394140
42
4345445446
474948
50
515352
55
565857
59
606261
PHADJ1
PHADJ0
NC
GND
RESETN
EXTADJN
CLKMODE
MONAPAN
CCD
V
MONAPAP
CCD
V
VALIDP
VALIDN
CK155N
CK155P
CCD
V
D0P
D0N
PARITYN
GND
PARITYP
GND
CCD
D1P
D1N
V
GND
5-8066(F)r.3
Figure 2. Pin Diagram of 128-Pin QFP (Top View)
4 Lucent Technologies Inc.
Preliminary Data Sheet TTRN012G5 and TTRN012G7
August 2000 Clock Synthesizer, 16:1 Data Multiplexer
Pin Information
(continued)
Table 1. Pin Descriptions—2.5 Gbits/s and Related Signals
In Table 1, when operating the TTRN012G7 device at the OC-48/STM-16 rate, 2.5 Gbits/s should be inter-
Note:
preted as 2.48832 Gbits/s. When operating the TTRN012G7 device at the RS FEC OC-48/STM-16 rate,
2.5 Gbits/s should be interpreted as 2.66606 Gbits/s. (A similar interpretation should be made for 2.5 GHz.)
Type
†
Level Name/Description
Data Output (2.5 Gbits/s NRZ).
output.
Loopback Data Output.
Additional 2.5 Gbits/s differential data
output for system loopback.
Clock Output (2.5 GHz).
2.5 GHz differential clock output.
2.5 Gbits/s differential data
Pin Symbol
*
14 D2G5P O CML
15 D2G5N
27 LBDP O CML
26 LBDN
17 CK2G5P O CML
18 CK2G5N
23 RREF1 I Analog
Resistor Reference 1.
CML current bias reference resistor.
(See Table 15, page 18 for values.)
22 RREF2 I Analog
21 ENCK2G5 I
u
CMOS
Resistor Reference 2.
1.5 kΩ resistor to V
Enable CK2G5P/N Clock Output.
CML bias reference resistor. Connect a
CCD
.
0 = CK2G5P/N buffer powered off
1 or no connection = CK2G5P/N buffer enabled
u
30 ENLBDN I
CMOS
Enable LBDP/N Data Output (Active-Low).
0 = LBDP/N buffer enabled
1 or no connection = LBDP/N buffer powered off
u
11 INVDATN I
CMOS
Invert D2G5P/N Data Output (Active-Low).
0 = invert
1 or no connection = noninvert
* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
† I = input, O = output. I
u
indicates an internal pull-up resistor on this pin.
5Lucent Technologies Inc.
TTRN012G5 and TTRN012G7 Preliminary Data Sheet
Clock Synthesizer, 16:1 Data Multiplexer August 2000
Pin Information
(continued)
Table 2. Pin Descriptions—155.52 Mbits/s and Related Signals
In Table 2, when operating the TTRN012G7 device at the OC-48/STM-16 rate, 155 Mbits/s should be inter-
Note:
preted as 155.52 Mbits/s. When operating the TTRN012G7 device at the RS FEC OC-48/STM-16 rate,
155 Mbits/s should be interpreted as 166.62 Mbits/s. (A similar interpretation should be made for 155 MHz.)
Type
†
Level Name/Description
Data Input (155 Mbits/s).
155 Mbits/s differential data input.
D15 is the most significant bit and is transmitted first on the
D2G5P/N output.
Pin Symbol
*
99 D15P I LVPECL
98 D15N
97 D14P LVPECL
96 D14N
94 D13P LVPECL
93 D13N
92 D12P LVPECL
91 D12N
89 D11P LVPECL
88 D11N
87 D10P LVPECL
86 D10N
84 D9P LVPECL
83 D9N
82 D8P LVPECL
81 D8N
79 D7P LVPECL
78 D7N
77 D6P LVPECL
76 D6N
74 D5P LVPECL
73 D5N
72 D4P LVPECL
71 D4N
69 D3P LVPECL
68 D3N
67 D2P LVPECL
66 D2N
62 D1P LVPECL
61 D1N
60 D0P LVPECL
59 D0N
* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
† I = input, O = output. I
u
indicates an internal pull-up resistor on this pin.
6 Lucent Technologies Inc.
Preliminary Data Sheet TTRN012G5 and TTRN012G7
August 2000 Clock Synthesizer, 16:1 Data Multiplexer
Pin Information
(continued)
Table 2. Pin Descriptions—155.52 Mbits/s and Related Signals
Type
†
Level Name/Description
Clock Output (155 MHz).
Pin Symbol
*
53 CK155P O LVPECL
52 CK155N
43
44
PHADJ1
PHADJ0
42 CLKMODE I
u
I
CMOS
u
CMOS
Phase Adjust.
Clock Mode Select.
Adjusts phase of CK155P/N in 90 degree steps.
0 = clockless transfer
1 or no connection = contra clock
57 PARITYP I LVPECL
Parity Input over Data (D[15:0]).
56 PARITYN
50 VALIDP O LVPECL
49 VALIDN
Parity Check Output.
0 = parity check does not agree with input PARITYP/N pins
1 = parity check agrees
33 LCKLOSSN O CMOS
41 EXTADJN I
u
CMOS
Loss of Lock (Active-Low).
External Automatic Phase Adjust (Active-Low).
155 MHz clock output, CK155P/N.
0 = adjust phase of 155 MHz clock to data upon next transition
of the D0P/N input signal
1 = no adjust
Must be held low until the first rising transition of D0P/N.
47 MONAPAP O LVPECL
46 MONAPAN
105 REFCLKP I LVPECL
106 REFCLKN
Monitor Automatic Phase Adjust.
adjustment in the automatic phase adjust block occurs.
Reference Clock Input (155 MHz).
When applying the REFCLKP/N, set the REFCLKP/N to one of
the following frequencies:
■
155.52 MHz if using the TRCV012G5, or the TRCV012G7 at
the 0C-48/STM-16 rate of 2.48832 GHz.
(continued)
155 MHz differential clock output.
Selects clockless data transfer mode.
Validates the input of PARITYP/N.
0 = PLL out of lock.
Adjusts the
Indicates when a phase
This clock is required.
■
166.62 MHz if using the TRCV012G7 at the RS FEC
0C-48/STM-16 rate of 2.66606 GHz.
112 LFP I Analog
Loop Filter PLL.
Connect LFP to VCP, and LFN to VCN.
111 LFN
113 VCP I Analog
VCO Control.
Connect VCP to LFP, and VCN to LFN.
110 VCN
* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
† I = input, O = output. I
u
indicates an internal pull-up resistor on this pin.
7Lucent Technologies Inc.
TTRN012G5 and TTRN012G7 Preliminary Data Sheet
Clock Synthesizer, 16:1 Data Multiplexer August 2000
Pin Information
(continued)
Table 3. Pin Descriptions—Reset and Test Signals
Type
u
†
Level Name/Description
CMOS
Reset (Active-Low).
Resets all synchronous logic. During a
Pin Symbol
*
40 RESETN I
reset, the true data outputs are in the low state and the barred
data outputs are in the high state.
0 = reset
1 or no connection = normal operation
6 TSTCK P I CML
Test Clock Input.
Buffer is powered down when TESTN = 1.
8TSTCKN
10 TESTN I
u
CMOS
Test Clock Select (Active-Low).
0 = select test clock
1 or no connection = select internal VCO
* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
† I = input, O = output. I
u
indicates an internal pull-up resistor on this pin.
Table 4. Pin Descriptions—Power and No-Connect Signals
Note:
V
CCA
and V
CCD
have the same dc value, which is represented as VCC unless otherwise specified. However,
high-frequency filtering is suggested between the individual supplies.
Pin Symbol
108, 109, 114,
V
*
CCA
†
Type
Level Name/Description
IPower
Analog Power Supply (3.3 V).
126, 127
2, 3, 5, 7, 9,
V
IPower
Digital Power Supply (3.3 V).
CCD
12, 20, 24, 29,
34, 35, 48, 51,
54, 63, 70, 80,
90, 104, 107
1, 4, 13, 16,
GND I Ground
Ground.
19, 25, 28, 31,
32, 37—39,
55, 58, 64, 65,
75, 85, 95,
100—103,
117—124, 128
36, 45, 115,
116, 125
NC — —
No Connection.
Pin 45 has an internal pull-up resistance
of approximately 25 kΩ. All of these pins must be left open.
* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
† I = input, O = output. I
u
indicates an internal pull-up resistor on this pin.
8 Lucent Technologies Inc.
Preliminary Data Sheet TTRN012G5 and TTRN012G7
August 2000 Clock Synthesizer, 16:1 Data Multiplexer
Functional Overview
The Lucent Technologies Microelectronics Group TTRN012G5 operates at the OC-48/STM-16 data rate of
2.5 Gbits/s.* The TTRN012G7 device operates at either 2.5 Gbits/s or the RS FEC OC-48/STM-16 data rate of
2.7 Gbits/s. The device performs the clock synthesis and 16:1 data multiplexing operations required to support
2.5 Gbits/s applications compliant with
clocked into an input register and checked for valid parity . Both clockless data transfer and contra-directional clocking modes are supported. The data is then multiplexed into a 2.5 Gbits/s serial stream and output buffered for interfacing to a laser driver. A 2.5 GHz clock is synthesized from a reference clock and is used to retime the serial data.
The 2.5 GHz clock is optionally available as an output. The serial data stream polarity can be inverted under pin
control to make interfacing easier.
Clock Synthesizer Operation
The clock synthesizer uses a PLL to synthesize a 2.5 GHz clock from a reference frequency. A 155 MHz clock
derived from the 2.5 GHz synthesized clock may be used to clock in the parallel data.
Clock Synthesizer Loop Filter
A typical loop filter that provides adequate damping for less than 0.1 dB of jitter peaking is shown in Figure 3. Connect the filter components and also connect LFP to VCP and connect LFN to VCN. The component values can be
varied to adjust the loop dynamic response (see Table 5).
Telcordia Technologies
and ITU standards. Parallel 155 Mbits/s data is
Table 5. Clock Synthesizer Loop Filter Component Values
Components Values for 2 MHz Loop Bandwidth
C1* 0.10 µF ± 10%
C2, C3 10 pF ± 20%
R1 680 Ω ± 5%
* Capacitor C1 should be either ceramic or nonpolar.
LFN/VCNLFP/VCP
1
C1R
2
C
3
C
5-8061(F)
Figure 3. Clock Synthesizer Loop Filter Components
Clock Synthesizer Settling Time
The clock synthesizer will acquire phase/frequency lock after a valid reference clock is applied to the REFCLKP/N
input pins. The actual time to acquire lock is a function of the loop bandwidth selected. The loop will acquire lock
within 5 ms when using the external loop bandwidth components corresponding to 2 MHz.
Loss of Lock Indicator (LCKLOSSN)
The LCKLOSSN pin indicates (active-low) when the clock synthesizer has exceeded phase-lock limits with the
incoming REFCLKP/N phase. The lock detect function compares the phases of the input 155 MHz clock at the
REFCLKP/N pins with the internally generated 155 MHz output clock at the CK155P/N pins. When the phase difference in the two signals is close to zero as determined by a second internal phase detector and filter, the lock
detect signal LCKLOSSN is set to the logic high state. When the phase difference between the two signals is
changing with time at a rate exceeding the filter's cutoff frequency, the device is declared out of lock and lock
detect signal LCKLOSSN is set to a logic low. If a set of highly damped phase-locked loop parameters is chosen
for the device, LCKLOSSN may exhibit more than one positive edge transition during the acquisition process
before a steady logic high state is achieved.
* The OC-48/STM-16 data rate of 2.48832 Gbits/s is typically approximated as 2.5 Gbits/s in this document when referring to the application
rate. The RS FEC OC-48/STM-16 data rate is 2.66606 Gbits/s and is approximated as 2.7 Gbits/s in this document. Similarly, the OC-3/
STM-1 data rate of 155.52 Mbits/s is typically approximated as 155 Mbits/s, and the RS FEC OC-3/STM-1 data rate of 166.62 Mbits/s is
approximated as 166 Mbits/s. The exact frequencies are used only when necessary for clarity.
9Lucent Technologies Inc.
TTRN012G5 and TTRN012G7 Preliminary Data Sheet
Clock Synthesizer, 16:1 Data Multiplexer August 2000
Functional Overview
Clock Synthesizer Operation
(continued)
(continued)
Clock Synthesizer Generated Jitter
The clock synthesizer’s generated jitter performance meets the requirements shown in Table 6. These specifications apply to the jitter generated at the 2.5 GHz clock pins (CK2G5P/N) when the jitter on the reference clock
(REFCLKP/N) is within the specifications given in T able 9 on page 16, and the loop filter components are chosen to
provide a loop bandwidth of 2 MHz.
Table 6. Clock Synthesizer Generated Jitter Specifications
Parameter T ypical Max
Generated Jitter (p-p):
(Device)
0.02 0.09 UIp-p
Unit
*
Measured with 12 kHz to 20 MHz Bandpass
Filter
Generated Jitter (rms):
0.002 0.009 UIrms
Measured with 12 kHz to 20 MHz Bandpass
Filter
* This denotes the device specification for system SONET/SDH compliance when the loop filter in
Table 5 and Figure3 is used.
Clock Synthesizer Jitter Transfer
The clock synthesizer’s jitter transfer performance meets the requirement shown in Figure 4 when the loop filter
values shown in Table 5 are used.
0
10
20
30
40
JITTER OUT/JITTER IN (dB)
50
60
(2 MHz, 0.1 dB)
1k 10k 100k 1M 10M
FREQUENCY (Hz)
100M
5-8062(F)r.1
Figure 4. Clock Synthesizer Jitter Transfer
10 Lucent Technologies Inc.
Preliminary Data Sheet TTRN012G5 and TTRN012G7
August 2000 Clock Synthesizer, 16:1 Data Multiplexer
Functional Overview
(continued)
Multiplexer Operation
The parallel 155 Mbits/s data is clocked into an input buffer by a 155 MHz clock derived from the synthesized
2.5 GHz clock. The data is checked for parity and then clocked into a 16:1 multiplexer. The relationship between
the parallel D[15:0] input data and the serial output data (D2G5P/N) is given in Figure 5. The D15 bit is the most
significant bit (MSB) and is shifted out first in time in the serial output stream.
D15
(MSB) (LSB)
(D15 SERIALLY SHIFTED OUT FIRST) (D0 SERIALLY SHIFTED OUT LAST)
D14 D1
TIME
Figure 5. Parallel Input to Serial Output Data Relationship
High-Speed Serial Clock Output Enable (ENCK2G5)
A separate output enable is provided for the 2.5 GHz clock output (CK2G5P/N). The enable is an active-high
CMOS input with an internal pull-up resistor. The default condition will enable the CK2G5P/N output, and applying
a ground or setting the enable pin (ENCK2G5) to logic low will disable the CK2G5P/N output. When disabled, the
CK2G5P/N output pins should be either left floating, or be connected to a load which returns to V
must not be connected directly to ground when it is disabled.
D0
D15
CC
. The output
5-8063(F)
Loopback 2.5 GHz Data Output (LBDP/N, ENLBDN)
An alternate 2.5 Gbits/s CML data output is available on the LBDP/N pin. This pin is provided for use in system
loopback testing and avoids the need for off-chip signal splitting of the data signal path. The alternate
2.5 Gbits/s loopback data output may be enabled by setting the ENLBDN pin to logic low. ENLBDN enable is an
active-low CMOS input with an internal pull-up resistor so the default condition will disable the LBDP/N output, and
a ground or logic-low signal must be applied to enable the loopback output. When disabled, the LBDP/N pin should
be either left floating, or be connected to a load which returns to V
CC
. The output must not be connected directly to
ground when it is disabled.
Parity Validation (VALIDP/N)
The parity signal is expected to be a logic 0 when the number of 1s in the 16-bit input register is an even number,
and the parity signal is expected to be a logic 1 when the number of 1s in the input register is an odd number. If the
parity bit agrees with the parity in the input register, then the VALIDP/N signal will be logic high. If the parity signal
is not generated, the VALIDP/N pin should be left open without termination to avoid meaningless signal swings and
avoid unnecessary power dissipation.
11Lucent Technologies Inc.
TTRN012G5 and TTRN012G7 Preliminary Data Sheet
Clock Synthesizer, 16:1 Data Multiplexer August 2000
Clocking Modes and Timing Adjustments
Clockless Transfer Mode
(CLKMODE, EXTADJN, MONAP AP/N)
The device supports two timing modes for the 155 Mbits/s data input. In clockless transfer mode (CLKMODE = 0),
data may be sent to the device without a clock. After phase/frequency lock has been obtained by the clock
synthesizer, the device automatically finds the correct phase of the internal 155 MHz clock by sampling the rising
edge of the D0P/N data bit. The skew of any data bit D[15:0]P/N must be less than 500 ps relative to D0P/N. If the
phase of the incoming data shifts more than ±2400 ps from the time the automatic phase adjustment occurred, the
device will automatically readjust its internal clocking phase. Data integrity may not be obtained at the instant of
phase adjustment, and an error burst of up to 16 data bits may occur.
The user may optionally force the automatic phase adjustment to occur by toggling the EXTADJN pin (active-low)
and keeping it low for at least 12.8 ns after the next rising edge of the D0P/N input. The phase will be adjusted one
time upon the first occurrence of a low-to-high transition of the D0P/N data bit while the EXTADJN pin is in the
logic-low state. To externally adjust the phase again, the RESETN pin must be brought low then high to enable
another phase adjustment. When CLKMODE = 0, the 155 MHz output clock (CK155P/N) is active but should be
left unconnected to conserve power.
MONAPAP/N can be used for the monitoring and reporting of phase adjustments. The MONAPAP/N output will go
high in the following sequence:
■
EXTADJN pin transitions to logic-low state
■
A rising edge of the D0P/N input occurs
■
MONAPAP/N transitions to logic 1 three CK2G5 cycles (1.2 ns) later
■
MONAPAP/N will stay high for 12 CK2G5 cycles (4.8 ns)
The first sixteen D2G5 data output bits after the rising edge of MONAPAP/N are invalid.
12 Lucent Technologies Inc.
Preliminary Data Sheet TTRN012G5 and TTRN012G7
August 2000 Clock Synthesizer, 16:1 Data Multiplexer
Clocking Modes and Timing Adjustments
Contra-Directional Clocking Mode
(CLKMODE, PHADJ[1:0])
(continued)
In the contra-directional clocking mode (CLKMODE = 1), the data is sampled with the internal 2.5 GHz clock at the
time of the falling edge of CK155P (see Figure 8 on page 19 for timing details). The device sends a 155 MHz clock
with one of four user-selectable phases out to the upstream device for clocking the data toward the device. The
user can program PHADJ[1:0] to adjust the phase of CK155 as a function of PWB layout and upstream device
propagation delay in order to meet the setup and hold time of the 155 Mbits/s data to the device. With a
PHADJ[1:0] = [11], the data is sampled by the internal CK2G5 clock at the falling edge of CK155P. PHADJ[1:0]
changes the phase of the CK155P clock without changing the input data sampling time. PHADJ[1:0] setting information is given in Table 7, and the phase relationship of CK155 for each PHADJ[1:0] setting is shown in Figure 6.
Table 7. PHADJ Settings for CK155 Output Clock (Contra-Clocking Mode)
Input Pins Phase
PHADJ1 PHADJ0
1 1 (See part A of Figure 6.)
1 0 (See part B of Figure 6.)
0 1 (See part C of Figure 6.)
0 0 (See part D of Figure 6.)
A. (0 DEG.)
B. (–90 DEG.)
C. (–180 DEG.)
D. (–270 DEG.)
Figure 6. CK155 Phase Relation vs. PHADJ Setting
TIME
5-8064(F)r.2
13Lucent Technologies Inc.
TTRN012G5 and TTRN012G7 Preliminary Data Sheet
Clock Synthesizer, 16:1 Data Multiplexer August 2000
CML Output Structure (Used on Pins D2G5P/N, CK2G5P/N)
The CML architecture is essentially a current-steering mechanism combined with an amplifier. This makes the output swing of the signal a function of the termination resistor and the programmable output current. The user should
connect external termination resistors from the CML output pins to V
vide a dc path when using an ac-coupled load.
The voltage swing of a CML signal is typically 400 mV, half that of ECL/PECL. The lower pulse amplitude reduces
noise transients, crosstalk, and EMI. It also uses half the amount of current through the termination resistors. The
schematic of a typical CML output structure is shown in Figure 7.
CC
. The on-chip, 100 Ω pull-up resistors pro-
DEVICE-INTERNAL CML OUTPUT BUFFER CIRCUIT
CC
V
100
Ω
CC
V
RREF1
VREF
RREF2
+
18X
–
CC
V
100
Ω
OUT
I
EXTERNAL OUTPUT TERMINATION
OUT
I
50
CC
V
Ω
CC
V
50
Ω
5-8065(F)r.2
Figure 7. T ypical CML Output Structure
Choosing the Value of the External CML Reference Resistors (RREF1, RREF2)
The flexibility of the CML interface permits certain parameters to be customized for a particular application. The
RREF1 resistor controls the CML output driver current source. Adjusting this tail
will allow signal amplitude control (see the CML output specifications for limitations, page 18 and page 20) and
flexibility in termination schemes.
With RREF2 set to 1.5 kΩ, the equation for the CML output current is the following:
Iout = (18)*(1.21)/RREF1
The CML outputs have on-chip 100 Ω load resistors to V
CC
to accommodate capacitive ac coupling. With a 50 Ω
1% load, the effective load resistance will be 33.33 Ω ± 6%. For a 400 mV voltage swing into the 50 Ω load, set
RREF1 to 1.8 kΩ. For a 600 mV voltage swing, set RREF1 to 1.2 kΩ. In both cases, RREF2 remains fixed at a
value of 1.5 kΩ.
14 Lucent Technologies Inc.
current and termination resistors
Preliminary Data Sheet TTRN012G5 and TTRN012G7
August 2000 Clock Synthesizer, 16:1 Data Multiplexer
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.
Parameter Min Max Unit
CC
Power Supply Voltage (V
)— 4.0 V
Storage Temperature –40 125 °C
Pin Voltage GND – 0.5 V
CC
+ 0.5 V
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid
exposure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model
(HBM) and charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD
voltage thresholds are dependent on the circuit parameters used in the defined model. No industrywide standard
has been adopted for the CDM. However, a standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely
used and, therefore, can be used for comparison purposes:
Device Voltage
TTRN012G5 ≥200 V
TTRN012G7 ≥200 V
Operating Conditions
Table 8. Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
Power Supply (dc voltage) — 3.135 3.3 3.465 V
Ground — — — — V
Input Voltage:
Low
High
Temperature:
Ambient T
Power Dissipation:
MBIC 025 BiCMOS
MBIC 025 SiGe BiCMOS
IL
V
IH
V
A
D
P
D
P
See Table 10,
Table 12,
Table 14.
See Table 10,
Table 12,
Table 14.
See Table 10,
Table 12,
Table 14.
–40 — 85 °C
—
—
1.5
0.9
TBD
1.14
V
V
W
W
15Lucent Technologies Inc.
TTRN012G5 and TTRN012G7 Preliminary Data Sheet
Clock Synthesizer, 16:1 Data Multiplexer August 2000
Electrical Characteristics
Reference Frequency (REFCLKP/N) Specifications
The device requires a differential LVPECL reference clock input.
■
When using the TTRN012G5 device, a 155.52 MHz differential LVPECL clock must be applied to the
REFCLKP/N input.
■
When using the TTRN012G7 device at the OC-48/STM-16 rate, a 155.52 MHz differential LVPECL clock must
be applied to the REFCLKP/N input.
■
When using the TTRN012G7 device at the RS FEC OC-48/STM-16 rate, a 166.62 MHz differential LVPECL
clock must be applied to the REFCLKP/N input.
Table 9 provides the characteristics of the REFCLKP/N input.
Table 9. Reference Frequency Characteristics
Parameter Min Typ Ma x Unit
Reference Frequency (REFCLKP/N) — 155.52 — MHz
— 166.62 — MHz
Reference Frequency Tolerance* –20 — 20 ppm
Duty Cycle 40 — 60 %
Phase Jitter
Temperature
Supply Voltage
* Includes effects of power supply variation, temperature, electrical loading, and aging. The ±20 ppm tolerance is
required to meet SONET/SDH requirements. For non-SONET/SDH compliant systems, looser tolerances may apply.
† Measured under one 3.3 V LVPECL load. Includes frequency components up to 2 MHz.
‡ Specified range is to be compatible with environmental specification of TTRN012G5 or TTRN012G7. Applications
requiring a reduced temperature range may specify the reference frequency oscillator accordingly.
†
‡
‡
— — 3 ps(rms)
–40 — 85 °C
3.10 — 3.60 V
16 Lucent Technologies Inc.
Preliminary Data Sheet TTRN012G5 and TTRN012G7
August 2000 Clock Synthesizer, 16:1 Data Multiplexer
Electrical Characteristics
(continued)
LVPECL, CMOS, CML Input and Output Pins
Notes:
CC
1. For Table 10 through Table 17, V
BiCMOS and MBIC 025 SiGe BiCMOS technologies.
2. For more information on interpreting CML specifications, see the CML Output Structure (Used on Pins
D2G5P/N, CK2G5P/N) section on page 14.
Table 10. LVPECL Input Pin Characteristics
Applicable
Symbol Parameter Conditions Min Typ Max Unit
Pins
IH
D[15:0]P/N,
PARITYP/N,
REFCLKP/N
V
V
I
I
Input Voltage High Referred to V
IL
Input Voltage Low Referred to V
IH
Input Current High Leakage V
IL
Input Current Low Leakage VIN = VIL (min) 5 — µA
Table 11. LVPECL Output Pin Characteristics
Applicable
Symbol Parameter Conditions Min Typ Max Unit
Pins
OH
CK155P/N,
V
Output Voltage High Load = 50 Ω
VALIDP/N,
MONAPAP/N
OL
V
Output Voltage Low Load = 50 Ω
= 3.3 V ± 5%, TA = –40 °C to +85 °C; these tables apply to both MBIC 025
CC
–1165 — –880 mV
CC
–1810 — –1475 mV
IN
IH
= V
(max) — — 20 µA
CC
V
– 1.31 V
CC
– 1.20 V
CC
– 0.90 V
connected to
CC
V
– 2.0 V
CC
V
– 1.95 V
CC
– 1.88 V
CC
– 1.80 V
connected to
CC
– 2.0 V
V
Table 12. CMOS Input Pin Characteristics
Applicable
Symbol Parameter Conditions Min Max Unit
Pins
RESETN,
PHADJ[1:0],
EXTADJN,
INVDATN,
TESTN,
V
V
Input Voltage High — V
IL
Input Voltage Low — GND 1.0 V
IH
I
Input Current High Leakage VIN = V
IL
Input Current Low Leakage V
I
IH
CLKMODE,
ENCK2G5,
ENLBDN
Table 13. CMOS Output Pin Characteristics
Applicable
Symbol Parameter Conditions Min Max Unit
Pins
LCKLOSSN V
OH
Output Voltage High I
OL
V
Output Voltage Low I
l
Output Load Capacitance — — 15 pF
C
CC
– 1.0 V
CC
IN
= GND –225 — µA
OH
= –4.0 mA VCC – 0.5 V
OL
= 4.0 mA GND 0.5 V
—10µA
CC
CC
V
V
17Lucent Technologies Inc.
TTRN012G5 and TTRN012G7 Preliminary Data Sheet
Clock Synthesizer, 16:1 Data Multiplexer August 2000
Electrical Characteristics
(continued)
LVPECL, CMOS, CML Input and Output Pins
Table 14. CML Input Pin dc Characteristics
Applicable
Pins
TSTCKP/N V
Table 15. CML Output Pin dc Characteristics
Applicable
Pins
D2G5P/N,
LBDP/N,
CK2G5P/N
* Applies when RREF1 = 1 k
† Applies when RREF1 = 1.8 k
‡ Applies when RREF1 = 6 k
Symbol Parameter Conditions Min Typ Max Unit
IL
Input Voltage Low —
IH
V
Input Voltage High
Symbol Parameter Conditions Min
OL
V
V
I
I
Output Voltage Low RREF2 = 1.5 k
L
R
OH
Output Voltage High — V
OL
Output Current Low 3.6 12 18 mA
OH
Output Current High — 0 1
Ω.
Ω.
Ω.
= 50
All signals
differential
(continued)
Ω,
Ω,
—
—
*
CC
V
– 1.2 VCC – 0.4 — V
CC
– 0.4
V
CC
V
†
Typ
CC
—
—
Max
VCC + 0.3 V
V
V
‡
Unit
A
µ
18 Lucent Technologies Inc.
Preliminary Data Sheet TTRN012G5 and TTRN012G7
August 2000 Clock Synthesizer, 16:1 Data Multiplexer
Timing Characteristics
Transmit Timing
Figure 8 shows the timing relationships between the 155.52 MHz or 166.62 MHz output clock (CK155P/N) and the
155.52 Mbits/s or 166.62 Mbits/s input data (D[15:0]P/N) and the input parity valid check (PARITYP/N). Also
shown is the relationship of the VALIDP/N output signal to CK155P/N; this relationship is true for both the contraclocking mode and the clockless transfer mode.
PERIOD
t
CK155P
OUTPUT
CK155N
SU
INPUTS
D[15:0]P/N,
PARITYP/N
t
DATA 1
DD
t
HOLD
t
DATA 2
OUTPUT VALIDP/N VALID 1 VALID 2
Note: T
SU
and T
HOLD
only apply in contra-clocking mode when CLKMODE = 1.
Figure 8. Transmit Timing Waveform
The 155 MHz or 166 MHz output clock and data signals from Figure 8 are characterized in Table 16.
Table 16. LVPECL Input/Output Pin ac Timing Characteristics
Applicable
Symbol Parameter Conditions Min Typ Max Unit
Pins
CK155P/N — Duty Cycle All signals
PERIOD
t
155.52 MHz Clock Period — 6.43 — ns
differential
40 50 60 %
166.62 MHz Clock Period — 6.00 — ns
Input Timing
D[15:0]P/N,
PA RITYP/N,
CK155P/N
SU
t
HOLD
t
RISE
t
FALL
t
SKEW
t
Setup from Clock Edge to
D[15:0]P/N or to
CLKMODE = 1, All
signals differential
2.0 — — ns
PA RITYP/N Edge
Hold from Clock Edge to
D[15:0]P/N or to
PA RITYP/N Edge
,
Rise, Fall Times:
20%—80%
CLKMODE = 1,
All signals
differential
All signals
differential
0.5 — — ns
200 500 800 ps
Transition Skew Rise to Fall –100 0 100 ps
Output Timing
VA LIDP/N,
CK155P/N
DD
t
RISE
t
FALL
t
SKEW
t
Time Delay from Clock Edge
to VALIDP/N Edge
,
Rise, Fall Times:
All signals
differential
–300 800 1500 ps
200 500 800 ps
20%—80%
Transition Skew Rise to Fall –100 0 100 ps
5-7726(F).hr.2
19Lucent Technologies Inc.
TTRN012G5 and TTRN012G7 Preliminary Data Sheet
Clock Synthesizer, 16:1 Data Multiplexer August 2000
Timing Characteristics
Transmit Timing
(continued)
(continued)
Figure 9 shows the timing relationship between the 2.5 GHz or 2.7 GHz output clock (CK2G5P/N) and the
2.5 Gbits/s or 2.7 Gbits/s output data (D2G5P/N).
PERIOD
t
CK2G5P
OUTPUT
CK2G5N
DD
t
OUTPUT
D2G5P/N
DATA 1
DATA 2 DATA 3
Figure 9. Transmit Timing Waveform with 2.5 GHz or 2.7 GHz Clock
The 2.5 GHz or 2.7 GHz output clock and data signals from Figure 9 are characterized in Table 17.
Table 17. CML Output Pin ac Timing Characteristics
5-7726(F).er.4
Applicable
Symbol Parameter Conditions Min Typ Max Unit
Pins
CK2G5P/N — Duty Cycle RREF1 = 1.8 kΩ
RREF2 = 1.5 kΩ
L
= 50 Ω
R
All signals
differential
D2G5P/N,
CK2G5P/N,
LBDP/N
PERIOD
t
DD
t
RISE
t
FALL
t
SKEW
t
2.48832 GHz Clock Period — 402 — ps
2.66606 GHz Clock Period — 375 — ps
Time Delay from Clock Edge
to Data Edge
,
Rise, Fall Times:
20%—80%
Transition Skew Rise to Fall –10 0 10 ps
40 50 60 %
151 201 251 ps
50 80 120 ps
20 Lucent Technologies Inc.
Preliminary Data Sheet TTRN012G5 and TTRN012G7
August 2000 Clock Synthesizer, 16:1 Data Multiplexer
Outline Diagram
128-Pin QFP
Dimensions are in millimeters.
17.20 ± 0.20
13.89 ± 0.10
8.13 (REF)
2.89
(REF)
103128
1
38
DETAIL A
1
XXXXXKNV
Code Name
YYWWL
11.43 ± 0.18
LUCENT
6439
102
5.87
(REF)
8.13
(REF)
65
2.80 (REF)
17.52
0.18
±
19.86
0.10
±
23.20
0.20
±
1.600 ± 0.150
0.800 ± 0.150
DETAIL A
2.89
(REF)
0.20 ± 0.06
0.50 (TYP)
8.13 (REF)
(8.13)2 x 0.305 HEAT SINK
0.000 TO 0.100
3.30 (REF)
0.38 (REF)
5-8416(F)r.2
21Lucent Technologies Inc.
TTRN012G5 and TTRN012G7 Preliminary Data Sheet
g
g
g
g
g
g
(
)
)
(
)
)
Clock Synthesizer, 16:1 Data Multiplexer August 2000
Ordering Information
Device Code Package Temperature Comcode
(Ordering Number)
TTRN012G5:
TTRN012G5
TTRN012G53XE1 (SiGe BiCMOS
BiCMOS
128-pin QFP
128-pin QFP
–40 °C to +85 °C
–40 °C to +85 °C
108419961
108700709
TTRN012G7:
TTRN012G7
TTRN012G73XE1 (SiGe BiCMOS
BiCMOS
128-pin QFP
128-pin QFP
–40 °C to +85 °C
–40 °C to +85 °C
108560335
108700717
————
DS00-375HSPL Replaces DS00-155HSPL to Incorporate the Following Updates
1. Added a second technology, MBIC 025 SiGe BiCMOS, to the data sheet.
2. Pa
3. Pa
4. Pa
5. Pa
6. Pa
7. Pa
e 7, REFCLKP/N pins, corrected definition.
e 15, Absolute Maximum Ratings, added maximum power supply value of 4.0 V.
e 15, Handling Precautions, corrected ESD threshold value from TBD to ≥200 V.
e 15, Table 8, added MBIC 025 SiGe BiCMOS power dissipation values.
e 17, Table 11, updated LVPECL Output Pin Characteristics.
e 22, Ordering Information, added MBIC 025 SiGe BiCMOS comcodes.
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET:
E-MAIL:
N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
CHINA: Microelectronics Group, Lucent Technologies ( C hina) Co., Lt d . , A - F2, 23/F, Zao Fong Uni verse Building, 1800 Zhong Sh an Xi Road, Sha ngh ai
JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE:
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.
Copyright © 2000 Lucent Technologies Inc.
All Rights Reserved
August 2000
DS00-375HSPL (Replaces DS00-155HSPL)
http://www.lucent.com/micro
docmaster@micro.lucent.com
1-800-372-2447
Tel. (65) 778 8833
200233 P. R. China
Tel. (81) 3 5421 1600
Technical Inquiries: GERMANY:
, FAX 610-712-4106 (In CANADA:
, FAX (65) 777 7495
Tel . ( 86) 21 6440 0468, ext. 325
, FAX (81) 3 5421 1700
FRANCE:
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ITALY:
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(Milan), SPAIN:
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, F A X ( 86) 21 6440 0652
(Munich), UNITED KINGDOM:
(Paris), SWEDEN:
, FAX 610-712-4106)
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, FAX (44) 1189 328 148
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