Lucent Technologies Inc TFRA08C13-DB Datasheet

Preliminary Data Sheet
October 2000

TFRA08C13 OCTAL T1/E1 Framer

Features

■

Eight independent T1/E1 transmit and receive
framers.

■

Internal DS1 transmit clock synthesis—no external
oscillator necessary.

■

Comprehensive alarm reporting and performance
monitoring:
— Programmable automatic and on-demand alarm

transmission.

■

Automatic facility data link:
— Automatic transmission of ESF performance

report message.

■

Common 2.048 Mbits/s, 4.096 Mbits/s, or

8.192 Mbits/s TDM highway.

■

Dual- or single-rail line-side I/O.

■

Supports one second polling interval for perfor­mance monitoring.

■

IEEE

* Std. 1149.1 JTAG boundary scan.

■

3.3 V low-power CMOS with 5 V tolerant inputs.

■

Available in 352-pin PBGA.

Facility Data Link Features

■

HDLC or transparent mode.

■

Automatic transmission of the ESF performance
report messages (PRM).

■

Detection of the ESF PRM.

■

Detection of the

■

64-byte FIFO in both transmit and receive direc-

ANSI

ESF FDL bit-oriented codes.

tions.

■

Programmable FIFO full and empty level interrupt.

■

User-programmable microprocessor interface.

Microprocessor Interface

■

33 MHz read and write access.

■

12-bit address, 8-bit data interface.

■

■

■

‡

Intel

or

Motorola

Directly addressable internal registers.
Programmable interrupts.

§

style control interfaces.

T1/E1 Framer Features

■

Supports T1 framing modes ESF, D4,
T1DM DDS.

■

Supports G.704 basic and CRC-4 multiframe for­mat E1 framing and procedures consistent with
G.706.

■

Supports unframed transmission format.

■

T1 signaling modes: transparent; ESF 2-state,
4-state, and 16-state; D4 2-state and 4-state;

SLC

-96 2-state, 4-state, 9-state, and 16-state. E1

signaling modes: transparent and CAS.

■

Alarm reporting and performance monitoring per
AT&T,

■

Programmable, independent transmit and receive

†

ANSI

, and ITU-T standards.

system interfaces at a 2.048 MHz, 4.096 MHz, or

8.192 MHz data rate.

SLC

®

-96,

Applications

■

DS3 and E3 port cards for narrowband DXCs.

■

Multiservice switches.

■

High density DS1 and E1 port cards.

■

Frame relay access devices.

■

Byte-synchronou s SDH/ SO NE T mappin g .

■

SONET and SDH drop alignment.

■

IP and packet routers.

*

IEEE

is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

†

ANSI

is a registered trademark of American National Standards

Institute, Inc.

Intel

is a registered trademark of Intel Corporation.

‡

§

Motorola

is a registered trademark of Motorola, Inc.

Preliminary Data Sheet

TFRA08C13 OCTAL T1/E1 Framer October 2000

Table of Contents

Contents Page

Features ................................................................................................................................................................... 1

T1/E1 Framer Features......................................................................................................................................... 1

Facility Data Link Features....................................................................................................................................... 1

Microprocessor Interface.......................................................................................................................................... 1

Applications .............................................................................................................................................................. 1

Feature Descriptions .............................................................................................................................................. 10

T1/E1 Framer Feature Descriptions.................................................................................................................... 10

Functional Description............................................................................................................................................ 11

Pin Information ....................................................................................................................................................... 15

LIU-Framer Interface.................................... ...... ....... ...... ....... ...... ................................................................. ...... ... 29

LIU-Framer Physical Interface............ ....... ...... ....... ...... ....... ...... ....... ...................................... ............................. 29

Line Encoding...................................................................................................................................................... 31

DS1: Zero Code Suppression (ZCS)................................................................................................................... 31

CEPT: High-Density Bipolar of Order 3 (HDB3).................................................................................................. 33

Frame Formats................................ ...... ....... ...... ....... ...... ....... ...................................... ..... .. ...... ...... ....................... 34

T1 Framing Structures......................................................................................................................................... 34

T1 Loss of Frame Alignment (LFA)..................................................................................................................... 41

T1 Frame Recovery Alignment Algorithms.......................................................................................................... 42

T1 Robbed-Bit Signaling ..................................................................................................................................... 43

CEPT 2.048 Basic Frame, CRC-4 Time Slot 0, and Signaling Time Slot 16 Multiframe Structures ................... 45

CEPT 2.048 Basic Frame Structure.................................................................................................................... 46

CEPT Loss of Basic Frame Alignment (LFA)...................................................................................................... 48

CEPT Loss of Frame Alignment Recovery Algorithm ......................................................................................... 48

CEPT Time Slot 0 CRC-4 Multiframe Structure .................................................................................................. 49

CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA).................................................................................... 50

CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms.....................................................................51

CEPT Time Slot 16 Multiframe Structure............................................................................................................ 55

CEPT Loss of Time Slot 16 Multiframe Alignment (LTS16MFA)......................................................................... 56

CEPT Loss of Time Slot 16 Multiframe Alignment Recovery Algorithm.............................................................. 56

CEPT Time Slot 0 FAS/NOT FAS Control Bits....................................................................................................... 56

FAS/NOT FAS Si- and E-Bit Source................................................................................................................... 56

NOT FAS A-Bit (CEPT Remote Frame Alarm) Sources ..................................................................................... 57

NOT FAS Sa-Bit Sources.................................................................................................................................... 57

Sa Facility Data Link Access............................................................................................................................... 58

NOT FAS Sa Stack Source and Destination....................................................................................................... 59

CEPT Time Slot 16 X0—X2 Control Bits............................................................................................................. 61

Signaling Access .................................................................................................................................................... 61

Transparent Signaling ......................................................................................................................................... 61

DS1: Robbed-Bit Signaling.................................................................................................................................. 61

CEPT: Time Slot 16 Signaling............................................................................................................................. 62

Auxiliary Framer I/O Timing ................................................................................................................................... 63

Alarms and Performance Monitoring...................................................................................................................... 67

Interrupt Generation ............................................................................................................................................ 67

Alarm Definition................................................................................................................................................... 67

Event Counters Definition ................................................................................................................................... 73

Loopback and Transmission Modes.................................................................................................................... 75

Line Test Patterns ............................................................................................................................................... 78

Receive Line Pattern Monitor—Using Register FRM_SR7................................................................................. 80

Automatic and On-Demand Commands ............................................................................................................. 82

Facility Data Link .................................................................................................................................................... 84

2 Lucent Technologies Inc.

Preliminary Data Sheet
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Table of Contents

(continued)

Contents Page

Receive Facility Data Link Interface.....................................................................................................................84

Transmit Facility Data Link Interface....................................................................................................................90

HDLC Operation ..................................................................................................................................................91

Transparent Mode................................................................................................................................................93

Diagnostic Modes ................................................................................................................................................95

Phase-Lock Loop Circuit .........................................................................................................................................96

Framer-System Interface ........................................................................................................................................98

DS1 Modes ..........................................................................................................................................................98

CEPT Modes........................................................................................................................................................98

Receive Elastic Store...........................................................................................................................................98

Transmit Elastic Store..........................................................................................................................................98

Concentration Highway Interface ............................................................................................................................98

CHI Parameters ...................................................................................................................................................99

CHI Frame Timing..............................................................................................................................................101

CHI Offset Programming....................................................................................................................................104

JTAG Boundary-Scan Specification..................................................................................................................... 105

Principle of the Boundary Scan..........................................................................................................................105

Test Access Port Controller...............................................................................................................................107

Instruction Register............................................................................................................................................109

Boundary-Scan Register....................................................................................................................................110

BYPASS Register ........................................................ ....... ...... ...... ....... ...... ....... ...... ....... .... .. ....... ...... ....... ...... ..110

DCODE Register................................................................................................................................................110

3-State Procedures............................................................................................................................................110

Microprocessor Interface.......................................................................................................................................111

Overview............................................................................................................................................................111

Microprocessor Configuration Modes ................................................................................................................111

Microprocessor Interface Pinout Definitions ......................................................................................................112

Microprocessor Clock (MPCLK) Specifications .................................................................................................112

Microprocessor Interface Register Address Map...............................................................................................113

I/O Timing ..........................................................................................................................................................113

Reset.................................................................................................................................................................... 118

Hardware Reset (Pin C19).................................................................................................................................118

Software Reset/Software Restart.......................................................................................................................118

Interrupt Generation..............................................................................................................................................118

Register Architecture.............................................................................................................................................119

Global Register Architecture .................................................................................................................................123

Global Register Structure......................................................................................................................................123

Framer Block Interrupt Status Register (GREG0)..............................................................................................123

Framer Block Interrupt Enable Register (GREG1).............................................................................................124

FDL Block Interrupt Status Enable Register (GREG2) ......................................................................................124

FDL Block Interrupt Enable Register (GREG3) .................................................................................................124

Global Control Register (GREG4)......................................................................................................................125

Device ID and Version Registers (GREG5—GREG7).......................................................................................125

Global Control Register (GREG8)......................................................................................................................126

Global PLLCK Control Register (GREG9) .........................................................................................................127

Framer Register Architecture.......... ...... ....... ...... ....... ...... ....... ...... ...... ................................................................. ..127

Framer Status/Counter Registers ............. ...... ....... ...... ....................................... ...... ....... ...... ...... . ...... ...............1 28

Framer Parameter/Control Registers..................... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ............................141

FDL Register Architecture.. ...... ....... ...... ....... ...... ....... ...... ....... ...... ....................................... ... ... ............................168

FDL Parameter/Control Registers ((A00—A0E); (A20—A2E); (B00—B0E);

(B20—B2E) (C00—C0E); (C20—C2E); (D00—D0E); (D20—D2E)) .................................................................169

Lucent Technologies Inc. 3

Preliminary Data Sheet

TFRA08C13 OCTAL T1/E1 Framer October 2000

Table of Contents

(continued)

Contents Page

Register Maps ...................................................................................................................................................... 176

Global Registers.................... ....... ...... ....... ....................................... ...... ...... ....... ...... ........................................ 176

Framer Parameter/Control Registers (Read-Write)........................................................................................... 177

Receive Framer Signaling Registers (Read-Only) ............................................................................................ 179

Framer Unit Parameter Register Map............................................................................................................... 180

Transmit Signaling Registers (Read/Write)....................................................................................................... 183

Facility Data Link Parameter/Control and Status Registers (Read-Write)......................................................... 184

Absolute Maximum Ratings.................................................................................................................................. 185

Operating Conditions.......... ...... ....... ...... ....... ...... ....... ...... ....... ...... ....... ...................................... ....... ...... ....... ...... . 185

Handling Precautions ............................ ....... ...... ....... ...... ....... ...... ....... ...... ....................................... ...... ....... ...... . 185

Electrical Characteristics ...................................................................................................................................... 186

Logic Interface Characteristics.......................................................................................................................... 186

Power Supply Bypassing...................................................................................................................................... 186

Outline Diagram.................................................................................................................................................... 187

352-Pin PBGA................................................................................................................................................... 187

Ordering Information............................................................................................................................................. 188

Figures Page

Figure 1. TFRA08C13 Block Diagram (One of Eight Channels)............................................................................. 11

Figure 2. TFRA08C13 Block Diagram: Receive Section (One of Eight Channels)................................................. 13

Figure 3. TFRA08C13 Block Diagram: Transmit Section (One of Eight Channels)................................................ 14

Figure 4. Pin Assignment ....................................................................................................................................... 15

Figure 5. Block Diagram of Framer Line Interface.................................................................................................. 29

Figure 6. Transmit Framer TLCK to TND, TPD and Receive Framer RND, RPD to RLCK Timing ......................... 30

Figure 7. T1 Frame Structure ................................................................................................................................. 34

Figure 8. T1 Transparent Frame Structure ............................................................................................................. 35

Figure 9. T7633 Facility Data Link Access Timing of the Transmit and Receive Framer Sections......................... 37

Figure 10.
Figure 11. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated

Signaling Multiframe Structures .......................................................................................................................... 45

Figure 12. CEPT Transparent Frame Structure...................................................................................................... 47

Figure 13. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer................................... 52

Figure 14. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4 Equipment

Interworking as Defined by ITU (From ITU Rec. G.706, Annex B.2.2 - 1991)..................................................... 54

Figure 15. Facility Data Link Access Timing of the Transmit and Receive

Framer Sections in the CEPT Mode.................................................................................................................... 58

Figure 16. Transmit and Receive Sa Stack Accessing Protocol............................................................................. 60

Figure 17. Timing Specification for RFRMCK, RFRMDATA, and RFS in DS1 Mode.............................................. 63

Figure 18. Timing Specification for TFS, TLCK, and TPD in DS1 Mode ................................................................ 63

Figure 19. Timing Specification for RFRMCK, RFRMDATA, and RFS in CEPT Mode ........................................... 64

Figure 20. Timing Specification for RFRMCK, RFRMDATA, RFS, and RSSFS in CEPT Mode ............................. 64

Figure 21. Timing Specification for RCRCMFS in CEPT Mode.............................................................................. 65

Figure 22. Timing Specification for TFS, TLCK, and TPD in CEPT Mode.............................................................. 65

Figure 23. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode ................................................ 66

Figure 24. Timing Specification for TFS, TLCK, TPD, and TCRCMFS in CEPT Mode .......................................... 66

Figure 25. Relation Between RLCK1 and Interrupt (Pin AD8)................................................................................ 67

Figure 26. Timing for Generation of LOPLLCK (Pin F25)....................................................................................... 69

Figure 27. The T and V Reference Points for a Typical CEPT E1 Application........................................................ 72

Figure 28. Loopback and Test Transmission Modes............................................................................................... 77

SLC-

96 Frame Format........................................................................................................................... 37

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Table of Contents

(continued)

Figures Page

Figure 29. 20-Stage Shift Register Used to Generate the Quasi-Random Signal ..................................................78

Figure 30. 15-Stage Shift Register Used to Generate the Pseudorandom Signal ..................................................79

Figure 31. TFRA08C13 Facility Data Link Access Timing of the Transmit and Receive Framer Sections..............84

Figure 32. Block Diagram for the Receive Facility Data Link Interface....................................................................85

Figure 33. Block Diagram for the Transmit Facility Data Link Interface ...................................................................90

Figure 34. Local Loopback Mode............................................................................................................................95

Figure 35. Remote Loopback Mode........................................................................................................................96

Figure 36. TFRA08C13 Phase Detector Circuitry...................................................................................................97

Figure 37. Nominal Concentration Highway Interface Timing (for FRM_PR43 bit 0—bit 2 = 100 (Binary))..........101

Figure 38. CHIDTS Mode Concentration Highway Interface Timing..................................................................... 102

Figure 39. Associated Signaling Mode Concentration Highway Interface Timing.................................................103

Figure 40. CHI Timing with ASM and CHIDTS Enabled .......................................................................................103

Figure 41. TCHIDATA and RCHIDATA to CHICK Relationship with CMS = 0

(CEX = 3 and CER = 4, Respectively)...............................................................................................................104

Figure 42. Receive CHI (RCHIDATA) Timing.........................................................................................................105

Figure 43. Transmit CHI (TCHIDATA) Timing ........................................................................................................105

Figure 44. Block Diagram of the TFRA08C13's Boundary-Scan Test Logic .........................................................106

Figure 45. BS TAP Controller State Diagram ........................................................................................................107

Figure 46. Mode 1—Read Cycle Timing (MPMODE = 0) .....................................................................................116

Figure 47. Mode 1—Write Cycle Timing (MPMODE = 0)......................................................................................116

Figure 48. Mode 3—Read Cycle Timing (MPMODE = 1) .....................................................................................117

Figure 49. Mode 3—Write Cycle Timing (MPMODE = 1)......................................................................................117

Tables Page

Table 1. Pin Assignments for 352-Pin PBGA by Pin Number Order.......................................................................16

Table 2. Pin Descriptions........................................................................................................................................18

Table 3. AMI Encoding ...........................................................................................................................................31

Table 4. DS1 ZCS Encoding...................................................................................................................................32

Table 5. DS1 B8ZS Encoding.................................................................................................................................32

Table 6. ITUHDB3 Coding......................................................................................................................................33

Table 7. T-Carrier Hierarchy....................................................................................................................................34

Table 8. D4 Superframe Format.............................................................................................................................36

Table 9. DDS Channel-24 Format ..........................................................................................................................37

Table 10.
Table 11.
Table 12. Transmit and Receive

Table 13. Extended Superframe (ESF) Structure...................................................................................................40

Table 14. T1 Loss of Frame Alignment Criteria ......................................................................................................41

Table 15. T1 Frame Alignment Procedures ............................................................................................................42

Table 16. Robbed-Bit Signaling Options.................................................................................................................43

Table 17.

Table 18.16-State Signaling Format.......................................................................................................................44

Table 19. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame......................................................46

Table 20. ITU CRC-4 Multiframe Structure.............................................................................................................49

Table 21. ITU CEPT Time Slot 16 Channel Associated Signaling Multiframe Structure........................................55

Table 22. Transmit and Receive Sa Stack Structure...............................................................................................59

Table 23. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames...........................................62

Table 24. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels....................................62

SLC

-96 Data Link Block Format .............................................................................................................38

SLC

-96 Line Switch Message Codes .....................................................................................................39

SLC

-96 Stack Structure.......................................................................................39

SLC

-96 9-State Signaling Format...........................................................................................................43

Lucent Technologies Inc. 5

Preliminary Data Sheet

TFRA08C13 OCTAL T1/E1 Framer October 2000

Table of Contents

(continued)

Tables Page

Table 25. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT..................................................... 62

Table 26. Red Alarm or Loss of Frame Alignment Conditions ............................................................................... 68

Table 27. Remote Frame Alarm Conditions........................................................................................................... 68

Table 28. Alarm Indication Signal Conditions ........................................................................................................ 69

Table 29. Sa6 Bit Coding Recognized by the Receive Framer. ............................................................................. 71

Table 30. Sa6 Bit Coding of NT1 Interface Events Recognized by the Receive Framer........................................ 71

Table 31. AUXP Synchronization and Clear Synchronization Process.................................................................. 72

Table 32. Event Counters Definition ...................................................................................................................... 73

Table 33. Summary of the Deactivation of SSTSSLB and SSTSLLB Modes as a

Function of Activating the Primary Loopback Modes .......................................................................................... 76

Table 34. Register FRM_PR69 Test Patterns........................................................................................................ 79

Table 35. Register FRM_PR70 Test Patterns........................................................................................................ 80

Table 36. Automatic Enable Commands................................................................................................................ 82

Table 37. On-Demand Commands ........................................................................................................................ 83

Table 38. Receive

Table 39. Performance Report Message Structure................................................................................................ 86

Table 40. FDL Performance Report Message Field Definition............................................................................... 87

Table 41. Octet Contents and Definition ................................................................................................................ 87

Table 42. Receive Status of Frame Byte................................................................................................................ 88

Table 43. HDLC Frame Format.............................................................................................................................. 91

Table 44. Receiver Operation in Transparent Mode............................................................................................... 94

Table 45. Summary of the TFRA08C13’s Concentration Highway Interface Parameters...................................... 99

Table 46. Programming Values for TOFF[2:0] and ROFF[2:0] when CMS = 0 .................................................... 104

Table 47. TAP Controller States in the Data Register Branch.............................................................................. 108

Table 48. TAP Controller States in the Instruction Register Branch..................................................................... 108

Table 49. TFRA08C13’s Boundary-Scan Instructions ......................................................................................... 109

Table 50. IDCODE Register................................................................................................................................. 110

Table 51. Microprocessor Configuration Modes .................................................................................................. 111

Table 52. Mode [1 and 3] Microprocessor Pin Definitions.................................................................................... 112

Table 53. Microprocessor Input Clock Specifications .......................................................................................... 112

Table 54. TFRA08C13 Register Address Map..................................................................................................... 113

Table 55. Microprocessor Interface I/O Timing Specifications............................................................................. 114

Table 56. Status Register and Corresponding Interrupt Enable Register for Functional Blocks.......................... 118

Table 57. Asserted Value and Deasserted State for GREG4 Bit 4 and Bit 6 Logic Combinations ...................... 118

Table 58. Register Summary ............................................................................................................................... 119

Table 59. Global Register Set (0x000—0x009) ................................................................................................... 123

Table 60. Framer Block Interrupt Status Register (GREG0) (000)....................................................................... 123

Table 61. Framer Block Interrupt Enable Register (GREG1) (001)...................................................................... 124

Table 62. FDL Block Interrupt Status Register (GREG2) (002)........................................................................... 124

Table 63. FDL Block Interrupt Enable Register (GREG3) (003) .......................................................................... 124

Table 64. Global Control Register (GREG4) (004) .............................................................................................. 125

Table 65. Device ID and Version Registers (GREG5—GREG7) (005—007) ...................................................... 125

Table 66. Global Control Register (GREG8) (008) .............................................................................................. 126

Table 67. Global PLLCK Control Register (GREG9) (009).................................................................................. 127

Table 68. Framer Status and Control Blocks Address Range (Hexadecimal)...................................................... 127

Table 69. Interrupt Status Register (FRM_SR0) (Y00)........................................................................................ 128

Table 70. Facility Alarm Condition Register (FRM_SR1) (Y01) ........................................................................... 129

Table 71. Remote End Alarm Register (FRM_SR2) (Y02) .................................................................................. 130

Table 72. Facility Errored Event Register-1 (FRM_SR3) (Y03) ........................................................................... 131

ANSI

Code ............................................................................................................................... 86

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Preliminary Data Sheet
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Table of Contents

(continued)

Tables Page

Table 73. Facility Event Register-2 (FRM_SR4) (Y04) ........................................................................................132

Table 74. Exchange Termination and Exchange Termination Remote

End Interface Status Register (FRM_SR5) (Y05)..............................................................................................133

Table 75. Network Termination and Network Termination Remote End

Interface Status Register (FRM_SR6) (Y06)......................................................................................................134

Table 76. Facility Event Register (FRM_SR7) (Y07) ............................................................................................135

Table 77. Bipolar Violation Counter Registers (FRM_SR8—FRM_SR9) (Y08—Y09) .........................................135

Table 78. Framing Bit Error Counter Registers (FRM_SR10—FRM_SR11) (Y0A—Y0B)....................................135

Table 79. CRC Error Counter Registers (FRM_SR12—FRM_SR13) (Y0C—Y0D) .............................................136

Table 80. E-Bit Counter Registers (FRM_SR14—FRM_SR15) (Y0E—Y0F).......................................................136

Table 81. CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16—FRM_SR17) (Y10—Y11)..............136

Table 82. E Bit at NT1 from NT2 Counter (FRM_SR18—FRM_SR19) (Y12—Y13) ............................................136

Table 83. ET Errored Seconds Counter (FRM_SR20—FRM_SR21) (Y14—Y15)...............................................137

Table 84. ET Bursty Errored Seconds Counter (FRM_SR22—FRM_SR23) (Y16—Y17)....................................137

Table 85. ET Severely Errored Seconds Counter (FRM_SR24—FRM_SR25) (Y18—Y19) ................................137

Table 86. ET Unavailable Seconds Counter (FRM_SR26—FRM_SR27) (Y1A—Y1B)........................................137

Table 87. ET-RE Errored Seconds Counter (FRM_SR28—FRM_SR29) (Y1C—Y1D) ........................................137

Table 88. ET-RE Bursty Errored Seconds Counter (FRM_SR30—FRM_SR31) (Y1E—Y1F)..............................137

Table 89. ET-RE Severely Errored Seconds Counter (FRM_SR32—FRM_SR33) (Y20—Y21)...........................137

Table 90. ET-RE Unav ailable Seconds Counter (FRM_SR34—FRM_SR35) (Y22—Y23)...................................138

Table 91. NT1 Errored Seconds Counter (FRM_SR36—FRM_SR37) (Y24—Y25).............................................138

Table 92. NT1 Bursty Errored Seconds Counter (FRM_SR38—FRM_SR39) (Y26—Y27)..................................138

Table 93. NT1 Severely Errored Seconds Counter (FRM_SR40—FRM_SR41) (Y28—Y29) ..............................138

Table 94. NT1 Unavailable Seconds Counter (FRM_SR42—FRM_SR43) (Y2A—Y2B)......................................138

Table 95. NT1-RE Errored Seconds Counter (FRM_SR44—FRM_SR45) (Y2C—Y2D) .....................................138

Table 96. NT1-RE Bursty Errored Seconds Counter (FRM_SR46—FRM_SR47) (Y2E—Y2F)...........................138

Table 97. NT1-RE Severely Errored Seconds Counter (FRM_SR48—FRM_SR49) (Y30—Y31)........................138

Table 98. NT1-RE Unavailable Seconds Counter (FRM_SR50—FRM_SR51) (Y32—Y33)................................139

Table 99. Receive NOT-FAS TS0 Register (FRM_SR52) (Y34) ...........................................................................139

Table 100. Receive Sa Register (FRM_SR53) (Y35) ...........................................................................................139

Table 101.

Table 102. CEPT Sa Receive Stack (FRM_SR54—FRM_SR63) (Y36—Y3F) ....................................................140

Table 103. Transmit Framer

Table 104. Received Signaling Registers: DS1 Format (FRM_RSR0—FRM_RSR23) (Y40—Y58)....................140

Table 105. Receive Signaling Registers: CEPT Format (FRM_RSR0—FRM_RSR31) (Y40—Y5F)...................141

Table 106. Summary of Interrupt Group Enable Registers (FRM_PR0—FRM_PR7) (Y60—Y67) ......................141

Table 107. Primary Interrupt Group Enable Register (FRM_PR0) (Y60) .............................................................142

Table 108. Interrupt Enable Register (FRM_PR1) (Y61)......................................................................................142

Table 109. Interrupt Enable Register (FRM_PR2) (Y62)......................................................................................142

Table 110. Interrupt Enable Register (FRM_PR3) (Y63)......................................................................................142

Table 111. Interrupt Enable Register (FRM_PR4) (Y64)......................................................................................143

Table 112. Interrupt Enable Register (FRM_PR5) (Y65)......................................................................................143

Table 113. Interrupt Enable Register (FRM_PR6) (Y66)......................................................................................143

Table 114. Interrupt Enable Register (FRM_PR7) (Y67)......................................................................................143

Table 115. Framer Mode Bits Decoding (FRM_PR8) (Y68) .................................................................................143

Table 116. Line Code Option Bits Decoding (FRM_PR8) (Y68)...........................................................................144

Table 117. CRC Option Bits Decoding (FRM_PR9) (Y69) ...................................................................................144

Table 118. Alarm Filter Register (FRM_PR10) (Y6A)...........................................................................................145

Table 119. Errored Event Threshold Definition.....................................................................................................145

Table 120. Errored Second Threshold Register (FRM_PR11) (Y6B)...................................................................146

SLC

-96 FDL Receive Stack (FRM_SR54—FRM_SR63) (Y36—Y3F) ...............................................139

ANSI

Performance Report Message Status Register Structure ..............................140

Lucent Technologies Inc. 7

Preliminary Data Sheet

TFRA08C13 OCTAL T1/E1 Framer October 2000

Table of Contents

(continued)

Tables Page

Table 121. Severely Errored Second Threshold Registers (FRM_PR12—FRM_PR13) (Y6C—Y6D) ................ 146

Table 122. ET1 Errored Event Enable Register (FRM_PR14) (Y6E)................................................................... 146

Table 123. ET1 Remote End Errored Event Enable Register (FRM_PR15) (Y6F).............................................. 146

Table 124. NT1 Errored Event Enable Register (FRM_PR16) (Y70)................................................................... 147

Table 125. NT1 Remote End Errored Event Enable Registers (FRM_PR17—FRM_PR18) (Y71—Y72)............ 147

Table 126. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (Y73)........... 147

Table 127. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (Y73)........... 148

Table 128. Transmit Test Pattern to the Line Enable Register (FRM_PR20) (Y74) ............................................. 148

Table 129. Framer FDL Control Command Register (FRM_PR21) (Y75) ........................................................... 149

Table 130. Framer Transmit Line Idle Code Register (FRM_PR22) (Y76)........................................................... 149

Table 131. Framer System Stuffed Time-Slot Code Register (FRM_PR23) (Y77).............................................. 149

Table 132. Primary Time-Slot Loopback Address Register (FRM_PR24) (Y78)................................................. 150

Table 133. Loopback Decoding of Bits LBC[2:0] in FRM_PR24, Bits 7—5 ......................................................... 150

Table 134. Secondary Time-Slot Loopback Address Register (FRM_PR25) (Y79) ............................................ 151

Table 135. Loopback Decoding of Bits LBC[1:0] in FRM_PR25, Bits 6—5 ......................................................... 151

Table 136. Framer Reset and Transparent Mode Control Register (FRM_PR26) (Y7A) ..................................... 152

Table 137. Transmission of Remote Frame Alarm and CEPT Automatic

Transmission of A Bit = 1 Control Register (FRM_PR27) (Y7B) ....................................................................... 153

Table 138. CEPT Automatic Transmission of E Bit = 0 Control Register (FRM_PR28) (Y7C)............................. 154

Table 139. Sa4—Sa8 Source Register (FRM_PR29) (Y7D) ............................................................................... 154

Table 140. Sa Bits Source Control for Bit 5—Bit 7 in FRM_PR29 ....................................................................... 155

Table 141. Sa4—Sa8 Control Register (FRM_PR30) (Y7E) ............................................................................... 155

Table 142. Sa Transmit Stack (FRM_PR31—FRM_PR40) (Y7F—Y88).............................................................. 156

Table 143.
Table 144. Transmit
Table 145. CEPT Time Slot 16 X-Bit Remote Multiframe Alarm and AIS

Control Register (FRM_PR41) (Y89) ................................................................................................................ 157

Table 146. Framer Exercise Register (FRM_PR42) (Y8A) .................................................................................. 157

Table 147. Framer Exercises, FRM_PR42 Bit 5—Bit 0 (Y8A) ............................................................................. 158

Table 148. DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43) (Y8B)........... 159

Table 149. Signaling Mode Register (FRM_PR44) (Y8C) ................................................................................... 160

Table 150. CHI Common Control Register (FRM_PR45) (Y8D).......................................................................... 161

Table 151. CHI Common Control Register (FRM_PR46) (Y8E).......................................................................... 162

Table 152. CHI Transmit Control Register (FRM_PR47) (Y8F) ........................................................................... 162

Table 153. CHI Receive Control Register (FRM_PR48) (Y90)............................................................................ 162

Table 154. CHI Transmit Time-Slot Enable Registers (FRM_PR49—FRM_PR52) (Y91—Y94) ......................... 163

Table 155. CHI Receive Time-Slot Enable Registers (FRM_PR53—FRM_PR56) (Y95—Y98).......................... 163

Table 156. CHI Transmit Highway Select Registers (FRM_PR57—FRM_PR60) (Y99—Y9C)............................ 163

Table 157. CHI Receive Highway Select Registers (FRM_PR61—FRM_PR64) (Y9D—YA0) ............................ 163

Table 158. CHI Transmit Control Register (FRM_PR65) (YA1)............................................................................ 164

Table 159. CHI Receive Control Register (FRM_PR66) (YA2)............................................................................ 164

Table 160. Auxiliary Pattern Generator Control Register (FRM_PR69) (Y A5)..................................................... 165

Table 161. Pattern Detector Control Register (FRM_PR70) (YA6)...................................................................... 166

Table 162. Transmit Signaling Registers: DS1 Format (FRM_TSR0—FRM_TSR23) (YE0—YF7)..................... 167

Table 163. Transmit Signaling Registers: CEPT Format (FRM_TSR0—FRM_TSR31) (YE0—YFF) .................. 167

Table 164. FDL Register Set ((A00—A0E); (A20—A2E); (B00—B0E); (B20—B2E)

(C00—C0E); (C20—C2E); (D00—D0E); (D20—D2E)).....................................................................................168

Table 165. FDL Configuration Control Register (FDL_PR0) (A00; A20; B00; B20; C00; C20; D00; D20) .......... 169

Table 166. FDL Control Register (FDL_PR1) (A01; A21; B01; B21; C01; C21; D01; D21)................................. 169

SLC

-96 Transmit Stack (FRM_PR31—FRM_PR40) (Y7F—Y88)...................................................... 156

SLC

-96 FDL Format ............................................................................................................ 156

8 Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Table of Contents

(continued)

Tables Page

Table 167. FDL Interrupt Mask Control Register (FDL_PR2) (A02; A22; B02; B22; C02; C22; D02; D22) .........170

Table 168. FDL Transmitter Configuration Control Register (FDL_PR3)

(A03; A23; B03; B23; C03; C23; D03; D23).......................................................................................................171

Table 169. FDL Transmitter FIFO Register (FDL_PR4) (A04; A24; B04; B24; C04; C24; D04; D24) ..................171

Table 170. FDL Transmitter Idle Character Mask Register (FDL_PR5)

(A05; A25; B05; B25; C05; C25; D05; D25).......................................................................................................171

Table 171. FDL Receiver Interrupt Level Control Register (FDL_PR6)

(A06; A26; B06; B26; C06; C26; D06; D26).......................................................................................................172

Table 172. FDL Register FDL_PR7......................................................................................................................172

Table 173. FDL Receiver Match Character Register (FDL_PR8) (A08; A28; B08; B28; C08; C28; D08; D28) ...172

Table 174. FDL Transparent Control Register (FDL_PR9) (A09; A29; B09; B29; C09; C29; D09; D29)..............173

Table 175. FDL Transmit
Table 176. FDL Interrupt Status Register (Clear on Read) (FDL_SR0)

(A0B; A2B; B0B; B2B; C0B; C2B; D0B; D2B) ...................................................................................................174

Table 177. FDL Transmitter Status Register (FDL_SR1) (A0C; A2C; B0C; B2C; C0C; C2C; D0C; D2C) ...........175

Table 178. FDL Receiver Status Register (FDL_SR2) (A0D; A2D; B0D; B2D; C0D; C2D; D0D; D2D) ..............175

Table 179. Receive

Table 180. FDL Receiver FIFO Register (FDL_SR4) (A07; A27; B07; B27; C07; C27; D07; D27)......................175

Table 181. Global Register Set.............................................................................................................................176

Table 182. Framer Unit Status Register Map .......................................................................................................177

Table 183. Receive Signaling Registers Map.......................................................................................................179

Table 184. Framer Unit Parameter Register Map.................................................................................................180

Table 185. Transmit Signaling Registers Map ......................................................................................................183

Table 186. Facility Data Link Register Map ..........................................................................................................184

Table 187. ESD Threshold Voltage.......................................................................................................................185

Table 188. Logic Interface Characteristics (T

ANSI

ESF Bit Codes (FDL_PR10) (A0A; A2A; B0A; B2A; C0A; C2A; D0A; D2A).......173

ANSI

FDL Status Register (FDL_SR3) (A0E; A2E; B0E; B2E; C0E; C2E; D0E; D2E) ........175

= –40 °C to +85 °C, VDD = 3.3 V ± 5%, VSS = 0).........................186

A

Lucent Technologies Inc. 9

Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Feature Descriptions

T1/E1 Framer Feature Descriptions

■

Framing formats:
— Compliant with T1 standards

AT&T TR54016, AT&T TR62411 (1998).

— Unframed, transparent transmission in T1 and E1

formats.
— DS1 extended superframe (ESF).
— DS1 superframe (SF): D4;

T1DM DDS with FDL access.
— DS1 independent transmit and receive framing

modes when using the ESF and D4 formats.
— Compliant with ITU CEPT framing recommenda-

tion:

1. G.704 and G.706 basic frame format.

2. G.704 Section 2.3.3.4 and G.706 Section 4.2:
CRC-4 multiframe search algorithm.

3. G.706 Annex B: CRC-4 multiframe search algo­rithm with 400 ms timer for interworking of
CRC-4 and non-CRC-4 equipment.

4. G.706 Section 4.3.2 Note 2: monitoring of 915
CRC-4 checksum errors for loss of frame state.

■

Framer line codes:
— DS1: alternate mark inversion (AMI); binary eight

zero code suppression (B8ZS); per-channel zero
code suppression; decoding bipolar violation mon­itor; monitoring of eight or fifteen bit intervals with­out positive or negative pulses error indication.

— DS1 independent transmit and receive path line

code formats when using AMI/ZCS and B8ZS
coding.

— ITU-CEPT: AMI; high-density bipolar 3 (HDB3)

encoding and decoding bipolar violation monitor­ing, monitoring of four bit intervals without positive
or negative pulses error indication.

— Single-rail option.

■

Signaling:
— DS1: extended superframe 2-state, 4-state, and

16-state per-channel robbed bit.

— DS1: D4 superframe 2-state and 4-state per-

channel robbed bit.

— DS1:

SLC

-96 superframe 2-state, 4-state, 9-state,

and 16-state per-channel robbed bit.
— DS1: channel-24 message-oriented signaling.
— ITU CEPT: channel associated signaling (CAS).
— Transparent (all data channels).

■

Alarm reporting, performance monitoring, and main­tenance:
—

ANSI

T1.403-1995, AT&T TR 54016, and ITU

G.826 standard error checking.
— Error and status counters:

1. Bipolar violations.

ANSI

T1.231 (1993),

SLC

-96; T1DM DDS;

2. Errored frame alignment signals.

3. Errored CRC checksum block.

4. CEPT: received E bit = 0.

5. Errored, severely errored, and unavailable
seconds.

— Selectable errored event monitoring for errored

and severely errored seconds processing with
programmable thresholds for errored and severely
errored second monitoring.

— CEPT: Selectable automatic transmission of E bit

to the line.

— CEPT: Sa6 coded remote end CRC-4 error E bit =

0 events.

— Programmable automatic and on-demand alarm

transmission:

1. Automatic transmission of remote frame alarm
to the line while in loss of frame alignment
state.

2. Automatic transmission of alarm indication
signal (AIS) to the system while in loss of frame
alignment state.

— Multiple loopback modes.
— Optional automatic line and payload loopback acti-

vate and deactivate modes.

— CEPT nailed-up connect loopback and CEPT

nailed-up broadcast transmission TS-X in TS-0

transmit mode.
— Selectable test patterns for line transmission.
— Detection of framed and unframed pseudorandom

and quasi-random test patterns.
— Programmable squelch and idle codes.

■

System interface:
— Autonomous transmit and receive system inter-

faces.
— Independent transmit and receive frame synchro-

nization input signals.
— Independent transmit and receive system interface

clock.
— 2.048 Mbits/s, 2.048 MHz concentration highway

interface (CHI) default mode.
— Optional 4.096 Mbits/s and 8.192 Mbits/s data

rates.
— Optional 4.096 MHz and 8.192 MHz frequency

system clock.
— Programmable clock edge for latching frame syn-

chronization signals.
— Programmable clock edge for latching transmit

and receive data.
— Programmable bit and byte offset.
— Programmable CHI master mode for the genera-

tion of the transmit CHI FS from internal logic with

timing derived from the receive line clock signal.

■

Digital phase comparator for clock generation in the
receive and transmit paths.

10 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Functional Description

Note:

The

Concentration Highway Interface Specification

1990 (DS90-124SMOS) defines the

transmit

as input from the system interface. This document is consistent with that definition.

, Lucent Technologies Microelectronics Group November

path as output to the system interface, and the

receive

path

RPD[1—8]

RND_RBPV[1—8]

RLCK[1—8]

TND[1—8],
TPD[1—8],
TLCK[1—8]

RECEIVE
CHANNEL [1—8]

DECODER

RECEIVE FACILITY

DATA LINK MONITOR

TRANSPARENT

TRANSMIT
CHANNEL [1—8]

ENCODER

RECEIVE
FRAMER

UNIT

(HDLC OR
FRAMING)

TRANSMIT FACILITY
DATA LINK MONITOR

TRANSPARENT

TRANSMIT

ELASTIC STORE

(2 FRAMES)

RECEIVE

SIGNALING UNIT

(DS1: ROBBED-BIT

OR

CEPT: TS16)

(HDLC OR
FRAMING)

FRAMER

UNIT

XMIT FRAMER

SYNTHESIZER

SIGNALING UNIT

(DS1: ROBBED-BIT

TCLK

MICROPROCESSOR INTERFACE

RECEIVE

CHICK

RLCK

TRANSMIT

OR

CEPT: TS16)

TRANSMIT

CONCENTRA T ION

HIGHWAY

INTERFA CE

RECEIVE

CHANNEL DIGITAL

PHASE DETECTOR

CHICK

TRANSMIT

ELASTIC STORE

(TCHI)

CHANNEL DIGITAL

PHASE DETECTOR

CONCENTRATION

TRANSMIT

RECEIVE

HIGHWAY

INTERFACE(2 FRAMES)

(RCHI)

INTERRUPTRDY_DTACKWR_DSRD_R/WALE_ASCSD[7:0]A[11:0]

MPCK

CHICK
CHIFS
TCHIDATA[1—8]
TCHIDATAB[1—8]
RFRMCK[1—8],

RFRMDATA [1—8],
RFS[1—8]

RFDL[1—8], RFDLCK[1—8]

DIV-RLCK, DIV-CHICK,
CHICK-EPLL

PLLCK[1—8]

DIV-PLLCK, DIV-CHICK,
PLLCK-EPLL

TFDL[1—8], TFDLCK[1—8]

RCHIDATA_A[1—8]
RCHIDATA_B[1—8]

TFS[1—8]

MPMODE

5-6937(F)r.4

Figure 1. TFRA08C13 Block Diagram (One of Eight Channels)

Lucent Technologies Inc. 11

Lucent Technologies Inc.

Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Functional Description

The Lucent Technologies Microelectronics Group
TFRA08C13 OCTAL T1/E1 Framer provides eight com­plete T1/E1 interfaces each consisting of a fully inte­grated, full-featured, primary rate framer with an HDLC
formatter for facility data link access. The TFRA08C13
provides glueless interconnection from a T1 or E1 ana­log line interface to devices interfacing to its CHI; for
example, the Lucent T7270 Time-Slot Interchanger or
T7115A Synchronous Protocol Data Formatter.

The line codes supported in the framer unit include
AMI, T1 B8ZS, per-channel T1 zero code suppression,
and ITU-CEPT HDB3.

The framer supports DS1 superframe (D4, T1DM,

SLC

-96) and extended superframe (ESF) formats. The
framer also supports, ITU-CEPT-E1 basic frame,
ITU-CEPT-E1 time slot 0 multiframe, and time slot 16
multiframe formats.

The receive framer monitors the following alarms: loss
of receive clock, loss of frame, alarm indication signal
(AIS), remote frame alarms, and remote multiframe
alarms. These alarms are detected as defined by the
appropriate
ommended that the LIU/Framer interface be placed in
dual rail mode, which allows the framers error/event
detector to detect and report code and BPV errors.

Performance monitoring as specified by AT&T,
and ITU is provided through counters monitoring bipo­lar violation, frame bit errors, CRC errors, errored
events, errored seconds, bursty errored seconds,
severely errored seconds, and unavailable seconds.

In-band loopback activation and deactivation codes
can be transmitted to the line via the payload or the
facility data link. In-band loopback activation and deac­tivation codes in the payload or the facility data link are
detected.

System, payload, and line loopbacks are programma­ble.

ANSI

, AT&T, and ITU standards. It is rec-

(continued)

ANSI

,

The default system interface is a 2.048 Mbits/s data
and 2.048 MHz clock CHI serial bus. This CHI interface
consists of independent transmit and receive paths.
The CHI interface can be reconfigured into several
modes: a 2.048 Mbits/s data interface and 4.096 MHz
clock interface, a 4.096 Mbits/s data interface and

4.096 MHz clock interface, a 4.096 Mbits/s data inter­face and 8.192 MHz clock interface, a 8.192 Mbits/s
data interface and 8.192 MHz clock interface, and

8.192 Mbits/s data interface.
The signaling formats supported are T1 per-channel

robbed-bit signaling (RBS), channel-24 message-ori­ented signaling (MOS), and ITU-CEPT-E1 channel­associated signaling (CAS). In the T1, RBS mode voice
and data channels are programmable. The entire pay­load can be forced into a data-only (no signaling chan­nels) mode, i.e., transparent mode by programming
one control bit. Signaling access can be through the
on-chip signaling registers or the system CHI port in
the associated signaling mode. Data and its associated
signaling information can be accessed through the CHI
in either DS1 or CEPT-E1 modes.

Extraction and insertion of the facility data link in ESF,
T1DM,
through a four-port serial interface or through a micro­processor-accessed, 64-byte FIFO either with HDLC
formatting or transparently. In
frame formats, a facility data link (FDL) stack (registers
in the framer section) is provided for FDL access. The
bit-oriented ESF data-link messages defined in
T1.403-1995 are monitored by the receive framer’s
facility data link unit. The transmit framer’s facility data
link unit overrides the XFDL-FIFO for the transmission
of the bit-oriented ESF data-link messages defined in

ANSI

The receive framer includes a two-frame (64-bytes)
elastic store buffer for jitter attenuation that performs
controlled slips and provides an indication of slip direc­tion. This buffer can be programmed to operate as a
function of the receive line clock and can be reduced to
one-frame (32-bytes) in length.

SLC

-96, or CEPT-E1 modes are provided

SLC

-96 or CEPT-E1

T1.403-1995.

ANSI

12 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Functional Description

(continued)

Accessing internal registers is done via the demultiplexed address and data bus microprocessor interface using
either the

80188 (or 80X88) interface protocol with independent read and write signals or the

Motorola

Intel

MC680X0 or M68360 interface protocol with address and data strobe signals.
The TFRA08C13 is manufactured using low-power CMOS technology and is packaged in an 352-pin plastic ball

grid array (PBGA) with 50 mils ball pitch.

RPD, RND_RBPV
RLCK

RECEIVE T1/E1 FRAME ALIGNMENT MONITOR,
REALIGNER, AND SYNC GENERATOR:

– SF: D4,

SLC

– ESF
– CEPT: BASIC FRAME, CRC-4 MULTIFRAME,

& SIGNALING MULTIFRAME

RECEIVE PERFORMANCE MONITOR:

– BIPOLAR VIOLATION ERRORS
– T1/E1 CRC ERRORS
– ERRORED EVENTS
– ERRORED SECONDS
– BURSTY ERRORED SECONDS
– SEVERELY ERRORED SECONDS
– UNAVAILABLE SECONDS

RECEIVE ALARM MONITOR:

– ANALOG LOSS OF SIGNAL
– DIGITAL LOSS OF SIGNAL
– REMOTE FRAME ALARM
– CEPT REMOTE MULTIFRAME ALARM
– ALARM INDICATION SIGNAL (AIS)
– SLIPS

-96, DDS;

RFRMCK

RECEIVE
ELASTIC

STORE

BUFFER

(2 FRAMES)

RECEIVE SLIP

MONITOR

RECEIVE SIGNALING EXTRACTER:

– DS1 ROBBED-BIT SIGNALING (RBS)
– CEPT CHANNEL ASSOCIATED AND

COMMON CHANNEL SIGNALING
– CONCENTRATION HIGHWAY ACCESS
– MICROPROCESSOR ACCESS

TRANSMIT

CONCENTRATION

HIGHWAY

INTERFACE

(RATE ADAPTER)

INTERNAL

SYSTEM CLOCK

CHIFS

TCHIDATA/B

CHICK

RECEIVE PATTE RN MONITOR:

– QUASI-RANDOM: 2
– PSEUDORANDOM: 215– 1
–

ANSI

T1.403 BIT-ORIENTED AND ESF-FDL ACTIVATE

AND DEACTIVATE LINE LOOPBACK CODES
– CEPT AUXILIARY PATTERN (CEPT = 01)
– CEPT ACTIVATE AND DEACTIVATE LOOPBACK

CODES

– CEPT Sa6 CODES

RECEIVE FACILITY DATA LINK EXTRACTER
AND MONITOR:

–

SLC

-96 FORMAT
– DDS ACCESS
–

ANSI

T1.403-1989 ESF FORMAT:

• BIT-ORIENTED MESSAGES

• MESSAGE-ORIENTED MESSAGES

20

– 1

RECEIVE FDL HDLC EXTRACTER:

– 64-byte RECEIVE FIFO
– TRANSPARENT MODE (NO HDLC FRAMING)
– MICROPROCESSOR ACCESS

Figure 2. TFRA08C13 Block Diagram: Receive Section (One of Eight Channels)

RFDLCK

RFDL

5-6965(F)

Lucent Technologies Inc. 13

Lucent Technologies Inc.

Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Functional Description

TLCK
TND, TPD

LINE FORMAT

ENCODER

(AMI; B8ZS; HDB3)

TRANSMIT PATTERN GENERATOR:

– QUASI-RANDOM: 2
– PSEUDORANDOM: 2
–

T1.403 BIT-ORIENTED AND ESF-FDL

ANSI

ACTIVATE AND DEACTIVATE LINE

LOOPBACK CODES
– CEPT AUXILIARY PATTERN (CEPT = 01)
– CEPT ACTIVATE AND DEACTIVATE

LOOPBACK CODES
– CEPT Sa6 CODES

TRANSMIT

CRC

GENERATOR:

– ESF
– CEPT

20

– 1

15

(continued)

– 1

TRANSMIT T1/E1 FRAME FORMATTER,
AND FRAME SYNC GENERATOR:

– SF: D4,

SUPERFRAME
– ESF
– CEPT: BASIC FRAME, CRC-4

MULTIFRAME, AND SIGNALING
MULTIFRAME

– TRANSPARENT FRAMING

-96, DDS; SIGNALING

SLC

TRANSMIT SIGNALING INSERTER:

– DS1 ROBBED-BIT SIGNALING (RBS)
– CEPT CHANNEL ASSOCIATED AND

COMMON-CHANNEL SIGNALING
– CONCENTRATION HIGHWAY ACCESS
– MICROPROCESSOR ACCESS

TRANSMIT ELASTIC

STORE BUFFER

(2 FRAMES)

TRANSMIT FACILITY DATA LINK
INSERTER:

-96 FORMAT

–

SLC

– DDS ACCESS
–

T1.403-1989 ESF FORMAT:

ANSI

• BIT-ORIENTED MESSAGES

• MESSAGE-ORIENTED MESSAGES

TRANSMIT FDL HDLC INSERTER:

– 64-byte TRANSMIT FIFO
– TRANSPARENT MODE

(NO HDLC FRAMING)

– MICROPROCESSOR A CCESS

RECEIVE CONCENTRATION

HIGHWAY INTERFACE

(RATE ADAPTER)

TFDL

TFDLCK

CHICK

CHIFS

RCHIDATA/B

TRANSMIT ALARM MONITOR:

– LOSS OF SYSTEM BIFRAME ALIGNMENT
– SYSTEM ALARM INDICATION SIGNAL (AIS)

Figure 3. TFRA08C13 Block Diagram: Transmit Section (One of Eight Channels)

5-6964(F)

14 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Pin Information

The package type and pin assignment for the TFRA08C13 is illustrated in Figure 4.

AF

AE
AD
AC
AB
AA

Y
W
V
U
T
R
P
N
M

L
K

J
H

G
F
E

D
C

B
A

TFRA08CF13

352-PIN PBGA

2322212019181716151413121110987654321

262524

A1 BALL

CORNER

5-6966(F)

Figure 4. Pin Assignment

Lucent Technologies Inc. 15

Lucent Technologies Inc.

Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Pin Information

(continued)

Table 1. Pin Assignments for 352-Pin PBGA by Pin Number Order

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

A1 NC B13 NC C25 NC F3 RFRMCLK1
A2 NC B14 NC C26 NC F4 NC
A3 NC B15 NC D1 TCHIDATA1 F23 NC
A4 RCHIDATAB1 B16 NC D2 TFS1 F24 NC
A5 RND8 B17 NC D3 TCHIDATAB1 F25 LOPLLCLK
A6 NC B18 3-STATE

D4

NC

F26 DS1/CEPT7
A7 RCHIDATA8 B19 RND7 D5 PLLCK1 G1 TPD1
A8 TSSFS8 B20 RCHIDATAB7 D6 NC G2 TND1
A9 TCHIDATAB8 B21 TCRCMFS7 D7 PLLCK8 G3 V

A10 RCRCMFS8 B22 TCHIDATA7 D8

TFDL8

G4 RFRMDATA1

SS

A11 RFRMCK8 B23 RCRCMFS7 D9 NC G23 LORLCK
A12 TPD8 B24 RFS7 D10 RFDLCK8 G24 RLCK7
A13 V
A14 V

SSD
DDD

B25 NC D11 NC G25 DIV-PLLCK

B26 NC D12 RFRMDATA8 G26 PLLCK-EPLL
A15 NC C1 TSSFS1 D13 NC H1 NC
A16 NC C2 TCRCMFS1 D14 NC H2 RLCK1
A17 NC C3
A18 V

SS

A19 CHIFS C5

NC

D15 NC H3 TCK

C4 NC D16 NC H4 NC

RCHIDATA1

D17 V

DDA

H23 DIV-RLCK

A20 PLLCK7 C6 RND1 D18 CHICK H24 CHICK-EPLL

V

A21 RCHIDATA7 C7
A22 TSSFS7 C8 RCHIDATAB

SS

D19 NC H25 RND6

8

D20 TFDLCK7 H26 DIV-CHICK
A23 RFDL7 C9 TCRCMFS8 D21 NC J1 TDI
A24 RSSFS7 C10 TCHIDATA8 D22 TCHIDATAB7 J2 TRST
A25 RFRMDATA7 C11

RSSFS8

D23 NC J3 V

SS

A26 NC C12 TLCK8 D24 RFRMCLK7 J4 DS1/CEPT1

B1 TFDLCK1 C13

NC

B2

C14 NC D26
B3 TFDL1 C15 NC E1
B4 RPD1 C16 NC E2
B5 RPD8 C17 V
B6 NC C18 NC E4
B7 TFDLCK8 C19 RESET
B8 TFS8 C20 RPD7 E24

RLCK8

SSA

D25 NC J23 NC

E3

NC
RSSFS1
RFDL1
RCRCMFS1
RFDLCK1

J24 DIV-CHICK
J25 NC
J26 RPD6

K1 TDO
K2 TMS

E23 TLCK7 K3 RPD2

V

DD

K4 V

DD

B9 RFDL8 C21 TFDL7 E25 TPD7 K23 PLLCK6

B10 RFS8 C22

TFS7

E26 TND7 K24 V

B11 TND8 C23 RFDLCK7 F1 TLCK1 K25 V

SS
DD

B12 DS1/CEPT8 C24 NC F2 RFS1 K26 NC

L1 PLLCK2 R25 TND6 Y23 TCHIDATAB5 AC19 TPD4
L2 RND2 R26 TLCK6 Y24 TFDL5 AC20 DS1/CEPT

5

16 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Pin Information

Table 1. Pin Assignments for 352-Pin PBGA by Pin Number Order

(continued)

(continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

L3 RCHIDATA2 T1 RFRMCLK2 Y25 TCRCMFS5 AC21 NC

L4 NC T2 RFS2 Y26 TFDLCK5 AC22 NC
L23 NC T3 NC AA1 TSSFS3 AC23 NC
L24 NC T4 NC AA2 TFDLCK3 AC24 RFRMDATA5
L25 TFDLCK6 T23 NC AA3 RFDL3 AC25 RFRMCLK5
L26 RCHIDATA6 T24 RFRMCLK6 AA4 NC AC26 RFS5

M1 RCHIDATAB2 T25 DS1/CEPT
M2 V

DD

T26 TPD6 AA24 TFS5 AD2 RFRMDATA3

6AA23NC AD1NC

M3 TSSFS2 U1 TPD2 AA25 TCHIDATA5 AD3 NC
M4 TFDLCK2 U2 TND2 AA26 TSSFS5 AD4 TPD3

M23 RCHIDATAB6 U3 V

DD

AB1 TCHIDATA3 AD5 A1
M24 TFDL6 U4 RLCK2 AB2 TCHIDATAB3 AD6 A4
M25 TFS6 U23 ALE

_AS AB3 RFS3 AD7 A8

M26 TCRCMFS6 U24 RLCK6 AB4 RCRCMFS3 AD8 INTERRUPT

N1 TCRCMFS2 U25 CS
N2 TFDL2 U26 RD

_RW AB24 RFDLCK5 AD10 RCHIDATA4

N3 RFDL2 V1 DS1/CEPT

2 AB25 RSSFS5 AD11 TSSFS4

AB23 RCRCMFS5 AD9 RND4

N4 NC V2 NC AB26 RFDL5 AD12 AD0
N23 RFDL6 V3 PLLCK3 AC1 RSSFS3 AD13 AD4
N24 TSSFS6 V4 NC AC2 RFDLCK3 AD14 NC
N25 RFDLCK6 V23 RCHIDATAB5 AC3 NC AD15 NC
N26 TCHIDATA6 V24 WR

_DS AC4 NC AD16 RCRCMFS4
P1 TCHIDATA2 V25 RND5 AC5 A0 AD17 RFRMCLK4
P2 TFS2 V26 RDY_DTACK

AC6 NC AD18 V

DD

P3 RCRCMFS2 W1 RPD3 AC7 A3 AD19 DS1/CEP T4
P4 TCHIDATAB2 W2 RND3 AC8 NC AD20 V

SS

P23 NC W3 TFDL3 AC9 A10 AD21 NC
P24 TCHIDATAB6 W4 RCHIDATAB3 AC10 PLLCK4 AD22 NC
P25 RFRMDATA6 W23 NC AC11 NC AD23 NC
P26 RSSFS6 W24 RPD5 AC12 TCHIDATAB4 AD24 NC

R1 RSSFS2 W25 RCHIDATA5 AC13 NC AD25 NC
R2 RFDLCK2 W26 PLLCK5 AC14 AD2 AD26 V

SS

R3 RFRMDATA2 Y1 RCHIDATA3 AC15 RFDL4 AE1 NC
R4 TLCK2 Y2 V

SS

AC16 NC AE2 NC
R23 RFS6 Y3 TFS3 AC17 RFS4 AE3 TLCK3
R24 RCRCMFS6 Y4 TCRCMFS3 AC18 NC AE4 TND3

Lucent Technologies Inc. 17

Lucent Technologies Inc.

Preliminary Data Sheet

pply

y

g

y

g

g

y

g

g

g

g

TFRA08C13 OCTA L T1/E1 Framer October 2000

Pin Information

Table 1. Pin Assignments for 352-Pin PBGA by Pin Number Order

(continued)

(continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

AE5 DS1/CEPT

3 AE17 RFDLCK4 AF3 V

DD

AF15 AD6
AE6 A2 AE18 RFRMDATA4 AF4 RLCK3 AF16 NC
AE7 A6 AE19 NC AF5 V

DD

AF17 RSSFS4
AE8 A9 AE20 TND4 AF6 A5 AF18 NC
AE9 SECOND AE21 V

SS

AF7 A7 AF19 TLCK4
AE10 MPCLK AE22 TPD5 AF8 A11 AF20 RLCK4
AE11 RCHIDATAB4 AE23 NC AF9 MPMODE AF21 RLCK5
AE12 TFDLCK4 AE24 NC AF10 RPD4 AF22 TND5
AE13 TFS4 AE25 NC AF11 TFDL4 AF23 NC
AE14 AD1 AE26 TLCK5 AF12 TCRCMFS4 AF24 NC
AE15 AD5 AF1 NC AF13 TCHIDATA4 AF25 NC
AE16 AD7 AF2 RFRMCLK3 AF14 AD3 AF26 NC

Table 2 shows the list of the TFRA08C13 pins and a functional description for each.

Table 2. Pin Descriptions

Pins Symbol Type

DD

AF3, AF5,

V

AD18, K25,

*

3.3 V Power Su

P

with a 0.1 µF capacitor to V

E24, K4,

M2, U3

AD20, AD26,

SS

V

G

Ground.

AE21, G3,

K24,

A18, J3, C7,

Y2

D17 V

DDA

3.3 V Quiet Analo

P

0.1 µF capacitor to V
this pin should be isolated from the 3.3 V power plane with an inductive

bead.
C17 V
A14 V

SSA
DDD

3.3 V Quiet Analo

G

3.3 V Quiet Di

P

0.1 µF capacitor to V

this pin should be isolated from the 3.3 V power plane with an inductive

bead.
A13 V
B18

3-STATE

SSD

3.3 V Quiet Di

G

u

3-State (Active-Low).

I

into a hi
C19

RESET

†

u

Reset (Active-Low).

I

entire device.

* Iu indicates an internal pull-up, Id indicates an internal pull-down.
† After RESET
‡ Asserting this pin low will initially force RDY to a low state.

is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

.

3.3 V ± 5%. Each of th ese pi ns m ust be b

Power Supply.

SSA

, as close to the pin as possible. In addition,

Ground.

ital Power Supply.

SSD

, as close to the pin as possible. In addition,

ital Ground.

Assertin

h-impedance state.

Assertin

Description

SS

, as close to the pin as possible.

This pin must be b

This pin must be b

passed with a

passed with a

this pin low forces the channel outputs

this pin low resets all channels on the

passed

18 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet

g

y

g

g

(N)

g

g

y

y

y cy

p

g

y (

(

)

g

g

p

g

y

y (

g

g

g

g

g

(

]

]

]

]

]

]

]

]

October 2000 TFRA08C13 OCTAL T1/E1 Framer

Pin Information

Table 2. Pin Descriptions

Pins

AE9 SECOND

(continued)

(continued)

Symbol Type

O

*

Second Pulse.

duration of the pulse is one RLCK c
si

nal (RLCK1) is the default clock source for the internal second pulse
timer. The internal second pulse is retimed in the individual framer sec­tions with their correspondin
LORLCK_
is used as the clock si
The second pulse is used for performance monitorin

D18

CHICK I

CHI Clock.

4.096 MHz, or 8.192 MHz.

A19

CHIFS I

CHI Frame S

width must be a minimum of one clock period of CHICK and a maxi­mum of a 50% dut

H24

CHICK-EPLL O

Error Phase-Lock Loo

phase difference between DIV-CHICK and DIV-RLCK as detected from
the internal PLL circuitr

GREG8) (008

G25

DIV-PLLCK O

Divided-Down PLLCK Clock.

from the PLLCK input si
Re

ister (FRM_PR45) (Y8D)).

G26

PLLCK-EPLL O

Error Phase-Lock Loo

phase difference between DIV-PLLCK and DIV-CHICK as detected b
the internal PLL circuitr

H23

DIV-RLCK O

Divided-Down Receive Line Clock.

the recovered receive line interface unit clock or the RLCK input si
The choice of which receive framer clock to use is defined in Table 66.
Global Control Re

H26, J24

DIV-CHICK O

Divided-Down CHI Clock.

CHI CLOCK input si

GREG8) (008)).

u

J4

V1

AE5
AD19
AC20

T25

F26

B12

* Iu indicates an internal pull-up, Id indicates an internal pull-down.
† After RESET
‡ Asserting this pin low will initially force RDY to a low state.

DS1/CEPT
DS1/CEPT
DS1/CEPT
DS1/CEPT
DS1/CEPT
DS1/CEPT
DS1/CEPT
DS1/CEPT

is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

[1
[2
[3
[4
[5
[6
[7
[8

I

DS1/CEPT.

Strap to V

Description

A one second timer with an active-hi

h pulse. The

cle. Framer_1’s receive line clock

receive line clock signal RLCK. When

is active, then Framer_(N + 1)’s receive line clock signal

nal source for the internal second pulse timer.

.

2.048 MHz,

nc.

CHI 8 kHz input frame s

nchronization pulse. Pulse

cle square wave.

Signal.

The error si

nal proportional to the

see Table 66. Global Control Register

32 kHz or 8 kHz clock signal derived

nal (see Table 150. CHI Common Control

Signal.

The error si

nal proportional to the

refer to the Phase-Lock Loop section).

8 kHz clock si

nal derived from

ister (GREG8) (008).

8 kHz clock si

nal derived from the transmit

nal (see Table 66. Global Control Register

Strap to V

to enable CEPT operation in the framer unit.

SS

to enable DS1 operation in the framer unit.

DD

nal.

Lucent Technologies Inc. 19

Lucent Technologies Inc.

Preliminary Data Sheet

]

g

g

q

q

(

]

]

]

]

]

]

]

gg

g

(

]

g

]

]

]

]

]

]

]

]

g

g

]

]

]

]

]

]

]

]

g

g

g

g

]

]

]

]

]

]

]

TFRA08C13 OCTA L T1/E1 Framer October 2000

Pin Information

Table 2. Pin Descriptions

Pins

D5 PLLCK
L1 PLLCK
V3 PLLCK

AC10 PLLCK

W26 PLLCK

K23 PLLCK
A20 PLLCK

D7 PLLCK

F25 LOPLLCK O

F1 TLCK
R4 TLCK

AE3 TLCK
AF19 TLCK
AE26 TLCK

R26 TLCK

E23 TLCK

C12 TLCK

G1 TPD
U1 TPD

AD4 TPD
AC19 TPD
AE22 TPD

T26 TPD

E25 TPD

A12 TPD

G2 TND
U2 TND

AE4 TND
AE20 TND
AF22 TND

R25 TND

E26 TND

B11 TND

* Iu indicates an internal pull-up, Id indicates an internal pull-down.
† After RESET
‡ Asserting this pin low will initially force RDY to a low state.

is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

(continued)

(continued)

Symbol Type

[1
[2
[3
[4
[5
[6
[7
[8

[1
[2
[3
[4
[5
[6
[7

[8
[1
[2
[3
[4
[5
[6
[7
[8

[1
[2
[3
[4
[5
[6
[7
[8

I

O

O

O

*

Transmit Framer Phase-Locked Line Interface Clock.

used to time the transmit framer. This si
CHICK clock si
fre

uency signal (1.544 MHz) or a high frequency signal (6.176 MHz).

In CEPT frame formats, PLLCK can be a low-fre

2.048 MHz) or a high-frequency signal (8.192 MHz).

Loss of PLLCK Clock.

clock does not to
250 µs after the first ed
ister

GREG8) (008)).

Transmit Framer Line Interface Clock.

2.048 MHz output signal from the transmit framer
chan

es on the rising edge of TLCK.

Transmit Line Interface Positive-Rail Data.

framer positive NRZ output data. Data chan
TLCK. In the sin

Transmit Line Interface Ne

mit framer ne
of TLCK. In the sin

Description

Clock signal

nal must be phase-locked to

nal. In DS1 frame formats, PLLCK can be a low-

uency signal

This pin is asserted high when the PLLCK

le for a 250 µs interval. This pin is deasserted

e of PLLCK (see Table 66. Global Control Reg-

Optional 1.544 MHz DS1 or

. TND and TPD data

This signal is the transmit
es on the rising edge of

le-rail mode, TPD = transmit framer data.

ative-Rail Data.

ative NRZ output data. Data changes on the rising edge

le-rail mode, TND = 0.

This si

nal is the trans-

20 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet

]

y

g

g

]

]

]

]

]

]

]

]

y

g

g

]

]

]

]

]

]

]

]

y

y

y

g

g

]

]

]

]

]

]

]

]

y

]

]

]

]

]

]

]

October 2000 TFRA08C13 OCTAL T1/E1 Framer

Pin Information

Table 2. Pin Descriptions

Pins

D2
P2

Y3
AE13
AA24

M25

C22

B8

B1

M4

AA2

AE12

Y26
L25
D20

B7

B3

N2

W3

AF11

Y24

M24

C21

D8

C5

L3

Y1

AD10

W25

L26
A21

A7

* Iu indicates an internal pull-up, Id indicates an internal pull-down.
† After RESET
‡ Asserting this pin low will initially force RDY to a low state.

is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

(continued)

(continued)

Symbol Type

TFS[1
TFS[2
TFS[3
TFS[4
TFS[5
TFS[6
TFS[7

TFS[8
TFDLCK[1
TFDLCK[2
TFDLCK[3
TFDLCK[4
TFDLCK[5
TFDLCK[6
TFDLCK[7
TFDLCK[8

TFDL[1
TFDL[2
TFDL[3
TFDL[4
TFDL[5
TFDL[6
TFDL[7

TFDL[8
RCHIDATA[1
RCHIDATA[2
RCHIDATA[3
RCHIDATA[4
RCHIDATA[5
RCHIDATA[6
RCHIDATA[7
RCHIDATA[8

*

O

Transmit Framer Frame S

nization pulse in the transmit framer. This si

O

Transmit Facilit

this is an 8 kHz clock si
latches data link bits on the fallin

I

Transmit Facilit

stream inserted into the transmit line data stream b
framer. In DS1-DDS with data link access, this is an 8 kbits/s si
otherwise, 4 kbits/s. In the CEPT frame format, TFDL can be pro-

rammed to one of the XSa bits of the NOT FAS frame time slot 0.

I

Receive CHI Data.

4.096 Mbits/s, or 8.192 Mbits/s.

Description

nc.

This si

Data Link Clock.

nal; otherwise, 4 kHz. The transmit frame

edge of TFDLCK.

Data Link.

Optional serial input facilit

Serial input s

nal is the 8 kHz frame synchro-

nal is active-high.

In DS1-DDS with data link access,

data link bit

the transmit

nal;

stem data at 2.048 Mbits/s,

Lucent Technologies Inc. 21

Lucent Technologies Inc.

Preliminary Data Sheet

]

y

]

]

]

]

]

]

]

gg

g

g

]

]

]

]

]

]

]

]

]

]

]

]

]

]

]

]

]

g

g

]

]

[4]

]

]

]

]

TFRA08C13 OCTA L T1/E1 Framer October 2000

Pin Information

Table 2. Pin Descriptions

Pins

A4 RCHIDATAB
M1
W4

AE11

V23
M23
B20

C8

G23

(continued)

(continued)

Symbol Type

[1

RCHIDATAB
RCHIDATAB
RCHIDATAB
RCHIDATAB
RCHIDATAB
RCHIDATAB
RCHIDATAB

[2
[3
[4
[5
[6
[7
[8

LORLCK O

*

I

Receive CHI Data B.

4.096 Mbits/s, or 8.192 Mbits/s.

Loss of Receive Clock.

in the receive framer does not to
asserted, this si

66. Global Control Re

Receive Framer Line Interface Clock.

H2
U4

AF4
AF20
AF21

U24

G24

C13

RLCK[1
RLCK[2
RLCK[3
RLCK[4
RLCK[5
RLCK[6
RLCK[7

RLCK[8
B4 RPD
K3 RPD

W1 RPD

AF10 RPD

W24 RPD

J26 RPD

C20 RPD

B5 RP8

C6 RND

L2 RND

W2 RND

[1
[2
[3
[4
[5
[6
[7
1
[1
[2
[3

I

2.048 MHz input clock signal used by the receive framer to latch RPD
and RND data.

Receive Positive-Rail Data.

I

of RLCK. Data rates: DS1-1.544 Mbits/s; CEPT-2.048 Mbits/s. Optional
single-rail NRZ receive data latched by the rising edge of RLCK.

Receive Negative-Rail Data.

I

latched by the rising edge of RLCK. Data rates: DS1-1.544 Mbits/s;
CEPT-2.048 Mbits/s.
bipolar violation counter increments once for each risin

AD9 RN
V25 RND
H25 RND
B19 RND

A5 RND

* Iu indicates an internal pull-up, Id indicates an internal pull-down.
† After RESET
‡ Asserting this pin low will initially force RDY to a low state.

is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

[5
[6
[7
[8

Description

Serial input s

stem data at 2.048 Mbits/s,

This pin is asserted high (logic 1) when RLCK

le for a 250 µs interval. Once

nal is deasserted on the first edge of RLCK (See T able

ister (GREG8) (008)).

This is the 1.544 MHz DS1 or

NRZ serial data latched by the rising edge

Nonreturn-to-zero (NRZ) serial data

In the sin

le-rail mode, when RND = 1 the receive

edge of RLCK.

22 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet

]

g

g

g

]

]

]

]

]

]

]

]

g

g

]

]

]

]

]

]

]

]

y

g

g

g

g

]

]

]

]

]

]

]

]

y

g

g

]

]

]

]

]

]

]

October 2000 TFRA08C13 OCTAL T1/E1 Framer

Pin Information

Table 2. Pin Descriptions

Pins

F3
T1

AF2
AD17
AC25

T24

D24

A11

G4
R3

AD2

AE18

AC24

P25

A25

D12

F2
T2

AB3
AC17
AC26

R23

B24

B10

E4
R2

AC2
AE17
AB24

N25
C23
D10

* Iu indicates an internal pull-up, Id indicates an internal pull-down.
† After RESET
‡ Asserting this pin low will initially force RDY to a low state.

is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

(continued)

(continued)

Symbol Type

RFRMCK[1
RFRMCK[2

RFRMCK[3
RFRMCK[4
RFRMCK[5
RFRMCK[6
RFRMCK[7

RFRMCK[8
RFRMDATA[1
RFRMDATA[2
RFRMDATA[3
RFRMDATA[4
RFRMDATA[5
RFRMDATA[6
RFRMDATA[7
RFRMDATA[8

RFS[1
RFS[2
RFS[3
RFS[4
RFS[5
RFS[6
RFS[7

RFS[8
RFDLCK[1
RFDLCK[2
RFDLCK[3
RFDLCK[4
RFDLCK[5
RFDLCK[6
RFDLCK[7
RFDLCK[8

*

O

Receive Framer Clock.

clock out the receive framer output si
the recovered receive line clock si

O

Receive Framer Data.

receive elastic store. Durin
forced to 1.

O

Receive Frame S

chronization pulse
frame ali
si

nal is forced to 0.

O

Receive Facilit

this is an 8 k Hz cloc k si
receive data link bit chan

Description

Output receive framer clock si

nal used to

nals. In normal operation, this is

nal.

This si

nal is the decoded data input to the

loss of frame alignment, this signal is

nc.

This active-hi

h signal is the 8 kHz frame syn-

enerated by the receive framer. During loss of

nment and signaling superframe or multiframe alignment, this

Data Link Clock.

In DS1-DDS with data link access,

nal. Otherwise, t his is a 4 kHz cl ock signal. The

es on the falling edge of RFDLCK.

Lucent Technologies Inc. 23

Lucent Technologies Inc.

Preliminary Data Sheet

]

y

y

y

g

g

g

g

]

]

]

]

]

]

]

]

y

g

]

]

]

]

]

]

]

]

y

g

]

]

]

]

]

]

]

]

g

g

g

]

]

]

]

]

]

]

TFRA08C13 OCTA L T1/E1 Framer October 2000

Pin Information

Table 2. Pin Descriptions

Pins

E2

N3

AA3
AC15
AB26

N23

A23

B9

D1

P1

AB1
AF13
AA25

N26

B22

C10

D3

P4

AB2
AC12

Y23

P24

D22

A9
E1 RSSFS

R1 RSSFS

AC1 RSSFS
AF17 RSSFS
AB25 RSSFS

P26 RSSFS

A24 RSSFS

C11 RSSFS

* Iu indicates an internal pull-up, Id indicates an internal pull-down.
† After RESET
‡ Asserting this pin low will initially force RDY to a low state.

is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

(continued)

(continued)

Symbol Type

RFDL[1
RFDL[2
RFDL[3
RFDL[4
RFDL[5
RFDL[6
RFDL[7

RFDL[8
TCHIDATA[1
TCHIDATA[2
TCHIDATA[3
TCHIDATA[4
TCHIDATA[5
TCHIDATA[6
TCHIDATA[7
TCHIDATA[8

TCHIDATAB[1
TCHIDATAB[2
TCHIDATAB[3
TCHIDATAB[4
TCHIDATAB[5
TCHIDATAB[6
TCHIDATAB[7
TCHIDATAB[8

[1
[2
[3
[4
[5
[6
[7
[8

*

O

Receive Facilit

extracted from the receive line data stream b
DS1-DDS with data link access, this is an 8 kbits/s si
4 kbits/s. In the CEPT frame format, RFDL can be pro
of the RSa bits of the NOT FAS frame TS0. Durin
ment, this si

O

Transmit CHI Data.

4.096 Mbits/s, or 8.192 Mbits/s. This port is forced into a hi
ance state for all inactive time slots.

O

Transmit CHI Data B.

4.096 Mbits/s, or 8.192 Mbits/s. This port is forced into a hi
ance state for all inactive time slots.

O

Receive Framer Si

is the CEP T si
the receive framer.

Description

Data Link.

Serial output facilit

data link bit stream

the receive framer. In

nal; otherwise,

rammed to one

loss of frame align-

nal is 1.

Serial output s

stem data at 2.048 Mbits/s,

h-imped-

Serial output s

stem data at 2.048 Mbits/s,

h-imped-

naling Superframe Sync.

This active-hi

h signal

naling superframe (multiframe) synchronization pulse in

24 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet

]

y

g

y

]

]

]

]

]

]

]

]

g

g

g

g

]

]

]

]

]

]

]

]

y

g

y

g

]

]

]

]

]

]

]

(

g

g

October 2000 TFRA08C13 OCTAL T1/E1 Framer

Pin Information

Table 2. Pin Descriptions

E3 RCRCMFS
P3 RCRCMFS

AB4 RCRCMFS

AD16 RCRCMFS

AB23 RCRCMFS

R24 RCRCMFS
B23 RCRCMFS
A10 RCRCMFS

C1 TSSFS
M3 TSSFS

AA1 TSSFS
AD11 TSSFS
AA26 TSSFS

N24 TSSFS

A22 TSSFS

A8 TSSFS
C2 TCRCMFS
N1 TCRC MFS
Y4 TCRCMFS

AF12 TCRCMFS

Y25 TCRCMFS

M26 TCRCMFS

B21 TCRCMFS

C9 TCRC MFS

AF9

(continued)

(continued)

[1
[2
[3
[4
[5
[6
[7
[8

MPMODE

[1
[2
[3
[4
[5
[6
[7
[8

[1
[2
[3
[4
[5
[6
[7
[8

O

Receive Framer CRC-4 Multiframe S

the CEPT CRC-4 multiframe s
framer.

Transmit Framer Si

O

CEPT si
transmit framer. This si

O

Transmit Framer CRC-4 Multiframe S

CRC-4 submultiframe s
si

nal is active-high.

u

MPMODE.

I

sor protocol (MODE1). Strap to V
processor protocol (MODE3).

U26

RD

Read

Active-Low).

_R/W I

the data bus with the contents of the addressed re

Read/Write

low.
hi

h for read accesses; this pin is asserted low for write accesses.

* Iu indicates an internal pull-up, Id indicates an internal pull-down.
† After RESET
‡ Asserting this pin low will initially force RDY to a low state.

is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

nc.

This active-hi

h signal is

nchronization pulse in the receive

naling Superframe Sync.

This si

nal is the

naling superframe (multiframe) synchronization pulse in the

nal is active-high.

nc.

This si

nal is the CEPT

nchronization pulse in the transmit framer. This

Strap to ground to enable the

DD

In the

Intel

interface mode, the TFRA08C13 drives

Motorola

to enable the

68360 microproces-

Intel

80X86/88 micro-

ister while RD is

.

In the

Motorola

interface mode, this signal is asserted

Lucent Technologies Inc. 25

Lucent Technologies Inc.

Preliminary Data Sheet

(

g

g

(

g

g

p

g

(

p

p

g

TFRA08C13 OCTA L T1/E1 Framer October 2000

Pin Information

Table 2. Pin Descriptions

Pins

V24 WR

(continued)

(continued)

Symbol Type

_DS I

*

Write

Active-Low).

bus is latched into the addressed re
si

nal applied to WR.

Data Strobe

R/W

is low (write), the value present on the data bus is latched into the
addressed re
when AS
bus with the contents of the addressed re

U25

CS

‡

I

Chi

Select (Active-Low).

asserted low to initiate a read or write access and kept low for the dura­tion of the access; assertin
ance state into a 0 state.

U23

ALE

Address Strobe

_AS I

must be asserted low to initiate a read or write access and kept low for
the duration of the access.

AD12

D0 I/O

AE14 D1

Micro

rocessor Data Bus.

write accesses. 3-stated output.

AC14 D2
AF14 D3
AD13 D4
AE15 D5
AF15 D6
AE16 D7

AC5 A0
AD5 A1

I

Micro

nal re

rocessor Address Bus.

isters.

AE6 A2
AC7 A3
AD6 A4
AF6 A5
AE7 A6
AF7 A7
AD7 A8
AE8 A9
AC9 A10
AF8 A11

* Iu indicates an internal pull-up, Id indicates an internal pull-down.
† After RESET
‡ Asserting this pin low will initially force RDY to a low state.

is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

Description

Intel

In the

mode, the value present on the data

ister on the positive edge of the

Active-Low).

In the

Motorola

mode, when AS is low and

ister on the positive edge of the signal applied to DS;

is low and R/W is high (read), the TFRA08C13 drives the data

ister while DS is low.

In the

Intel

interface mode, this pin must be

CS low forces RDY out of its high-imped-

Active-Low).

In the

Motorola

interface mode, this pin

Bidirectional data bus used for read and

Address bus used to access the inter-

26 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet

p

g

g

g

y

g

y

g

ge (

g

p

g

y

g

y

y

g

g

g

y

y

y

October 2000 TFRA08C13 OCTAL T1/E1 Framer

Pin Information

Table 2. Pin Descriptions

Pins

AD8

(continued)

(continued)

Symbol Type

INTERRUPT O

*

Interru

rupt condition/event has been
are maskable throu
OR or wired-AND to an
Re

ister (GREG4) (004)).

V26

RDY_DTACK

O

Read

.

In the
the completion of a read or write access; this pin is forced into a hi
impedance state while CS
Data Transfer Acknowled
mode,

DTACK

write access;

u

AE10 MPCK I

Microprocessor Clock.

enerate the READY signal.

K1 TDO O

JTAG Data Out

TCK from the boundar

u

J1 TDI I

JTAG Data Input.

for the boundar

u

H3 TCK I

K2 TMS I

JTAG Clock Input.

lo

ic.

u

JTAG Mode Select (Active-High).

are sampled on the risin
scan TAP controller to control boundar

d

J2 TRST

JT AG Reset Input (Active-Low).

I

initialize/reset the boundar

* Iu indicates an internal pull-up, Id indicates an internal pull-down.
† After RESET
‡ Asserting this pin low will initially force RDY to a low state.

is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

Description

t.

INTERRUPT is asserted hi

h/low indicating an internal inter-

enerated. Interrupt events/conditions

h the control registers. This output can be wired-

other logic output (see Table 64Global Control

Intel

interface mode, this pin is asserted high to indicate

is high.

Active-Low). In the

Motorola

is asserted low to indicate the completion of a read or

DTACK

is 1 otherwise.

Microprocessor clock used in the

ut.

Serial output data sampled on the fallin

-scan test circuitry.

Serial input data sampled on the risin

-scan test circuit ry.
TCK provides the clock for the boundar

The si

nal values received at TMS

edge of TCK and decoded by the boundary-

-scan test operations.

Assert this pin low to as

-scan test logic.

h-

interface

Intel

mode to

edge of

edge of TCK

-scan test

nchronous ly

Lucent Technologies Inc. 27

Lucent Technologies Inc.

Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Pin Information

Table 2. Pin Descriptions

Pins

A1, A2, A3,
A6, A15,
A16, A17,
A26, B2, B6,
B13, B14,
B15, B16,
B17, B25,
B26, C3,
C4, C14,
C15, C16,
C18, C24,
C25, C26,
D4, D6, D9,
D11, D13,
D14, D15,
D16, D19,
D21, D23
D25, D26,
F4, F23,
F24, H1,
H4, J23,
J25, K26,
L4, L23,
L24, N4,
P23, T3,
T4 T23,
V2, V4,
W23, AA4,
AA23, AC3,
AC4, AC6,
AC8, AC11,
AC13, AC16,
AC18, AC21,
AC22, AC23,
AD1, AD3,
AD14, AD15,
AD21, AD22,
AD23, AD24,
AD25, AE1,
AE2, AE19,
AE23, AE24,
AE25, AF1,
AF16, AF18,
AF23, AF24,
AF25, AF26

* Iu indicates an internal pull-up, Id indicates an internal pull-down.
† After RESET
‡ Asserting this pin low will initially force RDY to a low state.

is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

(continued)

(continued)

Symbol Type

NC —

*

No Connection.

Description

28 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

LIU-Framer Interface

LIU-Framer Physical Interface

The transmit framer-LIU interface for the TFRA08C13 consists of the TND, TPD, and TLCK pins. In normal opera­tions, TND , TPD, and TLCK are driven from the transmit framer and are connected to an external transmit line inter­face. The receive framer-LIU interface for the TFRA08C13 consists of the RPD, RND , and RLCK internal signals. In
normal operations, RND, RPD, and RLCK are sourced from an external receive line interface unit and are directly
connected to the receive framer. Figure 5 illustrates the interfaces of the transmit and receive framer units.

TRANSMIT

HDLC

FACILITY DATA

LINK

INTERFACE

TFDLCK

TFDL

TTIP

TRING

LINE INTERFACE

RTIP

RRING

EXTERNAL

TRANSMIT LINE

INTERFACE

UNIT

(XLIU)

EXTERNAL

RECEIVE LINE

INTERFACE

UNIT

(RLIU)

RLCK
RND
RPD

TLCK
TND
TPD

PLLCK

RECEIVE HDLC

FACILITY DATA

LINK INTERFACE

RECEIVE

FRAMER
(RFRMR)

TRANSMIT

FRAMER
(XFRMR)

CONCENTRATION

RFRMCK

TRANSMIT

HIGHWAY

INTERFACE

(XCHI)

Figure 5. Block Diagram of Framer Line Interface

RECEIVE

CONCENTRATION

HIGHWAY

INTERFACE

(RCHI)

RFDLCK
RFDL

RCHIDATA
RCHIDATAB

CHIFS
CHICK

SYSTEM
INTERFACE

TCHIDATA

TCHIDATAB

5-7169(F)

Lucent Technologies Inc. 29

Lucent Technologies Inc.

Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

LIU-Framer Interface

(continued)

Figure 6 shows the timing requirements for the transmit and receive framer interfaces in the LIU-bypass mode.

BIT 0 OF FRM_PR45

IS THE HFLF BIT

HFLF = 0 HFLF = 1

162 nst1-DS1 648 ns
122 ns

PLLCK

TLCK

TND, TPD

RLCK

RND, RPD

t2r-f

t1

t1-CEPT 488 ns

t2f-r

t3

t4

t5

t6

t7

t2r-f: t2f-r: PLLCK TO TLCK DELAY = 50 ns
t3-DS1 = 648 ns
t3-CEPT = 488 ns

t4 = TLCK TO VALID TPD, TND = 30 ns

t5-DS1 = 648 ns
t5-CEPT = 488 ns

t6 = RPD, RND SETUP TO RISING RLCK = 40 ns
t7 = RPD, RND HOLD FROM RISING RLCK = 40 ns

t8

RFRMCK

t8r-f: t8f-r: RLCK TO RFRMCK DELAY = 50 ns

Figure 6. Transmit Framer TLCK to TND, TPD and Receive Framer RND, RPD to RLCK Timing

5-4558(F).dr.1

30 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

LIU-Framer Interface

(continued)

Line Encoding

Single Rail

The default line code is single-rail mode and single-rail function of the framer specified by FRM_PR8 bit 7 = 1,
bit 6 = 1, and bit 5 = 0. In this mode, the framer bipolar encoder/decoder is disabled and monitoring of received
BPV errors is done with the use of the RND input. When RND = 1, the BPV counter increments by one on the rising
edge of RLCK.

The transmit framer transmits data via the TPD output pin while TND is forced to a 0 state.

Dual Rail

In dual-rail mode, the dual-rail function of the framer is selected through FRM_PR8 bits 5—7. Bipolar encoding/
decoding is enabled in the framer. Noncoded/decoded data is exchanged between the LIU and framer via the RPD,
RND, RCLK, TPD, TND, and TCLK LIU-framer interface.

DS1: Alternate Mark Inversion (AMI)

The default line code used for T1 applications is alternate mark inversion (AMI). The coding scheme represents a 1
with a pulse or mark on the positive or negative rail and a 0 with no pulse on either rails. This scheme is shown in
Table 3.

Table 3. AMI Encoding

Input Bit Stream 1011 0000 0111 1010
AMI Data –0+– 0000 0+–+ –0+0

The T1 ones density rule states that: In every 24 bits of information to be transmitted, there must be at least three
pulses, and no more than 15 zeros may be transmitted consecutively.

Receive ones density is monitored by the receive line interface as per T1M1.3/93-005, ITU G.775, or TR-TSY-

000009.
The receive framer indicates excessive zeros upon detecting any zero string length greater than 15 contiguous

zeros (no pulses on either RPD or RND). Both excessive zeros and coding violations are indicated as bipolar viola­tions.

DS1: Zero Code Suppression (ZCS)

Zero code suppression is a technique known as pulse stuffing in which the seventh bit of each time slot is stuffed
with a one. The line format (shown in Table 4) limits the data rate of each time slot from 64 kbits/s to 56 kbits/s.

The default ZCS format stuffs the seventh bit of those ALL-ZERO time slots programmed for robbed-bit signaling
(as defined in the signaling control registers with the F and G bits).

Lucent Technologies Inc. 31

Lucent Technologies Inc.

Preliminary Data Sheet

(

)

TFRA08C13 OCTA L T1/E1 Framer October 2000

LIU-Framer Interface

The receive framer indicates a bipolar violation upon detecting a block of 15 consecutive 0s with no AMI encoding
(no pulses on either RPD or RND). When an internal bipolar violation and a violation of 15 consecutive 0s occur
simultaneously, only one violation is indicated.

Table 4. DS1 ZCS Encoding

Input Bit Stream

ZCS Data (Framer Mode)

Default ZCS

DS1: Binary 8 Zero Code Suppression (B8ZS)

Clear channel transmission can be accomplished using binary 8 zero code suppression (B8ZS). Eight consecutive
0s are replaced with the B8ZS code. This code consists of two bipolar violations in bit position 4 and 7 and valid
bipolar marks in bit positions 5 and 8. The receiving end recognizes this code and replaces it with the original string
of eight 0s.

The receive framer indicates excessive zeros upon detecting a block of eight or more consecutive 0s. (no pulses on
either RPD or RND). Both excessive zeros and coding violations are indicated as bipolar violations.

Table 5 shows the encoding of a string of 0s using B8ZS. B8ZS is recommended when ESF format is used. V rep­resents a violation of the bipolar rule and B represents an inserted pulse conforming to the AMI rule.

(continued)

00000000 01010000 00000000 00000000
00000010 01010010 00000010 00000010
00000010 01010000 00000000

data time slot remains clear

00000010

Table 5. DS1 B8ZS Encoding

Bit Positions 12345678———12345678

Before B8ZS 0000000010100000000
After B8ZS* 000VB0VBB0B000VB0VB

* Bits 5—6 represent a bipolar violation pair. Bipolar violation with respect to the last previous 1 bit.

32 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

LIU-Framer Interface

(continued)

CEPT: High-Density Bipolar of Order 3 (HDB3)

The line code used for CEPT is described in ITU Rec. G.703 Section 6.1 as high-density bipolar of order 3 (HDB3).
HDB3 uses a substitution code that acts on strings of four zeros. The substitute HDB3 codes are 000V and B00V,
where V represents a violation of the bipolar rule and B represents an inserted pulse conforming to the AMI rule
defined in ITU Rec. G.701, item 9004. The choice of the B00V or 000V is made so that the number of B pulses
between consecutive V pulses is odd. In other words, successive V pulses are of alternate polarity so that no direct
current (dc) component is introduced. The substitute codes follow each other if the string of zeros continues. The
choice of the first substitute code is arbitrary. A line code error consists of two pulses of the same polarity that is not
defined as one of the two substitute codes. Excessive zeros consists of any zero string length greater than four
contiguous zeros. Both excessive zeros and coding violations are indicated as bipolar violations. An example is
shown i n Table 6.

Table 6. ITUHDB3 Coding

Input Bit Stream

HDB3-coded Data

HDB3-coded Levels

HDB3 with 5 Double BPVs

1011 0000 01 0000 0000 0000 0000
1011 000V 01 000V B00V B00V B00V
–0+– 000– 0+ 000+ –00– +00+ –00–
–0+– –000 0+ +00+ 0––– +00+ –00–

1-BPV 3-BPV 5-BPV

Lucent Technologies Inc. 33

Lucent Technologies Inc.

Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Frame Formats

The supported North American T1 framing formats are superframe (D4,

SLC

-96, and digital data service-DDS)
and extended superframe (ESF). The device can be programmed to support the ITU-CEPT-E1 basic format with
and without CRC-4 multiframe formatting. This section describes these framing formats.

T1 Framing Structure s

T1 is a digital transmission system which multiplexes tw enty-four 64 kbits/s time slots (DS0) onto a serial link. The
T1 system is the lowest level of hierarchy on the North American T-carrier system, as shown in Figure 7

Table 7. T-Carrier Hierarchy

T Carrier DS0 Channels Bit Rate (Mbits/s) Digital Signal Level

T1 24 1.544 DS1

T1-C 48 3.152 DS1C

T2 96 6.312 DS2
T3 672 44.736 DS3
T4 4032 274.176 DS4

Frame, Superframe, and Extended Superframe Definitions

Each time slot (DS0) is an assembly of 8 bits sampled every 125 µs. The data rate is 64 kbits/s and the sample rate
is 8 kHz. Time-division multiplexing 24 DS0 time slots together produces a 192-bit (24 DS0s) frame. A framing bit is
added to the beginning of each frame to allow for detection of frame boundaries and the transport of additional
maintenance information. This 193-bit frame, also referred to as a DS1 frame, is repeated every 125 µs to yield the

1.544 Mbits/s T1 data rate.DS1 frames are bundled together to form superframes or extended superframes.

FRAME 1 FRAME 2 FRAME 3 FRAME 24FRAME 23

FRAME 1 FRAME 2 FRAME 11 FRAME 12

F BIT TIME SLOT 1 TIME SLOT 2

123 45678

TIME SLOT 24

Figure 7. T1 Frame Structure

24-FRAME EXTENDED

SUPERFRAME

ESF = 3.0 ms

12-FRAME SUPERFRAME

SF = 1.5 ms

193-bit FRAME

DS1 = 125 µs

8-bit TIME SLOT

DS0 = 5.19 µs

5-4559(F).br.1

34 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Frame Formats

(continued)

Transparent Framing Format

The transmit framer can be programmed to transparently transmit 193 bits of system data to the line. The system
interface must be programmed such that the stuffed time slots are 1, 5, 9, 13, 17, 21, 25, and 29 (FRM_PR43 bits
2—0 must be set to 000) and either transparent framing mode 1 or transparent framing mode 2 is enabled
(FRM_PR26 bit 3 or bit 4 must be set to 1).

In transparent mode 1 or mode 2, the transmit framer extracts from the receive system data bit 8 of time slot 1 and
inserts this bit into the framing bit position of the transmit line data. The other 7 bits of the receive system time slot
1 are ignored by the transmit framer. The receive framer will extract the F-bit (or 193rd bit) of the receive line data
and insert it into bit 7 of time slot 1 of the system data; the other bits of time slot 1 are set to 0.

Frame integrity is maintained in both the transmit and receive framer sections.

TIME SLOT 1

SYSTEM INTERFACE CONTROL REGISTER BITS[2:0] = 000.

(STUFF TIME SLOT)

0000000F BIT

32 TIME-SLOT CHI FRAMETIME SLOT 2 TIME SLOT 3 TIME SLOT 31 TIME SLOT 32

SYSTEM FRAME SYNC MASK REGISTER FRM_PR26 BIT 3 OR BIT 4 = 1.
FRAME INTEGRIT Y IS MAINTAINED WITH F BIT AND THE SY ST EM PAYLOAD.

TRAMSMIT FRAMER’S

TIME SLOT 1 TIME SLOT 2 TIME SLOT 24F BIT

193-bit FRAME

DS1 = 125 µs

5-5989(F).b

Figure 8. T1 Transparent Frame Structure

In transparent framing mode 1, the receive framer is forced

not

to reframe on the receive line data. Other than
bipolar violations and unframed AIS monitoring, there is no processing of the receive line data. The receive framer
will insert the 193rd bit of the receive line data into bit 8 of time slot 1 of the transmit system data.

In transparent framing mode 2, the receive framer functions normally on receive line data. All normal monitoring of
receive line data is performed and data is passed to the transmit CHI as programmed. The receive framer will insert
the extracted framing bit of the receive line data into bit 8 of time slot 1 of the transmit system data. The remaining
bits in time slot 1 are set to 0.

Lucent Technologies Inc. 35

Lucent Technologies Inc.

Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Frame Formats

(continued)

D4 Frame Format

D4 superframe format consists of 12 DS1 frames. Table 8 shows the structure of the D4 superframe.

Table 8. D4 Superframe Format

Frame

Number

1

Number

Framing Bits Bit Used in Each Time Slot Signaling Options

Bit

Terminal

2

Frame F

T

Signal
Frame

F

S

Traffic

(All

Channels)

Remote

3

Alarm

Signaling None42-State 4-State

101—1—82————
2193—01—82 ————
33860—1—82 ————
4579—01—82 ————
57721—1—82 ————

5

6

965 — 1 1—7 2 8 — A A
7 1158 0 — 1—8 2 — — — —
8 1351 — 1 1—8 2 — — — —
9 1544 1 — 1—8 2 — — — —

10 1737 — 1 1—8 2 — — — —
11 1930 0 — 1—8 2 — — — —

5

12

2123 — 0 1—7 2 8 — A B

1. Frame 1 is transmitted first.

2. Following
1 of each DS0 is transmitted first.

3. The remote alarm forces bit 2 of each time slot to a 0-state when enabled. The Japanese remote alarm forces framing bit 12 (bit number

2123) to a 1-state when enabled.

4. Signaling option none uses bit 8 for traffic data.

5. Frames 6 and 12 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled.

ANSI

T1.403, the bits are numbered 0—2315. Bit 0 is transmitted first. Bits in each DS0 time slot are numbered 1 through 8, and bit

The receive framer uses both the FT and FS framing bits during its frame alignment procedure.

36 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Frame Formats

(continued)

Digital Data Service (DDS) Frame Format

The superframe format for DDS is the same as that given for D4. DDS is intended to be used for data-only traffic,
and as such, the system should ensure that the framer is in the nonsignaling mode. DDS uses time slot 24 (FAS
channel) to transmit the remote frame alarm and data link bits. The format for time slot 24 is shown in Table 9. The
facility data link timing is shown in Figure 9 below.

Table 9. DDS Channel-24 Format

Time Slot 24 = 10111YD0
Y = (bit 6) Remote frame alarm: 1 = no alarm state; 0 = alarm state
D = (bit 7) Data link bits (8 kbits/s )

t8

TFDLCK

TFDL

t8: TFDLCK CYCLE =

t9

t9

t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns

125 µs (DDS)
250 µs (ALL OTHER
MODES)

t10

RFDLCK

t11

RFDL

t10: RFDLCK CYCLE =

t11: RFDLCK TO RFDL DELAY = 40 ns

Figure 9. T7633 Facility Data Link Access Timing of the Transmit and Receive Framer Sections

-96 Frame Format

SLC

SLC

-96 superframe format consists of 12 DS1 frames similar to D4. The F

F

pattern uses that same structure as D4 but also incorporates a 24-bit data link word as shown below.

S

SSLC

-96 24-bit DATA LINK WORD

Fs =

. . .

000111000111D1DDDDDDDDDDDDDDDDDDDDDDD24000111000111DDD . . .

FRAME

N – 1

FRAMENFRAME

N + 1

FRAME

N + 2

FRAME

N + 3

FRAME

N + 4

FRAME

pattern is exactly the same as D4. The

T

FRAME

N + 5

FRAME

N + 6

N + 7

FRAME

N + 8

125 µs (DDS)
250 µs (ALL OTHER
MODES)

5-3910(F).cr.1

SLC

-96 36-FRAME D-bit SUPERFRAME INTERVAL

Lucent Technologies Inc. 37

Lucent Technologies Inc.

(72 DS1 FRAMES)

Figure 10.

96 Frame Format

SLC-

5-6421(F)r.1

.

Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Frame Formats

External TFDL So urce.

facility data link (TFDL) ports or the

(continued)

Data may be inserted and extracted from the

SLC

-96 data stack. Source selection is controlled by FRM_PR21 bit 6 and

SLC

-96 data link from either the external

FRM_PR29 bit 5—bit 7.
The transmit framer synchronizes on TFDL = 000111000111 . . . and forces a superframe boundary based on this

pattern. When sourcing an external bit stream, it is the system’s responsibility to ensure that TFDL data contain the

pattern of 000111000111 . . . . The D pattern sequence is shown in Table 10. Table 11 shows the encoding for the

line switch field.

Table 10.

-96 Data Link Block Format

SLC

Data Link Block Bit Definition Bit Value

D

(leftmost bit) C1—concentrator bit 0 or 1

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D

10

D

11

D

12

D

13

D

14

D

15

D

16

D

17

D

18

D

19

D

20

D

21

D

22

D

23

D

(rightmost bit) Spoiler bit 4 1

24

C2—concentrator bit 0 or 1
C3—concentrator bit 0 or 1
C4—concentrator bit 0 or 1
C5—concentrator bit 0 or 1
C6—concentrator bit 0 or 1
C7—concentrator bit 0 or 1
C8—concentrator bit 0 or 1

C9—concentrator bit 0 or 1
C10—concentrator bit 0 or 1
C11—concentrator bit 0 or 1

Spoiler bit 1 0
Spoiler bit 2 1

Spoiler bit 3 0
M1—maintenance bit 0 or 1
M2—maintenance bit 0 or 1
M3—maintenance bit 0 or 1

A1—alarm bit 0 or 1

A2—alarm bit 0 or 1
S1—line-switch bit Defined in Table 11
S2—line-switch bit Defined in Table 11
S3—line-switch bit Defined in Table 11
S4—line-switch bit Defined in Table 11

38 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Frame Formats

Table 11.

S

1

-96 Line Switch Message Codes

SLC

S

S

2

3

(continued)

S

4

Code Definition

1111 Idle
1 1 1 0 Switc h li ne A rec eive
1 1 0 1 Switch line B transmit
1 1 0 0 Switch line C transmit
1 0 1 0 Switch line D transmit
0 1 0 1 Switch line B transmit and receive
0 1 0 0 Switch line B transmit and receive
0 0 1 0 Switch line B transmit and receive

Internal

the FDL information in the
The transmit

(see FRM_PR31—FRM_PR35) consists of five 8-bit registers that contain the

-96 Stack Source.

SLC

SLC

-96 FDL bits are sourced from the transmit framer

Optionally , a

SLC

-96 frame format.

SLC

-96 FDL stack may be used to insert and correspondingly extract

SLC

-96 FDL stack. The

SLC

-96 FS and D-bit information as

SLC

-96 FDL stack

shown in Table 12. The transmit stack data is transmitted to the line when the stack enable mode is active in the
parameter registers FRM_PR21 bit 6 = 1 and FRM_PR29 bit 5—bit 7 = x10 (binary).

The receive

SLC

-96 mode, while in the loss of superframe alignment (LSFA) state, updating of the receive framer

SLC

-96 stack data is received when the receive framer is in the superframe alignment state. In the

SLC

-96 stack

is halted and neither the receive stack interrupt nor receive stack flag are asserted.

Table 12. Transmit and Receive

-96 Stack Structure

SLC

Register Number Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

1 (LSR) 0 000011 1

2 0 000011 1
3C

1

4C9C
5M3A

Bit 5—bit 0 of the first 2 bytes of the
sequence. Bit 7 of the third stack register is transmitted as the C1 bit of the
(SPB1, SPB2, SPB3, and SPB4) are taken directly from the transmit stack. The protocol for accessing the
stack information for the transmit and receive framer is described below. The tr ansmit

C

2

10

1

SLC

-96 FDL stack in Table 12 are transmitted to the line as the

C

3

C

11

A

2

C

4

C

5

C

6

SPB1 = 0 SPB2 = 1 SPB3 = 0 M

S

1

S

2

S

3

SLC

-96 D sequence. The spoiler bits

SLC

-96 stack must be written

C

7
1

S

4

C

M

SPB4 = 1

SLC

-96 F

8
2

SLC

S

-96

with valid data when transmitting stack data.
The device indicates that it is ready for an update of its transmit stack by setting register FRM_SR4 bit 5 (

SLC

-96
transmit FDL stack ready) high. At this time, the system has about 9 ms to update the stack. Data written to the
stack during this interval will be transmitted during the next

SLC

-96 superframe D-bit interval. By reading bit 5 in
register SR4, the system clears this bit so that it can indicate the next time the transmit stack is ready. If the trans­mit stack is not updated, then the content of the stack is retransmitted to the line. The start of the
F

interval of the transmit framer is a function of the first 2 bytes of the

S

SLC

-96 transmit stack registers. These

SLC

-96 36-fra me

bytes must be programmed as shown in Table 12. Programming any other state into these two registers disables
the proper transmission of the
mitted synchronous to the transmit

SLC

-96 D bits. Once programmed correctly , the transmit

SLC

-96 superframe structure.

SLC

-96 D-bit stack is tran s-

On the receive side, the device indicates that it has received data in the receive FDL stack (registers FRM_SR54—
FRM_SR58) by setting bit 4 in register FRM_SR4 (

SLC

-96 receive FDL stack ready) high. The system then has
about 9 ms to read the content of the stack before it is updated again (old data lost). By reading bit 4 in register
FRM_SR4, the system clears this bit so that it can indicate the next time the receive stack is ready. As explained
above, the

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SLC

-96 receive stack is not updated when superframe alignment is lost.

Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Frame Formats

(continued)

Extended Superframe Format

The extended superframe format consists of 24 DS1 frames. The F bits are used for frame alignment, superframe
alignment, error checking, and facility data link transport. Table 13 shows the ESF frame format.

Table 13. Extended Superframe (ESF) Structure

Frame

Number

1

Number

Bit

3

Frame Bit

F

E

Bit Use in Each Time

Signaling Option

Slot

D

CRC-64Traffic Signaling None52-State 4-State 16-State

L

2

1 0 —D—1—8 — —— — —
2 193 — — C

1

1—8 — — — — —
3 386 — D — 1—8 — — — — —
4 579 0 — — 1—8 — — — — —
5 772 — D — 1—8 — — — — —

6

6

965 — — C

2

1—7 8 — A A A
7 1158 — D — 1—8 — — — — —
8 1351 0 — — 1—8 — — — — —
9 1544 — D — 1—8 — — — — —

10 1737 — — C

3

1—8 — — — — —

11 1930 — D — 1—8 — — — — —

12

6

2123 1 — — 1—7 8 — A B B
13 2316 — D — 1—8 — — — — —
14 2509 — — C

4

1—8 — — — — —
15 2702 — D — 1—8 — — — — —
16 2895 0 — — 1—8 — — — — —
17 3088 — D — 1—8 — — — — —

6

18

3281 — — C

5

1—7 8 — A A C
19 3474 — D — 1—8 — — — — —
20 3667 1 — — 1—8 — — — — —
21 3860 — D — 1—8 — — — — —
22 4053 — — C

6

1—8 — — — — —
23 4246 — D — 1—8 — — — — —

6

24

4439 1 — — 1—7 8 — A B D

1. Frame 1 is transmitted first.

2. The remote alarm is a repeated 1111111100000000 pattern in the DL when enabled.

3. Following
1 of each DS0 is transmitted first.

4. The C

5. Signaling option none uses bit 8 for traffic data.

6. Frames 6, 12, 18, and 24 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled.

ANSI

T1.403, the bits are numbered 0—4361. Bit 0 is transmitted first. Bits in each DS0 time slot are numbered 1 through 8, and bit

1

to C6 bits are the cyclic redundancy check-6 (CRC-6) checksum bits calculated over the previous extended superframe.

The ESF format allows for in-service error detection and diagnostics on T1 circuits. ESF format consist of 24 fram­ing bits: 6 for framing synchronization (2 kbits/s); 6 for error detection (2 kbits/s); and 12 for in-service monitoring
and diagnostics (4 kbits/s).

40 Lucent Technologies Inc.

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Frame Formats

(continued)

Cyclic redundancy checking is performed over the entire ESF data payload (4,608 data bits, with all 24 framing bits

, DL, CRC-6) set to 1 during calculations). The CRC-6 bits transmitted in ESF will be determined as follows:

(F

E

■

The check bits, c1 through c6, contained in ESF(n + 1) will always be those associated with the contents of
ESF(n), the immediately preceding ESF. When there is no ESF immediately preceding, the check bits may be
assigned any value.

■

For the purpose of CRC-6 calculation only, every F bit in ESF(n) is set to 1. ESF(n) is altered in no other way.

■

The resulting 4632 bits of ESF(n) are used, in order of occurrence, to construct a polynomial in x such that the
first bit of ESF(n) is the coefficient of the term x

■

The polynomial is multiplied by the factor x6, and the result is divided, modulo 2, by the generator polynomial x6

4631

and the last bit of ESF(n) is the coefficient of the term x0.

+ x + 1. The coefficients of the remainder polynomial are used, in order of occurrence, as the ordered set of
check bits, c1 through c6, that are transmitted in ESF(n + 1). The ordering is such that the coefficient of the term

5

x

in the remainder polynomial is check bit c1 and the coefficient of the term x0 in the remainder polynomial is

check bit c6.

The ESF remote frame alarm consists of a repeated eight ones followed by eight 0s transmitted in the data link
position of the framing bits.

T1 Loss of Frame Alignment (LFA)

Loss of frame alignment condition for the superframe or the extended superframe formats is caused by the inability
of the receive framer to maintain the proper sequence of frame bits. The number of errored framing bits required to
detect a loss of frame alignment is given is Table 14.

Table 14. T1 Loss of Frame Alignment Criteria

Format Number of Errored Framing Bits That Will Cause a Loss of Frame Alignment Condition

D4 2 errored frame bits (F

2 errored F

SLC

-96 2 errored frame bits (FT or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1.
2 errored F

bits out of 4 consecutive FT bits if PRM_PR10 bit 2 = 0.

T

bits out of 4 consecutive FT bits if FRM_PR10 bit 2 = 0.

T

DDS: Frame 3 errored frame bits (F
ESF 2 errored F

bits out of 4 consecutive FE bits or optionally 320 or more CRC-6 errored check-

E

or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1.

T

or FS) or channel 24 FAS pattern out of 12 consecutive frame bits.

T

sums within a one second interval if loss of frame alignment due to excessive CRC-6 errors is
enabled in FRM_PR9.

The receive framer indicates the loss of frame and superframe conditions by setting the LFA and LSFA bits
(FRM_SR1 bit 0 and bit 1), respectively, in the status registers for the duration of the conditions. The local system
may give indication of its LFA state to the remote end by transmitting a remote frame alarm (RFA). In addition, in
the LF A state, the system may transmit an alarm indication signal (AIS) to the system interface.

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Frame Formats

(continued)

T1 Frame Recovery Alignment Algorithms

When in a loss of frame alignment state, the receive framer searches for a new frame alignment and forces its inter­nal circuitry to this new alignment. The receive framer’s synchronization circuit inhibits realignment in T1 framing
formats when repetitive data patterns emulate the T1 frame alignment patterns. T1 frame synchronization will not
occur until all frame sequence emulating patterns disappear and only one valid pattern exists. The loss of frame
alignment state will always force a loss of superframe alignment state. Superframe alignment is established only
after frame alignment has been determined in the D4 and
for establishing T1 frame and superframe alignment.

Table 15. T1 Frame Alignment Procedures

Frame Format Alignment Procedure

D4: Frame Using the F

secutive F

frame position as the starting point, frame alignment is established when 24 con-

T

and FS frame bits, excluding the twelfth FS bit, (48 total frames) are received

T

error-free. Once frame alignment is established, then superframe alignment is determined.

D4: Superframe After frame alignment is determined, two valid superframe bit sequences using the

F

bits must be received error-free to establish superframe alignment.

S

SLC

-96: Frame Using the FT frame position as the starting point, frame alignment is established when 24 con­secutive F

frame bits (48 total frames) are received error-free. Once frame alignment is

T

established, then superframe alignment is determined.

SLC

-96:

Superframe
DDS: Frame Using the F

After frame alignment is determined, superframe alignment is established on the first valid
superframe bit sequence 000111000111.

frame position as the starting point, frame alignment is established when six

T

consecutive F

frame bits and the DDS FAS in time slot 24 are received error-free. In the

T/FS

DDS format, there is no search for a superframe structure.

ESF Frame and superframe alignment is established simultaneously using the F

Alignment is established when 24 consecutive F
superframe alignment is established, the CRC-6 receive monitor is enabled.

SLC

-96 frame format. Table 15 gives the requirements

framing bit.

E

bits are received error-free. Once frame/

E

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Frame Formats

(continued)

T1 Robbed-Bit Signaling

To enable signaling, register FRM_PR44 bit 0 (TSIG) must be set to 0.
Robbed-bit signaling, used in either ESF or SF framing formats, robs the eighth bit of the voice channels of every

sixth frame. The signaling bits are designated A, B, C, and D, depending on the signaling format used. The robbed­bit signaling format used is defined by the state of the F and G bits in the signaling registers (see DS1: Robbed-Bit
Signaling on page 61). The received channel robbed-bit signaling format is defined by the corresponding transmit
signaling F and G bits. Table 16 shows the state of the transmitted signaling bits as a function of the F and G bits.

Table 16. Robbed-Bit Signaling Options

G F Robbed-Bit Signaling Format Frame

6121824

0 0 ESF: 16-State

SLC

*: 9-State, 16-State
01 4-State ABAB
1 0 Data channel (no signaling) PAYLOAD DATA
11 2-State AAAA

* See register FRM_PR43 bit 3 and bit 4.

ABCD

The robbed-bit signaling format for each of the 24 T1 transmit channels is programmed on a per-channel basis by
setting the F and G bits in the transmit signaling direction.

-96 9-State Signaling

SLC

SLC

-96 9-state signaling state is enabled by setting both the F and G bits in the signaling registers to the 0-state,
setting the
17 shows the state of the transmitted signaling bits to the line as a function of the A-, B-, C-, and D-bit settings in
the transmit signaling registers. In Table 17 below, X indicates either a 1- or a 0-state, and T indicates a toggle,
transition from either 0 to 1 or 1 to 0, of the transmitted signaling bit.

In the line receive direction, this signaling mode functions identically to the preceding transmit path description.

Table 17.

SLC

SLC

-96 signaling control register FRM_PR43 bit 3 to 1, and setting register FRM_PR44 bit 0 to 0. T able

-96 9-State Signaling Format

SLC

Transmit Signaling Register Settings Transmit to the Line Signal Bits

-96 Signaling StatesABCDA = f(A, C)B = f(B, D)

State 1 0000 0 0
State 2 0001 0 T
State 3 010X 0 1
State 4 0010 T 0
State 5 0011 T T
State 6 011X T 1
State 7 1 0 X 0 1 0
State 8 1 0 X 1 1 T
State 9 1 1 X X 1 1

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Frame Formats

16-State Signaling

The default signaling mode while in
setting both the F and G bits in the signaling registers to the 0 state, setting the
FRM_PR43 bit 3 and bit 4 to 0, and setting register FRM_PR44 bit 0 to 0. Table 18 shows the state of the transmit­ted signaling bits to the line as a function of the A-, B-, C-, and D-bit settings in the transmit signaling registers. In
Table 18 below, under Transmit to the Line Signal Bits, A and B are transmitted into one
superframe, while A’ and B’ are transmitted into the next successive

In the line receive direction, this signaling mode functions identically to the preceding transmit path description.
The signaling mapping of this 16-state signaling mode is equivalent to the mapping of the

mode.

Table 18. 16-State Signaling Format

-96 Signaling StatesABCDA BA’B’

SLC

State 0 00000000
State 1 00010001
State 2 00100010
State 3 00110011
State 4 01000100
State 5 01010101
State 6 01100110
State 7 01110111
State 8 10001000

State 9 10011001
State 10 10101010
State 11 10111011
State 12 11001100
State 13 11011101
State 14 11101110
State 15 11111111

(continued)

SLC

-96 framing is 16-state signaling.

Transmit Signaling Register Settings Transmit to the Line Signal Bits

SLC

-96 16-state signaling is enabled by

SLC

-96 signaling control register

SLC

-96 12-frame signaling

SLC

-96 12-frame signaling superframe.

SLC

-96 9-state signaling

44 Lucent Technologies Inc.

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Frame Formats

(continued)

CEPT 2.048 Basic Frame, CRC-4 Time Slot 0, and Signaling Time Slot 16 Multiframe Structures

As defined in TU Rec. G.704, the CEPT 2.048 frame, CRC-4 multiframe, and channel associated signaling multi­frame structures are illustrated in Figure 11

CRC-4 MULTIFRAME IN

TIME SLOT 0

C1 0 0 1 1 0 1 1
0 1 A SA4 SA5 SA6 SA7 S

0 0 1 1 0 1 1

C

2

0 1 A S

A4 SA5 SA6 SA7 SA8

C3 0 0 1 1 0 1 1
1 1 A S

A4 SA5 SA6 SA7 SA8

C4 0 0 1 1 0 1 1
0 1 A S

A4 SA5 SA6 SA7 SA8

C1 0 0 1 1 0 1 1
1 1 A S

A4 SA5 SA6 SA7 SA8

C2 0 0 1 1 0 1 1
1 1 A S

A4 SA5 SA6 SA7 SA8

C3 0 0 1 1 0 1 1
E 1 A S

A4 SA5 SA6 SA7 SA8

C4 0 0 1 1 0 1 1
E 1 A S

A4 SA5 SA6 SA7 SA8

TIME SLOT 1
TIME SLOT 1

A8

TIME SLOT 1
TIME SLOT 1
TIME SLOT 1
TIME SLOT 1
TIME SLOT 1
TIME SLOT 1
TIME SLOT 1
TIME SLOT 1
TIME SLOT 1
TIME SLOT 1
TIME SLOT 1
TIME SLOT 1
TIME SLOT 1
TIME SLOT 1

TIME SLOT 31
TIME SLOT 31
TIME SLOT 31
TIME SLOT 31
TIME SLOT 31
TIME SLOT 31
TIME SLOT 31
TIME SLOT 31
TIME SLOT 31
TIME SLOT 31
TIME SLOT 31
TIME SLOT 31
TIME SLOT 31
TIME SLOT 31
TIME SLOT 31
TIME SLOT 31

FRAME 0 OF CRC-4
MULTIFRAME

FRAME 15 OF CRC-4
MULTIFRAME

0 0 0 0 X

A

1 B1 C1 D1 A16

A2 B2 C2 D2 A
A3 B3 C3 D3 A18 B18 C18 D
A4 B4 C4 D4 A19 B19 C
A5 B5 C5 D5 A20 B20 C
A6 B6 C6 D6 A21 B21 C21 D
A7 B7 C7 D7 A
A8 B8 C8 D8 A23 B23 C23 D
A9 B9 C9 D9 A
A10 B10 C10 D10 A25 B25 C25 D
A11 B11 C11 D11 A26 B26 C26 D
A12 B12 C12 D12 A27 B27 C27 D

A13 B13 C13 D13 A28 B28 C28 D
A14 B14 C14 D14 A29 B29 C29 D

A15 B15 C15 D15 A30 B30 C30 D

CHANNEL ASSOCIATED

SIGNALING MULTIFRAME

CHANNEL NUMBERS REFER TO TELEPHONE
CHANNEL NUMBERS. TIME SLOTS 1 TO 15 AND
17 TO 31 ARE ASSIGNED TO TELEPHONE
CHANNELS NUMBERED FROM 1 TO 30.

YM X1 X

0

B16 C16 D

17 B17 C17 D17

22 B22 C22

C

24 B24

IN TIME SLOT 16

2

19 D19

20 D20

D

24 D24

16

18

21

22

23

25

26

27

28

29

30

FRAME 0 TIME
SLOT 16
MULTIFRAME

FRAME 15

TIME SLOT 16

MULTIFRAME

Si 0 0 1 1 0 1 1 TIME SLOT 1 TIME SLOT 31

FAS FRAME

PRIMARY BASIC FRAME

STRUCTURE

Si 1 A SA4 SA5 SA6 SA7 S

TIME SLOT 0

TIME SLOT 1

12345678

TIME SLOT 1 TIME SLOT 31

A8

TIME SLOT 16 TIME SLOT 31

8-bit TIME SLOT = 3.90625 µs

NOT FAS FRAME

256-bit FRAME = 125 µs

5-4548(F).cr.1

Figure 11. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated Signaling

Multiframe Structures

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Frame Formats

(continued)

CEPT 2.048 Basic Frame Structure

The ITU Rec. G.704 Section 2.3.1 defined frame length is 256 bits, numbered 1 to 256. The frame repetition rate is
8 kHz. The allocation of bits numbered 1 to 8 of the frame is shown in Table 19.

Table 19. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame

Basic Frames Bit 1 (MSB) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 (LSB)

Frame Alignment Signal (FAS) Si 0 0 1 1 0 1 1
Not Frame Alignment Signal

(NOT FAS)

The function of each bit in Table 19 is described below:

■

The Si bits are reserved for international use. A specific use for these bits is described in Table 20. ITU CRC-4
Multiframe Structure. If no use is realized, these bits should be fixed at 1 on digital paths crossing an interna­tional border.

■

Bit 2 of the NOT FAS frames is fixed to 1 to assist in avoiding simulations of the frame alignment signal.

■

Bit 3 of the NOT FAS is the remote alarm indication (A bit). In undisturbed operation, this bit is set to 0; in alarm
condition, set to 1.

■

Bits 4—8 of the NOT FAS (Sa4—Sa8) may be recommended by ITU for use in specific point-to-point applica­tions. Bit Sa4 may be used as a message-based data link for operations, maintenance, and performance moni­toring. If the data link is accessed at intermediate points with consequent alterations to the Sa4 bit, the CRC-4
bits must be updated to retain the correct end-to-end path termination functions associated with the CRC-4 pro­cedure. The receive framer does not implement the CRC-4 modifying algorithm described in ITU Rec. G.706
Annex C. Bits Sa4—Sa8, where these are not used, should be set to 1 on links crossing an international border.

Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8

■

MSB = most significant bit and is transmitted first.

■

LSB = least significant bit and is transmitted last.

46 Lucent Technologies Inc.

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Frame Formats

(continued)

Transparent Framing Format

The transmit framer can be programmed to transparently transmit 256 bits of system data to the line. The transmit
framer must be programmed to either transparent framing mode 1 or transparent framing mode 2 (see Table 136.
Framer Reset and Transparent Mode Control Register (FRM_PR26) (Y7A)).

In transparent mode 1 or mode 2, the transmit framer transmits all 256 bits of the RCHI payload unmodified to the
line. Time slot 1 of the RCHI, determined by the CHIFS signal, is inserted into the FAS/NOT FAS time slot of the
transmit line interface.

Frame integrity is maintained in both the transmit and receive framer sections.

TIME SLOT 1 32 TIME-SLOT CHI FRAMETIME SLOT 2 TIME SLOT 3 TIME SLOT 31 TIME SLOT 32

TIME SLOT 1 32 TIME-SLOT LINE FRAMETIME SLOT 2 TIME SLOT 3 TIME SLOT 31 TIME SLOT 32

5-5988(F)

Figure 12. CEPT Transparent Frame Structure

In transparent framing mode 1, the receive framer is forced

not

to reframe on the receive line data. Other than
bipolar violations and unframed AIS moni toring, there is no processing of the receive line data. The entire receive
line payload is transmitted unmodified to the CHI.

In transparent framing mode 2, the receive framer functions normally on the receive line data. All normal monitoring
of receive line data is performed and data is transmitted to the CHI as programmed.

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

■

Frame Formats

(continued)

CEPT Loss of Basic Frame Alignment (LFA)

Frame alignment is assumed to be lost when the follow­ing occurs :

■

As described in ITU Rec. G.706 Section 4.1.1, three
consecutive incorrect frame alignment signals have
been received.

■

So as to limit the effect of spurious frame alignment
signals, when bit 2 in time slot 0 in NOT FAS frames
has been received with an error on three consecutive
occasions.

■

Optionally, as described in ITU Rec. G.706 Section

4.3.2, by exceeding a count of >914 errored CRC-4
blocks out of 1000, with the understanding that a
count of
frame alignment.

≥

915 errored CRC blocks indicates false

If CRC-4 is enabled, loss of CRC-4 multiframe align­ment is forced.

■

If CRC-4 is enabled, the monitoring and processing
of CRC-4 checksum errors is halted.

■

If CRC-4 is enabled, all monitoring and processing of
received E-bit information is halted.

■

If CRC-4 is enabled, the receive continuous E-bit
alarm is deactivated.

■

If CRC-4 is enabled, optionally, E bit = 0 is transmit­ted to the line for the duration of loss of CRC-4 multi­frame alignment if register FRM_PR28 bit 4 is set to

1.

■

If time slot 16 signaling is enabled, loss of the signal­ing multiframe alignment is forced.

■

If time slot 16 signaling is enabled, updating of the
signaling data is halted.

■

On demand via the control registers.

■

In the LF A state:

■

No additional FAS or NOT FAS errors are processed.

■

The received remote frame alarm (received A bit) is
deactivated.

■

All NOT FAS bit (Si bit, A bit, and Sa4 to Sa8 bits)
processing is halted.

■

Receive Sa6 status bits are set to 0.

■

Receive Sa6 code monitoring and counting is halted.

■

All receive Sa stack data updates are halted. The
receive Sa stack ready, register FRM_SR4 bit 6 and
bit 7, is set to 0. If enabled, the receive Sa stack
interrupt bit is set to 0.

■

Receive data link (RFDL) is set to 1 and RFDCLK
maintains previous alignment.

■

Optionally, the remote alarm indication (A = 1) may
be automatically transmitted to the line if register
FRM_PR27 bit 0 is set to 1.

■

Optionally, the alarm indication signal (AIS) may be
automatically transmitted to the system if register
FRM_PR19 bit 0 is set to 1.

CEPT Loss of Frame Alignment Recovery Algorithm

The receive framer begins the search for basic frame
alignment one bit position beyond the position where
the LFA state was detected. As defined in ITU Rec.
G.706.4.1.2, frame alignment will be assumed to have
been recovered when the following sequence is
detected as follows:

■

For the first time, the presence of the correct frame
alignment signal in frame

■

The absence of the frame alignment signal in the fol­lowing frame detected by verifying that bit 2 of the
basic frame is a 1 in frame

■

For the second time, the presence of the correct
frame alignment in the next frame,

Failure to meet the second or third bullet above will ini
tiate a new basic frame search in frame

n

.

n

+ 1.

n

+ 2.

n

+ 2.

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Frame Formats

(continued)

CEPT Time Slot 0 CRC-4 Multiframe Structure

The CRC-4 multiframe is in bit 1 of each NOT FAS frame. As described in ITU Rec. G.704 Section 2.3.3.1, where
there is a need to provide additional protection against simulation of the frame alignment signal, and/or where there
is a need for an enhanced error monitoring capability, then bit 1 of each frame may be used for a cyclic redundancy
check-4 (CRC-4) procedure as detailed below. The allocation of bits 1—8 of time slot 0 of every frame is shown in
Table 20 for the complete CRC-4 multiframe.

Table 20. ITU CRC-4 Multiframe Structure

Multiframe Submultiframe

(SMF)

I0C10011011

II 8 C10011011

Frame

Number

12345678

Bits

1 0 1 A Sa4 Sa5 Sa6 Sa7 Sa8
2 C20011011
3 0 1 A Sa4 Sa5 Sa6 Sa7 Sa8
4 C30011011
5 1 1 A Sa4 Sa5 Sa6 Sa7 Sa8
6 C40011011
7 0 1 A Sa4 Sa5 Sa6 Sa7 Sa8

9 1 1 A Sa4 Sa5 Sa6 Sa7 Sa8
10 C2 0 0 1 1 0 1 1
11 1 1 A Sa4 Sa5 Sa6 Sa7 Sa8
12 C3 0 0 1 1 0 1 1
13 E 1 A Sa4 Sa5 Sa6 Sa7 Sa8
14 C4 0 0 1 1 0 1 1
15 E 1 A Sa4 Sa5 Sa6 Sa7 Sa8

Notes:
C1 to C4 = cyclic redundancy check-4 (CRC-4) bits.
E = CRC-4 error indication bits.
Sa4 to Sa8 = spare bits.
A = remote frame alarm (RFA) bit (active-high); referred to as the A bit.

The CRC-4 multiframe consists of 16 frames numbered 0 to 15 and is divided into two eight-frame submultiframes
(SMF), designated SMF-I and SMF-II that signifies their respective order of occurrence within the CRC-4 multi­frame structure. The SMF is the CRC-4 block size (2048 bits). In those frames containing the frame alignment sig­nal (FAS), bit 1 is used to transmit the CRC-4 bits. There are four CRC-4 bits, designated C1, C2, C3, and C4 in
each SMF. In those frames not containing the frame alignment signal (NOT FAS), bit 1 is used to transmit the 6-bit
CRC-4 multiframe alignment signal and two CRC-4 error indication bits (E). The multiframe alignment signal is
defined in ITU Rec. G.704 Section 2.3.3.4, as 001011. Transmitted E bits should be set to 0 until both basic frame
and CRC-4 multiframe alignment are established. Thereafter, the E bits should be used to indicate received errored
submultiframes by setting the binary state of one E bit from 1 to 0 for each errored submultiframe. The received E
bits will always be taken into account, by the receive E-bit processor

*

, even when the SMF that contains them is
found to be errored. In the case where there exists equipment that does not use the E bits, the state of the E bits
should be set to a binary 1 state.

* The receive E-bit processor will halt the monitoring of the received E bit during the loss of CRC-4 multiframe alignment.

Lucent Technologies Inc. 49

Lucent Technologies Inc.

Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Frame Formats

(continued)

The CRC-4 word, located in submultiframe N, is the

4

remainder after multiplication by x
(modulo 2) by the generator polynomial x

and then division

4

+ x + 1, of

the polynomial representation of the submultiframe N –

1. Representing the contents of the submultiframe
check block as a polynomial, the first bit in the block,
i.e., frame 0, bit 1 or frame 8, bit 1, is taken as being the
most significant bit and the least significant bit in the
check block is frame 7 or frame 15, bit 256. Similarly,
C

is defined to be the most significant bit of the

1

remainder and C

the least significant bit of the remain-

4

der. The encoding procedure, as described in ITU Rec.
G.704 Section 2.3.3.5.2, follows:

■

The CRC-4 bits in the SMF are replaced by binary
0s.

■

The SMF is then acted upon the multiplication/divi­sion process referred to above.

■

The remainder resulting from the multiplication/divi­sion process is stored, ready for insertion into the
respective CRC-4 locations of the next SMF.

The decoding procedure, as described in ITU Rec.
G.704 Section 2.3.3.5.3, follows:

■

A received SMF is acted upon by the multiplication/
division process referred to above, after having its
CRC-4 bits extracted and replaced by 0s.

■

The remainder resulting from this division process is
then stored and subsequently compared on a bit-by­bit basis with the CRC bits received in the next SMF.

■

If the remainder calculated in the decoder exactly
corresponds to the CRC-4 bits received in the next
SMF, it is assumed that the checked SMF is error­free.

CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA)

Loss of basic frame alignment forces the receive framer
into a loss of CRC-4 multiframe alignment state. This
state is reported by way of the status registers
FRM_SR1 bit 2. Once basic frame alignment is
achieved, a new search for CRC-4 multiframe align­ment is initiated. During a loss of CRC-4 multiframe
alignment state the following occurs:

■

The CRC-4 error counter is halted.

■

The CRC-4 error monitoring circuit for errored sec­onds and severely errored seconds is halted.

■

The received E-bit counter is halted.

■

The received E-bit monitoring circuit for errored sec­onds and severely errored seconds at the remote
end interface is halted.

■

Receive continuous E-bit monitoring is halted.

■

All receive Sa6 code monitoring and counting func­tions are halted.

■

The updating of the receive Sa stack is halted and
the receive Sa stack interrupt is deactivated.

■

Optionally , A = 1 ma y be automatically transmitted to
the line if register FRM_PR27 bit 2 is set to 1.

■

Optionally , E = 0 ma y be automatically transmitted to
the line if register FRM_PR28 bit 4 is set to 1.

■

Optionally, if LTS0MFA monitoring in the perfor­mance counters is enabled, by setting registers
FRM_PR14 through FRM_PR17 bit 1 to 1, then
these counts are incremented once per second for
the duration of the LTS0MFA state.

50 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Frame Formats

(continued)

CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms

Several optional algorithms exist in the receive framer.
These are selected through programming of register
FRM_PR9.

CRC-4 Multiframe Alignment Algorithm with 8 ms
Timer

The default algorithm is as described in ITU Rec.
G.706 Section 4.2. The recommendation states that if a
condition of assumed frame alignment has been
achieved, CRC-4 multiframe alignment is deemed to
have occurred if at least two valid CRC-4 multiframe
alignment signals can be located within 8 ms, the time
separating two CRC-4 multiframe signals being 2 ms or
a multiple of 2 ms. The search for the CRC-4 multi­frame alignment signal is made only in bit 1 of NOT
FAS frames. If multiframe alignment cannot be
achieved within 8 ms, it is assumed that frame align­ment is due to a spurious frame alignment signal and a
new parallel search for basic frame alignment is initi­ated. The new search for the basic frame alignment is
started at the point just after the location of the
assumed spurious frame alignment signal. During this
parallel search for basic frame alignment, there is no
indication to the system of a receive loss of frame align­ment (RLFA) state. During the parallel search for basic
frame alignment and while in primary basic frame align­ment, data will flow through the receive framer to the
system interface as defined by the current primary
frame alignment. The receive framer will continuously
search for CRC-4 multiframe alignment.

CRC-4 Multiframe Alignment Algorithm with
100 ms Timer

The CRC-4 multiframe alignment with 100 ms timer
mode is enabled by setting FRM_PR9 to 0XXXX1X1
(binary). This CRC-4 multiframe reframe mode starts a
100 ms timer upon detection of basic frame alignment.
This is a parallel timer to the 8 ms timer. If CRC-4 multi­frame alignment cannot be achieved within the time
limit of 100 ms due to the CRC-4 procedure not being
implemented at the transmitting side, then an indication
is given, and actions are taken equivalent to those
specified for loss of basic frame alignment, namely:

■

Optional automatic transmission of A = 1 to the line if
register FRM_PR27 bit 3 is set to 1.

■

Optional automatic transmission of E = 0 to the line if
register FRM_PR28 bit 5 is set to 1.

■

Optional automatic transmission of AIS to the system
if register FRM_PR19 bit 1 is set to 1.

Lucent Technologies Inc. 51

Lucent Technologies Inc.

Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Frame Formats

OUT OF PRIMARY BFA:

IN PRIMARY BFA:

CRC-4 MFA SEARCH (ITU REC. G.706, SECTION 4.2 -

YES

(continued)

• OPTIONALLY DISABLE TRAFFIC BY TRANSMITTING AIS TO THE SYSTEM

• OPTIONALLY TRANSMIT A = 1 AND E = 0 TO LINE

• INHIBIT INCOMING CRC-4 PERFORMANCE MONITORING

NO

• ENABLE TRAFFIC TO THE SYSTEM

• TRANSMIT A = 0 AND OPTIONALLY E = 0 TO THE LINE

• START 8 ms AND 100 ms TIMERS

• ENABLE PRIMARY BFA LOSS CHECKING PROCESS

PRIMARY

BFA SEARCH?

CAN CRC-4

MFA BE FOUND

IN 8 ms?

YES

NO

NOTE 2

YES

IS

INTERNAL

100 ms TRX = 1

?

)

NO

NO

PARALLEL

BFA SEARCH

GOOD?

100 ms

TIMER

ELAPSED?

YES

NO

YES

ASSUME CRC-4 MULTIFRAME ALIGNMENT:

• CONFIRM PRIMARY BFA ASSOCIATED WITH CRC-4 MFA

• ADJUST PRIMARY BFA IF NECESSARY

IS 100 ms TRX = 1

?

NO

START CRC-4 PERFORMANCE MONITORING:

• SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4

YES

CRC-4

COUNT > 914

IN 1 SECOND OR

LFA = 1?

YES

SET INTERNAL 100 ms TIMER EXPIRATION STATUS BIT TO 0:

• IF TRANSMITTING A BIT = 1 TO THE LINE INTERFACE, TRANSMIT A BIT = 0

• IF TRANSMITTING AIS TO THE SYSTEM INTERFACE, ENABL E DATA
TRANSMISSION TO THE SYSTEM INTERFACE

• IF TRANSMITTING E = 0 TO THE LINE INTERFACE, TRANSMIT E BIT = 1

NO

CONTINUE CRC-4 PERFORMANCE MONITORING:

• SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4

SET 100 ms TIMER EXPIRATION STATUS BIT TO THE 1 STATE:
SET INTERNAL 100 ms TIMER EXPIRATION STATUS BIT TO 1:

• OPTIONALLY TRANSMIT A BIT = 1 TO THE LINE INTERFACE FOR
THE DURATION OF LTS0MFA = 1

• OPTIONALLY TRANSMIT AIS TO THE SYSTEM INTERFACE FOR THE
DURATION OF LTS0MFA = 1

• OPTIONALLY TRANSMIT E BIT = 0 TO THE LINE INTERFACE FOR
THE DURATION OF LTSOMFA = 1

Figure 13. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer

5-3909(F).er.2

52 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Frame Formats

(continued)

CRC-4 Multiframe Alignment Search Algorithm with
400 ms Timer

The CRC-4 multiframe alignment with 400 ms timer
mode is enabled by setting FRM_PR9 to 0XXX1XX1
(binary). This receive CRC-4 multiframe reframe mode
is the modified CRC-4 multiframe alignment algorithm
described in ITU Rec. 706 Annex B, where it is referred
to as CRC-4-to-non-CRC-4 equipment interworking. A
flow diagram of this algorithm is illustrated in
Figure 14. When the interworking algorithm is enabled,
it supersedes the 100 ms algorithm described on
page 51 and in Figure 13. This algorithm assumes that
a valid basic frame alignment signal is consistently
present, but the CRC-4 multiframe alignment cannot be
achieved by the end of the total CRC-4 multiframe
alignment search period of 400 ms, if the distant end is
a non-CRC-4 equipment. In this mode, the following
consequent actions are taken:

■

An indication that there is no incoming CRC-4 multi­frame alignment signal.

■

All CRC-4 processing on the receive 2.048 Mbits/s
signal is inhibited.

■

CRC-4 data is transmitted to the distant end with
both E bits set to 0.

This algorithm allows the identification of failure of
CRC-4 multiframe alignment generation/detection, but
with correct basic framing, when interworking between
each piece of equipment having the modified CRC-4
multiframe alignment algorithm.

As described in ITU Rec. G.706 Section B.2.3:

■

A 400 ms timer is triggered on the initial recovery of
the primary basic frame alignment.

■

The 400 ms timer reset if and only if:
— The criteria for loss of basic frame alignment as

described in ITU Rec. G.706 Section 4.1.1 is
achieved.

— If 915 out of 1000 errored CRC-4 blocks are

detected resulting in a loss of basic frame align­ment as described in ITU Rec. G.706 Section

4.3.2.
— On-demand reframe is requested.
— The receive framer is programmed to the non-

CRC-4 mode.

■

The loss of basic frame alignment checking process
runs continuously, irrespective of the state of the
CRC-4 multiframe alignment process below it.

■

A new search for frame alignment is initiated if
CRC-4 multiframe alignment cannot be achieved in
8 ms, as described in ITU Rec. G.706 Section 4.2.
This new search for basic frame alignment will not
reset the 400 ms timer or invoke consequent actions
associated with loss of the primary basic frame align­ment. In particular, all searches for basic frame align­ment are carried out in parallel with, and
independent of, the primary basic frame loss check­ing process. All subsequent searches for CRC-4 mul­tiframe alignment are associated with each basic
framing sequence found during the parallel search.

■

During the search for CRC-4 multiframe alignment,
traffic is allowed through, upon, and to be synchro­nized to, the initially determined primary basic frame
alignment.

■

Upon detection of the CRC-4 multiframe before the
400 ms timer elapsing, the basic frame alignment
associated with the CRC-4 multiframe alignment
replaces, if necessar y, the initially determined basic
frame alignment.

■

If CRC-4 multiframe alignment is not found before
the 400 ms timer elapses, it is assumed that a condi­tion of interworking between equipment with and
without CRC-4 capability exists and the actions
described above are taken.

■

If the 2.048 Mbits/s path is reconfigured at any time,
then it is assumed that the (new) pair of path termi­nating equipment will need to re-establish the com­plete framing process, and the algorithm is reset.

Lucent Technologies Inc. 53

Lucent Technologies Inc.

Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Frame Formats

(continued)

OUT OF PRIMARY BFA:

• OPTIONALLY DISABLE TRAFFIC BY TRANSMITTING AIS TO THE SYSTEM

• OPTIONALLY TRANSMIT A BIT = 1 AND E BIT = 0 TO LINE

• INHIBIT INCOMING CRC-4 PERFORMANCE MONITORING

NO

IN PRIMARY BFA:

• ENABLE TRAFFIC NOT TRANSMITTING AIS TO THE SYSTEM

• TRANSMIT A = 0 AND OPTIONALLY E = 0 TO THE LINE

• START 400 ms TIMER

• ENABLE PRIMARY BFA LOSS CHECKING PROCESS

CRC-4 MFA SEARCH (ITU REC. G.706, SECTION 4.2)

BFA SEARCH?

YES

PRIMARY

YES

CAN CRC-4

MFA BE FOUND

IN 8 ms?

NO

NO

YES

PARALLEL

BFA SEARCH

?

NO

400 ms

TIMER

ELAPSED?

YES

ASSUME CRC-4-TO-CRC-4 INTERWORKING:

• CONFIRM PRIMARY BFA ASSOCIATED WITH CRC-4 MFA

• ADJUST PRIMARY BFA IF NECESSARY

• KEEP A = 0 IN OUTGOING CRC-4 DATA

START CRC-4 PERFORMANCE MONITORING:

• SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4

CRC-4

YES

COUNT > 914

IN 1 SECOND OR

LFA = 1?

NO

CONTINUE CRC-4 PERFORMANCE MONITORING:

• SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4

ASSUME CRC-4-TO-NON-CRC-4 INTERWORKING:

• CONFIRM PRIMARY BFA

• TRANSMIT A BIT = 0 TO THE LINE INTERFACE

• TRANSMIT E BIT = 0 TO THE LINE INTERFACE

• STOP INCOMING CRC-4 PROCESSING

• INDICATE “NO CRC-4 MFA”

5-3909(F).fr.3

Figure 14. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4 Equipment

Interworking as Defined by ITU (From ITU Rec. G.706, Annex B.2.2 - 1991)

54 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Frame Formats

(continued)

CEPT Time Slot 16 Multiframe Structure

The TFRA08C13 supports two CEPT signaling modes: channel associated signaling (CAS) or per-channel signal­ing (PCS0 and PCS1).

Channel Associated Signaling (CAS)

The channel associated signaling (CAS) mode utilizes time slot 16 of the FAS and NOT FAS frames. The CAS for­mat is a multiframe consisting of 16 frames where frame 0 of the multiframe contains the multiframe alignment pat­tern of four zeros in bits 1 through 4. Table 21 illustrates the CAS multiframe of time slot 16. The TFRA08C13 can
be programmed to force the transmitted line CAS multiframe alignment pattern to be transmitted in the FAS frame
by selecting the PCS0 option or in the NOT FAS frame by selecting the PCS1 option. Alignment of the transmitted
line CAS multiframe to the CRC-4 multiframe is arbitrary.

Table 21. ITU CEPT Time Slot 16 Channel Associated Signaling Multiframe Structure

Time Slot 16

Channel

Associated

Signaling

Multiframe

Frame

Number

123 4 5 6 7 8

0 000 0 X
1A1B
2A2B
3A3B
4A4B
5A5B
6A6B
7A7B
8A8B

9A9B
10 A
11 A
12 A
13 A
14 A
15 A

10
11
12
13
14
15

B
B
B
B
B
B

10
11
12
13
14
15

C

1
2
3
4
5
6
7
8
9

1

C

2

C

3

C

4

C

5

C

6

C

7

C

8

C

9

C

10

C

11

C

12

C

13

C

14

C

15

Bit

Y

0

D
D
D
D
D
D
D
D

D
D
D
D
D
D
D

10
11
12
13
14
15

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

A

9

A
A
A
A
A
A

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

B

16

B

17

B

18

B

19

B

20

B

21

B

22

B

23

B

24

B

25

B

26

B

27

B

28

B

29

B

30

X

M

C

16

C

17

C

18

C

19

C

20

C

21

C

22

C

23

C

24

C

25

C

26

C

27

C

28

C

29

C

30

X

1

2

D

16

D

17

D

18

D

19

D

20

D

21

D

22

D

23

D

24

D

25

D

26

D

27

D

28

D

29

D

30

Notes:
Frame 0 bits 1—4 define the time slot 16 multiframe alignment.

X0—X2 = time slot 16 spare bits defined in FRM_PR41 bit 0—bit 2.

M

= yellow alarm, time slot 16 remote multiframe alarm (RMA) bit (1 = alarm condition).

Y

Lucent Technologies Inc. 55

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Frame Formats

(continued)

CEPT Loss of Time Slot 16 Multiframe Align­ment (LTS16MFA)

Loss of basic frame alignment forces the receive framer
into a loss of time slot 16 signaling multiframe align­ment state. In addition, as defined in ITU Rec. G.732
Section 5.2, time slot 16 signaling multiframe is
assumed lost when two consecutive time slot 16 multi­frame 4-bit all-zero patterns is received with an error. In
addition, the time slot 16 multiframe is assumed lost
when, for a period of two multiframes, all bits in time
slot 16 are in state 0. This state is reported by way of
the status registers FRM_SR1 bit 1. Once basic frame
alignment is achieved, the receive framer will initiate a
search for the time slot 16 multiframe alignment. During
a loss of time slot 16 multiframe alignment state, the
following occurs:

■

The updating of the signaling data is halted.

■

The received control bits forced to the binary 1 state.

■

The received remote multiframe alarm indication sta­tus bit is forced to the binary 0 state.

■

Optionally, the transmit framer can transmit to the
line the time slot 16 signaling remote multiframe
alarm if regist er FRM_PR41 bit 4 is set to 1.

■

Optionally , the transmit framer can transmit the alarm
indication signal (AIS) in the system transmit time
slot 16 data if register FRM_PR44 bit 6 is set to 1.

CEPT Loss of Time Slot 16 Multiframe Align­ment Recovery Algorithm

The time slot 16 multiframe alignment recovery algo­rithm is as described in ITU Rec. G.732 Section 5.2.
The recommendation states that if a condition of
assumed frame alignment has been achieved, time slot
16 multiframe alignment is deemed to have occurred
when the 4-bit time slot 16 multiframe pattern of 0000
is found in time slot 16 for the first time, and the preced­ing time slot 16 contained at least one bit in the binary
1 state.

CEPT Time Slot 0 F AS/NO T FAS Control Bits

FAS/NOT FA S Si- and E-Bit Source

The Si bit can be used as an 8 kbits/s data link to and
from the remote end, or in the CRC-4 mode, it can be
used to provide added protection against false frame
alignment. The sources for the Si bits that are transmit­ted to the line are the following:

■

CEPT with no CRC-4 and FRM_PR28 bit 0 = 1: the
TSiF control bit (FRM_PR28 bit 1) is transmitted in
bit 1 of all FAS frames and the TSiNF control bit
(FRM_PR28 bit 2) is transmitted in bit 1 of all NOT
FAS frames.

■

The CHI system interface (CEPT with no CRC-4 and
FRM_PR28 bit 0 = 0)

■

This option requires the received system data (RCHI­DATA) to maintain a biframe alignment pattern where
frames containing Si bit information for the NOT FAS
frames have bit 2 of time slot 0 in the binary 1 state
followed by frames containing Si bit information for
the FAS frames that have bit 2 of time slot 0 in the
binary 0 state. This ensures the proper alignment of
the Si received system data to the transmit line Si
data. Whenever this requirement is not met by the
system, the transmit framer will enter a loss of
biframe alignment condition (indication is given in the
status registers) and then search for the pattern; in
the loss of biframe alignment state, transmitted line
data is corrupted (only when the system interface is
sourcing Sa or Si data). When the transmit framer
locates a new biframe alignment pattern, an indica­tion is given in the status registers and the transmit
framer resumes normal operations.

* Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system

transparently, FRM_PR29 must first be momentarily written to
001xxxxx (binary). Otherwise, the transmit framer will not be able
to locate the biframe alignment.

*

.

56 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

■

CEPT Time Slot 0 F AS/NOT FAS Control
Bits

(continued)

■

CEPT with CRC-41: manual transmission of E bit = 0:
— If FRM_PR28 bit 0 = 0, then the TSiF bit

(FRM_PR28 bit 1) is transmitted in bit 1 of frame
13 (E bit) and the TSiNF bit (FRM_PR28 bit 2) is
transmitted in bit 1 of frame 15 (E bit).

— If FRM_PR28 bit 0 = 1, then each time 0 is written

into TSiF (FRM_PR28 bit 1) one E bit = 0 is trans­mitted in frame 13, and each time 0 is written into
TSiNF (FRM _PR 28 bi t 2) one E bi t = 0 i s tr a nsmi t­ted in frame 15.

■

CEPT with CRC-41, automatic transmission of
E bit = 0:
— Optionally, one transmitted E bit is set to 0 by the

transmit framer, as described in ITU Rec. G.704
Section 2.3.3.4, for each received errored CRC-4
submultiframe detected by the receive framer if
FRM_PR28 bit 3 = 1.

— Optionally, as described in ITU Rec. G.704 Sec-

tion 2.3.3.4, both E bits are set to 0 while in a
received loss of CRC-4 multiframe alignment

2

state

if FRM_PR28 bit 4 = 1.

— Optionally, when the 100 ms or 400 ms timer is

enabled and the timer has expired, as described
in ITU Rec. G.706 Section B.2.2, both E bits are
set to 0 for the duration of the loss of CRC-4 multi­frame alignment state

Otherwise, the E bits are transmitted to the line in the 1
state.

2

if FRM_PR28 bit 5 = 1.

Optionally for the following alarm conditions as
selected through programming register FRM_PR27.
— The duration of loss of basic frame alignment as

described in ITU Rec. G.706 Section 4.1.1
ITU Rec. G.706 Section 4.3.2

4

if register

3

, or

FRM_PR27 bit 0 = 1.

— The duration of loss of CRC-4 multiframe align-

ment if register FRM_PR27 bit 2 = 1.

— The duration of loss of signaling time slot 16 multi-

frame alignment if register FRM_PR27 bit 1 = 1.

— The duration of loss of CRC-4 multiframe align-

ment after either the 100 ms or 400 ms timer
expires if register FRM_PR27 bit 3 = 1.

— The duration of receive Sa6_8hex

5

if register

FRM_PR27 bit 4 = 1.

— The duration of receive Sa6_Chex

5

if register

FRM_PR27 bit 5 = 1.

NOT FAS Sa-Bit Sources

6

The Sa bits, Sa4—Sa8, in the NOT F AS fr ame can be a
4 kbits/s data link to and from the remote end. The
sources and value for the Sa bits are as follows:

■

The Sa source register FRM_PR29 bit 0—bit 4 if
FRM_PR29 bit 7—bit 5 = 000 (binary) and
FRM_PR30 bit 4—bit 0 = 11111 (binary).

■

The facility data link external input (TFDL) if register
FRM_PR29 bit 7 = 1 and register FRM_PR21
bit 6 = 1.

■

The internal FDL-HDLC if register FRM_PR29
bit 7 = 1 and register FRM_PR21 bit 6 = 0.

■

NOT FAS A-Bit (CEPT Remote Frame Alarm) Sources

The A bit, as described in ITU Rec. G.704 Section

2.3.2, Table 4a/G.704, is the remote alarm indication
bit. In undisturbed conditions, this bit is set to 0 and
transmitted to the line. In the loss of frame alignment
(LFA) state, this bit may be set to 1 and transmitted to
the line as determined by register FRM_PR27. The A
bit is set to 1 and transmitted to the line for the following
conditions:

■

Setting the transmit A bit = 1 control bit by setting
register FRM_PR27 bit 7 to 1.

Lucent Technologies Inc. 57

Lucent Technologies Inc.

The Sa transmit stack if register FRM_PR29
bit 7—bit 5 are set to 01x (binary).

1. The receive E-bit processor will halt the monitoring of received E
bits during loss of CRC-4 multiframe alignment.

2. Whenever loss of frame alignment occurs, then loss of CRC-4
multiframe alignment is forced. Once frame alignment is estab­lished, then and only then, is the search for CRC-4 multiframe
alignment initiated. The receive framer unit, when programmed for
CRC-4, can be in a state of LFA and LTS0MFA or in a state of
LTS0MFA only, but cannot be in a state of LFA only.

3. LFA is due to framing bit errors.

4. LFA is due to detecting 915 out of 1000 received CRC-4 errored
blocks.

5. See Table 29 . Sa6 Bit Coding Recognized by the Receive Framer,
for a definition of this Sa6 pattern.

6. Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system
transparently, FRM_PR29 must first be momentarily written to
001xxxxx (binary). Otherwise, the transmit framer will not be able
to locate the biframe alignment.

Preliminary Data Sheet
TFRA08C13 OCTA L T1/E1 Framer October 2000

CEPT Time Slot 0 FAS/NOT FAS Control
Bits

(continued)

■

The CHI system interface if register FRM_PR29 bit
7—bit 5 are set to 001 (binary). This option requires
the received system data (RCHIDATA) to maintain a
biframe alignment patter n where (1 ) frames contain ­ing Sa bit information have bit 2 of time slot 0 in the
binary 1 state and (2) these NOT FAS frames are fol­lowed by frames not containing Sa bit information,
the FAS frames, which have bit 2 of time slot 0 in the
binary 0 state. This ensures the proper alignment of
the Sa received system data to the transmit line Sa
data. Whenever this requirement is not met by the
system, the transmit framer will enter a loss of
biframe alignment condition indicated in the status
register, FRM_SR1 bit 4, and then search for the pat­tern. In the loss of biframe alignment state, transmit­ted line data is corrupted (only when the system
interface is sourcing Sa or Si data). When the trans­mit framer locates a new biframe alignment pattern,
an indication is given in the status registers and the
transmit framer resumes normal operations.

The receive Sa data is present at the following:

■

The Sa received stack, registers FRM_SR54—
FRM_SR63, if the TFRA08C13 is programmed in the
Sa stack mode.

The status of the received Sa bits and the received Sa
stack is available in status register FRM_SR4. The
transmit and receive Sa bit for the FDL can be selected
by setting register FRM_PR43 bit 0—bit 2 as shown in
Table 148.

Sa Facility Data Link Access

The data link interface may be used to source one of
the Sa bits. Access is controlled by registers
FRM_PR29, FRM_PR30, and FRM_PR43, see NOT
F AS Sa-Bit Sources on page 57. The receive Sa data is
always present at the receive facility data link output
pin, RFDL, along with a valid clock signal at the receive
facility clock output pin, RFDLCK. During a loss of
frame alignment (LFA) state, the RFDL signal is forced
to a 1 state while RFDLCK continues to toggle on the
previous frame alignment. When basic frame alignment
is found, RFDL is as received from the selected receive
Sa bit position and RFDLCK is forced (if necessary) to
the new alignment. The data rate for this access mode
is 4 kHz. The access timing for the transmit and receive
facility data is illustrated in Figure 15 below . During loss
of receive clock (LOFRMRLCK), RFDL and RFDLCK
are frozen in a state at the point of the LOFRMRLCK
being asserted.

■

The system transmit interface.

TFDLCK

TFDL

RFDLCK

RFDL

Figure 15. Facility Data Link Access Timing of the Transmit and Receive Framer Sections

in the CEPT Mode

t11

t8

t8: TFDLCK CYCLE = 250 µs

t9

t10

t9

t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns

t10: RFDLCK CYCLE = 250 µs

t11: RFDLCK TO RFDL DELAY = 40 ns

5-3910(F).dr.1

5858 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

CEPT Time Slot 0 FAS/NOT FAS Control Bits

(continued)

NOT FAS Sa Stack Source and Destination

The transmit Sa4 to Sa8 bits may be sourced from the transmit Sa stack, registers FRM_PR31—FRM_PR40. The
Sa stack consists of ten 8-bit registers that contain 16 NOT FAS frames of Sa information as shown in Table 22.
The transmit stack data may be transmitted either in non-CRC-4 mode or in CRC-4 mode to the line.

The receive stack data, registers FRM_SR54—FRM_SR63, is valid in both the non-CRC-4 mode and the CRC-4
mode. In the non-CRC-4 mode while in the loss of frame alignment (LFA) state, updating of the receive Sa stack is
halted and the transmit and receive stack interrupts are deactivated. In the CRC-4 mode while in the loss of time
slot 0 multiframe alignment (LTS0MFA) state, updating of the receive Sa stack is halted and the transmit and
receive stack interrupts are deactivated.

Table 22. Transmit and Receive Sa Stack Structure

Register

Number

1 Sa4-1 Sa4-3 Sa4-5 Sa4-7 Sa4-9 Sa4-11 Sa4-13 Sa4-15
2 Sa4-17 Sa4-19 Sa4-21 Sa4-23 Sa4-25 Sa4-27 Sa4-29 Sa4-31
3 Sa5-1 Sa5-3 Sa5-5 Sa5-7 Sa5-9 Sa5-11 Sa5-13 Sa5-15
4 Sa5-17 Sa5-19 Sa5-21 Sa5-23 Sa5-25 Sa5-27 Sa5-29 Sa5-31
5 Sa6-1 Sa6-3 Sa6-5 Sa6-7 Sa6-9 Sa6-11 Sa6-13 Sa6-15
6 Sa6-17 Sa6-19 Sa6-21 Sa6-23 Sa6-25 Sa6-27 Sa6-29 Sa6-31
7 Sa7-1 Sa7-3 Sa7-5 Sa7-7 Sa7-9 Sa7-11 Sa7-13 Sa7-15
8 Sa7-17 Sa7-19 Sa7-21 Sa7-23 Sa7-25 Sa7-27 Sa7-29 Sa7-31
9 Sa8-1 Sa8-3 Sa8-5 Sa8-7 Sa8-9 Sa8-11 Sa8-13 Sa8-15

10 Sa8-17 Sa8-19 Sa8-21 Sa8-23 Sa8-25 Sa8-27 Sa8-29 Sa8-31

Bit 7

(MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

+

Bit 0

(LSB)

The most significant bit of the first byte is transmitted to the line in frame 1 of a double CRC-4 multiframe. The least
significant bit of the second byte is transmitted to the line in frame 31 of the double CRC-4 multiframe. The protocol
for accessing the Sa Stack information for the transmit and receive Sa4 to Sa8 bits is shown in Figure 16 and
described briefly below.

The device indicates that it is ready for an update of its transmit stack by setting register FRM_SR4 bit 7 (CEPT
transmit Sa stack ready) high. At this time, the system has about 4 ms to update the stack. Data written to the stack
during this interval will be transmitted during the next double CRC-4 multiframe. By reading register FRM_SR4
bit 7, the system clears this bit so that it can indicate the next time the transmit stack is ready. If the transmit stack
is not updated, then the content of the stack is retransmitted to the line. The 32-frame interval of the transmit framer
in the non-CRC-4 mode is arbitrary. Enabling transmit CRC-4 mode forces the updating of the internal transmit
stack at the end of the 32-frame CRC-4 double multiframe; the transmit Sa stack is then transmitted synchronous
to the transmit CRC-4 multiframe structure.

On the receive side, the TFRA08C13 indicates that it has received data in the receive Sa stack, register
FRM_SR54—FRM_SR63, by setting register FRM_SR4 bit 6 (CEPT receive Sa stack ready) high. The system
then has about 4 ms to read the contents of the stack before it is updated again (old data lost). By reading register
FRM_SR4 bit 6, the system clears this bit so that it can indicate the next time the receive stack is ready. The
receive framer always updates the content of the receive stack so unread data will be overwritten. The last 16 valid
Sa4 to Sa8 bits are always stored in the receive Sa stack on a double-multiframe boundary. The 32-frame interval
of the receive framer in the non-CRC-4 mode is arbitrary . Enab ling the receive CRC-4 mode forces updating of the
receive Sa stack at the end of the 32-frame CRC-4 double multiframe. The receive Sa stack is received synchro­nous to the CRC-4 multiframe structure.

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

CEPT Time Slot 0 FAS/NOT FAS Control Bits

SYSTEM ACCESS Sa STACK (SASS) INTERVAL:

1)

TRANSMIT FRAMER UNIT TRANSMITS TO THE LINE
THE DATA IN THE TRANSMIT Sa STACK WRITTEN DURING
THE PREVIOUS SASS INTERVAL.

2)

THE SYSTEM CAN UPDATE THE TRANSMIT Sa STACK
REGISTERS FOR TRANSMISSION IN THE NEXT CRC-4
DOUBLE MULTIFRAME.

3)

THE SYSTEM CAN READ THE RECEIVE Sa STAC K R EGISTERS
TO ACCESS THE Sa BITS EXTRA C TE D DURING T H E PRE VI OU S
VALID (IN MULTIFRAME ALIGNMENT) DOUBLE CRC-4
MULTIFRAME.

START OF CRC-4 DOUBLE MULTIFRAME:

• BASIC FRAME ALIGNMENT FOUND, OR,

• CRC-4 MULTIFRAME ALIGNMENT FOUND.

31 FRAMES

CRC-4 DOUBLE MULTIFRAME

(DMF): 32 FRAMES

START FRAME 1 OF 32 IN DMF. INTERNAL Sa STACK UPDATE INTERVAL

SYSTEM ACCESS Sa STACK INTERVAL

1 FRAME

CRC-4 DOUBLE MULTIFRAME: 32 FRAMES

(continued)

1-FRAME INTERVAL

31 FRAMES

SYSTEM ACCESS IS DISABLED DURING THIS INTERVAL:

THE INTERNAL TRANSMIT Sa STACK IS UPDATED

1)
FROM THE FRAMER UNIT’S 10-by te TRANSMIT STACK CONTROL
REGISTERS DURING THIS 1-FRAME INTERVAL.

ACCESS TO THE STACK CONTROL REGISTERS IS DISABLED

2)
DURING THIS 1-FRAME INTERVAL.

3)

ONCE LOADED, THE INFORMATION IN THE INTERNAL TRANSMIT
Sa STACK IS TRANSMITTED TO THE LINE DURING THE NEXT
CRC-4 DOUBLE MULTIFRAME, ALIGNED TO THE CRC-4 MULTIFRAME.

4)

IF THE TRANSMIT Sa STACK IS NOT UPDATED, THEN THE
CONTENT OF THE TRANSMIT Sa STACKS IS RETRANSMITTED
TO THE LINE.

5)

THE SYSTEM READ-ONLY RECEIVE STACK IS UPDATED FROM
THE INTERNAL RECEIVE STACK INFORMATION REGISTERS.

6)

IN NON-CRC-4 MODE, THE RECEIVE Sa STACK EXTRACTING
CIRCUITRY ASSUMES AN ARBITRARY DOUBLE 16-FRAME MULTIFRAME STRUCTURE
(32 FRAMES), AND DATA IS EXTRACT ED ONLY IN THE FRAME ALIGNED STATE.

7)

IN CRC-4 MODE, THE RECEIVE Sa STACK INFORMATION IS ALIGNED
TO A CRC-4 DOUBLE MULTIFRAME STRUCTURE (32 FRAMES), AND THE
DATA IS EXTRACTED ONLY IN CRC-4 MULTIFRAME ALIGNED STATE.

Figure 16. Transmit and Receive Sa Stack Accessing Protocol

5-3911(F).c

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

CEPT Time Slot 0 F AS/NOT FAS Control
Bits

(continued)

Interrupts indicating that the transmit Sa stack or the
receive Sa stack are ready for system access are avail­able, see register FRM_SR4 bit 6 and bit 7.

CEPT Time Slot 16 X0—X2 Control Bits

Each of the three X bits in frame 0 of the time slot 16
multiframe can be used as a 0.5 kbits/s data link to and
from the remote end. The transmitted line X bits are
sourced from control register FRM_PR41 bit 0—bit 2.
In the loss of TS16 multiframe alignment (LTS16MFA)
state, receive X bits are set to 1 in status register
FRM_SR53.

Signaling Access

Signaling information can be accessed by three differ­ent methods: transparently through the CHI, via the
control registers, or via the CHI associated signaling
mode.

The receive-channel robbed-bit signaling mode is
always defined by the state of the F and G bits in the
corresponding transmit signaling registers for that
channel. The received signaling data is stored in the
receive signaling registers, FRM_RSR0—
FRM_RSR23, while receive framer is in both the frame
and superframe alignment states. Updating the receive
signaling registers can be inhibited on-demand, by set­ting register FRM_PR44 bit 3 to 1, or automatically
when either a framing error event, a loss of frame, or
superframe alignment state is detected or a controlled
slip event occurs. The signaling inhibit state is valid for
at least 32 frames after any one of the following: a
framing errored event, a loss of frame and/or super­frame alignment state, or a controlled slip event.

In the common channel signaling mode, data written in
the transmit signaling registers is transmitted in chan­nel 24 of the transmit line bit stream. The F and G bits
are ignored in this mode. The received signaling data
from channel 24 is stored in receive signaling registers
FRM_RSR0—FRM_RSR23 for T1.

Associated Signaling Mode

This mode is enabled by setting register FRM_PR44 bit
2 to 1.

Transparent Signaling

This mode is enabled by setting register FRM_PR44 bit
0 to 1.

Data at the received RCHIDATA interface passes
through the framer undisturbed. The framer generates
an arbitrary signaling multiframe in the transmit and
receive directions to facilitate the access of signaling
information at the system interface.

DS1: Robbed-Bit Signaling

Microprocessor Control Registers

To enable signaling, register FRM_PR44 bit 0 must be
set to 0 (default).

The information written into the F and G bits of the
transmit signaling registers, FRM_TSR0—
FRM_TSR23, define the robbed-bit signaling mode for
each channel for both the transmit and receive direc­tions. The per-channel programming allows the system
to combine voice channels with data channels within
the same frame.

Signaling information in the associated signaling mode
(ASM) is allocated an 8-bit system time slot in conjunc­tion with the payload data information for a particular
channel. The default system data rate in the ASM
mode is 4.096 Mbits/s. Each system channel consists
of an 8-bit payload time slot followed by its correspond­ing 8-bit signaling time slot. The format of the signaling
byte is identical to that of the signaling registers.

In the ASM mode, writing the transmit signaling regis­ters will corrupt the transmit signaling data. In the trans­mit signaling register ASM (TSR-ASM) format, enabled
by setting register FRM_PR44 bit 2 and bit 5 to 1, the
system must write into the F and G bit
signaling registers to program the robbed-bit signaling
state mode of each DS0. The ABCD bits are sourced
from the RCHI ports when TSR-ASM mode is enabled.

* All other bits in the signaling registers are ignored, while the F and

G bits in the received RCHIDATA stream are ignored.

*

of the transmit

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Signaling Access

(continued)

Table 23 illustrates the ASM time-slot format for valid channels.

Table 23. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames

DS1: ASM CHI Time Slot

PAYLOAD DATA SIGNALING INFORMATION*

12345678ABCDXFGP

* X indicates bits that are undefined by the fr amer.
† The identical sense of the received system P bit in the transmitted signaling data is echoed back to the system in the received

signaling information.

†

The DS1 framing formats require rate adaptation from the line-interface 1.544 Mbits/s bit stream to the system­interface 4.096 Mbits/s bit stream. The rate adaptation results in the need for stuffed time slots on the system inter­face. Table 24 illustrates the ASM format for T1 stuffed channels used by the TFRA08C13. The stuffed data byte
contains the programmable idle code in register FRM_PR23 (default = 7F (hex)), while the signaling byte is
ignored.

Table 24. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels

ASM CHI Time Slot

PAYLOAD DATA SIGNALING INFORMATION*

01111111XXXXXXXX

* X indicates bits which are undefined by the framer.

CEPT: Time Slot 16 Signaling

Microprocessor Control Registers

To enable signaling, register FRM_PR44 bit 0 must be set to 0 (default).
The information written into transmit signaling control registers FRM_TSR0—FRM_TSR31 define the state of the

ABCD bits of time slot 16 transmitted to the line.
The received signaling data from time slot 16 is stored in receive signaling registers FRM_RSR0—FRM_RSR31.

Associated Signaling Mode

Signaling information in the associated signaling mode (ASM), register FRM_PR44 bit 2 = 1, is allocated an 8-bit
system time slot in conjunction with the data information for a particular channel. The default system data rate in
the ASM mode is 4.096 Mbits/s. Each system channel consists of an 8-bit payload time slot followed by its associ­ated 8-bit signaling time slot. The format of the signaling byte is identical to the signaling registers.

Table 25 illustrates the ASM time-slot format for valid CEPT E1 time slots

Table 25. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT

CEPT ASM CHI Time Slot

PA YLOAD DATA SIGNALING INFORMATION

12345678ABCDEX

* In the CEPT formats, these bits are undefined.
† The P bit is the parity-sense bit calculated over the 8 data bits, the ABCD (and E) bits, and the P bit. The identical sense of the received

system P bit in the transmitted signaling data is echoed back to the system in the received signaling information.

62 Lucent Technologies Inc.

*

Lucent Technologies Inc.

*

X

†

P

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Auxiliary Framer I/O Timing

Transmit and receive timing and data signals are provided by terminals RFRMCK (receive framer clock), RFRM­DATA (receive framer data), RFS (receive frame sync), RSSFS (receive framer signaling superframe sync), RCRC­MFS (receive frame CRC-4 multiframe sync), TFS (transmit framer frame sync), TSSFS (transmit framer signaling
superframe sync), TCRCMFS (transmit framer CRC-4 multiframe sync).

The receive signals are synchronized to the recovered receive line clock, RLCK, and the transmit signals are syn­chronized to the transmit line clock, TLCK. Note that TLCK must be phase locked to the CHI clock, CHICK, see
Table 2. Pin Descriptions, pin D18.

Detailed timing specifications for these signals are given in Figure 17—Figure 24.

RFRMCK

125 µs

RFS

TLCK

TFS

TPD

(SINGLE

RAIL)

RFRMDATA

BIT 0

BIT 7 BIT 1

DATA VALID

TIME SLOT 1TIME SLOT 24

Figure 17. Timing Specification for RFRMCK, RFRMDATA, and RFS in DS1 Mode

125 µs

F

BIT

BIT 0

(MSB)

TS1

TS2 TS24

F

BIT

BIT 0

(MSB)

Figure 18. Timing Specification for TFS, TLCK, and TPD in DS1 Mode

5-6290(F)r.6

TS1

5-6292(F)r.7

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Auxiliary Framer I/O Timing

RFRMCK

RFS

BIT 0

RFRMDATA

Figure 19. Timing Specification for RFRMCK, RFRMDATA, and RFS in CEPT Mode

RFRMCK

BIT 7 BIT 1

DATA VALID

(continued)

125 µs

FAS/NFAS: TIME SLOT 0TIME SLOT 31

5-6294(F)r.6

RFS

RSSFS

RFRMDATA

125 µs

2 ms

TS0 OF THE FRAME AFTER THE

FRAME CONTAINING THE

SIGNALING MULTIFRAME

PATTERN (0000)

TS0 OF THE FRAME AFTER THE

FRAME CONTAINING THE

SIGNALING MULTIFRAME

PATTERN (0000)

Figure 20. Timing Specification for RFRMCK, RFRMDATA, RFS, and RSSFS in CEPT Mode

5-6295(F)r.8

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Auxiliary Framer I/O Timing

RFRMCLK

RFS

RCRCMFS

RFRMDATA

TS0 OF FRAME #0

OF MULTIFRAME

Figure 21. Timing Specification for RCRCMFS in CEPT Mode

TLCK

(continued)

2 ms

TS0 OF FRAME #0

OF MULTIFRAME

5-6296(F)r.5

TFS

TPD

(SINGLE

RAIL)

125 µs

TS0 OF FRAME X

TS0 OF FRAME X + 1

Figure 22. Timing Specification for TFS, TLCK, and TPD in CEPT Mode

5-6297(F)r.5

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Auxiliary Framer I/O Timing

TFS

11 CLOCK CYCLES

TLCK

TSSFS

TPD

(SINGLE

RAIL)

Figure 23. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode

(continued)

2 ms

TS0 OF THE FRAME

CONTAINING THE SIGNALING

MULTIFRAME PATTERN (0000)

5-6298(F)r.5

TLCK

TFS

TCRCMFS

TPD

(SINGLE

RAIL)

1 ms

TS0 OF FRAME #0

OF MULTIFRAME

TS0 OF FRAME #0

OF MULTIFRAME

1 ms

TS0 OF FRAME #8

OF MULTIFRAME

Figure 24. Timing Specification for TFS, TLCK, TPD, and TCRCMFS in CEPT Mode

5-6299(F)r.5

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Alarms and Performance Monitoring

Interrupt Generation

A global interrupt (pin AD8) may be generated if enabled by register GREG1. This interrupt is clocked using chan­nel 1 framer receive line clock (RLCK1). If RLCK1 is absent, the interrupt is clocked using RLCK2, the receive line
clock of channel 2. If both RLCK1 and RLCK2 are absent, clocking of interrupts is controlled by an interval

2.048 MHz clock generated from the CHI clock. Timing of the interrupt is shown in Figure 25. There is no relation
between MPCK (pin AE10) and the interrupt, i.e., MPCK maybe asynchronous with any of the other TFRA08C13
clocks.

RLCK1

INTERRUPT

(PIN AD8)

5-6563(F).ar.1

Figure 25. Relation Between RLCK1 and Interrupt (Pin AD8)

Alarm Definition

The receive framer monitors the receive line data for alarm conditions and errored events, and then presents this
information to the system through the microprocessor interface status registers. The transmit framer, to a lesser
degree, monitors the receive system data and presents the information to the system through the microprocessor
interface status registers. Updating of the status registers is controlled by the receive line clock signal. When the
receive loss of clock monitor determines that the receive line clock signal is lost, the system clock is used to clock
the status registers and all status information should be considered corrupted.

Although the precise method of detecting or generating alarm and error signals differs between framing modes, the
functions are essentially the same. The alarm conditions monitored on the received line interface are:

Red alarm

■

or the
frame alignment for the line has been lost and the data cannot be properly extracted. The red alarm is indicated
by the loss of frame condition for the various framing formats as defined in Table 26.

loss of frame alignment

indication (FRM_SR1 bit 0). The red alarm indicates that the receive

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Alarms and Performance Monitoring

(continued)

Table 26. Red Alarm or Loss of Frame Alignment Conditions

Framing Format Number of Errored Framing Bits That Will Cause a Red Alarm

(Loss of Frame Alignment) Condition

D4 2 errored frame bits (F

2 errored F

SLC

-96 2 errored frame bits (FT or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1.
2 errored F

bits out of 4 consecutive FT bits if PRM_PR10 bit 2 = 0.

T

bits out of 4 consecutive FT bits if FRM_PR10 bit 2 = 0.

T

DDS: Frame 3 errored frame bits (F
ESF 2 errored F

bits out of 4 consecutive FE bits or, optionally, 320 or more CRC6 errored

E

or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1.

T

or FS) or channel 24 FAS pattern out of 12 consecutive frame bits.

T

checksums within a one second interval if loss of frame alignment due to excessive CRC-6
errors is enabled in FRM_PR9.

CEPT Three consecutive incorrect FAS patterns or three consecutive incorrect NOT FAS patterns;

or optionally, greater than 914 received CRC-4 checksum errors in a one second interval if
loss of frame alignment due to excessive CRC-6 errors is enabled in FRM_PR9.

Yellow alarm

■

or the

remote frame alarm

(FRM_SR1 bit 0). This alarm is an indication that the line remote end
is in a loss of frame alignment state. Indication of remote frame alarm (commonly referred to as a yellow alarm)
as for the different framing formats is shown in Table 27.

Table 27. Remote Frame Alarm Conditions

Framing Format Remote Frame Alarm Format

Superframe: D4 Bit 2 of all time slots in the 0 state.
Superframe: D4-Japanese The twelfth (12th) framing bit in the 1 state in two out of three consecutive super-

frames.
Superframe: DDS Bit 6 of time slot 24 in the 0 state.
Extended Superframe (ESF) An alternating pattern of eight ones followed by eight 0s in the ESF data link.
CEPT: Basic Frame Bit 3 of the NOT FAS frame in the 1 state in three consecutive frames.
CEPT: Signaling Multiframe Bit 6 of the time slot 16 signaling frame in the 1 state.

Blue alarm

■

or the

alarm indication signal

(AIS). The alarm indication signal (AIS), sometimes referred to as the
blue alarm, is an indication that the remote end is out-of-service. Detection of an incoming alarm indication signal
is defined in Table 29.

68 Lucent Technologies Inc.

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Alarms and Performance Monitoring

(continued)

Table 28. Alarm Indication Signal Conditions

Framing Format Remote Frame Alarm Format

T1 Loss of frame alignment occurs and the incoming signal has two or fewer zeros in each of

two consecutive double frame periods (386 bits).

CEPT ETSI As described in ETSI ETS 300 233: May 1994, Section 8.2.2.4, loss of frame alignment

occurs and the framer receives a 512 bit period containing two or less binary zeros. This
is enabled by setting register FRM_PR10 bit 1 to 0.

CEPT ITU As described in ITU Rec. G.775, the incoming signal has two or fewer zeros in each of

two consecutive double frame periods (512 bits). AIS is cleared if each of two consecutive
double frame periods contains three or more zeros or frame alignment signal (FAS) has
been found. This is enabled by setting register FRM_PR10 bit 1 to 1.

SLIP

■

The
buffer’s write address pointer from the receive framer and the read address pointer from the transmit concentra­tion highway interface are equal

condition (FRM_SR3 bit 6 and bit 7). SLIP is defined as the state in which the receive elastic store

*

.

— The negative slip (Slip-N) alarm indicates that the receive line clock (RLCK) - transmit CHI clock (CHICK)

monitoring circuit detects a state of overflow caused by RLCK and CHICK being out of phase-lock and the
period of the received frame being less than that of the system frame. One system frame is deleted.

— The positive slip (Slip-P) alarm indicates the line clock (RLCK) - transmit CHI clock (CHICK) monitoring circuit

detects a state of underflow caused by RLCK and CHICK being out of phase-lock and the period of the
received frame being greater than that of the system frame. One system frame is repeated.

loss of framer receive clock

■

The

(LORLCK, pin G23). The LORLCK alarm is asserted high when an interval of
250 ms has expired with no transition of RLCK (pin see Table 2. Pin Descriptions) detected. The alarm is dis­abled on the first transition of RLCK. Bit 0—bit 2 of global register 8 (GREG8) determine which framer sources
the LORLCK pin (see Table 69 Interrupt Status Register (FRM_SR0) (Y00)).

loss of PLL clock

■

The

(LOPLLCK, pin F25). LOPLLCK alarm is asserted high when an interval of 250 ms has
expired with no transition of PLLCK (pin see Table 2 . Pin Descriptions) detected. The alarm is disabled 250 µs
after the first transition of PLLCK. Timing for LOPLLCK is shown in Figure 26. Bit 0—bit 2 of global register 8
(GREG8) determine which framer sources the LOPLLCK pin (see Table 69).

PLLCK

250 µs

LOPLLCK

CHICK

250 µs

Figure 26. Timing for Generation of LOPLLCK (Pin F25)

5-6564(F).a

* After a reset, the read and write pointers of the receive path elastic store will be set to a known state.

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Alarms and Performance Monitoring

(continued)

■

Received
bit 0. This alarm indicates any bipolar decoding error
or detection of excessive zeros.

■

Received
bit 3. In ESF, this alarm is asserted when 320 or
more CRC-6 checksum errors are detected within a
one second interval. In CEPT, this alarm is asserted
when 915 or more CRC-4 checksum errors are
detected within a one second interval.

■

The CEPT
(FRM_SR2 bit 2). CREBIT is asserted when the
receive framer detects the following:
— Five consecutive seconds where each 1 s interval

contains ≥991 received E bits = 0 events.
— Simultaneously no LFA occurred.
— Optionally, no remote frame alarm (A bit = 1) was

detected if register FRM_PR9 bit 0, bit 4, and bit 5

are set to 1.
— Optionally, neither Sa6-F

were detected if register FRM_PR9 bit 0, bit 4,

and bit 6 are set to 1.
The 5 s timer is started when the following occur s:
— CRC-4 multiframe alignment is achieved.
— And optionally, A = 0 is detected if register

FRM_PR9 bit 0, bit 4, and bit 5 are set to 1.
— And optionally , neither Sa6_F

detected if register FRM_PR9 bit 0, bit 4, and bit 6

are set to 1.
The 5 s counter is restarted when the following
occurs:
— LFA occurs, or
— ≥990 E bit = 0 events occur in 1 s, or
— Optionally, an A bit = 1 is detected if register

FRM_PR9 bit 0, bit 4, and bit 5 are set to 1.
— Optionally, a valid Sa6 pattern 1111 (binary) or

Sa6 pattern 1110 (binary) code was detected if

register FRM_PR9 bit 0, bit 4, and bit 6 are

set to 1.

bipolar violation errors

excessive CRC errors

continuous E-bit

alarm (CREBIT)

nor Sa6-E

hex

hex

alarm, FRM_SR3

alarm, FRM_SR3

codes

hex

*

nor Sa6_E

hex*

Failed state

■

alarm or the

FRM_SR5 bit 3 and bit 7 and FRM_SR6 bit 3 and bit

7. This alarm is defined as the unavailable state at
the onset of ten consecutive severely errored sec­onds. In this state, the receive framer inhibits incre­menting of the severely errored and errored second
counters for the duration of the unavailable state. The
receive framer deasserts the unavailable state condi­tion at the onset of ten consecutive errored seconds
which were not severely errored.

4-bit Sa6 codes

■

The

(FRM_SR2 bit 3—bit 7). Sa6
codes are asserted if three consecutive 4-bit pat­terns have been detected. The alarms are disabled
when three consecutive 4-bit Sa6 codes have been
detected that are different from the pattern previously
detected. The receive framer monitors the Sa6 bits
for special codes described in ETSI ETS 300 233:
May 1994, Section 9.2. The Sa6 codes are defined in
Table 29 and Table 30. The Sa6 codes in Table 29
may be recognized as an asynchronous bit stream in
either non-CRC-4 or CRC-4 modes as long as the
receive framer is in the basic frame alignment state.
In the CRC-4 mode, the receive framer can optionally
recognize the received Sa6 codes in Table 29 syn­chronously to the CRC-4 submultiframe structure as
long as the receive framer is in the CRC-4 multiframe
alignment state (synchronous Sa6 monitoring can be
enabled by setting register FRM_PR10 bit 1 to 1).
The Sa6 codes in Table 30 are only recognized syn-

is

chronously to the CRC-4 submultiframe and when
the receive framer is in CRC-4 multiframe alignment.
The detection of three (3) consecutive 4-bit patterns
are required to indicate a valid received Sa6 code.
The detection of Sa6 codes is indicated in status reg­ister FRM_SR2 bit 3—bit 7. Once set, any three-nib­ble (12-bit) interval that contains any other Sa6 code
will clear the current Sa6 status bit. Interrupts may be
generated by the Sa6 codes given in Table 29

* See Table 29, for the definition of this Sa6 pattern.

unavailable state alarm

,

This alarm is disabled during loss of frame alignment
(LFA) or loss of CRC-4 multiframe alignment
(LTS0MFA).

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Preliminary Data Sheet
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Alarms and Performance Monitoring

(continued)

Table 29. Sa6 Bit Coding Recognized by the Receive Framer

Code First Receive Bit (MSB) Last Received Bit (LSB)

Sa6_8
Sa6_A

Sa6_C

Sa6_E
Sa6_F

hex

hex
hex
hex

hex

100 0
101 0
110 0
111 0
111 1

Table 30 defines the three 4-bit Sa6 codes that are always detected synchronously to the CRC-4 submultiframe
structure, and are only used for counting NT1 events.

Table 30. Sa6 Bit Coding of NT1 Interface Events Recognized by the Receive Framer

Code First Receive Bit

(MSB)

Sa6_1
Sa6_2
Sa6_3

hex
hex
hex

000 1 E = 0 16
0 0 1 0 CRC-4 Error 16
0 0 1 1 CRC-4 Error & E = 0

Last Received Bit

(LSB)

Event at NT1 Counter Size

(bits)

—

This code will cause both

counters to increment.

The reference points for receive CRC-4, E-bit, and Sa6 decoding are illustrated in Figure 27

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Alarms and Performance Monitoring

NT2

(NT1 REMOTE)

E BIT = 0

T REFERENCE

POINT

CRC ERROR

DETECTED

CRC-4 ERRORS AT THE NT1
E BIT = 0, ERROR EVENT DETECTED AT THE NT1 REMOTE

NT1 ET

E BIT = 0

Sa6

CRC-4 ERRORS DETECTED FROM NT1 REMOTE, THEN SET Sa6 = 001X
E = 0 DETECTED FROM NT1 REMOTE, THEN SET Sa6 = 00X1

Figure 27. The T and V Reference Points for a Typical CEPT E1 Application

V REFERENCE

POINT

CRC ERROR

DETECTED

(continued)

CRC-4 ERRORS AT THE ET,
E BIT = 0, ERROR EVENT AT THE ET REMOTE

COUNT:

1) CRC ERRORS,

2) E = 0,

3) Sa6 = 001X, AND

4) Sa6 = 00X1

5-3913(F)r.8

CEPT auxiliary pattern alarm (AUXP) (FRM_SR1 bit 6).

■

The received auxiliary alarm, register FRM_SR1 bit 6
(AUXP), is asserted when the receive framer is in the LFA state and has detected more than 253 10 (binary) pat­terns for 512 consecutive bits. In a 512-bit interval, only two 10 (binary) patterns are allowable for the alarm to be
asserted and maintained. The 512-bit interval is a sliding window determined by the first 10 (binary) pattern
detected. This alarm is disabled when three or more 10 (binary) patterns are detected in 512 consecutive bits.
The search for AUXP is synchronized with the first alternating 10 (binary) pattern as shown in Table 31.

Table 31. AUXP Synchronization and Clear Sychronization Process

00 10 10 01 11 11 00 00 0 10 00 10

— sync — — — clear sync — — — sync . . . . . .

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Alarms and Performance Monitoring

(continued)

Event Counters Definition

The error events monitored in the receive framer’s status registers are defined in Table 32 for the hardwired
(default) threshold values. The errored second and severely errored second threshold registers can be pro­grammed through FRM_PR11—FRM_PR13 such that the errored and severely errored second counters function
as required by system needs. DS1 errors are reported in the ET Error registers, FRM_SR20 through FRM_SR35.
For the framer to correctly report coding and BPV errors, the LIU/Framer interface must be configured as dual rail
mode.

Table 32. Event Counters Definition

Error Event Functional Mode Definition Counter Size

(bits)

Bipolar
Violations
(BPVs)

Frame
Alignment Erro rs
(FERs)

CRC Checksum
Errors

Excessive CRC
Errors

Received
E bits = 0

Errored Second
Events

AMI Any bipolar violation or 16 or more consecutive zeros 16
B8ZS Any BPV, code violation, or any 8-bit interval with no

one pulse

CEPT HDB3 Any BPV, code violation, or any 4-bit interval with no

one pulse

SF: D4 Any F

F

SLC

SF:

SF: DDS Any F
ESF Any F
CEPT Any FAS (0011011) or NOT FAS (bit 2) bit error if

ESF or CEPT with CRC Any received checksum in error 16

ESF
CEPT with CRC
CEPT with CRC-4 E bits = 0 in frame 13 and frame 15 16

All Any one of the relevant error conditions enabled in

DS1: non-ESF Any framing bit errors within a one second interval
DS1: ESF Any CRC-6 errors within a one second interval
CEPT without CRC-4 Any framing errors within a one second interval
CEPT with CRC-4 (ET1) Any CRC-4 errors within a one second interval
CEPT with CRC-4

(ET1 remote)
CEPT with CRC-4 (NT1) Any Sa6 = 001x (binary) code event within a one

CEPT with CRC-4
(NT1 remote)

-96 Any FT or FS bit errors (FRM_PR10 bit 2 = 1) or any
F

register FRM_PR10, bit 2 = 0.
Any FAS (0011011) bit error if register FRM_PR10,
bit 2 = 1.

≥
≥

registers FRM_PR14—FRM_PR18 within a one
second inter val

Any E bit = 0 event within a one second interval

second inter val
Any Sa6 = 00x1 (binary) code event within a one

second inter val

or FS bit errors (FRM_PR10 bit 2 = 1) or any

T

bit errors (FRM_PR10 bit 2 = 0)

T

bit errors (FRM_PR10 bit 2 = 0)

T

, FS, or time slot 24 FAS bit error

T

bit error

E

320 checksum errors in a one second interval NONE
915 checksum errors in a one second interval

16

16

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Alarms and Performance Monitoring

Table 32. Event Counters Definition

Error Event Functional Mode Definition Counter Size

Bursty Errored
Second Events

Sev erely Errored
Second Events

Unavailable
Second Events

DS1: non-ESF Greater than 1 but less than 8 framing bit errors

DS1: ESF Greater than 1 but less than 320 CRC-6 errors within

CEPT without CRC-4 Greater than 1 but less than 16 framing bit errors

CEPT with CRC-4 (ET1) Greater than 1 but less than 915 CRC-4 errors within

CEPT with CRC-4 (ET1
remote)

CEPT with CRC-4 (NT1) Greater than 1 but less than 915 Sa6=001x (binary)

CEPT with CRC-4 (NT1
remote)

All Any one of the relevant error conditions enabled in

DS1: non-ESF 8 or more framing bit errors within a one second

DS1: ESF 320 or more CRC-6 errors within a one second

CEPT with no CRC-4 16 or more framing bit errors within a one second

CEPT with CRC-4 (ET1) 915 or more CRC-4 errors within a one second

CEPT with CRC-4
(ET1 remote)

CEPT with CRC-4 (NT1) 915 or more Sa6=001x (binary) code events within a

CEPT with CRC-4
(NT1 remote)

All A one second period in the unavailable state 16

(continued)

(continued)

(bits)

within a one second interval

a one second interval

within a one second interval

a one second interval
Greater than 1 but less than 915 E bit = 0 events

within a one second interval

code events within a one second interval
Greater than 1 but less than 915 Sa6=00x1 (binary)

code events within a one second interval

registers FRM_PR14—FRM_PR18 within a one
second inter val

interval

interval

interval

interval
915 or more E bit = 0 events within a one second

interval

one second interval
915 or more Sa6=00x1 (binary) code events within a

one second interval

16

16

The receive framer enters an unavailable state condition at the onset of ten consecutive severely errored second
events. When in the unavailable state, the receive framer deasserts the unavailable state alarms at the onset of ten
consecutive seconds which were not severely errored.

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

■

Alarms and Performance Monitoring

(continued)

Loopback and Transmission Modes

Primary Loopback Modes

Framer primary loopback mode is controlled by register
FRM_PR24. There are seven primary loopback and
transmission test modes supported:

■

Line loopback (LLB).

■

Board loopback (BLB).

■

Single time-slot system loopback (STSSLB).

■

Single time-slot line loopback (STSLLB).

■

CEPT nailed-up broadcast transmission (CNUBT).

■

Payload loopback (PLLB).

■

CEPT nailed-up connect loopback (CNUCLB).

The loopback and transmission modes are described in
detail below:

■

The LLB mode loops the receive line data and clock
back to the transmit line. The received data is pro­cessed by the receive framer and transmitted to the
system interface. This mode can be selected by set­ting register FRM_PR24 to 001xxxxx (binary).

■

The BLB mode loops the receive system data back
to the system after:
— The transmit framer processes the data, and
— The receive framer processes the data.

In the BLB mode, AIS is always transmitted to the line
interface. This mode can be selected by setting register
FRM_PR24 to 010xxxxx (binary).

■

The STSSLB mode loops one and only one received
system time slot back to the transmit system inter­face. The selected looped back time-slot data is not
processed by either the transmit framer or the
receive framer. The selected time slot does not pass
through the receive elastic store buffer and therefore
will not be affected by system-AIS, RLFA conditions,
or controlled slips events. Once selected, the desired
time-slot position has the programmable idle code in
register FRM_PR22 transmitted to the line interface
one frame before implementing the loopback and for
the duration of the loopback. This mode can be
selected by setting register FRM_PR24 to
011A

4A3A2A1A0

address of the selected time slot.

, where A4A3A2A1A0 is the binary

The STSLLB mode loops one and only one received
line time slot back to the transmit line. The selected
time-slot data is looped to the line after being pro­cessed by the receive framer, and it passes through
the receive elastic store. The selected time slot has
the programmable idle code in register FRM_PR22
transmitted to the system interface one frame before
implementing the loopback and for the duration of the
loopback. In CEPT, selecting time slot 0 has the
effect of deactivating the current loopback mode
while no other action will be taken (time slot 0 will not
be looped back to the line and should not be cho­sen). This mode can be selected by setting register
FRM_PR24 to 100A

4A3A2A1A0

, where A4A3A2A1A0

is the binary address of the selected time slot.

■

The CNUBT mode transmits received-line time slot X
to the system in time slot X and time slot 0 (of the
next frame). Any time slot can be broadcast. This
mode can be selected by setting register FRM_PR24
to 101A

4A3A2A1A0

where A4A3A2A1A0 is the binary

address of the selected time slot.

■

The PLLB mode loops the received line data and
clock back to the transmit line while inserting (replac­ing) the facility data link in the looped back data. Two
variations of the payload loopback are available. In
the pass-through framing/CRC bit mode (chosen by
setting register FRM_PR24 to 111xxxxx (binary)),
the framing and CRC bits are looped back to the line
transmit data. In the regenerated framing/CRC bit
mode (chosen by setting register FRM_PR24 to
110xxxxx (binary) and register FRM_PR10 bit
3 to 0), the framing and CRC bits are regenerated by
the transmit framer. The payload loopback is only
available for ESF and CEPT modes.

■

The CNUCLB mode loops received system time slot
X back to the system in time slot 0. The selected time
slot is not routed through the receive elastic store
buffer and, therefore, will not be affected by system­AIS, RLFA conditions, or controlled slips. Any time
slot can be looped back to the system. Time slot X
transmitted to the line is not affected by this loopback
mode. Looping received system time slot 0 has no
effect on time slot 0 transmitted to the line, i.e., the
transmit framer will always overwrite the FAS and
NOT FAS data in time slot 0 transmitted to the line.
This mode can be selected by setting register
FRM_PR24 to 110A

4A3A2A1A0

FRM_PR10 bit 3 to 1, where A

and register

4A3A2A1A0

is the

binary address of the selected time slot.

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Alarms and Performance Monitoring

(continued)

Secondary Loopback Modes

There are two secondary loopback modes supported:

■

Secondary-single time-slot system loopback (S-STSSLB).

■

Secondary-single time-slot line loopback (S-STSLLB).

The loopbacks are described in detail below:

■

The secondary-STSSLB mode loops one and only one received system time slot back to the transmit system
interface. The selected time-slot data looped back is not processed by either the transmit framer or the receive
framer. The selected time slot does not pass through the receive elastic store buffer and therefore will not be
affected by system-AIS, RLFA conditions, or controlled slips events. Whenever the secondary loopback register
is programmed to the same time slot as the primary register, the primary loopback mode will control that time
slot. Once selected, the desired time-slot position has the programmable line idle code in register FRM_PR22
transmitted to the line interface one frame before implementing the loopback and for the duration of the loopback.

■

The secondary-STSLLB mode loops one and only one line time slot back to the line. The selected time slot data
is looped to the line after being processed by the receive framer and it passes through the receive elastic store.
The selected time slot has the programmable idle code in register FRM_PR22 transmitted to the system inter­face one frame before implementing the loopback and for the duration of the loopback. In CEPT, selecting time
slot 0 has the effect of deactivating the current loopback mode while no other action will be taken (time slot 0 will
not be looped back to the line and should not be chosen in this mode).

Table 33 defines the deactivation of the two secondary loopback modes as a function of the activation of the pri­mary loopback and test transmission modes.

Table 33. Summary of the Deactivation of SSTSSLB and SSTSLLB Modes as a Function of Activating the

Primary Loopback Modes

Primary Loopback Mode Deactivation of S-STSSLB Deactivation of S-STSLLB

STSSLB If primary time slot = secondary If primary time slot = secondary
STSLLB If primary time slot = secondary If primary time slot = secondary

BLB Always Always

CNUBT If the secondary time slot is TS0 or if the

If primary time slot = secondary

primary time slot = secondary

LLB Always Always

NUCLB If the secondary time slot is TS0 or if the

If primary time slot = secondary

primary time slot = secondary

PLLB Always Always

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Alarms and Performance Monitoring

(continued)

Figure 28 illustrates the various loopback modes implemented by each framer unit.

RECEIVE SYSTEM DAT A

IS IGNORED

LINE

(1) LINE LOOPBACK

TRANSMIT PROGRAMMABLE LINE IDLE CODE

LINE

(3) SINGLE TIME-SLOT SYSTEM LOOPBACK

IN REGISTER FRM_PR22

FRAMER

LOOPBACK TS-X

ES

SYSTEM

SYSTEM

AIS

LINE

LINE

FRAMER

(2) BOARD LOOPBACK

TRANSMIT PROGRAMMA BLE IDLE CODE

IN REGISTER FRM_PR22

IN OUTGOING SYSTEM TS-XIN OUTGOING LINE TS-X

INSERT ONLY TIME SLOT X

(4) SINGLE TIME-SLOT LINE LOOPBACK

SYSTEM

ES

SYSTEM

ES

FRAMER

LINE

TRANSMIT LINE TS-X IN

SYSTEM TS-X AND SYSTEM TS -0

(5) CEPT NAILED-UP BROADCAS T TRANS MI SS ION

ES

LINE

(7) CEPT NAILED-UP CONNECT LOOPBACK

SYSTEM

FRAMER

LOOPBACK TS-X IN TS-0

Figure 28. Loopback and Test Transmission Modes

ES

LINE

TRANSMIT FRAMER

SYSTEM

(6) PAYLOAD LINE LOOPBACK

SYSTEM

5-3914(F).d

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Alarms and Performance Monitoring

(continued)

Line Test Patterns

Test patterns may be transmitted to the line through either register FRM_PR20 or register FRM_PR69. Only one of
these sources may be active at the same time. Signaling must be inhibited while sending these test patterns.

Transmit Line Test Patterns—Using Register FRM_PR20

The transmit framer can be programmed through register FRM_PR20 to transmit various test patterns. These test
patterns, when enabled, overwrite the received CHI data. The test patterns available using register FRM_PR20
are:

■

The unframed-AIS pattern which consists of a continuous bit stream of ones (. . . 111111 . . .) enabled by setting
register FRM_PR20 bit 0 to 1.

■

The unframed-auxiliary pattern which consists of a continuous bit stream of alternating ones and 0s (. . .
10101010 . . .) enabled by setting register FRM_PR20 bit 1 to 1.

■

The quasi-random test signal, enabled by setting register FRM_PR20 bit 3 to 1, which consists of the following:
— A pattern produced by means of a 20-stage shift register with feedback taken from the seventeenth and twen-

tieth stages via an exclusive-OR gate to the first stage. The output is taken from the twentieth stage and is
forced to a 1 state whenever the next 14 stages (19 through 6) are all 0. The pattern length is
1,048,575 or 2

and illustrated in Figure 29.
— Valid framing bits.
— Valid transmit facility data link (TFDL) bit information.
— Valid CRC bits.

20

– 1 bits. This pattern is described in detail in

AT&T Technical Reference 62411 [5] Appendix

A

C

B

XOR

D

#1

D-TYPE FLIP-FLOPS

DD

#2 #17

#6

#19

#20

D

#18

NOR

DD

#19 #20

QUASI-RANDOM TEST OUTPUT

OR

5-3915(F).dr.1

Figure 29. 20-Stage Shift Register Used to Generate the Quasi-Random Signal

■

The pseudorandom test pattern, enabled by setting register FRM_PR20 bit 2 to 1, which consists of:

15

— A 2

– 1 pattern inserted in the entire payload (time slots 1—24 in DS1 and time slots 1—32 in CEPT), as

described by ITU Rec. 0.151 and illustrated in Figure 30.
— Valid framing pattern.
— Valid transmit facility data link (TFDL) bit data.
— Valid CRC bits.

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Alarms and Performance Monitoring

A

C

B

XOR D-TYPE FLIP-FLOPS

D

#1

DD

#2 #3

(continued)

D

#13

DD

#14 #15

PSEUDORANDOM
TEST OUTPUT

5-3915(F).er.1

Figure 30. 15-Stage Shift Register Used to Generate the Pseudorandom Signal

■

The idle code test pattern, enabled by setting register FRM_PR20 bit 6 to 1, which consists of the following:
— The programmable idle code, programmed through register FRM_PR22, in time slots 1—24 in DS1 and 0—31

in CEPT.
— Valid framing pattern.
— Valid transmit facility data link (TFDL) bit data.
— Valid CRC bits.

Transmit Line Test Patterns—Using Register FRM_PR69

Framed or unframed patterns indicated in Table 34 may be generated and sent to the line by register FRM_PR69
and by setting register FRM_PR20 to 00 (hex). Selection of transmission of either a framed or unframed test pat­tern is made through FRM_PR69 bit 3. If one of the test patterns of register FRM_PR69 is enabled, a single bit
error can be inserted into the transmitted test pattern by toggling register FRM_PR69 bit 1 from 0 to 1.

Table 34. Register FRM_PR69 Test Patterns

Pattern Register FRM_PR69

Bit 7 Bit 6 Bit 5 Bit 4

MARK (all ones AIS) 0 0 0 0
QRSS (2

5

2

– 1 0 0 1 0
63 (2
511 (2
511 (2
2047 (2
2047 (2

15

2

20

2

20

2

23

2

20

– 1 with zero suppression) 0 0 0 1

6

– 1) 0 0 1 1

9

– 1) 0 1 0 0

9

– 1) reversed 0 1 0 1

11

– 1) 0 1 1 0

11

– 1) reversed 0 1 1 1
– 1 1 0 0 0
– 1 1 0 0 1
– 1 1 0 1 0
– 1 1 0 1 1

1:1 (alternating) 1 1 0 0

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Alarms and Performance Monitoring

(continued)

Receive Line Pattern Monitor—Using Register FRM_SR7

The receive framer pattern monitor continuously monitors the received line, detects the following fixed framed pat­terns, and indicates detection in register FRM_SR7 bit 6 and bit 7.

■

The pseudorandom test pattern as described by ITU Rec. O.151 and illustrated in Figure 30. Detection of the
pattern is indicated by register FRM_SR7 bit 6 = 1.

■

The quasi-random test pattern described in
ure 29. Detection of the pattern is indicated by register FRM_SR7 bit 7 = 1.

In DS1 mode, the received 193 bit frame must consist of 192 bits of pattern plus 1 bit of framing information. In
CEPT mode, the received 256 bit frame must consist of 248 bits of pattern plus 8 bits (TS0) of framing information.
No signaling, robbed bit in the case of T1 and TS16 signaling in the case of CEPT, may be present for successful
detection of these two test patterns.

To establish lock to the pattern, 256 sequential bits must be received without error. When lock to the pattern is
achieved, the appropriate bit of register FRM_SR7 is set to a 1. Once pattern lock is established, the monitor can
withstand up to 32 single bit errors per frame without a loss of lock. Lock will be lost if more than 32 errors occur
within a single frame. When such a condition occurs, the appropriate bit of register FRM_SR7 is deasserted. The
monitor then resumes scanning for pattern candidates.

Receive Line Pattern Detector—Using Register FRM_PR70

AT&T Technical Reference 62411[5] Appendix

and illustrated in Fig-

Framed or unframed patterns indicated in Table 35 may be detected using register FRM_PR70. Detection of the
selected test pattern is indicated when register FRM_SR7 bit 4 is set to 1. Selection of a framed or unframed test
pattern is made through FRM_PR70 bit 3. Bit errors in the received test pattern are indicated when register
FRM_SR7 bit 5 = 1. The bit errors are counted and reported in registers FRM_SR8 and FRM_SR9, which are nor­mally the BPV counter registers. (In this test mode, the BPV counter registers do not count BPVs but count only bit
errors in the received test pattern.)

Table 35. Register FRM_PR70 Test Patterns

Pattern Register FRM_PR70

Bit 7 Bit 6 Bit 5 Bit 4

MARK (all ones AIS) 0 0 0 0
QRSS (2

5

2
63 (2
511 (2
511 (2
2047 (2
2047 (2

15

2

20

2

20

2

23

2

20

– 1 with zero suppression) 0 0 0 1

– 1 0 0 1 0

6

– 1) 0 0 1 1

9

– 1) 0 1 0 0

9

– 1) reversed 0 1 0 1

11

– 1) 0 1 1 0

11

– 1) reversed 0 1 1 1
– 1 1 0 0 0
– 1 1 0 0 1
– 1 1 0 1 0
– 1 1 0 1 1

1:1 (alternating) 1 1 0 0

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Preliminary Data Sheet
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Alarms and Performance Monitoring

(continued)

The pattern detector continuously monitors the received line for the particular pattern selected in register
FRM_PR70 bit 7—bit 4 (DPTRN). To establish detector lock to the pattern, 256 sequential bits must be detected.
Once the detector has locked onto the selected pattern, it will remain locked to the established alignment and count
all unexpected bits as single bit errors until register FRM_PR70 bit 2 (DBLKSEL) is set to 0.

To select a pattern or change the pattern to be detected, the following programming sequence must be followed:

■

DBLKSEL (register FRM_PR70 bit 2) is set to 0.

■

The new pattern to be detected is selected by setting register FRM_PR70 bit 7—bit 4 to the desired value.

■

DBLKSEL (register FRM_PR70 bit 2) is set to 1.

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Alarms and Performance Monitoring

(continued)

Automatic and On-Demand Commands

Various alarms can be transmitted either automatically as a result of various alarm conditions or on demand. After
reset, all automatic transmissions are disabled. The user can enable the automatic or on-demand actions by set­ting the proper bits in the automatic and on-demand action registers as identified below in Table 36. T able 37 shows
the programmable automatically transmitted signals and the triggering mechanisms for each. Table 37 shows the
on-demand commands.

Table 36. Automatic Enable Commands

Action Trigger Enabling Register Bit

Transmit Remote Frame Alarm
(RFA)

Transmit CEPT E Bit = 0 Detection of CEPT CRC-4 error FRM_PR28 bit 3 = 1

Transmit AIS to System RLFA FRM_PR19 bit 0 = 1

Transmit CEPT Time Slot 16
Remote Multiframe Alarm to
Line

Transmit CEPT AIS in Time Slot
16 to System

Automatic Enabling of DS1 Line
Loopback On/Off

Automatic Enabling of ESF FDL
Line Loopback On/Off

Automatic Enabling of ESF FDL
Payload Loopback On/Off

Loss of frame alignment (RLFA) FRM_PR27 bit 0 = 1
Loss of CEPT time slot 16 multiframe

alignment (RTS16LMFA)
Loss of CEPT time slot 0 multiframe

alignment (RTS0LMFA)
Detection of the timer (100 ms or

400 ms) expiration due to loss of
CEPT multiframe alignment

Detection of the CEPT RSa6 = 8 (hex)
code

Detection of the CEPT RSa6 = C (hex)
code

RTS0LMFA FRM_PR28 bit 4 = 1
Detection of the timer (100 ms or

400 ms) expiration due to loss of
CEPT multiframe alignment

Detection of the timer (100 ms or
400 ms) expiration due to loss of
CEPT multiframe alignment

RTS16LMFA FRM_PR41 bit 4 = 1

RTS16LMFA FRM_PR44 bit 6 = 1

Line loopback on/off code FRM_PR19 bit 4 = 1

ESF line loopback on/off code FRM_PR19 bit 6 = 1

ESF payload loopback on/off code FRM_PR19 bit 7 = 1

FRM_PR27 bit 1 = 1

FRM_PR27 bit 2 = 1

FRM_PR27 bit 3 = 1
FRM_PR9 bit 7—bit 0 = 0xxxx1x1 or
0xxx1xx1

FRM_PR27 bit 4 = 1

FRM_PR27 bit 5 = 1

FRM_PR28 bit 5 = 1
FRM_PR9 bit 7—bit 0 = 0xxxx1x1 or
0xxx1xx1

FRM_PR19 bit 1 = 1
FRM_PR9 bit 7—bit 0 = 0xxxx1x1 or
0xxx1xx1

82 Lucent Technologies Inc.

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Alarms and Performance Monitoring

Table 37. On-Demand Commands

Type Frame Format Action Enabling Register Bit

Transmit Remote Frame Alarm D4 (Japanese) F

D4 (US) Bit 2 of all time slots = 0 FRM_PR27 bit 7 = 1
DDS Bit 6 in time slot 24 = 0
ESF Pattern of 1111111100000000 in

CEPT A bit = 1

Transmit Time Slot 16 Remote
Multiframe Alarm to the Line

Transmit Data Link AIS
(Squelch)

Transmit Line Test Patterns All Transmit test patterns to the line

Transmit System AIS All Transmits AIS to the system FRM_PR19 bit 3 = 1
T r ansmit System Signaling AIS

(Squelch)

Receive Signaling Inhibit All Suspend the updating of the

Receive Framer Reframe All Force the receive framer to reframe FRM_PR26 bit 2 = 1
Transmit Line Time Slot 16 CEPT Transmit AIS in time slot 16 to the

Enable Loopback All Enables system and line loopbacks See Loopback and Trans-

Framer Software Reset All The framer and FDL are placed in

Framer Software Restart All The framer and FDL are placed in

CEPT Time slot 16 remote alarm bit = 1 FRM_PR41 bit 5 = 1

SLC

-96, ESF Transmit data link bit = 1 FRM_PR21 bit 4 = 1

T1 Transmit ABCD = 1111 to the sys-

CEPT Transmit AIS in system time slot 16 FRM_PR44 bit 7 = 1

(continued)

bit in frame 12 = 1 FRM_PR27 bit 6 = 1

S

the FDL F-bit position

See Transmit Line Test

interface

tem

receive signaling registers

line

the reset state for four RCLK clock
cycles. The framer parameter reg­isters are forced to the default
value.

the reset state as long as this bit is
set to 1. The framer parameter reg­isters are not changed from their
programmed values.

Patterns—Using Register
FRM_PR20 section on
page 78 and T r ansmit Line
Test Patterns—Using Reg­ister FRM_PR69 section
on page 79.

FRM_PR44 bit 1 = 1

FRM_PR44 bit 3 = 1

FRM_PR41 bit 6 = 1

mission Modes secti on on
page 75.

FRM_PR26 bit 0 = 1

FRM_PR26 bit 1 = 1

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Facility Data Link

Data may be extracted from and inserted into the facility data link in

SLC

-96, DDS, ESF, and CEPT framing for­mats. In CEPT, any one of the Sa bits can be declared as the facility data link by programming register FRM_PR43
bit 0—bit 2. Access to the FDL is made through:

■

The FDL pins (RFDL, RFDLCK, TFDL, and TFDLCK). Figure 15 shows the timing of these signals.

■

The 64-byte FIFO of the FDL HDLC block. FDL information passing through the FDL HDLC Section may be
framed in HDLC format or passed through transparently.

t8

TFDLCK

TFDL

RFDLCK

t11

t10

t8: TFDLCK CYCLE =

t9

t9

t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns

t10: RFDLCK CYCLE =

t11: RFDLCK TO RFDL DELAY = 40 ns

125 µs (DDS)
250 µs (ALL OTHER
MODES)

125 µs (DDS)
250 µs (ALL OTHER
MODES)

RFDL

5-3910(F).cr.1

Figure 31. TFRA08C13 Facility Data Link Access Timing of the Transmit and Receive Framer Sections

In the ESF frame format, automatic assembly and
transmission of the performance report message
(PRM) as defined in both

cordia Technologies

ANSI

T1.403-1995 and

Tel-

* TR-TSY-000194 Issue 1, 12—87
is managed by the receive framer and transmit FDL
sections. The

ANSI

T1.403-1995 bit-oriented data link
messages (BOM) can be transmitted by the transmit
FDL section and recognized and stored by the receive
FDL section.

Receive Facility Data Link Interface

writing to register FDL_PR0 bit 4— bit 7. When a
valid

ANSI

code is detected, register FDL_SR0 bit 7

(FRANSI) is set.

HDLC operation.

■

This is the default mode of opera­tion when the FDL receiver is enabled (register
FDL_PR1 bit 2 = 1). The HDLC framer detects the
HDLC flags, checks the CRC bytes, and stores the
data in the FDL receiver FIFO (register FDL_SR4)
along with a status of frame (SF) byte.

HDLC operation with performance report mes-

■

sages (PRM).

This mode is enabled by setting regis-

ter FDL_PR1 bit 2 and bit 6 to 1. In this case, the

Summary

receiv e FDL will st ore th e 13 b ytes o f the PRM report
field in the FDL receive FIFO (register FDL_SR4)

A brief summary of the receive facility data link func­tions is given below:

Bit-oriented message (BOM) operation.

■

The

ANSI

T1.403-1995 bit-oriented data link messages are
recognized and stored in register FDL_SR3. The
number of times that an

ANSI

code must be received

for detection can be programmed from 1 to 10 by

84 Lucent Technologies Inc.

along with a status of frame (SF) byte.

Transparent operation.

■

Enabling the FDL and set­ting register FDL_PR9 bit 6 (FTM) to 1 disables the
HDLC processing. Incoming data link bits are stored
in the FDL receive FIFO (register FDL_SR4).

*

Telcordia Technologies

Communications Research, Inc.

is a registered trademark of Bell

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Facility Data Link

Transparent operation with pattern match.

■

(continued)

Enabling the FDL and setting registers FDL_PR9 bit 5 (FMATCH)
and FDL_PR9 bit 6 (FTM) to 1 forces the FDL to start storing data in the FDL receive FIFO (register FDL_SR4)
only after the programmable match character defined in register FDL_PR8 bit 0—bit 7 has been detected. The
match character and all subsequent bytes are placed into the FDL receive FIFO.

The FDL interface to the receive framer is illustrated in Figure 32.

RECEIVE LINE

DATA

LOSS OF FRAME

ALIGNMENT

RECEIVE

FRAMER

RECEIVE FDL

DATA

EXTRACTER

RFDL RFDLCK

RECEIVE

FACILITY DATA

TRANSPARENT

RFDL

RECEIVE F ACILITY

DATA LINK HDLC

RFDLCK

ANSI

T1.403-1995

BIT-ORIENTED DATA

LINK MESSAGES

MONITOR

ONE 8-bit REGISTER

IDENTIFYING THE ESF

BIT-ORIENTED CODE

MICROPROCESSOR INTERFACE

RECEIVE F ACILITY

DATA LINK FIFO

64 8-bit LOCATIONS

5-4560(F).ar.1

Figure 32. Block Diagram for the Receive Facility Data Link Interface

Receive

■

The receive FDL monitor will detect any of the

T1.403 Bit-Oriented Messages (BOM)

ANSI

ANSI

T1.403 ESF bit-oriented messages (BOMs) and generate an
interrupt, enabled by register FDL_PR6 bit 7, upon detection. Register FDL_SR0 bit 7 (FRANSI) is set to 1 upon
detection of a valid BOM and then cleared when read.

■

The received ESF FDL bit-oriented messages are received in the form 111111110X0X1X2X3X4X50 (the left most
bit is received first). The bits designated as X are the defined
ten into the received

■

The minimum number of times a valid code must be received before it is reported can be programmed from 1 to

ANSI

FDL status register FDL_SR3 when the entire code is received.

ANSI

ESF FDL code bits. These code bits are writ-

10 using register FDL_PR0 bit 4—bit 7.

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Preliminary Data Sheet

p

g

g

TFRA08C13 OCTA L T1/E1 Framer October 2000

Facility Data Link

The received

Table 38.

ANSI

Receive

(continued)

FDL status byte, register FDL_SR3, has the following format.

ANSI

Code

B7 B6 B5 B4 B3 B2 B1 B0

00X

ANSI

Receive

As defined in

Performance Report Messages (PRM)

ANSI

T1.403, the performance report messages consist of 15 bytes, starting and ending with an

5

4

X

3

X

2

X

1

X

0

X

HDLC flag. The receive framer status information consists of four pairs of octets, as shown in Table 39. Upon
detection of the PRM message, the receive FDL extracts the 13 bytes of the PRM report field and stores it in the
receive FDL FIFO along with the status of frame byte.

Table 39.

Octet

Performance Re

ort Message Structure

*

PRM B7 PRM B6 PRM B5 PRM B4 PRM B3 PRM B2 PRM B1 PRM B0

Number

1Fla
2SAPIC/REA
3 TEI EA
4Control
5 G3LVG4U1U2G5SLG6
6 FESELBG1 R G2NmNl
7 G3LVG4U1U2G5SLG6
8 FESELBG1 R G2NmNl

9 G3LVG4U1U2G5SLG6
10 FE SE LB G1 R G2 Nm Nl
11 G3 LV G4 U1 U2 G5 SL G6
12 FE SE LB G1 R G2 Nm Nl

13—14 FCS

15 Fla

* The rightmost bit (bit 1) is transmitted first for all fields except for the 2 bytes of the FCS that are transmitted

left most bit (bit 8) first.

The definition of each PRM field is shown in Table 40, and octet content is shown in Table 41.

86 Lucent Technologies Inc.

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Preliminary Data Sheet

p

y

)

)

y

(

)

g

g

g

(T)

)

)

)

g

g

October 2000 TFRA08C13 OCTAL T1/E1 Framer

Facility Data Link

Table 40.

PRM Field Definition

U1, U2 = 0 Reserved

Nm, Nl = 00,

01, 10, 11

Table 41.

FDL Performance Re

G1 = 1 CRC Error Event = 1
G2 = 1 1 < CRC Error Event ≤ 5
G3 = 1 5 < CRC Error Event ≤ 10
G4 = 1 10 < CRC Error Event ≤ 100
G5 = 1 100 < CRC Error Event ≤ 319
G6 = 1 CRC Error Event ≥ 320
SE = 1 Severel

FE =1 Frame Synchronization Bit Error Event ≥ 1 (SE will = 0
LV = 1 Line Code Violation Event ≥ 1
SL = 1 Slip Event ≥ 1
LB = 1 Pa

R = 0 Reserved

Octet Contents and Definition

(continued)

ort Message Field Definition

Errored Framing Event ≥ 1 (FE will = 0

load Loopback Activated

default value = 0

One-Second Report Modulo 4 Counter

Octet

Number

1 01111110 Openin
2 00111000

3 00000001 TEI = 0, EA = 1

4 00000011 Unacknowled
5, 6 Variable Data for Latest Second
7, 8 Variable Data for Previous Second (T – 1

9, 10 Variable Data for Earlier Second (T – 2

11, 12 Variable Data for Earlier Second (T – 3

13, 14 Variable CRC-16 Frame Check Sequence

15 01111110 Closin

Octet

Contents

00111010

Definition

LAPD Fla

From CI: SAPI = 14, C/R = 0, EA = 0

From Carrier: SAPI = 14, C/R = 1, EA = 0

ed Frame

LAPD Fla

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Preliminary Data Sheet

y

TFRA08C13 OCTA L T1/E1 Framer October 2000

Facility Data Link

Receive HDLC Mode

This is the default mode of the FDL. The receive FDL receives serial data from the receive framer, identifies HDLC
frames, reconstructs data bytes, provides bit destuffing as necessary, and loads parallel data in the receive FIFO.
The receive queue manager forms a status of frame (SF) byte for each HDLC frame and stores the SF byte in the
receive FDL FIFO (register FDL_SR4) after the last data byte of the associated frame. HDLC frames consisting of
n bytes will have n + 1 bytes stored in the receive FIFO. The frame check sequence bytes (CRC) of the received
HDLC frame are not stored in the receive FIFO. When receiving
bytes are stored in the receive FIFO.

The SF byte has the following format.

Table 42.

BAD CRC ABORT RFIFO

Bit 7 of the SF status byte is the CRC status bit. A 1 indicates that an incorrect CRC was detected. A 0 indicates
the CRC is correct. Bit 6 of the SF status byte is the abort status. A 1 indicates the frame associated with this status
byte was aborted (i.e., the abort sequence was detected after an opening flag and before a subsequent closing
flag). An abort can also cause bits 7 and/or 4 to be set to 1. An abort is not reported when a flag is followed by
sev en o nes . Bit 5 is the FIF O ov er run bit . A 1 indica tes th at a rece iv e FIF O ov er run occurr ed (t he 64-b yte FIFO s ize
was exceeded). Bit 4 is the FIFO bad byte count that indicates whether or not the bit count received was a multiple
of eight (i.e., an integer number of bytes). A 1 indicates that the bit count received after 0-bit deletion was not a mul­tiple of eight, and a 0 indicates that the bit count was a multiple of eight. When a non-byte-aligned frame is
received, all bits received are present in the receive FIFO. The byte before the SF status byte contains less than
eight valid data bits. The HDLC block provides no indication of how many of the bits in the byte are valid. User
application programming controls processing of non-byte-aligned frames. Bit 3—bit 0 of the SF status byte are not
used and are set to 0. A good frame is implied when the SF status byte is 00 (hex).

Receive Status of Frame B

RSF B7 RSF B6 RSF B5 RSF B4 RSF B3 RSF B2 RSF B1 RSF B0

(continued)

OVERRUN

te

BAD BYTE

COUNT

ANSI

PRM frames, the frame check sequence

0000

Receive FDL FIFO

Whenever an SF byte is present in the receive FIFO, the end of frame registers FDL_SR0 bit 4 (FREOF) and
FDL_SR2 bit 7 (FEOF) bits are set. The receiver queue status (register FDL_SR2 bit 0—bit 6) bits report the num­ber of bytes up to and including the first SF byte. If no SF byte is present in the receive FIFO, the count directly
reflects the number of data bytes available to be read. Depending on the FDL frame size, it is possible for multiple
frames to be present in the receive FIFO. The receive fill level indicator register FDL_PR6 bit 0—bit 5 (FRIL) can be
programmed to tailor the service time interval to the system. The receive FIFO full register FDL_SR0 bit 3 (FRF)
interrupt is set in the interrupt status register when the receive FIFO reaches the preprogrammed full position. An
FREOF interrupt is also issued when the receiver has identified the end of frame and has written the SF byte for
that frame. An FDL overrun interrupt register FDL_SR0 bit 5 (FROVERUN) is generated when the receiver needs
to write either status or data to the receive FIFO while the receive FIFO is full. An overrun condition will cause the
last byte of the receive FIFO to be overwritten with an SF byte indicating the overrun status. A receive idle register
FDL_SR0 bit 6 (FRIDL) interrupt is issued whenever 15 or more continuous ones have been detected.

88 Lucent Technologies Inc.

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Facility Data Link

The receive queue status bits, register FDL_SR2 bit
0—bit 6 (FRQS), are updated as bytes are loaded into
the receive FIFO. The SF status byte is included in the
byte count. When the first SF status byte is placed in
the FIFO, register FDL_SR0 bit 4 (FREOF) is set to 1,
and the status freezes until the FIFO is read. As bytes
are read from the FIFO, the queue status decrements
until it reads 1. The byte read when register FDL_SR2
bit 0—bit 6 = 0000001 and the FREOF bit is 1 is the SF
status byte describing the error status of the frame just
read. Once the first SF status byte is read from the
FIFO, the FIFO status is updated to report the number
of bytes to the next SF status byte, if any, or the number
of additional bytes present. When FREOF is 0, no SF
status byte is currently present in the FIFO, and the
FRQS bits report the number of bytes pr esent. As
bytes are read from the FIFO, the queue status decre­ments with each read until it reads 0 when the FIFO is
totally empty . The FREOF bit is also 0 when the FIFO is
completely empty . Thus, the FRQS and FREOF bit pro­vide a mechanism to recognize the end of 1 frame and
the beginning of another. Reading the FDL receiver
status register does not affect the FIFO buffers. In the
event of a receiver ov errun, an SF status byte is written
to the receive FIFO. Multiple SF status bytes can be
present in the FIFO. The FRQS reports only the num­ber of bytes to the first SF status byte. If FRQS is 0, do
not read the receive FIFO. A read will result in the cor­ruption of receive FIFO.

To allow users to tailor receiver FIFO service intervals
to their systems, the receiver interrupt level bits in reg­ister FDL_PR6 bit 0—bit 5 (FRIL) are provided. These
bits are coded in binary and determine when the
receiver full interrupt, register FDL_SR0 bit 3 (FRF), is
asserted. The interrupt pin transition can be masked by
setting register FDL_PR2 bit 3 (FRFIE) to 0. The value
programmed in the FRIL bits equals the total number of
bytes necessary to be present in the FIFO to trigger an
FRF interrupt. The FRF interrupt alone is not sufficient
to determine the number of bytes to read, since some
of the bytes may be SF status bytes. The FRQS bits

(continued)

and FREOF bit allow the user to determine the number
of bytes to read. The FREOF interrupt can be the only
interrupt for the final frame of a group of frames, since
the number of bytes received to the end of the frame
cannot be sufficient to trigger an FRF interrupt.

Programming Note:

receive FIFO and the host reading from the receive
FIFO are asynchronous events, it is possible for a host
read to put the number of bytes in the receive FIFO just
below the programmed FRIL level and a receiver write
to put it back above the FRIL level. This causes a new
FRF interrupt, and has the potential to cause software
problems. It is recommended that during service of the
FRF interrupt, the FRF interrupt be masked FRFIE = 0,
and the interrupt register be read at the end of the ser­vice routine, discarding any FRF interrupt seen, before
unmasking the FRF interrupt.

Receiver Overrun

A receiver overrun occurs if the 64-byte limit of the
receiver FIFO is exceeded, i.e., data has been received
faster than it has been read out of the receive FIFO.
Upon overrun, an SF status byte with the overrun bit
(bit 5) set to 1 replaces the last byte in the FIFO. The
SF status b y te ca n have o ther err or condi ti ons pres ent .
For ex ample, it is unlike ly the CRC is correct. Thus,
care should be taken to prioritize the possible frame
errors in the software service routine. The last byte in
the FIFO is overwritten with the SF status byte regard­less of the type of byte (data or SF status) being over­written. The overrun condition is reported in register
FDL_SR0 bit 5 and causes the interrupt pin to be
asserted if it is not masked (register FDL_PR2 bit 5
(FROVIE)). Data is ignored until the condition is
cleared and a new frame begins. The overrun condition
is cleared by reading register FDL_SR0 bit 5 and read­ing at least 1 byte from the receive FIFO. Because mul­tiple frames can be present in the FIFO, good frames
as well as the overrun frame can be present. The host
can determine the overrun frame by looking at the SF
status byte.

Since the receiver writing to the

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Facility Data Link

(continued)

Transmit Facility Data Link Interface

The FDL interface of the transmit framer is shown in Figure 33, indicating the priority of the FDL sources.
The remote frame alarm, enabled using register FRM_PR27, is given the highest transmission priority by the trans-

mit framer.
The

ANSI

T1.403-1995 bit-oriented data link message transmission is given priority over performance report mes­sages and the automatic transmission of the performance report messages is given priority over FDL HDLC trans­mission. Idle code is generated by the FDL unit when no other transmission is enabled.

The FDL transmitter is enabled by setting register FDL_PR1 bit 3 to 1.

MICROPROCESSOR INTERFACE

TRANSMIT

FDL FIFO

TRANSPARENT

TRANSMIT FDL

HDLC FRAMER

TFDL

RECEIVE

FRAMER

TRANSMIT

PERFORMANCE

REPORT MESSAGE

ASSEMBLER

TRANSMIT

T1.403 FDL BIT

GENERATOR

ANSI

CODE

FDL

IDLE CODE

GENERATOR

TFDLCK

TRANSMIT FDL

CLOCK GENERATOR

TFDLCK

FDL

YELLOW

ALARM

TRANSMIT

FRAME

ASSEMBLER

Figure 33. Block Diagram for the Transmit Facility Data Link Interface

Transmit

When the
the

ANSI

The transmit ESF FDL bit-oriented messages of the form 111111110X

ANSI

FDL parameter register FDL_PR10 bit 0—bit 5. The ESF FDL bit-oriented messages will be repeated while

T1.403 Bit-Oriented Messages (BOM)

ANSI

ANSI

BOM mode is enabled by setting register FDL_PR10 bit 7 to 1, the transmit FDL can send any of

T1.403 ESF bit-oriented messages automatically through the FDL bit in the frame.

0X1X2X3X4X5

0 are taken from the transmit

register FDL_PR10 bit 7 (FTANSI) is set to 1.

5-4561(F).a

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Facility Data Link

Transmit

When the
transmits the

After assembling the
ters FRM_SR62 and FRM_SR63 and transfers the data to the FDL transmit FIFO. After accumulating three sec­onds (8 bytes) of the message, the FDL transmit block appends the header and the trailer (including the opening
and closing flags) to the PRM messages and transmits it to the framer for transmission to the line.

Table 39—Table 41 show the complete format of the PRM HDLC packet.

Performance Report Messages (PRM)

ANSI

ANSI

PRM mode is enabled by setting register FDL_PR1 bit 7 to 1, the transmit FDL assembles and

ANSI

(continued)

performance report message once every second.

ANSI

PRM message, the receive framer stores the current second of the message in regis-

HDLC Operation

HDLC operation is the default mode of operation. The transmitter accepts parallel data from the transmit FIFO, con­verts it to a serial bit stream, provides bit stuffing as necessary, adds the CRC-16 and the opening and closing
flags, and sends the framed serial bit stream to the transmit framer. HDLC frames on the serial link have the follow­ing format.

Table 43.

Opening Flag User Data Field Frame Check

HDLC Frame Format

Closing Flag

Sequence (CRC)

01111110 ≥8 bits 16 bits 01111110

All bits between the opening flag and the CRC are considered user data bits. User data bits such as the address,
control, and information fields for LAPB or LAPD frames are fetched from the transmit FIFO for transmission. The
16 bits preceding the closing flag are the frame check sequence, cyclic redundancy check (CRC), bits.

Zero-Bit Insertion/Deletion (Bit Stuffing/Destuffing)

The HDLC protocol recognizes three special bit patterns: lags, aborts, and idles. These patterns have the common
characteristic of containing at least six consecutive ones. A user data byte can contain one of these special pat­terns. Transmitter zero-bit stuffing is done on user data and CRC fields of the frame to avoid transmitting one of
these special patterns. Whenever five ones occur between flags, a 0 bit is automatically inserted after the fifth 1,
prior to transmission of the next bit. On the receive side, if five successive ones are detected followed by a 0, the 0
is assumed to have been inserted and is deleted (bit destuffing).

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Preliminary Data Sheet

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Facility Data Link

*

Flags

(continued)

All flags have the bit pattern 01111110 and are used for
frame synchronization. The FDL HDLC block automati­cally sends two flags between frames. If the chip-con­figuration register FDL_PR0 bit 1 (FLAGS) is cleared to
0, the ones idle byte (11111111) is sent between
frames if no data is present in the FIFO. If FLAGS is set
to 1, the FDL HDLC block sends continuous flags when
the transmit FIFO is empty. The FDL HDLC does not
transmit consecutive frames with a shared flag; there­fore, two successive flags will not share the intermedi­ate 0.

An opening flag is generated at the beginning of a
frame (indicated by the presence of data in the transmit
FIFO and the transmitter enable register FDL_PR1 bit
3 = 1). Data is transmitted per the HDLC protocol until
a byte is read from the FIFO while register FDL_PR3
bit 7 (FTFC) set to 1. The FDL HDLC block follows this
last user data byte with the CRC sequence and a clos­ing flag.

The receiver recognizes the 01111110 pattern as a
flag. Two successive flags may or may not share the
intermediate 0 bit and are identified as two flags (i.e.,
both 011111101111110 and 0111111001111110 are
recognized as flags by the FDL HDLC block). When the
second flag is identified, it is treated as the closing flag.
As mentioned above, a flag sequence in the user data
or CRC bits is prevented by zero-bit insertion and dele­tion. The HDLC receiver recognizes a single flag
between frames as both a closing and opening flag.

Aborts

An abort is indicated by the bit pattern of the sequence

01111111. A frame can be aborted by writing a 1 to
register FDL_PR3 bit 6 (FTABT). This causes the last
byte written to the transmit FIFO to be replaced with
the abort sequence upon transmission. Once a byte is
tagged by a write to FTABT, it cannot be cleared by
subsequent writes to register FDL_PR3. FTABT has
higher priority than FDL transmit frame complete
(FTFC), but FT ABT and FTFC should never be set to 1
simultaneously since this causes the transmitter to
enter an invalid state requiring a transmitter reset to
clear. A frame should not be aborted in the very first
byte following the opening flag. An easy way to avoid
this situation is to first write a dummy byte into the
queue and then write the abort command to the queue.

When receiving a frame, the receiver recognizes the
abort sequence whenever it receives a 0 followed by
seven consecutive ones. The receive FDL unit will
abort a frame whenever the receive framer detects a
loss of frame alignment. This results in the abort bit,
and possibly the bad byte count bit and/or bad CRC
bits, being set in the status of frame status byte (see
Table 42) which is appended to the receive data queue.
All subsequent bytes are ignored until a valid opening
flag is received.

Idles

In accordance with the HDLC protocol, the HDLC block
recognizes 15 or more contiguous received ones as
idle. When the HDLC block receives 15 contiguous
ones, the receiver idle bit register FDL_SR0 bit 6
(RIDL) is set.

For transmission, the ones idle byte is defined as the
binary pattern 11111111 (FF (hex)). If the FLAGS con­trol bit in register FDL_PR0 bit 1 is 0, the ones idle byte
is sent as the time-fill byte between frames. A time-fill
byte is sent when the transmit FIFO is empty and the
transmitter has completed transmission of all previous
frames. Frames are sent back-to-back otherwise.

CRC-16

For given user data bits, 16 additional bits that consti­tute an error-detecting code (CRC-16) are added by
the transmitter. As called for in the HDLC protocol, the
frame check sequence bits are transmitted most signifi­cant bit first and are bit stuffed. The cyclic redundancy
check (or frame check sequence) is calculated as a
function of the transmitted bits by using the ITU-T stan­dard polynomial:

16

x

+ x 12 + x 5 + 1

The transmitter can be instructed to transmit a cor­rupted CRC by setting register FDL_PR2 bit 7 (FTB­CRC) to 1. As long as the FTBCRC bit is set, the CRC
is corrupted for each frame transmitted by logically flip­ping the least significant bit of the transmitted CRC.

The receiver performs the same calculation on the
received bits after destuffing and compares the results
to the received CRC-16 bits. An error indication occurs
if, and only if, there is a mismatch.

* Regardless of the time-fill byt e used, there always is an opening

and closing flag with each frame. Back-to-back frames are
separated by two flags.

92 Lucent Technologies Inc.

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Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Facility Data Link

Transmit FDL FIFO

Transmit FDL data is loaded into the 64-byte transmit
FIFO via the transmit FDL data register, FDL_PR4. The
transmit FDL status register indicates how many addi­tional bytes can be added to the transmit FIFO. The
transmit FDL interrupt trigger level register FDL_PR3
bit 0—bit 5 (FTIL) can be programmed to tailor service
time intervals to the system environment. The transmit­ter empty interrupt bit is set in the FDL interrupt status
register FDL_SR0 bit 1 (FTEM) when the transmit
FIFO has sufficient empty space to add the number of
bytes specified in register FDL_PR3 bit 0—bit 5. There
is no interrupt indicated for a transmitter overrun that is
writing more data than empty spaces exist. Overrun­ning the transmitter causes the last valid data byte writ­ten to be repeatedly overwritten, resulting in missing
data in the frame.

Data associated with multiple frames can be written to
the transmit FIFO by the controlling microprocessor.
However, all frames must be explicitly tagged with a
transmit frame complete, register FDL_PR3 bit 7
(FTFC), or a transmit abort, register FDL_PR3 bit 6
(FTABT). The FTFC is tagged onto the last byte of a
frame written into the transmitter FIFO and instructs the
transmitter to end the frame and attach the CRC and
closing flag following the tagged byte. Once written, the
FTFC cannot be changed by another write to register
FDL_PR3. If FTFC is not written before the last data
byte is read out for transmission, an underrun occurs
(FDL_SR0 bit 2). When the transmitter has completed
a frame, with a closing flag or an abort sequence, reg­ister FDL_SR0 bit 0 (FTDONE) is set to 1. An interrupt
is generated if FDL_PR2 bit 0 (FTDIE) is set to 1.

Sending 1-Byte Frames

Sending 1-byte frames with an empty transmit FIFO is
not recommended. If the FIFO is empty, writing two
data bytes to the FIFO before setting FTFC provides a
minimum of eight TFDLCK periods to set FTFC. When
1 byte is written to the FIFO, FTFC must be written
within 1 TFDLCK period to guarantee that it is effective.
Thus, 1-byte frames are subject to underrun aborts.
One-byte frames cannot be aborted with FTABT. Plac­ing the transmitter in ones-idle mode, register
FDL_PR0 bit 1 (FLAGS) = 0, lessens the frequency of
underruns. If the transmit FIFO is not empty, then
1-byte frames present no problems.

(continued)

Transmitter Underrun

After writing a byte to the transmit queue, the user has
eight TFDLCK cycles in which to write the next byte
before a transmitter underrun occurs. An underrun
occurs when the transmitter has finished transmitting
all the bytes in the queue, but the frame has not yet
been closed by setting FTFC. When a transmitter
underrun occurs, the abort sequence is sent at the end
of the last valid byte transmitted. A FTDONE interrupt
is generated, and the transmitter reports an underrun
abort until the interrupt status register is read.

Using the Transmitter Status and Fill Level

The transmitter-interrupt level bits, register FDL_PR3
bit 0—bit 5, allow the user to instruct the FDL HDLC
block to interrupt the host processor whenever the
transmitter has a predetermined number of empty loca­tions. The number of locations selected determines the
time between transmitter empty, register FRM_SR0 bit
1 (FTEM), interrupts. The transmitter status bits, regis­ter FDL_SR1, report the number of empty locations in
the FDL transmitter FIFO. The transmitter empty
dynamic bit, register FDL_SR1 bit 7 (FTED), like the
FTEM interrupt bit, is set to 1 when the number of
empty locations is less than or equal to the pro­grammed empty level. FTED returns to 0 when the
transmitter is filled to above the programmed empty
level. Polled interrupt systems can use FTED to deter­mine when they can write to the FDL transmit FIFO.

Transparent Mode

The FDL HDLC block can be programmed to operate in
the transparent mode by setting register FDL_PR9 bit 6
(FTRANS) to 1. In the transparent mode of operation,
no HDLC processing is performed on user data. The
transparent mode can be exited at any time by setting
FDL_PR9 bit 6 (FTRANS) to 0. It is recommended that
the transmitter be disabled when changing in and out of
transparent mode. The transmitter should be reset by
setting FDL_PR1 bit 5 (FTR) to 1 whenever the mode
is changed.

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Preliminary Data Sheet

p

TFRA08C13 OCTA L T1/E1 Framer October 2000

Facility Data Link

In the transmit direction, the FDL HDLC takes data
from the transmit FIFO and transmits that data exactly
bit-for-bit on the TFDL interface. Transmit data is octet­aligned to the first TFDLCK after the transmitter has
been enabled. The bits are transmitted least significant
bit first. When there is no data in the transmit FIFO, the
FDL HDLC either transmits all ones, or transmits the
programmed HDLC transmitter idle character (register
FDL_PR5) if register FDL_PR9 bit 6 (FMATCH) is set
to 1. To cause the transmit idle character to be sent
first, the character must be programmed before the
transmitter is enabled.

The transmitter empty interrupt, register FDL_SR0 bit 1
(FTEM), acts as in the HDLC mode. The transmitter­done interrupt, register FDL_SR0 bit 0 (FTDONE), is
used to report an empty FDL transmit FIFO. The
FTDONE interrupt thus provides a way to determine
transmission end. Register FDL_SR0 bit 2 (FTUND­ABT) interrupt is not active in the transparent mode.

In the receive direction, the FDL HDLC block loads
received data from the RFDL interface directly into the
receive FIFO bit-for-bit. The data is assumed to be
least significant bit first. If FMATCH register FDL_PR9
bit 6 is 0, the receiver begins loading data into the
receive FIFO beginning with the first RFDLCK detected
after the receiver has been enabled. If the FMATCH bit
is set to 1, the receiver does not begin loading data into
the FIFO until the receiver match character has been
detected. The search for the receiver match character
is in a sliding window fashion if register FDL_PR9 bit 4

(continued)

(FALOCT) bit is 0 (align to octet), or only on octet
boundaries if FALOCT is set to 1. The octet boundary
is aligned relative to the first RFDLCK after the receiver
has been enabled. The matched character and all sub­sequent bytes are placed in the receive FIFO. An FDL
receiver reset, register FDL_PR1 bit 4 (FRR) = 1,
causes the receiver to realign to the match character if
FMATCH is set to 1.

The receiver full (FRF) and receiver overrun
(FROVERUN) interrupts in register FDL_SR0 act as in
the HDLC mode. The received end of frame (FREOF)
and receiver idle (FRIDL) interrupts are not used in the
transparent mode. The match status (FMSTAT) bit is
set to 1 when the receiver match character is first rec­ognized. If the FMATCH bit is 0, the FMSTAT
(FDL_PR9 bit 3) bit is set to 1 automatically when the
first bit is received, and the octet offset status bits
(FDL_PR9 bit 0—bit 2) read 000. If the FMATCH bit is
programmed to 1, the FMSTAT bit is set to 1 upon rec­ognition of the first receiver match character, and the
octet offset status bits indicate the offset relative to the
octet boundary at which the receiver match character
was recognized. The octet offset status bits have no
meaning until the FMSTA T bit is set to 1. An octet offset
of 111 indicates byte alignment.

An interrupt for recognition of the match character can
be generated by setting the FRIL lev el to 1. Since the
matched character is the first byte written to the FIFO,
the FRF interrupt occurs with the writing of the match
character to the receive FIFO.

The operation of the receiver in transparent mode is
summarized in Table 44.

Table 44.

Note: The match bit (FMATCH) affects both the transmitter and the receiver. Care should be taken to correctly program both the transmit idle

9494 Lucent Technologies Inc.

Receiver O

FALOCT FMATCH Receiver Operation

X0

01

11

character and the receive match character before setting FMATCH. If the transmit idle character is programmed to FF (hex), the FMATCH
bit appears to affect only the receiver.

eration in Transparent Mode

Serial-to-parallel conversion begins with first RFDLCK after FRE, register
FDL_PR1 bit 2, is set. Data loaded to receive FIFO immediately.

Match user-defined character using sliding window . Byte aligns once character is
recognized. No data to receive FIFO until match is detected.

Match user-defined character, but only on octet boundary. Boundary based on
first RFDLCK after FRE, register FDL_PR1 bit 2, set. No data to receive FIFO
until match is detected.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Facility Data Link

(continued)

Diagnostic Modes

Loopbacks

The serial link interface can operate in two diagnostic loopback modes: (1) local loopback and (2) remote loopback.
The local loopback mode is selected when register FDL_PR1 bit 1 (FLLB) is set to 1. The remote loopback is
selected when register FDL_PR1 bit 0 (FRLB) is set to 1. For normal traffic, i.e., to operate the transmitter and
receiver independently, the FLLP bit and the FRLB bits should both be cleared to 0. Local and remote loopbacks
cannot be enabled simultaneously.

In the local loopback mode:

■

TFDLCK clocks both the transmitter and the receiver.

■

The transmitter and receiver must both be enabled.

■

The transmitter output is internally connected to the receiver input.

■

The TFDL is active.

■

The RFDL input is ignored.

■

The communication between the transmit and receive FIFO buffers and the microprocessor continues normally.

XMIT HDLC FDL BLOCK

XMIT FIFO

RCVR FIFO

RCVR HDLC FDL BLOCK

XMIT HDLC

RCVR HDLC

FDL XMIT

INTERFACE

FDL RCVR

INTERFACE

TFDL

TFDLCK

RFDLCK

RFDL

5-4562(F)r.2

Figure 34. Local Loopback Mode

In the remote loopback mode:

■

Transmitted data is retimed with a maximum delay of 2 bits.

■

Received data is retransmitted on the TFDL.

The transmitter should be disabled. The receiver can be disabled or, if desired, enabled. Received data is sent as
usual to the receive FIFO if the receiver is enabled

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Facility Data Link

XMIT HDLC FDL BLOCK

XMIT FIFO

RCVR FIFO

RCVR HDLC FDL BLOCK

(continued)

XMIT HDLC

RCVR HDLC

Figure 35. Remote Loopback Mode

FDL XMIT

INTERFACE

FDL RCVR

INTERFACE

TFDL

TFDLCK

RFDLCK

RFDL

5-4563(F)r.1

Phase-Lock Loop Circuit

DIV-CHICK and DIVPLLCK are phase-locked, the
PLLCK-EPLL signal is in a high-impedance state. A

The TFRA08C13 allows for independent transmit path
and receive path clocking. The device provides outputs
to control v ari ab le cl oc k osc ill ato rs on bo th th e tr ans mit
and receive paths. As such, the system may have both
the transmit and receive paths phase-locked to two
autonomous clock sources.

The block diagram of the TFRA08C13 phase detector
circuitry is shown in Figure 36. The TFRA08C13 uses
elastic store buffers (two frames) to accommodate the
transfer of data from the system interface clock rate of

2.048 Mbits/s to the line interface clock rate of either

1.544 Mbits/s or 2.048 Mbits/s. The transmit line side of
the TFRA08C13 does not have any mechanism to
monitor data overruns or underruns (slips) in its elastic
store buffer. This interface relies on the requirement
that the PLLCK clock signal (variable) is phase-locked
to the CHICK clock signal (reference). When this
requirement is not met, uncontrolled slips may occur in
the transmit elastic store buffer that would result in cor­rupting data and no indication will be given. Typically, a
variable clock oscillator (VCXO) is used to drive the
PLLCK signal. The TFRA08C13 provides a phase error
signal (PLLCK-EPLL) that can be used to control the
VCXO PLLCK. The PLLCK-EPLL signal is generated
by monitoring the divided-down PLLCK (DIV-PLLCK)
and CHICK (DIV-CHICK) signals. The DIV-CHICK sig­nal is used as the reference to determine the phase dif­ference between DIV-CHICK and DIV-PLLCK. While
96 Lucent Technologies Inc.

phase difference between DIV-CHICK and DIV-PLLCK
drives PLLCK-EPLL to either 3.3 V or 0 V. An appropri­ate loop filter, for example, an RC circuit with R = 1 kΩ
and C = 0.1 µF, is used to filter these PLLCK-EPLL
pulses to control the VCXO.

The system can force CHICK to be phase-locked to
RLCK by using RLCK as a reference signal to control a
VCXO that is sourcing the CHICK signal. The
TFRA08C13 uses the receive line signal (RLCK) as the
reference and the CHICK signal as the variable signal.
The TFRA08C13 provides a phase error signal
(CHICK-EPLL) that can be used to control the VCXO
generating CHICK. The CHICK-EPLL signal is gener­ated by monitoring the divided-down CHICK signal
(DIV-CHICK) and RLCK (DIV-RLCK) signals. The DIV­RLCK signal is used as the reference to determine the
phase difference between DIV-CHICK and DIV-RLCK.
While DIV-RLCK and DIV -CHICK are phase-locked, the
CHICK-EPLL signal is in a high-impedance state. A
phase difference between DIV-RLCK and DIV-CHICK
drives CHICK-EPLL to either 3.3 V or 0 V. An appropri­ate loop filter, for example, an RC circuit with R = 1 kΩ
and C = 0.1 µF, is used to filter these CHICK-EPLL
pulses to control the VCXO. In this mode, the
TFRA08C13 can be programmed to act as a master
timing source and is capable of generating the system
frame synchronization signal through the CHIFS pin
and setting FRM_PR45 bit 4 to 1.

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000 TFRA08C13 OCTAL T1/E1 Framer

Phase-Lock Loop Circuit

VOLTAGE-

CONTROLLED

CRYSTAL

OSCILLATOR

(VCXO)

PLLCK DIV-PLLCK

INTERNAL_XLCK

TLCK

TRANSMIT

FRAMER

TPD, TND

(continued)

PLLCK
DIVIDER
CIRCUIT

READ ADDRESS

FACILITY DATA

EXTERNAL CIRCUIT

DETECTOR

TRANSMIT

2-FRAME

ELASTIC STORE

BUFFER

PLLCK-EPLL DIV-CHICK

DIGITAL

PHASE

WRITE ADDRESS

SYSTEM DATA

CONCENTRATION

CHICK
DIVIDER
CIRCUIT

INTERNAL_CHICK

RECEIVE

HIGHWAY

INTERFACE

CHICK

CHIFS

RCHIDATA

RPD, RND

RLCK

RECEIVE

FRAMER

INTERNAL_RLCK

BUFFER OVERRUN

BUFFER UNDERRUN

WRITE ADDRESS

FACILITY DATA

RLCK
DIVIDER
CIRCUIT

DIV-RLCK

SLIP

MONITOR

RECEIVE
2-FRAME

ELASTIC STORE

BUFFER

DIGITAL

PHASE

DETECTOR

EXTERNAL CIRCUIT

READ ADDRESS

SYSTEM DATA

CHICK_EPLL

TRANSMIT

CONCENTRATION

HIGHWAY

INTERFACE

INTERNAL_CHICK

CHICK

DIVIDER
CIRCUIT

DIV-CHICK

VOLTAGE-

CONTROLLED

CRYSTAL

OSCILLATOR

(VCXO)

TCHIDATA

CHIFS

CHICK

5-5268(F).a

Figure 36. TFRA08C13 Phase Detector Circuitry

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Framer-System Interface

DS1 Modes

The DS1 framing formats require rate adaptation from
the 1.544 Mbits/s line interface bit stream to the system
interface which functions at multiples of a 2.048 Mbits/s
bit stream. The rate adaptation results in the need for
eight stuffed time slots on the system interface since
there are only 24 DS1 (1.544 Mbits/s) payload time
slots while there are 32 system (2.048 Mbits/s) time
slots. Placement of the stuffed time slots is defined by
register FRM_PR43 bit 0—bit 2.

CEPT Modes

The framer maps the line time slots into the corre­sponding system time slot one-to-one. Framing time
slot 0, the FAS and NFAS bytes, are placed in system
time slot 0.

Receive Elastic Store

The receive interface between the framer and the sys­tem CHI includes a 2-frame elastic store buffer to
enable rate adaptation. The receive line elastic store
buffer contains circuitry that monitors the read and
write pointers for potential data overrun and underrun
(slips) conditions. Whenever this slip circuitry deter­mines that a slip may occur in the receive elastic store
buffer, it will adjust the read pointer such that a con­trolled slip is performed. The controlled slip is imple­mented by dropping or repeating a complete frame at
the frame boundaries. The occurrence of controlled
slips in the receive elastic store are indicated in the sta­tus register FRM_SR3 bit 6 and bit 7.

Transmit Elastic Store

The transmit interface between the framer and the sys­tem CHI includes a 2-frame elastic store buffer to
enable rate adaptation. The line transmit clock applied
to PLLCK[1—8] must be phase-locked to CHICK. No
indication of a slip in the transmit elastic store is given.

Concentration Highway Interface

Each framer has a dual, high-speed, serial interface to
the system known as the CHI. This flexible bus archi­tecture allows the user to directly interface to other
Lucent components which use this interface, as well as
to

Mitel*

and
glue logic. Configured via the highway control registers
FRM_PR45 through FRM_PR66, this interface can be
set up in a number of different configurations.

The following is a list of the CHI features:

■

Lucent Technologies standard interface for communi­cation devices.

■

Two pairs of transmit and receive paths to carry data
in 8-bit time slots.

■

Programmable definition of highways through offset
and clock-edge options which are independent for
transmit and receive directions.

■

Programmable idle code substitution of received time
slots.

■

Programmable 3-state control of each transmit time
slot.

■

Independent transmit and receive framing signals to
synchronize each direction of data flow.

■

An 8 kHz frame synchronization signal internally
generated from the received line clock.

■

Compatible with

Supported is the optional configuration of the CHI
which presents the signaling information along with the
data in any framing modes when the device is pro­grammed for the associated signaling mode (ASM).
This mode is discussed in the signaling section.

Data can be transmitted or received on either one of
two interface ports, called CHIDATA and CHIDATAB.
The user-supplied clock (CHICLK ) co ntrol s the timi ng
on the transmit or receive paths. Individual time slots
are referenced to the frame synchronization (CHIFS)
pulse. Each frame consists of 32 time slots at a pro­grammable data rate of 2.048 Mbits/s, 4.096 Mbits/s, or

8.192 Mbits/s requiring a clock (CHICK) of the same
rate. The clock and data rates of the transmit and
receive highways are programmed independently.

†

AMD

TDM highway interfaces, with no

Mitel

and

AMD

PCM highways.

*

Mitel

is a registered trademark of Mitel Corporation.

†

AMD

is a registered trademark of Advanced Micro Devices, Inc.

98 Lucent Technologies Inc.

Lucent Technologies Inc.

Preliminary Data Sheet

ge (

)

g (

y

)

g

g

ge (

)

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(

)

(00)

October 2000 TFRA08C13 OCTAL T1/E1 Framer

Concentration Highway Interface

(continued)

Rate adaptation is required for all DS1 formats between
the 1.544 Mbits/s line rate and 2.048 Mbits/s,

4.966 Mbits/s, or 8.182 Mbits/s CHI rate. This is
achieved by means of stuffing eight idle time slots into
the existing twenty-four time slots of the T1 frame. Idle
time slots can occur every fourth time slot (starting in

the first, second, third, or fourth time slot) or be
grouped together at the end of the CHI frame as
described in register FRM_PR43 bit 0—bit 2. The posi­tioning of the idle time slots is the same for transmit
and receive directions. Idle time slots contain the pro­grammable code of register FRM_PR23. Unused time
slots can be disabled by forcing the TCHIDATA inter­face to a high-impedance state for the interval of the
disabled time slots.

CHI Parameters

The CHI parameters that define the receive and transmit paths are given in Table 45.

Table 45. Summary of the TFRA08C13’s Concentration Highway Interface Parameters

Name Description

HWYEN

CHIMM

CHIDTS

TFE

RFE

CDRS0—CDRS1

Highway Enable (FRM_PR45 bit 7).

concentration highway interfaces. This allows the framer to be fully configured before
transmission to the highway. A 0 forces the idle code as defined in register
FRM_PR22, to be transmitted to the line in all payload time slots while TCHIDATA is
forced to a high-impedance state for all CHI transmitted time slots.

Concentration Highway Master Mode (PRM_PR45 bit 4).

CHIMM = 0 enables an external system frame synchronization signal (CHIFS) to
drive the transmit CHI. A 1 enables the transmit CHI to generate a system frame syn­chronization signal from the receive line clock. The transmit CHI system frame syn­chronization signal is generated on the CHIFS output pin. Applications using the
receive line clock as the reference clock signal of the system are recommended to
enable this mode and use the CHIFS signal generated by the framer. The receive CHI
path is

CHI Double Time-Slot Mode (FRM_PR65 bit 1 and FRM_PR66 bit 1).

defines the 4.096 Mbits/s and 8.192 Mbits/s CHI modes. CHIDTS = 0 enables the 32
contiguous time-slot mode. This is the default mode. CHIDTS = 1 enables the double
time-slot mode in which the transmit CHI drives TCHIDATA for one time slot and then
3-states for the subsequent time slot, and the receive CHI latches data from RCHI­DATA for one time slot and then ignores the following time slot and so on. CHIDTS = 1
allows two CHIs to interleave frames on a common bus.

Transmit Frame Ed

fallin
a transmit frame strobe to provide s
0
can be used for receive data on RCHIDATA. The timin
is identical to the timin

Receive Frame Ed

fallin

CHI Data Rate

rate. The default state

not

affected by this mode.

FRM_PR46 bit 3

or rising) edge of CHICK. In CHIMM (CHI master mode), the CHIFS pin outputs

, CHIFS is centered around rising (or falling) edge of CHICK. In this mode, CHIFS

for CHIFS in CHIMM = 0 mode.

FRM_PR46 bit 7

or rising) edge of CHICK.

FRM_PR45 bit 2 and bit 3

enables the 2.048 Mbits/s.

CDRS Bit: 2 3 CHI Data Rate

0 0 2.048 Mbits/s
0 1 4.096 Mbits/s
1 0 8.192 Mbits/s
1 1 Reserved

A 1 in this bit enables the transmit and receive

The default mode

. TFE = 0 (or 1), CHIFS is sampled on the

nchronization for TCHIDATA. When TFE = 1 (or

for CHIFS in CHIMM = 1 mode

. RFE = 0 (or 1), CHIFS is sampled on the

. Two-bit control for selecting the CHI data

CHIDTS

Lucent Technologies Inc. 99

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Preliminary Data Sheet

TFRA08C13 OCTA L T1/E1 Framer October 2000

Concentration Highway Interface

Table 45. Summary of the TFRA08C13’s Concentration Highway Interface Parameters

Name Description

TCE

RCE

TTSE31—TTSE0

RTSE31—RTSE0

THS31—THS0

RHS31—RHS0

TOFF2—TOFF0

ROFF2—ROFF0

TBYOFF6—TBYOFF0

RBYOFF6—RBYOFF0

ASM

STS0—STS2 Stuffed Time Slots (FRM_PR43 bit 0—bit 2). Valid only in T1 framing formats, these 3

T ransmitter Clock Edge (FRM_PR47 bit 6)

the falling (or rising) edge of CHICK.

Receiver Clock Edge (FRM_PR48 bit 6)

the falling (or rising) edge of CHICK.

Transmit Time-Slot Enable 31—0 (FRM_ PR 4 9—F R M _P R52 ) .

which transmit CHI time slots are enabled. A 1 enables the TCHIDATA or TCHIDATAB
time slot. A 0 forces the CHI transmit highway time slot to be 3-stated.

Receive Time-Slot Enable 31—0 (FRM_PR53—FRM_PR56).

which receive CHI time slots are enabled. A 1 enables the RCHIDATA or RCHDATAB
time slots. A 0 disables the time slot and transmits the programmable idle code of reg­ister FRM_PR22 to the line interface.

Transmit Highway Select 31—0 (FRM_PR57—FRM_PR60).

which transmit CHI highway, TCHIDATA or TCHIDATAB, contains valid data for the
active time slot. A 0 enables TCHIDATA; a 1 enables the TCHIDATAB.

Receive Highway Select 31—0 (FRM_PR61—FRM_PR64).

receive CHI highway, RCHIDATA or RCHIDATAB, contains valid data for the active
time slot. A 0 enables RCHIDATA; a 1 enables the RCHIDATAB.

Transmitter Bit Offset (FRM_PR46 bit 0— bit 2)

with the transmitter byte offset to define the beginning of the transmit frame. They
determine the offset relative to TCHIFS, for the first bit of transmit time slot 0. The off­set is the number of CHICK cycles by which the first bit is delayed.

Receiver Bit Offset (FRM_PR46 bit 4—bit 6)

with the receiver byte offset to define the beginning of the receiver frame. They deter­mine the offset relative to the RCHIFS, for the first bit of receiv e time slot 0. The offset
is the number of CHICK cycles by which the first bit is delayed.

Transmitter Byte Offset (FRM_PR47 bit 0—bit 5 and FRM_PR65 bit 0)

determine the offset from the CHIFS to the beginning of the next frame on the trans­mit highway. Note that in the ASM mode, a frame consists of 64 contiguous bytes;
whereas in other modes, a frame contains 32 contiguous bytes. Allowable offsets:

2.048 Mbits/s 0—31 bytes.

4.096 Mbits/s 0—63 bytes.

8.192 Mbits/s 0—127 bytes.

Receiver Byte Offset (FRM_PR48 bit 0—bit 5 and FRM_PR66 bit 0)

determine the offset from CHIFS to the beginning of the receive CHI frame. Note that
in the ASM mode, a frame consists of 64 contiguous bytes; whereas in other modes,
a frame contains 32 contiguous bytes. Allowable offsets:

2.048 Mbits/s 0—31 bytes.

4.096 Mbits/s 0—63 bytes.

8.192 Mbits/s 0—127 bytes.

Associated Signaling Mode (FRM_PR44 bit 2)

naling mode configures the CHI to carry both payload data and its associated signal­ing information. Enabling this mode must be in conjunction with the programming of
the CHI data rate to either 4.048 Mbits/s or 8.096 Mbits/s. Each time slot consists of
16 bits where 8 bits are data and the remaining 8 bits are signaling information.

bits define the location of the eight stuffed CHI (unused) time slots.

(continued)

(continued)

. TCE = 0 (or 1), TCHIDAT A is clocked on

. RCE = 0 (or 1), RCHIDATA is latched on

These bits define

These bits define

These bits define

These bits define which

. These bits are used in conjunction

. These bits are used in conjunction

. When enabled, the associate sig-

. These bits

. These bits

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