Lucent Technologies Inc TDAT042G51A-3BLL1 Datasheet

Data Addendum

May 2001

TDAT SONET/SDH
155/622/2488 Mbits/s Data Interfaces

Introduction

The TDAT data interface is available in three different configurations as summarized in Table 1.

TDAT04622

The TDAT04622 device contains a subset of the TDAT042G5 device. The TDAT04622 device functions as
described in the TDAT042G5 SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet
(DS98-193SONT-4) with the following limitations:

■

Quad OC-3 operation only or single OC-12 operation only.

■

Single UTOPIA port.

TDAT021G2

The TDAT021G2 device contains a subset of the TDAT042G5 device. The TDAT021G2 device functions as
described in the TDAT042G5 SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet
(DS98-193SONT-4) with the following limitations:

■

Quad OC-3 operation only or dual OC-12 operation only.

■

Two UTOPIA ports.

TDAT042G5

The TDAT042G5 device contains all functionality as described in the TDAT042G5 SONET/SDH 155/622/2488
Mbits/s Data Interface Data Sheet (DS98-193SONT-4).

Table 1. TDAT Device Product Line

Device Line Ports UTOPIA Ports

OC-3 OC-12 OC-48 Ports Present Modes

TDAT04622 4

(A, B, C, D)

TDAT021G2 4

(A, B, C, D)

TDAT042G5 4

(A, B, C, D)4(A, B, C, D)

1

(A)

2

(A, B)

NA 1

NA 2

1

(16-bit parallel

multiplexed/

demultiplexed)

(A)

(A, B)

4

(A, B, C, D)

U2, U2+, U3, U3+

■

8-bit

■

16-bit

U2, U2+, U3, U3+

■

8-bit

■

16-bit

■

32-bit

U2, U2+, U3, U3+

■

8-bit

■

16-bit

■

32-bit

TDAT SONET/SDH
155/622/2488 Mbits/s Data Interfaces

Data Addendum

May 2001

For additional information, contact your Agere Systems Account Manager or the following:
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EUROPE: Data Requests: DATALINE: Te l. (44) 7000 582 368, FAX [phone]

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

Copyright © 2001 Agere Systems Inc.
All Rights Reserved
Printed in U.S.A.

1-800-372-2447, FAX [phone] (In CANADA: 1-800-553-2448, FAX [phone])
Tel. [phone], FAX [phone]
Tel. [phone], FAX [phone]
Tel. [phone], FAX [phone]

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May 2001
DA01-010SONT (Replaces DA00-001SONT and must accompany DS98-193SONT-4)

Advisory

May 2001

TDAT042G5 Device Advisory
for Version 1 and 1A of the Device

System Programming (SP)

SP1. Required Provisioning Sequen ce and Clo cks

The core registers must be written prior to provisioning any other registers (1) to establish the internal clock
rates for the device, and (2) because writing to certain core registers resets the remainder of the device. Cer­tain clocks must be present to read/write registers prior to provi sioning the device.

One of the following clocks must be present prior to provisioning to enable register access:

■

TxCKP and TxCKN

■

MPU clock (microprocessor interface sy nchronous mode only)

Provisioning must be implemented in the following sequence:

■

Core register 0x0010 (mode) must be provisioned first

■

Core register 0x0011 (channel [A—D] control) second

■

Remainder of the core registers must then be provisioned (order does not matter)

It is recommended, but not required, that the remainder of the device be provisioned in the following order:

■

OHP, PT, and DE blocks (order does not matter)

■

UT block to turn on the data source to the master and slave

Workaround

Provisioning must be implemented in the following sequence:

■

Apply either TxCKP and TxCKN or MPU clock.

■

Provision core:
— Mode, register 0x0010
— Channel [A—D] control, register 0x0011
— Remainder of the core

Corrective Action

Not applicable. Use above procedure in provisioning the device.

TDAT042G5 Device Advisory
for Version 1 and 1A of the Device

Advisory

May 2001

System Programming (SP)

(continued)

SP2. Behavior During Loss of Receive Line Clock

All state and counter values will be held at their current values when Rx line clock has been lost. The device will not
automatically multiplex in the Tx line clock when the Rx line clock is lost.

Workaround

System software should monitor loss of line clock bits in the receive/transmit state register (addresses 0x040A—
0x040D) and ignore all other alarms. This condition must be serviced as a major failure event.

Corrective Action

This is informational only. No corrective action is required for this condition.

SP3. PT Register Addressing

Addresses for the PT error counter registers are as follows:

■

Channel A: 0x09B3 to 0x09E3

■

Channel B: 0x09EF to 0x0A20

■

Channel C: 0x0A2C to 0x0A5C

■

Channel D: 0x0A68 to 0x0A98

The reserved address space between the error counter registers is not symmetric. (The reserved space

Note:

between channels B and C is 0x003D, and the reserved space between channels A and B and channels
C and D is 0x003C.)

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

No corrective action is required for this condition.

2 Agere Systems Inc.

Advisory
May 2001

Microprocessor Interface (MPU)

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

MPU1. In te rf a ce to

The interface between the
the following incompatibilities in the specifications of these two devices. For a 33 MHz microprocessor clock rate,

Motorola

the
without DT
applied to TDAT042G5 must be held low until the address changes. Details are given below.

Chip Select Timing

The TDAT042G5 CS

x output signals. TDAT042G5 timing does not allow simultaneous deassertion of CS and ADS signals. Chip

CS
select applied to TDAT042G5 must be held low for at least 5 ns after the MC68360 deasserts ADS

Workaround:

signals meeting the requirements of TDAT042G5.

DT

Timing

Motorola

If the
does not satisfy the MC68360 processor DSACK
high-impedance state. This causes the next MPU cycle to be terminated early.

Workaround:

MC68360 series processors can be interfaced to TDAT042G5 without intervening glue logic, if used

and if programmed for six wait-states. If a user wishes not to use the wait-states, then the chip select

Use external glue logic to decode the address to generate CS

MC68360 processor CS

Place a 1 kΩ resistor from DT

Motorola

Motoro la

input signal requirements are not compatible with the

*

MC68360 Processor Is Not Gl ueless

MC68360 processor and TDAT042G5 requires interven ing logic because of

Motorola

, or provide microprocessor interface

x signal is used to drive the TDAT042G5 CS, then TDAT042G5 DT output

timing requirement. DT is not pulled to 1 before it is placed in a

DDD

to V

.

MC68360 series processor

.

Corrective Action

Corrective action for MPU1 has not been determined.

MPU2. Synchronous Microprocessor Interface Mode Is Nonfunctional

The synchronous microprocessor interface mode, MPMODE = 1 (pin D8), functions as described in the advance
data sheet, but causes data errors. Placing TDAT042G5 in the synchronous mode and placing a clock on MPCLK
(pin C8) will cause the data passing through the device to be corrupted. Data errors are generated at a rate of 1%
or less of corrupted packets.

Workaround

Use the TDAT 042G5 in the asynchronous microprocessor mode, MPMODE = 0, with no clock applied to MPCLK.

Corrective Action

This condition will be resolved in version 1A of the device.

Motorola

*

is a registered trademark of Motorola, Inc.

Agere Systems Inc. 3

TDAT042G5 Device Advisory
for Version 1 and 1A of the Device

Core Registers (CR)

CR1. Clear on Read/Clear on Write Behavior

Bit 6 of line provisioning register 0x0010 sets the functionality of the COR/W registers.

Table 1. COR/W Settings of Register 0x0010, Bit 6

Bit 6 Mode Bit Clear Behavior of Accessed Registers

1 COR After COR has been set (address 0x0010, bit 6 = 1), all registers that are accessed

are cleared when read.

0 COW After COW has been set (address 0x0010, bit 6 = 0), a 1 must be written to a given bit

in a given register to clear that bit. Writing a 0 to a bit in a given register does not clear
that bit.

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

Advisory

May 2001

This condition will be described in revision 4 of the advance data sheet.

Line Interface (LI)

LI1. STS-48/STM-16 Mode Lacks Facility Loopback

There is no facility loopback function (line input to line output) available in STS-48/STM-16 mode. Facility loopback
is available only in STS-12/STM-4 and STS-3/STM-1 mo des as described in the advance data sheet.

Workaround

This function is not a feature of TDAT0 42G5.

Corrective Action

No corrective action is required for this condition.

4 Agere Systems Inc.

Advisory
May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

Path Terminator (PT)

PT1. Signal Degrade (SD) and Signal Fail (SF) Bit Behavior

Receive signal degrade and receive signal fail bits in the PT state registers (addresses 0x0838, 0x088A, 0x08DC,
and 0x092E, bits [1:0]) do not function as described. Until the signal degrade (SD) and signal fail (SF) thresholds
are programmed, the SD and SF bits will toggle on a frame-by-frame basis.

Workaround

Program thresholds during system software initializati on.

Corrective Action

This functionality will be retained in its current state in future versions of the device. The advance data sheet will be
corrected to reflect the actual function of the registers.

PT2. Clear-After-Write Behavior of Signal Degrade Clear Bits

Signal degrade clear (bits 15—12) of the PT one-shot control parameters register (address 0x0AA4) are described
as one-shot, clear-after-write bits. Writing these bits should automatically set and then clear the bits. This one-shot
behavior is not observed.

Workaround

The bits must be set to 1 and then explicitly set to 0 to clear these signal degrade bits.

Corrective Action

This functionality will be retained in its current state in future versions of the device. The advance data sheet will be
corrected to reflect the actual function of the registers.

Agere Systems Inc. 5

TDAT042G5 Device Advisory
for Version 1 and 1A of the Device

Advisory

May 2001

Path Terminator (PT)

(continued)

PT3. Remote Defect Indicator (RDI) Behavior

The SONET standards require that when an RDI changes value, it should hold the value for a minimum of
20 frames. This applies to a

no error

However, it is also intended by the SONET standard that the occurrence of an
immediately.

TDAT042G5 responds to error conditions within 100 ms (
erated or removed within 100 ms of detecting or terminating an incoming defect), in which case the two require­ments become functionally the same.

Single-bit and enhanced RDI behave differently under the following conditions:

■

Transition from

■

While in th e

error

state to

error

state, a subsequent error occurs.

The single-bit error RDI does not hold the no error st ate for 20 frames. Howev er, the enhan ced RDI does hold the
no error state for 20 consecutive frames.

Workaround

No workaround is available for this condition.

Corrective Action

state, which should be maintained for at least 20 consecutive frames.

state should be reported

error

*

ANSI

T1.105 which states only that RDI-L must be gen-

no error

state.

The enhanced RDI indicator in future versions of the device will behave the same as the single-bit error i ndicator.

PT4. SS Pointer Interpretation Algorithm

The SDH standards do not require that the SS bits are set to binary 10 for SDH equipment. The SS bit values are
not used in determining a valid pointer value. Because of this, the SS pointer interpretation algorithm is not imple­mented in the device. Bit 5 (RSSPTRNORM[A—D]) of PT control registers 0x0AA6, 0xAAE, 0x0AB6, and 0x0ABE
is not used. Bi ts 1 and 0 (RSSEXP[1:0]) of PT provisioning register 0x0AC7 are not used.

Workaround

No workaround is available for this condition.

Corrective Action

These bits w ill be r emoved from the PT registers in future re v is ion s of the advanc e da ta sheet.

ANSI

*

is a registered trademark of American National Standards Institute, Inc.

6 Agere Systems Inc.

Advisory
May 2001

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Path Terminator (PT)

(continued)

PT5. Delta/Event Registers in COR Mode

Because there is a one-cycle delay before the PT delta event registers (0x802, 0x080F, 0x081C, 0x0829) are
cleared after being read in COR mode, new interrupts may be lost.

Workaround

No workaround is available for this condition.

Corrective Action

This condition will be addressed in future versions of the device.

Data Engine (DE)

DE1. SDL Mode—Header Error Correction in LSB

In SDL mode, the header error correction process is susceptible to single-bit errors in the least significant bit (LSB)
of the special payload.

Workaround

No workaround is available for this condition.

Corrective Action

This condition will be addressed in future versions of the device.

DE2. Incorrect ATM Loss of Cell Delineation (LCD) Implementation

Currently, the LCD is implemented in the same way that out of cell delineation (OCD) is implemented. This is not in
accordance with the ITU-TI.432-2 February 1999 standard.

Workaround

No workaround is available for this condition.

Corrective Action

A software workaround will be available with version 1A of the device.

Agere Systems Inc. 7

TDAT042G5 Device Advisory
for Version 1 and 1A of the Device

Advisory

May 2001

Data Engine (DE)

(continued)

DE3. ATM Transmit Count of Idle Cells

For ATM mode in the transmit direction, all cells are currently counted, including the idle cells. Only the cells con­taining data should be counted.

Workaround

No workaround is available for this condition.

Corrective Action

This condition will be addressed in version 1A of the device.

DE4. Channel Provisioning

When using the device in STS-3/STM-1 and STS-12/STM-4 modes with either PPP, CRC, or HDLC, egress config­uration registers 0x1016, 0x1017, 0x1018, and sequencer cell state register 0x1036 of all four channels must be
provisioned, even if a channel is not being used.

Workaround

Provision all four transmit DE channels. Set DE egress configuration registers and the sequencer cell state register
as shown in Table 2.

Table 2. Tr ansmi t DE Egres s and Sequ enc er C ell State Registers

Address Value

STS-3/STM-1 STS-12/STM-4

0x1016 0x4567 0x4567
0x1017 0x4567 0x4567
0x1018 0x4567 0x4567

0x1019—0x1021 — 0x4567

0x1036 0x0000 0x0000

Corrective Action

This condition will be addressed in future versions of the device.

8 Agere Systems Inc.

Advisory
May 2001

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Data Engine (DE)

(continued)

DE5. Packet Be havi o r in P OS /S D L Mo d e—Dry Mode

When the device is configured in POS mode with dry mode enabled, the following conditions may persist:

■

PPP mode; STS-48/STS-12/STS-3.
When running in PPP mode, the PPP header—0x FF03 0x 0021 (provisionable)—may be incorrectly inserted at
any point in a packet within the outgoing data stream when the FIFO runs dry, thereby corrupting the packet.
Packet s being sent are corrupted if the FIFO r uns dry.

■

PPP and CRC modes; STS-48/STS-12/STS-3.
CRC, PPP, and HDLC modes; STS-48/STS-12/STS-3.
In PPP, CRC, and HDLC dry modes, some of the packet data may be corrupted when the packet length is above
a certain size where size is dependent upon UT clock rate and low watermark setting. Either sections of the
packet may be lost or additional packets may be inserted.

Workaround

Several workarounds are possible:

■

Do not provision dry mode for this devic e.

■

If dry mode is provisioned:
— Do not allow the FIFO to be emptied.
— Run the UTOPIA clock fast enough, as shown in Table 3, so that the FIFO is never empty.
— Use a larger external FIFO to buffer the data.
— Do not allow the packet size to exceed the low watermark.

Table 3. Required UTOPIA Clock (TxCLK) Rates

Mode TxCLK and Rate

STS-48/STM-16 TxCLK > 77 MHz (U3+, 32-bit mode)

STS-12/STM-4 TxCLK > 40 MHz

STS-3/STM-1 TxCLK > 10 MHz

Corrective Action

This condition will be corrected in version 1A of the device.

Agere Systems Inc. 9

TDAT042G5 Device Advisory
for Version 1 and 1A of the Device

Advisory

May 2001

Data Engine (DE)

(continued)

DE6. Incorrect ATM Out of Cell Delineation (OCD) Implementation

In ATM mode, the OCD reporting for channels B, C, and D is incorrect. The OCD state of channel A is reported for
channels B, C, and D. The OCD reporting is correct for channel A.

Workaround

No workaround is available for this condition.

Corrective Action

This condition will be corrected in version 1A of the device.

DE7. Incorrect Frame State of ATM Data Streams

When sending a single ATM data stream to channel A, the frame states of channels B, C, and D are incorrectly set
to sync mode. This prevents LCD errors from being reported on channel A as well. In addition, when sending a sin­gle ATM data stream to channels B, C, or D, the frame states always remain in hunt mode. This results in LCD
errors on those channels.

Workaround

No workaround is available for this condition.

Corrective Action

A software workaround will be available with version 1A of the device.

10 Agere Systems Inc.

Advisory
May 2001

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Data Engine (DE)

(continued)

DE8. Clearing DE Interrupt Register (0x1002)

DE interrupt register 0x1002 is incorrectly defined in the revision 3 of the data sheet as RO. DE interrupt register
0x1002 is correctly defined as a COR/W register. However, register 0x1002 must be used in the COR mode (regis­ter 0x0010 bit 6 set to 1). The bits of register 0x1002 are explained in detail in Table 4.

Table 4. Register 0x1002: DE Interrupt (COR/W)

Bits Mode Clear Behavior of Register 0x1002

15—12 RO To clear these SDL Rx frame state interrupt bits, read and

clear their associated interrupt source registers
(addresses 0x14E0—0x 14E3).

11—0COR or COW

(address 0x0010, bit 6)

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

This behavior will be desc ribed in fu ture rev isions of the adv ance data sheet.

To properly clear these bits, device must be in COR m ode
(address 0x0010, bit 6 = 1).

DE9. Single Packet Transmission in HDLC-CRC, SDL-CRC, and PPP Modes

When receiving in either PPP or CRC mode, a single packet may not pass through the device. This occurs when
the end of packet (which contains the CRC) never reaches the UT FIFO. The ingress channel suspends transfer to
the UT when there is no end of packet in the FIFO. These bytes are transferred to the UT when the next packet is
received. This proble m will aff ect HDLC-CRC, SDL-CRC, and PPP modes.

Workaround

There are two possible workarounds:

■

Set ingress payload type and mode control registers (0x1040—0x1043) to CRC strip mode. However, i n CRC-16

mode, single packets may still get stuck if CRC ends on bytes A or B.

■

Send a minimum 4-byte dummy packet after each packet.

Corrective Action

This condition will be addressed in future versions of the device.

Agere Systems Inc. 11

TDAT042G5 Device Advisory
for Version 1 and 1A of the Device

Advisory

May 2001

Data Engine (DE)

(continued)

DE10. Excessive HDLC Flag Characters

The following three issues refer to HDLC flag character (0x7E) problems in the data engine:

■

An excessive number of HDLC fl ag characters (0x7Es) may be inserted between packets on the transmit side if
the UTOPIA low watermark value is set above 2. This will have the effect of reducing the bandwidth of the device.

■

The data engine operates on 32-bit boundaries. Egress packets that are not multiples of four will be fil led with
0x7Es.

■

Egress packets consisting of all 0x7Es as data will be c orru pte d.

Workaround

Set the UTOPIA egress low watermark value in the UTOPIA egress provisioning registers (0x0212, 0x0216,
0x021A, 0x021E) to either 1 or 2 to prevent excessive 0x7Es from being inserted between packets.

Corrective Action

This condition will be addressed in future versions of the device.

UTOPIA (UT)

UT1. Polling in Multidevice MPHY Mode

When the TDAT042G5 is polled and respon ds, the data bus become s enabled. In a multidevice MPHY configura­tion, if the data bus is active from a different PHY device, response to a poll from the device will corrupt a data
transfer already in progress. TDAT042G5 MPHY always functions without data corruption in a single-device
(slave), multiple-channel configuration (point-to-point).

Workaround

No workaround is available for this condition.

Corrective Action

This condition will be addressed in future versions of the device.

12 Agere Systems Inc.

Advisory
May 2001

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

UTOPIA (UT)

(continued)

UT2. UTOPIA Clock Limitations

The maximum spee d of the UTOPIA interface is 104 MHz. When operating at clock speeds greate r than 52 MHz,
RxCLK[D:A] must be placed in source mode and will use the same external clock as the corresponding
TxCLK[D:A] clock. RxCLK[D:A] source mode is set by provisioning bit 6 (CLOCK_MODE_Rx) for channel A of the
UTOPIA receive provisioning registers (address 0x020F).

When operating at speeds less than 52 MHz, separate external clocks for RxCLK[D:A] and TxCLK[D:A] may be
used.

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

This condition will be addressed in future versions of the device. Design modifications will be directed towards
allowing a maximum interface speed of 104 MHz in all cases. Note that UTOPIA Level 3 clock architecture has
changed in the A TM Forum’s UTOPIA Level 3 specification as of the July 1998 version.

UT3. PMRST Register Value Invalid After Reset

The value in PMRST_PECTx[A—D] (addresses 0x020B through 0x 020E) is invalid after reset until the second
PMRST clock period is completed. After the second PMRST, the register value is valid.

Workaround

Always have the system software execute a read of PMRST_PECTx as part of the system initialization following a
reset.

Corrective Action

This condition will be addressed in future versions of the device.

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TDAT042G5 Device Advisory
for Version 1 and 1A of the Device

Advisory

May 2001

UTOPIA (UT)

(continued)

UT4. FIFO Overflow and Error Reporting

If the RxFIFO overflows, RxEOP is not asserted as expected. Therefore, when errors occur, two packets will be
corrupted instead of one because two start of packets (SOPs) occurred without an end of packet (EOP). RxERR is
not asserted when the above overflow condition occurs. No effect is noticeable in the ATM mode. Channel A works
as expected; this problem occurs in channels B, C, and D.

Workaround

This error is detectable in the status registers. No workaround is available for this c ondition .

Corrective Action

This condition will be addressed in future versions of the device.

UT5. Timing Difference Between Direct and Polled Status Modes

In the receive direction of the MPHY mode, RxPA[A] shows the polled packet (or ATM) available status for a ll four
slices, while the RxPA[B], RxPA[C], and RxPA[D] show the direct status states of their respective FIFOs. In some
cases, the status of RxPA[A] does not agree with the status of RxPA[D:B]. The direct status indication has one
additional cycle of pipeline delay from that of the polled status.

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

No corrective action is required for this condition.

UT6. UTOPIA Interface D Nonfunctional in Some Mixed MPHY and Point-to-Point

Configurations

When TDAT042G5 is configured with slice D in a point-to-point mode, slice D is nonfunctional in one special case.
If UTOPIA interfaces A and B are configured for 32-bit MPHY operation with slice C as part of the polled channels,
interface D will be nonfunctional and cannot be independently configured in a UTOPIA Level 2 point-to-point mode.
This condition does not occur in 16-bit MPHY operation.

Workaround

For mixed MPHY and point-to-point configuration, use UTOPIA slice D for MPHY mode instead of slice C.
UTOPIA slice C will then be available for normal point-to point mode.

Corrective Action

This condition will be addressed in future versions of the device.

14 Agere Systems Inc.

Advisory
May 2001

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

UTOPIA (UT)

(continued)

UT7. Response to 0x1F MPHY Address

TDAT042G5 MPHY currently generates a polled status response to the address 0x1F (the null address), which is
not compliant with the UTOPIA Level 2 standard. The address 0x1F is valid for UTOPIA Level 3 operation.

Workaround

No workaround is available for this condition.

Corrective Action

This condition will be addressed in future versions of the device.

UT8. Far-End Loopback Bandwidth Limitations

In the STS-48/STM-16 mode (U3, U3+), looping back data at the far end (UTOPIA interface) can only be accom­plished without cell/packet corruption at rates below the following, as shown in Table 5.

Table 5. Cell/Packet Corruption Rates

Mode ATM Packet

STS-48/STM-16 300 Mbits/s Rate not ye t determined

STS-12/STM-4 70 Mbits/s Rate not yet determined

STS-3/STM-1 30 Mbits/s Rate not yet determined

When cell/packet corruption occurs, the device reports transmit FIFO underflow.

Workaround

No workaround is available for this condition.

Corrective Action

This condition will be addressed in future versions of the device.

Agere Systems Inc. 15

TDAT042G5 Device Advisory
for Version 1 and 1A of the Device

Advisory

May 2001

UTOPIA (UT)

(continued)

UT9. Clock Requirements for MPHY Modes

When using the TDAT042G5 in MPHY mode, receive and transmit clocks m ust be provided for all channels (A, B,
C, and D). Also, the packet available (PA) signal for each channel must be provided on each channel’s associated
PA pin.

Workaround

It is possible to place RxCLK[D:A] into source mode by provisioning bit 6 (CLOCK_MODE_Rx) of the UTOPIA
receive provisioning registers (addresses 0x020F, 0x0213, 0x0217, 0x021B). This will eliminate the need to supply
separate receive and transmit clocks.

Corrective Action

This is informational only. No corrective action is required for this condition.

UT10. Egress Packet Mode Overflows

In the UTOPIA modes listed below, the device will report transmit packet overflow errors when no overflows have
occurred. This occurs when the egress high watermark is set for the UTOPIA modes as shown in Table 6.

Table 6. Settings at Which Overflows Reported in Error

UTOPIA Modes Egress High Watermark Thresholds

8-bit, U3+
16-bit, U2+
32-bit, U3+

Workaround

Set the egress high watermark threshold as shown in Table 7. If there is a delay bet ween TxPA dea ssertion and
TxENB deassert ion, the additional cycl es should also be accounted for when setting the threshold.

Table 7. Settings to Prevent Overflows Reported in Error

UTOPIA Modes Egress High Watermark Thresholds

8-bit, U3+
16-bit, U2+
32-bit, U3+

Corrective Action

This condition will be addressed in future versions of the device.

≥

0x3D

≥

0x3B

≥

0x37

<

0x3D

<

0x3B

<

0x37

16 Agere Systems Inc.

Advisory
May 2001

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

UTOPIA (UT)

(continued)

UT11. Clearing UT Interrupt Re gis ter

When a UT interrupt event occurs and COW mode is enabled, writing to UT interrupt register 0x0201 does not
clear the register (this register is read-only). The interrupt is cleared by writing to the UT delta and event registers
(addresses 0x0202—0x0205).

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

No corrective action is required for this condition.

UT12. Incorrect Implementation of POS Multi-PHY Mode

Because the TDAT042G5 lacks a selected PA signal (SPA), the status of a channel that is transmitting data in POS
MPHY mode is not known during polling. Therefore, the PA signal cannot be used as a data valid signal. If the
channel transmitting data runs dry, the master side may receive invalid data.

Workaround

Use direct status polling mode only and ensure that the address of channel A is applied to the address bus at all
times, except during the clock cycle when another channel is being selected.

Corrective Action

No corrective action is required for this condition.

UT13. Invalid Extra Cycle Between EOP and SOP in CRC-16/32 Mode

When using the device in CRC-16 or CRC-32 mode, there is always an extra cycle between the end of packet
(EOP) of the previous packet and the start of packet (SOP) of the following packet.

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

This is condition will be addressed in the future version of the device.

Agere Systems Inc. 17

TDAT042G5 Device Advisory
for Version 1 and 1A of the Device

Advisory

May 2001

UTOPIA (UT)

(continued)

UT14. Nonfunctional RxPA Signal for Channels B and D in Packet Direct Status MPHY Mode

When using MPHY direct status for all operational modes (8-bit, 16-bit, and 32-bit), the RxPA signal for channels B
and D is not functional. The RxPA signal is functional only for channels A and C.

Workaround

The TDAT UTOPIA interface currently has nonfunctioning RxP A B and RxPAD output signals when used in four­channel Multi-PHY mode as shown in Figure 1. The result of this problem is the unavailability of direct status polling
on the receive-side UTOPIA interface. To work around this problem, the following analysis is done to aid the user i n
doing a round-robin data extraction procedure.

R

PAA

INGRESS CHANNEL A FIFO

256 byt es DEEP

INGRESS CHANNEL B FIFO

256 byt es DEEP

A

32-bit INTERFACE (A AND B)

B

X

X

RXPAB

INGRESS CHANNEL C FIFO

256 byt es DEEP

INGRESS CHANNEL D FIFO

256 byt es DEEP

C

D

X

RXPAC

RXPAD

Figure 1. Receive-Side UTOPIA Interface and Channel FIFOs

The rate at which data fills and drains the receive-side UTOPIA FIFOs is calculated as follows:

■

The data enters each UTOPIA FIFO from the data engin e bytewise running on a 77.76 MHz system clock.

■

If we assume each channel (worst case) is filled with an STS-12c rate signal, then the amount of data (excluding
SONET overhead, both section/line, path, and three stuff columns) per second is
(87 x12 x 9 x 8000) – (4 x 9 x 8000) = 74.88 Mbytes/STS-12c/s or 599.040 Mbits/STS-12c/s.

■

Since each FIFO contains a maximum of 256 bytes/FIFO, it takes on average
(256/74,880,000) = 3.4188µs to fill a FIFO, and with a clock cycle of 77.76 MH z, it requires as a worst case,

3.2922 µs to fi ll th e FIFO.

■

Since there are four FIFOs all receiving data at 74.88 Mbytes/s, then the total bandwidth requirements of all four
channels combined is (4 x 74,880,000) = 299.52 Mbytes/s.

1664 (F)

■

The servicing rate on each FIFO is based on the UTOPIA interface width and frequency. If we assume a
32-bit A/B UTOPIA interface operating at 100 MHz, then the service rate is 400 Mbytes/s to service all the
channels.

18 Agere Systems Inc.

Advisory
May 2001

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

UTOPIA (UT)

■

The interface can drain an entire FIFO at a rate of 400 Mbytes/s. To drain 256 bytes, it requires a maximum of
(2 56 / 400,000,000) = 0.64µs to drain a FIFO that is completely full. To drain all four FIFOs, it requires
(0.64 x 4) = 2.56 µs total

For data to be efficiently removed from each of the Rx FIFOs, a round-robin extraction method must be employed
since the RxPAB and RxP AD signals are not avai lable f or direct status polling. Since it requires a worst case total of

3.2922µs to fill a FIFO, the master must serv ice all FIFOs in a manner such that it does not allow any particular
FIFO to fill and hence overflow. Assuming equal servicing of each FIFO, the master must therefore not service any
particular FIFO for longer than (3.2922 / 4) = 0.8231µs. This also must account for any dead cycles in a cycling
between channels and any dead cycles on a particular channel (single dead cycle between EOP and SOP).

When servicing four FIFOs, there is a maximum clock cycle penalty for switching between channels. For two-cycle
mode, this penalty is a maximum of four UTOPIA master clock cycles; so to switch between all four channels, a
total of up to sixteen master clock cycles may be required to perform all the switching. The value of fou r is worst
case, and in some cases this can be as low as one cycle. The value of four results from the case where the FIFO
drains while servicing that channel, which will be common when draining at the 100 MHz frequency. In that case,
the master must first see that the FIFO has drained by observing that RxPAA is invalid on the last cycle while drain­ing the FIFO (best case is one cycle lost). It must then deactivate RxENB and place a new channel address on the
address bus on the following cycle (best case is one cycle lost). It must then activate RxEN B for the new channel
on the following cycle and have TDAT sample RxENB low (best case is one cycle lost). The TDAT will then output
data two cycles later when using a PA response mode of two cycles (o ne cycle lost with data output on second
cycle). Any additional delays by the master must be added to these to calculate a worst-case condition. The best­case condition occurs when the master stops the data flow when there are still more than two data items contained
within the FIFO. In th is case, the master deactivates RxENB at some predetermined max imum 32-bit word drain
value, where the PA response on the cycle prior to deactivation had valid data. For two-cycle mode, two additional
data items will be output from the FIFO for that particular channel, if available. The master deactivates RxENB,
places the new channel address on the FIFO, and activates RxENB. On the cycle where RxENB is activated, the
last valid data item from the previous channel may be output (best case), and one dead cycle will follow this before
data for the following selected channel is output.

(continued)

.

Given the information above, as sume the worst case of four cycles between channel switching. Also assume the
FIFOs are f illing at a worst-c as e rate, 3 .2922µs/FIFO. Assume the master is draining each FIFO using the 32-bit,
100 MHz, A/B, UTOPIA interface. Assume the master extracts a maximum of thirty 32-bit words (120 bytes) from
each FIFO before switching to an alt ernate channel. This requires (30 x 10) = 300 ns/FIFO, and assume that it
takes the worst-case four clock cycles to switch to alternate channels. Therefore, the total servicing time per FIFO
is (300 + 4 x 10) = 340 ns/channel, and the total servicing time per four channels is (4 x 340) = 1.36 µs per round
robin servicing of all four channels. At this round-robin rate, a maximum of 120 bytes are serviced per channel per

1.360µs interval; so to service the total bytes per channel (74.88 Mbytes/s), it requires a total of 0.849 seconds,
which is sufficient bandwidth to service all channels.

Since the FIFOs fill at the maximum rate of 1 byte/13.355 ns, each FIFO w ill fill to a depth of 102 bytes in the

1.360µs interval between channel servicing. This is well below the overflow threshold, which is set by the user to a
value near the top of the FIFO (high watermar k, 0x36 (216 bytes) default) and is below the number of byt es ser­viced by the master per channel per round-robin servicing (120 bytes). Each customer’s servicing characte r istics
will depend on the master’s behavior and how fast it performs the channel switching. If it cannot switch in the worst­case, fo ur-cycle manner described above, performance will degrade.

One item not accounted for in the above analysis is the fact that TDAT may place a dead cycle between packets (in
CRC and PPP modes, not in HDLC mode). In this case, there can be a maximum of three dead cycles per FIFO
(assuming 40-byte packets worst c ase and 102 bytes in FIFO between round-robin cycle). This will be tak en up by
the slack provided above , where (102 bytes + 4 bytes/dead cycle x 3 dead cycles) = 114 bytes, which still falls
below the servicing rate of 120 bytes per round-robin servicing.

Agere Systems Inc. 19

TDAT042G5 Device Advisory
for Version 1 and 1A of the Device

Advisory

May 2001

UTOPIA (UT)

(continued)

The logical flow of the above proce dure is shown in Figure 2 below:

SELECT NEXT

CHANNEL

HOLD ADDRESS OF SELECTED
CHANNEL ON ADDRESS BUS

PA = 1

YES

YES

<

COUNT

NO

DEACTIVATE

RXENB

30

NO

1665 (F)

Figure 2. Master Control Flow Chart

Select channel

If PA = 1 continue

If count = 30 words, then deactivat e RxENB and switch to new channel
Else continue with current channel

Else deactivate RxENB and switch to next channel

Return to selection of new channel

Corrective Action

This is condition will be addressed in the future version of the device.

20 Agere Systems Inc.

Advisory
May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

Overhead Processor (OHP)

OHP1. Maximum BER Count

The maximum number of errors the device can report is limited to 5.00E-04 in STS-12/STM-4 mode and 1.00E-04
in STS-48/STM-16 mode. This applies to the SDLSET, SDLCLEAR, SFLSE T, and SFLCLEA R bits of the signal
degrade and signal fail BER algorithm OHP registers. These bits are shown in Table 8.

Table 8. Signal Degrade and Signal Fail Algorithm OHP Registers [6:3]

OHP Bits

OHP_SDLSET[A—D][3:0] 0x043B, 0x043D, 0x043F, 0x0441

OHP_SDLCLEAR[A—D][3:0] 0x0447, 0x0449, 0x044B, 0x044D

OHP_SFLSET[A—D][3:0] 0x0453, 0x0455, 0x0457, 0x0459

OHP_SFLCLEAR[A—D][3:0] 0x045F, 0x0461, 0x0463, 0x0465

* The OHP prefix shown here will be added to the current bit names in revision 4 of the advance data

sheet.

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

No corrective action is required for this condition.

*

Addresses

OHP2. RDI-L Reporting

When the device is initially powered up, it defaults to STS-48/STM-16 mode. This locks a counter value into trans­mit control registers for channels B, C, and D. When the device is configured for STS-3/STM-1 mode, the counter
does not automatically clear.

Workaround

During STS-3/STM-1 OHP configuration in the system code, manually clear transmit control registers 0x0431,
0x0433, and 0x0435 for channels B, C, and D. In order to clear these transmit control registers, the bits must be
toggled. The following pseudocode shows how to clear the bits on channels B, C, and D:

Set address 0x0431 to 0x007F # set bits on channel B
Set address 0x0431 to 0x0000 # clear bits on channel B
Set address 0x0433 to 0x007F # set bits on channel C
Set address 0x0433 to 0x0000 # clear bits on channel C
Set address 0x0435 to 0x007F # set bits on channel D
Set address 0x0435 to 0x0000 # clear bits on channel D

Corrective Action

This is informational only. No corrective action is required for this condition.

Agere Systems Inc. 21

TDAT042G5 Device Advisory
for Version 1 and 1A of the Device

Advisory

May 2001

Overhead Processor (OHP)

(continued)

OHP3. M1 Error Counter in STS-48/STM-16 Mode

When the device receives REI-L errors in the STS-48/STM-16 mode, no M1 errors are reported.

Workaround

There are several workarounds for this problem:

■

Pass the B2 error count value to the far end through system sof tware.

■

Process the M1 byte from the receive TOAC with an external FPGA.

■

Pass the B2 error count from the receive to the transmit direction using transmit TOAC capability. The error count
must be inserted into the eleventh Z2 byte in an STS-48/STM-16 transmit signal. The transmit TOAC signal is
driven by an exter nal device with s o ftwar e in s ert capability.

■

Pass the B2 error count from the receive to the transmit direction in the section overhead byte. The device has F1
and S1 monitor capab ility ; the pro tocol for sending the error mess age to the far end with F1 or S1 bytes is user­defined.

Corrective Action

This condition will be addressed in future versions of the device.

Packaging and Pinouts (P)

P1. Pin F5 (Previously JTEST) Is No Connect (NC)

Item deleted. Corrected in the advance data sheet.

P2. Modified Pinout and Power Supply Configuration—F utur e Versions

Item deleted. No modifications to the power supply configuration will be made.

P3. Change to TDAT042G5 Version 1 Pinout

Item deleted. All devices conform to power pin assignments as listed in the advance data sheet.

22 Agere Systems Inc.

Advisory
May 2001

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Packaging and Pinouts (P)

(continued)

P4. Power Dissipation

The worst-case power dissipation of TDAT042G5 is currently estimated to be 7.5 W. The minimum and maximum
power dissipation is listed in Table 9, as well as the relative package thermal characteristics.

Table 9. Power Dissipation and Relative Package Thermal Characteristics

Parameter Symbol Test Conditions Min Typ Ma x Unit

Power Dissipation:

Minimum
Maximum

Thermal Performance

(JEDEC standard
conditions)*

Correlation Factor

Between Die and Case
Temperatures

*

= (TJ – TA)/PD: TJ = ju nction temperature, TA = ambien t tem pe ra tur e o f medi um sur rou nd in g t he pac k age, PD = electr ic al po wer dissi pa t ed

θ

JA

by the device.

†

= (TJ – TC)/PD: TJ = junction temperature, TC = package temperature (top, dead-center), PD = electrical power diss ipated by the device.

ψ

JC

†

D

P

STS-3/STM-1 line ra te
STS-12/STM-4 and STS-48/

—
—

3
6

—
—

W
W

STM-16 line rates

JA

θ

JC

ψ

Standard JEDEC 4-layer PWB:

■

Standard natural convection

■

200 LFPM airflow

■

800 LFPM airflow

Standard JEDEC 4-layer PWB:

■

Standard natural convection

■

200 LFPM airflow

■

800 LFPM airflow

—
—
—

—
—
—

9

6.5
5

0.3

0.4

0.5

—
—
—

—
—
—

°C/W
°C/W
°C/W

°C/W
°C/W
°C/W

Maximum junction temperature of TDAT042 G5 is 125 °C. Therefore, maximum cas e temperature under nat ural
convection conditions must be less than approximately 50 °C, and in this case, an external heat sink is required.

References

Jeff Weiss,

HL250C 3.3 Volt 0.25

600 LBGA Thermal Test Report

m CMOS Standard-Cell Library

µ

, February 25, 1999.

(MN98-060ASIC-02), pages 2-2 and 2-3.

Workaround

An external heat sink is required.

Corrective Action

Power consumption will be addressed in future versions of the device.

Agere Systems Inc. 23

TDAT042G5 Device Advisory
for Version 1 and 1A of the Device

Data Addenda

DA1. Incorrect PT Control Register Mapping

Advisory

May 2001

TDAT042G5 SONET/SDH 155/622/2488 Mbits/s Data Interface

mapping for PT control registers 0x0AAA, 0x0AB2, 0x0ABA, and 0x0AC2:
bit #9 TRDIP_PLMPINH[A—D]

bit #8 TRDIP_UNEQUIPINH[A—D]
bit #7 TRDIP_LCDINH[A—D]

The correct bit mapping is the following:
bit #9 TRDIP_LCDINH[A—D]

bit #8 TRDIP_PLMPINH[A—D]
bit #7 TRDIP_UNEQUIPINH[A—D]

Workaround

No workaround is available for this condition.

Corrective Action

This correct bit mapping will be included in July 2000 of the advance data sheet.

Advance Data Sheet, Rev. 3 lists the following bit

D A2. Variable Change

TDAT042G5 SONET/SDH 155/622/2488 M bits/s Data Interface

TRD_LCDINH[A—D], which has been changed to TRD_LCD[A—D] in the January 2001 revision.

Advance Data Sheet, Rev. 3 lists the variable

Workaround

No workaround is available for this condition.

Corrective Action

This correction will be included in Janu ary 2001 of the advance data sh eet.

24 Agere Systems Inc.

Advisory
May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

AY99-013SONT-2 Replaces AY99-013SONT to Incorporate the Following Updates

1. Pag e 1, SP1. Required Provisioning Sequenc e and Clocks, added new issue.

2. Pag e 8, DE4. Channe l Provisioning, added new issue.

3. Pag e 9, DE5. Packet Behavior in P OS/SDL M ode—Dry Mode, added new issue.

4. Page 15, UT8. Far-End Loopback Bandwidth Limitations, added new issue.

5. Page 16, advance data sheet document number corrected.

AY99-013SONT-3 Replaces AY99-013SONT-2 to Incorporate the Following Updates

1. Page 1, notice that the advisory issues still apply to the advance data sheet which has just been updated.

AY99-013SONT-4 Replaces AY99-013SONT-3 to Incorporate the Following Updates

1. Replaced OC- designation with STS- and STM- throughout advisory.

2. Page 2, SP2. Behavior During Loss of Receive Line Clock, added new issue.

3. Page 2, SP3. PT Register Addressing, added new issue.

4. Pag e 4, CR1. Clear on Read/Clear on Write Behavior, added new issue.

5. Pag e 5, PT2. Clear-After-Write B ehavior of Signal Degrade Clear Bits, corrected description.

6. Page 6, PT4. SS Pointer Interpretation Algorithm, added new issue.

7. Page 7, PT5. Delta/Event Registers in COR Mode, added new issue.

8. Page 7, DE2. Incorrect ATM Loss of Cell Delineation (LCD) Implementation, identified the specific ITU stan­dard with which the LCD implementation does not comply.

9. Page 8, DE4. Channel Provisioning, Table Transmit DE Egress and Sequencer Cell State Registers, corrected
register 0x102D to 0x1021.

10. Page 9, DE5. Packet Behavior in POS/SDL Mode—Dry Mode , identified dry m ode issues.

11. Page 10, DE6. Incorrect ATM Out of Cell Delineation (OCD) Implementation, added new issue.

12. Page 10, DE7. Incorrect Frame State of ATM Data Streams, added new issue.

13. Page 11, DE8. Clearing DE Interrupt Register (0x1002), added new issue.

14. Page 11, DE9. Single Packet Transmission in HDLC-CRC, SDL-CRC, and PPP Modes, added new issue.

15. Page 12, DE10. Excessive HDLC Flag Characters, added new issue.

16. Page 13, UT2. UTOPIA Clock Limitations, clarified wording.

17. Page 14, UT4. FIFO Overf low and Error Reporting , clar ified wording.

18. Page 16, UT9. Clock Requirements for MPHY Modes, added new issue.

19. Page 16, UT10. Egress Packet Mode Overflows, added new issue.

20. Page 17, UT11. Clearing UT Interrupt Register, added new issue.

21. Page 17, UT12. Incorrect Implementation of POS Multi-PHY Mode, added new issue.

22. Page 21, OHP1. Maximum BER Count, added new issue. In addition, differentiated OHP bits from PT bits with

the same name; the names will be corrected in revision 4 of the advance data sheet.

Agere Systems Inc. 25

TDAT042G5 Device Advisory
for Version 1 and 1A of the Device

Advisory

May 2001

AY99-013SONT-4 Replaces AY99-013SONT-3 to Incorporate the Following Updates

(continued)

23. Page 21, OHP2. RDI-L Reporting, added new issue.

24. Page 22, OHP3. M1 Error Counter in STS-48/STM-16 Mode, added new issue.

25. Page 22, remove d issue P1. Pin 5 (Previously JTEST
accompanying advance data sheet, DS98-193SONT-3.

26. Page 22, remov ed issue P2. Modified Pinout and Power Supply Configuration—Future Vers ions. Plans for 2.5 V
power ring implementation considered, but no schedule ava ilable at this time.

27. Page 22, removed issue P3. Change to TDAT042G5 Version 1 Pinout. Listed pins have been corrected to NC in
the accompanying advance data sheet, DS98-193SONT-3.

28. Page 24, DA1. Incorrect PT Control Register Mapping, added new issue.

) Is No Co nnect (NC ) . Pin F5 wa s cor rected to NC in the

AY01-015SONT (Replaces AY99-013SONT-4 and Must Accompany
DS98-193SONT-4) Replaces AY99-013SONT-4 to Incorporate the Following
Updates

Change List

This change list summarizes changes across the various versions of thi s document starting with the version dated
1/25/01.

1/25/01

1. Page 6, PT3. Remote Defect Indicator (RDI) Behavior, clarified wording.

2. Page 12, DE 11. ATM Header Error Correction (HEC) Behavior, added entire section to document.

1/29/01

1. Page 24, DA1. Incorrect PT Control Register Mapping, changed corrective action description to include the July

2000 date.

2. Page 24, DA2. Variable Change, added entire section to document.

2/13/01

1. Page 12, updated issue on DE 11. ATM Header Error Correction (HEC) Behavior, to i nc lude more information.

2. Page 17, added issue UT13. Invalid Extra Cycle Between EOP and SOP in CRC-16/32 Mode.

3. Page 18, added issue UT14 . Nonfunctional RxPA Signal for Channels B and D in Packet Direct Status MPHY
Mode.

3/1/01

1. Page 12, removed DE 11 from document.

2. Page 18, UT14. Nonfunctional RxPA Signal for Channels B and D in Packe t Direct Status MPHY Mode, added

workaround to document.

26 Agere Systems Inc.

Advisory
May 2001

Notes

TDAT042G5 Device Advisory

for Version 1 and 1A of the Device

Agere Systems Inc. 27

TDAT042G5 D evi ce Advisory
for Version 1 and 1A of the Device

Advisory

May 2001

For additional information, contact your Agere Sys tems A ccount Manager or the following:
INTERNET:
E-MAIL:
N. AMERICA: Agere Systems Inc ., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286

ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
CHINA: Agere System s (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC
JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japa n
EUROPE: Data Request s: DATALINE:

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

Copyright © 2001 Agere Systems Inc.
All Right s Reserv e d
Printed in U.S.A.

http://www.agere.com
[e-mail]

1-800-372-2447
Tel. [phone]
Tel. [phone]
Tel. [phone]

Technical Inquiries:GERM A NY:

, FAX [phone] (In CANADA :

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Tel. [phone]

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(Helsinki),

May 2001
AY01-015S O NT (Replaces AY99-013SONT-4 and Must Accompany DS98-193SONT-4)

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Features

Point-to-point path termination device for interface

■

termination.
Versatile IC supports 155/622/2488 Mbits/s

■

SONET/SDH interface solutions for packet over
SONET (POS), asynchronous transfer mode
(ATM), or simplified data link (SDL) for data over
fiber applicatio ns.

Suppor ts point-to-point and multi-P H Y UTOPIA.

■

Low-power 3.3 V operation, CMOS technology.

■

High-speed I/O is LVPE CL. Al l other logi c has 5 V

■

tolerant TTL-level inputs.
–40 °C to +85 °C temperature range.

■

600 LBGA package.

■

SONET/SDH Interface

Termination of quad STS-3/STM-1, quad STS-12/

■

STM-4, or single STS-48/STM-16.
Suppor ts overhead processing for transport and

■

path overhead bytes.
Optional insertion and extraction of overhead bytes

■

via serial overhead interface.
Full path termi nat ion and SPE extraction/insertion.

■

SONET/SDH compliant condition and alarm

■

reporting.
Handles all concatenation levels of STS-3c

■

through STS-48c (in multiples of 3; i.e., 3c, 6c, 9c,
etc.), STM-1 through STM-16.

Built-in diagnostic loopback modes.

■

— ITU-T G.707: Network Node Interface for the

Synchronous Digital Hier ar c hy .

— ITU-T G.803: Architecture of Transport Net-

works Based on the Synchronous Digital Hier­archy.

— T1.105: SONET-Basic Description including

Multiplex Structure, Rates, and Formats.
— T1.105.02 SONET-Payload Mappings.
— T1.105.03 SONET-Jitter at Network Interfaces.
— T1.105.06 SONET Physical Layer Specifica-

tions.
— T1.105.07 SONET-Sub-STS-1 Interface Rates

and Formats Specification.
— ITU-T I.432: B-ISDN User-Network Interface-

Physical Layer Specification.
— IETF RFC 2615 (June 1999): PPP over

SONET/SDH.
— IETF RFC 1661: The Point-to-Point Protocol

(PPP).
— IETF RFC 1662: PPP in HDLC-like Framing.

Data Processing

Provisionable data engine supports payload inser-

■

tion/extraction and CRC-16/-32 generation/verifica­tion for ATM cell or PPP, SDL, or HDLC streams.

Maintains counts for cell/packet traffic (e.g., total

■

number of cells, number of discarded cells).
Integrated UTOPIA Level 2- and UTOPIA Level 3-

■

compatible ATM physical layer interface with
packet extensions for all test and operations.

Insertion and extraction of up to four separate data

■

channels.
Compliant with 1998: ATM Forum, ITU standards,

■

and IETF standards.

Compliant with the following Telcordia† (Bellcore),

■

ANSI*, and ITU standards:
— GR-253 CORE: SONET Transport Systems:

Common Generic Criteria.

*ANSI is a registered trademark of American National Standards

Institute, Inc.

†Telcordia is a registered trademark of Bell Communications

Research, Inc.

Microprocessor Interface

16-bit address and 16-bit data interface with up to

■

66 MHz read and write acces s.
Compatible with most industry-standard proces-

■

sors.

Please see the Description section, page 11, for
details.

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Table of Contents

Contents Page

Features ...................................................................................................................................................................3

SONET/SDH Interface ...........................................................................................................................................3

Data Processing .....................................................................................................................................................3

Microprocessor Interface .......................................................................................................................................3

Description ......................... ............. ............. ............. ............. ............. ............ ............. ...........................................11

Pin Information .......................................................................................................................................................11

Overview ...................... ...... ...... ....... ...... ....... ...... ....... ...... ....... ...................................... ...........................................45

ATM/HDLC/HDLC-CRC/PPP Support ...................................................................... ....... ....................................47

SDL Support ........................................................................................................................................................48

Over-Fiber Mode .............................................................................. ....................................................................49

Test and General-Purpose I/O Support ...............................................................................................................49

External Interfaces ................................................. ..............................................................................................49

Functional Description ............. ....................................... ........................................................................................50

Line Interface Block ..................................................... ....... ...... ....... ....................................................................51

SONET Framer ...................................................... ..............................................................................................53

Overhead Processor (OHP) Block .......................................................................................................................53

Path Terminator (PT) Block ......... ....................................... ...... ....... ...................................... . .............................62

Data Engine (DE) Block .......................................................................................................................................70

UTOPIA (UT) Interface Block ...............................................................................................................................84

JTAG (Boundary-Scan) Tes t B lock ....................................................................................................................100

Line Interface ........................................................................................................................................................100

LVPECL I/O Termination and Loa d Spec i ficati ons ................................................... ....... ...... ....... .....................100

Interface Description .............................................................................................................................................101

Microprocessor Interface ...................................................................................................................................101

General-Purpose I/O Bus (GPIO) ......................................................................................................................102

Interrupts ......................... .................................................... ...............................................................................103

Reset ............................... ................... ............. .................... ................... ................... .........................................104

Performance Monitor Reset (PMRST) ...............................................................................................................104

Loopback Operation ...........................................................................................................................................106

System Interfaces ........................................... ....... ...... ....... ...... ....... ..................................................................107

Register Access Description ..................................................................... ............................................................111

Register Maps ....................................................................................................... ...............................................112

Core Registers ............................................................. ....... ...... ....... ...... ............................................................112

UT Registers ................................................................................................ ......................................................113

OHP Registers ...................... ....................................... ....... ...................................... ....... ..................................116

PT Registers ............................................. .........................................................................................................126

DE Registers ............. ...... ....................................... ...... ....................................... ...... ..... ....................................138

Register Descriptions ...........................................................................................................................................147

Core Registers ............................................................. ....... ...... ....... ...... ............................................................147

UT Registers ................................................................................................ ......................................................154

OHP Registers ...................... ....................................... ....... ...................................... ....... ..................................165

PT Registers ............................................. .........................................................................................................192

DE Registers ............. ...... ....................................... ...... ....................................... ...... ..... ....................................211

Absolute Maximum Ratings ..................................................................................................................................253

Handling Precautions ..................... ...... ....... ...... ....................................... ...... ....... ...... ....... ..................................253

Operating Conditions ............... ....... ...... ....... ...... ....... ...................................... ....... ...... ....... ..................................254

Electrical Characterist ic s ................................................................................ ......................................................254

4 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Table of Contents

(continued)

Contents Page

Interface Timing Specifications .............................................................................................................................255

Microprocessor Interface Timing ........................................................................................................................255

Line Interface I/O Timing ........................... ...... ....... ...................................... ....... ...... ....... ..................................264

UTOPIA Interface Timing ...................................................................................................................................268

Transport Overhead Access Ch ann el (TOAC ) Interface Timing .................. ....... ....................................... ........271

Reference of SONET/SDH Terms and Comparisons ...........................................................................................273

Definitions of SONET/SDH Bytes .......................................................................................... ............................273

SONET/SDH Comparisons .......................................... ....................................... ...............................................274

SONET/SDH New Terminology .........................................................................................................................274

Outline Diagram ........................................... ...... ....... ...... ....... ...................................... .........................................275

600-Pin LBGA ....................................................................................................................................................275

Ordering Information ... ....... ...... ....... ...... ....... ...... ....... ...... ....... ...... .........................................................................276

DS98-193SONT-4 Replaces DS98-193SONT-3 to Incorporate the Following Updates ......................................276

Agere Systems Inc. 5

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

List of Figures

Contents Page

Figure 1. Pin Diagram of 600-Pin LBGA (Bottom View) .........................................................................................11

Figure 2. Overview Block Diagram .................... ....................................... ...... ....... ...... ....... ...... ..............................45

Figure 3. Interface Block Diagram ............................................................ ..............................................................46

Figure 4. External Interface Summary Di agram ............. ....... ...................................... ....... ....................................49

Figure 5. Functional Block Dia gram ................................................... ...... ..............................................................50

Figure 6. Signal Degrade and Failure Parameters for BER ........................................ ....... ....................................56

Figure 7. Pointer Interpreter State Diagram ................................................... ....... ...... ....... ...... ..............................62

Figure 8. STS-48 Signal Carrying One STS-48c Frame ........................................................................................65

Figure 9. STS-48 Signal Carrying Four STS-12c Frames ........... ....................................... ...... ..............................66

Figure 10. Quad STS-12 Configuration With Each STS-12 Signal Carrying One STS-3c Frame ..........................66

Figure 11. Quad STS-12 Configuration With Each STS-12 Signal Carrying One STS-12c Frame (Channel A), One

STS-9c Frame (Channel B), One STS -6 c Frame (Cha nne l C), and One STS-3c Fr ame ( Chan nel D) .67

Figure 12. Quad STS-3 Configuration With Each STS-3 Signal Carrying One STS-2c Frame ..............................67

Figure 13. Block Diagram of Date Engine (DE) ......................................................................................................70

Figure 14. State Diagram for the X31 Scram ble r Synchr oni zati on Proc ess ... ....... ...... ....... ...... ....... .......................72

Figure 15. General Structure of SDL Packets ........................................................................................................72

Figure 16. Uncompressed and Compressed PPP Packets ......... ............................................. ..............................75

Figure 17. Example of Tx/Rx Sequence r C onf igurat ion: STS-48c into Single OC-48 S ignal ............................. ....78

Figure 18. Example of Tx/Rx Sequencer Configuration: 4xSTS-12c into Four Independent OC-12 Signals .........79

Figure 19. SONET Multiplexing: 2-Stage Byte Interleaving Example .....................................................................80

Figure 20. Example of Tx/Rx Sequencer Configuration: 4xSTS-3c into Four Independent OC-3 Signals ............. 81

Figure 21. TDAT042G5 Over-Fiber Modes: SDL, ATM (X31) ................................................................................82

Figure 22. UT Block Diagram .. ....... ....................................... ...... ....................................... ....................................84

Figure 23. Receive-Side Interface Hand sh ak ing in Po int -to -Poi nt, Single Cyc le Mod e ........................ ....... ..........91

Figure 24. Receive-Side Interface Hand sh ak ing in Po int -to -Poi nt, Two-Cycle Mode ............................................92

Figure 25. Transmit-Side Interfac e Hand shak ing in Po int-to-Point, Single Cycle Mod e ........................................95

Figure 26. Multi-PHY Configuration of All Four Channels ......................................................................................96

Figure 27. TxPA Two-Cycle Responses of a Multi-PHY for All Four Channels ......................................................98

Figure 28. RxPA Responses of a Mult i-P HY for All Four Ch annels (PA Response Configured for One Cycle) ....99

Figure 29. GPIO Functionality ..................................................... ....... ...... ............................................................102

Figure 30. Interrupt Functionality ..........................................................................................................................103

Figure 31. Miscellaneous Functionality ....................................... ....................................... ...... .... ........................104

Figure 32. Loopback Opera tion ................................................... ....................................... ...... ............................106

Figure 33. Quad ATM UTOPIA 2 ....................... ....................................... ...... ....... ...............................................107

Figure 34. Single ATM UTOPIA 3 ............................ ...................................... ....... ...... .........................................108

Figure 35. Quad POS UTOPIA 2 ................. ...... ....................................... ...... ......................................................109

Figure 36. Single POS UTOPIA 3 ............................ ...... ....... ...................................... ....... ...... ............................110

Figure 37. 32-bit MPHY UTOPIA 3 .......................................................................................................................110

Figure 38. Microprocessor Interface Synchronous Write Cycle (MPMODE (Pin D8) = 1) ....................................256

Figure 39. Microprocessor Interface Synchronous Read Cycle (MPMODE (Pin D8) = 1) ...................................258

Figure 40. Microprocessor In terfac e As ynch ro nou s Write Cy cl e Descr iption (MPMODE (Pin D8) = 0) ....... ...... ..260

Figure 41. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin D8) = 0) ..................................262

Figure 42. Receive Line-Side Tim ing W ave form ...................................................................... ....... .....................264

Figure 43. Transmit Line-Side Timing Waveform—STS-48/STM-16 Contra cloc king .. ....... ...... ....... ...... ....... ...... ..265

Figure 44. Transmit Line-Side Timing Waveform—Frame Synch ............................... ....... ...... ....... .....................26 5

Figure 45. Transmit Line-Side Timing Waveform—STS-48/STM-16 Forw ard Clocki ng ....................... ....... ...... ..265

Figure 46. Transmit UTOPIA Interface Timing .....................................................................................................268

Figure 47. Receive UTOPIA Interfac e Timing ....................................................... ...... .........................................269

Figure 48. Transmit TOAC Interface Timing .........................................................................................................271

Figure 49. STS-12/STM-4 and STS-48/STM-16 Receive TOAC Interface Timing ...............................................272

Figure 50. STS-3/STM-1 Receive TOAC Interface Timing ...................................................................................272

6 Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

List of Tables

Contents Page

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order .......................................................................12

Table 2. Pin Assignments for 600-Pin LBGA by Signal Name ...............................................................................17

Table 3. Pin Descriptions—Line Interface Signals .................................................................................................22

Table 4. Pin Descriptions—TOH Interface Signals .................................................................................................27

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals ..........................................................................28

Table 6. Pin Descriptions—Microprocessor Interface Signals ............................................................... .................40

Table 7. Pin Descriptions—General-Purpose I/O Signals: Interface Signals .........................................................41

Table 8. Pin Descriptions—JTAG Int erf ac e Signals .......................... ....................................... ..............................42

Table 9. Pin Descriptions—Power Signals .................................. ....................................... ....................................43

Table 10. Pin Descriptions—No Connect Pins ............................ ...... ....... ....................................... ...... ....... ...... ....44

Table 11. Optional Offset Field ...............................................................................................................................48

Table 12. Line Interface Modes ..............................................................................................................................51

Table 13. Clock Settings for CLKDIV Pin .......................................... ....... ...... ....... ...... ...........................................52

Table 14. R/T TOH Interface Rates ........................................................................................................................53

Table 15. TOAC Byte Insertion: An STS-3/STM-1 Example ..................................................................................53

Table 16. Ns, L, M, and B Values to Set the BER Indicator ...................................................................................57

Table 17. Ns, L, M, and B Values to Clear the BER Indicator ................................................................................58

Table 18. TOAC Channel I/O vs. STS Number/Time Slot ......................................................................................59

Table 19. Types of Signal Labels ...........................................................................................................................64

Table 20. 1-bit Mode ...............................................................................................................................................64

Table 21. 3-bit Mode (Enhanced RDI) ....................................................................................................................64

Table 22. Valid Concatenation Starting Locations: STS-Mc into an STS-48c ........................................................68

Table 23. Packet Length Field ................................................................................................................................73

Table 24. UTOPIA Traffic Types ............................................................................................................................85

Table 25. Standard 53-byte ATM Cell Structure .....................................................................................................86

Table 26. Bus Format for 16-bit Interface ...............................................................................................................86

Table 27. Bus Format for 8-bit Interface .................................................................................................................87

Table 28. Bus Format for 32-bit Interface ...............................................................................................................87

Table 29. Egress High Watermark Thresholds .......................................................................................................94

Table 30. Nominal dc Power for Suggested Terminations ...................................................................................100

Table 31. MPU Modes ..........................................................................................................................................101

Table 32. PMRST Provisioning ............................................................................................................................105

Table 33. Quad ATM UTOPIA 3 Interface ............................................................................................................107

Table 34. Quad POS UTOPIA 3 Interface ............................................................................................................109

Table 35. Register Address Space .......................................................................................................................111

Table 36. Map of Core Registers ..........................................................................................................................112

Table 37. Map of UT Registers .............................................................................................................................113

Table 38. Map of OHP Registers ..........................................................................................................................116

Table 39. Map of Path Terminator Registers ........................................................................................................126

Table 40. Map of DE Registers ............................................................................................................................138

Table 41. Register 0x0000: Device Version (RO) ................................................................................................147

Table 42. Registers 0x0001—0x0005: Device Name (RO) ..................................................................................147

Table 43. Register 0x0008: Composite Interrupts (RO or COR/W) ......................................................................148

Table 44. Register 0x000A: GPIO Input (RO) ......................................................................................................148

Table 45. Register 0x000C: Block Interrupt Masks (R/W) ........................................... .........................................149

Table 46. Register 0x000E: Core Resets (WO) ...................................................................................................149

Table 47. Register 0x000F: GPIO Output (R/W) ..................................................................................................150

Table 48. Register 0x0010: Line Provisioning/Mode (R/W) ..................................................................................150

Table 49. Register 0x0011: Channel (A—D) Contr ol (R/W ) ........................... ......................................................151

Table 50. Register 0x0012: Loopback Control (R/W) ...........................................................................................151

Table 51. Register 0x0013: GPIO Mode (R/W) ....................................................................................................152

Agere Systems Inc. 7

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

List of Tables

(continued)

Contents Page

Table 52. Registers 0x0014, 0x0015: GPIO Output Configuration .......................................................................152

Table 53. Register 0x001F: Scratch (R/W) ...........................................................................................................153

Table 54. Register 0x0200: UT Macrocell Version Number (RO) ........................................................................154

Table 55. Register 0x0201: UT Interrupt (RO) .....................................................................................................154

Table 56. Registers 0x0202, 0x0203, 0x0204, 0x0205: Channel [A—D] (COR) ..................................................155

Table 57. Register 0x0206: Interrupt Mask (R/W) ................................................................................................156

Table 58. Registers 0x0207, 0x0208, 0x0209, 0x020A: Interrupt Mask—Channel [A—D] (R/W) ......... ....... ........156

Table 59. Register 0x020B: Channel [A—D] Error Count in PMRST Mode (RO) ................................................156

Table 60. Fields of the Provisioning Registers .....................................................................................................157

Table 61. Registers 0x020F, 0x0213, 0x0217, 0x021B: Channel [A—D] Rec ei ve Prov is i oni ng Regi ste r (R /W) .158
Table 62. Registers 0x0210, 0x0214, 0x0218, 0x021C: Channel [A—D] Tran smit Provisioning Regist er (R/W) 159
Table 63. Registers 0x0211, 0x0215, 0x0219, 0x021D: Channel [A—D] Ingress Pro vi sioni ng Regi ster (R/W) ..161
Table 64. Registers 0x0212, 0x0216, 0x021A, 0x021E: Channel [A—D] Egress Provisioning Register (R/W) ...161

Table 65. Register 0x021F: Reset Register (R/W) ...............................................................................................162

Table 66. Register 0x0220: Channel [A—D] Error Count (RO) ...................... ....... ...... ....... ...... ....... .....................16 2

Table 67. Register 0x0224: UT_Scratch Register (R/W) ......................................................................................162

Table 68. Register 0x0225: PA Response Register (R/W) ...................................................................................163

Table 69. Register 0x0226: Size Mode Register (R/W) ........................................................................................164

Table 70. Register 0x0400: OHP Macrocell Version Number (RO) .....................................................................165

Table 71. Register 0x0401: OHP Interrupt (RO) ..................................................................................................165

Table 72. Registers 0x0402—0x0409: Delta/Event (COR/W) ..............................................................................165

Table 73. Registers 0x040A—0x040D: Receive/Transmit State (RO) .................................................................168

Table 74. Registers 0x040E, 0x0410, 0x0412, 0x0414: Mask Bits (R/W) ............................................................169

Table 75. Registers 0x040F, 0x0411, 0x0413, 0x0415: Mask Bits (R/W) ............................................................170

Table 76. Registers 0x0416—0x0419: Toggles (R/W) .........................................................................................171

Table 77. Registers 0x041A, 0x041C, 0x041E, 0x0420: Continuous N Times Detect (CNTD) Values (R/W) .....171

Table 78. Registers 0x041B, 0x041D, 0x041F, 0x0421: Continuous N Times Detect (CNTD) Values (R/W) .....172

Table 79. Registers 0x0422—0x042D: Receive Contr ol (R/W) ... ....................................... ...... ....... ...... ...............173

Table 80. Registers 0x042E: Transmit Control Port A (R/W) ...............................................................................177

Table 81. Registers 0x042F, 0x0431, 0x0433, 0x0435: Transmit Control (R/W) .................................................180

Table 82. Registers 0x0430, 0x0432, 0x0434: Transmit Control Port [B—D] (R/W) ............................................181

Table 83. Registers 0x0436—0x0439: Transmit Control (R/W) ...........................................................................184

Table 84. Registers 0x043A—0x0451: OHP Signal Degrade BER Algorithm Parameters (R/W) ........................185

Table 85. Registers 0x0452—0x0469: OHP Signa l Fail BE R Algori thm Pa r ame ters (R/ W) ................................186

Table 86. Ns, L, M, and B Values to Set the BER Indicator .................................................................................187

Table 87. Ns, L, M, and B Values to Clear the BER Indicator ..............................................................................188

Table 88. Registers 0x046A—0x047D: B1, B2, M1 Error Count (RO) .................................................................189

Table 89. Registers 0x047E—0x0485: Transmit F1, S1, K2, K1 OH Insert Value (R/W) ....................................189

Table 90. Registers 0x0486—0x0491: Receive F1, S1, K2, K1 Monitor Value (RO) ...........................................190

Table 91. Registers 0x0492—0x04F9: Receive J0 Monitor Value (R O) ............................................... ....... ...... ..190

Table 92. Registers 0x0512—0x0579: Transmit J0 Insert Value (R/W) ...............................................................190

Table 93. Registers 0x05AA—0x05C1: Transmit Z0 Insert Value (R/W) .............................................................191

Table 94. Register 0x05C2: Scratch Register (R/W) ............................................................................................191

Table 95. Register 0x0800: PT Macrocell Version Number (RO) .........................................................................192

Table 96. Register 0x0801: PT Interrupt (RO) ......................................................................................................192

Table 97. Registers 0x0802, 0x080F, 0x081C, 0x0829 and 0x0803, 0x0810, 0x081D, 0x082A:

PT Delta/Event Parameters (COR/W) ......................................................... .........................................192

Table 98. Registers 0x0836—0x083B, 0x0868—0x0887, 0x0888—0x088D, 0x08BA—0x08D9,

0x08DA—0x08DF, 0x09 0C—0x092B, 0x092C—0x0931, 0x095E—0x097D:

PT State Registers (RO) .......................................................... ....................................... .....................194

Table 99. Register 0x097E: PT Interrupt Mask Control (R/W) .............................................................................195

8 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

List of Tables

(continued)

Contents Page

Table 100. Registers 0x097F—0x0980, 0x098C—0x098D, 0x0999—0x099A, 0x09A6—0x09A7: PT Interrupt

Mask Control (R/W) ......................................................... ....................................... ............................196

Table 101. Registers (0x09B3, 0x09BF, 0x09CB, 0x09D7, 0x09E3), (0x09EF, 0x09FB, 0x0A07, 0x0A14, 0x0A20),

(0x0A2C, 0x0A38, 0x0A44, 0x0A50, 0x0A5C), (0x0A68, 0x0A74, 0x0A80, 0x0A8C, 0x0A98):

Error Counters (RO) ...........................................................................................................................198

Table 102. Register 0x0AA4: PT One-Shot Control Parameters (WO) ................................................................198

Table 103. Registers 0x0AA6—0x0AAD, 0x0AAE, 0x0AB5, 0x0AB6—0x0ABD, 0x0ABE—0x0AC5:

PT Control Parameters (R/W) ......... ....................................... ............................................................199

Table 104. Registers 0x0AC6—0x0AF7: PT Provisioning (R/W) ...... ...................................................................205

Table 105. Registers 0x0ACC—0x0AD1: PT Signal Fail BER Algorithm Parameters (R/W) ...............................206

Table 106. Registers 0x0AD2—0x0AD7: PT Signal Degrade BER Algorithm Parameters (R/W) .......................207

Table 107. Ns, L, M, and B Values to Set the BER Indicator ...............................................................................208

Table 108. Ns, L, M, and B Values to Clear the BER Indicator ............................................................................209

Table 109. Registers 0x0AD8—0x0AF7: Transmit J1 Data Insert (R/W) .............................................................210

Table 110. Register 0x0AF8: Scratch Register (R/W) ..........................................................................................210

Table 111. Register 0x1000: DE Macrocell Version Number (RO) ......................................................................211

Table 112. Register 0x1001, 0x1002: DE Inte rrup ts (0x1 001 is RO, 0x10 02 is RO and COR/W ) .......................211

Table 113. Register 0x1004: Dry Escape Marker (R/W) ......................................................................................213

Table 114. Registers 0x1010—0x1015: Sequencer Provisioning Registers (R/W) ..............................................214

Table 115. Registers 0x1016—0x1021: Egress Configuration (R/W) ..................................................................215

Table 116. Registers 0x1022—0x102D: Ingress Configuration (R/W) .................................................................219

Table 117. Registers 0x102E—0x1031: Over-Fiber Mode (Packet-Over -Fiber or POF) Control (R/W) ..............223

Table 118. Registers 0x1032—0x1036: Sequencer Cell State Registers (R/W) ..................................................225

Table 119. Registers 0x1040—0x1043: Ingress Payload Type and Mode Control (R/W) ...................................225

Table 120. Receive Type and Mode Control Summary Table (Registers 0x1040—0x10 43) ............................. .. 226

Table 121. Registers 0x1080—0x1087: ATM Framer Idle Cell Match Mask (R/W) .............................................227

Table 122. Registers 0x1088—0x108F: ATM Idle Cell Registers (R/W) ..............................................................227

Table 123. Registers 0x1090—0x1097: ATM Unassigned Cell Match Mask (R/W) .............................................228

Table 124. Registers 0x1098—0x109F: ATM Unassigned Cell Registers (R/W) .................................................228

Table 125. Registers 0x10A0—0x10A3: ATM Framer State Registers (RO) .......................................................229

Table 126. Register 0x10A4: ATM X43 Frame Control (R/W) ..............................................................................229

Table 127. Register 0x10A5: ATM X31 Frame Control (R/W) ..............................................................................230

Table 128. Register 0x10A6: ATM X31 V/W Values (R/W) ..................................................................................230

Table 129. Register 0x10A7: ATM X31 X/Y Values (R/W) ...................................................................................231

Table 130. Register 0x10A8: ATM X31 Z Value (R/W) ........................................................................................231

Table 131. Register 0x10A9: Frame State Interrupt Mask (R/W) .........................................................................232

Table 132. Register 0x10AA: Scrambler State Interrupt Mask (R/W) ..................................................................232

Table 133. Register 0x10AB: ATM Receive Debug Register (R/W) .....................................................................233

Table 134. Registers 0x10B0—0x10B3: PPP Attach (R/W) .................................................................................234

Table 135. Registers 0x10E0—0x10E3: Egress Payload Type and Mode Control (R/W) ...................................234

Table 136. Transmit Type and Mo de Contr ol S umm ar y Table (Registers 0x10E0—0x10E3) ............................. 235

Table 137. Registers 0x10F0—10FB: PPP Header Value Detach (R/W) ............................................................235

Table 138. Registers 0x10FC—0x10FF: PPP Header Detach Search (R/W) ......................................................236

Table 139. Registers 0x1100—0x1107: ATM/HDLC/SDL Framer—Condition Counter 1

(PMRST Update) (RO) .......................................................................................................................238

Table 140. Registers 0x1108—0x110F: ATM/HDLC/SDL Framer—Condition Counter 2

(PMRST Update) (RO) .......................................................................................................................239

Table 141. Registers 0x1110—0x1117: CRC Checker—Bad Packet Counte r (PMRST Update) (RO) ...............240

Table 142. Registers 0x1118—0x111F: PPP Detach—Mismatched Header Counter (P MRST Update) (RO) ...241

Table 143. Registers 0x1120—0x1127: Receive Good Packet/Cell Counter (PMRST Update) (RO) .................242

Table 144. Registers 0x1128—0x112F: Transmit Good Packet/Cell Counter (PMRST Update) (RO) ................243

Agere Systems Inc. 9

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Data Sheet

May 2001

List of Tables

(continued)

Contents Page

Table 145. Registers 0x1180—0x1186: Interrupt Masks for Packet Counters (R/W) ..........................................243

Table 146. Registers 0x1181—0x1187: Interrupts for Packet Counters (COR/W) ..............................................244

Table 147. Registers 0x1200—0x1213, 0x12F0: ATM Transmit Registers (R/W) ...............................................244

Table 148. Registers 0x1400—0x1403: SDL State Registers (RO) .....................................................................246

Table 149. Registers 0x1470—0x1473: A Me ss ag e M ail box Registers (RO) .................................................... ..247

Table 150. Registers 0x1480—0x1483: A Me ss ag e M ail box Registers (RO) .................................................... ..247

Table 151. Registers 0x1490—0x1493: A Me ss ag e M ail box Registers (RO) .................................................... ..247

Table 152. Registers 0x14A0—0x14A3 : B Mess age Mailb ox Regis ters (RO) ............ ....... ...... ....... ...... ....... ........247

Table 153. Registers 0x14B0—0x14B3 : B Mess age Mailb ox Regis ters (RO) ............ ....... ...... ....... ...... ....... ........248

Table 154. Registers 0x14C0—0x14C3: B Mess age Mailbox Registers (RO) ...... ....................................... ...... ..248

Table 155. Registers 0x14D0—0x14D3: SDL Interrupt Masks (R/W) ..................................................................248

Table 156. Registers 0x14E0—0x14E3: SDL Interrupts (COR/W) ......................................................................249

Table 157. Register 0x14F0: SDL Recei ve Con figuration Registers (R/W) .......... ...... ....... ...... ....... .....................249

Table 158. Registers 0x1600—0x1607: SDL Transmit Registers (R/W) ..............................................................250

Table 159. Recommended Operating Conditions ................................................................................................254

Table 160. 3.3 V Logic Interface Characteristics ..................................................................................................254

Table 161. LVPECL Interface Characteristics ......................................................................................................254

Table 162. LVPECL 3.3 V Logic Interface Characteristics ...................................................................................255

Table 163. Microprocessor Interface Synchronous Write Cycle Specifications ...................................................257

Table 164. Microprocessor Interface Synchronous Read Cycle Specifications ...................................................259

Table 165. Microprocessor Interface Asynchronous Write Cycle Specifications ..................................................261

Table 166. Microprocessor Interface Asynchronous Read Cycle Specifications .................................................263

Table 167. Receive Line-Side Timing Specifications ...........................................................................................266

Table 168. Transmit Line-Side Timing Specifications ..........................................................................................267

Table 169. Transmit UTOPIA Interface Timing Specifications .............................................................................268

Table 170. Receive UTOPIA Interface Timing Specifications ..............................................................................269

Table 171. UTOPIA Interface Clock Specifications ..............................................................................................270

Table 172. Transmit TOAC Interface Timing Specifications .................................................................................271

Table 173. Receive TOAC Interface Timing Specifications ..................................................................................272

Table 174. SONET/SDH Comparisons ................................................................................................................274

Table 175. SONET/SDH New Terminology ..........................................................................................................274

10 Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Description

The TDAT042G5 SONET/SDH interface device provides a versatile solution for quad STS-3/STM-1,
quad STS-12/STM-4, and for single STS-48/STM-16 point-to-point datacom/telecom applications. Constructed
using Agere Systems Inc.’s state-of-the-art CMOS technology, this device incorporates integrated SONET/SDH
framing, section and line overhead insertion and extraction, path termination, and generation.

The integra ted circuit provides complete encapsulation and decapsulation for packet and ATM streams into and
out of SONET/SDH payloads.

Communication with the device is accomplished through a generic microprocessor interface. The device supports
separate address and data buses.

With the device, construction of all types of point-to-point STS-3/STS-12/STS-48 (STM-1/STM-4/
STM-16) data equipment is simplified and cost-reduced, allowing extremely efficient solutions.

Pin Information

TDAT042G5 is available in a 600-pin LBGA package. The pin diagram is shown in Figure 1. For convenience, pin
assignments are listed by pi n o rd er in Table 1 and by signal name in Table 2. The pin descr i pti ons as well as the
pin assignments are listed in Table 3—Table 10 and are grouped by interface type.

AR
AP
AN

AM

AL

AK

AJ

AH

AG

AF
AE
AD
AC
AB
AA

Y

W

V

U

T

R

P

N

M

L
K

J
H
G

F

E
D
C

B

A

523257312915 2132711 179131 3533

19

3026 2824 32222018468101214162 34

5-7175(F)

Figure 1. Pin Diagram of 600-Pin LBGA (Bottom View)

Agere Systems Inc. 11

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

(continued)

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

A1 V
A2 V

DDD
DDD

A3 GND
A4 GND
A5 V
A6 V

DDD
DDD

A7 GND
A8 GND

D
D

D
D

B1 V
B2 V
B3 GND
B4 GND
B5 NC C5 NC D5 NC
B6 V
B7 INT C7 RST D7 PMRST
B8 CS C8 MPCLK D8 MPMODE

A9 DATA[1] B9 DATA[0] C9 DS

DDD
DDD

DDA

DDD

D
D

D1 GND
D2 GND
D3 GND

D

A

D4 V

D6 NC

C1 GND
C2 GND

D
D

C3 V
C4 GND

C6 GND

D
D
D

DDD

D9 R/W
A10 DATA[6] B10 DATA[5] C10 DATA[4 ] D10 DATA[3]
A11 DATA[10] B11 DATA[9] C11 DATA[8] D11 DATA[7]
A12 DATA[15] B12 DATA[14] C12 DATA[13] D12 DATA[12]
A13 GND

D

B13 ADDR[3] C13 ADDR[2] D13 ADDR[1]
A14 ADDR[8] B14 ADDR[7] C14 ADDR[6] D14 ADDR[5]
A15 ADDR[12] B15 ADDR[11] C15 ADDR[10] D15 NC
A16 GND
A17 V
A18 V

DDD
DDD

D

B16 ADDR[15] C16 ADDR[14] D16 ADDR[13]

B17 NC C17 NC D17 NC

B18 NC C18 NC D18 NC
A19 NC B19 NC C19 NC D19 NC
A20 GND

D

B20 NC C20 NC D20 NC
A21 NC B21 NC C21 NC D21 NC
A22 NC B22 NC C22 NC D22 NC
A23 GND

D

B23 NC C23 NC D23 NC
A24 NC B24 NC C24 NC D24 NC
A25 NC B25 NC C25 NC D25 NC
A26 NC B26 NC C26 NC D26 NC
A27 GND
A28 GND
A29 GND
A30 V
A31 V
A32 GND
A33 GND
A34 V
A35 V

Note: NC refers to no connect. Do not connect pins so designated.

DDD
DDD

DDD
DDD

D
D
D

B27 NC C27 NC D27 V

B28 NC C28 NC D28 NC

B29 NC C29 NC D29 NC

DDD

B30 NC C30 NC D30 NC

B31 NC C31 NC D31 NC

D
D

B32 GND

B33 GND

B34 V

B35 V

DDD
DDD

D
D

C32 GND
C33 V
C34 GND
C35 GND

DDD

D

D32 V
D33 GND

D
D

D34 GND
D35 GND

DDD

D
D
D

12 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

(continued)

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

E1 V

DDD

F1 V

DDD

J31 TxEOP[A] N1 GND

D

E2 NC F2 TCK J32 TxSOP/C[A] N2 TxD[6]N
E3 V
E4 GND
E5 V

DDD

PLL F3 GND

D

PLL F4 TMS J34 TxDATA[A][15] N4 TxD[7]N

DDD

F5 NC J35 TxDATA[A][14] N5 TxD[7]P

D

J33 TxPRTY[A] N3 TxD[6]P

E6 NC F31 NC K1 TxD[12]N N31 RxDATA[A][15]
E7 ICT
E8 DT

E9 ADS
E10 DATA[2] F35 V
E11 V

DDD

F32 NC K2 TxD[12]P N32 RxDATA[A][14]
F33 NC K3 TxD[13]N N33 RxDATA[A][13]
F34 NC K4 TxD[13]P N34 RxDATA[A][12]

DDD

G1 GND

K5 V

D

K31 TxDATA[A][13] P1 TxD[4]N

DDD

N35 GND

D

E12 DATA[11] G2 TDO K32 TxDATA[A][12] P2 TxD[4]P
E13 ADDR[ 0] G3 TRST
E14 ADDR[4] G4 NC K34 TxDATA[A][10] P4 V

K33 TxDATA[A][11] P3 TxD[5]N

DDD

E15 ADDR[9] G5 TDI K35 TxDATA[A][9] P5 TxD[5]P
E16 V

DDD

G31 NC L1 TxD[10]N P31 RxDATA[A][11]
E17 NC G32 TxADDR[0] L2 TxD[10]P P32 RxDATA[A][10]
E18 NC G33 TxADDR[1] L3 TxD[11]N P33 RxDATA[A][9]
E19 NC G34 TxCLK[A] L4 TxD[11]P P34 RxDATA[A][8]
E20 V
E21 NC H1 GND

DDD

G35 GND

D
D

L5 V

L31 V

DDD
DDD

P35 RxDATA[A][7]

R1 V

DDD

E22 NC H2 TxCKQP L32 TxDATA[A][8] R2 TxD[2]N/TxD[B]N
E23 NC H3 GND

D

L33 TxDATA[A][7] R3 TxD[2]P/TxD[B]P
E24 NC H4 CLKDIV L34 TxDATA[A][6] R4 TxD[3]P/TxD[A]P
E25 V

DDD

H5 GND

D

L35 TxDATA[A][5] R5 TxD[3]N/TxD[A]N
E26 NC H31 TxSZ[A] M1 TxD[8]N R31 RxDATA[A][6]
E27 NC H32 TxERR[A] M2 TxD[8]P R32 RxDATA[A][5]
E28 NC H33 TxPA[A] M3 TxD[9]N R33 RxDATA[A][4]
E29 NC H34 TxENB[A] M4 TxD[9]P R34 RxDATA[A][3]
E30 NC H35 GND
E31 V

DDD

J1 TxD[14]N M31 TxDATA[A][4] T1 GND

D

M5 V

DDD

R35 RxDATA[A][2]

D

E32 NC J2 TxD[14]P M32 TxDATA[A][3] T2 TxD[0]P/TxD[D]P
E33 NC J3 TxD[15]N M33 TxDATA[A][2] T3 TxD[1]N/TxD[C]N
E34 NC J4 TxD[15]P M34 TxDATA[A][1] T4 TxD[1]P/TxD[C]P
E35 V

Note: NC refers to no connect. Do not connect pins so designated.

DDD

J5 TxCKQN M35 TxDATA[A][0] T5 V

DDD

Agere Systems Inc. 13

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

(continued)

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

T31 V

DDD

Y1 GND

T32 RxDATA[A][1] Y2

T33 RxDATA[A][0] Y3

T34 RxPRTY[A] Y4 GND
T35 GND

D

Y5 V
U1 TxFSYNCN Y31 V
U2 TxD[0]N/

Y32 TxSZ[B] AD2 RxD[5]P AG32 RxDATA[B][6]

D

RxD[13]N/
RxCLK[B]N

RxD[13]P/
RxCLK[B]P

D
DDD
DDD

AC31 TxDATA[B][8] AG1 RxD[0]N
AC32 TxDATA[B][9] AG2 RxD[0]P

AC33 TxDATA[B][10] AG3 ECLREFLO

AC34 TxDATA[B][11 ] AG4 ECLREFHI
AC35 GND

D

AG5 GPIO[3]

AD1 RxD[5]N A G31 RxDATA[B][5]

TxD[D]N
U3 TxFSYNCP Y33 TxCLK[B] AD3 RxD[6]N AG33 RxDATA[B][7]
U4 TxCKP Y34 TxADDR[3] AD4 RxD[6]P AG34 RxDATA[B][8]
U5 TxCKN Y35 GND

U31 RxSOP/C[A] AA1
U32 RxEOP[A] AA2

U33 NC AA3
U34 RxENB[A] AA4
U35 V

V1 V
V2 V
V3 GND
V4
V5

V31 GND

DDD
DDD
DDD

D

RxCKN/RxD

RxCKP/RxD

D

[A]
[A]

AA5 GND
AA31 TxEOP[B] AE1 RxD[3]N AH31 RxDATA[B][1]
AA32 TxSOP/C[B] AE2 RxD[3]P AH32 RxDATA[B][2]
AA33 TxENB[B] AE3 RxD[4]N AH33 RxDATA[B][3]

N

AA34 TxPA[B] AE4 RxD[4]P AH34 RxDATA[B][4]

P

AA35 TxERR[B] AE5 V

AB1

V32 RxERR[A] AB2
V33 RxPA[A] AB3
V34 NC AB4
V35 V

W1 V

DDD
DDD

W2 RxD[14]N

/

AB5 V
AB31 TxDATA[B][13] AF1 RxD[1]N AJ31 RxEOP[B]
AB32 TxDATA[B][12] AF2 RxD[1]P AJ32 RxSOP/C[B]

D

RxD[11]N/
RxCLK[C]N

RxD[11]P/RxCLK[C]P
RxD[12]N/RxD[C]N
RxD[12]P/RxD[C]P

D

RxD[9]N/RxCLK[D]N
RxD[9]P/RxCLK[D]P
RxD[10]N/RxD[D]N
RxD[10]P/RxD[D]P

DDD

AD5 V

AD31 TxDATA[B][3] AH1 GND

DDD

AG35 RxDATA[B][9]

D

AD32 TxDATA[B][4] AH2 GPIO[2]
AD33 TxDATA[B][5] AH3 GPIO[1]
AD34 TxDATA[B][6] AH4 GPIO[0]
AD35 TxDATA[B][7] AH5 TxTOHF

AE31 V

DDD
DDD

AH35 GND

AJ1 GND

D
D

AE32 RxDATA[B][15] AJ2 TxTOHCK
AE33 TxDATA[B][0] AJ3 TxTOHD[A]
AE34 TxDATA[B][1] AJ4 TxTOHD[B]
AE35 TxDATA[B][2] AJ5 TxTOHD[C]

RxCLK[A]N

W3 RxD[14]P

/

AB33 TxDATA[B][14] AF3 RxD[2]N AJ33 RxPRTY[B]

RxCLK[A]P

W4 RxD[15]N/

AB34 TxDATA[B][15] AF4 RxD[2]P AJ34 RxDATA[B][0]

RxD[B]N

W5 RxD[15]P/

AB35 TxPRTY[B] AF5 V

DDD

AJ35 GND

D

RxD[B]P

W31 RxADDR[0] AC1 GND

D

W32 RxADDR[1] AC2 RxD[7]N AF32
W33 RxCLK[A] AC3 RxD[7]P AF33
W34 TxADDR[2] AC4 RxD[8]N AF34
W35 RxSZ[A] AC5 RxD[8]P AF35

Note: NC refers to no connect. Do not connect pins so designated.

AF31

RxDATA[B][10]
RxDATA[B][11]
RxDATA[B][12]
RxDATA[B][13]
RxDATA[B][14]

AK1 V

DDD

AK2 TxTOHD[D]
AK3 RxREF
AK4 RxTOHF[A]
AK5 RxTOHCK[A]

14 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

(continued)

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

AK31 RxSZ[B] AL31 V

DDD

AK32 RxERR[B] AL32 RxADDR[3] AM32 V
AK33 RxPA[B] AL33 RxADDR[2] AM33 GND
AK34 RxENB[B] AL34 RxCLK[B] AM34 GND
AK35 V

AL1 V

DDD
DDD

AL35 V

AM1 GND
AL2 RxTOHD[A] AM2 GND
AL3 RxTOHF[B] AM3 GND
AL4 RxTOHCK[B] AM4 V
AL5 V

DDD

AM5 RxTOHD[B] AN5 RxTOHF[C] AP5 NC

DDD

D
D
D

DDD

AL6 RxTOHCK[C] AM6 RxTOHD[C] AN6 GND

AM31 TxADDR[4] AN31 NC

DDD

AM35 GND

AN1 GND
AN2 GND
AN3 V

DDD

AN4 GND

D
D
D
D
D

D

D

AN32 GND
AN33 V
AN34 GND
AN35 GND

AP1 V
AP2 V
AP3 GND
AP4 GND

AP6 RxTOHF[D]

D

DDD

D

D
DDD
DDD

D

D

AL7 RxTOHCK[D] AM7 NC AN7 RxTOHD[D] AP7 NC
AL8 NC AM8 RxCLK[D] AN8 RxSZ[D] AP8 RxERR[D]

AL9 RxPA[D] AM9 RxENB[D] AN9 RxEOP[D] AP9 RxSOP/C[D]
AL10 RxDATA[D][0] AM10 RxDATA[D][1] AN10 RxDATA[D][2] AP10 RxDATA[D][3]
AL11 V

DDD

AM11 RxDATA[D][5] AN11 RxDATA[D][6] AP11 RxDATA[D][7]
AL12 RxDATA[D][9] AM12 RxDATA[D][10] AN12 RxDATA[D][11] AP12 RxDATA[D][12]
AL13 RxDATA[D][14] AM13 RxDATA[D][15] AN13 TxDATA[D][0] AP13 TxDATA[D][1]
AL14 TxDATA[D][3] AM14 TxDATA[D][2] AN14 TxDATA[D][4] AP14 TxDATA[D][5]
AL15 TxDATA[D][8] AM15 TxDAT A[D][7] AN15 TxDATA[D][9] AP15 TxDATA[D][10]
AL16 V

DDD

AM16 TxDATA[D][12] AN16 TxDATA[D][13] AP16 TxDATA[D][14]
AL17 TxSOP/C[D] AM17 TxPRTY[D ] AN17 TxEOP[D] AP17 TxDATA[D][15]
AL18 V

DDD

AM18 TxERR[D] AN18 TxSZ[D] AP18 TxPA[D]
AL19 NC AM19 NC AN19 NC AP19 TxCLK[D]
AL20 V

DDD

AM20 RxSZ[C] AN20 RxCLK[C] AP20 RxADDR[4]
AL21 RxSOP/C[C] AM21 RxEOP[C] AN21 RxENB[C] AP21 RxPA[C]
AL22 RxDATA[C][3] AM22 RxDATA[C][2] AN22 RxDATA[C][1] AP22 RxDATA[C][0]
AL23 RxDATA[C][7] AM23 RxDATA[C][6] AN23 RxDATA[C][5] AP23 RxDATA[C][4]
AL24 RxDATA[C][12] AM24 RxDATA[C][11] AN24 RxDATA[C][10] AP24 RxDATA[C][9]
AL25 V

DDD

AM25 TxDATA[C][0] AN25 RxDATA[C][15] AP25 RxDATA[C][14]
AL26 TxDATA[C][5] AM26 TxDATA[C][4] AN26 TxDATA[C][3] AP26 TxDATA[C][2]
AL27 TxDATA[C][10] AM27 TxDATA[C][9] AN27 TxDATA[C][8] AP27 TxDATA[C][7]
AL28 TxDATA[C][14] AM28 TxDATA[C][13] AN28 TxDATA[C][12] AP28 TxDATA[C][11]
AL29 TxEOP[C] AM29 TxSOP/C[C] AN29 TxPRTY[C ] AP29 TxDATA[C][15]
AL30 TxSZ[C] AM30 TxERR[C] AN30 TxPA[C] AP30 TxENB[C]

Note: NC refers to no connect. Do not connect pins so designated.

Agere Systems Inc. 15

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

(continued)

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

AP31 TxCLK[C] AR6 V
AP32 GND
AP33 GND
AP34 V
AP35 V

AR1 V
AR2 V
AR3 GND
AR4 GND
AR5 V

Note: NC refers to no connect. Do not connect pins so designated.

D

D
DDD
DDD
DDD
DDD

D

D
DDD

AR7 GND
AR8 GND

AR9 RxPRTY[D] AR19 V
AR10 RxDATA[D][4] AR20 GND
AR11 RxDATA[D][8] AR21 RxERR[C] AR31 V
AR12 RxDATA[D][13] AR22 RxPRTY[C] AR32 GND
AR13 GND
AR14 TxDATA[D][6] AR24 RxDATA[C][8] AR34 V
AR15 TxDATA[D][11] AR25 RxDATA[C][13] AR35 V

DDD

D
D

D

AR16 GND
AR17 TxENB[D] AR27 TxDATA[C][6]
AR18 V

AR23 GND

DDD
DDD

D

D

D

AR26 TxDATA[C][1]

AR28 GND
AR29 GND
AR30 V

AR33 GND

D

D
DDD
DDD

D

D
DDD
DDD

16 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

(continued)

Table 2. Pin Assignments for 600-Pin LBGA by Signal Name

Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Pin

ADDR[0] E13 DS
ADDR[1] D13 DT

C9 GND

E8 GND
ADDR[2] C13 ECLREFHI AG4 GND
ADDR[3] B13 ECLREFLO AG3 GND
ADDR[4] E14 GND
ADDR[5] D14 GND
ADDR[6] C14 GND
ADDR[7] B14 GND
ADDR[8] A14 GND
ADDR[9] E15 GND
ADDR[10] C15 GND
ADDR[11] B15 GND
ADDR[12] A15 GND
ADDR[13] D16 GND
ADDR[14] C16 GND
ADDR[15] B16 GND
ADS

E9 GND
CLKDIV H4 GND
CS

B8 GND
DA TA[0] B9 GND
DA TA[1] A9 GND
DA TA[2] E10 GND
DA TA[3] D10 GND
DA TA[4] C10 GND
DA TA[5] B10 GND
DA TA[6] A10 GND
DA TA[7] D11 GND
DA TA[8] C11 GND
DA TA[9] B11 GND
DATA[10] A11 GND
DATA[11] E12 GND
DATA[12] D12 GND
DATA[13] C12 GND
DATA[14] B12 GND
DATA[15] A12 GND

Note: NC refers to no connect. Do not connect pins so designated.

A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

C6 GND
A3 GND
A4 GND
A7 GND

A8 GND
A13 GND
A16 GND
A20 GND
A23 GND
A27 GND
A28 GND
A29 GND
A32 GND
A33 GND

B3 GND

B4 GND
B32 GND
B33 GND

C1 GND

C2 GND

C4 GND
C32 GND
C34 GND
C35 GND

D1 GND

D2 GND

D3 GND
D33 GND
D34 GND
D35 GND

F3 GND

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

G1 GND

G35 GND

H1 GND
H3 GND
H5 GND

H35 GND

N1 GND

N35 GND

T1 GND

T35 GND

V3 GND

V31 GND

Y1 GND

Y4 GND
Y35 GND
AA5 GND
AC1 GNDD PLL E4

AC35 GPIO[0] AH4

AH1 GPIO[1] AH3

AH35 GPIO[2] AH2

AJ1 GPIO[3] AG5

AJ35 ICT E7

AM1 INT B7
AM2 MPCLK C8

AM3 MPMODE D8
AM33 NC A19
AM34 NC A21
AM35 NC A22

AN1 NC A24

AN2 NC A25

AN4 NC A26

AN6 NC B5
AN32 NC B17
AN34 NC B18
AN35 NC B19

D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D

AP3
AP32
AP33

AP4

AR3

AR4

AR7

AR8
AR13
AR16
AR20
AR23
AR28
AR29
AR32
AR33

Agere Systems Inc. 17

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

(continued)

Table 2. Pin Assignments for 600-Pin LBGA by Signal Name (continued)

Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Pin

NC B20 NC D21 NC V34 RxD[6]N AD3
NC B21 NC D22 NC AL8 RxD[6]P AD4
NC B22 NC D23 NC AL19 RxD[7]N AC2
NC B23 NC D24 NC AM7 RxD[7]P AC3
NC B24 NC D25 NC AM19 RxD[8]N AC4
NC B25 NC D26 NC AN19 RxD[8]P AC5
NC B26 NC D28 NC AN31
NC B27 NC D29 NC AP5
NC B28 NC D30 NC AP7
NC B29 NC D31 PMRST D7
NC B30 NC E2 R/W
NC B31 NC E6 RST

D9

C7
NC C5 NC E17 RxADDR[0] W31
NC C17 NC E18 RxADDR[1] W32
NC C18 NC E19 RxADDR[2] AL33
NC C19 NC E21 RxADDR[3] AL32
NC C20 NC E22 RxADDR[4] AP20
NC C21 NC E23
NC C22 NC E24

RxCKN/RxD
RxCKP/RxD

[A]
[A]

N

V4

P

V5 RxD[15]N/RxD[B]N W4

RxD[9]N/RxCLK[D]N
RxD[9]P/RxCLK[D]P
RxD[10]N/RxD[D]N
RxD[10]P/RxD[D]P
RxD[11]N/RxCLK[C]N
RxD[11]P/RxCLK[C]P
RxD[12]N/RxD[C]N
RxD[12]P/RxD[C]P

RxD[13]N/RxCLK[B]N
RxD[13]P/RxCLK[B]P

RxD[14]N/RxCLK[A]N
RxD[14]P/RxCLK[A]P

AB1
AB2
AB3
AB4
AA1
AA2
AA3
AA4

W2
W3

NC C23 NC E26 RxCLK[A] W33 RxD[15]P/RxD[B]P W5
NC C24 NC E27 RxCLK[B] AL34 RxDATA[A][0] T33
NC C25 NC E28 RxCLK[C] AN20 RxDATA[A][1] T32
NC C26 NC E29 RxCLK[D] AM8 RxDATA[A][2] R35
NC C27 NC E30 RxD[0]N AG1 RxDATA[A][3] R34
NC C28 NC E32 RxD[0]P AG2 RxDATA[A][4] R33
NC C29 NC E33 RxD[1]N AF1 RxDATA[A][5] R32
NC C30 NC E34 RxD[1]P AF2 RxDATA[A][6] R31
NC C31 NC F5 RxD[2]N AF3 RxDATA[A][7] P35
NC D5 NC F31 RxD[2]P AF4 RxDATA[A][8] P34
NC D6 NC F32 RxD[3]N AE1 RxDATA[A][9] P33
NC D15 NC F33 RxD[3]P AE2 RxDATA[A][10] P32
NC D17 NC F34 RxD[4]N AE3 RxDATA[A][11] P31
NC D18 NC G4 RxD[4]P AE4 RxDATA[A][12] N34
NC D19 NC G31 RxD[5]N AD1 RxDATA[A][13] N33
NC D20 NC U33 RxD[5]P AD2 RxDATA[A][14] N32

Note: NC refers to no connect. Do not connect pins so designated.

Y2
Y3

18 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

Table 2. Pin Assignments for 600-Pin LBGA by Signal Name (continued)

Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Pin

RxDATA[A][15] N31 RxDATA[D][2] AN10 RxSOP/C[A] U31 TxCLK[B] Y33
RxDATA[B][0] AJ34 RxDATA[D][3] AP10 RxSOP/C[B] AJ32 TxCLK[C] AP31
RxDATA[B][1] AH31 RxDATA[D][4] AR10 RxSOP/C[C] AL21 TxCLK[D] AP19
RxDATA[B][2] AH32 RxDATA[D][5] AM11 RxSOP/C[D] AP9 TxD[0]N/TxD[D]N U2
RxDATA[B][3] AH33 RxDATA[D][6] AN11 RxSZ[A] W35 TxD[0]P/TxD[D]P T2
RxDATA[B][4] AH34 RxDATA[D][7] AP11 RxSZ[B] AK31 TxD[1]N/TxD[C]N T3
RxDATA[B][5] AG31 RxDATA[D][8] AR11 RxSZ[C] AM20 TxD[1]P/TxD[C]P T4
RxDATA[B][6] AG32 RxDATA[D][9] AL12 RxSZ[D] AN8 TxD[2]N/TxD[B]N R2
RxDATA[B][7] AG33 RxDATA[D][10] AM12 RxTOHCK[A] AK5 TxD[2]P/TxD[B]P R3
RxDATA[B][8] AG34 RxDATA[D][11] AN12 RxTOHCK[B] AL4 TxD[3]N/TxD[A]N R5
RxDATA[B][9] AG35 RxDATA[D][12] AP12 RxTOHCK[C] AL6 TxD[3]P/TxD[A]P R4

RxDATA[B][10]
RxDATA[B][11]
RxDATA[B][12]
RxDATA[B][13]
RxDATA[B][14]

RxDATA[B][15] AE32 RxENB[C] AN21 RxTOHF[A] AK4 TxD[6]P N3
RxDATA[C][0] AP22 RxENB[D] AM9 RxTOHF[B] AL3 TxD[7]N N4
RxDATA[C][1] AN22 RxEOP[A] U32 RxTOHF[C] AN5 TxD[7]P N5
RxDATA[C][2] AM22 RxEOP[B] AJ31 RxTOHF[D] AP6 TxD[8]N M1
RxDATA[C][3] AL22 RxEOP[C] AM21 TCK F2 TxD[8]P M2
RxDATA[C][4] AP23 RxEOP[D] AN9 TDI G5 TxD[9]N M3
RxDATA[C][5] AN23 RxERR[A] V32 TDO G2 TxD[9]P M4
RxDATA[C][6] AM23 RxERR[B] AK32 TMS F4 TxD[10]N L1
RxDATA[C][7] AL23 RxERR[C] AR21 TRST
RxDATA[C][8] AR24 RxERR[D] AP8 TxADDR[0] G32 TxD[11]N L3
RxDATA[C][9] AP24 RxPA[A] V33 TxADDR[1] G33 TxD[11]P L4
RxDATA[C][10] AN24 RxPA[B] AK33 TxADDR[2] W34 TxD[12]N K1
RxDATA[C][11] AM24 RxPA[C] AP21 TxADDR[3] Y34 TxD[12]P K2
RxDATA[C][12] AL24 RxPA[D] AL9 TxADDR[4] AM31 TxD[13]N K3
RxDATA[C][13] AR25 RxPRTY[A] T34 TxCKN U5 TxD[13]P K4
RxDATA[C][14] AP25 RxPRTY[B] AJ33 TxCKP U4 TxD[14]N J1
RxDATA[C][15] AN25 RxPRTY[C] AR22 TxCKQN J5 TxD[14]P J2
RxDATA[D][0] AL10 RxPRTY[D] AR9 TxCKQP H2 TxD[15]N J3
RxDATA[D][1] AM10 RxREF AK3 TxCLK[A] G34 TxD[15]P J4

Note: NC refers to no connect. Do not connect pins so designated.

(continued)

AF31 RxDATA[D][13] AR12 RxTOHCK[D] AL7 TxD[4]N P1
AF32 RxDATA[D][14] AL13 RxTOHD[A] AL2 TxD[4]P P2
AF33 RxDATA[D][15] AM13 RxTOHD[B] AM5 TxD[5]N P3
AF34 RxENB[A] U34 RxTOHD[C] AM6 TxD[5]P P5
AF35 RxENB[B] AK34 RxTOHD[D] AN7 TxD[6]N N2

G3 TxD[10]P L2

Agere Systems Inc. 19

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

(continued)

Table 2. Pin Assignments for 600-Pin LBGA by Signal Name (continued)

Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Pin

TxDATA[A][0] M35 TxDATA[C][3] AN26 TxEOP[C] AL29 V
TxDATA[A][1] M34 TxDATA[C][4] AM26 TxEOP[D] AN17 V
TxDATA[A][2] M33 TxDATA[C][5] AL26 TxERR[A] H32 V
TxDATA[A][3] M32 TxDATA[C][6] AR27 TxERR[B] AA35 V
TxDATA[A][4] M31 TxDATA[C][7] AP27 TxERR[C] AM30 V
TxDATA[A][5] L35 TxDATA[C][8] AN27 TxERR[D] AM18 V
TxDATA[A][6] L34 TxDATA[C][9] AM27 TxFSYNCN U1 V
TxDATA[A][7] L33 TxDATA[C][10] AL27 TxFSYNCP U3 V
TxDATA[A][8] L32 TxDATA[C][11] AP28 TxPA[A] H33 V
TxDATA[A][9] K35 TxDATA[C][12] AN28 TxPA[B] AA34 V
TxDATA[A][10] K34 TxDATA[C][13] AM28 TxPA[C] AN30 V
TxDATA[A][11] K33 TxDATA[C][14] AL28 TxPA[D] AP18 V
TxDATA[A][12] K32 TxDATA[C][15] AP29 TxPRTY[A] J33 V
TxDATA[A][13] K31 TxDATA[D][0] AN13 TxPRTY[B] AB35 V
TxDATA[A][14] J35 TxDATA[D][1] AP13 TxPRTY[C] AN29 V
TxDATA[A][15] J34 TxDATA[D][2] AM14 TxPRTY[D] AM17 V
TxDATA[B][0] AE33 TxDATA[D][3] AL14 TxSOP/C[A] J32 V
TxDATA[B][1] AE34 TxDATA[D][4] AN14 TxSOP/C[B] AA32 V
TxDATA[B][2] AE35 TxDATA[D][5] AP14 TxSOP/C[C] AM29 V
TxDATA[B][3] AD31 TxDATA[D][6] AR14 TxSOP/C[D] AL17 V
TxDATA[B][4] AD32 TxDATA[D][7] AM15 TxSZ[A] H31 V
TxDATA[B][5] AD33 TxDATA[D][8] AL15 TxSZ[B] Y32 V
TxDATA[B][6] AD34 TxDATA[D][9] AN15 TxSZ[C] AL30 V
TxDATA[B][7] AD35 TxDATA[D][10] AP15 TxSZ[D] AN18 V
TxDATA[B][8] AC31 TxDATA[D][11] AR15 TxTOHCK AJ2 V
TxDATA[B][9] AC32 TxDATA[D][12] AM16 TxTOHD[A] AJ3 V
TxDATA[B][10] AC33 TxDATA[D][13] AN16 TxTOHD[B] AJ4 V
TxDATA[B][11] AC34 TxDATA[D][14] AP16 TxTOHD[C] AJ5 V
TxDATA[B][12] AB32 TxDATA[D][15] AP17 TxTOHD[D] AK2 V
TxDATA[B][13] AB31 TxENB[A] H34 TxTOHF AH5 V
TxDATA[B][14] AB33 TxENB[B] AA33 V
TxDATA[B][15] AB34 TxENB[C] AP30 V
TxDATA[C][0] AM25 TxENB[D] AR17 V
TxDATA[C][1] AR26 TxEOP[A] J31 V
TxDATA[C][2] AP26 TxEOP[B] AA31 V

Note: NC refers to no connect. Do not connect pins so designated.

DDA
DDD
DDD
DDD
DDD

B6 V
A1 V
A2 V
A5 V
A6 V

DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD

A17
A18
A30
A31
A34
A35

B1

B2
B34
B35

C3
C33

D4
D27
D32

E1

E5
E11
E16
E20
E25
E31
E35

F1
F35

K5

L5
L31

M5

P4

R1

T5
T31
U35

V1

20 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

(continued)

Table 2. Pin Assignments for 600-Pin LBGA by Signal Name (continued)

Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Pin

DDD

V

DDD

V
V

DDD

V

DDD
DDD

V
V

DDD

V

DDD
DDD

V
V

DDD

V

DDD

Note: NC refers to no connect. Do not connect pins so designated.

V2 V

V35 V

W1 V

Y5 V
Y31 V
AB5 V
AD5 V
AE5 V

AE31 V

AF5 V

DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD

AK1 V

AK35 V

AL1 V

AL5 V
AL11 V
AL16 V
AL18 V
AL20 V
AL25 V
AL31 V

DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD

AL35 V

AM4 V

AM32 V

AN3 V

AN33 V

AP1 V

AP2 V
AP34 V
AP35 V

AR1 V

DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD

PLL E3

AR2
AR5

AR6
AR18
AR19
AR30
AR31
AR34
AR35

Agere Systems Inc. 21

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

Note:3.3 V CMOS logic inputs are 5 V tolerant. Logic inputs can be driven from standard TTL levels, and logic out-

puts can drive standard TTL in puts . All LVPECL buffers are differential. LVPECL is compliant with low-volt­age (3.3 V) pseudo-emitter-coupled logic interface levels. All PECL outputs, including ECLREFHI and
ECLREFLO require terminating resistors. The required termination for the PECL buffers is 50 Ω to a termi­nating voltage of V

D

). Other termination styles are not recommended. LVPECL inputs with a / in the name indicate multiple

GND
functionality. The name preceding the / is the function in STS-48/STM-16 mode. The name after the / is the
function in STS-3/STM-1 or S TS- 12/ STM- 4 mod e.

Table 3. Pin Descriptions—Line Interface Signals

Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally
disabled whenever core registers 0x0010 and 0x0011 are properly provisioned. The unused inputs can be consid­ered to be NC (no connect).

Pin Symbol Type I/O Name/Description

V5 RxCKP/

RxD[A]P

V4 RxCKN/

RxD[A]N

AG2 RxD[0]P LVPECL I Receive Line Data Inputs (STS-48/STM-16). In STS-48/STM-16 mode,
AG1 RxD[0]N

AF2 RxD[1]P LVPECL
AF1 RxD[1]N
AF4 RxD[2]P LVPECL
AF3 RxD[2]N
AE2 RxD[3]P LVPECL
AE1 RxD[3]N
AE4 RxD[4]P LVPECL

AE3 RxD[4]N
AD2 RxD[5]P LVPECL
AD1 RxD[5]N
AD4 RxD[6]P LVPECL
AD3 RxD[6]N
AC3 RxD[7]P LVPECL
AC2 RxD[7]N
AC5 RxD[8]P LVPECL
AC4 RxD[8]N

AB2 RxD[9]P/

RxCLK[D]P

AB1 RxD[9]N/

RxCLK[D]N

(continued)

DDD

– 2 V. The Theven in equivalent is also ac ce ptab le (1 30 Ω to V

LVPECL I Receive Line Clock (S TS-48/STM-16)/Receive Line Data Input Channel

A. In STS-48/STM-16 mode, these pins function as receive line clock. This

155.52 MHz clock comes from an external clock data recovery circuit. This
clock is used to clock in the RxD[15:0] receive line data inputs.

In STS-3/STM-1 or STS-12/ST M-4 mode, these pins function as rece iv e
data input channel A at 155.52 Mbi ts /s or 622.08 Mbits/s, respectively.

This buffer is internally disabled when not in STS-48/STM-16 mode and
channel A is disabled. This buffer is internally disa bled throug h proper pr o­visioning when the input is not active.

these pins function as receive line data inputs [0:8]. The remaining receive
line data inputs [9:15] are listed below and are multiplexed for use in the
STS-3/STM-1 or STS-12/STM-4 modes.

The 2.488 Gbits/s STS-48/STM-16 serial data stream is converted to a

155.52 Mbits/s parallel 16-bit word externa l to TDAT042G5 by a demulti­plexer.

All 32 differential data input pins, RxD[ 15:0]P/N, are used as the parallel
data input bus in the STS-48/STM-16 mode. These pins constitute a

155.52 Mbits/s parallel 16-bit word-align ed to the RxCKP/N 155.52 MH z
receive line clock. RxD[15] is the most significant bit and is the first bit
received. RxD[0] is the least significant bit and is the last bit received.

This buffer is internally disabled through proper provisioning when the input
is not active.

LVPECL I Receive Line Data Input [9]/Receive Line Clock Channel D. In STS-48/

STM-16 mode, these pins function as receive line data input [9] at

155.52 Mbits/s.
In STS-3/STM-1 or STS-12/ST M-4 mode, these pins function as rece iv e

line clock channel D at either 155.52 MHz (STS-3/STM-1) or 622.08 MHz
(STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16 mode and
channel D is disabled. This buffer is intern all y disabled thro ugh pr ope r pro­visioning when the input is not active.

DDD

and 82 Ω to

22 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

Table 3. Pin Descriptions—Line Interface Signals (continued)

Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally
disabled whenever co re r egi ste r s 0x0010 and 0x0011 are properly provisi oned. The unused inputs can be consid­ered to be NC (no connect).

Pin Symbol Type I/O Name/Description

AB4 RxD[10]P/

RxD[D]P

AB3 RxD[10]N/

RxD[D]N

AA2 RxD[11]P/

RxCLK[C]P

AA1 RxD[11]N/

RxCLK[C]N

AA4 RxD[12]P/

RxD[C]P

AA3 RxD[12]N/

RxD[C]N

Y3 RxD[13]P/

RxCLK[B]P

Y2 RxD[13]N/

RxCLK[B]N

W3 RxD[14]P/

RxCLK[A]P

W2 RxD[14]N/

RxCLK[A]N

(continued)

LVPECL I Receive Line Data Input [10]/Receive Line Data Input

Channel D. In STS-48/STM-16 mode, the se pin s functi on as
receive line data input [10] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 m ode, the se pins func ti on as
receive line data input channel D at either 155.52 Mbits/s (STS-3/
STM-1) or 622.08 Mbi ts/s (STS-12/STM-4).

This bu ffer is internally disabled when not in STS-48/STM-16
mode and channel D is disabled. This buffer is internally disabled
through proper provisioning when the input is not active.

LVPECL I Receive Line Data Input [11]/Receive Line Clock Channel C.

In STS-48/STM-16 mode, these pins function as receive line data
input [11] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 m ode, the se pins func ti on as
receive line clock channel C at either 155.52 MHz (STS-3/STM-1)
or 622.08 MHz (STS-12/STM-4).

This bu ffer is internally disabled when not in STS-48/STM-16
mode and channel C is disabled. This buffer is internally disabled
through proper provisioning when the input is not active.

LVPECL I Receive Line Data Input [12]/Receive Line Data Input

Channel C. In STS-48/STM-16 mode, the se pin s functi on as
receive line data input [12] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 m ode, the se pins func ti on as
receive line data input channel C at either 155.52 Mbits/s (STS-3/
STM-1) or 622.08 Mbi ts/s (STS-12/STM-4).

This bu ffer is internally disabled when not in STS-48/STM-16
mode and channel C is disabled. This buffer is internally disabled
through proper provisioning when the input is not active.

LVPECL I Receive Line Data Input [13]/Receive Line Clock Channel B.

In STS-48/STM-16 mode, these pins function as receive line data
input [13] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 m ode, the se pins func ti on as
receive line clock channel B at either 155.52 MHz (STS-3/STM-1)
or 622.08 MHz (STS-12/STM-4).

This bu ffer is internally disabled when not in STS-48/STM-16
mode and channel B is disabled. This buffer is internally disabled
through proper provisioning when the input is not active.

LVPECL I Receive Line Data Input [14]/Receive Line Clock Channel A.

In STS-48/STM-16 mode, these pins function as receive line data
input [14] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 m ode, the se pins func ti on as
receive line clock channel A at either 155.52 MHz (STS-3/STM-1)
or 622.08 MHz (STS-12/STM-4).

This bu ffer is internally disabled when not in STS-48/STM-16
mode and channel A is disabled. This buffer is internally disabled
through proper provisioning when the input is not active.

Agere Systems Inc. 23

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

(continued)

Table 3. Pin Descriptions—Line Interface Signals (continued)
Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally

disabled whenever core registers 0x0010 and 0x0011 are properly provisioned. The unused inputs can be consid­ered to be NC (no connect).

Pin Symbol Type I/O* Name/Description

W5 RxD[15]P/

RxD[B]P

W4 RxD[15]N/

RxD[B]N

LVPECL I Receive Line Data Input [15]/Receive Line Data Input

Channel B. In STS-48/STM-16 mode, these pins function as
receive line data input [15] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as
receive line data in put channe l B at either 155.52 Mbits/s
(STS-3/STM-1) or 622.08 Mbits/s (STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16
mode and channel B is disabled. This buffer is internal ly disabled
through proper provisioning when the input is not active.

u

H4 CLKDIV 3.3 V

(5 V tolerant)

Clock Division. This pin controls a divider in the line transmit

I

block to create a 77.76 MHz clock from either the 155.52 MHz
STS-3/STM-1 or STS-48/STM-16 tra n smit line clock, or the

622.08 MHz STS-12/STM-4 transmit line clock, TxCKP/N.
CLKDIV = 1 for STS-12/STM-4 (divide by 8).

CLKDIV = 0 for STS-3/STM-1 and STS-48 /STM-16 (divide by 2).
AG3 ECLREFLO — O Reference Voltage for LVPECL I/O Buffers. ECLREFLO and
AG4 ECLREFHI — O

ECLREFHI are buffer outputs which provide the reference for the

output level of the LVPECL output buffers. ECLREFLO and ECL-

REFHI must be connected to a 50 Ω source of V

DDD

– 2 V.† No

user-accessible signal is present on these pin s.

*Iu = Id = 50 kΩ, where Iu = internal pull-up resistance and Id = internal pull-down resistance.
†This may be obtained from a passive voltage divider of a 130 Ω resistor connected from V

which is connected to GND

D.

to one end of an 82 Ω resistor, the other end of

DDD

Note: The TDAT042G5 has internal ci rcu itry that is ass oc iat ed with the buffer section of the chip. This section

monitors the voltage levels of REFLO and REFHI. A very low frequency calibration process, during which
the values at the ECLREFLO and ECLREFH I pins ar e con tinuous l y monitored, is performed to allow the
drive capactity of remaining buffers to be adjusted within true PECL levels. Therefore, it is important to ter­minate the ECLREFLO and ECLREFHI outputs in exactly the same way as you would terminate LVPECL
outputs.

24 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

Table 3. Pin Descriptions—Line Interface Signals (continued)

Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally
disabled whenever co re r egi ste r s 0x0010 and 0x0011 are properly provisi oned. The unused inputs can be consid­ered to be NC (no connect).

Pin Symbol Type I/O* Name/Description

U4 TxCKP LVPECL I Transmit Line Clock. When in STS-48/STM-16 mode, this clock
U5 TxCKN

U3 TxFSYNCP LVPECL I
U1 TxFSYNCN I

T2 TxD[0]P/

TxD[D]P

U2 TxD[0]N/

TxD[D]N

T4 TxD[1]P/

TxD[C]P

T3 TxD[1]N/

TxD[C]N

R3 TxD[2]P/

TxD[B]P

R2 TxD[2]N/

TxD[B]N

R4 TxD[3]P/

TxD[A]P

R5 TxD[3]N/

TxD[A]N

(continued)

is a 155.52 MHz input and clocks out TxD[15:0]P/N or TxD[D:A].
When in STS-12/STM-4 mode, this clock is a 622.08 MHz input

and clocks out TxD[D:A]P/N.
When in STS-3/STM-1 mode, this clock is a 155.52 MHz input

and clocks out TxD[D:A]P/N.

d

Transmit Line Frame Sync. This input is the exter n a l 8 kHz
transmit line frame sync. Driving this input is optional. If undriven

u

from an external source, these pins must be no connects. When
this input is used, it must be (1) synchronized to TxCKP/N, and (2)
at least one TxCKP/N cycle wide, up to a maximum of 1 frame
period minus 2 TxCKP/N cycles wide.

LVPECL O Transmit Line Data Output [0]/Transmit Line Data Output

Channel D. In STS-48/STM-16 mode, the pins function as trans­mit line data output [0] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, the pin s functi on as
transmit data output channel D at either 155.52 Mbits/s or

622.08 Mbits/s.
This buffer is internally disabled through proper provisioning when

the input is not active.

LVPECL O Transmit Line Data Output [1]/Transmit Line Data Output

Channel C. In STS-48/STM-16 mode, the pins function as trans­mit line data output [1] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, the pin s functi on as
transmit data output channel C at either 155.52 Mbits/s or

622.08 Mbits/s.
This buffer is internally disabled through proper provisioning when

the input is not active.

LVPECL O Transmit Line Data Output [2]/Transmit Line Data Output

Channel B. In STS-48/STM-16 mode, the pins function as trans­mit line data output [2] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, the pin s functi on as
transmit data output channel B at either 155.52 Mbits/s or

622.08 Mbits/s.
This buffer is internally disabled through proper provisioning when

the input is not active.

LVPECL O Transmit Line Data Output [3]/Transmit Line Data Output

Channel A. In STS-48/STM-16 mode, the pins function as trans­mit line data output [3] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, the pin s functi on as
transmit data output channel A at either 155.52 Mbits/s or

622.08 Mbits/s.
This buffer is internally disabled through proper provisioning when

the input is not active.

* Iu = Id = 50 kΩ, where Iu = internal pull-up resistance and Id = internal pull-down resistance.

Agere Systems Inc. 25

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

Table 3. Pin Descriptions—Line Interface Signals (continued)

Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally
disabled whenever core registers 0x0010 and 0x0011 are properly provisioned. The unused inputs can be consid­ered to be NC (no connect).

Pin Symbol Type I/O Name/Description

H2 TxCKQP LVPECL O Tr ansmit Line Clock Q. This 155.52 MHz cl ock is used t o clock

J5 TxCKQN

P2 TxD[4]P LVPECL O Transmit Line Data Outputs (STS-48/STM-16). In STS-48/
P1 TxD[4]N
P5 TxD[5]P LVPECL
P3 TxD[5]N
N3 TxD[6]P LVPECL
N2 TxD[6]N
N5 TxD[7]P LVPECL

N4 TxD[7]N
M2 TxD[8]P LVPECL
M1 TxD[8]N
M4 TxD[9]P LVPECL
M3 TxD[9]N

L2 TxD[10]P LVPECL

L1 TxD[10]N

L4 TxD[11]P LVPECL

L3 TxD[11]N

K2 TxD[12]P LVPECL

K1 TxD[12]N

K4 TxD[13]P LVPECL

K3 TxD[13]N

J2 TxD[14]P LVPECL
J1 TxD[14]N
J4 TxD[15]P LVPECL
J3 TxD[15]N

(continued)

out the data in the STS-48/STM-16 mode for forward-directional
timing with the 155 Mbits/s 16- bi t parall el -to -2.5 Gb its /s serial
MUX.

For an STS-48/STM-16 contra-clocking interface with the
155 Mbits/s parall el -to-2.5 Gbits/s serial MUX, this clock is not
used. In the contra-clocking mode, a phase-locked version of
TxCKP/N is used to clock out the data. In the contra-clocking
mode, the transmit line clock PLL must be active (see core regis­ter map 0x0010, bit 5 (PLL_ MODE) on pag e 112).

This clock is not used in the STS-3/STM -1 or STS-12/STM- 4
modes.

STM-16 mode, these pins function as transmit line data out puts
[4:15]. The remaining transmit li ne data outp uts [0 :3] are li st ed
below and are multiplexed for use in the STS-3/STM-1 or STS-12/
STM-4 modes.

The 155.52 Mbits/s 16- bi t word paral le l bus is conve rted to a

2.488 Gbits/s serial data stream external to TDAT042G5 by a mul­tiplexer.

All 32 differential data output pins, TxD[15:0]P/N, are used as the
parallel data output bus in the STS-48/STM-16 mode. These pins
constitute a 155.52 Mbyte/s parallel 16-bit word-aligned to the
TxCKP/N and TxCKQP/N 155.52 MHz transmit line clock.
TxD[15] is the most significant bit and is the first bit transmitted.
TxD[0] is the least significant bit and is the last bit transmitted.

This buffer is internally disabled through proper provisioning when
the input is not active.

26 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

Table 4. Pin Descriptio ns—TOH Interface Signals

Pin Symbol Type I/O* Name/Description

AK3 RxREF 3.3 V O Receive Line Frame. This output provides the receive 8 kHz

AL7
AL6
AL4

AK5

AN7
AM6
AM5

AL2

AP6

AN5

AL3

AK4

AJ2 TxTOHCK 3.3 V O Transmit TOH Interface Clock. This clock is nominally a

AK2

AJ5
AJ4
AJ3

AH5 TxTOHF 3.3 V O Transmit TOH Interface Frame. This 8 kHz fram ing signal is

RxTOHCK[D]
RxTOHCK[C]
RxTOHCK[B]
RxTOHCK[A]

RxTOHD[D]
RxTOHD[C]
RxTOHD[B]
RxTOHD[A]

RxTOHF[D]
RxTOHF[C]
RxTOHF[B]
RxTOHF[A]

TxTOHD[D]
TxTOHD[C]
TxTOHD[B]
TxTOHD[A]

(continued)

frame reference for external timing needs. RxREF is derived from
one of the received line clocks (user-selectable). It is a 50% duty
cycle clock when TDAT042G5 is in frame. This signal may be
used to implement line tim ing on a SON ET r i ng. When not provi­sioned, this signal must not be used. RxREF is valid only when
the SONET framer is in frame. Upon LOC or LOF, RxREF is
present but is free running. Because jitter may be present on this
signal when th e d evice goes into and o ut of an LOC or LOF stat e,
it should not be used as a reference for TxFSYNCP/N.

3.3 V O Receive TOH Interface Clock. This clock is nominally a

5.184 MHz (STS-3/S TM - 1) or 20.736 MHz (STS-12/ST M- 4,
STS-48/STM-16) clock which provides timing for circuitry that
receives and externally processes the receive transport overhead
bytes. The duty cycle of the clock is not 50% (see Figure 49 and
Figure 50, page 272). In STS-48/STM-16 mode, all four of these
clocks are active.

3.3 V O Receive TOH Interface Data. This 5.184 Mbits/s or

20.736 Mbits/s signal contains all the receive transport overhead
bytes (A1, A2, J0/Z0, B1, E1, F1, D1—D3, H1—H3, K1, K2,
D4—D12, S1/Z1, M0, and E2) for all 3/12/48 STS-1s. This signal
can be used by external circuitry to process the TOH bytes.
RxTOHD is updated on the falling edge of RxTOHCK. In STS-48/
STM-16 mode, RxTOHD[A] contains all current ly defined TOH
bits except for M1, which is located in RxTOHD[C].

3.3 V O Receive TOH Interface Frame. This 8 kHz framing signal is used
to locate the individual receive transport overhead bits in the
RxTOHD bit stream. RxTOHF is only high while bit 1 (MSB) of the
first framing byte (A1 during parity time in first byte) is present on
the RxTOHD output. RxTOHF is updated on the falling edge of
RxTOHCK.

5.184 MHz (STS-3/STM -1) , 20.736 MHz (STS-12/STM-4,
STS-48/STM-16) clock which provides timing for circuitry that
externally generates and transmi ts the transmit transpor t over­head bytes for inclusion in the transmit data stream. The duty
cycle of the clock is not 50% (see Figure 48, pag e271).

3.3 V

(5 V tolerant)

u

I

Transmit TOH Interface Data. This 5.184 Mbits/s or

20.736 Mbits/s signal contains all the transmit transport overhead
bytes (A1, A2, J0/Z0, B1, E1, F1, D1—D3, H1—H3, K1, K2,
D4—D12, S1/Z1, M0, and E2) for all 3/12/48 STS-1s. This signal
is generat ed b y external circuitry for c us tom TOH byte definitions.
TxTOHD is sampled on the rising edge of TxTOHCK.

used to align the individual transmit transport overhead bits in the
TxTOHD bit stream. TxTOHF is only high while bit 1 (MSB) of the
first framing byte (A1 during parity time in first byte) is expected
on the TxTOHD input. TxTOHF is updated on the falling edge of
TxTOHCK.

* Iu = Id = 50 kΩ, where Iu = internal pull-up resistance and Id = internal pull-down resistance.

Agere Systems Inc. 27

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

Note:An external pull-up resi sto r of 50 kΩ—100 kΩ is required on all input pins of a disabled UTOPIA port. Either

an external pull-up resistor of 50 kΩ—100 kΩ or an external pull-down resistor of 0 Ω—1 kΩ is required on all
unused inputs of an enabled UTOPIA port. Use of either a pull-up or pull-down resistor is selected to place
the unused input pin into the inactive state.

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals

Pin Symbol Type I/O Name/Description

AM31

Y34

W34

G33
G32

J34

J35
K31
K32
K33
K34
K35

L32

L33

L34

L35

M31
M32
M33
M34
M35

AB34
AB33
AB31
AB32
AC34
AC33
AC32
AC31
AD35
AD34
AD33
AD32
AD31
AE35
AE34
AE33

TxADDR[4]
TxADDR[3]
TxADDR[2]
TxADDR[1]
TxADDR[0]

TxDATA[A][15]
TxDATA[A][14]
TxDATA[A][13]
TxDATA[A][12]
TxDATA[A][11]
TxDATA[A][10]

TxDATA[A][9]
TxDATA[A][8]
TxDATA[A][7]
TxDATA[A][6]
TxDATA[A][5]
TxDATA[A][4]
TxDATA[A][3]
TxDATA[A][2]
TxDATA[A][1]
TxDATA[A][0]

TxDATA[B][15]
TxDATA[B][14]
TxDATA[B][13]
TxDATA[B][12]
TxDATA[B][11]
TxDATA[B][10]

TxDATA[B][9]
TxDATA[B][8]
TxDATA[B][7]
TxDATA[B][6]
TxDATA[B][5]
TxDATA[B][4]
TxDATA[B][3]
TxDATA[B][2]
TxDATA[B][1]
TxDATA[B][0]

(continued)

3.3 V

(5 V tolerant)

3.3 V

(5 V tolerant)

3.3 V

(5 V tolerant)

I Transmit Ad dr e ss . The TxADDR is driven by the UTOPIA mas-

ter to poll and select the approp r ia t e PHY ch anne l of
TDAT042G5 to transmit data.

Note:The PHY address (0x00 to 0x1E) for each of the four

channels in TD AT042G5 is configured vi a software
provisioning.

I Transmit Data Channel A. Used to transport data into the

UTOPIA PHY Tx block. TxDATA[A] is only valid when TxENB[A]
is asserted, and is sampled on the rising edge of TxCLK[A].
Note that TxDATA[A] is used in various UTOPIA modes. In U2 or
U2+, all 16 bits are valid. In U3 or U3+ (8-bit mode), only bits 15
to 8 are valid.

In U3 or U3+ (32-bit mode), TxDATA[A][15:0] forms the most
significant 16 bits of the combined data bus (bits 31 to 16), and
TxDATA[B][15:0] forms the least significant 16 bits of the com­bined data bus (bits 15 to 0).

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

I Transmit Data Channel B. Used to transport data into the

UTOPIA PHY Tx block. TxDATA[B] is only valid when TxENB[B]
is asserted (TxENB[A] for U3 or U3+ (32-bit mode)), and is sam­pled on the rising edge of TxCLK[B] (TxCLK[A] for U3 or U3+
(32-bit mode). Note that TxDATA[B] is used in various UTOPIA
modes. In U2 or U2+, all 16 bits are valid. In U3 or U3+ (8-bit
mode), only bits 15 to 8 are valid.

In U3 or U3+ (32-bit mode), TxDATA[B][15:0] forms the least sig­nificant 16 bits of the combined data bus (bits 15 to 0), and
TxDATA[A][15:0] forms the most significant 16 bits of the com­bined data bus (bits 31 to 16). In this mode, channel B port must
be provisioned to the idle (default) state.

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

28 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

Table 5. Pin Descriptions—Enhanced UTOPIA Interface Signals

Pin Symbol Type I/O Name/Description

AP29

AL28
AM28
AN28

AP28

AL27
AM27
AN27

AP27
AR27

AL26
AM26
AN26

AP26
AR26
AM25

AP17

AP16
AN16
AM16
AR15

AP15
AN15

AL15
AM15
AR14

AP14
AN14

AL14
AM14

AP13
AN13

AM17
AN29

AB35

J33

TxDATA[C][15]
TxDATA[C][14]
TxDATA[C][13]
TxDATA[C][12]
TxDATA[C][11]
TxDATA[C][10]

TxDATA[C][9]
TxDATA[C][8]
TxDATA[C][7]
TxDATA[C][6]
TxDATA[C][5]
TxDATA[C][4]
TxDATA[C][3]
TxDATA[C][2]
TxDATA[C][1]
TxDATA[C][0]

TxDATA[D][15]
TxDATA[D][14]
TxDATA[D][13]
TxDATA[D][12]
TxDATA[D][11]
TxDATA[D][10]

TxDATA[D][9]
TxDATA[D][8]
TxDATA[D][7]
TxDATA[D][6]
TxDATA[D][5]
TxDATA[D][4]
TxDATA[D][3]
TxDATA[D][2]
TxDATA[D][1]
TxDATA[D][0]

TxPRTY[D]
TxPRTY[C]

TxPRTY[B]
TxPRTY[A]

(continued)

3.3 V

(5 V tolerant)

3.3 V

(5 V tolerant)

3.3 V

(5 V tolerant)

(continued)

I Transmit Data Channel C. Used to transport data into the

UTOPIA PHY Tx blo ck. TxDATA[C] is only valid w hen Tx ENB[C ]
is asserted, and is sampled on the rising edge of TxCLK[C].
Note that TxDATA[C] is used in various UTOPIA modes. In U2
or U2+, all 16 bits are valid. In U3 or U3+ (8-bit mode), only bits
15 to 8 are valid.

In U3 or U3+ (32-bit mode), channel C port is considered dis­abled, and must be provisioned to the idle (default) state.

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

I Transmit Data Channel D. Used to transport data into the UTO-

PIA PHY Tx block. TxDATA[D] is only valid w hen TxENB[D] is
asserted, and is sampled on the rising edge of TxCLK[D]
(TxCLK[A] for U3+, 32-bit mode). Note that TxDA TA[D] is used in
various UTOPIA modes. In U2 or U2+, all 16 bits are valid. In U3
or U3+ (8-bit mode), only bits 15 to 8 are valid.

In U3 or U3+ (32-bit mode), channel D port is considered dis­abled, and must be provisioned to the idle (default) state.

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

I Transmit Parity. This signal indicates the parity on the

TxDATA[D:A][15:0] bus. A parity error raises an alarm but does
not cause the cell/packet to be dropped. Odd or even parity may
be provisioned through a software register. TxPRTY[D:A] is con­sidered valid only when TxENB[D:A] is ass erted, and is sam­pled on the rising edge of TxCLK[D:A].

In U3 or U3+ (32-bit mode), the TxPRTY[A] parity pin of port A
indicates the parity for the entire 32-bit data input.

Agere Systems Inc. 29

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

.

Table 5

Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

(continued)

Pin Symbol Type I/O Name/Description

AL17

AM29

AA32

J32

TxSOP/C[D]
TxSOP/C[C]
TxSOP/C[B]
TxSOP/C[A]

3.3 V

(5 V tolerant)

I Transmit Start o f Packet/Cell. In ATM mode, the TxSOP/C[D:A]

signal marks the start of a ce ll on the TxDATA[D:A][15:0] bus.
When TxSOP/C[D:A] is active, the first word of the cell is present
on the TxDATA[D:A][1 5:0 ] bus.

In packet modes, the TxSOP/C[D:A] signal marks the start of a
packet on the TxDATA[D:A][15:0] bus. When TxSOP/C[D:A] is
active, the first word of the packet is present on the
TxDATA[D:A][15:0] bus.

TxSOP/C[D:A] is considered valid only when TxENB[D:A] is
asserted, and is sampled on the rising edge of TxCLK[D:A].

In U3 or U3+ (32-bit mode), only the TxSOP/C[A] pin of port A is
used to indicate a start of packet/cell for the 32-bit data input.

AP18
AN30
AA34

H33

TxPA[D]
TxPA[C]
TxPA[B]
TxPA[A]

3.3 V O Transmit Cell/Packet Available. This signal indicates when the
TDAT042G5 transmit FIFO can accept data from the master
device. If the FIFO is empty or more than the provisioned space is
available in the FIFO, TxPA[D:A] is set active.

One-Cycle Delay Mode. This mode follows the UTOPIA Level

■

2 Standard. The TxP A response occurs one cycle after the
address is polled .

Two-Cycle Delay Mode. This mode follows the UTOPIA Level

■

3 baselined text*. The TxPA response occurs two cycles after
the address is polled.

TxPA[D:A] Assertion. The TxPA[D:A] signal behavior relies on

■

the UTOPIA provisionab le wate rmar ks . In pa ck et mode ,
TxPA[D:A] goes high when the amount of data in the FIFO is
less than the high watermark setting. In ATM mod e, TxPA[D:A]
goes high when the FIFO has space to receive a complete ATM
cell from the master. (This requires the high threshold to be set
appropriately by the user, i.e., set so that an entire cell can be
received once TxPA[D:A] goes ac ti ve. )

* ATM Forum Technical Committee, UTOPIA Level 3, STR-PHY-UL3-01.00, July

1999.

(See further description on nex t page.)

30 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

.

Table 5

Pin Symbol Type I/O Name/Description

AP18

AN30

AA34

H33

AP19
AP31

Y33

G34

AR17

AP30
AA33

H34

Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

TxPA[D]
TxPA[C]
TxPA[B]
TxPA[A]

TxCLK[D]
TxCLK[C]
TxCLK[B]
TxCLK[A]

TxENB[D]
TxENB[C]
TxENB[B]
TxENB[A]

(continued)

3.3 V O Transmit Cell/Packet Available. (continued)
TxPA[D:A] Deassertion. In packet mode, TxPA[D:A] goes low

■

when the amount of data in the FIFO reaches or exceeds the
high watermark. In ATM mode, TxPA[D:A] goes low when there
is not enough space in the FIFO to receive an entire ATM cell.
(This requires th e thre sh old values to be provisioned proper l y,
i.e., set low enough such that when the high watermark is
reached, the transmission of the current cell can be completed
without overflowing the FIFO). In ATM mode, TxPA[D:A] will be
deasser ted four cycles before the end of the current cell trans­fer if the FIFO cannot accept a complete ATM cell on the follow­ing transmission.

TxPA[D:A] is updated on the rising edge of TxCLK[D:A].
In 32-bit mode , only the T xPA[A] pin of port A is used t o in dicat e

the packet/cell available status.
MPHY Support. When the TxP A signals are used for multi-PHY

■

(MPHY) direct status, the corresponding TxCLK[B, C, and/or D]
must be provided. This clock will be the same as TxCLK[A].

3.3 V

(5 V tolerant)

3.3 V

(5 V tolerant)

I Transmit Clock. This clock is used to write cells or packets into

the transmit FIFO. TxCLK[D:A] can operate at speeds from dc to
104 MHz.

In U3 or U3+ (32-bit mode), only the TxCLK[A] input pin of port A
is used to clock the data input.

If MPHY direct status is used, then all clocks TxCLK[D:A] must be
provided.

I Transmit Data Enable (Active-Low). This signal is used to trans-

fer data on the TxDATA[D: A][1 5:0 ] bus into the transmit FIFOs. If
TxENB[D:A] is high, no operation is performed. If TxENB[D:A] is
low, a write occurs.

TxENB[D:A] is sampled on the rising edge of TxCLK[D:A].
TxENB[D:A] has the same meaning as da ta valid.

In U3 or U3+ (32-bit mode), only the TxENB[A] input pin of port A
is used to enable the transfer of data.

Agere Systems Inc. 31

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

.

Table 5

Pin Descriptions—Enhanced UTOPIA Interface Signals

(continued)

(continued)

Pin Symbol Type I/O Name/Description

AN18

AL30

Y32
H31

TxSZ[D]
TxSZ[C]
TxSZ[B]
TxSZ[A]

3.3 V

(5 V tolerant)

I Transmit Size. These pin s are used only in U2+ and U3+

(packet) modes. This signal defines the valid bytes transmitted
and their packing within (1) TxDATA[D:A][15:0] for U2+ 16-bit
mode, and (2) TxDATA[A][15:0] and TxDATA[B][15:0] for the U3+
(32-bit mode). The meaning of these bits may be inverted
through UT register 0x0226 TxSIZE/Rx SIZE mode, page 164.

In U3+ (8-bit mode), TxSZ[D:A] are unused.
For U2+ 16-bit mode,

TxSZ[D:A] = 0 defines the MSByte of TxDATA[D:A][15:0], i.e.,
TxDATA[D:A][15:8], to be the last byte of the packet transmit­ted when using the default configuration.

TxSZ[D:A] = 1 defines the LSByte of TxDATA[D:A][15:0], i.e.
TxDATA[D:A][7:0], to be the last byte of the packet transmit­ted when using the default configuration.

For U3+ (32-bit mode), TxSZ[A] and TxSZ[B] are combined to
define four states of the transmitted dat a stream. TxSZ[C] and
TxSZ[D] are unused. The following states are assigned by
TxSZ[A] and TxSZ[B] when TxEOP[A] is asserted when using
the default configuration. TxSZ[D:A] is ignored when
TxEOP[D:A] is not pres en t.

TxDATA[A] TxDATA[B]

TxDATA[A][15:8] TxDATA[A][7:0] TxDATA[B][15:8] TxDATA[B][7:0]

TxSZ[B]DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0]

TxSZ[A]

0 0 Valid Not valid Not valid Not valid
0 1 Valid Valid Not valid Not valid
1 0 Valid Valid Valid Not valid
1 1 Valid Valid Valid Valid

There is no byte swapping and the data bytes are packed into
the upper transmitted bytes first.

32 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

.

Ta ble 5

AN17

AL29
AA31

AM18
AM30

AA35

H32

AP20
AL32
AL33

W32
W31

N31
N32
N33
N34
P31
P32
P33
P34
P35
R31
R32
R33
R34
R35
T32
T33

Pin Descriptions—Enhanced UTOPIA Interface Sign als (continued)

Pin Symbol Type I/O Name/Description

TxEOP[D]
TxEOP[C]
TxEOP[B]

J31

TxEOP[A]

TxERR[D]
TxERR[C]
TxERR[B]
TxERR[A]

RxADDR[4]
RxADDR[3]
RxADDR[2]
RxADDR[1]
RxADDR[0]

RxDATA[A][15]
RxDATA[A][14]
RxDATA[A][13]
RxDATA[A][12]
RxDATA[A][11]
RxDATA[A][10]

RxDATA[A][9]
RxDATA[A][8]
RxDATA[A][7]
RxDATA[A][6]
RxDATA[A][5]
RxDATA[A][4]
RxDATA[A][3]
RxDATA[A][2]
RxDATA[A][1]
RxDATA[A][0]

(continued)

(5 V tolerant)

(5 V tolerant)

(5 V tolerant)

3.3 V

3.3 V

3.3 V

3.3 V O Receive Data Channel A. Used to transport data out of the

I Transmit End of Packet. These pins are used only in U2+

and U3+ (packet) modes. This signal indicates that the last
word of a packet is on the TxDATA[D:A][15:0] bus.
TxEOP[D:A] is valid only when TxENB[D:A] is asserted, and
is sampled on the rising edge of TxCLK[D:A] .

In U3+ (32-bit mode), onl y the TxE OP[ A] input pi n of po rt A
is used to indicate the end of the incoming packet.

I Transmit Error. These pins are used only in U2+ and U3+

(packet) modes. TxERR[D:A] is only used in packet modes,
and indicates that the current packet is to be aborted and
discarded, if possible. TxERR[D:A] is only valid when
TxEOP[D:A] and TxENB[D:A] are asserted, and is sampled
on the rising edge of TxCLK[D:A].

In U3+ (32-bit mode), the TxERR[A] and the TxERR[B] input
pin of port A is used to indicate an error on the incoming
packet.

I Receive Address. Receive address is driven to the MPHY

to poll and sele ct the a ppropriate MPHY chan nel .
Note: Th e addr ess for each chann el is configured by the

microprocessor.

UTOPIA PHY Rx block. RxDATA[A ][15 :0] is onl y valid when
RxENB[A] is asserted, and is updat ed on the rising edge of
RxCLK[A]. Note that RxDATA[A][15:0] is used in various
UTOPIA modes. In U2 or U2+, all 16 bits are valid. In U3 or
U3+ (8-bit mode), only bi ts 15 to 8 are valid.

In U3 or U3+ (32-bit mode), RxDATA[A][15:0] forms the most
significant 16 bits of the combined data bus (bits 31 to 16),
and RxDATA[B][15:0] forms the least significant 16 bits of the
combined data bus (bits 15 to 0).

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

Agere Systems Inc. 33

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

.

Table 5

AE32

AF35
AF34
AF33
AF32

AF31
AG35
AG34
AG33
AG32
AG31
AH34
AH33
AH32
AH31

AJ34
AN25

AP25
AR25

AL24

AM24

AN24
AP24
AR24

AL23

AM23

AN23
AP23

AL22

AM22

AN22
AP22

Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

Pin Symbol Type I/O Name/Description

RxDATA[B][15]
RxDATA[B][14]
RxDATA[B][13]
RxDATA[B][12]
RxDATA[B][11]
RxDATA[B][10]

RxDATA[B][9]
RxDATA[B][8]
RxDATA[B][7]
RxDATA[B][6]
RxDATA[B][5]
RxDATA[B][4]
RxDATA[B][3]
RxDATA[B][2]
RxDATA[B][1]
RxDATA[B][0]

RxDATA[C][15]
RxDATA[C][14]
RxDATA[C][13]
RxDATA[C][12]
RxDATA[C][11]
RxDATA[C][10]

RxDATA[C][9]
RxDATA[C][8]
RxDATA[C][7]
RxDATA[C][6]
RxDATA[C][5]
RxDATA[C][4]
RxDATA[C][3]
RxDATA[C][2]
RxDATA[C][1]
RxDATA[C][0]

(continued)

3.3 V O Receive Data Channel B. Used to transport data out of the
UTOPIA PHY Rx block. RxDATA[B][15:0] is only valid when
RxENB[B] is asserted, and is updated on the rising edge of
RxCLK[B]. Note that RxDATA[B][15:0] is used in various UTO­PIA modes. In U2 or U2+, all 16 bits are valid. In U3 or U3+ (8­bit mode), only bits 15 to 8 are valid.

In U3 or U3+ (32-bit mode), RxDATA[B][15:0] forms the least sig­nificant 16 bits of the combined data bus (bits 15 to 0), and
RxDATA[A][15:0] forms the most significant 16 bits of the com­bined data bus (bits 31 to 16). In this mode, channel B port must
be provisioned to idle.

In this mode, RxDATA[B][15:0] is valid when RxENB[A] is
asserted, and RxDATA[B][15:0] is updated on the rising edge of
RxCLK[A].

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

3.3 V O Receive Data Channel C. Used to transport data out of the
UTOPIA PHY Rx block. RxDATA[C][15:0] is only valid when
RxENB[C] is asserted, and is updated on the rising edge of
RxCLK[C]. Note that RxDATA[C][15:0] is used in various UTO­PIA modes. In U2 or U2+, all 16 bits are valid. In U3+ (8-bit
mode), only bits 15 to 8 ar e valid.

In U3 or U3+ (32-bit mode), channel C port must be provisioned
to idle mode.

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

34 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

.

Ta ble 5

AM13

AL13

AR12

AP12
AN12
AM12

AL12
AR11

AP11
AN11
AM11
AR10

AP10
AN10
AM10

AL10

AR9

AR22

AJ33

T34

Pin Descriptions—Enhanced UTOPIA Interface Sign als (continued)

Pin Symbol Type I/O Name/Description

RxDATA[D][15]
RxDATA[D][14]
RxDATA[D][13]
RxDATA[D][12]
RxDATA[D][11]
RxDATA[D][10]

RxDATA[D][9]
RxDATA[D][8]
RxDATA[D][7]
RxDATA[D][6]
RxDATA[D][5]
RxDATA[D][4]
RxDATA[D][3]
RxDATA[D][2]
RxDATA[D][1]
RxDATA[D][0]

RxPRTY[D]
RxPRTY[C]
RxPRTY[B]
RxPRTY[A]

(continued)

3.3 V O Receive Data Channel D. Used to transport data out of the
UTOPIA PHY Rx block. RxDATA[D][15:0] is only valid when
RxENB[D] is asserted, and is updated on the rising edge of
RxCLK[D]. Note that RxDATA[D][15:0] is used in various UTO­PIA modes. In U2 or U2+, all 16 bits are valid. In U3+ (8-bit
mode), only bits 15 to 8 are valid.

In U3 or U3+ (32-bit mode), channel D port must be provisioned
to idle mode.

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

3.3 V O Receive Parity. This signal indicates the parity on the
RxDATA[D:A][15:0]. Odd or even parit y may be pr ov is io ned
through a software register. RxPRTY[D:A] is considered valid
only when RxENB[D:A] is asserted, and is updated on the rising
edge of RxCLK[D:A].

AP9

AL21

AJ32

U31

RxSOP/C[D]
RxSOP/C[C]
RxSOP/C[B]
RxSOP/C[A]

In U3 or U3+ (32-bit mode), the RxPRTY[A] parity pin of port A
indicates the parity for the entire 32-bit data output.

3.3 V O Receive Start of Packet/Cell. In ATM mode, RxSOP/C[D:A]
signal marks the start of a cell on the RxDATA[D:A][15:0] bus.
When RxSOP/C[D:A] is high on the clock cycle following the
latching of an active RxENB[D:A] signal, the first word of the cell
structure is pre sen t on the RxDATA [D:A ][15 :0] bus.

In packet modes, the RxSOP/C[D:A] signal marks the start of a
packet on the RxDATA[D:A][15:0] bus. When RxSOP/C[D:A] is
high, the first word of the packet is present on the
RxDATA[D:A][15:0] bus.

RxSOP/C[D:A] is considered valid only when RxENB[D:A] is
asserted, and is updated on the rising edge of RxCLK[D:A].

In U3 or U3+ (32- bit mode ), only the RxSOP/ C[A] pin of port A is
used to indicate a start of packet/cell for the 32-bit data output.

Agere Systems Inc. 35

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

.

Table 5

Pin Descriptions—Enhanced UTOPI A Interface Signals (continued)

(continued)

Pin Symbol Type I/O Name/Description

AL9
AP21
AK33

V33

RxPA[D]
RxPA[C]
RxPA[B]
RxPA[A]

3.3 V O Receive Cell/Packet Available. This signal indicates when the
TDAT042G5 receive FIFO can send data to the master device.
The RxPA[D:A] signal behavior depends on the provisioned low
watermark in the UTOPIA interfac e.

One-Cycle Delay Mode. This mode follows the UTOPIA Level

■

2 Standard. The RxPA response occurs one cycle after the
address is polled. RxENB is asserted to activate the selected
PHY. RxDATA and RxSOP are output one cycle after RxENB is
sampled active by the PHY device.

Two-Cycle Delay Mode. This mode follows the UTOPIA Level

■

3 baselined text*. The RxPA response occurs two cycles after
the address is polled. Rx ENB is asserted to activate the
selected PHY. RxDATA and RxSOP are output two cycles after
RxENB is sampled active by the PHY device.

RxPA[D:A] Assertion. RxPA[D:A] goes high (is asserted)

■

when the amount of data in the receive FIFO has reached or
exceeded the low watermark or there is end of packet (EOP)
resident in the FIFO.

RxPA[D:A] Deassertion. In ATM mode, the RxPA[D:A] signal

■

goes low (is deasser ted) when the FIFO has less than the low
threshold amount of data and there is no EOP inside the FIFO
(i.e., part of an ATM cell). Once the last byte of the current cell
is transmitted, and if the amount of data within the FIFO is still
less than the low threshold, RxPA[D:A] is deasserted.

In packet mode, the RxPA[D:A] signal goes low (is deasserted)
when the FIFO has less than the low threshold amount of data
and there is no EOP inside the FIFO.

Once the data transfer begins (since the amount of data has
reached or exceeded the low watermark), and if there is no
EOP below the low threshold (i.e., a long packet), the RxPA
signal is deasserted when the FIFO is drained by the UTOPIA
master device. In this case, the master must closely monitor the
RxPA[D:A] signals and use these signals as data valid indica­tors to ensure that bad data is not read from the TDAT042G5.
TDAT042G5 will deassert the RxPA[D:A] signal immediately
when the FIFO is drained.

* ATM Forum Technical C ommittee, UTOPIA Level 3, STR-P HY-UL3-01.00, July

1999.

(See fur the r description on next page.)

36 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

.

Ta ble 5

AL9
AP21
AK33

V33

Pin Descriptions—Enhanced UTOPIA Interface Sign als (continued)

Pin Symbol Type I/O Name/Description

RxPA[D]
RxPA[C]
RxPA[B]
RxPA[A]

(continued)

3.3 V O Receive Cell/Packet Available. (continued)
Data Transfer. A TDAT042G5 ingress channel sends data

■

when it has asserted RxPA[D:A] and the master device
requests data (via RxENB[D:A]). In ATM mode, if the master
device requests data using RxENB[D:A] and if the TDAT042G5
has less than the low watermar k amo unt of data to send an d
there is no end of cell in the FIFO (RxPA[D:A] is deasserted),
then the TDAT042G5 UTOPIA interface will send out data that
should be ignored by the master, i.e., it does not send data from
its internal FIFO.

In ATM mode, once an ATM cell transfer starts, the Tx or Rx
side must complete the transfer. If the transfer is not com­pleted, then the cell will be corrupted. The transfer continues
until either (1) the end of cell is reached, when the end of cell
exists below the low watermark, or (2) the end of the FIFO is
reached. If the end of the FIFO is reached, no underflow is
flagged on the receive side. In ATM mode, the low watermark
should be set so that at least one entire cell is in the FIFO prior
to asserting RxPA[D:A].

AM9

AN21

AK34

U34

RxENB[D]
RxENB[C]
RxENB[B]
RxENB[A]

3.3 V

(5 V tolerant)

In packet mode, once the data transfer begins, the RxPA[D:A]
signal will remain asserted until the FIFO is drained if there is
no EOP below the low watermark. During the time RxPA[D:A] is
asserted, valid data is being transferred.

RxPA[D:A] is updated on the rising edge of RxCLK[D:A].
In 32-bit mode, only the RxPA[A] pin of port A is used to indi-

cate the packet/cell available status.
MPHY Support. When the RxPA signals are used for MPHY

■

direct status, the corresponding RxCLK[B, C, and/or D] must be
provided. This clock will be the same as RxCLK[A].

I Receive Data Enable (Active-Low). This signal is used to indi-

cate to the UTOPIA PHY Rx block that it is selected. If
RxENB[D:A] is high, no operation is performed. If RxENB[D:A] is
low, th e UTOPIA PHY Rx block sends data (no t necessarily valid
data).

In U3 or U3+ (32-bit mode), only the RxENB[A] input pin of port A
is used to enable the transfer of data.

Agere Systems Inc. 37

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

.

Table 5

Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

(continued)

Pin Symbol Type I/O* Name/Description

AM8

AN20

AL34

W33

RxCLK[D]
RxCLK[C]
RxCLK[B]
RxCLK[A]

3.3 V

(5 V tolerant)

u

I

/O Receive Clock. This clock is used to read cells or packets from

the receive FIFO. RxCLK[D:A] can operate at speeds from dc to
104 MHz. For clock rates above 52 MHz, the receive clock mu st
be placed in source mode.

RxCLK[D:A] sourcing from the respect ive TxCLK[D:A] may be
provisioned by CLOCK_MODE_Rx (see registers 0x020F,
0x0213, 0x0217, 0x021B on pages 114—115).

In U3 or U3+ (32-bit mode), only the RxCLK[A] input/output pin of
port A is u se d to clock the data out put.

If MPHY mode is used, then all clocks RxCLK[D:A] must be pro­vided.

AN8

AM20

AK31

W35

RxSZ[D]
RxSZ[C]
RxSZ[B]
RxSZ[A]

3.3 V O Recei ve S ize. These pins are used only in U2+ and U3+ (packet)
modes. This signal defines the valid bytes received and their
packing within (1) RxDATA[D:A][15:0] for U2+ 16-bit mode, and (2)
RxDATA[A][15:0] and RxDATA[B][15:0] for the U3+ (32-bit mode).
The meaning of these bits may be inverted through UT register
0x0226 TxSIZE/RxSIZE mode, page 164.

In U3+ (8-bit mode), RxSZ[D:A] are unused.
For U2+ 16-bit mode,

RxSZ[D:A] = 0 defines the MSByte of RxDATA[D:A][15:0], i.e.,
RxDATA[D:A][15:8], to be the last byte of the packet received
when using the default configuration.

RxSZ[D:A] = 1 defines the LSByte of RxDATA[D:A][15:0], i.e.,
RxDATA[D:A][7:0], to be the last byte of the packet received
when using the default configuration.

In U3+ (32-bit mode), the MSByte will be placed on RxDATA[A],
bits 15 to 8. In the 16-bit mode, the MSByte will be placed on
RxDATA[D:A], bits 15 to 8.

For U3+ (32-bit mode), RxSZ[A] and RxSZ[B] are combined to
define four states of the received data stream. RxSZ[C] and
RxSZ[D] are unused. The following states are assigned by
RxSZ[A] and RxSZ[B] when RxEOP[A] is asserted and the
default configuration is provisioned.

RxDATA[A][15:8] RxDATA[A][7:0] RxDATA[B][15:8] RxDAT A[B][7:0]

RxSZ[B]DATA[31:24] DATA[23:16] DATA[15:8] DAT A[7:0]

RxSZ[A]

0 0 Valid N ot valid Not valid Not valid
0 1 Valid Valid Not valid Not valid
1 0 Valid Valid Valid Not valid
1 1 Valid Valid Valid Valid

RxDATA[A] RxDATA[B]

The data bytes are packed into the upper transmitted bytes first.

* Iu = Id = 50 kΩ, where Iu = internal pull-up resistance and Id = internal pull-down resistance.

38 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

.

Table 5

Pin Symbol Type I/O* Name/Description

AN9

AM21

AJ31

U32

AP8

AR21

AK32

V32

Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)

RxEOP[D]
RxEOP[C]
RxEOP[B]
RxEOP[A]

RxERR[D]
RxERR[C]
RxERR[B]
RxERR[A]

(continued)

3.3 V O Receive End of Packet. These pins are used only in U2+ and
U3+ (packet) modes. This signal indicates that the last word of a
packet is on the RxDATA[D:A][15:0] bus. RxEOP[D:A] is valid only
when RxENB[D:A] is asserted, and is updated on the rising edge
of RxCLK[D:A].

In U3+ (32-bit mode), only the RxEOP[A] output pin of port A is
used to indicate the end of the outgoing packet.

3.3 V O Receive Error. The se pins are used only in U2+ and U3+
(packet) modes. RxERR[D:A] is only used in POS mode, and indi­cates that the current packet is to be aborted and discarded, if
possible. RxERR[D:A] is only valid when RxEOP[D:A] and
RxENB[D:A] are asserted, and is updated on the rising edge of
RxCLK[D:A].

If the Rx FIFO overflows, RxERR[D:A] and RxEOP[D:A] are
asserted to indicate a corrupted packet.

RxERR is asserted when a CRC error occurs in any packet mode
using CRC-16 or CRC-32. RxERR is asserted when an incoming
packet has an abort flag at the end of its stream. In both of these
cases, an RxEOP is asserted with the RxERR.

RxERR is not asser ted when a header does not match in PPP
header attaching mode. In that case, no data is sent to the UTO­PIA interface.

In U3+ (32-bit mode), only the RxERR[A] output pin of port A is
used to indicate an error on the outgoing packet.

* Iu = Id = 50 kΩ, where Iu = internal pull-up resistance and Id = internal pull-down resistance.

Agere Systems Inc. 39

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

(continued)

Table 6. Pin Descriptions—Microproce ssor Interface Signals

Pin Symbol Type I/O* Name/Description

u

C7 RST

3.3 V

(5 V tolerant)

Reset (Asynchronous) (Active-Low). Reset must be held

I

active-low for a minimum of 100 ns. After deassertion of reset, the
device is reset and available for use after 8 µs.

E7 ICT

3.3 V

(5 V tolerant)

u

3-State Control (Active-Low). ICT

I

has an intern al 100 kΩ pull­up. This control 3-states the digital outputs. It does not control the
LVPECL outputs.

D7 PMRST 3.3 V

(5 V tolerant)

I/O 1-Second Performance Monitor (PM) Clock. PM clock can be

generated on-chip. This signal will have a 50% duty cycle.
PMRST clock may be programmed by core register 0x0013,

bit 15 (PMRST_I/O_CTRL) to be either an output or input. As an
output clock, it is derived from the transmit line clock, TxCKP/N.
This clock is divided to produce a 1 second, 50% duty cycle clock
output. As an input, PMRST is under software control and can be
activated longer or shorter than once per second. In the software
control mode with PMRST an input, the minimum pulse width of
the external PMRST signal is 10 ms.

D8 MPMODE 3.3 V

(5 V tolerant)

C8 MP CLK 3.3 V

(5 V tolerant)

B8 CS

3.3 V

(5 V tolerant)

B7 INT

3.3 V

(open drain)

A12
B12
C12
D12
E12
A11
B11
C11
D11
A10
B10
C10
D10
E10

A9
B9

* Iu = Id = 50 kΩ, where Iu = internal pull-up resistance and Id = internal pull-down resistance.

DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]

DA TA[9]
DA TA[8]
DA TA[7]
DA TA[6]
DA TA[5]
DA TA[4]
DA TA[3]
DA TA[2]
DA TA[1]
DA TA[0]

3.3 V

(5 V tolerant)

u

I

MPU Mode Select. This sign al is se t high for a synchronous
microprocessor, or low for an asynchronous microprocessor.

u

I

MPU Clock. This clock can operate from 1 Hz to 66 MHz when in
synchronous mode.

u

Chip Select (Active-Low). This signal must be low during regis-

I

ter access.

O Interrupt (Active-Low). This signal goes low when the device

generates an unmasked interrupt.

u

I

/O Data Bus. This bus is a bidirectiona l data bus for writing and

reading software registers. [15:0] refers to a 16-bit data b us
(15 = MSB, 0 = LSB).

40 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

Table 6. Pin Descriptions—Microprocessor Interfa ce Sig nals

(continued)

(continued)

Pin Symbol Type I/O* Name/Description

B16
C16
D16
A15
B15
C15
E15
A14
B14
C14
D14
E14
B13
C13
D13
E13

ADDR[15]
ADDR[14]
ADDR[13]
ADDR[12]
ADDR[11]
ADDR[10]

ADDR[9]
ADDR[8]
ADDR[7]
ADDR[6]
ADDR[5]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[1]
ADDR[0]

E9 ADS

3.3 V

(5 V tolerant)

3.3 V

(5 V tolerant)

u

I

Address Bus. This bus is used to address registers. [15:0] refers
to a 16-bit data bus (15 = MSB, 0 = LSB).

u

Address Strobe (Active-Low). This signal indicates the address

I

is valid for MPU access in the asynchronous mod e, and trans fer
start for the synchronou s mode.

D9 R/W

C9 DS

3.3 V

(5 V tolerant)

3.3 V

(5 V tolerant)

u

Read/Write. This signal is low to indicate a write operation and is

I

high to indicate a read operation.

u

Data Strobe (Active-Low). This signal used in the asynchronous

I

mode (MPMODE = 0) indicates that the data is valid for MPU
writes.

E8 DT

3.3 V O Data Transfer Acknowledge (Active-Low). This signal acknowl-
edges the data transfer cycle.

* Iu = Id = 50 kΩ, where Iu = internal pull-up resistance and Id = internal pull-down resistance.

Table 7. Pin Descriptio ns—General-Purpose I/O Signals: Interface Signals

Pin Symbol Type I/O* Name/Description

AG5
AH2
AH3
AH4

* Iu = Id = 50 kΩ, where Iu = internal pull-up resistance and Id = internal pull-down resistance.

GPIO[3]
GPIO[2]
GPIO[1]
GPIO[0]

3.3 V

(5 V tolera n t )

u

I

/O General-Purpose I/O. These programmable I/O pins may be

used to monitor or control external circuitry . These pins may also
be provisioned to cause an interrupt upon a change in their val­ues.

Agere Systems Inc. 41

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

(continued)

Table 8. Pin Descriptions—JTAG Interface Signals

Pin Symbol Type I/O* Name/Description

u

F2 TCK 3.3 V

(5 V tolerant)

F4 TMS 3.3 V

(5 V tolerant)

G5 TDI 3.3 V

(5 V tolerant)

JTAG Test Clock. This 10 MHz si gnal provides timing for test

I

operations.

u

I

JTAG Test Mode Se lect . Controls test operations. TMS is sam­pled on the risi ng edge of TCK.

u

I

JTAG Test Data In. Provides a 10 Mbits/s test data input signal.
TDI is samp led on the rising edge of TCK.

G2 TDO 3.3 V O JTAG Test Data Out. This 10 Mbits/s data ou tput signa l is

updated on the falling edge of TCK. The TDO output is 3-stated
except when scanning out test data.

G3 TRST

3.3 V

(5 V tolerant)

* Iu = Id = 50 kΩ, where Iu = internal pull-up resistance and Id = internal pull-down resistance.
Note: JTAG interface signals are used for test operations that are carried out using the IEEE P1149.1 test access port. IEEE is a registered

trademark of The Institute of Electrical and Electronics Engineers, Inc.

u

JTAG Test Re set (Ac tive-Low). This signal provides an asyn-

I

chronous reset for the TAP. Under normal device operations,
TRST

should be pulled low. TRST is a Schmitt-trig ger ed inp ut.

42 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Pin Information

(continued)

Table 9. Pin Descriptio ns—Power Signals

Pin Symbol Type* I/O Name/Description

B6 V

A1, A2, A5, A6, A17,

V

DDA

DDD

A18, A30, A31, A34,

A35, B1, B2, B34, B35,

C3, C33, D4, D27, D32,

E1, E5, E11, E16, E20,

E25, E31, E35, F1, F35,

K5, L5, L31, M5, P4, R1,

T5, T31, U35, V1, V2,

V35, W1, Y5, Y31, AB5,

AD5, AE5, AE 31, AF5,

AK1, AK35, AL1, AL5,

AL11, AL16, AL18,
AL20, AL25, AL31,

AL35, AM4, AM32, A N3,

AN33, AP1, AP2, AP34,

AP35, AR1, AR2, AR5,

AR6, AR18, AR19,

AR30, AR31, AR34,

AR35

DDD

E3 V

C6 GND

A3, A4, A7, A8, A13,

PLL P — Digital Power Supply PLL.

A

GND

D

A16, A20, A23,

A27, A28, A29, A32,

A33, B3, B4, B32, B33,

C1, C2, C4, C32, C34,
C35, D1, D2, D3, D33,

D34, D35, F3, G1, G35,

H1, H3, H5, H35, N1,

N35, T1, T35, V3, V31,
Y1, Y4, Y35, AA5, AC1,
AC35, AH1, AH35, AJ1,

AJ35, AM1, AM2, AM3,

AM33, AM34, AM35,

AN1, AN2, AN4, AN6,

AN32, AN34, AN35,

AP3, AP4, AP32, AP33,

AR3, AR4, AR7, AR8,

AR13, AR16, AR20,
AR23, AR28, AR29,

AR32, AR33

D

E4 GND

*P = power.

PLL P — Digi tal Ground PLL.

P — Analog Power Supply.
P — Digital Power Supply.

P — Analog Ground.
P — Digital Ground.

Agere Systems Inc. 43

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Pin Information

Table 10. Pin Descriptions —No Connect Pins

Pin Symbol Type I/O Name/Description

E6, D6 NC ——No Connection. Has internal pull-up resistor.

A19, A21, A22, A24,

A25, A26, B5, B17, B 18,

B19, B20, B21, B22,
B23, B24, B25, B26,
B27, B28, B29, B30,

B31, C5, C17, C18, C19,

C20, C21, C22, C23,
C24, C25, C26, C27,

C28, C29, C30, C31, D5,

D15, D17, D18, D19,
D20, D21, D22, D23,
D24, D25, D26, D28,

D29, D30, D31, E2, E17,

E18, E19, E21, E22,
E23, E24, E26, E27,
E28, E29, E30, E32,

E33, E34, F5, F31, F32,

F33, F34, G4, G31, U33,

V34, AL8, AL19, AM7,

AM19, AN19, AN31,

AP5, AP7

(continued)

NC ——No Connection. Do not connect to these pins.

Do not connect to these pins.

44 Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Overview

This device integrates the SONET/SDH interface termination functions with a generic cell/packet delineation cir­cuit. It supports STS-48/STM-16, quad STS-12/STM-4, and quad STS-3/STM-1 interface rates. Up to four data
channels transported within an STS-N payload are processed via the SONET/SDH termination blocks and the on­chip data encapsulation/decapsulation engine. Packet or ATM data are transmitted/received by this device on the
equipment side via the enhanced UTOPIA interface. S ON ET /SD H st rea ms a re tr ansm itte d /received by thi s devic e
on the network side via the line interface.

Concatenation levels supported by this device range fr om STS -1 to ST S-48c. Val id standard concate nate d
SONET frame configurations for this device are STS-3c, STS6c, STS-9c, STS-12c, STS-15c, STS-18c, and STS­48c. Non-standard concatenation levels (such as STS-4c, STS-5c, STS-7c, etc.) are supported as well. In STS-48
mode, four pointer processors are available. This allows an STS-48 frame to carry up to four concatenated sub­frames (for example, mapping of four STS-12c payloads into an STS-48 frame). In quad STS-3 and STS-12
modes, only one pointer processor is available. Therefore, only a single subframe may be mapped into an STS-3
or STS-12 frame (mapping a single STS-3c payload into an STS-12 frame, for instance). For details, see Table 22
on page 68.

This device supports mapping for ATM cells into SONET/SDH, mapping for packet data via all existing or currently
proposed standards (e.g., PPP, SDL) into SONET/SDH streams. Via SDL mapping, this device also supports
packet over fiber or ATM over fiber, respectively. Figure 2 shows the overview block diagram, and Figure 3 sh ows
the interface block diagram for this d ev ice.

SINGLE STM-16/STS-48

OR QUAD STM-4/STS-12

OR QUAD STM-1/STS-3

LINE INTERFACE

SINGLE STM-16/STS-48

OR QUAD STM-4/STS-12

OR QUAD STM-1/STS-3

LINE

TERMINATION

OVERHEAD

PROCESSOR

INSERT

OVERHEAD

PROCESSOR

LINE INTERFACE BLOCK

MONITOR

Figure 2. Overview Block Diagram

PATH

TERMINATION

SPE

MAPPER

POINTER

INTERPRETER

CONTROL

µP INTERFACE

PAYLOAD

TERMINATION

PACKET/CELL
PROCESSOR

-ENCAPSULATION

-SCRAMBLING

-CRC GENERATION

PACKET/CELL
PROCESSOR

-DELINEATION

-DECAPSULATION

-UNSCRAMBLING

-CRC VERIFICATION

ENHANCED

UTOPIA

COMPATIBLE

INTERFACE

(U2, U2+, U3, U3+)

ENHANCED

UTOPIA

INTERFACE

5-6680(F).ar.15

Agere Systems Inc. 45

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Overview

(continued)

Figure 3 shows the interface diagram of the IC.

TRANSMIT

OVERHEAD

TOH

PROCESSOR

OVERHEAD
INTERFACE

RECEIVE

OVERHEAD

PROCESSOR

INTERPRETER

INTERFACE

STS-3/STM-1

STS-12/STM-4

STS-48/STM-16

LINE INTERFACE

STS-3/STM-1

STS-12/STM-4

STS-48/STM-16

INTERFACE

SPE

MAPPER

POINTER

MPU

ATM/HDLC/SDL

FRAME INSERTION

SCRAMBLING

ENCAPSULATION

ATM/HDLC/SDL

FRAME

UNSCRAMBLING

DECAPSULATION

JTAG

INTERFACE

UTOPIA

Tx

UTOPIA

Rx

ENHANCED
UTOPIA
INTERFACE

5-6746(F)r.11

Figure 3. Interface Block Diagram

The receive path terminates and processes section, line, and path overhead. It performs frami ng (A1, A2),
descrambling, detects al ar m con ditions, and monito rs s e c ti on, line, and path BIP-Ns (B1, B2, B3), accumulating
error counts for each level for performance monitoring purposes. Line and path remote error indications (M1, G1)
are also accumulated. The payload pointers (H1, H2) are interpreted, and the synchronous payload envelope
(SPE) is extracted.

The transmit path inserts section, line, and path overhead. It inserts the framing pattern (A1, A2), performs scram­bling, inserts AIS (optionally), and calculates and inserts section, line, and path BIP-8s (B1, B2, B3). Line and path
remote failure indications (M1, G1) are inserted based on received BIP-8 errors. The payload pointers (H1, H2) are
generated, and the SPE is inserted.

When used to implement an ATM UNI, ATM cells are written into an internal 4-cell FIFO buffer using a generic
8-/16-/32-bit wide UTOPIA 2/3 compliant interface. Idle/unassigned cells are automatically inserted when the inter­nal FIFO is empty. The device provides generation of the hea der check sequence and optionally scrambles the
ATM pay lo ad.

46 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Overview

When used to implement a POS UNI, the dev ic e writes pa ck et s into an internal 256-byte FIFO bu ffer using a
generic 8-/16-/32-bit wide enhanced UTOPIA 2/3 compliant interface. HDLC framing performs the insertion of
flags, control escape characters, and the FCS fields. Either the CRC-ITU or CRC-32 (in regular or reversed mode)
can be computed and added to the frame. Counts of transmitted packets and errored/dropped packets are accu­mulated for performance mon ito ring purpos es .

(continued)

ATM/HDLC/HDLC-CRC/PPP Support

TDAT042G5 supports the transfer of ATM cel ls or variable-length packets. Support for 52- or 53-byte cell size s is
provided at the UTOPIA interface through register provisioning. The following three types of packet data can be
sent and received with HLDC-like framing: transparent HDLC, CRC, and PPP. Transparent HDLC contains 0x7E
framing but no CRC. CRC mode is HDLC with an attached CRC. PPP has 0x7E framing with provisionable
attached header information and CRC.

When used to implement an ATM UNI, the device performs cell delineation on the SPE. HEC error correction is
provided. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon
detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled before being
passed to a 4-cell FIF O bu ffer. The r ec eived cells are read from the FIFO u sing a gener i c 8-/16- /32 -b it wide
UTOPIA 2/3 compliant interface. Counts of received ATM cells, uncorrectable HEC errors, and correctable HEC
errors are accumulated independently for performance monitoring purposes.

When used to implement a POS UNI, the device descrambl es the SP E befo re ex trac tin g HDLC frame s. T he con­trol escape characters are removed. Descrambling can be performed after control escape byte destuffing (or
before to control malicious HDLC expansion)
rectness. The packets are placed into a 256-byte FIFO buffer.* The received packets are read from the FIFO using
a generic 8-/16-/32-bit wide enhanced UTOPIA 2/3 compliant interface. Counts of received packets and errored/
dropped packets are accumulated independ ently for perfo r man ce mon ito ring pur po se s. Th e devi ce P O S imple ­mentation also allows the optional attach/detach of a p e r-c hannel p rov i sionable P P P header.

.

The optional 16- or 32-bit error ch eck sequence is ve rified for cor-

* FI FOs are 256 bytes per channel and cannot be reallocated.

Agere Systems Inc. 47

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Overview

(continued)

SDL Support

Supports the simplified data link (SDL) protocol, which is currently being reviewed in standards bodies. The imple­mentation supports 4-b yte modified SDL UNI including the foll owi ng:

CRC-16 based frame delineation with 2-byte packet field length

■

Forty-eighth order scrambler

■

No HDLC-like packet expansion

■

Optional CRC-16/-32 payload check

■

Capable of packet-over-fiber operation (i.e., no SONET frame)

■

Two user-programmable 6-byte OAM messages

■

Optional offset field from 0 to 32 bytes

■

TDA T042G5 provides support for a provisionable offset to the packet to allow for the attachment of layer 2 routing
information (e.g., MPLS tags). Table 11 defines the provisioned value for each offset.

Table 11. Optional Offset Field

Provisioned

Value

0x0 0
0x1 1
0x2 2
0x3 3
0x4 4
0x5 5
0x6 6
0x7 7
0x8 8

0x9 10
0xA 12
0xB 14
0xC 16
0xD 20
0xE 24

0xF 32

Route Tag Length

(Bytes)

The packet length value (header value that CRC is calculated over) will account for the total l ength of the packet
datagram as well as the associated route tags.

48 Agere Systems Inc.

Data Sheet

May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Overview

(continued)

Over-Fiber Mode

Over-fiber mode is used for packet delivery over fi ber . No SONET overhead is added in this mode. Since no
SONET overhead is added, the OHP and PT blocks must be confi gured for the bypass mode.

In transmitting from the TDAT042G5 to the line, the data engine maps the data payload into a full SONET frame
starting at what normally would be the first A1 byte. The data engine continues to map payload into the full SONET
frame until an end of packet or end of frame is reached, at which time the data engine halts the mapping of the
incoming data stream into the SO NE T frame un til the nex t start of frame.

When TDAT042G5 is receiving from the line, the data engine must be provisioned to receive the maximum packet
size, unless the location of the last byte of the packet is known in advance. If the size of the packet is not known,
one must program the data engine to receive the entire SONET frame. The external UTOPIA interface device must
then be capable of extracting the variable length packets from the full SONET frame.

Details of the over-fiber mode are given in the Data Engine (DE) Block section, page 82.

Test and General-Purpose I/O Support

The device is provisioned, controlled, and monitored using a generic 16-bit microprocessor interface. A standard
five-signal IEEE -1149.1 compliant JTAG test port is also provided for boundary-scan purposes.

A 4-bit GPIO (general-purpose input/output) interface is provided to control and/or monitor other onboard devices.

External Interfaces

Figure 4 shows the external interfaces.

TXTOHF

TxCK

TxD

RxD

2

2

TX LINE

2

32

2

32

2

RX LINE

TxFSYNC

TxCKQ

ECLREF

RxCLK

CLKDIV

TXTOHCK

TOHD

X

T

4

MPU AND TEST INTERFACE

RXREF

OHP

RXTOHF

4

RXTOHCK

4

RXTOHD

4

348 SIGNAL PINS

UTOPIA INTERFACE

4 x 24 Tx UTOPIA
+5 MPHY ADDRESS

4 x 24 Rx UTOPIA
+5 MPHY ADDRESS

16

JTAG

5

GPIO

4

RST

ICT

PMRST

MPMODE

MPCLKCSINT

DATA

ADDR

16

ADS

R/W

DS

DT

5-6745(F).br.3

Figure 4. External Interface Summary Diagram

Agere Systems Inc. 49

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Functional Description

The block diagram for this device can be seen in Figure 5.

TOH I/O

Data Sheet

May 2001

Tx LINE I/O

Rx LINE I/O

TX LINERX LINE

OHP

PT DE

Tx UTOPIA I/O

UTOPIA IF

Rx UTOPIA I/O

CTRL

MP JTAG GPIO

5-7055(F).br.2

Figure 5. Functional Block Diagram

50 Agere Systems Inc.

Data Sheet

May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Functional Description

(continued)

Line Interface Block

This device is designed to work with co mmo nl y ava ilabl e optoe lec tron ic co nv erter s for OC- 3, OC-12, and OC-48
line rates. It will also wor k with av ail ab le mul tip lex er and demultiplexer chip se ts for an ST S -48/S T M- 16 li ne inte r­face rate. The line interface will operate in one of three possible modes, and is provisioned through core register
0x0010 (mode), bits 4—0. These three values of the mode register are the only values allowed.

Table 12. Line Interface Modes

Mode[4:0]

Core Register

0x0010

10000 STS-48/STM-16 RxC KP/N, RxD[15: 0]P /N, Tx CKP/N, TxD[15:0]P/N
01111 STS-12/STM-4 RxCLK[D]P/N, RxD[D]P/N, TxCKP/N, TxD[D]P/N

00000 STS-3/STM-1 RxCLK[D]P/N, RxD[DP/N, TxCKP/N, TxD[D]P/N

Interfaces Line Interface Signals

RxCLK[C]P/N, RxD[C]P/N, TxCKP/N, TxD[C]P/N
RxCLK[B]P/N, RxD[B]P/N, TxCKP/N, TxD[B]P/N
RxCLK[A]P/N, RxD[A]P/N, TxCKP/N, TxD[A]P/N

RxCLK[C]P/N, RxD[C]P/N, TxCKP/N, TxD[C]P/N
RxCLK[B]P/N, RxD[B]P/N, TxCKP/N, TxD[B]P/N
RxCLK[A]P/N, RxD[A]P/N, TxCKP/N, TxD[A]P/N

This block provides the interface between the external SONET/SDH line components and the overhead processor
(OHP) block. The line interface mu st prov ide tr ansmi t/r ec ei ve fun cti ons fo r quad STS-3/STM-1, quad STS-12/
STM-4, and STS-48/STM-16 applications. All external inputs and outputs for the TDAT042G5 line I/O block are ref­erenced to the positive edge of the clock. When the external devices are referenced to the negative edge, the dif­ferential input clock will ne ed to be re ve rsed at the TDAT042G5 input.

Receive Line Interface Summary

The following list summarizes the receive line interface operations for each STS mode:

In quad STS-3/STM-1 mode, the receive line interface provides four separate STS-3/STM-1 input pin groups.

■

Each input group comprises a differential LVPECL 155.52 Mbits/s data input and a differential 155.52 MHz clock.
Each input group provides data to only one of four (A, B, C, or D) OHP blocks. This interface is synchronous and
requires an external CDR.

In quad STS-12/STM-4 mode, the receive line interface provides four separate STS-12/STM-4 input pin groups.

■

Each input group comprises a differential LVPECL 622.08 Mbits/s data input and a differential 622.08 MHz clock.
Each input group provides data to only one of four (A, B, C, or D) OHP blocks. This interface is synchronous and
requires an external CDR.

In the STS-48/STM-16 mode, the device provides 16 differential LVPECL data inputs at 155.52 Mbits/s with a dif-

■

ferential LVPECL 155.52 MHz clock. In this mode, an external 1:16 data demultiplexer with a 1/16 clock divider is
required. External barrel shifter circuitry to byte align the data is not required.

Multiplexers select between the terminal loopback data, the 32-bit parallel STS-48/STM-16 data bus, and the

■

four STS-12/STM-4 or STS-3/STM-1 8-bit parallel data buses. The controls for these MUXes are mode (register
0x0010) and loopback (register 0x0012) provided by the control block (see Table 48 and Table 50 on pages
150—151).

For STS-48 mode, the 155.52 MHz input clock is divided by two to 77.76 MH z and distributed to all four multi-

■

plexers. For the STS-1 2/S T M-4 mo de, each 622.08 MHz in p u t clock i s divided by eight to 77.76 MHz. Each

77.76 MHz clock is distr ibuted to the appr opriate clock multiplexer (A, B, C, or D). For the STS-3/STM -1 mode,
each 155.52 MHz input clock is divided by eight to 19.44 MHz. Each 19.44 MHz clock is distributed to the appro­priate clock multiplexer (A, B, C, or D).

Agere Systems Inc. 51

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description

Line Interface Block

(continued)

(continued)

Transmit Line Interface Summary

The following list summarizes the tra ns mit li ne int er fac e operatio ns for each STS mode.

In quad STS-3/STM-1 and STS-12/STM-4 modes, the transmit line interface receives 8 bits of data from each

■

OHP block (A, B, C, and D) at 19.44 Mbits/s and 77.76 Mbits/s, respectively. An 8-to-1 parallel-to-serial conver­sion produces output data at 155.52 Mbits/s for STS-3/STM-1 mode and 622.08 Mbits/s for STS-12/STM-4
mode. For fa ci li ty loo pba ck, the outputs ar e multiplexed with the correspondi ng data fr om the ST S -12 /ST S-3
(STM-4/STM-1) receive block and sent to four differential LVPE CL buffer s.

In STS-48/STM-16 mode, a 32-bit data word at 77.76 Mbits/s is received from the OHP. Then a 2-to-1 parallel-to-

■

parallel conversion is performed producing a 16-bit word at 155.52 Mbits/s. In this mode, an external 16:1 data
demultiplexer is required. Facility loopback is not available for the STS-48/STM-16 mode.

There is a single clock input, TxCKP/N, in the transmit case. The clock source rates are 622.08 MHz (STS-12/

■

STM-4), 155.52 MHz (STS-3/STM-1), or 155.52 MHz (STS-48/STM-16).

In the STS-48/STM-16 case, two transmit clock modes are available, contra* and forward clocking. In the contra­clocking mode, the transmit data is sent out as commanded by TxCKP/N; in addition, an internal PLL must be
activated, core register 0x0010 bit 5, to minimize the phase delay between TxCKP/N and the transmitted data. In
the forward clocking mod e, the transmit data and the clock, TxCKQ (used to clock out the data), are sent in par­allel to the transmit multiplexer.

In STS-12/STM-4 and STS-3/STM-1 modes, the input clock is divided by eight producing the internal clock at

77.76 MHz and 19.44 MHz, respectively. In STS-48/STM-16 mode, the input clock is divided by eight to produce
an internal clock at 77.76 MHz. The CLKDIV pin (H4) controls this division. Table 13 shows the required value of
CLKDIV.

Table 13. Clock Settings for CLKDIV Pin

CLKDIV Pin Description

CLKDIV = 1 When in STS-12/ST M-4 (62 2.08 MHz divide by 8).
CLKDIV = 0 When in STS-3/STM - 1, STS- 48/STM-16 (155.52 MHz divide by 2).

TxFSYNCP/N is an optional external frame sync. This 8 kHz frame sync pulse must be synchronous with

■

TxCKP/N. It is, at minimum, a one TxCKP/N clock cycle wide pulse that is latched in at the system rate
(622.08 MHz or 155.52 MHz). TOH interface signal RxREF should not be used as a source to TxFSYNCP/N.

The active edge of the transmit clock is the positive edge.

■

When TDAT042G5 operates in asynchronous mode (MPMO DE = 0), the li ne block provides the microproc es s or

■

clock to the microprocessor interface block. The CLKDIV pin must be set to ensure that the clock is always

77.76 MHz.

Line interface timing is given in the Interface Timing Specifications section (see Table 168, page 267).

* Contra refers to a type of data transmission whereby a clock signal is received by a register before the register sends data.

52 Agere Systems Inc.

Data Sheet

May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Functional Description

(continued)

SONET Framer

The SONET framer consis ts of the overhead processor (OHP) and path termina t or (PT) blocks. The receive
SONET framer req ui res 625 µs to drop frame after the line input signal is lost. Once a valid receive line input is
restored, the maximum average reframe time (MART) is 250 µs.

Overhead Processor (OHP) Block

The OHP block terminates/generates the section and line overhead bytes of the line. The data rate of the TOH
interface is given in Table 14. Timing for the TOH interface is given in the Interface Timing Specifications section
(see Table 172 and Ta ble 173 , page 271) .

Table 14. R/T TOH Interface Rates

Mode R/T TOH Interface Rate

STS-48/STM-16 20.736* Mbits/s

STS-12/STM-4 20.736 Mbits/s

STS-3/STM-1 5.184 Mbits/s

* This STS-48/STM-16 interface is a four-line interface resulting in an effective interface rate

of 82.944 Mbits/s.

All receive transport overhead bytes are output on the RTOH interface for external processing. Tra nsmit transport
overhead bytes can optionally be inserted from the TTOH interface.

The transmit transport overhead bytes can be inserted in one of three ways selected through software provision­ing: (1) automatically by hardware, (2) via software provisioning, or (3) through the TOAC. Table 15 defines those
overhead bytes that can be inserted via each of the three paths. In some cases, the user has the choice to insert
the byte via software registers or through the TOAC. Superscripts in the table reference these insertion methods
which are des cribed in the footnotes.

Table 15. TOAC Byte Insertion: An STS-3/STM-1 Example

OH Parity

3

6

X

6

X

6

X

6

X

6

X

J0

5

Z0

4

Z0

4

(1st bit of

1st byte)

X

D1

X

X
D4
D7

D10

S1

6

3
6
6

3

3

3

5

B1-2
D1-2

6

X

6

X
D4-2
D7-2

D10-2

Z1-2

1
1

1
1

1

3

B1-3
D2-3

6

X

6

X
D4-3
D7-3

D10-3

Z1-3

1
1

1
1

1

3

E1

D2

X

K1
D5
D8

D11

Z2

5
3

6

2
3
3

3

3

E1-2

D2-2

6

X

K1-2
D5-2
D8-2

D11-2

Z2-2

1
1

1
1
1

1

3

E1-3

D2-3

6

X

K1-3
D5-3
D8-3

D11-3

6

X

1
1

1
1
1

1

F1

D3

X
K2
D6
D9

D12

E2

5

3

6

2
3
3

3

3

F1-2
D3-2

6

X
K2-2
D6-2
D9-2

D12-2

E2-2

1
1

1
1
1

1

1

F1-3
D3-3

6

X
K2-3
D6-3
D9-3

D12-3

E2-3

1

1

1

1
1

1

1

1.Inserted via TOAC, but not part of SONET standard.

2.Inserted via software or automatically via hardware.

3.Inserted via TOAC only.

4.Inserted via software register only.

5.Inserted via TOAC or software register.

6.Inserted via TOAC hardware; should be included in TOAC interface timing.

Agere Systems Inc. 53

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description

Overhead Processor (OHP) Block

(continued)

(continued)

The TOAC inserter must insert the first bit of A1 at the TOAC input, TxTOHD[D:A], during the first clock cycle when
TxTOHF = 1. The TOAC has a built-in parity checker. For the parity che ck, th e value of the first inserted bit of A1
must be set to the parity value of the previous frame. The remainder of the inserted bits of the A1, A2 bytes are
ignored by the transmi t fram er.

Receive OHP
Loss-of-Signal. The loss-of-signal block monitors the incoming scrambled data for the absence of transitions.

When an absence of transitions is detected for a programmable length of time, a loss-of-signal (LOS) is declared.
LOS is cleared when two valid framing patterns are detected, and during the intervening time, no LOS condition is
detected.

Framer. The frame block finds and locks onto the incoming A1 and A2 by tes of the SO NE T trans port ove rhead.
Loss-of-frame (LOF) is declared when a defect persists for more than 3 ms. LOF is cleared when the defect is
absent for more than 3 ms. To prevent intermittent out-of-frame/in-frame conditions, the 3 ms timer is not reset to
zero until an in-frame (or out-of-frame) condition persists for 3 ms. The framer is also responsible for performing bit
rotations on the incoming data stream to ensure that the rest of the IC receives byte-aligned data.

While in-frame, the A1/A2 fr amin g by tes in each frame are compared against the exp ect ed patte rn . Out-of- fr am e
(OOF) is declared when five consecutive frames containing one or more framing pattern errors have been
received.

While out-of-frame, this block will monitor the receive data stream for an occurrence of the framing pattern. When a
framing pattern has been recognized, t he framer performs the necessary bit rotation and verifies that an error-free
framing pattern is present in the next frame before declaring in-frame.

J0 Section Trace. The section trace message is extracted and stored in a 16-byte memory for access by software.
The first byte of the message can be provisioned to be either:

The byte with the most significant bit (MSB) set high (for SDH), or

■

The byte following a carriage return (0x0 D) and line feed (0x0A ) sequen ce (for SONET).

■

J0 mismatch detection is provided using one of four methods (provisionable via J0MONMODE[A—D][1:0]; see reg­ister description, page 173).

Descrambler. The descrambler block implemen ts the fra me sy nchr ono us SONE T desc ramb ler with a gener ati ng
polynomial of 1 + x

6

+ x7. The framing bytes (A1, A2), the section trace bytes (J0), and the growth bytes (Z0) are

not descrambled. The descrambler may be disabled through a software register.

54 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Functional Description

Overhead Processor (OHP) Block

Receive OHP (continued)
B1 BIP-8 Check. The SBIP block counts section BIP-8 (B1) errors. The SBIP value is c alculated over the scram-

bled data of the complete previous frame. The calculated value is compared against the received B1 byte and dif­ferences (errors) are counted. A theoretical maximum of 64,000 errors may be detected per second. The SBIP
block accumulate s these error s in a 16-bit saturating counter. This counter operates in la tch and clear mode to
ensure Bellco re an d ITU com pli ance with regard to not mis si ng any ev ents (bit errors). It is intended that this
counter be polled at least once per second so that no error events a r e missed. Optionally, a maximum of only
one SBIP error per frame can be counted (provisionable via B1BITBLKCNT[A—D]; see register description,
page 174). This causes the error counter to only increment by one when one or more errors are detected.

B2 BIP-N Check. The LBIP block counts line BIP- N error s . The LB IP va lue is calcula ted over the incoming frame
and is compared to the received B2 bytes re ce iv ed in the nex t fram e. The er r ors are coun ted. Op tio nal ly, a maxi­mum of only one LBIP error per frame can be counted (B2BITBLKCNT[A—D]; see register description, page 174).
This causes the block error counter to only increment by one when one or more errors are detected. A theoretical
maximum of 3,072,000 errors may be detected per second. The LBIP block accumulates these errors in a 22-bit
saturating counter. This counter is operated in latch and clear mode to ensure Bellcore and ITU compliance with
regard to not missing any events (bit err ors) . It is inten ded that thi s cou nte r be polled at least o nce per second so
that no error events are missed.

BER Check. The OHP block also detects provisionable signal fail (SF) and signal degrade (SD) conditions. The
SF and SD values are provisioned through a group of software registers (SF addresses 0x0452—0x0469,
SD addresses 0x043A—0x0451). The SF alarm can be provisioned for a bit error rate (BER) of between 10

–5

10

; the SD alarm can be provisioned for a bit error rate (BER) of between 10–5 to 10–9 (see Table 86, page 187).

(continued)

(continued)

–3

to

Agere Systems Inc. 55

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description

Overhead Processor (OHP) Block

(continued)

(continued)
Receive OHP (continued)
Figure 6 illustrates the parameters used in determining the bit error detection rate.

NUMBER OF MONITORING BLOCKS SFBSET[A—D] OR SDBSET[A—D] (I N T H IS CASE, 3)

NUMBER OF FRAMES IN A MONITORING BLOCK SFNSSET[A—D] OR SDNSSET[A—D],

FRAME

BOUNDARY

SFNSCLEAR[A—D] OR SDNSCLEAR[A—D]
(IN THIS CASE, 7)

BLOCK

BOUNDARY

SFLSET[A—D] OR SDLSET[A—D]
SFLCLEAR[A—D] OR SDLCLEAR[A—D]

ACCUMULATED BIP ERROR COUNT:

B1 OR B2 FOR LINE
B3 FOR PATH

SFMSET[A—D] OR SDMSET[A—D]
SFMCLEAR[A—D] OR SDMCLEAR[A—D]

BLOCK GOOD/BAD COUNT

5-7934(F)

Figure 6. Signal Degrade and Failure Parameters for BER

TDAT042G5 provides a method to monitor the BER at the line and path layers. The following explains the algo­rithm for this method to set and clear the BER. The al gorithm for this method is the same for setti ng and clear in g
the BER, the only difference is the programmed values. TDAT042G5 includes two complete sets of identical
counters, one used to determi ne si gnal fa il (SF ) and one us ed to deter mi ne si gnal degrade (SD). The only d iffer­ence between SF and SD is the provisioned values. The same algorithm is used for both the line and path layers of
SONET.

The algorithm uses four sets of counters: labelled Ns (number of frames), L (number of errors), M (number of
errored blocks), and B (total number of blocks). Each of these counters has different values that are provisioned to
either set the BER high or clear the BER indication. The algorithm works by counting blocks, i.e., a preset number
of SONET/SDH frames (Ns). If the number of errors in the block exceeds the provisioned level (L), then the errored
block counter is incremented by 1; othe rw ise, t he numb er of block s in error sta ys at its current level. At this point,
the frame counter and the error counter are reset back to 0 and start counting again. At the end of a preset number
of blocks (B), the count in the errored block counter is compared against a provisioned threshold (M). If the total
number of blocks in error equals or exceeds the provisioned threshold (M), then the BER alarm is raised. If the total
number of blocks in error is less than the provisioned amount (M), then the BER alarm is cleared.

The values used by the counters are determined by the state of the algorithm. If the BER state is low, then the SET
parameters are used. If the BER state is high, then the CLEAR parameters are used.

56 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Functional Description

Overhead Processor (OHP) Block

(continued)

(continued)
Receive OHP (continued)
Table 16 and Table 17 show values of Ns, L, M, and B for STS-3/STM-1, STS-12/STM-4, and STS-48/STM-16 to

set and clear the BER indicator. SF registers are 0x0452—0x0469 and SD registers are 0x043A—0x0451. All
SF/SD set and clear values are hexadecimal.

Table 16. Ns, L, M, and B Values to Set the BER Indicator

Mode BER SF/SD Se t Values Actual

Number o f

Frames

Ns* L* M* B* @BER @BER/2 @BER @BER/2

STS-3/

STM-1

1.00E-03 1 6 3D 3D 62 99.96 85.13 97.68 0.00 0.008 64

1.00E-04 6 9 3 7 48 72.70 7.28 96.06 0.16 0.013 104

1.00E-05 30 7 3 7 384 71.34 10.08 95.19 0.52 0.1 800

1.00E-06 1E0 7 3 7 3840 71.34 10.09 95.19 0.52 1 8000

1.00E-07 127 5 7 4 9 47250 69.74 9.44 95.07 0.13 10 80000

1.00E-08 B5A4 7 3 9 465000 68.07 8.82 98.47 0.82 83 664000

1.00E-09 3F7A0 4 5 F 4160000 56.90 11.25 96.52 0.60 667 5336000

1.00E-10 ————— ———— — —

Probability of

Detecting L

Errors (%)

Probability of

Declaring

SF/SD (%)

Integra-

tion

Time

(s)

Max-

imum

Number

of Frame s

†

STS-12/

STM-4

STS-48/

STM-16

* These are the numbers to be provisioned in TDAT042G5. The actual values of the BER algorithm are 1 greater than the actual values shown.

These BER values cannot be provisioned because the maximum value of L is 0xF (i.e., L is a 4-bit register).

†

1.00E-03

1.00E-04 2 B 6 A 22 84.92 9.64 98.3 8 0.00 0.008 64

1.00E-05 D 8 3 8 117 67.93 7.17 96.48 0.25 0.025 200

1.00E-06 80 8 3 8 1152 66.19 6.66 95.46 0.19 0.25 2000

1.00E-07 4FB 8 3 8 11475 65.75 6.53 95.16 0.18 2.5 20000

1.00E-08 31CE 8 3 8 1 14750 65.75 6.53 95 .16 0.18 21 168000

1.00E-09 1F20C 8 3 8 1147500 65.75 6.53 95.16 0.18 167 1336000

1.00E-10 ————— ———— — —

1.00E-03

1.00E-04 1 E 3F 3F 64 99.95 58.97 96.89 0.00 0.008 64

1.00E-05 5 A 35 3F 320 90.60 16.25 96.47 0.00 0.008 64

1.00E-06 20 7 8 E 480 77.55 13.09 96.69 0.00 0.0625 500

1.00E-07 13A 7 8 E 4710 75.80 12.15 95.17 0. 00 0.625 5000

1.00E-08 C1C 7 7 E 46500 74.58 11 .54 98.09 0.01 5.2 41600

1.00E-09 765C 6 6 A 333300 82.92 19.71 97.29 0.18 42 336000

1.00E-10 ————— ———— — —

— ——— 64 100.00 88.43 100.00 0.04 0.00 8 64

†

— ——— 64 100.00 100.00 100.00 100.00 0.008 64

Agere Systems Inc. 57

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description

Overhead Processor (OHP) Block

(continued)

(continued)

Receive OHP (continued)
Overhead (OH) Extract . A ll tr an sport overhead (TOH) bytes are extracted and sent over the RxTOH interface for

possible external proces si ng . The num ber of bits sent are as follows:

STS-3/STM-1: 5,184,000 bits/s per interface

■

STS-12/STM-4: 20,736,000 bits/s per interface

■

STS-48/STM-16: 82,944,000 bit s/s (over 4 seria l lines (20,736 kbits/s each))

■

Table 17. Ns, L, M, and B Values to Clear the BER Indicator

Mode BE R SF/SD Set Values Actual

Number of

Frames

Ns* L* M* B* @BER*5 @BER @BER*5 @BER

STS-3/

STM-1

1.00E-03 ————— ————— —

1.00E-04 1 6 3 7 8 85.13 0.39 0.27 100.00 0.013 104

1.00E-05 6 2 3 7 48 93.01 11.33 0.01 99.21 0.1 800

1.00E-06 30 2 3 7 384 84.42 6.84 0.34 99.88 1 8 000

1.00E-07 1E05 2 3 7 3840 84.42 6.84 0.34 99.88 10 80000

1.00E-08 1 275 2 4 9 47250 83.66 6.59 0.22 99.98 83 664000

1.00E-09B5A423946500082.866.35 0.0399.756675336000

1.00E-10 3F7A0 2 2 F 4160000 46.31 1.48 0.50 99.84 6670 53360000

Probability of

Detecting L

Errors (%)

Probability of

Clearing

SF/SD (%)

Integra-

tion

Time

(s)

Max-

imum

Number

of Frames

†

STS-12/

STM-4

STS-48/
STM-16

* These are the numbers to be provisioned in TDAT042G5. The actual values of the BER algorithm are 1 greater than the actual values shown.

These BER values cannot be provisioned because the maximum value of L is 0xF (i.e., L is a 4-bit register).

†

1.00E-03

1.00E-04 1 7 6 6 7 100.00 51.54 0.00 99.03 0.008 64

1.00E-05 2 2 8 A 22 98.36 20.51 0.07 100.00 0.025 200

1.00E-06 D 2 3 8 117 87.99 8.23 0.02 99.59 0.25 2000

1.00E-07 80 2 3 8 1152 87.34 7.94 0.02 99.64 2.5 20000

1.00E-08 4FB 2 3 8 11475 87.17 7.87 0.03 99.65 21 168000

1.00E-0931CE23811475087.177.87 0.0399.65 1671336000

1.00E-10 1F20C 2 3 8 1147500 87.17 7.87 0.03 99.65 1670 13360 000

1.00E-03

1.00E-04 † ††† 64 100.00 45.99 0.00 99.42 0.008 64

1.00E-05 1 2 D E 15 100.00 60.11 0.00 99.47 0.008 64

1.00E-06 5 3 D 3F 320 95.07 7.28 0.00 99.98 0.0625 500

1.00E-07 20 2 6 13 640 87.34 7.94 0.00 99.94 0.625 5000

1.00E-08 13A 2 6 13 6280 86.52 7.61 0.00 99.95 5.2 41600

1.00E-09 C1C 2 6 13 62000 85.95 7.38 0.00 99.96 42 336000

1.00E-10 765C 2 4 A 333300 84.89 7.00 0.03 99.95 420 3360000

————— ————— —

†

————— ————— —

58 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Functional Description

Overhead Processor (OHP) Block

(continued)

(continued)
Receive OHP (continued)
The OH interface consists of clock, data, and frame. The data and frame signals update on the falling edge of the

clock. The frame pulse is high for the most significant bit (MSB) of the first bit of the frame. Bytes J0, Z0, and F1
(current and previous), K1, K2, and S1 can also be extracted via software registers.

Table 18 shows the ordering of the bytes for the allowed TOAC configurations.

Table 18. TOAC Channel I/O vs. STS Number/Time Slot

Output Rate TOAC Channel Input vs. Input STS Number/Time Slot

Time

STS-3/STM-1 3 2 1 (Channel A)

3 2 1 (Channel B)
3 2 1 (Channel C)
3 2 1 (Channel D)

STS-12/STM-4 12 9 6 3 11 8 5 2 10 7 4 1 (Channel A)

12 9 6 3 11 8 5 2 10 7 4 1 (Channel B)
12 9 6 3 11 8 5 2 10 7 4 1 (Channel C)
12 9 6 3 11 8 5 2 10 7 4 1 (Channel D)

STS-48/STM-16 39 27 15 3 38 26 14 2 37 25 13 1 (Channel A)

42 30 18 6 41 29 17 5 40 28 16 4 (Channel B)
45 33 21 9 44 32 20 8 43 31 19 7 (Channel C)
48 36 24 12 47 35 23 11 46 34 22 10 (Channel D)

The overhead extract block also performs the following functions:

Error Monitors. The REI_L block counts remote error indication block errors. The M1 byte is extracted and

■

counted. This represents the number of LBIP errors detected by the far-end equipment. Optionally, a maximum
of only one REI-L error per frame may be counted (provisionable via M1BITBLKCNT[A—D]; register description,
page 175). This causes the block error counter to only increment by one when one or more errors are detected.

Automatic Protection Switch Signaling. The APS block filters the K1 and K2 bytes (automatic protecti on

■

switching channel) and stores the validated message in software-accessible registers. The K bytes are validated
after a programmable number of consecutive frames contain identical K1 (and K2[7:3] or K2[7:0]) values. APS
protection switching byte failure is detected within this block when a programmable number of frames have
passed without valid K bytes. The protection switching byte failure is removed upon detection of a programmable
number of frames with identical K1 (and K2[7:3] or K2[7:0]) bytes. The use of K2[7:3] or K2[7:0] is provisionable
via the K1K2_2_OR_1 registe r bit ( see regi st er desc ription, page 169).

Line Remote Defect Indicator. Bits 2, 1, and 0 of the K2 byte are monitored for the pattern 110. If this pattern

■

appears for 3—15 (provisionable by OHP register CNTDK2) consecutive frames, RDI-L is asserted. RDI-L is
removed when any pattern other than 110 is detected for 3—15 (provisionable by OHP register CNTDK2) con­secutive frames. (See page 171 for register description of CNTDK2[A—D][3:0].)

Line Alarm Indication Signal. Bits 6, 7, and 8 of the K2 byte are monitored for the pattern 111. If this pattern

■

appears for 3—15 (provisionable by OHP register CNTDK2) consecutive frames, AIS-L is asserted. AIS-L is
removed when any pattern other than 111 is detected for 3—15 (provisionable by OHP register CNTDK2) con­secutive frames. (See page 171 for register description of CNTDK2[A—D][3:0].)

Agere Systems Inc. 59

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description

Overhead Processor (OHP) Block

(continued)

(continued)

Receive OHP (continued)

Rx Synchronization Message. The S1 block filters the synchronization message (S 1) byte and s tor es the vali-

■

dated message in a software-accessible register. The s ynchro ni zati on me ssage will be validated if a programma­ble number (in OHP register CNTDS1) of consecutive frames contain identical S1 values. An inconsistent
synchronization message alarm will be reported if a provisional number (by OHP register CNTDS1FRAME) of
consecutive frames pass without a validated message occurring. (See page 172 for register descriptions of
CNTDS1[A—D][3:0] and CNTDS1FRAME [A—D][3:0].)

F1 User Channel. The F1 byte is extracted by the OHP. The F1 user channel is monitored for change of state

■

using OHP registers 0x0402, 0x0404, 0x0406, 0x0408 (see register map, page 116). The previous and current
F1 values are stored in F1DMON1[A—D][7:0] and F1DMON0[A—D][7:0], respectively (see page 122 for register
map, page 190 for register descriptions).

DCC and Orderwire Bytes. The data communication channel (D1—D3, D4—D12) and orderwire bytes (E1, E2)

■

can only be extracted via the TOAC.
D1/D2/D3 Section Data Communications Channels (DCC). DCC outputs are taken from the TOAC.

■

D4—D12 Line Data Communications Channels (DCC). DCC outputs are taken from the TOAC.

■

M1 REI-L. REI-L is extracted by the OHP.

■

Support for ATM/Packet-Over-Fiber. The transport overhead must be bypassed when operating in data-over-

■

fiber mode. In this mode, the TOH_BYPASS and ROH_BYPASS register bits must be set to 1. No overhead
inserti on/extraction is done when in bypass mod e.

Transmit OHP
Overhead Insertion. Some transport overhead (TOH) bytes can optionally be inserted via the TxTOH interface

and inserted into the TOH bytes (see Table 15, page 53). Certain bytes can be either inserted from values stored in
registers or automatically generated. The TxTOH interface controls the insertion mechanism. Software insertion
takes precedence over TOAC insertion. The number of bits received are as follows:

STS-3/STM-1: 5,184,000 bits/s per interface

■

STS-12/STM-4: 20,736,000 bits/s per interface

■

STS-48/STM-16: 82,944,000 bits/s (over 4 serial lines (20,736 kbits/s each))

■

S1 Synchronizat io n Me ssage. The S1 block controls the insertion of the S1 byte. The byte ordering is the same
as the RxTOAC and is shown in Table 18 (see pa ge59). The S1 byte can be provisioned to come from the TxTOH
interface or from a software-settable register. Control for message insertion is from software control register
TS1INS[A—D] (see register description, page 179 and page 183).

K1K2 APS Signaling. The APS block controls the insertion of the K bytes based on software provisioned K bytes,
and alarm conditions (AIS-L, RDI-L). Inconsistent APS bytes can be inserted via register provisioning by
TAPSBABBLEINS[A—D] (see register description, page 178 and page 183).

RDI_L Generation. The following six alarms contribute to RDI_L generation: LOF, OOF, LOS, LOC, AIS_L, and
SF. They can be inhibited from contributing to RDI-L via transmit control registers (addresses 0x042F, 0x0431,
0x0433, 0x0435; see register description, page 180).

60 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Functional Description

Overhead Processor (OHP) Block

Transmit OHP (continued)
BIP-8 Generation. The SBIP block calcula tes the B1 value according to B el lcore and ITU standards. Insertion of

SBIP errors is possible through the use of software control register TB1ERRINS[A—D] (see register description,
page 180).

The LBIP block calculates the B2 values according to Bellcore and ITU standards. Insertion of LBIP errors is pos­sible through the use of software control register TB2ERRINS[A—D] (see register description, page 180).

The REI_L block controls the insertion of t he remote err or indication bl ock err o r co u nt.
J0 Section Trace. The section trace message is ins er ted eit her from the T xTOH inter fac e or from a mes s age

stored in a 16-byte software-accessible memory. Control for message insertion is from software control register
TJ0INS[A—D] (see register description, page 177 and page 181).

SONET Scrambler. The scramble r b lo ck i m pl em e nts th e fra me sy nc hr on o us SONE T scr am b le r w it h a generating
polynomial of 1 + x

A1/A2 Framing Bytes. A1 and A2 are automatically placed on the line. Errors can be inserted into A2 by setting
OHP register TA1A2ERRINS[A—D][4:0] (see register description, page 180).

6

+ x7. The scrambler may be di sa ble d thro ugh a soft war e reg ist er.

(continued)

(continued)

E1/E2 Orderwire Bytes. The orderwire bytes for section and line are taken from the TOAC.
D1/D2/D3 Section Data Communications Channels (DCC). DCC inputs are taken from the TOAC.
D4—D12 Line Data Communications Channels (DCC). DCC inputs are taken from the TOAC.
F1 User Channel. The F1 byte can be optionally inserted from stored values in OHP register TF1INS[A—D]

(addresses 0x047E, 0x0480, 0x0482, 0x0484; see register description, page 179 and page 183).
M1 REI-L. REI-L can be automatically generated and inserted into the outgoing SONET frame, or can optionally

be inhibited. Errors can be inserted into M1 via OHP register TM1_ERR_INS[A—D] (addresses 0x042E, 0x0430,
0x0432, 0x0434; see register description, page 179 and page 183).

Support for ATM/Packet-Over-Fiber. The transport overhead must be bypassed when operating in data-over­fiber mode. In this mode, the TOH_BYPASS and ROH_BYPASS register bits must be set to 1. No overhead inser­tion/extraction is do ne w hen in by pas s mod e.

Agere Systems Inc. 61

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description

(continued)

Path Terminator (PT) Block

The path terminator performs path overhead (POH) ter mination and extracts the payload for further processing by
the downstream circuitry. The path terminator block interprets the incoming H1/H2 pointer of each incoming STS
channel. The pointer interpreter supports up to four channels and performs path overhead termination on each
channel. Each channel may be either an STS-1, STS-3c, STS-6c, STS-9c, . . . , STS-45c, or STS-48c.

The pointer is validated according to Bellcore and ITU specifica tions. The H1/H2 pointers are used to determine
the location of the first path overhead (POH) byte (J1). The pointer interpreter consists of a finite state machine
(FSM) with four steady states. These states are defined as follows:

Normal state

■

Loss-of-pointer (LOP)

■

Alarm indicati on si gna l (AIS)

■

Concatenation

■

The transition between states will require several consecutive events to protect against transient conditions caused
by bit errors during high BER conditions. The state machine is shown below in Figure 7.

1 NDF POINTER OR

3 NORMAL POINTERS

NORMAL AIS

3

N

8 NDF POINTERS

OR 8 INVALID POINTERS

3 NORMAL POI N T E R S

O

R

M

A

L

P

O

I

N

S

I

A

3

8 INVALID POINTERS

3 AIS INDICATIONS

I

L

A

V

N

I

8

T

E

R

S

S

N

O

I

T

A

C

I

D

N

I

S

R

E

T

N

I

O

P

D

3

C

O

N

C

I

N

D

I

C

A

T

3 CONC INDICATIONS

I

O

N

S

CONCLOP

3 AIS INDICATIONS

3 CONC INDICATIONS

5-7935(F)

Figure 7. Pointer Interpreter State Diagram

The PT block monitors for the following conditions and takes appropriate actions:

Pointer Increment. TDAT042G5 uses an 11-bit counter to count the number of pointer increments and updates

■

the associated counter holding register on the occurrence of PMRST (RPI_INC[A—D][10:0]; see register
description, page 198). A pointer increment can occur when in the normal pointer mode. The following two meth­ods can be used to determine if the pointer increment operation should be performed: 6-of-10 or 8-of-10 majority
matching (selectable via software provisioning of register RINCDEC_6OR8MAJ [A—D]; see register description,
page 200).

62 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Functional Description

Path T erminator (PT) Block

Pointer Decrement. TDAT042G5 uses an 11-bit counter to count the number of pointer decrements and

■

(continued)

(continued)

updates the associated counter holding register on the occurrence of PMRST (RPI_DEC[A—D][10:0]; see regis­ter description, page 198). A pointer decrement can occur when in the normal pointer mode. The following two
methods can be used to determine if the pointer decrement operation should be performed: 6-of-10 or 8-of-10
majority matching (selectable via software provisioning of register RINCDEC_6OR8MAJ [A—D]; see register
description, page 200).

Loss-of-Pointer. LOP-P is declared as shown in the above state diagram. In an LOP-P state, none of the path

■

overhead bytes are ext racted.
AIS-P. The AIS-P is declared when the H1 and H2 bytes are set to all ones. In an AIS-P state, none of the path

■

overhead bytes are ext racted.
Concatenated Pointer. A concatenated pointer is detected when the new data flag is set and the pointer offset

■

value is all ones.
New Pointer. TDAT042G5 uses a 13-bit counter to count the number of new data flags that occur and updates

■

the associated counter holding register on the occurrence of PMRST (RNDFCNT[A—D][12:0]; see register
description, page 198). TDAT042G5 uses a 3-of-4 majority voting scheme to determine if the new data flag is
set. Valid new data flags occur when the NDF bits are either 1001, 0001, 1101, 1011, or 1000.

Normal Pointer. A nor mal pointer occurs when all of the following condition s are tr u e simult ane ous ly :

■

1. NDF is not set (NDF bits are either 0110, 0111, 0100, or 0010),

2. The re is no invalid pointe r value,

3. The re is a valid offset (0 to 782)
Invalid Pointer. An invalid pointer is declared when neither a new data flag nor a normal pointer is detected.

■

SPE Terminate
Receive Path Trace. The path trace message is extracted and stored in a 16-byte (SDH) or 64-byte (SONET)

memory for access by software. The first byte of the message can be provisioned to be either of the following:

For SDH mode, the byte with the most significant bit (MSB) set high (for SDH)

■

For SONET mode, the byte following a carriage re turn (0x0D) and li ne feed (0x0A) sequence

■

The framing can also be disabled.
Receive Error Monitor. The PBIP block counts path BIP-8 errors. A theoretical maximum of 64,000 errors may be

detected per second. The PBIP block accumulates these errors in a 16-bit saturating counter. This counter is oper­ated in latch and clear mode to ensure Bellcore and ITU compliance with regard to not missing any events (bit
errors). It is intended that this counter be polled at least once per second in order that no error events are missed.
The REI_P block counts remote error indication block errors.

Agere Systems Inc. 63

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description

Path Terminator (PT) Block

SPE Terminate (continued)
Receive Signal Label. The C2 block will extract and validate the signal label byte (C2) and store it in a softwar e -

accessible regi ste r. The signal label is updated when a provisionable num ber of co ns ec utive detections of a new
C2 value occur (CNTDC2[A—D][3:0]; see register description, page 204). All monitoring is disabled when the
pointer is in an LOP-P or an AIS -P stat e. Commonly used val ues of C2 with their signal labe ls are lis te d belo w in
Table 19.

Table 19. Types of Signal Labels

C2 Va lue Signal Label

0x00 Unequipped STS SPE
0x01 Equipped nonspeci fic payload
0x13 Mapping for ATM
0x16 Mapping for HDLC-PPP

Any value of C2 may be provisioned. If the provisioned value is not matched by the detected value, then data is not
passed to the DE. If the provisioned value does match the detected value, then data is passed to the DE.

TDA T042G5 will detect unequipped payloads (UNEQ-P) when a provisionable number of consecutive monitored
C2 bytes match the 0x00 unequipped STS SP E sta te. TD AT042G5 will detect mism atc hed payloads (PLM-P)
when a provisionable number of consecutive monitored C2 bytes do not match the provisioned expected payload
label (RC2EXPVAL[7:0]; see register description, page 205).

(continued)

(continued)

Receive Path Status. The G1 block extracts the path remote error indication (REI-P) bits of G1[7:4] and accumu­lates the REI-P errors in a 16-bit saturating counter. This counter is operated in latch and clear mode to ensure
Bellcore and ITU compliance. It is intended that this counter be polled at least once per second in order that no
error events are mi ssed.

RDI-P. This block will also validate the path remote defect indication (RDI-P) bits and store the result in a software­accessible register. The receive path can monitor remote defect indications in either enhanced or single bit RDI-P
modes (provisionable via software bit RDIPMON_ENH_OR1B [A—D]; see register description, page 200). The
interpretation of the G1 byte is as follows.

Table 20. 1-bit Mode

G1 Bytes Description

G1[3:1] = 0xx No RDI-P defec ts
G1[3:1] = 1xx AIS-P, LOP-P

Table 21. 3-bit Mode (Enhanced RDI)

G1 Bytes Description

G1[3:1] = 001 No RDI-P defects
G1[3:1] = 010 PLM-P or LCD-P
G1[3:1] = 101 AIS-P or LOP-P
G1[3:1] = 110 UNEQ-P or TIM-P (TIM-P is J1 mismatc h*)

* TIM-P must be accomplished through (microprocessor) software by reading the

transmit RDI-P state and inserting the G1 bit.

64 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Functional Description

Path T erminator (PT) Block

(continued)

(continued)

Z5/N1, Z4/K4, Z3/F3, H4, F2 Monitoring. TDAT042G5 monitors the F2 user channel byte, the H4 VT multiframe
indicator byte, Z3/F3 growth/user byte, Z4/K4 growth/APS path byte, and the Z5/N1 tandem connection byte.
These bytes are stored in software registers. These registers are updated when a provisionable number of detec­tions of new values occur on the associated incoming byte. All monitoring is disabled when the pointer is in an
LOP-P or an AIS-P state.

Signal Failure and Signal Degrade Monitoring. The path overhead processor also detects/clears provisionable
signal fail (SF) and signal degrade (SD) conditions. The SF and SD values are provisionable through a group of
software registers in the PT register map. The provisioning is the same as that shown in Table 16, page 57 of the
Overhead Processor (OHP) Block section.

SPE Generate
Transmit Pointer Generation. The pointer generation block generates the outgoing H1 and H2 poin ter valu es .

Each of the four PT channels can generate one normal (valid) pointer. Therefore, in STS-3/STM-1 and STS-12/
STM-4 modes, only one normal pointer (and only one SPE) may be inserted into the transmitted SONET/SDH
frame. In STS-48/STM-12 mode, all four PT channels are used. Therefore, up to four normal pointers (and four
SPEs) may be inserted into the transmitted SONET/SDH frame.

When inserting concatenated frames, only the fir s t H1 and H2 byte s will con tain a val id poi nte r va lue . The remai n­ing H1 and H2 bytes of the channel will be set to indicate concatenation. The remaining unequipped channels will
have their H1 and H2 pointers set to a fixed pointer value.

For proper pointer generation, the appropriate values must be provisioned in the H-byte transmit state register
THx_STATE (see register description, page 203).

The following examples illustrate how the device may be co nfi gur ed to t rans mit various sub-rates and concate­nated payloads. Each block in the following diagrams represents one STS-1 frame. Figure 8 illustrates how to pro­vision the THx_STA TE registers to transmit an STS-48c frame within an STS-48 signal. In this example, the pointer
to the first STS-1 is provisioned as a normal pointer value while the pointers to the remaining STS-1 signals are
provisioned as concatenated pointers. Figure 9 illustrates how to provision the THx_STATE registers to transmit
four STS-12c frames within an STS-48 signal. The concatenated STS-Mc frames that may be mapped into STS-N
signals (where M ≤ N) are restricted to those listed in Table 22 (see page 68).

121110987654321
39

27

15

3

38

26

14

2

37

25

13

42

30

18

6

41

29

17

5

40

28

16

45

33

21

9

44

32

20

8

43

31

19

48

36

24

12

47

35

23

11

46

34

22

01 01 01 01 01 01 01 01 01 01 01 00
01 01 01 01 01 01 01 01 01 01 01 01
01 01 01 01 01 01 01 01 01 01 01 01
01 01 01 01 01 01 01 01 01 01 01 01

TIME-SLOT NUMBER

1
4
7

10

NORMAL POINTER

TH

_STATE[A][12—1][1:0]

X

TH

_STATE[B][12—1][1:0]

X

_STATE[C][12—1][1:0]

X

TH

_STATE[D][12—1][1:0]

TH

X

47 CONCATENATED POINTERS

0351(F)

Figure 8. STS-48 Signal Carr ying One STS-48c Frame

Agere Systems Inc. 65

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description

Path Terminator (PT) Block

SPE Generate (continued)

121110987654321
39

27

15

3

42

30

18

6

45

33

21

9

48

36

24

12

01 01 01 01 01 01 01 01 00 00 00 00
01 01 01 01 01 01 01 01 01 01 01 01
01 01 01 01 01 01 01 01 01 01 01 01
01 01 01 01 01 01 01 01 01 01 01 01

44 CONCATENATED POINTERS

(continued)

(continued)

38

26

41

29

44

32

47

35

14
17
20
23

11

TIME-SLOT NUMBER

2

37

25

13

1

5

40

28

16

4

8

43

31

19

7

46

34

22

10

FOUR NORMAL POINTERS

TH

_STATE[A][12—1][1:0]

X

TH

_STATE[B][12—1][1:0]

X

_STATE[C][12—1][1:0]

X

TH

_STATE[D][12—1][1:0]

TH

X

0352(F)

Figure 9. STS-48 Signal Carrying Four STS-12c Frames

121110987654321

12a

9a

6a

3a

11a

8a

5a

2a

10a

7a

4a

12b

9b

6b

3b

11b

8b

5b

2b

10b

7b

4b

12c

9c

6c

3c

11c

8c

5c

2c

10c

7c

4c

12d

9d

6d

3d

11d

8d

5d

2d

10d

7d

4d

10 10 10 01 10 10 10 01 10 10 10 00
10 10 10 01 10 10 10 01 10 10 10 00
10 10 10 01 10 10 10 01 10 10 10 00
10 10 10 01 10 10 10 01 10 10 10 00

UNEQUIPPED

POINTERS

UNEQUIPPED

POINTERS

UNEQUIPPED

POINTERS

TIME-SLOT NUMBER

1a
1b
1c
1d

CONCATENATED POINTERS

TH

_STATE[A][12—1][1:0]

X

TH

_STATE[B][12—1][1:0]

X

_STATE[C][12—1][1:0]

X

TH

_STATE[D][12—1][1:0]

TH

X

NORMAL POINTERS

Figure 10. Quad STS-12 Configuration With Each STS-12 Signal Carrying One STS-3c Frame

0353(F)

66 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Functional Description

Path T erminator (PT) Block

SPE Generate (continued)

121110987654321

12a

9a

6a

3a

12b

9b

6b

3b

12c

9c

6c

3c

12d

9d

6d

3d

01 01 01 01 01 01 01 01 01 01 01 00
10 01 01 01 10 01 01 01 10 01 01 00
10 10 01 01 10 10 01 01 10 10 01 00
01 10 10 01 10 10 10 01 10 10 10 00

Figure 11. Quad STS-12 Configuration With Each STS-12 Signal Carrying One STS-12c Frame

(Channel A), One STS-9c Frame (Channel B), One STS-6c Frame (Channel C), and
One STS-3c Frame (Channel D)

(continued)

(continued)

11a

8a

11b

8b

11c

8c

11d

8d

5a
5b
5c
5d

2a
2b
2c
2d

10a
10b
10c
10d

7a
7b
7c
7d

4a
4b
4c
4d

TIME-SLOT NUMBER

1a
1b
1c
1d

NORMAL POINTERS

TH

_STATE[A][12—1][1:0]

X

_STATE[B][12—1][1:0]

TH

X

_STATE[C][12—1][1:0]

X

TH

_STATE[D][12—1][1:0]

TH

X

0354(F)

121110987654321
3a

2a

1a

3a

2a

1a

3a

2a

1a

3a

2a

3b

2b

1b

3b

2b

1b

3b

2b

1b

3b

2b

3c

2c

1c

3c

2c

1c

3c

2c

1c

3c

2c

3d

2d

1d

3d

2d

1d

3d

2d

1d

3d

2d

10 10 10 10 10 10 10 10 10 10 10 00
10 10 10 10 10 10 10 10 10 10 10 00
10 10 10 10 10 10 10 10 10 10 10 00
10 10 10 10 10 10 10 10 10 10 10 00

UNEQUIPPED POINTERS

TIME-SLOT NUMBER

1a
1b
1c
1d

CONCATENATED POINTERS

TH

_STATE[A][12—1][1:0]

X

TH

_STATE[B][12—1][1:0]

X

_STATE[C][12—1][1:0]

X

TH

_STATE[D][12—1][1:0]

TH

X

NORMAL POINTERS

Figure 12. Quad STS-3 Configuration With Each STS-3 Signal Carrying One STS-2c Frame

0355(F)r.1

Agere Systems Inc. 67

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description

Path Terminator (PT) Block

SPE Generate (continued)

The general rule for mapping STS-Mc frames in STS-N signals (M ≤ N) is that the TDAT042G5 can have a maxi­mum of four normal pointers in STS-48 mode. For M ≤ 12, the valid starting locations for mapping into an STS-48
signal are 1, 13, 25, and 37. For M >12, only one normal pointer is permitted and it must start at the first location
(the first STS-1). The TDAT042G5 allows only one normal pointer in STS-3 or STS-12 modes. The only valid start­ing location for mapping concatenated frames into an STS-3 or STS-12 signal is 1.

Table 22. Valid Concatenation Starting Locations: STS-Mc into an STS-48c

STS-1 Number STS-3c STS-6c STS-9c STS-12c STS-15c STS-18c STS-48c

1 YYYYYYY
4 NoNoNoNoNoNoNo

7 NoNoNoNoNoNoNo
10 No No No No No No No
13 Y Y Y Y No No No
16 No No No No No No No
19 No No No No No No No
22 No No No No No No No
25 Y Y Y Y No No No
28 No No No No No No No
31 No No No No No No No
34 No No No No No No No
37 Y Y Y Y No No No
40 No No No No No No No
43 No No No No No No No
46 No No No No No No No

(continued)

(continued)

68 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Functional Description

Path T erminator (PT) Block

SPE Generate (continued)
BIP-8. The PBIP block calculates the B3 value according to Bellcore and ITU standards. Insertion of PBIP errors is

possible through t he use of a so ftware control register.
REI Generation. The REI_P block controls the insertion of the remote error indication block error count. The

received PBIP error counts are inserted into the path status (G1) byte.
RDI-P Generation. The transmit path can insert remote defect indications using either single-bit or enhanced

RDI-P modes (provisionable via software register bit TRDIP_ENH_OR1B[A—D]; see register description, page

202). The highest to lowest priority of the defect code insertion is as follows:

1. AIS-P, LOP-P (applies only to the single-bit version of RDI-P),

2. UNEQ-P,

3. P L M- P, L C D - P,

4. No defects
TIM-P can be inserted using software through TRDIPSINS (registers 0x0AAA, 0x0AB2, 0x0ABA, or 0x0AC2,

bits 15—11; see register description, page 201). The LCD-P defect is observed in the data engine and passed to
the pointer block for transmission. Each particular defect can be inhibited from contributing to the transmitted
RDI-P insertion value via software registers 0x0AAA, 0x0AB2, 0x0ABA, and 0x0AC2. RDI_P can either be inserted
by software or automatically through hardware.

(continued)

(continued)

Z5/N1, Z4/K4, Z3/F3, H4, F2 Insertion. TDAT042G5 inserts the F2 user channel byte, the H4 VT multiframe indi­cator byte, Z3/F3 growth/user byte, Z4/K4 growth/APS path byte, and the Z5/N1 tandem connection byte via soft­ware provisionin g.

Error Insertion Mec han ism s . TDAT042G5 provides a method to inject via software REI- P
(TREIPERRINS[A—D]) and B3 (TB3ERRINS[A—D]) errors into the transmitted SONET frame (see register
descriptions, pag e 202).

Insertion of J1, F2, C2, Z3, H4, Z4, Z5, SS Values. TDAT042G5 provides paged provisionable registers to insert
the path overhead bytes into the outgoing SONET frame. The paging is done by first writing to the page provision­ing register at location 0x0AC6 to set the port number and time slot to be provisioned, and then writing to the
appropriate insertion registers. Available time-slot values for TDAT042G5 are time slot 1 for STS-48c mode; time
slots 1, 2, 3, and 4 for STS-48 consisting of four STS-Mc (M ≤ 12) signals; and time slot 1 for quad STS-12c and
quad STS-3c modes (ports A, B, C, and D confi gu re d for quad ST S -3c and qua d STS- 12 c) .

Agere Systems Inc. 69

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description

(continued)

Data Engine (DE) Block

The DE block processes ATM, SDL, PPP, and HDLC cells/packets at rates up to 2.488 Gbits/s. The DE block
behaves like four ind epe nden t logi ca l data cha nne ls , one for each of the fou r STS -1 2/S TM- 4 or STS -3 /STM -1
channels, or like a separate single channel for STS-48/STM-16. The following description is for each one of these
data engines. Each of the functional elements to be described are independently provisioned.

The data engine suppo rts both AT M cells and packet data formats.

The ATM processor functions with 52-byte, 53-byte, and 56-byte ATM cells.

■

The packet processor has three packet modes: HDLC, CRC, and PPP. All three modes use HDLC framing, i.e.,

■

0x7E delineates the packets. In HDLC mode, the 0x7E framing bytes are inserted or detected by the data
engine. In the CRC mode, a user-selectable 16-bit or 32-bit CRC word is appended or detected at the end of the
packet. The PPP mode places or detects a PPP header on the front of the packet as well as uses the CRC word.

The block diagram for the data engi ne is show n in Figure 13.

RECEIVE-SIDE DE BLOCK

CBINT

PT

INTERFACE

PT

INTERFACE

RX

SEQUENCER

TX

SEQUENCER

SDL

FRAMER

ATM

FRAMER

X43

POST-

UNSCRAMB LE R

X43

POST-

SCRAMBLER

HDLC

FRAMER

TRANSMIT-SIDE DE BLOCK

SDL

INSERTER

ATM

INSERTER

HDLC

INSERTER

X43

PRE-

UNSCRAMBLER

CBINT

X43

PRESCRAMBLER

Figure 13. Block Diagram of Date Engine (DE)

CRC

CHECKER

CRC

GENERATOR

PPP

DETACH

PPP

ATTACH

UT

INTERFACE

UT

INTERFACE

5-8385(F)r.2

70 Agere Systems Inc.

Data Sheet
May 2001

TDAT042G5 SONET/SDH

155/622/2488 Mbits/s Data Interface

Functional Description

Data Engine (DE) Block

(continued)

(continued)

Receive Data Engine
Receive Sequencer. The receive sequencer demaps SONET framing to four logical channels, performs the phys-

ical channel byte alignmen t and pa ck in g, and p erfor ms ap propr i ate pay lo ad clock d oma in tra nsfer. The receive
sequencer must be provisioned properly for correct operation. There are six registers that are fixed for each partic­ular mode of operation (STS-3/STM- 1, STS -1 2/ST M-4, or STS -4 8/S TM- 16) an d must not be modifi ed
(SEQ_CTRL, INIT_CNTS, OH_MARKER_LO, OH_MARKER_HI, SOH_MARKER_LO, SOH_MARKER_HI). See
the register descriptions for details, page 214. Also, the appropriate time slots must be provi sioned for the r ate of
the payload expected for each channel. This is done via the registers Rx_TS[1—12] (see register descriptions,
page 219). An example of how to configure this for STS-48c mode is shown in the section on configuring the trans­mit/receive seque nc er (s ee Transmit Data Engine section, page 78).

ATM Cell Processor. The cell proces s or perfo rm s ATM cell delineation using the ATM header error co rr ec tion
(HEC) field found in the cell header. The HEC is a CRC-8 calculation over the first four octets (total of 32 bits) of
the ATM cell header. If the TDAT042G5 is in bit-synchronous mode (data is not byte-aligned), 32 separate HEC
calculatio ns ar e p er fo rm e d to deli n ea t e an ATM cell . I f the TDAT 042G5 is i n byte - synchronous mode (data is byte­aligned), four separate HEC calculations are performed to delineate an ATM cell. An alpha-delta counter is used to
track the processo r’s ability to frame the ATM cells consistently. When a certain level of confidence is reached
(defined by the programmable delta counter threshold), the frame is declared in sync state, and data is passed to
subsequent blocks. If the frame r is unable to frame ATM cells over a few cell per i ods (def ine d by the programma­ble delta counter threshold), the framer resumes hunt state.

In SONET mode, the processor performs optional X

43

unscrambling of the payload. Because the X43 scrambler is

self-synchronizing, the framer needs no assistance from the data in order to synchronize the scrambler. The

31

TDAT042G5 also supports an X
applications. The state dia gr am for the X

31

an x

+ x28 + 1 polynomial to scramble the data. Unlike the X43 scrambler, the X31 scrambler does not self-

scrambler, complia nt with I.432 , whic h is mainly us ed for pac ket -o ve r-fi ber

31

scrambler is shown in Figure 14 on page 72. The X31 scrambler uses

synchronize based upon the data it receives. Thus, one-bit samples of the scrambler output are sent on the trans­mit side and compared with the scrambler samples on the receive side every 212 bits. If the samples do not match,
the receive-side scrambler is adjusted to converge with the transmit-side scrambler. This process continues until a

31

certain level of confidence in the scrambler synchronization is achieved. In the X
does not send out any output until both the framer and the scrambler are synchronized, whereas in X

mode, the ATM cell processor

31

mode, only

the framer needs to be synchronized.
Idle ATM cells, which contain no real data, can be either left in or removed from the bit stream. The idle cell header

description can be configured, though it is set to a default value (0x00000001). ATM cells can also be filtered if the
header contents match a provisioned match register after masking with a provisionable mask register. This allows
filtering based on the contents of the GFC, PTI, and CLP fields of the header. Optionally, ATM cells may be
dropped if uncorrectable HEC errors are detected. Incoming single-bit ATM header errors can be corrected and the
cells may be passed through or dropped, depending on the software configuration.

The data engine processes only standard 53 -b yte ATM cells. However, the UTOPIA block process e s 52 -byte, 53­byte, 54-byte, and 56-byte cells, and interfaces these to the dat a engine. (See UTOPIA (UT) Interface Block,
page 86, for details).

Agere Systems Inc. 71

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Data Sheet

May 2001

Functional Description

Data Engine (DE) Block

(continued)

(continued)

Receive Data Engine (continued)

COUNTER EQUALS Y

VERIFICATION SYNCHRONIZED

COUNTER LESS

THAN Y

COUNTER EQUALS X

Note: Even in synchronized mode, the confidence counter can continue to increase up to the Z value.

COUNTER DROPS

BELOW V

ACQUISITION

COUNTER LESS

THAN X

COUNTER DROPS

BELOW W

5-8388(F)

Figure 14. State Diagram for the X31 Scrambler Synchronization Process

SDL Frame Processor. The SDL frame processor consists of an SDL framer, which detects the start of SDL pack-

ets, and an (optional) X

48

unscrambler, which is us ed to uns cr am ble payload data. SDL pac ke ts can also arrive
unscrambled, in which case the unscrambler is disabled. The SDL frame processor can frame packets in SDL form
which contain a data length between 4 and 65,535 bytes.

The SDL framer uses a CRC-16 check upon 2 bytes sequences used to determine packet length in order to frame
SDL packets. Since the framer is designed to support data that is no t byte- al ig ned , 32 se par at e fram er s may be
used to search for the CRC-16 pattern. If the data is byte-synchronized, only four frame rs are needed. A confi­dence counter is used to gauge the framer’s ability to frame SDL packets consi s tent ly. When the confidence
counters reaches a certai n lev el (d efi ned by the programmable SD L delta counter register), the framer is in sync
state. Single-bit error correction for the SDL headers is also supported. Shown below in Figure 15 is the general
structure of the SDL packets. In this figure, there is no interpacket fill.

PACKET PAYLOAD

PACKET
LENGTH

CRC-16 PACKET PAYLOAD

PACKET
LENGTH

PACKET PAYLOADCRC-16

5-8386(F)r.2

Figure 15. General Structure of SDL Packets

72 Agere Systems Inc.