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TA16S2FAA
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Lucent Technologies Inc TA16S2FAA, TA16S2CAA, TA16S1FAA, TA16S1CAA, TA16N1CAA Datasheet

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TA16-Type 2.5 G bits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Applications

Telecommunicat ions:
— Inter- and intraoffice SONET/SDH — Subscriber loop — Metropolitan area networks
High-speed data communications

Description

Data Sheet
March 2001
The TA16-Type transpon der s inte gra te up to 15 discre te ICs and optical components, including a 2.5 Gbits/s optical trans­mitte r and receiver pai r, all in a sing le , co mp ac t package.

Features

2.5 Gbits/s optical transmitter and receiver with
16-channel 155 Mbits/s multiplexer/demultiplex er Available with 1.31 µm Fabry-Perot laser transmit-
ter and PIN receiver for intraoffice applications, and 1.31 µm or 1.55 µm DFB laser transmitters and PIN or APD receiver for short-haul to long-haul applications
Pigtailed low-profile package
Differential LVPECL data interface
Operating case temperature range: 0 °C to 65 °C
Automatic transmitter optical power control
Laser bias monitor outp ut
The TA16 transponder performs the parallel-to-serial­to-optical transport and optical transport-to-serial-to­parallel function of the SONE T/SDH protocol. The TA16 transmitter performs the bit serialization and optical transmission of SONET/SDH OC-48/STM-16 data that has been formatted into standard SONET/ SDH compliant, 16-bit parallel format. The TA16 receiver performs the optical-to-electrical conversion function and is then able to detect frame and byte boundaries and demultiplex the serial data into 16-bit parallel OC-48/STM-16 format.
Note: The TA16 transponder does not perform byte-
level multiplexing or interleaving.
Figure 1 shows a simplified block diagram of the TA16-type transponder. This device is a bidirectional module designed to provide a SONET or SDH com­pliant electro-optical interface between the SONET/ SDH photonic p hysical layer and the electrical sec­tion layer. The module contains a 2.5 Gbits/s opt ical transmitter and a 2.5 Gbits/s optical receiver in the same physical package along with the electronics necessary to multip lex and demultiplex sixteen 155 Mbits/s electrical channels. Clock synthesis and clock recovery circuits are also included within the module.
Optical transmitter disable input
SONET frame-detect enable
Loss of signal, loss of sync, loss of framing alarms
Diagnostic loopback capability
Line loopback operation
In the transmit direction, the transponder module multiplexes sixteen 155 Mbits/s LVPECL electrical data signals into an opti cal signal at 2488.32 Mbits/s for launching into optical fiber. An internal 2.488 GHz reference oscillator is phase-locked to an external 155 MHz data timing reference.
TA16-Type 2.5 Gbits/s Transponder with Data Sheet 16-Chann el 155 Mb its/s Multiple x er/D e m u litp le xer March 2001
Table of Contents
Contents Page Tables Page
Features .................................................................... 1
Applications ...............................................................1
Description ................................................................ 1
Absolute Maximum Ratings.......................................3
Pin Information ..........................................................5
Pin Descriptions........................................................ 6
Functional Description ............. ...............................12
Receiver ............................................................. 12
Transmitter ......................................................... 12
Loopback Modes................................................ 13
Transponder Interfacing......................................13
Optical Charac te r i stics ........................... .................14
Electrical Characteristics .........................................15
Timing Characteristics ............................................ 17
Transmitter Data Input Timing ............................17
Input Timing Mode 1 ..........................................18
Input Timing Mode 2 ..........................................19
Forward Clocking ...............................................20
PC
-to-PICLK Timing.........................................21
LK
PHERR/PHINIT...................................................22
Receiver Framing ...............................................24
Qualification and Reliability ..................................... 26
Laser Safety Information ........................................ 26
Class 1 Laser Product.........................................26
Electromagnetic Em iss ions and Immunit y ..........26
Outline Diagram ......................................................27
Ordering Information ...............................................28
Related Product Information....................................28
Table 1. TA16-Type Transponder Pinout ..................6
Table 2. TA16-Type Transponder Input
Pin Descriptions .........................................10
Table 3. TA16-Type Transponder Output
Pin Descriptions.........................................11
Table 4. OC48/STM-16 Transm itter Optical
Characteristics...........................................14
Table 5. OC48/STM-16 Receiver O pt ical
Characteristics...........................................14
Table 6. Transmitter Electrical I/O Characteristics ..15
Table 7. Receiver Electrical I/O Characteristics ......16
Table 8. Power Supply Characteristics ................... 16
Table 9. Transmitter ac Timing Characteristics .......23
Table 10. Receiver ac Timing Characteristics .........23
Table 11. Ordering Information................................28
Table 12. Related Product Information ....................28

Figures Page

Figure 1. TA16-Type Transponder Block Diagram ....4
Figure 2. TA16-Type Transponder Pinout .................5
Figure 3. Transponder Interfacing............................13
Figure 4. Block Diagram Timing Mode 1..................18
Figure 5. Block Diagram Timing Mode 2..................19
Figure 6. Forward Clocking of T A16 Transmitter.....20
Figure 7. PC
Figure 8. PHERR/PHINIT Timing. ................ ............22
Figure 9. ac Input Timing .........................................22
Figure 10. Receiver Output Timing Diagram ...........23
Figure 11. Frame and Byte Detection......................24
Figure 12. OOF Timing (FRAMEN = High)............ ..24
Figure 13. FRAME N Tim ing.....................................25
Figure 14. Interfacing to TxR
-to-PICLK Timing...............................21
LK
Input.................25
EFCLK
2
Agere Systems Inc.
Data Sheet TA16-Type 2.5 Gbits/s Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Description
(continued)
In the receive direction, the transponder module receives a 2488.32 Mbits/s optical signal and converts
The optical transmitter is available with either a 1.31 µm Fabry-Perot laser for short-reach applications or
1.31 µm and 1.55 µm DFB lasers for intermediate- to long-rea ch applic a ti ons. Th e opt ica l ou tpu t signa l is SONET and ITU compliant for OC-48/STM-16 applica­tions as shown in Table 4, Optical Characteristics.
it to an electrical signal, extracts a clock si gnal, and then demultiplexes the data into s ixteen 155 Mbits/s differential LVPECL data signals. The optical receiver is available with either a PIN photodetector or with an APD photodetector. The receiver operates over the wavelength range of 1.1 µm to 1.6 µm and is fully com­pliant to SONET/SDH OC-48/STM-16 physical layer specifications as shown in Table 5, Optical Characteris­tics.

Absolute Maximum Ratings

Stresses in excess of the absol ute maximum ratings can cause permanent damage to the dev ice. These are abso­lute stress ratin gs onl y. Functional operation of the device is not implied at these or any o ther conditions in excess of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect reliability.
Parameter Symbol Min Max Unit
Operating Case Temperature Range T Storage Case Temperature Range T
C S –40 85 °C
Supply Voltage — –0.5 5.5 V Voltage on Any LVPECL Pin — 0 V High-speed LV PECL Output Source Current — — 50 mA Static Discharge Voltage
1
ESD — 500 V Relative Humidity (noncondensing) RH — 85 % Receiver Optical Input Power—Biased:
APD PIN
P
IN
P
IN
Minimum Fiber Bend Radius — 1.25 (31.8) — in. (mm)
075°C
—
dBm dBm
— —
CC
0 8
1. Human body model.
Agere Systems Inc.
3
TA16-Type 2.5 Gbits/s Transponder with Data Sheet 16-Chann el 155 Mb its/s Multiple x er/D e m u litp le xer March 2001
Block Diagram
TXDIS
LSRBIAS
LSR ALRM
LPM TXD[0:15]P TXD[0:15]N
PICLKP/N
PHINIT
PHERR
PCLKP/N
TXREFCLKP/N
LOCKDET
LLOOP
RESET
DLOOP
OOF
FRAMEN
SEARCH
POCLKP/N
FP
16 16
2
2
2
CLOCK DIVIDER PHASE DETECT
2
16:1 PARALL EL
TO SERIAL
TIMING
GENERATION
AND
FRAME/BYTE
DETECT
TIMING
GEN
MUX
D
OC-48/STM-16
OPTICAL TRANSMITTER
MUX
MUX
RXQ[0:15]P RXQ[0:15]N
LOS
IPDMON
16 16
1:16 SE RIAL
TO PARALLEL
MUX

Figure 1. TA16-Type Transponder Block Diagram

CK
OC-48/STM-16
OPTICAL RECEIVER
W/CLOCK RECOVERY
D
1-1011(F).e
4
Agere Systems Inc.
Data Sheet TA16-Type 2.5 Gbits/s Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demulitplexer

Pin Information

60
50
40
30
20
10
1
FGND
NC NC NC NC
RXDGND
RXQ00N RXQ00P RXQ02N RXQ02P
RXDGND
RXQ04N RXQ04P RXQ06N RXQ06P
RXDGND
RXQ08N RXQ08P RXQ10N RXQ10P
RXDGND
RXQ12N RXQ12P RXQ14N RXQ14P
RXDGND
NC NC
NC RXDGND RXAGND RXAGND
RX3.3A RXAGND RXAGND
NC RX3.3D RX3.3D
RXDGND
FRAMEN
NC DLOOP
NC
LSRBIAS
LSRALM
LPM
TXAGND
TX3.3A TX3.3A
TXAGND
TX3.3D TX3.3D
TXDGND
LOCKDET
PICLKN PICLKP
TXDGND
TXD01N TXD01P TXD03N TXD03P
TXDGND
TXD05N TXD05P TXD07N TXD07P
TXDGND
TXD09N TXD09P TXD11N TXD11P
TXDGND
TXD13N TXD13P TXD15N TXD15P
TXDGND
IPDMON
FGND
FGND 16080 NC NC NC NC RXDGND RXQ01N RXQ01P RXQ03N RXQ03P RXDGND 15070 RXQ05N RXQ05P RXQ07N RXQ07P RXDGND RXQ09N RXQ09P RXQ11N RXQ11P RXDGND 140 RXQ13N RXQ13P RXQ15N RXQ15P RXDGND NC NC NC NC POCLKN POCLKP RX3.3A RXAGND RXAGND SEARCH RX3.3D RX3.3D RXDGND OOF
FP
RXDGND LOS LLOOP PHERR NC TXDIS PHINIT NC TX3.3A TX3.3D TXAGND TXDGND PCLKN PCLKP TXDGND TXD00N TXD00P TXDGND TXD02N TXD02P TXD04N TXD04P TXDGND TXD06N TXD06P TXD08N TXD08P TXDGND TXD10N TXD10P TXD12N TXD12P TXDGND TXD14N TXD14P TXREFCLKN TXREFCLKP TXDGND RESET FGND
130
120
110
100
90
81
RX
TX
TOP VIEW
Agere Systems Inc.
1-1014(F).r2

Figure 2. TA16-Type Transponder Pinout

5
TA16-Type 2.5 Gbits/s Transponder with Data Sheet 16-Chann el 155 Mb its/s Multiple x er/D e m u litp le xer March 2001

Pin Descriptions

Table 1. TA16-Type Transpon de r Pinout

Pin # Pin Name I/O Logic Description
01 FGND I Supply Frame Ground 02 IPDMON O Analog Receiver Photodiode Curren t Monitor 03 TxDGND I Supply Transmitter Di gital Ground 04 TxD15P I LVPECL Transmitter 155 Mbits/s MSB Data Input 05 TxD15N I LVPECL Transmi tter 155 Mbits/s MSB Data Input 06 TxD13P I LVPECL Transmitter 155 Mbits/s Data Input 07 TxD13N I LVPECL Transmitter 155 Mbits/s Data Input 08 TxDGND I Supply Transmitter Di gital Ground 09 TxD11P I LVPECL Transmitter 155 Mbits/s Data Input 10 TxD11N I LVPECL Transmitter 155 Mbits/s Data Input 11 TxD09P I LVPECL Transmitter 155 Mbits/s Data Input 12 TxD09N I LVPECL Transmitter 155 Mbits/s Data Input 13 TxDGND I Supply Transmitter Di gital Ground 14 TxD07P I LVPECL Transmitter 155 Mbits/s Data Input 15 TxD07N I LVPECL Transmitter 155 Mbits/s Data Input 16 TxD05P I LVPECL Transmitter 155 Mbits/s Data Input 17 TxD05N I LVPECL Transmitter 155 Mbits/s Data Input 18 TxDGND I Supply Transmitter Di gital Ground 19 TxD03P I LVPECL Transmitter 155 Mbits/s Data Input 20 TxD03N I LVPECL Transmitter 155 Mbits/s Data Input 21 TxD01P I LVPECL Transmitter 155 Mbits/s Data Input 22 TxD01N I LVPECL Transmitter 155 Mbits/s Data Input 23 TxDGND I Supply Transmitter Di gital Ground 24 PIC 25 PIC
P I LVPECL Byte-Aligned Parallel Input Clock at 155 MHz
LK
N I L VPECL Byte-Aligned Parallel Input Clock ar 155 MHz
LK
26 LOCKDET O LVTTL Lock Detect 27 TxDGND I Supply Transmitter Di gital Ground 28 Tx3. 3D I Supply Transmitter 3.3 V Digital Supp ly 29 Tx3. 3D I Supply Transmitter 3.3 V Digital Supp ly 30 TxAGND I Supply Transmitter Anal og Ground 31 Tx3.3A I Supply Trans mi tter 3. 3 V Analog Supply 32 Tx3.3A I Supply Trans mi tter 3. 3 V Analog Supply 33 TxAGND I Supply Transmitter Anal og Ground 34 LPM O Analog Laser Power Monitor 35 LSRAL R M O A nalog Laser Degrade Alarm 36 LSRBIAS O Analog Transmitter Laser Bias Output 37 NC — — No User Connection Permitted 38 D
LOOP
I LVTTL Diagnostic Loopback 39 NC — — No User Connection Permitted 40 FP O LVPECL Frame Pulse 41 FRAMEN I LVTTL Frame Enable 42 RxDGND I Supply Receiver Digital Ground
1. Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND , RxDGND, RxAGND).
1
6
Agere Systems Inc.
Data Sheet TA16-Type 2.5 Gbits/s Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Pin Descriptions
(continued)

Table 1. T A16-Type T r ansponder Pinout (continued)

Pin # Pin Name I/O Logic Description
43 Rx3.3D I Supply Receiver 3.3 V Digital Supply 44 Rx3.3D I Supply Receiver 3.3 V Digital Supply 45 NC — — No User Connection Permitted 46 RxAGND I Supply Receiver Analog Ground 47 RxAGND I Supply Receiver Analog Ground 48 Rx3.3A I Supply Receiver 3.3 V Analog Supply 49 RxAGND I Supply Receiver Analog Ground 50 RxAGND I Supply Receiver Analog Ground 51 RxDGND I Supply Receiver Digital Ground 52 NC — — No User Connection Permitted 53 NC — — No User Connection Permitted 54 NC — — No User Connection Permitted 55 RxDGND I Supply Receiver Digital Ground 56 RxQ14P O LVPECL Rec eiver 155 M b i ts/s Data Output 57 RxQ14N O LVPECL Receiver 155 Mbits/s Data Output 58 RxQ12P O LVPECL Rec eiver 155 M b i ts/s Data Output 59 RxQ12N O LVPECL Receiver 155 Mbits/s Data Output 60 RxDGND I Supply Receiver Digital Ground 61 RxQ10P O LVPECL Rec eiver 155 M b i ts/s Data Output 62 RxQ10N O LVPECL Receiver 155 Mbits/s Data Output 63 RxQ08P O LVPECL Rec eiver 155 M b i ts/s Data Output 64 RxQ08N O LVPECL Receiver 155 Mbits/s Data Output 65 RxDGND I Supply Receiver Digital Ground 66 RxQ06P O LVPECL Rec eiver 155 M b i ts/s Data Output 67 RxQ06N O LVPECL Receiver 155 Mbits/s Data Output 68 RxQ04P O LVPECL Rec eiver 155 M b i ts/s Data Output 69 RxQ04N O LVPECL Receiver 155 Mbits/s Data Output 70 RxDGND I Supply Receiver Digital Ground 71 RxQ02P O LVPECL Rec eiver 155 M b i ts/s Data Output 72 RxQ02N O LVPECL Receiver 155 Mbits/s Data Output 73 RxQ00P O LVPECL Receiver 155 Mbits/s LSB Data Output 74 RxQ00N O LVPECL Receiver 155 Mbits/s LSB Data Output 75 RxDGND I Supply Receiver Digital Ground 76 NC — — No User Connection Permitted 77 NC — — No User Connection Permitted 78 NC — — No User Connection Permitted 79 NC — — No User Connection Permitted 80 FGND I Supply Frame Ground 81 FGND I Supply Frame Ground
1 1
82 RESET I LVTTL Master Reset 83 TxDGND I Supply Transmitter Digital Ground 84 TxR 85 TxR
1. Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).
P I LVPECL Transmitter 155 Mbits/s Reference Clock Input
EFCLK
N I LVPECL Transmitter 155 Mbits/s Reference Clock Input
EFCLK
Agere Systems Inc.
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TA16-Type 2.5 Gbits/s Transponder with Data Sheet 16-Chann el 155 Mb its/s Multiple x er/D e m u litp le xer March 2001
Pin Descriptions
(continued)

Table 1. T A16-Type T r ansponder Pinout (continued)

Pin # Pin Name I/O Logic Description
86 TxD14P I LVPECL Transmitter 155 Mbits/s Data Input 87 TxD14N I LVPECL Transmitter 155 Mbits/s Data Input 88 TxDGND I SUPPLY Transmitter Digital Ground 89 TxD12P I LVPECL Transmitter 155 Mbits/s Data Input 90 TxD12N I LVPECL Transmitter 155 Mbits/s Data Input 91 TxD10P I LVPECL Transmitter 155 Mbits/s Data Input 92 TxD10N I LVPECL Transmitter 155 Mbits/s Data Input 93 TxDGND I Supply Transmitter Di gital Ground 94 TxD08P I LVPECL Transmitter 155 Mbits/s Data Input 95 TxD08N I LVPECL Transmitter 155 Mbits/s Data Input 96 TxD06P I LVPECL Transmitter 155 Mbits/s Data Input 97 TxD06N I LVPECL Transmitter 155 Mbits/s Data Input 98 TxDGND I Supply Transmitter Di gital Ground 99 TxD04P I LVPECL Transmitter 155 Mbits/s Data Input
100 TxD04N I LVPECL Transmitter 155 Mbits/s Data Input 101 TxD02P I LVPECL Transmitter 155 Mbits/s Data Input 102 TxD02N I LVPECL Transmitter 155 Mbits/s Data Input 103 TxDGND I Supp ly Transmi tter Di gital Ground 104 TxD00P I LVPECL Transmi tter 155 Mbits/s LSB Data Input 105 TxD00N I LVPECL Transmitter 155 Mbits/s LSB Data Input 106 TxDGND I Supp ly Transmi tter Di gital Ground 107 PC 108 PC
P O LVPECL Transmitter Parallel Reference Clock Output
LK
N O LVPEC L Transmitter Parallel Reference Clock Output
LK
109 TxDGND I Supp ly Transmi tter Di gital Ground 110 TxAGND I Supply Transmitter A nalog Ground 111 Tx3.3D I Supply Transmitter Digital 3.3 V Supply 112 Tx3.3A I Supply T r ansmitter Analog 3.3 V Supply 113 NC — — No User Connection Permitted 114 PHINIT I LVPECL Phase Initialization 115 T
DIS I TTL Transmitter Disable
X
116 NC — — No User Connection Permitted 117 PHERR O L VPECL Phase Error 118 L
LOOP
I LVTTL Line Loopback (active-low)
119 LOS O LVTTL Loss of Sign al 120 RxDGND I Supply Receiver Digital Ground 121 OOF I LVTTL Out of Frame (enable frame detection) 122 RxDGND I Supply Receiver Digital Ground 123 Rx3.3D I Supp ly Receiver Digital 3.3 V Supply 124 Rx3.3D I Supp ly Receiver Digital 3.3 V Supply 125 SE ARCH O LVTTL Frame Search Output 126 RxAGND I Supply Receiver Analog G r ound 127 RxAGND I Supply Receiver Analog G r ound 128 Rx3.3A I Supply Receiver Analog 3.3 V Supply
1. Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).
8
Agere Systems Inc.
Data Sheet TA16-Type 2.5 Gbits/s Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Pin Descriptions

Table 1. TA16 -Type Transponder Pi nout (continued)

Pin # Pin Name I/O Logic Description
129 POCLKP O LV PECL Byte-Aligned Parallel Output Clock at 155 MHz 130 POC 131 NC — — No User Connection Permitted 132 NC — — No User Connection Permitted 133 NC — — No User Connection Permitted 134 NC — — No User Connection Permitted 135 RxDGND I Supply Receiver Digital Ground 136 RxQ15P O LVPECL Receiver MSB 155 Mbits/s Data Output 137 RxQ15N O LVPECL Receiver MSB 155 Mbits/s Data Output 138 RxQ13P O LVPECL Receiver 155 Mbits/s Data Output 139 RxQ13N O LVPECL Receiver 155 Mbits/s Data Output 140 RxDGND I Supply Receiver Digital Ground 141 RxQ11P O LVPECL Receiver 155 Mbits/s Data Output 142 RxQ11N O LVPECL Receiver 155 Mbits/s Data Output 143 RxQ09P O LVPECL Receiver 155 Mbits/s Data Output 144 RxQ09N O LVPECL Receiver 155 Mbits/s Data Output 145 RxDGND I Supply Receiver Digital Ground 146 RxQ07P O LVPECL Receiver 155 Mbits/s Data Output 147 RxQ07N O LVPECL Receiver 155 Mbits/s Data Output 148 RxQ05P O LVPECL Receiver 155 Mbits/s Data Output 149 RxQ05N O LVPECL Receiver 155 Mbits/s Data Output 150 RxDGND I Supply Receiver Digital Ground 151 RxQ03P O LVPECL Receiver 155 Mbits/s Data Output 152 RxQ03N O LVPECL Receiver 155 Mbits/s Data Output 153 RxQ01P O LVPECL Receiver 155 Mbits/s Data Output 154 RxQ01N O LVPECL Receiver 155 Mbits/s Data Output 155 RxDGND I Supply Receiver Digital Ground 156 NC — — No User Connection Permitted 157 NC — — No User Connection Permitted 158 NC — — No User Connection Permitted 159 NC — — No User Connection Permitted 160 FGND I Supply Frame Ground
1. Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).
(continued)
N O LVPECL Byte-Aligned Parallel Output Clock at 155 MHz
LK
1
Agere Systems Inc.
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TA16-Type 2.5 Gbits/s Transponder with Data Sheet 16-Chann el 155 Mb its/s Multiple x er/D e m u litp le xer March 2001
Pin Descriptions
(continued)

Table 2. TA16-Type Transponder Input Pin Descriptions

Pin Name Pin Description
TxD[0:15]P TxD[0:15]N
16-bit Differential LVPECL Parallel Input Data Bus. TxD15P/N is the most signifi­cant bit of the input word and is the first bit serialized. TxD00P/N is the least signifi­cant bit of the inp ut word and is the last bit serialized. TxD[0:15]P/N is sampled on
PIC PIC
LK LK
the rising edge of PIC
P
Differential LVPECL Parallel Input Clock. A 155 MHz nominally 5 0% duty cycle
N
input clock to which TxD[0:15]P/N is aligned. The rising edge of PICLK transfers the
LK
.
data on the 16 TxD inputs into the holding register of the parallel-to-ser ial converter.
TxR TxR
EFCLK EFCLK
P
Differ ent ia l L VPEC L Low Jitter 155.520 MHz Input Reference Clock. This input is
N
used as the reference for the internal clock frequency synthesizer which generates the 2.5 GHz bit rate clock used to shift data out of the parallel-to-serial converter and also for the byte-rate clock, which transfers the 16-bit parallel input data from the input holding r egister into the parallel-to-serial shift regi ster. Input is internally termi­nated and biased. See discussion on interfacing, page 13.
TxDIS Transmitter Disable Input. A logic HIGH on this input pin shuts off the transmitter’s
laser so that there is no optical output.
D
LOOP
Diagnostic Loopback Enable (LVTTL). When t he D
input is low, the
LOOP
2.5 Gbits/s serial data stream from the parallel-to-serial converter is looped back internally to the serial-to-parallel converter along with an internally generated b it syn­chronous serial clock. The received serial data path from the optical receiver is dis­abled.
L
LOOP
Line Lo opback Enable (LVTTL). When L
is low, the 2.5 Gbits/s serial data and
LOOP
recovered clock from the optical receiver are looped directly back to the optical trans­mitter. The multiplexed serial data from the parallel-to-s erial converter is ignored.
PHINIT Phase Init ializ ation (LVP ECL). A rising edge on this input will realign the internal
timing associated with clocking data into and out of the inte rn al FIFO. For a detailed explanation, see the section on Transmitter Data Input Timing on page 17.
FRAMEN Frame Enable Input (LVTTL). Enables the frame detection circuitry to detect A1
A2 byte alignment and to lock to a word boundary. The TA16 transponder will contin­ually perform fram e acquisiti o n as long as FRAMEN is held high. When this input is low, the frame-detection circuitry is disabled. Frame-detection process is initiated by rising edge of out-of-frame pulse.
OOF Out of Frame (LVTTL). This input indicator is typically generated by external
SONET/SDH overhead monitor circuitry in response to a state in which the frame boundaries of the received SONET/SDH signal are unknown, i.e., after system reset or loss of synchronization. The rising edge of the OOF input initiates the frame detec­tion function if FRAMEN is high. The FP output goes high wh en the frame boundary is detected in the incoming serial data stream from the optical receiver.
RESET Master Reset (LVTTL). Reset input for the multiplexer/demu ltiplexer. A low on this
input clears all buffers and registers. During reset, POC
and PCLK do not toggle.
LK
10
Agere Systems Inc.
Data Sheet TA16-Type 2.5 Gbits/s Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Pin Descriptions
(continued)

Table 3. TA16-Type Transponder Outp ut Pin Descriptions

Pin Name Pin Description
RxQ[0:15]P RxQ[0:15]N
16-bit Differential LVPECL Parallel Output Data Bus. RxQ[0:15] is the 155 Mbyte/s 16-bit output word. RxQ15P/N is the most significant bit of the received word and is the first bit se rialized. RxQ00P/N is the least significant bit of the received word and is the las t bit serialized. RxQ[0:15]P / N i s updated on the falling
POC POC
LK LK
edge of POC
P
Differential LVPECL Parallel Output Clock. A 155 M Hz nominally 50% duty cycle,
N
byte rate output clock that is aligned to the RxQ[0:15] byte serial output data. RxQ[0:15] and FP are updated on the falling edge of POC
Lk
.
.
LK
FP F rame Pulse (LVPECL). Indicates frame boundaries in the received serial data
stream. If framing pattern detec tion is enabled (FRAMEN high and OOF), FP pulses high for one POC detected in the received serial data. FP is updated on the falling edge of POC
cycle when a 32-bit sequence matching the framing pattern is
LK
LK
SEARCH A1 A2 Frame Search Output (LVTTL). A high on this output pin indicates that the
frame detection circuit is active and is searching for a new A1 A2 b yte al ignment. This output will be high during the entire A1 A2 frame search. Once a new alignmen t is found, this signal will remain high for a minimum of one 155 MHz clock period beyond the third A2 byte before it will be set low.
LOS Loss of S ignal (LVTTL). A low on this output indicates a loss of lock by the clock
recovery circuit in the optical receiver.
LSRBIAS Laser Bias (Analog). Provides an indication of the heal th of the laser in th e trans-
mitter. This output changes at the rate of 20 mV/mA of bias current. If this output voltage reaches 1.4 V (70 mA of bias), the automatic power control circuit is strug­gling to maintain output power. This may indicate that the transmitter has reached an end-of-life condition.
LSRALRM Laser Degrade Alarm (5 V CMOS). A logic low on this output i ndicat es t hat the
transmitter’s automatic power control circuits are unable to maintain the n o minal out­put power . This output becomes active when the optical output power degrades 2 dB below the nominal operating power.
LPM Laser Power Monitor (Analog). Provides an indication of the output power level
from the transmitter laser. This output is set at 500 mV for the nominal transmitter optical output power. If the optical power decreases by 3 dB, this output will drop to approximately 250 mV, and if the output power should increase by 3 dB, this output will increase to 1000 mV.
PC
P/N Parallel Byte Clock (Differential LVPECL). A byte-rate reference clock generated
LK
by dividing the internal 2.488 GHz serial bit clock by 16. This output is normally used to synchronize byte-wide transfers from upstream logic into the TA16 transponder. See timing discussion for additional details, page 17.
PHERR Phase Error Signal (Single-Ended LVPECL). T h is signal pulses hig h during each
PC
cycle for which there is potential setup/hold timing violations between the inter-
LK
nal byte clock and the PIC of the PIC
output. For a detailed explanation, see the section on Transmitter Data
LK
timing domains. PHERR is updated on the falling edge
LK
Input Timing on page 17.
IDPMON Receiver Photodiode Current Monitor (Analog). This output provides a current
output that is a mirror of the photocurrent generated by the optica l r eceiver’s photo­diode (APD or PIN).
LOCKDET Lock Detect (LVTTL). This output goes low after the transmit side PLL has locked to
the clock signal provided at the T
XREFCLK
input pins. LOCKDET is an asynchronous
output.
.
Agere Systems Inc.
11
TA16-Type 2.5 Gbits/s Transponder with Data Sheet 16-Chann el 155 Mb its/s Multiple x er/D e m u litp le xer March 2001

Functional Description

Receiver

The optical receiver in the TA16-type transponder is optimized for the particular SDH/SONE T application segment in which it was designed to operate and will have either an APD or PIN photodetector. The detected serial data output of the optical receiver is connected to a clock and data recovery circuit (CDR), which extracts a 2488.32 MHz clock signal. This r ecovered serial bit clock signal and a retimed serial data signal are pre­sented to the 16-bit serial-to-parallel converter and to the frame and byte detection logic.
The serial-to-parallel converter consists of three 16-bit registers. The first is a serial-in parallel-out shift regis­ter, which performs serial-to -parallel conversion. The second is an internal 16-bit holding register, which transfers data from the serial-to-parallel register on byte boundaries as determined by the frame and byte detection logic. On the falling edge of the free-running POC ferred to the output holding register where it becomes available as RxQ[0:15].
The frame and byte boundary detecti on circuitry searches the incoming data for three consecutive A1 bytes followed immediately by an A2 byte. Framing pat­tern detection is enabled and disabled by the FRAMEN input. The frame detection process is started by a ris­ing edge on OOF while FRAMEN is active (FRAMEN= high). It is disabled when a framing pattern is detected. When framing pattern detection is enabled (FRAMEN = high), the framing pattern is used to locate byte and frame boundaries in the incoming serial data stream from the CDR circuits. During this time, the parallel out­put data bus (RxQ[0:15]) will not contain valid data. The timing generator circuitry takes the locate d byte boundary and uses it to block the incoming serial data stream into bytes for output on the parallel output data bus (RxQ[0:15]). The frame boundary is reported on the framing pulse (FP) output when any 32-bit pattern matching the framing pattern is detected in the incom­ing serial data stream. When framing detection is dis­abled (FRAMEN = low), the byte boundary is fixed at the location found when frame detection was previously enabled.

Transmitter

signal, the dat a in the holding register is trans-
LK
element and can operate at e ither 1310 nm or 1550 nm. The transmitter is driven by a serial data stream developed in the parallel-to-serial conversion logic and by a 2488.32 MHz serial bit clock signal syn­thesized from the 155.52 MHz TxR
EFCLK
input.
The parallel-to-serial converter block shown in Figure 1 is comprised of two byte-wide r e g isters. The first regis­ter latches the 16 bits of parallel input data (TxD[0:15]) on the rising edge of PIC
. The second reg ister is a
LK
16-bit parallel-load serial-out shift register that is loaded from the input register. An internally generated byte clock, which is phase aligned to the 2488.32 M H z serial transmit clock, activates the data transfer between the input r egister and the parallel-to-serial register.
The clock divider and p has e detect circuitry shown in Figure 1 generates internal reference clocks and timing functions for the transmitter. Therefore, it is import ant that the TxR
input is generated from a precise
EFCLK
and stable source. To prevent internal timing signals from producing jitter in the transmitted ser ial data tha t exceeds the SDH/SONET jitter generation require­ments of 0.01 UI, it is required that the TxR
EFCLK
be gen e rat e d from a c rysta l oscillator or other so u rce having a frequency accuracy better than 20 ppm. In order to meet the SDH/SO NET requirement, the refer­ence clock jitter must be guaranteed to be less than 1 ps rms over the 12 kHz to 20 MHz bandwidth. When used in SONET network applications, this input clock must be derived from a source that is synchronized to the primary reference clock (stratum 1 clock).
The timing generation circuitry provides two separate functions. It develops a byte rate clock that is synchro­nized to the 2488.32 MHz transmit serial clock, and it provides a mechanism for aligning the phase between the incoming byte clock (PIC
) and the clock which
LK
loads the parallel data from the input register into the parallel-to-serial shift register. T he PC
output is a
LK
byte rate (155 MHz) version of the serial transmit clock and is intended for use by upstream multiplexing and overhead processing circuits. Using PC
for upstream
LK
circuits will ensure a stable frequency and phase rela­tionship between the parallel data coming into the transmitter and the subsequent parallel-to-serial timing functions. The timing generator also provides a feed­back reference clock to the phase detector for use by the transmit serial clock synthesizer (for additional dis­cussions, see transmitter input options, page 17.)
input
The optical transmitter in the TA16-type transponder is optimized for the particular SDH/SONE T segment in which it is designed to operate. The transmitter will have either a Fabry-Perot or a DFB laser as the optical
12
12
Agere Systems Inc.
Data Sheet TA16-Type 2.5 Gbits/s Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Functional Description
(continued)

Loopback M ode s

The TA16 transponder i s capable of operating in either of two loopback modes: diagnostic loopback or line loopback.
Line Loo pback
When LLOOP is pulled low, the received serial data stream and recovered 2488.32 MHz seri a l clock from the optical receiver are connected directly to the serial data and clock inputs of the optical transmitter. This establishes a receive-to-transmit loopback at the serial line rate.
Diagnostic Loopback
When DLOOP is pulled low, a loopback path is estab­lished from the transmitter to the receiver. In this mode, the serial data from the parallel-to-serial converter and the transmit serial clock are looped back to the serial­to-parallel converter and the frame and byte detect cir­cui try, respec tive l y.

Tr ansp onde r Interfac ing

The TxD[0:15]P/N and P I CLKP/N inputs and the RxQ[0:15]P/N, POC high-speed (155 Mbits/s), LVPECL differ ential dat a and clock signals. To maintain optimum signal fidelity, these inputs and ou tputs must be connected to their term i­nating devices via 50 Ω controlled-impedance trans­mission lines. The transmitter inputs (TxD[0:15]P/N, TxR
P/N, and PICLKP/N) must be terminated as
EFCLK
close as possible to the TA16 transponder connector with a Thevenin equivalent impedance equal to 5 0 ¾ terminated to V cc – 2 V. The receiver outputs (RxQ[0:15]P/N, POC minated as close as possible to the device (IC) that these signals int er face to with a Thevenin equivalent impedance equal to 50 Ω terminated to V cc – 2 V.
Figure 3, below, shows one e xample of the proper ter­minations. Other methods m ay be used, provided they meet the requirements stated above.
TxR
P/N. The reference clock input is different
EFCLK
than the TxD and PIC terminated, ac -coupled, and self-biased. Therefore, it must be treated somewhat differently than the TxD and PIC
inputs. Figure 14 shows the proper method for
LK
connecting the TxR
P/N, and PCLKP/N outputs are
LK
P/N, and PCLKP/N) must be ter-
LK
inputs because it is internally
LK
input.
EFCLK
SONET/SDH
INTERFACE IC
TxLINE
RxLINE
130 Ω
80 Ω
50 Ω IMPEDANCE
TRANSMISSION LINES
3.3 V
130 Ω
80 Ω

Figure 3. Transponder Interfa c ing

130 Ω
80 Ω
50 Ω IMPEDANCE
TRANSMISSION LINES
3.3 V
130 Ω
80 Ω
TA16-TYPE TRANSPONDER
TxD[0:15]P
(LVPECL)
MUX
TxD[0:15]N
(LVPECL)
RxD[0:15]P
CONNECTOR
(LVPECL)
DEMUX
RxD[0:15]N
(LVPECL)
Tx
Rx
1-1054(F)
Agere Systems Inc.
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TA16-Type 2.5 Gbits/s Transponder with Data Sheet 16-Chann el 155 Mb its/s Multiple x er/D e m u litp le xer March 2001

Optical Characteristics

Minimum and maximum values specified over operating case temperature range at 50% duty cycle data signal. Typical values are measured at room temperature unless otherwise noted.

Table 4. OC48/STM-16 Transmitter Optical Characteristics (Tc = 0 °C to 65 °C)

Parameter Symbol Min Typ Max Unit
Average Output Power:
Intraoffice (F-P laser) Short Haul (DFB laser) Long Haul:
1.3 µm DFB Laser
1.55 µm DFB Laser
Operating Wavelength:
Intraoffice (F-P laser) Short Haul (DFB laser) Long Haul (1.3 µm DFB laser) Long Haul (1.55 µm DFB laser)
Spectral Width:
Intraoffice (F-P laser)
Short Haul and Long Haul (DFB laser) Side-mode Suppression Ratio (DFB laser) Extinction Ratio
4
Optic a l R ise and Fall Times t Eye Mask of Optical Output Jitter Generation Compliant with GR-253 and ITU-T G.958
1. Output power definitions and measurements per ITU-T Recommendation G.957.
2. Full spectral width measured 20 dB down from the central wavelength peak under fully modulated conditions.
3. Ratio of the average output power in the dominant longitudinal mode to the power in the most significant side mode under fully modulated conditions.
4. Rat io of lo gic 1 output power to log ic 0 outp ut pow er under full y m odulate d co nd itions.
5. GR-253-CORE, Synchronous Optical Network (SONET) Transport Systems: Common Generic Crite ria.
6. ITU- T Recommen da t io n G. 95 7, Optical Int erf ac es for Equipment and Sys tems Relat i ng to th e S yn chronous Digi tal Hierarchy.
1
5, 6
P
o
P
o
P
o
P
o
λ λ λ λ
rms
2
3
∆λ
20
∆λ
SSR 30 — — dB
r
e
, t
R
F
Compliant with GR-253 and ITU-T G.957
–10
–5 –2
–2
1270 1270 1280 1500
— —
–5 –2
0 0
— — — —
— —
–3
0 2
3
1360 1360 1335 1580
4 1
dBm dBm
dBm dBm
nm nm nm nm
nm nm
8.2 — — dB ——200ps

Table 5. OC48/STM-16 Receiver Optical Characteristics (Tc = 0 °C to 65 °C)

Parameter Symbol Min Typ Max Unit
Average Receiver Sensitivity
PIN Receiver (intraoffice, short haul) APD Receiver (long haul)
1
:
P P
RMIN RMIN
–20 –29
–25 –34
— —
Maximum Optical Power:
PIN Rec eiver APD Receiver (long reach)
P
RMAX
RMAX
1
–6
— —
— —
Link Status Switching Threshold
Decreasing Light Input:
APD PIN
LSTD LSTD
— —
TBD TBD
—
— Link Status Response Time — 3 — 100 µs Optical Path Penalty (1310 nm/1550 nm) — — — 1/2 dB Receiver Reflectance — — — –27 dB Jitter Tolerance and Jitter Transfer Compliant with GR-253 and ITU-T G.958
1. At 1310 nm, 1 x 10
14
–10
BER, 2
23
– 1 pseudorandom data input.
Agere Systems Inc.
dBm dBm
dBm dBm
dBm dBm
Data Sheet TA16-Type 2.5 Gbits/s Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demulitplexer

Electrical Characteristics

Table 6. Transmitter Electrical I/O Characteristics (T
= 0 °C to 65 °C, VCC = 3.3 V ± 5%)
C
Parameter Symbol Logic Min Typ Max Unit
Parallel Input Clock PIC
P/N Diff.
LK
153.90 155.52 157.00 MHz
LVPECL Parallel Clock in Duty Cycle — — 40 — 60 % Reference Clock
Frequency Tolerance
Reference Clock Jitter
EFCLK
P/N Diff.
TxR
LVPECL
————1ps
–20 — 20 ppm
(in 12 KHz to 20 MHz band)
Reference Clock
——45—55%
Input Duty Cycle
Reference Clock Rise
and Fall Times
1
Reference Clock Signal Levels:
Diff. Input Voltage Swing Single-ended Input V oltage Swing Differential Input Resistance
Input Data Signal Levels:
Input High, V
IH
Input Low , VIL
Input Voltage Swing, ∆VIN Transmitter Disable Input Transmitter Enable Input Laser Bias Voltage Output Laser Power Monitor Output
3
3
4
5
Laser Degrade Alarm:
Output High, V
Output Low, V
OH
OL
Phase Initialization:
Input High, V
Input Low , V Phase Error
Output High, V
Output Low, V
IH
IL
6
:
OH
OL
Line Loopback Enable:
2
————1.5ns
Diff.
∆V
INSINGLE
∆V
R
INDIFF
DIFF
LVPECL 300
150
80
— —
100
1200
600 120
TxD[0:15]P/N Diff.
TxD
TxE
LVPECL V
IS N
TTL (5 V) 2.0 — 5. 5 V TTL (5 V) 0 — 0.8 V
CC – 1.2
V
CC – 2.0
300
— — —
CC – 0.3
V V
CC – 1.5
—
LSRBIAS Analog 0 200 1600 mV
LPM Analog 35 500 1000 mV
LSRALM 5 V
CMOS 4.5
0
— —
5.2
0.4
PHINIT Single-
Ended
LVPECL
V V
CC CC
– 1.0 – 2.3
— —
V V
– 0.57
CC
– 1.44
CC
PHERR Single-
L
LOOP
Ended
LVPECL
LVTTL
V V
CC CC
– 1.2 – 2.2
— —
V
V
– 0.65
CC
– 1.5
CC
Active-Low:
Input High, V
Input Low , V
1. 20% to 80%.
2. Inte rnally b ia se d and ac-c oupled. Se e Fig ure 13.
3. The tr an sm itter is n or m ally ena ble d and on ly requires an external voltage to disable.
4. Out pu t conversion facto r i s 20 m V/m A of las er bias cu rrent.
5. Set at 500 mV at nominal output power; will track P
6. Terminated into 220 Ω to GND with 100 Ω line-to-line.
IH
IL
O
linear l y (–3 dB = 250 mV, +3 dB = 1000 mV).
2.0 0
— —
V
CC
+ 1.0
0.8
rms
mV mV
Ω
V V
mV
V V
V V
V V
V V
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TA16-Type 2.5 Gbits/s Transponder with Data Sheet 16-Chann el 155 Mb its/s Multiple x er/D e m u litp le xer March 2001
Electrical Characteristics
Table 6 . Transmitter Electrical I/O Characteristics (T
Diagnostic Loopback Enable:
(continued)
= 0 °C to 65 °C, VCC = 3.3 V ± 5%) (continued)
C
DLOOP LVTTL
Active-Low:
Input High, V Input Low, V
Parallel Output Clock:
Output High, V Output Low, V S-E Output Voltage Swing, ∆V Diff. Voltage Swing, ∆V
1. 20% to 80 %.
2. Internally biased and ac-coupled. See Figure 13.
3. The transmitte r is normally enabled and only requi res an external voltage to disable.
4. Output conversion factor is 20 mV/m A of laser bias cur r ent.
5. Set at 500 mV at nominal output power; will track P
6. Terminated in to 220 Ω to GND with 100 Ω line-to-line.
OL
IL
OH
IH
6
PCLKP/N Diff.
LVPECL V
SINGLE
DIFF
O linearly (–3 dB = 250 mV, +3 dB = 1000 mV).
V
2.0
– 1.15
CC
– 1.95
CC
400 800
0
— —
— — — —

Table 7. Receiver Electrical I/O Characteristics (Tc = 0 °C to 65 °C, Vcc = 3.3 V ± 5%)

Parameter Symbol Logic Min Typ Max Unit
Parallel Output Clock:
Output High, V Output Low, V
Duty Cycle — — 40 — 60 %
POC
Lk
Output Data Signal Levels
Output High, V Output Low, V
RxQ[0:15] Rise/Fall Time
OL
OL
OH
OH
1
:
2
Frame Pulse:
Output High, V Output Low, V
OH
OL
Loss-of-Signal Output:
Output High, V Output Low, V
OH
OL
Out-of-Frame Input:
Input High, V Input Low, V
IH
IL
Frame Enable Input F
POCLKP/N
Diff.
LVPECL
V
V
CC
– 2.00
CC
– 1.3
— —
RxQ[0:15]P/N Diff.
LVPECL 2.275
1.490
— —
————1.0ns
FP LVPECL
V
– 1.3
V
CC
– 2.00
CC
— —
LOS LVTTL
2.4 0
— —
OOF LVTTL
RAMEN
2.00
0.0
LVTTL
2.00
0.0
— —
— —
V
V
V
CC
CC
V V
CC
CC
V V
CC
V
CC
V
CC
+ 1.0
CC
0.8
– 0.6
CC
– 1.45
950
1900
– 0.7 – 1.4
2.420
1.680
– 0.7 – 1.4
V
CC
0.4
+ 1.0
0.8
+ 1.0
0.8
V V
V
V mV mV
V V
V V
V V
V V
V V
V V
1. Terminated in to 330 Ω to ground.
2. 20% to 80 %, 330 Ω to ground.

Table 8. Power Supply C haracteristics (Tc = 0 °C to 65 °C)

Parameter Symbol Min Typ Max Unit
Supply Voltage V dc Power Supply Current Drain
1
Power Dissipation P
1. Does not include output termination resistor current drain.
CC
I
CC
DISS
16
3.13 3.3 3.47 V — 1800 2300 mA —6 —W
Agere Systems Inc.
Data Sheet TA16-Type 2.5 Gbits/s Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demulitplexer

Timing Characteristics

Trans mitter Da ta Input T iming

The TA16 transponder utilizes a unique FIFO to decou­ple the internal and external (PIC can be initialized, which allows the system designer to have an infinite PC
-to-PICLK delay through this inter-
LK
facing logic (ASIC or commercial chip set). The config­uration of the FIFO is dependent upon the I/O pins, which comprise the synch timing l oop. This loop is formed from PHERR to PHINIT and PC
The FIFO can be thought of as a memory stack that can be initialized by PHINT or LOCKDET . The PHERR signal is a pointer that goes high when a potential tim­ing mismatch is detected between PIC nally generated PC
clock. When PHERR is fed back
LK
to PHINIT, it initializes the FIFO so that it does not over­flow or underflow.
The internally generated divide-by-16 clock is used to clock out data from the FIFO. PHINIT and LOCKDET signals will center the FIFO after the third PIC This is done to ensure that PIC scheme allows the user to have an infinite PC PIC
delay through the ASIC. Once the FIFO i s cen-
LK
tered, the PC
and PICLK can have a maximum drift of
LK
±5 ns.
) clocks. T he FIFO
LK
to PICLK.
LK
and the inter-
LK
is stable. This
LK
pulse.
LK
to
LK
During normal operation, the incoming data is passed from the PIC generated divide-by-16 PC the frequency o f PIC
nput timing domain to the internally
LK i
timing domain. Although
LK
and PCLK are the same, their
LK
phase relationship is arbitrary. To prev ent errors caused by short setup or hold times between the two domains, the timing generator circu itry m o n itor s the phase relationship betw een PIC
and PCLK.
LK
When an FIFO timing violation is detected, the phase error (PHERR) signal pulses high. If the condition per­sists, PHERR will remain high. When PHERR is fed back into the PHINIT input (by shorting them on the printed-circuit board [PCB]), PHINIT will in itialize the FIFO if PHINIT is held high for at least two byte clocks. The in itialization of the FIFO prevents P C
and PICLK
LK
from concurrently trying to read and write over the same FIFO bank.
During realignment, one to three bytes (16-bits wide) will be lost. Alternatively, the customer logic can take in the PHERR signal, proc es s it, and send an output to the PHINIT input in such a way that only idle bytes are lost during the initialization of the FIFO. Once the FIFO has been initialized, PHERR will go inactive.
Agere Systems Inc.
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TA16-Type 2.5 Gbits/s Transponder with Data Sheet 16-Chann el 155 Mb its/s Multiple x er/D e m u litp le xer March 2001
Timing Characteristics
(continued)

Input Timing Mode 1

In the configuration shown in Figure 4, PHERR to PHINIT has a zero delay (shorted on the PCB) and the PC
is used to clock 16-bit-wide data out of the cus-
LK
tomer ASIC. The FIFO in the multiplex er is 16-bits wide and six registers deep.
The PC
and PIC
LK
READ and WRITE counters for the FIFO. The data bank from the FIFO has to be read by the intern ally
signals respectively control the
LK
CLOCK
generated clock (PC ten by the PIC
LK
) only once after it has been writ-
LK
input.
Since the delay in the customer ASIC is unk nown, the two clocks (PC
and PICLK) might drift in respect to
LK
each other and try to p erform the read and writer oper­ation on the same bank in the FIFO at the same time. However, b efore such a clock mismatch can occur, PHERR goes high and, if externally connected to PHINIT, will initialize the FIF O provided PHINIT rem a i ns high for at lea st two byte clocks. One to three 16-bit words of data will be lost during the initialization of the FIFO.
OSCILLATOR
155.52 MHz ± 20 ppm
XREFCLK
T
PCLK
PICLK
DIVIDER
INTERNAL PCLK
PLL
DATA
CUSTOMER LOGIC
16
PHERR
PHINIT
TXD[0:15]
TIMING
GENERATOR
CENTERS
FIFO
LOCKDET
TA16 TRANSPOND ER

Figure 4. Block Diagram Tim ing Mode 1

FIFO
1-1020(F)
18
18
Agere Systems Inc.
Data Sheet TA16-Type 2.5 Gbits/s Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Timing Characteristics
(continued)

Input Timing Mode 2

To avoid the loss of data, idle or dummy bytes should be sent on the T high. In the configuration shown in Figure 5, the PHERR signal is used as an input to the customer logic. Upon detecting a high on the PHERR signal, the customer logic should return a high signal, one that remains high for at least two byte-clock cycles, to the PHINIT input of the TA16. Also, when PHERR goes
D[0:15] bus whenever PHERR goes
X
CLOCK
high, the cu stomer logic should start sending idle or dummy bytes to the TA16 on the T
D[0:15] bus. This
X
should continue until PHERR goes low. The FIFO is initialized two-to-eight byte clocks after
PHINIT goes high for two byte clocks. PHERR goes low after the FIFO is initialized. Upon detecting a low on PHER R , the customer logic can start sending real data bytes on T PIC
and PHERR to PHINIT) do not have to be of
LK
D[0:15]. The two timing loops (PCLK to
X
equal length.
OSCILLATOR
155.52 MHz ± 20 ppm
XREFCLK
T
PCLK
PICLK
DIVIDER
INTERNAL PCLK
PLL
DATA
D
Q
CUSTOMER LOGIC
16
PHERR
PHINIT
TXD[0:15]
TIMING
GENERATOR
CENTERS
LOCKDET
TA16 TRANSPOND ER

Figure 5. Block Diagram Tim ing Mode 2

FIFO
FIFO
1-1021(F)
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TA16-Type 2.5 Gbits/s Transponder with Data Sheet 16-Chann el 155 Mb its/s Multiple x er/D e m u litp le xer March 2001
Timing Characteristics
(continued)

Forward Clocking

In some applications, it is necessary to forward-clock the data in a SONET/SDH system. In this application, the reference clock from which the high-speed serial clock is synthesized and the parallel data clock both originate from the same source on the customer appli­cation circuit. The timing control logic in the TA16 tran­sponder transmitter automatically generates an internal load signal that has a fixed relationship to the reference
OSCILLATOR
155.52 MH z ± 20 ppm
CLOCK
BUFFER
clock. The logic takes into account the variation of the reference clock to the internal load signal over temper­ature and voltage. The connections required to imple­ment this clocking method are shown in Figure 6. The setup and hold times for PIC
to TxD[0:15] must be
LK
met by the customer logic. Possible p roblems: to meet the jit ter generation spec ifi-
cations required by SONET/SDH, the jitter of the refer­ence clock must be minimized. It could be difficult to meet the SONET jitter generation specifications using a reference clock generated from the customer logic.
TXREFCLK
CLOCK
DATA
CUSTOMER LOGIC

Figure 6. Forward Clocking of the TA16 Transmitter

16
PCLK
TXD[0:15]
TIMING
GENERATOR
PHERR
PHINIT
TA16 TRANSPONDER
PICLK
TXREFCLK
DIVIDER
INTERNAL PCLK
CENTERS
LOCKDET
PLL
FIFO
FIFO
1-1122(F)
20
20
Agere Systems Inc.
Data Sheet TA16-Type 2.5 Gbits/s Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Timing Characteristics
(continued)

PCLK-to-PICLK Timing

After powerup or RESET, the LOCKDET signal will go active, signifying that the PLL has locked to the clock provided on the T
XREFCLK
PCLK
PICLK
input. The FIFO is initialized
LOCKDET
ACTIVE
PCLK-TO-PICLK DELAY IS FI XED AND FIFO
IS INITALIZED AT THE THIRD RISING EDGE OF
PICLK AFTER LOCKDET GOES ACTIVE.

Figure 7. PCLK-to-PICLK Timing

on the third PICLK after LOCKDET goes active. The PC
-to-PICLK delay (tD) can have any value before
LK
the FIFO is initialized. The t
is fixed at the third PICLK
D
after LOCKDET goes active. Once the FIFO is initial­ized, PC
and PICLK cannot drift more than 5.2 ns;
LK
tCH cannot be m ore tha n 5.2 ns.
tD
2ND1ST
3RD
tCH tCH
tD
1123(F)
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TA16-Type 2.5 Gbits/s Transponder with Data Sheet 16-Chann el 155 Mb its/s Multiple x er/D e m u litp le xer March 2001
Timing Characteristics
(continued)

PHERR/PHINIT

Case 1— PHERR and PHINIT are shorted on the printed-circuit board:
PHINIT would go high whenever there is a potential timing mismatch between PC would remain high as long as the timing mismatch between PC
and PICLK. If PHINIT is high for more
LK
than two byte clocks, the FIFO will be in itialized. PHINIT will initialize the FIFO two-to-eight byte clocks after it is high for at least two byte clocks, PHERR (and thus PHINIT) goes active once the FIFI is initialized.
PHERR
PHINIT
and PICLK. PHINIT
LK
2 BYTE
CLOCKS
MINIMU M P UL S E
WIDTH R E QUIR ED
TO CENTER
THE FIFO
2—8 BYTE CLOCKS
Case 2—PHERR signal is input to the customer logic and the customer logic outputs a signal to P H I N IT:
Another possible configuration is where the PHERR signal is input into the customer logic and the customer logic sends an output to the PHINIT input. However , the customer logic must ensure that, upon detecting a high on PHERR, the PHINIT signal remains high for more than two byte clocks. If PHINIT is high for less than two byte clocks, the FIFO is not guaranteed to be initialized. Also, the customer logic must ensure that PHINIT goes low after the FIFO is initialized (PHERR goes low).
CUSTOMER ASIC SENDS A MINIMUM PULSE WIDTH OF 2 BYTE CLOCKS UPON DETECTING A HIGH ON PHERR
PCLK
PICLK
INTERNAL
PCLK
PICLKP
TXD[0:15]
PHERR GOES HIGH ON DETECTING A FIFO TIMING ERROR

Figure 8. PHERR/PHINIT Timing

STXD
t
HTXD
t
FIFO IS INITIALIZED 2—8 BYTE CLOCKS AFTER PHINIT IS HIGH FOR 2 BYTE CLOCKS
1125(F)
1027(F)
22
22

Figure 9. ac Input Ti m ing

Agere Systems Inc.
Data Sheet TA16-Type 2.5 Gbits/s Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Timing Characteristics
(continued)

Table 9. Transmitter ac Timing Characteristics

Symbol Description Min Max Unit
t
STXD
t
HTXD
—PC —PIC
t
D
TxD[0:15] Setup Time w. r. t. PIC TxD[0:15] Hold Time w. r. t. PIC
P/N Duty Cycle 40 60 %
LK
P/N Duty Cycle 40 60 %
LK
LK
LK
1.5 — ns
0.5 — ns
PCLK -to-PICLK Drift After FIFO is Centered — 5.2 ns

Table 10. Receiver ac Timing Characteristics

Symbol Description M i n Max Unit
—POC — RxD[15:0] Rise and Fall Time
tP
POUT
tS
POUT
tH
POUT
1. 20% to 80%; 330 Ω to GND
POCLK Low to RxD[15:0] Valid prop. delay –1 1 ns RxD[15:0] and FP Setup Time w . r. t. POC RxD[15:0] and FP Hold Time w. r. t. POC
Duty Cycle 45 55 %
LK
1
LK
LK
—1.0ns
2—ns 2—ns
POCLKP
FP
RXD[15:0]
tP
POUT
tS
POUT
tH
POUT
1-1022(F)

Figure 10. Receiver Output Timing Diagram

Agere Systems Inc.
23
TA16-Type 2.5 Gbits/s Transponder with Data Sheet 16-Chann el 155 Mb its/s Multiple x er/D e m u litp le xer March 2001
Timing Characteristics
(continued)

Receiver Framing

Figure 11 shows a typical reframe sequence in which a byte realignment is made. The frame and byte bound­ary detection is enabled by the rising edge of OOF. Bot h th e frame and b yte boundaries are recognized upon receipt of the first A2 byte following three consec­utiv e A1 b ytes . The thi rd A2 by te is the first dat a byte to be reported with the correct byte alignment on the out­going data bus (RxD[15:0]). Concurrently, the frame pulse (FP) is set high for one POC
RECOVERED
CLOCK
OOF
SERIAL
DATA
cycle.
LK
A1 A1 A1 A2 A2 A2 A2 A2 A2
The frame and byte boundary detection block is acti­vated by the rising edge of OOF and stays active until the first FP pulse.
Figure 12 shows the frame and byte boundary detec­tion activation by a rising edge of OOF and deactivation by the first FP pulse.
Figure 13 shows the frame and byte boundary detec­tion by the activation of a rising edge of OOF and deac­tivation by the FRAMEN input.
RXD[15:0]
ROCLK
OOF
FP
SEARCH
A1, A1 A1, A1 A1, A1 A2, A2 A2, A2 A2, A2 A2, A2
INVALID DATA VALID DATA
FP
1-1023(F)r.3

Figure 11. Frame and Byte Detection

BOUNDARY DETECTION ENABLED
1-1024(F)
24
24

Figure 12. OOF Timing (FRAMEN = High)

Agere Systems Inc.
Data Sheet TA16-Type 2.5 Gbits/s Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demulitplexer
Timing Characteristics
OOF
FRAMEN
FP
SEARCH
SONET/SDH INTERFACE
IC
(V
CC = 3.3 V)
(continued)
BOUNDARY DETECTION ENABLED

Figure 13. FRAMEN Timing

TXREFCLKP
TXREFCLKN
TA16 TRANSPON DER
MULTIPLEXER
PLL
CLOCK
SYNTHESIZER
100 Ω
1-1025(F)
SONET/SDH INTERFACE
IC
CC
(V
= 3.3 V)
330 Ω
330 Ω
DIFFERENTIAL INTERFACE
330 Ω
50 Ω TRANSMISSION LINES
SINGLE-ENDED INTERFACE
50 Ω TRANSMISSION LINES
TXREFCLKP
TXREFCLKN
300 Ω
0.1 µF
CONNECTOR
TA16 TRANSPON DER
MULTIPLEXER
PLL
CLOCK
60 Ω
SYNTHESIZER
FOR A SINGLE-ENDED INPUT, THE INPUT IMPEDANCE IS EQUIVALENT TO 60 Ω.
CONNECTOR

Figure 14. Interfacing to the TxRefClk Input

Agere Systems Inc.
25
TA16-Type 2.5 Gbits/s Transponder with Data Sheet 16-Chann el 155 Mb its/s Multiple x er/D e m u litp le xer March 2001

Qualification and Reliability

To help ensure high pr oduct reliabilit y and custo m er satisfaction, Agere is committed to an intensive quality pro­gram that starts in the design phase and proceeds through the manufacturing process. Optoelectronics modules are qualified to Agere internal standards using MIL-STD-883 test methods and procedures and using sampling techniques consistent with Telcordia Tech nologies * requirements. This qualification program fully meets t he intent of Telcordia Technologies reliability practices TR-NWT-000468 and T A -TSY-000983. In addition, the Agere Opto- electronics design, development, and manufacturing facility has been certified to be in full compliance with the lat­est ISO
* Telcordia Technologies is a trademar k of Telcordia Technologies, Inc. † ISO is a regi s tere d t rad em a r k o f the Intern at io nal Organiz at i o n for Stan da r d iz ati on .
†
-9001 Quality System Standards.

Laser Safety Information

Class I Las e r Product

All versions of the TA16-type transponders are classified as Class I laser products per FDA/CDRH, 21 CFR 1040 Laser Safety requirements. The transponders have been registered/certified with the FDA under Accession Num­ber 8720009. All versions are classified as Class I laser products per IEC
‡
60825-1:1993.
CAUTION: Use of controls, adjustments, and procedures other than those specified herein may result in
hazardous laser radiation exposure.

This product complies with 21 CFR 1040.10 and 1040.11.

8.8 µm/125 µm single-mode pigtail with 900 µm tight bu ffer jacket and connector. Wa v el ength = 1.3 µm, 1.5 µm. Maximum power = 1.6 mW. Product is not shipped with power suppl y. Because of size constraints, laser safety labeling is not affixed to the module but is attached t o the outside of the shipping carton.
NOTICE
Unterminated optical connectors can emit lase r r adiation.
Do not view with optical instruments.

Electromagnetic Emissions and Immunity

The TA16 transponder will be tested against CENELEC EN50 081 part 1 and pa rt 2, FCC 15, Class B limits for emissions.
The TA16 transponder will be tested against CENELEC EN50 082 part 1 immunity requirements.
‡ IEC i s a registered tradem a r k of The In terna tional Electrotec hn ical Commissio n.
26
Agere Systems Inc.
Data Sheet TA16-Type 2.5 Gbits/s Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demulitplexer

Outline Diagram

Dimensions are in inches and (millimeters).

0.50 (12.7)
3.600
2.600
(66.04)
(91.44)
TRANSMITTER
RECEIVER
0.28 (7.11)
(16.51)
0.65
CL
0.380
(9.65)
PIN 1
(33.02)
0.500
(12.70)
(11.43)
0.45
(11.43)
1.30
0.450
0.30
(7.62)
0.92
(22.37)
(11.43)
0.45
1.50
(38.10)
1.80
(45.72)
1.840
(46.74)
160-PIN JAE CONNECTOR
MAT’G P/N WR -160PB-VF50- A3
1.5 (38.1)
0.22 (5.59)
34.5 (875) ± 43.0 (1100)
MAX
TX
RX
MOUNTING HOLES (3 PLACES) M2.5 x 0.45 (METRIC) 2 mm MAXIMUM LENGTH INTO PACKAGE
0.75
(19.05)
Agere Systems Inc.
1-1012(F).d
27
TA16-Type 2.5 Gbits/s Transponder with Data Sheet 16-Chann el 155 Mb its/s Multiple x er/D e m u litp le xer March 2001

Ordering Information

ORDER CODE: 16 XX X XXTA ––– BASIC PART NUMBER STM LEVEL
16 = STM-16 (SONET OC-48) APPLICATION
N1 = I-16, 1310 nm, intraoffice/(SONET short reach) S1 = S-16.1, 1310 nm, short hauL (SONET IR-1) S2 = S-16.2, 1550 nm, short haul (SONET IR-2) L1 = L-16.1, 1310 nm, long hauL (SONET LR-1) L2 = L-16.2, 1550 nm, long haul (SONET LR-2)
* Other co nnectors may be m ade available.

Table 11. Ordering Information

Code Application Connector Comcode
TA16N1CAA 1310 nm, Intraoffice SC 108440066
TA16N1FAA 1310 nm, Intraoffice FC/PC 108440074
TA16S1CAA 1310 nm, Sh ort Haul SC 108432907
TA16S1FAA 1310 nm, Short Haul FC/PC 108432915
TA16S2CAA 1550 nm, Sh ort Haul SC 108432923
TA16S2FAA 1550 nm, Short Haul FC/PC 108432931
TA16L1CAA 1310 nm, Long Haul SC 108432865
TA16L1FAA 1310 nm, Long Haul FC/PC 108432873
TA16L2CAA 1550 nm, Long Haul SC 108432881
TA16L2FAA 1550 nm, Long Haul FC/PC 108432899
OPTIONS
CONNECTOR* C = SC
F = FC

Related Product Information

Table 12. Related Product Information

Description Document Number
Using the Lucent Technologies Transponder Test Board Application Note AP00-017OPTO
For additional information, contact your Agere Systems Accou nt Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc ., 555 Uni on Boulevard , Room 30L-15P- BA, A llentown, PA 18109-3286
ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright © 2001 Agere Systems Inc. All Right s Reserv ed Printed in U.S.A.
March 20 01 DS01-119OPTO (Replaces DS00-259OPTO)
1-800-372-2447, FAX 610-712-4 106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)
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