Lucent Technologies Inc T8208-BAL-DB Datasheet

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Advance Data Sheet

September 2001

CelXpres

T8208

ATM Interconnect

1 Product Overview

1.1 Features

■ OC-12 data throughput on UTOPIA (16-bit)

(independently on RX and TX UTOPIA)

■ Shared UTOPIA mode

■ UTOPIA Level 1 and 2 (8-bit/16-bit) cell-level

handshake interface (ATM or PHY layers)

■ Multi-PHY (MPHY) operation

■ Programmable ATM layer supports up to 64 PHY

ports

■ Egress SDRAM buffer support to extend UTOPIA

output priority queues for 32K to 512K cells:

— 128 queues configurable up to four queues per

PHY with programmable size s

— Programmable number of UTOPIA output

queues with four levels of priority

■ Support of ATM traffic management via partial

packet discard (PPD), forward explicit congestion notification (FECN), and the cell loss priority (CLP) bit

■ Programmable slew rate GTL+ I/O:

— Programmable as bus arbiter — 1.7 Gbits/s cell bus operation

■ Flexible per port cell counters

■ Cell header insertion with virtual path identifier

(VPI) and virtual channel identifier (VCI) translation via external SRAM (up to 64K entries)

■ Support of network node interface (NNI) and user

network interface (UNI) header types with optional generic flow-control (GFC) insertion

■ Optional sourcing of cell bus clocks from device

■ LUT bypass option

■ TX UTOPIA cell buffer increased to 256 cells for

better queue management with SDRAM queue bypass option

■ Ability for cell bus arbiter to mask devices on the

cell bus

■ Ability to modify cell bus priority based on RX PHY

FIFO thresholds

■ Programmable priority for control/data cells trans-

mission onto cell bus

■ Microprocessor access to all headers of control

cell

■ Ability to clear counters on read

■ Simplified looping to any system device with a sin-

gle register programming

■ UTOPIA clock sourcing with additional settings

■ Programmable operations and maintenance and

resource management (OAM/RM) cell routing

■ Support of multicast and broadcast cells per PHY

■ Optional monitoring of misrouted cells

■ Counters for dropped cells per queue

■ Digital loopback before cell bus

■ Microprocessor interface, supporting both

Motor-

ola

and

Intel

modes (multiplexed and nonmul ti-

plexed)

■ Control cell transmission and re ception through

microprocessor port

■ Single 3.3 V power supply

■ 3.3 V TTL I/O (5 V tolerant)

■ 272-pin plastic ball grid array (PBGA) package

■ Industrial temperature range (–40 °C to +85 °C)

■ Hot insertion capability

■ Eight GPIO pins

■ JTAG support

■ Compatible with

Transwitch CellBus

1.2 Applications

■ Asymmetric digital subscriber line (ADSL) digital

subscriber line access multiplexers (DSLAMs)

■ Access gateways

■ Access multiplexers/concentrators

■ Multiservice platforms

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T8208

Table of Contents

Contents Page

1 Product Overview................................................................................................................................................1

1.1 Features....................................................................................................................................................1

1.2 Applications...............................................................................................................................................1

1.3 Description ................................................................................................................................................9

1.4 Conventions ............................................................................................................................................12

1.5 Glossary..................................................................................................................................................13

2 Pinout................................................................................................................................................................14

3 Powerup/Reset Sequence ................................................................................................................................22

4 Hot Insertion.... ....... ............................................. ............................................. ................................ ....... ...... ....23

5 PLL Configuration .............................................................................................................................................24

6 Microprocessor Interface ..................................................................................................................................25

6.1 Microprocessor Interface Configuration ..................................................................................................25

6.2 Microprocessor Interrupts........................................................................................................................25

6.3 Accessing the

CelXpres

T8208 via Microprocessor Interface.................................................................25

6.3.1 Accessing the Extended Memory Registers...............................................................................26

6.3.1.1 Extended Memory Writes.............................................................................................26

6.3.1.2 Extended Memory Reads.............................................................................................26

6.3.2

CelXpres

T8208 Access Performance .......................................................................................27

7 General-Purpose I/O (GPIO) ............................................................................................................................28

8 Look-Up Table ..................................................................................................................................................29

8.1 Look-Up Table RAM................................................................................................................................29

8.2 Organization............................................................................................................................................30

8.3 Look-Up Procedure .................................................................................................................................35

8.4 Extended Records...................................................................................................................................38

8.5 Diagnostics..............................................................................................................................................42

8.6 Setup.......................................................................................................................................................42

8.7 LUT Bypass.............................................................................................................................................42

9 UTOPIA Interface..............................................................................................................................................43

9.1 Incoming UTOPIA Cell Interface.............................................................................................................44

9.1.1 Incoming PHY Mode (Cells Received by T8208).......................................................................44

9.1.2 Incoming ATM Mode (Cells Received by T8208).......................................................................44

9.2 Outgoing UTOPIA Cell Interface.............................................................................................................45

9.2.1 Outgoing PHY Mode (Cells Sent by T8208)...............................................................................45

9.2.2 Outgoing ATM Mode (Cells Sent by T8208) ..............................................................................46

9.3 Counters..................................................................................................................................................48

9.3.1 Dropped Cell Counters...............................................................................................................49

9.4 55-Byte UTOPIA Mode............................................................................................................................49

9.5 Shared UTOPIA Mode ............................................................................................................................50

9.6 UTOPIA Pin Modes.................................................................................................................................52

9.6.1 UTOPIA Pin Modes for 8-Bit UTOPIA Operation .......................................................................52

9.6.2 UTOPIA Pin Modes for 16-Bit UTOPIA Operation .....................................................................56

9.7 UTOPIA Clocking ....................................................................................................................................58

9.8 Option for Counters to Clear on Read.....................................................................................................58

10 Cell Bus Interface..............................................................................................................................................59

10.1 General Architecture ...............................................................................................................................59

10.2 Cell Bus Frames......................................................................................................................................61

10.3 Cell Bus Routing Headers.......................................................................................................................64

10.3.1 Control Cells...............................................................................................................................65

10.3.2 Data Cells...................................................................................................................................65

10.3.3 Loopback Cells...........................................................................................................................66

10.3.4 Multicast Routing...... ....... ...... ....... ...... ....... ...... ....... ...... ...... ....... ............................................. ....66

10.3.5 Broadcast Routing......................................................................................................................67

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Table of Contents (continued)

Contents Page

10.4 Cell Bus Arbitration.................................................................................................................................67

10.5 Cell Bus Monitoring.................................................................................................................................68

10.6 GTL+ Logic .............................................................................................................................................68

10.7 Cell Bus Write and Read Clocks.............................................................................................................69

10.8 Modify Cell Bus Request Priority Based on RX PHY FIFO Threshold....................................................70

10.9 Digital Loopback Before Cell Bus ...........................................................................................................70

11 SDRAM Interface..............................................................................................................................................71

11.1 Memory Configuration.............................................................................................................................71

11.2 Powerup Sequence.................................................................................................................................71

11.3 SDRAM Interface Timing ........................................................................................................................72

11.4 Queuing ..................................................................................................................................................73

11.5 SDRAM Refresh .....................................................................................................................................80

11.6 SDRAM Throughput................................................................................................................................81

12 Traffic Management.................. ...... ....... ...... ............................................. ................................. ...... ....... ...... ....82

12.1 Cell Loss Priority (CLP)...........................................................................................................................82

12.2 Forward Explicit Congestion Notification (FECN) ...................................................................................82

12.3 Partial Packet Discard (PPD)..................................................................................................................83

13 JTAG Test Access Port ....................................................................................................................................84

13.1 Instruction Register......... ...... ....... ...... ....... ...... ....... ............................................. ....................................84

13.2 Boundary-Scan Register.........................................................................................................................85

14 Registers...........................................................................................................................................................88

14.1 Register Types........................................................................................................................................88

14.2 Direct Memory Access Registers............................................................................................................92

14.2.1 Little-Endian Format (big_end = 0) for Extended Memory Access Registers 30h—37h............97

14.2.2 Big-Endian Format (big_end = 1) for Extended Memory Access Registers 30h—37h..............99

14.2.3 General-Purpose I/O Control Registers...................................................................................101

14.2.4 Control Cells ............................................................................................................................102

14.2.5 Multicast Memories ..................................................................................................................103

14.3 Extended Memory Registers.................................................................................................................103

14.3.1 Main Registers.........................................................................................................................103

14.3.2 UTOPIA Registers ...................................................................................................................125

14.3.2.1 TX UTOPIA Configuration .........................................................................................130

14.3.2.2 TX UTOPIA Monitoring..............................................................................................175

14.3.2.3 RX UTOPIA Count Monitoring ...................................................................................176

14.3.2.4 RX UTOPIA Configuration Monitoring .......................................................................177

14.3.3 SDRAM Registers....................................................................................................................179

14.3.3.1 SDRAM Control Memory ...........................................................................................187

14.3.4 Various Internal Memories .............................................................. ....... ...... ....... ...... ...............190

14.3.4.1 Control Cell Memories ...............................................................................................190

14.3.4.2 Multicast Number Memories ......................................................................................191

14.3.4.3 PPD State Memory.............. ....... ...... ...... ....... ...... .............................................. ........193

14.3.5 Dropped Cell Count .................................................................................................................194

14.3.6 External Memories...................................................................................................................197

14.3.6.1 Look-Up Translation Memory ....................................................................................197

14.3.6.2 SDRAM Buffer Memory .............................................................................................197

15 Absolute Maximum Ratings............................................................................................................................198

16 Recommended Operating Conditions.............................................................................................................198

17 Handling Precautions......................................................................................................................................198

18 Electrical Requirements and Characteristics..................................................................................................199

18.1 Crystal Information................................................................................................................................199

18.2 dc Electrical Characteristics..................................................................................................................200

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Table of Contents (continued)

Contents Page

19 Timing Requirements.....................................................................................................................................201

19.1 Microprocessor Interface Timing..........................................................................................................202

19.2 UTOPIA Timing ....................................................................................................................................208

19.3 External LUT Memory Timing...............................................................................................................209

19.4 Cell Bus Timing ....................................................................................................................................211

19.5 SDRAM Interface Timing......................................................................................................................212

20 Outline Diagram.............................................................................................................................................213

21 Ordering Information......................................................................................................................................214

List of Figures

Figure Page

Figure 1. Functional Block Diagram ....................................................................................................................... 10

Figure 2. Dual Bus Implementatio n ........................................ ...... ....... ...... ...... ....... ................................................ 11

Figure 3. 272-Pin PBGA—Top View ...................................................................................................................... 21

Figure 4. Translation RAM Memory Map—8-Byte Records ................................................................................... 31

Figure 5. Translation Record Types—8-Byte Records........................................................................................... 32

Figure 6. Translation RAM Flow Diagram .............................................................................................................. 37

Figure 7. Translation Record Types—Extended Mode .......................................................................................... 39

Figure 8. Translation RAM Memory Map—Extended Mode................................................................................... 40

Figure 9. Queue Priority Multiplexing ..................................................................................................................... 48

Figure 10. TX UTOPIA Cell Handling..................................................................................................................... 49

Figure 11. TX UTOPIA Bus Sharing for 8-Bit UTOPIA Mode................................................................................. 51

Figure 12. TX UTOPIA Bus Sharing for 16-Bit UTOPIA Mode................................................................................52

Figure 13. Cell Bus Frame Format (Bit Positions for 16-User Mode)..................................................................... 61

Figure 14. Cell Bus Frame Format (Bit Positions for 32-User Mode)..................................................................... 62

Figure 15. Cell Bus Routing Headers..................................................................................................................... 64

Figure 16. GTL+ External Circuitry......................................................................................................................... 68

Figure 17. SDRAM Timing Parameters.................................................................................................................. 72

Figure 18. Crystal ................................................................................................................................................. 199

Figure 19. Negative Resistance Plot .................................................................................................................... 199

Figure 20. Nonmultiplexed

Intel

Mode Write Access Timing................................................................................ 202

Figure 21. Nonmultiplexed

Intel

Mode Read Access Timing................................................................................ 202

Figure 22.

Motorola

Mode Write Access Timing................................................................................................... 204

Figure 23.

Motorola

Mode Read Access Timing .................................................................................................. 204

Figure 24. Multiplexed

Intel

Mode Write Access Timing....................................................................................... 206

Figure 25. Multiplexed

Intel

Mode Read Access Timing ...................................................................................... 206

Figure 26. External LUT Memory Read Timing (cyc_per_acc = 2 and cyc_per_acc = 3).................................... 209

Figure 27. External LUT Memory Write Timing (cyc_per_acc = 2 and cyc_per_acc = 3).................................... 209

Figure 28. Cell Bus Timing................................................................................................................................... 211

Figure 29. SDRAM Interface Timing..................................................................................................................... 212

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List of Tables

Table Page

Table 1. UTOPIA Pins ..............................................................................................................................................14

Table 2. Shared UTOPIA Pins ..................................................................................................................................15

Table 3. Cell Bus Pins ..............................................................................................................................................16

Table 4. SDRAM Interface Pins ................................................................................................................................17

Table 5. Microprocessor Interface Pins .................................................................................................................... 18

Table 6. Translation SRAM Interface .........................................................................................................................19

Table 7. JTAG Pins ...................................................................................................................................................19

Table 8. General-Purpose Pins ................................................................................................................................20

Table 9. Power Pins ..................................................................................................................................................20

Table 10. Loop Filter Register Settings .....................................................................................................................24

Table 11. Access Times ...........................................................................................................................................27

Table 12. Active and Ignore Truth Table ..................................................................................................................33

Table 13. VPI Value Truth Table ..............................................................................................................................34

Table 14. OAM Routing Control Truth Table ............................................................................................................3 4

Table 15. F5 Translation Record Addresses Table—8-Byte Records .......................................................................35

Table 16. F5 Translation Record Addresses Table—Extended Mode ......................................................................41

Table 17. Pin Configuration for 8-Bit UTOPIA ..........................................................................................................53

Table 18. Pin Configuration for 16-Bit UTOPIA ................................................................................... ..................... 57

Table 19. Supported Memory Configurations ...........................................................................................................71

Table 20.

Queue Organization and Port Group Address/Priority Bits for 32 Ports in 8-Bit UTOPIA Mode ............74

Table 21.

Queue Organization and Port Group Address/Priority Bits for 64 Ports in 8-Bit UTOPIA Mode and

32 Ports in 16-Bit UTOPIA Mode

.............................................................................................................. 77

Table 22. Instruction Register ...................................................................................................................................8 4

Table 23. Boundary-Scan Register Descriptions .............................................................................................. ........ 85

Table 24. Register Map..............................................................................................................................................88

Table 25. Identification 0 (IDNT0) (00h) ...................................................................................................................9 2

Table 26. Identification 1 (IDNT1) (01h) ....................................................................................................................9 2

Table 27. Identification 2 (IDNT2) (02h) ...................................................................................................................9 2

Table 28. Direct Configuration/Control Register (DCCR) (28h) ................................................................................. 93

Table 29. Interrupt Service Request (ISREQ) (29h) .................................................................................................94

Table 30. mclk PLL Configuration 0 (MPLLCF0) (2Ah) .................................................................................... ........ 94

Table 31. mclk PLL Configuration 1 (MPLLCF1) (2Bh) ............................................................................................95

Table 32. GTL+ Slew Rate Configuration (GTLSRCF) (2Eh) ....................................................................................95

Table 33.

GTL+ Control (GTLCNTRL) (2Fh)...........................................................................................................96

Table 34. Extended Memory Address 1 (Little Endian) (EMA1_LE) (30h) ................................................................97

Table 35. Extended Memory Address 2 (Little Endian) (EMA2_LE) (31h) ................................................................97

Table 36. Extended Memory Address 3 (Little Endian) (EMA3_LE) (32h) ................................................................97

Table 37. Extended Memory Address 4 (Little Endian) (EMA4_LE) (33h) ................................................................97

Table 38. Extended Memory Access (Little Endian) (EMA_LE) (34h) .......................................................................97

Table 39. Extended Memory Data Low (Little Endian) (EMDL_LE) (36h) .................................................................98

Table 40. Extended Memory Data High (Little Endian) (EMDH_LE) (37h) ................................................................98

Table 41. Extended Memory Address 4 (Big Endian) (EMA4_BE) (30h) ......................................... ... ......................99

Table 42. Extended Memory Address 3 (Big Endian) (EMA3_BE) (31h) ......................................... ... ......................99

Table 43. Extended Memory Address 2 (Big Endian) (EMA2_BE) (32h) ......................................... ... ......................99

Table 44. Extended Memory Address 1 (Big Endian) (EMA1_BE) (33h) ......................................... ... ......................99

Table 45. Extended Memory Access (Big Endian) (EMA_BE) (34h) .......................................................................100

Table 46. Extended Memory Data High (Big Endian) (EMDH_BE) (36h) ................................................................100

Table 47. Extended Memory Data Low (Big Endian) (EMDL_BE) (37h) .................................................................100

Table 48. GPIO Output Enable (GPIO_OE) (39h) ...................................................................................................101

Table 49. GPIO Output Value (GPIO_OV) (3Bh) .................................................................................................... 101

Table 50. GPIO Input Value (GPIO_IV) (3Dh) .........................................................................................................101

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List of Tables (continued)

Table Page

Table 51. Control Cell Receive Direct Memory (CCRXDM) (5Ch to 93h) ................................................................102

Table 52. Control Cell Transmit Direct Memory (CCTXDM) (A0h to D7h) ...............................................................102

Table 53. PHY Port 0 and Control Cells Multicast Direct Memory (PP0MDM) (E0h to FFh) ...................................103

Table 54. Main Configuration 1 (MCF1) (0100h) ......................................................................................................104

Table 55. Main Interrupt Status 1 (MIS1) (0102h) ...................................................................................................105

Table 56. Main Interrupt Enable 1 (MIE1) (0104h) ..................................................................................................106

Table 57. TX UTOPIA Clock Configuration (TXUCCF) (010Ch) ..............................................................................107

Table 58. RX UTOPIA Clock Configuration (RXUCCF) (010Eh) .............................................................................108

Table 59. Main Configuration/Control (MCFCT) (0110h) .........................................................................................109

Table 60. Main Configuration 2 (MCF2) (0112h) ......................................................................................................110

Table 61. UTOPIA Configuration (UCF) (0114h) ....................................................................................................113

Table 62. Main Configuration 3 (MCF3) (0116h) .....................................................................................................113

Table 63. UTOPIA Configuration 5 (UCF5) (0118h) ...............................................................................................114

Table 64. UTOPIA Configuration 4 (UCF4) (011Ah) ...............................................................................................114

Table 65. UTOPIA Configuration 3 (UCF3) (011Ch) ...............................................................................................114

Table 66. UTOPIA Configuration 2 (UCF2) (011Eh) ...............................................................................................114

Table 67. Extended LUT Control (ELUTCN) (0120h) ..............................................................................................115

Table 68. Generated Cell Bus Clocks Control Register (GCBCCR) (0122h) ...........................................................116

Table 69. RX PHY FIFO Thresholds to Change Cell Bus Request Priority (RXPFTCRP) (0126h) ........................118

Table 70. Enable Request on Upper Backplane Address (ERUB) (012Ch) ............................................................119

Table 71. Enable Request on Lower Backplane Address (ERLB) (012Ch) ............................................................ 119

Table 72. Cell Bus Configuration/Status (CBCFS) (0130h) ....................................................................................120

Table 73. Main Interrupt Status 2 (MIS2) (0132h) ....................................................................................................121

Table 74. Main Interrupt Enable 2 (MIE2) (0134h) ...................................................................................................122

Table 75. Loopback (LB) (0136h) ..................... ................................. ........................................................ .............122

Table 76. Extended LUT Configuration (ELUTCF) (0138h) ....................................................................................122

Table 77. Misrouted Cell LUT 3 (MLUT3) (013Ch) ................................................................................................. 123

Table 78. Misrouted Cell LUT 2 (MLUT2) (013Eh) .................................................................................................. 123

Table 79. Misrouted Cell LUT 1 (MLUT1) (0140h) ..................................................................................................123

Table 80. Misrouted Cell LUT 0 (MLUT0) (0142h) ..................................................................................................123

Table 81. Misrouted Cell LUT 4 (MLUT4) (0144h) ..................................................................................................124

Table 82. Misrouted Cell Header High (MCHH) (0146h) ......................................................................................... 124

Table 83. Misrouted Cell Header Low (MCHL) (0148h) .......................................................................................... 124

Table 84. HEC Interrupt Status 3 (HIS3) (0300h) ................................................................................................... 125

Table 85. HEC Interrupt Status 2 (HIS2) (0302h) .................................................................................................... 125

Table 86. HEC Interrupt Status 1 (HIS1) (0304h) ...................................................................................................125

Table 87. HEC Interrupt Status 0 (HIS0) (0306h) ...................................................................................................125

Table 88. HEC Interrupt Enable 3 (HIE3) (0308h) ..................................................................................................126

Table 89. HEC Interrupt Enable 2 (HIE2) (030Ah) ..................................................................................................126

Table 90. HEC Interrupt Enable 1 (HIE1) (030Ch) ..................................................................................................126

Table 91. HEC Interrupt Enable 0 (HIE0) (030Eh) ..................................................................................................126

Table 92. LUT Interrupt Service Request 3 (LUTISR3) (0310h) .............................................................................127

Table 93. LUT Interrupt Service Request 2 (LUTISR2) (0312h) .............................................................................127

Table 94. LUT Interrupt Service Request 1 (LUTISR1) (0314Ch) ...........................................................................127

Table 95. LUT Interrupt Service Request 0 (LUTISR0) (0316h) .............................................................................127

Table 96. LUT X Configuration/Status (LUTXCFS) (0320h to 039Eh) ....................................................................128

Table 97. Master Queue 7 (MQ7) (0150h)............................................................................................................... 130

Table 98. Master Queue 6 (MQ6) (0152h)............................................................................................................... 130

Table 99. Master Queue 5 (MQ5) (0154h)............................................................................................................... 130

Table 100. Master Queue 4 (MQ4) (0156h) ................................. ................................. .......................... .................131

Table 101. Master Queue 3 (MQ3) (0158h) ................................. ................................. .......................... .................131

Table 102. Master Queue 2 (MQ2) (015Ah) ....................... ................................. .....................................................131

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List of Tables (continued)

Table Page

Table 103. Master Queue 1 (MQ1) (015Ch) ............................................................................................................132

Table 104. Master Queue 0 (MQ0) (015Eh) ............................................................................................................132

Table 105. Slave Queue 7 (SQ7) (0160h) ..............................................................................................................133

Table 106. Slave Queue 6 (SQ6) (0162h) ..............................................................................................................133

Table 107. Slave Queue 5 (SQ5) (0164h) ..............................................................................................................134

Table 108. Slave Queue 4 (SQ4) (0166h) ..............................................................................................................134

Table 109. Slave Queue 3 (SQ3) (0168h) ..............................................................................................................134

Table 110. Slave Queue 2 (SQ2) (016Ah) ..............................................................................................................135

Table 111. Slave Queue 1 (SQ1) (016Ch) .............................................................................................................135

Table 112. Slave Queue 0 (SQ0) (016Eh) ..............................................................................................................135

Table 113. TX PHY FIFO Routing 7 (TXPFR7) (0170h) .........................................................................................136

Table 114. TX PHY FIFO Routing 6 (TXPFR6) (0172h) .........................................................................................137

Table 115. TX PHY FIFO Routing 5 (TXPFR5) (0174h) .........................................................................................138

Table 116. TX PHY FIFO Routing 4 (TXPFR4) (0176h) .........................................................................................139

Table 117. TX PHY FIFO Routing 3 (TXPFR3) (0178h) .........................................................................................140

Table 118. TX PHY FIFO Routing 2 (TXPFR2) (017Ah) ........................................................................................141

Table 119. TX PHY FIFO Routing 1 (TXPFR1) (017Ch) ........................................................................................142

Table 120. TX PHY FIFO Routing 0 (TXPFR0) (017Eh) ........................................................................................143

Table 121. Global Bypass SDRAM Control Register (GBSCR) (01B0h) ................................................................144

Table 122.

Bypass SDRAM Service Request Register (BSSR) (01BEh) .................. ................................. ..........145

Table 123.

Bypass SDRAM Queue Interrupt Status Register 0 (BSQISR0) (01C0h) ..........................................147

Table 124.

Bypass SDRAM Queue Interrupt Status Register 1 (BSQISR1) (01C2h) ..........................................148

Table 125.

Bypass SDRAM Queue Interrupt Status Register 2 (BSQISR2) (01C4h) ..........................................149

Table 126.

Bypass SDRAM Queue Interrupt Status Register 3 (BSQIS30) (01C6h) ..........................................150

Table 127.

Bypass SDRAM Queue Interrupt Status Register 4 (BSQISR4) (01C8h) ..........................................151

Table 128.

Bypass SDRAM Queue Interrupt Status Register 5 (BSQISR5) (01CAh) ...................... ....................152

Table 129.

Bypass SDRAM Queue Interrupt Status Register 6 (BSQISR6) (01CCh) .........................................153

Table 130.

Bypass SDRAM Queue Interrupt Status Register 7 (BSQISR7) (01CEh) ...................... ....................154

Table 131.

Bypass SDRAM Queue Interrupt Status Register 8 (BSQISR8) (01D0h) ..........................................155

Table 132.

Bypass SDRAM Queue Interrupt Status Register 9 (BSQISR9) (01D2h) ..........................................156

Table 133.

Bypass SDRAM Queue Interrupt Status Register 10 (BSQISR10) (01D4h) ......................................157

Table 134.

Bypass SDRAM Queue Interrupt Status Register 11 (BSQISR11) (01D6h) ......................................158

Table 135.

Bypass SDRAM Queue Interrupt Status Register 12 (BSQISR12) (01D8h) ......................................159

Table 136.

Bypass SDRAM Queue Interrupt Status Register 13 (BSQISR13) (01DAh) .....................................160

Table 137.

Bypass SDRAM Queue Interrupt Status Register 14 (BSQISR14) (01DCh) .....................................161

Table 138.

Bypass SDRAM Queue Interrupt Status Register 15 (BSQISR15) (01DEh) .....................................162

Table 139. Routing Information 1 (RI1) (0200h) .....................................................................................................163

Table 140. Routing Information 2 (RI2) (0202h) .....................................................................................................164

Table 141. Routing Information 3 (RI3) (0204h) .....................................................................................................165

Table 142. PPD Information 1 (PPDI1) (0206h) .....................................................................................................166

Table 143. PPD Information 2 (PPDI2) (0208h) .....................................................................................................167

Table 144. PPD Information 3 (PPDI3) (020Ah) ......................................................................................................168

Table 145. PPD Information 4 (PPDI4) (020Ch) .....................................................................................................169

Table 146. PPD Information 5 (PPDI5) (020Eh) .....................................................................................................170

Table 147. PPD Information 6 (PPDI6) (0210h) .....................................................................................................171

Table 148. PPD Information 7 (PPDI7) (0212h) .....................................................................................................172

Table 149. Routing Information 4 (RI4) (0214h) .....................................................................................................173

Table 150. PPD Memory Write (PPDMW) (0418h) ................................................................................................174

Table 151. PHY Port X Transmit Count Structure (PPXTXCNT) (0600h to 06FEh) ................................................175

Table 152. PHY Port X Receive Count Structure (PPXRXCNT) (4000h to 40FEh) ...............................................176

Table 153.

PHY Port X Configuration Structure (PPXCF) (4200h to 42FEh) .......................................................177

Table 154. SDRAM Control (SCT) (0400h) ............................................................................................................179

Table 155. SDRAM Interrupt Status (SIS) (0402h) .................................................................................................179

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List of Tables (continued)

Tables Pages

Table 156. SDRAM Interrupt Enable (SIE) (0404h) ................................................................................................179

Table 157. SDRAM Configuration (SCF) (0408h) ...................................................................................................180

Table 158. Refresh (RFRSH) (0410h) .....................................................................................................................181

Table 159. Refresh Lateness (RFRSHL) (0412h) ...................................................................................................181

Table 160. Idle State 1 (IS1) (0420h) ......................................................................................................................181

Table 161. Idle State 2 (IS2) (0422h) ......................................................................................................................181

Table 162. Manual Access State 1 (MAS1) (0424h) ...............................................................................................182

Table 163. Manual Access State 2 (MAS2) (0426h) ...............................................................................................182

Table 164. SDRAM Interrupt Service Request 7 (SISR7) (0430h) .........................................................................183

Table 165. SDRAM Interrupt Service Request 6 (SISR6) (0432h) .........................................................................183

Table 166. SDRAM Interrupt Service Request 5 (SISR5) (0434h) .........................................................................183

Table 167. SDRAM Interrupt Service Request 4 (SISR4) (0436h) ......................................................................... 183

Table 168. SDRAM Interrupt Service Request 3 (SISR3) (0438h) .........................................................................184

Table 169. SDRAM Interrupt Service Request 2 (SISR2) (043Ah) .........................................................................184

Table 170. SDRAM Interrupt Service Request 1 (SISR1) (043Ch) .........................................................................184

Table 171. SDRAM Interrupt Service Request 0 (SISR0) (043Eh) .........................................................................184

Table 172. Queue X (QX) (0440h to 053Eh) ...........................................................................................................185

Table 173. Queue X Definition Structure (QXDEF) (2000h to 2FFEh) ....................................................................187

Table 174. Control Cell Receive Extended Memory (CCRXEM) (07FCh to 0832h) ................................................190

Table 175. Control Cell Transmit Extended Memory (CCTXEM) (0900h to 0936h) ................................................190

Table 176. PHY Port 0 and Control Cells Multicast Extended Memory (PP0ME M ) (0C0 0h to 0C1Eh) ...................191

Table 177. PHY Port X Multicast Memory (PPXMM) (0C20h to 0FFEh) .................................................................192

Table 178. PPD Memory (PPDM) (1000h to 13FEh) ..............................................................................................193

Table 179.

Queue X Dropped Cell Count (QXDCC) (3000h to 31FEh) .................................................................194

Table 180. Translation RAM Memory (TRAM) (100000h to 17FFFEh) ....................................................................197

Table 181. SDRAM (SDRAM) (2000000h to 3FFFFFEh) .......................................................................................197

Table 182. Maximum Rating Parameters and Values ..............................................................................................198

Table 183. Recommended Operating Conditions ..................................... ................................. .......................... ....1 98

Table 184. HBM ESD Threshold ............................... ...............................................................................................198

Table 185. Crystal Specifications ............................................................................................................................199

Table 186. External Clock Requirements ........................... ................................. ............................ .........................199

Table 187. dc Electrical Characteristics ..................................................................................................................200

Table 188. Input Clocks .................................................................................. .......................... ..............................201

Table 189. Output Clocks ........................................................................................................................................201

Table 190. Nonmultiplex ed

Intel

Mode Write Access Timing ................................ ................................. .................203

Table 191. Nonmultiplex ed

Intel

Mode Read Access Timing ..................................................................................203

Table 192.

Motorola

Mode Write Access Timing ................................ ................................. ................................ ....205

Table 193.

Motorola

Mode Read Access Timing .....................................................................................................205

Table 194. Multiplexed

Intel

Mode Write Access Timing .........................................................................................207

Table 195. Multiplexed

Intel

Mode Read Access Timing .........................................................................................207

Table 196. TX UTOPIA Timing (70 pF Load on Outputs) .......................................................................................208

Table 197. RX UTOPIA Timing (70 pF Load on Outputs) .......................................................................................208

Table 198. External LUT Memory Read Timing (cyc_per_acc = 2) ........................................................................210

Table 199. External LUT Memory Read Timing (cyc_per_acc = 3) ........................................................................210

Table 200. External LUT Memory Write Timing (cyc_per_acc = 2) ........................................................................210

Table 201. External LUT Memory Write Timing (cyc_per_acc = 3) ........................................................................210

Table 202. Cell Bus Timing ........................ ................................. ................................. .......................... .................211

Table 203. SDRAM Interface Timing .......................................................................................................................212

Agere Systems Inc. 9

Advance Data Sheet September 2001

ATM Interconnect

CelXpres

T8208

1 Product Overview (continued)

1.3 Description

The

CelXpres

T8208 device integrates all of the required functionality to transport ATM cells across a backplane architecture with high-speed cell traffic exceeding 1.5 Gbits/s to a maximum of 32 destinations. The management of multiple service categories and monitoring of performance on ATM and PHY interfaces is incorporated in the

device’s functionality. Traffic delivery to multi-PHYs (MPHYs) is managed through the UTOPIA interface. The T8208 device meets the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1,

Version 2.01 and Level 2, Version 1.0 specifications for cell-level handshake and MPHY data path operation with rates up to 635 Mbits/s. The T8208 supports the required MPHY operation as described in Sections 4.1 and 4.2 of the ATM Forum’s level 2 specification. The T8208 supports MPHY operation with one transmit cell available (TxCLAV) signal and one receive cell available (RxCLAV) signal for up to 16 PHY ports for an 8-bit UTOPIA 2 interface configuration. With four transmit cells available/enable (TxCLAV/Enb*) pairs of signals and receive cell available/enable (RxCLAV/Enb*) pairs of signals, 64 MPHYs can be supported. For a 16-bit UTOPIA 2 interface configuration, the T8208 supports MPHY operation with one transmit cell available (TxCLAV) signal and one receive cell available (RxCLAV) signal for up to 8 PHY ports. With four transmit cell available (TxCLAV/Enb*) signals and four receive cell available (RxCLAV/Enb*) signals, 32 MPHYs can be supported in 16-bit UTOPIA 2 interface configuration. In addition to the required UTOPIA signals, the optional transmit parity (TxPRTY) and receive parity (RxPRTY) signals are provided.

The T8208 may be configured as an ATM or PHY level device providing cell routing between UTOPIA and a 32-bit wide cell bus. In addition to the 32 data signals, the bus has the following signals:

■ Read clock

■ Write clock

■ Frame sync

■ Acknowledge

AT M cells arriving from the UTOPIA interface may get VPI and VCI translation and routing information from a lookup table in external SRAM. An external synchronous dynamic random access memory (SDRAM) is used to extend the buffering for ATM cells destined for the UTOPIA interface. This external SDRAM may be partitioned into four or less independently sized queues per PHY for a configuration of 32 MPHYs and two queues per PHY or a programmable number of queues per PHY for a configuration of 64 MPHYs. The four queues may be used to support quality of service (QoS) by directing different traffic categories to each queue. The number of cells per queue per PHY is programmable.

The

CelXpres

T8208 provides a shared UTOPIA mode, which allows two devices on different cell buses to share the same UTOPIA bus in ATM mode. Using a glueless interface, the two T8208 devices resolve queue priorities and arbitrate the use of the UTOPIA bus. This shared mode can be used to provide redundancy or increase UTOPIA traffic capacity by supporting traffic from multiple cell busses.

The

CelXpres

T8208 supports the transport of control and loopback cells with an external microprocessor. Control or loopback cells may be sent or received through the microprocessor interface. The 8-bit microprocessor interface may be configured to be

Motorola

Intel

compatible and is used to configure and monitor the device.

10 Agere Systems Inc.

Advance Data Sheet

September 2001

ATM Interconnect

CelXpres

T8208

1 Product Overview (continued)

5-7542d F

Figure 1. Functional Block Diagram

ONE OR TWO

32K TO 256K x 8

LOOK-UP

ENGINE

UTOPIA

INTERFACE

RX PHY

FIFO

(16 CELLS)

CONTROL CELL

TX FIFO (1 CELL)

LOOPBACK

FIFO

(1 CELL)

CONTROL CELL

RX FIFO

(16 CELLS)

TX PHY

FIFO

(256 CELLS)

SDRAM

INTERFACE

TX UTOPIA

1M TO 16M x 16

SDRAM

MICROPROCESSOR

INTERFACE

MICROPROCESSOR

CELL BUS

ARBITER

CELL BUS

MONITORING

CELL BUS

INTERFACE

CELL BUS

UTOPIA

INTERFACE

UTOPIA

(4 CELLS)

INPUT FIFO

(256 CELLS)

CELL BUFFER

(LUT) SRAMs

RX UTOPIA

FIFO

DIGITAL LOOPBACK

(4 CELLS)

CELL BUS

OUTPUT FIFO

(4 CELLS)

Agere Systems Inc. 11

Advance Data Sheet September 2001

ATM Interconnect

CelXpres

T8208

1 Product Overview (continued)

Figure 2 illustrates the use of the

CelXpres

T8208 in a system with dual backplane cell buses using shared UTOPIA mode. In this configuration, both T8208 devices on each card receive cells from the UTOPIA bus, and each device uses its translation table to determine if the cell should be transmitted on its backplane cell bus. In the egress direction, each T8208 device receives cells from its cell bus to transmit on the UTOPIA bus. MPHY arbitration and queue priorities are resolved using a six-wire interface between the two devices. Although a single ATM virtual connection is not typically established on both backplane cell buses simultaneously, no restrictions exist for a single PHY utilizing both backplane cell buses for different virtual connections supporting higher throughput from two bus interfaces. Redundant bus configurations can be supported in the event of a bus failure with T8208 devices by configuring one device to assume bus responsibility from the other.

0041b

Figure 2. Dual Bus Implementation

DOWNSTREAM

BUFFERING

UPSTREAM

TRANSLATION

UTOPIA

T8208

DOWNSTREAM

BUFFERING

UPSTREAM

TRANSLATION

UTOPIA

PHYs

T8208

BACKPLANE

BUS

DOWNSTREAM

BUFFERING

UPSTREAM

TRANSLATION

UTOPIA

T8208

DOWNSTREAM

BUFFERING

UPSTREAM

TRANSLATION

UTOPIA

PHYs

T8208

12 Agere Systems Inc.

Advance Data Sheet

September 2001

ATM Interconnect

CelXpres

T8208

1 Product Overview (continued)

1.4 Conventions

■ All numbers in this document are decimals unless otherwise specified.

■ Hexadecimal numbers can be identified by the ‘h’ suffix, e.g., A5h.

■ Binary numbers are either in double quotes for multiple bits or in single quotes for individual bits, e.g., “1001” and

‘0.’

■ A byte is 8 bits, a word is 16 bits, and a double word (dword) is 32 bits.

■ A binary value of ‘1’ is high, and a binary value of ‘0’ is low.

■ To clear is to change one or multiple bit values to ‘0.’

■ To set is to change one or multiple bit values to ‘1.’

■ All memory addresses are specified in hexadecimal.

■ Addresses are converted from bytes to words or double words using the little-endian format, unless otherwise

specified.

■ A signal name with a trailing asterisk is active-low, e.g., sd_we*.

■ Bits y to x will be designated bits (y:x).

Agere Systems Inc . 13

Advance Data Sheet September 2001

ATM Interconnect

CelXpres

T8208

1 Product Overview (continued)

1.5 Glossary

Bus Cell:

Major content of the cell bus frame consisting of 56 bytes, 4 bytes for routing options and 52 bytes for the ATM cell content, which excludes the HEC. The bus cell is preceded by the 4 bytes of request and followed by the 4 bytes of grant and parity information.

CLP: Cell loss priority. The CLP is a 1-bit field in the cell header that becomes set when the cell violates the negotiated quality of service parameters.

EFCI: Explicit forward congestion indication. The EFCI is a 1-bit field in the PTI field of the cell header that becomes set when the cell encounters congestion.

FECN: Forward explicit congestion notification. FECN is a method used by the network to signal to the destination when congestion is encountered. The EFCI bit is used to indicate the congestion.

GFC: Generic flow control. The GFC is a 4-bit field in the cell header that may be used by a UNI to support traffic and congestion control. Typically, this field is pro-

grammed to “0000” indicating that generic flow control is not sup

ported. GFC may be used in priority proto-

cols. Grant Section:

Last 4 bytes of the cell bus frame. The grant section occurs during the last clock cycle of the cell bus frame. During this cycle, the cell bus arbiter indicates which T8208 may transmit during the next bus cell unit of the cell bus frame. A parity vector is also transmitted during the grant section.

HEC: Header error control. The HEC is a 1-byte field in the cell header used for bit error detection and correction in the header.

NNI: Network node interface. The NNI is the interface between nodes in the public network.

OAM Cell: Operations and maintenance cell. An OAM cell carries local management infor mat ion .

PPD: Partial packet discard. PPD is a technique to relieve congestion. When one cell in a packet is lost, all remaining cells in the packet, except the last, are discarded.

PTI: Payload type identifier. The PTI is a 3-bit field in the cell header containing information about the type of data (user, OAM, or traffic management) and about encountered congestion.

QoS: Quality of service. Quality of service parameters define the performance requirements and characteristics for traffic on an assigned channel. Some parameters include cell loss ratio, cell transfer delay, cell delay variation, peak cell rate, and sustained cell rate.

Request Section: First 4 bytes of the cell bus frame. The request section occurs during the first clock cycle of the cell bus frame. During this cycle, 16 T8208 devices assert their transmission requests onto the cell bus.

RM: Resource management. RM is the local management of network resources.

RxCLAV: Receive cell available signal as described in the ATM

Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications.

RxENB: Receive enable signal as described in the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications.

TxCLAV: Transmit cell available signal as described in the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications.

TxENB: Transmit enable signal as described in the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications.

UNI: User network interface. The UNI is the interface between a private network node and a public network node.

VCI: Virtual channel identifier. The VCI is a 2-byte field in the cell header that identifies the virtual channel used by the cell.

VPI: Virtual path identifier. The VPI is an 8-bit field in the UNI cell header or a 12-bit field in the NNI cell header that identifies the virtual path of the cell.

14 Agere Systems Inc.

Advance Data Sheet

September 2001

ATM Interconnect

CelXpres

T8208

2 Pinout

This section defines the

CelXpres

T8208 pins. All TTL compatible inputs or I/O are 5 V tolerant. No GTL+ inputs or

I/O are 5 V tolerant.

Table 1. UTOPIA Pins

Symbol Ball Reset

Value

Type Name/Description

u_rxaddr[4:0] R2, P3, R1, P2, P1Z I/O RX UTOPIA Address Lines. 10 mA drive, TTL compatible I/O,

5 V tolerant.

u_rxdata[15:0] V4, W4, Y2, W3,

Y1, W2, V3, W1,

V2, U3, T4, V1,

U2, T3, U1, T2

—IRX UTOPIA Data Lines. TTL compatible input, 5 V tolerant.

u_rxclk T1 Z I/O RX UTOPIA Clock. 10 mA drive, TTL compatible I/O, 5 V tolerant.

u_rxsoc P4 — I RX UTOPIA Start of Cell (Active-High). TTL compatible input,

5 V tolerant.

u_rxclav[0] L4 Z I/O RX UTOPIA PHY 0 Cell Available (Active-High). Main RX cell

available in single PHY mode. 10 mA drive, TTL compatible I/O, 5 V tolerant. This pin has an internal 50 kΩ pull-up resistor.

u_rxclav[3:1] M3, M2, M1 — I RX UTOPIA Cell Available Lines (Active-High). TTL compatible

input, 5 V tolerant. These pins have an internal 50 kΩ pull-up resistor.

u_rxenb*[0] M4 Z I/O RX UTOPIA PHY 0 Enable (Active-Low). Main RX enable in sin-

gle PHY mode. 10 mA drive, TTL compatible I/O, 5 V tolerant.

u_rxenb*[3:1] N3, N2, N1 Z I/O RX UTOPIA PHY Enable Lines (Active-Low). 10 mA drive, TTL

compatible I/O, 5 V tolerant.

u_rxprty R3 — I RX UTOPIA Odd Parity. TTL compatible input, 5 V tolerant. This

pin has an internal 50 kΩ pull-up resistor.

u_txaddr[4:0] P17, R19, R20,

P18, P19

Z I/O TX UTOPIA Address Lines. 10 mA drive, TTL compatible I/O.

5 V tolerant.

u_txdata[15:0] Y18, U16, V17,

W18, Y19, V18,

W19, Y20, W20,

V19, U19, U18, T17, V20, U20,

T18

ZOTX UTOPIA Data Lines. 10 mA drive, TTL compatible output.

u_txclk R18 Z I/O TX UTOPIA Clock. 10 mA drive, TTL compatible I/O, 5 V tolerant.

u_txsoc T20 Z O TX UTOPIA Start of Cell (Active-High). 10 mA drive, TTL compat-

ible output.

u_txclav[0] M20 Z I/O TX UTOPIA PHY 0 Cell Available (Active-High). Main TX cell

available in single PHY mode. 10 mA drive, TTL compatible I/O. 5 V tolerant. This pin has an internal 50 kΩ pull-up resistor.

u_txclav[3:1] M17, M18, M19 — I TX UTOPIA Cell Available Lines (Active-High). TTL compatible

input, 5 V tolerant. These pins have an internal 50 kΩ pull-up resistor.

u_txenb*[0] N20 Z I/O TX UTOPIA PHY 0 Enable (Active-Low). Main TX enable in single

PHY mode. 10 mA drive, TTL compatible I/O, 5 V tolerant.

u_txenb*[3:1] P20, N18, N19 Z O TX UTOPIA Enable Lines (Active-Low). 10 mA drive, TTL com-

patible output.

u_txprty T19 Z O TX UTOPIA Odd Parity. 10 mA drive, TTL compatible output.

Agere Systems Inc. 15

Advance Data Sheet September 2001

ATM Interconnect

CelXpres

T8208

2 Pinout (continued)

T able 2. Shared UTOPIA Pins

Symbol Ball Reset

Value

Type Name/Description

u_shr_grant[1:0] W17, V16 1 I/O

Shared UTOPIA Grant.

Used for grant if device is shared. UTOPIA master to indicate approval of the requested cell transfer. 6 mA drive, TTL compatible I/O. These pins have an internal 50 kΩ pull-up resistor.

u_shr_req[3:0] B2, B3, C4, D5 1 I/O

Shared UTOPIA Request.

Used to indicate a cell to be transferred from a requested queue if device is shared UTOPIA slave. 6 mA drive, TTL compatible I/O. These pins have an internal 50 kΩ pull-up resistor.

16 Agere Systems Inc.

Advance Data Sheet

September 2001

ATM Interconnect

CelXpres

T8208

2 Pinout (continued)

Table 3. Cell Bus Pins

Symbol Ball Reset

Value

Type Name/Description

ua*[4:0] B18, B17, C17, D16,

A18

—I

Unit Address Lines (Active-Low).

Address assigned to device for cell bus identification. TTL compatible input, 5 V tolerant.

cb_d*[31:0] B5, C6, D7, A5, B6,

C7, A6, B7, A7, C8, B8, A8, D9, C9, B9,

A9, A11, C11, B1 1, A12, B12, C12, D12, A13, B13, C13, A14, B14, C14, A15, B15,

D14

Z I/O Cell Bus Data Lines (Active-Low). GTL+ I/O.

cb_wc* A10 — I Cell Bus Write Clock (Active-Low). Uses falling edge

to output data on cell bus. Write and read clocks have the same frequency but different phase. GTL+ input.

cb_rc* B10 — I Cell Bus Read Clock (Active-Low). Uses falling edge

to latch data from cell bus. Write and read clocks have the same frequency but different phase. GTL+ input.

cb_fs* C15 Z I/O Cell Bus Frame Sync (Active-Low). GTL+ I/O.

cb_ack* B16 Z I/O Cell Bus Acknowledge Signal (Active-Low). Driven

low on cycle 0 of the following frame when a valid cell is received from the cell bus. This signal is not driven for broadcast or multicast cells. GTL+ I/O.

arb_en* A17 — I Cell Bus Arbiter Enable (Active-Low). Cell bus arbiter

enable. Only one device on the cell bus may be configured as arbiter. TTL-compatible input, 5 V tolerant. This pin has an internal 50 kΩ pull-up resistor.

cb_disable* C16 — I Cell Bus Disable (Active-Low). CMOS input that 3-

states all GTL+ outputs when low, but G TL+ buffer inputs are active. Th is pi n has a n in te rnal 50 kΩ pull-up resistor.

cb_iref A4 — I Cell Bus Current Reference. Precision curr ent re fer-

ence for GTL+ buffers. A 1 kΩ, 1% resistor must be connected between this pin and GND.

cb_vref D10 — I Cell Bus Voltage Reference. GTL+ buffer threshold

voltage reference (1.0 V typical). This voltage reference is 2/3 V

TT, created using a voltage divider of three 1 kΩ,

1% resistors between V

TT and cb_vref_vss.

cb_vref_vss C10 — — Cell Bus Voltage Reference Ground.

cb_gen_wc A3 — O Cell Bus Generated Write Clock. TTL Compatible

(+5 V) drive r. 10 mA drive. This is the write clock generated by the T8208 device. Read/write clock delay set by register 0122h bits[15:13].

cb_gen_rc B4 — O Cell Bus Generated Read Clock. TTL Compatible

(+5 V) driver. 10 mA drive. This is the read clock generated by the T8208 device. Read/write clock delay set by register 0122h bits[15:13].

Agere Systems Inc. 17

Advance Data Sheet September 2001

ATM Interconnect

CelXpres

T8208

2 Pinout (continued)

T able 4. SDRAM Interface Pins

Symbol Ball Reset

Value

Type Name/Description

sd_a[11:0] L19, L18, L20,

K20, K19, K18,

K17, J20, J19,

J18, J17, H20

SDRAM Address Lines. 7 mA drive, TTL compatible output. These buffers are 50 Ω impedance matching buffers. Long printed-wiring board traces should have 50 Ω nominal impedance.

sd_d[15:0] F19, E20, G17,

F18, E19, D20,

E18, D19, C20 E17, D18, C19, B20, C18, B19,

A20

Z I/O

SDRAM Data Lines. 7 mA drive, TTL comp atib le I/O. Th ese buffers are 50 Ω

impedance matching buffers. Long printed-

wiring board traces should have 50 Ω nominal impedance.

sd_bs[1:0] H18, G20 X O

SDRAM Bank Selects. 7 mA drive, TTL compatible output. These buffers are 50 Ω

impedance matching buffers. Long printed-wiring board traces sh ould have 50 Ω nominal impedance.

sd_ras* G19 1 O

SDRAM Row Address Select (Active-Low). 7 mA drive, TTL compatible output. This buffer is a 50 Ω

impedance matching buffer. Long printed-wiring board traces should have 50 Ω nominal impedance.

sd_cas* F20 1 O

SDRAM Column Address Select (Active-Low). 7 mA drive, TTL compatible output. This buffer is a 50 Ω

impedance matching buffer. Long printed-wiring board traces should have 50 Ω nominal impedance.

sd_we* G18 1 O

SDRAM Write Enable (Active-Low). 7 mA drive, TTL compatible output. This buffer is a 50 Ω

impedance matching buffer. Long printed-wiring board traces should have 50 Ω nominal impedance.

sd_clk H19 Z O

SDRAM Clock. 7 mA drive, TTL compatible output. This buffer is a 50 Ω

impedance matching buffer. Long printed-

wiring board traces should have 50 Ω nominal impedance.

sd_iref A19

—ISDRAM Current Reference. Precision current reference for

SDRAM buffers. A 1 kΩ, 1% resistor must be connected between this pin and GND.

18 Agere Systems Inc.

Advance Data Sheet

September 2001

ATM Interconnect

CelXpres

T8208

2 Pinout (continued)

Table 5. Microprocessor Interface Pins

Symbol Ball Reset

Value

Type Name/Description

a[7:1] W6, Y6, V7, W7 ,

Y7, V8, W8

—IMicroprocessor Port Address Lines. Most significant

7 bits of the address bus. TTL compatible input, 5 V tolerant.

a[0]/ale Y8 — I Microprocessor Port Address 0/Address Latch Enable.

Least significant bit of the address bus in nonmultiplexed mode or address latch enable in multiplexed mode.

d[7:0] U9, V9 W9, Y9,

W10, V10, Y10,

Y11

Z I/O Microprocessor Port Data Lines. 6 mA driv e, TT L compat-

ible I/O, 5 V tolerant.

sel* W12 — I Microprocessor Chip Select (Active-Low). TTL compati-

ble input, 5 V tolerant.

wr*_ds* V12 — I Microprocessor Write/Data Strobe. Active-low write

enable in

Intel

mode. Active-low data strobe in

Motorola

mode. TTL compatible input, 5 V tolerant.

rd*_rw* U12 — I Microprocessor Read/Write. Active-low read enable in

Intel

mode, or read/write* enable in

Motorola

mode, where read is active-high and write is active-low. TTL compatible input, 5 V tolerant.

int_irq* Y12 0/1 O CPU Interrupt. Active-high in

Intel

mode and active-low in

Motorola

mode. 4 mA drive, TTL compatible output.

rdy_dtack* U11 Z O Ready/Data Transfer Acknowledge. Active-high ready sig-

nal in

Intel

mode and active-low data transfer acknowledge

Motorola

mode. Indicates access complete. 6 mA drive,

TTL compatible output.

mot_sel Y13 — I

Intel/Motorola

Selection. ‘0’ =

Intel

, ‘1’ =

Motorola

. TTL

compatible input, 5 V tolerant.

mux W13 — I Microprocessor Multiplex Select. Active-high for multiplex

mode. TTL compatible input, 5 V tolerant.

Agere Systems Inc. 19

Advance Data Sheet September 2001

ATM Interconnect

CelXpres

T8208

2 Pinout (continued)

T able 6. Translation SRAM Interface

Table 7. JTAG Pins

Symbol Ball Reset

Value

T ype Name/Description

tr_a[17:0] L3, L2, L1, K1,

K3, K2, J1, J2,

J3, J4, H1, H2,

H3, G1, G2, G3,

F1, F2

XOTranslation RAM Address Lines. 4 mA drive, TTL compat-

ible output.

tr_d[7:0] E3, D1, C1, E4,

D3, D2, C2, B1

Z I/O Translation RAM Data Lines. 4 mA drive, TTL compatible

I/O, 5 V tolerant.

tr_cs*[1:0] E1, E2 1 O Translation RAM Chip Selects (Active-Low). Chip selects

to select one of two external SRAMs. For connection to one external device, tr_cs*[0] is used. 4 mA drive, TTL compatible output.

tr_oe* F3 1 O External RAM Output Enable (Active-Low). 4 mA drive,

TTL compatible output.

tr_we* G4 1 O External RAM Write Enable (Active-Low). 4 mA drive,

TTL compatible output.

Symbol Ball Reset

Value

T ype Name/Description

jtag_tdi Y16 —IT est Data Input (JTAG). TTL compatible input, 5 V tolerant.

This pin has an internal 50 kΩ pull-up resistor.

jtag_tdo W16 X O Test Data Output (JTAG). 4 mA drive, TTL compatible out-

put.

jtag_trst* W15 — I Test Reset (JTAG) (Active-Low). Should be pulled low

when part is in normal operation. TTL compatible input, 5 V tolerant. This pin has an internal

50 kΩ pull-up resistor.

jtag_tclk V15 — I

T est Clock (JTAG).

TTL compatible input, 5 V tolerant. This

pin has an internal 50 kΩ pull-up resistor.

jtag_tms U14 — I

Test Mode Select (JTAG).

TTL compatible input, 5 V toler-

ant. This pin has an internal 50 kΩ pull-up resistor.

20 Agere Systems Inc.

Advance Data Sheet

September 2001

ATM Interconnect

CelXpres

T8208

2 Pinout (continued)

Table 8. General-Purpose Pins

Table 9. Power Pins

Symbol Ball Reset

Value

Type Name/Description

gpio[7:0] U5, Y3, Y4, V5,

W5, Y5, V6, U7

— I/O General-Purpose I/O. 4 mA drive, TTL compatible I/O, 5 V

tolerant. These pins have an internal 50 kΩ pull-up resistor.

reset* V14 — I Reset (Active-Low). Schmitt trigger, TTL compatible input,

5 V tolerant.

xtalin V13 — I Crystal Input (pclk). This input may be driven by either a

crystal or an external clock. If a crystal is used, connect it between this pin and xtalout and connect the appropriately valued capacitor from this pin to V

SS.

If an external clock is used, this is a 5 V tolerant CMOS input with 50 MHz max input frequency.

xtalout Y14 — O Crystal Output Feedback. If a crystal is used, connect it

between this pin and xtalin and connect the appropriately valued capacitor from this pin to V

SS. If an external clock is

used to drive xtalin, this pin must be left unconnected.

cko W11 — O Buffered Clock Output. If enabled, pclk is output on this

pin. 8 mA drive, TTL compatible output. This pin is high impedance if not enabled.

cko_e V11 — I CKO Enable. Enable for buffered clock output. If cko is not

used, tie this enable pin low. Active-high, TTL compatible input, 5 V tolerant.

NC A2, A16, C3, C5,

Y15, Y17

——No Connection. Reserved.

Symbol Ball Name/Description

DD D6, D11, D15, F4, F17, K4, L17, R4, R17, U6,

U10, U15

Power. 3.3 V. These pins should be properly decoupled using 0.01 µF or 0.1 µF capacitors.

SS A1, D4, D8, D13, D17, H4, H17, J9, J10, J11,

J12, K9, K10, K11, K12, L9, L10, L11, L12, M9,

M10, M11, M12, N4, N17, U4, U8, U13, U17

Ground.

DDA W14 Clock Oscillator Power. 3.3 V. This pin should

be properly decoupled using 0.01 µF or 0.1 µF capacitors.

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2 Pinout (continued)

5-8013(f) m

Figure 3. 272-Pin PBGA—Top View

VDD

VSS

VSS VDD VSS VSS VDD VSS

VDD

VSS

VDD

VSS

VDD

VDDVSS VDD VSS VSS VDD VSS

VDD

VSS

VDD

VSS

VDD

1234567891011121314151617181920

VSS VSS VSS VSS

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3 Powerup/Reset Sequence

One of the following two methods may be used to reset the T8208:

1. Assert the reset* pin low for at least 5 pclk periods or 100 ns, whichever is longer, and then return it high for a hardware reset. For a powerup reset, the reset* pin should be held low for at least 5 pclk periods or 100 ns, whichever is longer, after the power supply ramps to its operating voltage and the crystal oscillator is stable.

Write both the srst* and srst_reg* bits in the direct configuration/control register (address 28h) to ‘0,’ and leave them at that value for at least 1 µs to perform a software reset.

The device is now in the reset state, and the following start-up procedure must be executed to ensure proper operation:

1. After pclk (xtalin) is provided to the T8208, and the device is in the reset state: A. Write the mclk PLL configuration 0 and 1 registers at addresses 2Ah and 2Bh. B. Continue after the PLL has stabilized in 100 µs.

2. Set the srst_reg* bit (to take the main registers out of reset), and program the cyc_per_acc and big_end bits in the direct configuration/control register (address 28h).

3. Wait 1 µs for the circuit to stabilize.

Extended memory accesses may now be performed only to the main register group.

4. Write the desired values to the main configuration 1 register (address 0100h), the TX UTOPIA clock configuration register (address 010Ch), and the RX UTOPIA clock configuration register (address 010Eh) in the extended memory registers. These bits should not be modified at a later time without returning to the reset state.

5. Program the main configuration 2 register (address 0112h) and the UTOPIA configuration register (address 0114h). These registers should not be modified at a later time without returning to the reset state.

6. Program the cb_arb_sel and cb_usr_mode bits in the cell bus configuration/status register (address 0130h).

7. Wait one clock period of the slowest clock (cell bus, UTOPIA, or pclk) for the circuit to stabilize.

8. Set the srst* bit in the direct configuration/control register (address 28h).

9. Wait three clock periods of the slowest clock (cell bus, UTOPIA, or pclk) for the circuit to stabilize.

The T8208 device is now out of reset state.

10. Initialize the SDRAM per the SDRAM specifications.

11. Enable the SDRAM by setting the sdram_en bit in the SDRAM control register (address 0400h).

12. Initialize the LUT to benign values (recommended).

13. Initialize the multicast memory to all ’0’ (recommended).

14. Program the four routing information registers (addresses 0200h through 0204h and 0214h) and the seven PPD information registers (addresses 0206h through 0212h).

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T8208

4 Hot Insertion

When a connector with proper pin sequencing is used, the Agere Systems Inc. GTL+ buffers withstand hot insertion into a backplane without corrupting the cell bus or damaging the device. The ground pins on the connector should extend beyond all other pins so that the ground connections are made first. In addition, the power pins on the connector should extend beyond the signal pins so that the power connections are made before the signal but after the ground connections.

During hot insertion, the cell bus is not corrupted because the GTL+ outputs go to a high-impedance state during the powerup reset. Therefore, proper timing should be met in the external powerup reset circuit.

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5 PLL Configuration

The frequency of the device’s main clock (mclk) is derived from the clock at the xtalin input (pclk) and is given by the following equation when the PLL is engaged:

mclk = fpclk x

Note: When the PLL is engaged, mclk is the output of the PLL.

M and N are the pll_m[4:0] and pll_n[2:0] counter values in the mclk PLL configuration 1 register (address 2Bh) and must be set so that the voltage-controlled oscillator (VCO) operates in the appropriate range. The maximum value for f

mclk is 100 MHz. The valid range for M is between 2 and 22 inclusive, and the valid range for N is between 0

and 7 inclusive. When multiple sets of values can achieve the desired result, choose the lowest value of M and the corresponding value for N.

Note: The output of the PLL must always be at least 50 MHz.

The loop filter must be set properly for correct operation of the PLL. The proper setting of the loop filter bits, lf[3:0], in the mclk PLL configuration 0 register (address 2Ah) is determined by the chosen value for M. The following table lists the lf[3:0] settings for given values of M. Typical PLL lock-in time is 50 µs.

Table 10. Loop Filter Register Settings

PLL Configuration Example

Given a pclk frequency of 50 MHz and a desired mclk frequency of 100 MHz, the proper values of M, N, and lf[3:0] are the following:

M = 2 N = 7

lf[3:0] = “0010” The bypass PLL (bypb) and PLL enable (pllen) bits are used to select the source of mclk for the T8208. To select

the output of the PLL as the clock, both bits must be programmed to ‘1,’ and to select pclk as the clock, both bits must be programmed to ‘0.’

M Mclk PLL Configuration 0

(2Ah) lf[3:0]

22 “0111” 16—21 “01 10” 10—15 “0101”

6—9 “0100” 4—5 “0011” 2—3 “0010”

()

2MOD8N1

()1

()×()

------------------------------------------------------------------

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6 Microprocessor Interface

6.1 Microprocessor Interface Configura tion

The microprocessor interface may be configured for either

Intel

Motorola

mode via the mot_sel input. Tie

mot_sel high to select

Motorola

mode and low to select

Intel

mode. In addition, the address and data buses may be configured for multiplexed or nonmultiplexed mode using the mux input. To select multiplexed mode, tie mux high, and to select nonmultiplexed mode, tie mux low. In multiplexed mode, d[7:0] are used for both the address and the data bus, and the a[0] input becomes an address latch enable (ale) signal. In nonmultiplexed mode, separate address, a[7:0], and data, d[7:0], buses are used. In both modes, the active-low sel* input selects the device for microprocessor read or write accesses. The data leads are 3-stated when the sel*, wr*_ds*, or rd*_wr* signal is high.

Motorola

mode, rd*_rw* is a read/write enable signal, which indicates the current access is a read when it is high

and a write when low. The wr*_ds* signal is data strobe in

Motorola

mode. The rdy_dtack* output is an active-low data transfer acknowledge signal. The T8208 takes this signal low when the microprocessor access is complete. The rdy_dtack* output returns high when the microprocessor acknowledges the access by taking the sel* or wr*_ds* signal high. The rdy_dtack* output then goes high-impedance.

Intel

mode, the rd*_rw* input is an active-low read enable signal, and wr*_ds* is an active-low write enable signal. A logic low level on rd*_rw* indicates to the T8208 that the current access is a read, and a logic low level on wr*_ds* indicates the access is a write. Finally, the rdy_dtack* output is an active-high ready signal. The T8208 asserts this signal high when a microprocessor access is complete. The rdy_dtack* output then goes high-impedance when the sel*, wr*_ds*, or rd*_wr* signal goes high.

6.2 Microprocessor Interrupts

The int_irq* output is an active-high interrupt in

Intel

mode and an active-low interrupt request in

Motorola

mode. In

Intel

mode, int_irq* is normally low and goes high when an interrupt is generated. In

Motorola

mode, the interrupt request signal is normally high and goes low during an interrupt. Interrupts are generated when an enabled interrupt status bit becomes set. All interrupt status bits in the T8208 have a corresponding interrupt enable bit. When the enable bit is cleared, the corresponding interrupt status bit is not enabled and will not generate an interrupt. Several registers containing interrupt status bits exist in the four separate extended memory register groups (main, UTOPIA, SDRAM, and bypass SDRAM) of the T8208. The interrupt service request register at direct address 29h indicates which register group is generating the interrupt. Only enabled interrupts will cause the int_serv_mainreg, int_serv_sdramreg, and int_serv_utopiareg bits to become set. For the main register group, a special case exists. The ctrl_cell_sent and the ctrl_cell_av interrupts (in the main interrupt status 1 register) do not cause the main group indication bit to be set in the interrupt service request register. These interrupts have their own dedicated service request bits to optimize sending and receiving control cells. The ctrl_cell_sent and ctrl_cell_av bits may become set whether the corresponding interrupt is enabled or not.

6.3 Accessing the

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The

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T8208 has two distinct memory spaces: the direct memory access registers and the extended memory registers. The direct memory access registers are directly addressed 8-bit (byte) registers and are mapped between addresses 00h and FFh. The extended memory registers are indirectly addressed and mapped between addresses 0100h and 3FFFFFEh. The extended memory contains the SDRAM memory, the translation RAM,

internal memories, and the device’s configuration, status, and control registers. Extended memory registers are 16 bits wide, and all accesses to the extended memory registers are executed internally as 16 bits. Direct memory access registers are located in Section 14.2, Direct Memory Access Registers, and extended memory registers are located in Section 14.3, Extended Memory Registers.

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6 Microprocessor Interface (continued)

6.3.1 Accessing the Extended Memory Registers

Before accessing the extended memory registers, the powerup sequence, as described in Section 3, Powerup/ Reset Sequence, must be completed. Accesses to extended memory are word accesses internally; therefore, the

least significant bit of the address is always ‘0.’ Only the most significant 25 bits are supplied to the extended memory address registers (addr es ses 30h—34h). The following procedure outlines the steps needed for extended

memory accesses in the T8208 device.

6.3.1.1 Extended Memory Writes

1. Write ext_a [25] bit to the extended memory address 4 register (little endian or big endian) (optional).

2. Write ext_a [24:17] byte to the extended memory address register 3 (little endian or big endian) (optional).

3. Write ext_a [16:9] byte to the extended memory address register 2 (little endian or big endian) (optional).

4. Write ext_a [8:6] bits to the extended memory address register 1 (little endian or big endian) (optional).

5. Write ext_d [15:8] byte to the extended memory data high register (little endian or big endian) (optional).

6. Write ext_d [7:0] byte to the extended memory data low register (little endian or big endian) (optional).

7. Write ext_a [5:1] bits; write “01,” “10,” or “11” to ext_we[1:0]; and write ‘1’ to ext_strt_acc in the extended memory access register (little endian or big endian) (mandatory).

8. Read the extended memory access register (little endian or big endian) to determine that the ext_strt_acc bit has been cleared by hardware (mandatory).

6.3.1.2 Extended Memory Reads

1. Write ext_a [25] bit to the extended memory address 4 register (little endian or big endian) (optional).

2. Write ext_a [24:17] byte to the extended memory address register 3 (little endian or big endian) (optional).

3. Write ext_a [16:9] byte to the extended memory address register 2 (little endian or big endian) (optional).

4. Write ext_a [8:6] bits to the extended memory address register 1 (little endian or big endian) (optional).

5. Write ext_a [5:1] bits; write “00” to ext_we[1:0]; and write ‘1’ to ext_strt_acc in the extended memory access register (little endian or big endian) (mandatory).

6. Read the extended memory access register (little endian or big endian) to determine that the ext_strt_acc bit has been cleared by hardware (mandatory).

7. Read ext_d [15:8] byte from the extended memory data high register (little endian or big endian) (optional).

8. Read ext_d [7:0] byte from the extended memory data low register (little endian or big endian) (optional).

Note: Once the ext_strt_acc bit is set by software, only the extended memory access register should be

accessed until the ext_strt_acc bit is cleared by hardware.

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6 Microprocessor Interface (continued)

6.3.2

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T8208 Access Performance

The times represented in the following table reflect access times for various microprocessor interface reads and writes. For direct access registers, the values represent the time until the rdy_dtack signal transitions indicating the data transfer portion of the access is complete. For accesses to extended memory, the values represent the time from the completion of a write to register 34h until the ext_strt_acc bit is cleared.

The actual times are dependent on the frequency of the pclk and mclk clocks (see Section 5, PLL Configuration). The terms pclkp and mclkp in the table represent the period of pclk and mclk, respectively, in ns.

T able 11. Access Times

Description Min Typ Max Unit

Read/Write to 28h—3Dh 4 x pclkp 5 x pclkp 5 x pclkp + 30 ns Reads to:

60h—93h, A0h—D7h, E0h—FFh

(direct internal memory)

6 x pclkp + 3 x mclkp 8 x pclkp + 9 x mclkp 12 x pclkp + 15 x mclkp ns

Writes to:

60h—93h, A0h—D7h, E0h—FFh

(direct internal memory)

6 x pclkp 8 x pclkp + 4 x mclkp 10 x pclkp + 9 x mclkp ns

Reads to Extended Memory

Internal Structures

6 x pclkp + 6 x mclkp 8 x pclkp + 12 x mclkp 12 x pclkp + 18 x mclkp ns

Writes to Extended Memory

Internal Structures

6 x pclkp 8 x pclkp + 7 x mclkp 10 x pclkp + 12 x mclkp ns

Read from LUT SRAM 4 x pclkp + 11 x mclkp — 10 x pclkp + 50 x mclkp ns Write to LUT SRAM 4 x pclkp — 10 x pclkp + 50 x mclkp ns

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7 General-Purpose I/O (GPIO)

The T8208 has eight programmable general-purpose I/O pins called GPIO. These GPIO pins may be independently programmed, via the GPIO_oe[7:0] bits in the GPIO output enable register (address 39h), to be inputs or

outputs. If a GPIO_oe bit is set to ‘1,’ the corresponding GPIO pin is an output, or if cleared to ‘0,’ the corresponding GPIO pin is an input. Input values are read from the GPIO_in[7:0] bits in the GPIO input value register (address 3Dh), and output values are written to the GPIO_out[7:0] bits in the GPIO output value register (address 3Bh). The GPIO[7:0] pins all have internal 50 kΩ pull-up resistors.

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8 Look-Up Table

Cells arriving from the UTOPIA bus obtain information from the external static RAM look-up table (LUT), which is divided among VPI, VCI, and OAM/RM records. Each of these records contains specific VPI or VPI/VCI translation and cell bus routing information. The size of the records is programmable to 8 bytes or an extended 16 bytes. The 16-byte mode adds two 32-bit counters to each record. The 16-byte mode is discussed in Section 8.4, Extended Records.

The VPI value in the header, in addition to the PHY port number, of the incoming cell points to a VPI record in the look-up table. This VPI record is examined first. If the VPI record indicates OAM F4 routing, the OAM record, to which the VPI record points, provides the OAM routing and VPI/VCI translation information. If OAM F4 routing is not indicated, information about the type of translation, VPI only or VPI/VCI, is obtained from the original VPI record. For VPI only translation, routing information is obtained from the VPI record, and full or partial VPI translation is performed.

For VPI/VCI translation, the VPI record points to the appropriate VCI record, where VPI/VCI translation and routing information is stored. If the VCI record indicates OAM F5 routing, the OAM record, to which the VCI record points, provides the OAM routing and VPI/VCI translation information. If no OAM F5 routing is indicated, VPI/VCI translation and cell routing are performed using the information in the VCI record.

8.1 Look-Up Table RAM

The number of memory devices (up to two) used for the look-up table and the size of the external SRAM are programmable. The tram_qnty_sel bit in the main configuration 1 register (address 0100h) specifies whether one or two RAM chips are used. If two memory devices are used, separate chip select signals are generated. These chip selects are created from the decoded RAM addresses. The tram_size configuration bits, also in the main configuration 1 register, are used to select memory sizes of 32 Kbytes, 64 Kbytes, 128 Kbytes, or 256 Kbytes. Therefore, the maximum look-up table size of 512 Kbytes is realized when two RAM chips of 256 Kbytes each are used.

If a single SRAM of 512 Kbytes is used (instead of two SRAMs of 256 Kbytes each), then bit 5 in the main configu-

ration 1 register must be set to ‘1.’ If a single SRAM of 512 Kbytes is not used, this bit must be cleared to ‘0.’

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8 Look-Up Table (continued)

8.2 Organization

Organization is discussed in terms of 8-byte records. Differences in organization for 8-byte records and 16-byte records will be discussed in Section 8.4, Extended Records. The look-up table may be configured to support up to 64 ports when multi-PHY mode is used, effectively creating a separate look-up table for each port.

All VPI, VCI, and OAM/RM records may be either 8 bytes or 16 bytes in length. (See Section 8.4, Extended Records for information on 16-byte records.) Figure 4 shows the translation RAM memory map for 8-byte records. OAM/RM translation records are located at the bottom of the memory space with 64 OAM/RM records used by each port. If the device is configured to support 64 ports, the first 4096 records will be used for OAM and RM translation records. This translates to 32 Kbytes of memory for 8-byte records. The remaining memory is then used for VPI and VCI records. For 8-byte records, the base addresses of the OAM records are calculated from the following equation:

OBA = PN × 8 × 64 In this equation, OBA is the OAM base address, PN is the port number, 8 is the number of bytes per record, and 64

is the number of records per port. For example, the OAM/RM translation records for port 2 will have a base address of 1024 or 400h.

Note: If the device is configured to use less than 64 ports, the OAM/RM translation record memory space will be

allocated enough memory to handle ports 0 through the maximum port number used. For example, if the device is configured to use ports 0, 2, 4, and 6 (see Section 9, UTOPIA Interface), the OAM/RM translation record memory space will use 448 records (for ports 0 through 6). OAM/RM translation record memory space for ports 1, 3, and 5 will be skipped even though the ports are not used.

Note: If the device is configured in PHY mode (see Section 9, UTOPIA Interface), the device supports only a single

PHY and the translation RAM memory will be addressed as port 0.

Separate VPI record base addresses may be set up for each port in multi-PHY mode, and the number of incoming VPI bits used as a pointer into the look-up table may be programmed. (See Section 14.3, Extended Memory Registers, Table 153, PHY Port X Configuration Structure (PPXCF) (4200h to 42FEh).) For 8-byte records, the total memory used by the VPI records is calculated using the following equation:

MS = NP x 2

x 8

In this equation, MS is the memory size used for VPI records, NP is the number of ports used, 8 is the number of bytes per record, and NB is the number of incoming VPI bits used to address the look-up table.

This calculated memory space must be reserved for VPI records.

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8 Look-Up Table (continued)

Figure 4. Translation RAM Memory Map—8-Byte Records

The four translation record types (VCI, OAM/RM, VPI only, and VPI for VPI/VCI) for 8-byte records are illustrated in Figure 5. There are two types of VPI translation records: one for VPI translation only and one for VPI/VCI translation. The VPI only translation record differs from other records in that it has the SH and SL bits which are used to indicate full or partial VPI translation. (See T able 13, the VPI V alue Truth Table.) The other VPI record is used when VPI/VCI translation occurs. It has the VCI offset bits and max VCI value bits which are used to point to the VCI record where translation and routing information reside. The maximum VCI offset is 19 bits in length; therefore, only bits 3 through 18 are stored in the VPI record.

To address the appropriate VCI translation record, the VCI from the cell’s header is multiplied by 8 and added to bits 3 through 18 of the VCI offset which is obtained from the VPI record. This sum is the final offset into the lookup table. This final offset should then be added to the Translation RAM Memory beginning address 100000h (T able

180) to obtain the final address. The max VCI value indicates the maximum number of VCI translation records in the table. Therefore, if the VCI from the cell’s header is greater than the max VCI value, the cell’s VCI is out of range and is counted as a misrouted cell. Note that VPI records from different ports may reference the same VCI translation record. Other control bits in these records are described following Figure 5.

Routing Look-Up Memory Map OAM Cell Routing Port X Record Map

0000h OAM Cell Routing Port 0 +0000h VP OAM VCI = 0 (F4) 0200h OAM Cell Routing Port 1

•

0400h OAM Cell Routing Port 2 0600h OAM Cell Routing Port 3

0800h OAM Cell Routing Port 4 +00F8h VP OAM VCI = 31 (F4) 0A00h OAM Cell Routing Port 5 +0100h VP OAM VCI = 6 & PT = “110” (F4) (RM-VPC) 0C00h OAM Cell Routing Port 6 +0108h VC OAM PTI = “100” (F5) 0E00h OAM Cell Routing Port 7 +0110h VC OAM PTI = “101” (F5)

1000h OAM Cell Routing Port 8 +0118h VC OAM PTI = “110” (F5)

1200h OAM Cell Routing Port 9 +0120h VC OAM PTI = “111” (F5)

1400h OAM Cell Routing Port 10 +0128h Reserved

• +0130h Reserved

•

7A00h OAM Cell Routing Port 61 7C00h OAM Cell Routing Port 62

7E00h OAM Cell Routing Port 63 +01F8h Reserved

8000h

Any Purpose Look-Up Memory

Shared Between Each of the 64

Ports

7FFFFh

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8 Look-Up Table (continued)

Figure 5. Translation Record Types—8-Byte Records

VPI Only Translation Record

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 A P E I VPI[11:0] +2 SH SL Reserved +4 Cell Bus Routing Header[15:0] +6 Tandem Routing Header[15:0]

VPI for VPI/VCI Translation Record

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 A P E I Reserved +2 Bits 3 Through 18 of VCI Offset[15:0] +4 Max VCI Value[15:0] +6 Reserved

VCI Translation Record

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 A — E I VPI[11:0]

+2 VCI[15:0] +4 Cell Bus Routing Header[15:0] +6 Tandem Routing Header[15:0]

OAM/RM Translation Record

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 A C1 C0 I VPI[11:0] +2 VCI[15:0] +4 Cell Bus Routing Header[15:0] +6 Tandem Routing Header[15:0]

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8 Look-Up Table (continued)

The routing control bits for VPI, VCI, and OAM/RM records are described below:

■ Active (A). This bit is one when the VPI or VCI is considered active. See the truth table (Table 12) below. This bit

is used in all types of records.

■ Ignore (I). When this bit is one, the VPI or VCI is ignored. See the truth table (Table 12) below. This bit is used in

all types of records.

If masking the I bit is required (when the I bit is set to ‘1’), then the mask_ignore bit (bit 13 in register 0112h) can be used to achieve this masking.

When this bit is set to 1, the T8208 ignores the ignore bit that was programmed in the look-up records that control the translation of the incoming UTOPIA cells. This can be used for redundancy if desired. For redundancy, the software can populate the look-up tables of two T8208 devices (one active and one inactive for redundancy). The ignore (I) bit needs to be set in both the active and inactive devices. The active device has the mask_ignore bit = 1 and the inactive device has the mask_ignore bit = 0. This way the inactive device will not count, route or translate the incoming cells (ignores them). When the active device fails, its mask_ignore bit becomes 0 and the inactive device becomes active by setting its mask_ignore bit = 1. The failed device now will no longer try to count, route, or translate incoming cells, and the new active device takes over cell routing and VPI/VCI translation.

Table 12. Active and Ignore Truth Table

AI Action

0 0 The cell is discarded, considered misrouted, and counted as a received cell. 0 1 The cell is discarded, is not flagged as misrouted, and is not counted as a received cell. 1 0 The cell is valid and is counted as a received cell. 1 1 The cell is discarded, is not flagged as misrouted, and is not counted as a received cell.

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8 Look-Up Table (continued)

■ Enable OAM/RM Routing (E). When this bit is ‘1’ in the VPI record and the VCI is less than 32, the routing and

translation information is obtained from the appropriate OAM/RM F4 record. If this bit is ‘1’ in the VCI record and the most significant bit of the PTI in the cell header is ‘1,’ the routing and translation information is obtained from the appropriate OAM/RM F5 record. This bit is used only in VPI and VCI records.

■ VPI Translation (P). When this bit is ‘1,’ translation is on the VPI only. When this bit is ‘0,’ VPI/VCI translation is

performed. This bit is used only in VPI records.

■ VPI Value High (SH). When this bit is ‘1,’ bits 8 through 11 of the incoming VPI are replaced with the correspond-

ing bits in the VPI record. See the truth table (Table 13) below. This bit is used in VPI only translation records.

■ VPI Value Low (SL). When this bit is ‘1,’ bits 0 through 7 of the incoming VPI are replaced with the corresponding

bits in the VPI record. See the truth table (Table 13) below. This bit is used in VPI only translation records.

Table 13. VPI Value Truth Table

■ OAM Routing Control (C1, C0). These 2 bits determine if the cell is routed as OAM/RM and if VPI/VCI translation

is performed. See the truth table (Table 14) below. These bits are used only in OAM/RM records.

Table 14. OAM Routing Control Truth Table

1. The most significant 4 bits of the VPI will only be substituted if the global rplc_gfc bit in the direct configuration/control register (address 28h) is set in UNI mode or if the port is configured in NNI mode.

SH SL Action

0 0 No VPI translation is performed. 01VPI translation is performed only on bits 0—7 of the incoming VPI.

1 0 VPI translation is performed only on bits 8—11 of the incoming VPI. 1 1 Complete VPI translation is performed.

C1 C0 Action

0 0 Both incoming VPI and VCI are substituted with the VPI

and VCI, respectively, in the OAM/RM record, and the cell is routed according to the cell bus and tandem routing headers in the OAM/RM record.

0 1 The cell is not routed as OAM/RM. If the record is OAM/RM F5, the cell is translated and routed

according to the cell bus and tandem routing headers in the original VCI record. If the record is OAM/ RM F4, the cell is translated and routed according to the cell bus and tandem routing headers in the original VPI record.

1 0 The incoming VPI and VCI will be preserved, and the cell is routed according to the cell bus and tan-

dem routing headers in the OAM/RM record.

11Reserved.

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8 Look-Up Table (continued)

8.3 Look-Up Procedure

Look-up procedure is discussed in terms of 8-byte records. Differences in look-up procedures for 8-byte records and 16-byte records will be discussed in Section 8.4, Extended Records. When a cell is received, the set lutX_vpi_mask bits in the PHY port X configuration structure (T able 153) indicate which incoming VPI bits are used to address the VPI record in the look-up table. The selected incoming VPI bits are multiplied by eight (for 8-byte records) to create an offset into the table. The sum of this offset and the VPI base address, found in the PHY port X configuration structure, creates the actual look-up table address for the VPI record associated with the cell. Note that only bits 3 through 18 of the VPI base address are stored in the PHY port X configuration structure. If the

lutX_vpi_chk bit is set, all unused VPI bits in the cell header must be ‘0,’ or the cell will be considered out of range. If the port is configured as UNI, the upper four VPI bits (GFC field) will be ignored in the verification. When the cell is out of range, it is discarded and not counted as a received cell.

The validity of the accessed VPI record is determined by checking its active (A) and ignore (I) bits. If the cell is valid, the enable OAM/RM routing (E) bit is consulted to determine if F4 type OAM cell treatment should occur. (See the definition for these bits in Section 8.2, Organization.)

When the E bit is set and the incoming VCI is less than 32, the OAM record associated with the cell is read. T o calculate the translation record address for the OAM/RM cell, the incoming VCI is multiplied by eight (for 8-byte records), and the resulting product is added to the port’s OAM base address. (See Section 8.2, Organization.) A special case exists when the incoming VCI is six and the PTI in the cell header is “110.” For this case, the OAM translation record address is the sum of the port’s OAM base address and 100h.

Next, the validity of the F4 OAM record is determined by checking its A and I bits. If it is valid, the cell is routed as described by the OAM routing control (C1, C0) bits. (See the definition for these bits in Section 8.2, Organization.)

If the E bit in the VPI record is not one or if the C1 and C0 bits in the OAM record are zero and one, respectively, the cell does not receive OAM routing. If the cell is not routed OAM, the virtual path routing bit (P bit) in the original VPI is checked to determine if the cell receives VPI only or VPI/VCI routing. If the P bit indicates VPI only routing, the cell’s VPI is replaced as indicated by the switch VPI high and low (SH, SL) bits in the VPI only translation record. (See the definition for these bits in Section 8.2, Organization.) The cell bus routing header and tandem routing header are then added to the cell, and the cell is transmitted on the cell bus.

If the P bit indicates VPI/VCI routing, the VCI translation record is accessed using the VCI offset and max VCI value bits in the VPI for VPI/VCI translation record. (The VCI offset and max VCI value bits are described in Section 8.2, Organization.) Again, the validity of the VCI translation record is determined by checking its A and I bits. Next, if the cell is valid, the E bit in the VCI record and the most significant bit of the PTI value in the cell header are

examined to determine if F5 type OAM cell treatment should occur. The value of the incoming cell’s PTI and port number determines the address in the OAM/RM record space. The following table outlines the look-up table offsets used for 8-byte records. The OAM translation record address is the sum of this offset and the port’s OAM base address.

Table 15. F5 Translation Record Addresses Table—8-Byte Records

PTI OAM Translation Offset

“100” Port’s OAM base address plus 108h “101” Port’s OAM base address plus 110h “110” Port’s OAM base address plus 118h “111” Port’s OAM base address plus 120h

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8 Look-Up Table (continued)

Next, the validity of the F5 OAM record is determined by checking its A and I bits. If it is valid, the cell is routed as described by the OAM routing control (C1, C0) bits. (See the definition for these bits in Section 8.2, Organization.)

If the E bit in the VCI record is not one or if the C1 and C0 bits in the OAM record are zero and one, respectively, the cell does not receive OAM routing. If the cell is not routed as an OAM cell, information in the VCI translation record is used to route the cell. The cell’s VPI and VCI are replaced with the VPI and VCI, respectively, in the VCI record. The most significant 4 bits of the VPI will only be substituted if the global rplc_gfc bit in the direct configuration/control register (address 28h) is set or if the port is configured in NNI mode. The cell bus routing header and tandem routing header are then added to the cell, and the cell is transmitted on the cell bus.

Note: Unused OAM cell routing records in the LUT memory space can be used for other purposes.

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8 Look-Up Table (continued)

This look-up procedure is outlined in the flow diagram below.

5-7781F and 5-7782F

Figure 6. Translation RAM Flow Diagram

CELL IN

READ VPI

UNUSED

FROM ATM CELL

HEADER

VPI BITS ALL ‘0’

OR LUTX_VPI_CHECK

= ‘0’?

A bit = 1

AND

I bit = 0?

E bit = 1

AND

VCI < 32?

READ VP

OAM RECORD

A bit = 1

AND

I bit = 0?

C1 & C0

= “00” ?

C1 & C0

= “10” ?

P bit = 1 ?

VCI

CELL

DISCARDED

CELL

DISCARDED

YES

CELL

DISCARDED

YES

VPI/VCI

TRANSLATION;

ROUTING FROM

OAM RECORD

VPI/VCI

PRESERVED;

ROUTING FROM

OAM RECORD

VPI

TRANSLATION;

ROUTING FROM

VP RECORD

READ VPI

RECORD

VCI

READ VCI

FROM ATM CELL

HEADER

VCI IN

RANGE?

A bit = 1

AND

I bit = 0?

E bit = 1

AND

PTI[2] = ‘1’?

YES

READ VC

OAM RECORD

A bit = 1

AND

I bit = 0?

YES

CELL

DISCARDED

C1 & C0

= “00” ?

C1 & C0

= “10” ?

YES

VPI/VCI

TRANSLATION;

ROUTING FROM

OAM RECORD

VPI/VCI

PRESERVED;

ROUTING FROM

OAM RECORD

VPI/VCI

TRANSLATION;

ROUTING FROM

VC RECORD

CELL

DISCARDED

CELL

DISCARDED

YES

READ VCI

RECORD

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8 Look-Up Table (continued)

8.4 Extended Records

The length of the translation records may be extended to 16 bytes to support two cell counts for each translation record. The lut_rec_form bits in the extended LUT configuration register (address 0138h) are used to select this extended mode. In extended (16-byte) mode, two 32-bit counters are appended to the 8-byte records.

The first counter in the translation record, total cell count, keeps a total count of all incoming cells received from the UTOPIA bus whether ultimately routed or discarded except those in which the VPI is out of range. See the definition of the A and I bits in Section 8.2, Organization.

The second counter, special cell count, is a subset of the total cell count counter. This counter counts only cells whose PTI and CLP values in the cell header match the values specified in the extended LUT control register (address 0120h). For example, this counter may be used to track specific F5 type OAM/RM cells and cells indicating forward congestion (EFCI = 1) or lower priority (CLP = 1).

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8 Look-Up Table (continued)

The four translation record types for extended mode are illustrated in Figure 7 below.

Figure 7. Translation Record Types—Extended Mode

Extended VPI Only Translation Record

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 A P E I VPI[11:0] +2 SH SL Reserved +4 Cell Bus Routing Header[15:0] +6 Tandem Routing Header[15:0] +8 Total Cell Count[31:16]

+A Total Cell Count[15:0] +C Special Cell Count[31:16] +E Special Cell Count[15:0]

Extended VPI for VPI/VCI Translation Record

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 A P E I Reserved +2 Bits 3 Through 18 of VCI Offset[15:0] +4 Max VCI Value[15:0] +6 Reserved +8 Reserved

+A Reserved +C Reserved +E Reserved

Extended VCI Translation Record

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 A — E I VPI[11:0]

+2 VCI[15:0] +4 Cell Bus Routing Header[15:0] +6 Tandem Routing Header[15:0] +8 Total Cell Count[31:16]

+A Total Cell Count[15:0] +C Special Cell Count[31:16] +E Special Cell Count[15:0]

Extended OAM/RM Translation Record

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 A C1 C0 I VPI[11:0] +2 VCI[15:0] +4 Cell Bus Routing Header[15:0] +6 Tandem Routing Header[15:0] +8 Total Cell Count[31:16]

+A Total Cell Count[15:0] +C Special Cell Count[31:16] +E Special Cell Count[15:0]

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8 Look-Up Table (continued)

Because the translation records are larger in extended mode, the look-up table memory map changes, the translation record address calculations change, and the memory size calculations change. Figure 8 shows the new translation RAM memory map for 16-byte records when the device is configured for 64 PHY ports.

Figure 8

. Translation RAM Memory Map—Extended Mode

Routing Look-Up Memory Map OAM Cell Routing Port X Record Map

0000h OAM Cell Routing Port 0 +0000h VP OAM VCI = 0 (F4) 0400h OAM Cell Routing Port 1

•

0800h OAM Cell Routing Port 2

0C00h OAM Cell Routing Port 3

1000h OAM Cell Routing Port 4 +01F0h VP OAM VCI = 31 (F4) 1400h OAM Cell Routing Port 5 +0200h VP OAM VCI = 6 & PT = “110” (F4) (RM-VPC)

1800h OAM Cell Routing Port 6 +0210h VC OAM PTI = “100” (F5)

1C00h OAM Cell Routing Port 7 +0220h VC OAM PTI = “101” (F5)

2000h OAM Cell Routing Port 8 +0230h VC OAM PTI = “110” (F5) 2400h OAM Cell Routing Port 9 +0240h VC OAM PTI = “111” (F5) 2800h OAM Cell Routing Port 10 +0250h Reserved

• +0260h Reserved

•

F400h OAM Cell Routing Port 61 F800h OAM Cell Routing Port 62

FC00h OAM Cell Routing Port 63 +03F0h Reserved

10000h

Any Purpose Look-Up Memory

Shared Between Each of the 64

Ports

7FFFFh

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8 Look-Up Table (continued)

The OAM/RM translation records at the bottom of the memory map now use 64 Kbytes of memory when the device is configured to support 64 MPHY ports, and the base addresses for the OAM records are now calculated using the following equation:

OBA = PN

× 16 × 64

In this equation, OBA is the OAM base address, PN is the port number, 16 is the number of bytes per record, and 64 is the number of records per port.

To calculate the 16-byte translation record address for the F4 type OAM cell, the incoming VCI is multiplied by 16,

and the resulting product is added to the port’s OAM base address. For the special case when the incoming VCI is six and the PTI in the cell header is “110,” the OAM translation record address is the sum of the port’s OAM base address and 200h.

The 16-byte OAM type F5 translation record offset is determined from the incoming cell’s PTI using the following table. The OAM translation record address is the sum of this offset and the port’s OAM base address.

Table 16. F5 Translation Record Addresses Table—Extended Mode

In extended mode, the memory space used by the VPI records also changes. The total memory now used by the VPI records is calculated using the following equation:

MS = NP x 2

x 16

In this equation, MS is the memory size used for VPI records, NP is the number of ports used, 16 is the number of bytes per record, and NB is the number of incoming VPI bits used to address the look-up table.

To address the 16-byte VPI translation record, the selected incoming VPI bits (see Section 8.3, Look-Up Procedure) are multiplied by 16 to create an offset into the look-up table. The sum of this offset and the VPI base address creates the actual VPI translation record address associated with the incoming cell. Note that only bits 3 through 18 of the VPI base address are stored

in the PHY port X configuration structure.

To address the 16-byte VCI translation record, the VCI from the cell’s header is multiplied by 16 and added to bits 3 through 18 of the VCI offset, which is obtained from the VPI record. This sum is the final offset into the look-up table. This final offset should then be added to the translation RAM memory beginning address 100000h (Table

180) to obtain the final address.

PTI OAM Translation Offset

“100” Port’s OAM base address plus 210h “101” Port’s OAM base address plus 220h “110” Port’s OAM base address plus 230h

“111” Port’s OAM base address plus 240h

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8 Look-Up Table (continued)

8.5 Diagnostics

The T8208 also includes diagnostics to track misrouted cells. A cell is considered misrouted if its A and I bits are

“00,” if its VCI is out of range, or if the lutX_vpi_chk bit is ‘1’ and the unused VPI bits in the incoming cell header are not all zero (see Section 8.3, Look-Up Procedure). When a misrouted cell is detected, the misrouted cell header high and low registers (addresses 0146h and 0148h) may be updated. If enabled, the mis_cell interrupt, the vci_or interrupt, or the vpi_or interrupt will be generated as appropriate (see Table 96 in Section 14.3, Extended Memory Registers).

The misrouted cell header high and low registers contain the first four header bytes of selected misrouted cells. Only a misrouted cell from a port whose mis_cell_lut_sel bit is set will update these registers, and this misrouted cell will update the registers only if it is the first received after the mis_cell_clr bit is set. The lst_mis_cell_lut bits indicate the port from which the header bytes in the misrouted cell header high and low registers were received. The mis_cell_lut_sel bits are located in the misrouted LUT 0, 1, 2, and 3 registers (addresses 0142h, 0140h, 013Eh, and 013Ch respectively). The mis_cell_clr, mis_cell_latch, and lst_mis_cell_lut bits are located in the misrouted LUT 4 register (address 0144h). (See Tables 77, 78, 79, 80, and 81 in Section 14.3, Extended Memory Registers, for a complete description of the above bits.)

8.6 Setup

When configuring the lut_en bits in the LUT X configuration/status register (addresses 0320h through 039Eh), care must be taken to ensure that the enabled ports’ LUTs correspond to the ports chosen in UTOPIA mode. (See Section 9.6, UTOPIA Pin Modes.) If a LUT is not enabled, corresponding bits in the PHY port X configuration structure (Section 14.3.2.4, RX UTOPIA Configuration Monitoring, Table 153) will be ignored. Also, when the device is configured for UTOPIA PHY mode (see Section 9, UTOPIA Interface), only port 0 entries in the external RAM look-up table are used; therefore, the look-up table should be set up accordingly.

8.7 LUT Bypass

This feature allows the elimination of the SRAM (which has the LUT information) in implementations that can provide the cell bus routing header (CBRH) and the tandem routing header (TRH) to the T8208 device. This feature is

enabled when bit 6 in register 0100h is set to ‘1.’ When this LUT bypass feature is enabled, the T8208 is expecting 58-byte cells in 16-bit UTOPIA mode and 57-byte cells in 8-bit UTOPIA mode on Rx UTOPIA.

If bit 7 in register 0100h is cleared to ‘0,’ then the T8208 device expects to see the TRH before the CBRH on the incoming cells. But, if bit 7 in register 0100h is set to ‘1,’ the T8208 device expects to see the CBRH before the TRH on the incoming cells.

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9 UTOPIA Interface

The

CelXpres

T8208 supports the ATM Forum’s UTOPIA level 1 and level 2 specifications for cell-level handshake

and MPHY operation with rates up to 635 Mbits/s. The device may be configured as an ATM layer or as a PHY layer by programming the phyen* bit in the main configuration 1 register (address 0100h).

The device may be configured for 16 data bit operation by setting utopia_16 bit (bit 7) in register 0112h. If the utopia-16 bit (bit 7) in register 0112h is cleared to ‘0,’ then the TX and RX UTOPIA interfaces of the T8208 are configured for 8 data bit operation.

In UTOPIA 2, 16 bit data mode, a maximum of 32 MPHYs (64 queues) are supported. In UTOPIA 2, 8-bit data mode, a maximum of 64 MPHYs (128 queues) are supported.

As an ATM layer, the device may interface with a single PHY layer or multiple PHY layers (up to 64). Also as an ATM layer, it may be configured for shared UTOPIA mode for 64 (8-bit data mode) or 32 (16-bit data mode) MPHYs. (Note that if shared UTOPIA mode is not used, the slave_en bit in the main configuration/control register (address 0110h) must be cleared at device setup.)

In PHY mode, the T8208 functions as a single PHY device on the UTOPIA bus or as one of 31 PHY devices on the UTOPIA level 2 bus.

In addition to the required UTOPIA signals, the T8208 supports an additional three transmit and three receive enable (u_txenb*[3:1] and u_rxenb*[3:1]) signals, an additional three transmit and three receive cell available (u_txclav[3:1] and u_rxclav[3:1]) signals, a transmit parity (u_txprty) signal, and a receive parity (u_rxprty) signal.

The T8208 UTOPIA signal names begin with u_tx, for UTOPIA transmit, or u_rx, for UTOPIA receive. References to transmit or receive are made relative to the UTOPIA data flow for the ATM layer UTOPIA interface. Therefore, signals starting with u_rx, such as u_rxenb*[3:0] and u_rxdata[15:0], are receive UTOPIA signals for devices in ATM mode but are transmit UTOPIA signals for devices in PHY mode. Furthermore, signals such as u_txclav[3:0] and u_txaddr[4:0] are transmit UTOPIA signals for devices in ATM mode but are receive UTOPIA signals for devices in PHY mode. The above ATM to PHY terminology will be used throughout this UTOPIA Interface section.

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9 UTOPIA Interface (continued)

9.1 Incoming UTOPIA Cell Interface

9.1.1 Incoming PHY Mode (Cells Received by T8208)

In PHY mode, only one enable (u_rxenb*[0]) signal and one cell available (u_rxclav[0]) signal are used. The

u_rxenb*[0] signal is an input connected to the ATM layer’s TxEnb* signal, and the u_rxclav[0] signal is an output connected to the ATM layer’s TxClav signal. As a PHY device, the T8208 uses only the LUT 0 configuration/status register (address 0320h) and PHY port 0 configuration structure register (addresses 4200h—4202h). For UTOPIA level 2 functionality, the PHY address is programmed in the addr_match bits of the UTOPIA configuration register (address 0114h), and the addr_clav_en bits of the main configuration 2 register (address 0112h) can be programmed to any value mentioned in the register except “0000.” As specified in the UTOPIA level 2 specification, during the polling process, the T8208 drives the u_rxclav[0] signal during the clock cycle following the cycle in which its address appears on the u_rxaddr pins. The u_rxclav[0] pin goes high impedance when not selected to support MPHY operation. In UTOPIA level 1, the above level 2 bits are not meaningful; therefore, the addr_clav_en bits must be programmed to “0000,” the u_rxaddr pins must be grounded, and the addr_match bits cleared.

When the T8208 device is in PHY mode, if bit 5 (dont_inhibit_rxphy_clav) of register 01 12h is cleared to ‘0,’ the

rx_clav signal is deasserted if the RX UTOPIA FIFO is considered full. If this bit is set to

‘1,’ the T8208 keeps

the rx_clav signal always asserted high indicating the capability to accept cells even if the RX UTOPIA FIFO could overrun, or is actually overrun.

9.1.2 Incoming ATM Mode (Cells Received by T8208)

In ATM mode, the T8208 may connect to PHY devices that either meet level 1 or level 2 UTOPIA specifications. If the connection is to devices that meet only UTOPIA level 1 specifications, the T8208 may access up to four of these PHY devices using the four enable (u_rxenb*[3:0]) and cell available (u_rxclav[3:0]) signals. Connection to more than one PHY device is possible only if the PHY’s data, start of cell, and parity outputs go high impedance when the device is not enabled. Polling of the cell available signals usually occurs while the current cell is received.

If the T8208 connects to PHY devices meeting level 2 UTOPIA specifications, in 8-bit data mode, up to 64 MPHY ports may be accessed. In 8-bit UTOPIA 2 mode, 64 MPHYs are supported with four RxCLAV/RxENB pairs with 16-port addressing per RxCLAV/RxENB pair. For 32 PHY ports, two RxCLAV/RxENB pairs support two groups of 16 PHY ports for a total of 32 PHY ports. In 16-bit UTOPIA 2 mode, the T8208 supports 32 PHYs with four RxCLAV/RxENB pairs with 8-port addressing per RxCLAV/RxENB pair. In ATM MPHY mode, the u_rxdata[15:0], u_rxaddr[4:0], u_rxsoc, and u_rxprty signals are connected to each PHY port. In addition, the T8208 generates the address (u_rxaddr[4:0]) signals, permitting selection and arbitration among the MPHY ports. The number of address lines used in the connection may vary from one to four, giving a maximum address value of 15. (All five address lines must be connected to provide for the NULL address.) Refer to Section 9.6, UTOPIA Pin Modes, for more information about the possible combinations of address, cell available, and enable signals. The UTOPIA specification for operation with one TxClav and one RxClav is used when the T8208 connects to multiple level 2 PHY devices.

Whether the T8208 is connected to several level 1 or level 2 PHY devices, a round robin algorithm is implemented that ensures that all PHY devices are serviced (accessed) in a timely manner. In addition, the number of clock cycles wasted for bus arbitration is minimized because polling is performed during cell transfer.

In ATM mode, all unused u_rxclav inputs require connection to ground. Note: The u_rxenb outputs are high impedance during powerup and reset. An attached PHY may interpret this

high-impedance state as an enable; however, the T8208 is not ready to properly handle input data during this time. Attach pull-up resistors to these outputs if a problem is anticipated.

When the T8208 is in ATM mode, if bit 6 (inhibit_rxuto_fifo_overrun) of register 0112h is set to ‘1,’ the T8208 prevents the RX UTOPIA FIFO from overflowing by deasserting its rx_enb* signal even though the rx_clav signal is high when polled, if the RX UTOPIA FIFO is considered full. If this bit is cleared to ‘0,’ the rx_enb* signal is not

deasserted even if the RX UTOPIA FIFO is considered full.

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9 UTOPIA Interface (continued)

9.2 Outgoing UTOPIA Cell Interface

9.2.1 Outgoing PHY Mode (Cells Sent by T8208)

In PHY mode, only one enable (u_txenb*[0]) signal and one cell available (u_txclav[0]) signal are used. The

u_txenb*[0] signal is an input connected to the ATM layer’s RxEnb* signal, and the u_txclav[0] signal is an output connected to the ATM layer’s RxClav signal. As a PHY device, the T8208 may use queue group 0 (queues 0, 1, 2, and 3) in the SDRAM and TX UTOPIA cell buffer. The div_queue bits in the main configuration 2 register (address 0112h) may be programmed to “000” for 4 queues or “111” for 1 queue, and the port_rte[127:0] bits in the TX PHY FIFO routing 0, 1, 2, 3, 4, 5, 6, and 7 registers (addresses 0170h, 0172h, 0174h, 0176h, 0178h, 017Ah, 017Ch, and 017Eh) must be programmed to zero. If only queue 0 is used, configure and use only the queue 0 registers at addresses 0440h and 2000h through 2016h. Also, if only queue 0 is used, program the mphy_select bits and priority_select bits in the routing information 1, 2, 3, and 4 registers addresses 0200h, 0202h, 0204h, and 0214h to the zero value of “110000.” If queues 0, 1, 2, and 3 are used, configure and use only the queue 0, 1, 2, and 3 registers at addresses 0440h through 0446h and 2000h through 2076h. Also, if queues 0, 1, 2, and 3 are used, only the mphy_select bits in the routing information 1, 2, and 4 registers (addresses 0200h, 0202h, and 0214h) must all be programmed to the zero value of “110000.”

For UTOPIA level 2 functionality, the PHY address is programmed in the addr_match bits of UTOPIA configuration register (address 0114h), and the addr_clav_en bits of the main configuration 2 register (address 0112h) can be programmed to any

value mentioned in the register except “0000.”

As specified in the UTOPIA level 2 specification, the T8208 drives the u_txclav[0] signal during the clock cycle following the one with its address on the u_txaddr pins. The u_txclav[0] pin goes high impedance when not selected to support MPHY operation. When the tx_utopia_hi_z bit in the main configuration 1 register (address 0100h) is cleared, the u_txsoc, u_txdata[7:0], and u_txprty outputs go high impedance when not selected, allowing multiple PHYs to be connected on the same UTOPIA bus. In UTOPIA level 1, the above level 2 bits are not meaningful; therefore, the addr_clav_en bits must be

programmed to “0000,” the u_txaddr pins must be grounded, and the addr_match bits cleared. Note: If the SDRAM is bypassed, the TX UTOPIA cell buffer in the T8208 device can be divided into a minimum of

1 queue and a maximum of 128 queues.

Note: Even though the outgoing (egress) queues are 0—3, the egress port is determined by the address match

bits in register 0114h.

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9 UTOPIA Interface (continued)

9.2.2 Outgoing ATM Mode (Cells Sent by T8208)

In ATM mode, the T8208 may connect to PHY devices that either meet level 1 or level 2 UTOPIA specifications. If connection is to devices that meet only UTOPIA level 1 specifications, the T8208 may access up to four of these PHY devices using the four enable (u_txenb*[3:0]) and cell available (u_txclav[3:0]) signals. Polling of the cell available signals occurs while the current cell is transmitted.

In ATM MPHY mode, the u_txdata[15:0], u_txaddr[4:0], u_txsoc, and u_txprty signals are connected to each PHY port. In addition, the T8208 generates the address (u_txaddr[4:0]) signals, permitting selection and arbitration among the MPHY ports. The number of address lines used in the connection may vary from one to four, giving a maximum address value of 15. (All five address lines must be connected to provide for the NULL address.) Refer to Section 9.6, UTOPIA Pin Modes, for more information about the possible combinations of address, cell available, and enable signals. The UTOPIA specification for operation with one TxClav and one RxClav is used when the T8208 connects to multiple UTOPIA 2 PHY devices.

In ATM mode, all unused u_txclav inputs require connection to ground. Note: The u_txenb outputs are high impedance during powerup and reset. An attached PHY may interpret this

high-impedance state as an enable; however, the T8208 is not ready to send data during this time. Attach pull-up resistors to these outputs if a problem is anticipated.

The TX UTOPIA cell buffer holds the next cells to be transmitted onto the UTOPIA bus. This TX UTOPIA cell buffer, which holds 256 cells, may be divided into 1, 4, 8, 16, 32, 64, or 128 queues using the div_queue bits in the main configuration 2 register (address 0112h). The number of ports that the T8208 supports determines the number of queues that should be chosen. (See Section 9.6, UTOPIA Pin Modes.) The number of cells per queue, held by the buffer, is determined by dividing 256 (maximum number of cells that TX UTOPIA cell buffer holds) by the number of queues selected (e.g., two cells per queue for 128 queues and 64 cells per queue for four queues).

Agere Systems Inc. 47

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T8208

9 UTOPIA Interface (continued)

Each port is assigned four queues in the TX UTOPIA cell buffer except in the case of 64 ports (for 8-bit UTOPIA) and 32 ports (for 16-bit UTOPIA). In the case of 64 ports (for 8-bit UTOPIA) and 32 ports (for 16-bit UTOPIA), each port is assigned two queues or a programmable number of queues per PHY. Each group of four queues is priority encoded where the lowest-numbered queue has the highest priority. Groups of four queues are shared among two ports as follows:

■ Queues 0—3 are shared between ports 0 and 1.

■ Queues 4—7 are shared between ports 2 and 3.

■ Queues 8—11 are shared between ports 4 and 5.

■ Queues 12—15 are shared between ports 6 and 7.

■ Queues 16—19 are shared between ports 8 and 9.

■ Queues 20—23 are shared between ports 10 and 11.

■ Queues 24—27 are shared between ports 12 and 13.

■ Queues 28—31 are shared between ports 14 and 15.

■ Queues 32—35 are shared between ports 16 and 17.

■ Queues 36—39 are shared between ports 18 and 19.

■ Queues 40—43 are shared between ports 20 and 21.

■ Queues 44—47 are shared between ports 22 and 23.

■ Queues 48—51 are shared between ports 24 and 25.

■ Queues 52—55 are shared between ports 26 and 27.

■ Queues 56—59 are shared between ports 28 and 29.

■ Queues 60—63 are shared between ports 30 and 31.

■ Queues 64—67 are shared between ports 32 and 33.

■ Queues 68—71 are shared between ports 34 and 35.

■ Queues 72—75 are shared between ports 36 and 37.

■ Queues 76—79 are shared between ports 38 and 39.

■ Queues 80—83 are shared between ports 40 and 41.

■ Queues 84—87 are shared between ports 42 and 43.

■ Queues 88—91 are shared between ports 44 and 45.

■ Queues 92—95 are shared between ports 46 and 47.

■ Queues 96—99 are shared between ports 48 and 49.

■ Queues 100—103 are shared between ports 50 and 51.

■ Queues 104—107 are shared between ports 52 and 53.

■ Queues 108—111 are shared between ports 54 and 55.

■ Queues 112—115 are shared between ports 56 and 57.

■ Queues 116—119 are shared between ports 58 and 59.

■ Queues 120—123 are shared between ports 60 and 61.

■ Queues 124—127 are shared between ports 62 and 63.

48 Agere Systems Inc.

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T8208

9 UTOPIA Interface (continued)

If 32 or less ports in 8-bit UTOPIA and 16 or less ports in 16-bit UTOPIA are used, then each port uses four queues with priorities from 0 to 3, where 0 is the highest priority. The lowest-numbered queue in the group of four is assigned priority 0, and the highest-numbered queue in the group is assigned priority 3. For 64 PHY ports in 8-bit UTOPIA and 32 PHY ports in 16-bit UTOPIA, any of the four queues in each group may be assigned to either the even or odd-numbered port. An example, which will be called

normal 64-port mode, assigns queues with priorities of 0 and 2 to the even-numbered ports and queues with priorities of 1 and 3 to the odd-numbered ports. The configuration of queues to ports is supported by port-rte[127:112] to [15:0] bits in the TX PHY FIFO routing 7 to 0 register structures. Please see addresses 0170h through 017Eh (Tables 113 through 120). Figure 9 illustrates the selection of ports when 64 are used.

5-7784.c F

Figure 9. Queue Priority Multiplexing

The TX UTOPIA cell buffer is kept full by cells transferred to it from the SDRAM. Each port has equal priority for transmitting onto the UTOPIA bus. The cell transmitted by any one port is determined by the priority of its queues with cells waiting to be transmitted. In addition, the number of clock cycles wasted for bus arbitration is minimized because polling is performed during cell transfer.

Cells arriving from the cell bus have their header error check (HEC) bytes removed. Therefore, the T8208 calculates the HEC and inserts it into each cell before transmitting it onto the UTOPIA bus. See Figure 10.

9.3 Counters

For each port selected in MPHY mode, two 16-bit registers (in_cnt_phyX[31:16] and in_cnt_phyX[15:0] in Table

152) are used as a 32-bit free-running incoming cell counter. Each port’s counter counts valid and misrouted incoming cells. Incoming cells are not counted if they encounter an ignore (I) bit in their translation records that is

‘1’ or if their VPI and/or VCI are out of range. The counter for port 0 is found at addresses 4000h and 4002h. See Table 152 in Section 14.3.2.3, RX UTOPIA Count Monitoring, for the addresses of other ports' incoming cell counters.

Also, for each port selected in MPHY mode, two 16-bit registers (out_cnt_phyX[31:16] and out_cnt_phyX[15:0] in Table 151) are used as a 32-bit free-running outgoing cell counter. Each port's counter counts all outgoing cells to the UTOPIA bus. The counter for port 0 is found at addresses 0600h and 0602h. See Table 151 in Section

14.3.2.2, TX UTOPIA Monitoring, for the addresses of other ports' outgoing cell counters.

CELL BUS

256 CELL FIFO

QUEUE 0 QUEUE 1 QUEUE 2 QUEUE 3

P0 P1 P2 P3 P4 P5 P6 P7 P8 P9

P10

P62 P63

TX UTOPIA PORT

PRIORITY

PORT_RTE[127:112], PORT_RTE[15:0]

IN TX PHY FIFO ROUTING 7—0

REGISTERS STARTING AT ADDRESS 0170h

QUEUE 124 QUEUE 125 QUEUE 126 QUEUE 127

DEMULTIPLEXER CONTROLLED BY

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9 UTOPIA Interface (continued)

9.3.1 Dropped Cell Counters

There is a 24-bit counter for each queue in the T8208 device that counts all dropped cells. The counter for queue 0 is found at addresses 3000h and 3002h. drop_cell_cnt [15:0] (at address 3002h) and drop_cell_cnt [23:16] (at address 3000h) count the number of dropped cells for queue 0. drop_cell_cnt_ovfl (bit 8 in register 3000h), when

set to ‘1,’ indicates that the drop cell counter has overflowed since last read by the microprocessor if clear_on_read is enabled. drop_cell_cnt_clp0 (bit 9 in register 3000h), when set to ‘1,’ indicates that the CLP = 0 cells have been discarded since last read by the microprocessor if clear_on_read is enabled.

The drop cell counters for the remaining queues (1 to 127) are at addresses 3004h to 31FEh.

9.4 55-Byte UTOPIA Mode

In this special UTOPIA mode, the T8208 transmits a 55-byte cell, as opposed to 53 bytes, on the UTOPIA bus. The extra 2 bytes are the tandem routing header received with the cell from the cell bus. These 2 bytes are appended to the beginning of the cell with the tandem routing header [15:8] byte first, followed by the tandem routing header [7:0] byte. Clearing the sp_utopia_sel* bit in the main configuration 1 register (address 0100h) enables this mode. The start of cell signal (u_txsoc) is asserted only once with the first tandem routing header byte. The T8208 may be configured for 55-byte UTOPIA mode whether it is an ATM or PHY device or in 8-bit or 16-bit UTOPIA mode (bit 7 in register 112h).

MODIFIED FROM 5-7783aF

Figure 10. TX UTOPIA Cell Handling

EXTERNAL

SDRAM

CONTROLLER

QUEUE FILL

MANAGER

EFCI

INSERTION

FECN ENA

QUEUE 0

TX UTOPIA

CELL BUFFER

(2 CELLS)

QUEUE 1

TX UTOPIA

CELL BUFFER

(2 CELLS)

QUEUE 126 TX UTOPIA

CELL BUFFER

(2 CELLS)

QUEUE 127 TX UTOPIA

CELL BUFFER

(2 CELLS)

HEC

INSERTION

53-byte CELL TO TX UTOPIA

50 Agere Systems Inc.

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9 UTOPIA Interface (continued)

9.5 Shared UTOPIA Mode

The shared UTOPIA mode allows two T8208 devices on different cell buses to share the same UTOPIA bus. Shared UTOPIA mode functionality requires the T8208 devices to be configured for ATM mode. This configuration is supported for both UTOPIA level 1 and 2 configurations. The shared mode can be used to provide system backplane redundancy or to increase the cell bus system capacity. One T8208 device is configured as master and the other as slave, using the slave_en bit in the main configuration/control register (address 110h). The master and the slave communicate to each other through the shared UTOPIA pins; u_shr_grant[1:0] and u_shr_req[3:0]. For the master, u_shr_grant[1:0] functions as the grant outputs for the cell of specific queue to be sent, and the u_shr_req[3:0] pins function as the request inputs to identify which cell of the 128 queues is to be sent. For the slave, u_shr_grant[1:0] functions as the grant input, and u_shr_req[3:0] as the request output. The configuration for the addr_clav_en bits must be the same in both devices in MCF2 (0112h) and port_rte (0170h to 017Eh) registers.

Note: The T8208 will support shared UTOPIA mode for up to 128 queues (64 MPHYs) in 8-bit UTOPIA mode and

will support only 64 queues (32 MPHYs) in 16-bit UTOPIA mode.

The TX UTOPIA cell buffers in the master and the slave may be divided into the same number of queues or different number of queues. The register settings for mast_queue_in[127:112], mast_queue_in[111:96], mast_queue_in[95:80], mast_queue_in[79:64] mast_queue_in[63:48], mast_queue_in[47:32], mast_queue_in[31:16], mast_queue_in[15:0] and slav_queue_in[127:112], slav_queue_in[111:96], slav_queue_in[95:80], slav_queue_in[79:64] slav_queue_in[63:48], slav_queue_in[47:32], slav_queue_in[31:16], and slav_queue_in[15:0] must be configured in the master device. These bits indicate which queues in the master and which queues in the slave are enabled. The master’s priority algorithm uses its mast_queue_in information to determine which waiting cell should be transmitted. The slav_queue_in (0160h to 016Eh) registers are ignored in the slave.

The transmit operation in shared UTOPIA mode is illustrated in Figure 11 for 8-bit UTOPIA mode and Figure 12 for 16-bit UTOPIA mode. For the transmit interface, all enable, start of cell, and data signals occur relative to the lowgoing start of grant signal from the master. The start of grant signal occurs every 60 clock cycles for 8-bit UTOPIA mode and 34 clock cycles for 16-bit UTOPIA mode and is always preceded by at least six clock cycles of ones.

Both devices can transmit on the TX UTOPIA bus; the master arbitrates the bus and grants the slave access via the u_shr_grant pins. When the slave has cells waiting for transmission, it makes a request for each queue (up to 128 in 8-bit UTOPIA mode and 64 in 16-bit UTOPIA mode) that contains cells. T o make this request, the slave pulls its u_shr_req pins low for one clock cycle during the queue’s request period. The request clock period for each queue is assigned relative to the master’s start of grant signal. The request period for first group of queues occurs ten clock cycles after the falling edge of the start of grant. In 8-bit UTOPIA mode, the next 31 clock cycles evaluate queues 4 to 127 and a low bit for the corresponding queue in the 128 queues represents the queue containing a cell to be sent. In 16-bit UTOPIA mode, the next 15 clock cycles evaluate queues 4 to 63 and a low bit for the corresponding queue in the 64 queues represents the queue containing a cell to be sent.

The master uses the received queue requests and a priority algorithm to determine if a slave’s cell should be transmitted before one of its own. Both master and slave have an equal chance to transmit cells if the cells have equal priority. The first bit in grant[0] is the low-going grant signal. The next six clock cycles designate the queue number of the cell to be transmitted which only requires 7 of the bits to represent any of the 128 queues in 8-bit UTOPIA mode and 6 bits to represent any of the 64 queues in 16-bit UTOPIA mode. The additional bits in the six clock cycles are reserved. The slave then has 53 cycles (8-bit UTOPIA mode) or 27 cycles (16-bit UTOPIA mode) or 55/28 cycles to transmit its cell depending on the mode.

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9 UTOPIA Interface (continued)

In UTOPIA receive mode, the master controls the UTOPIA bus, and the slave only monitors the bus. Both master and slave receive all cells and use their individual look-up tables to determine which cells are destined for their cell bus. The master controls the enable (u_rxenb[3:0]) and address (u_rxaddr[4:0]) signals to the UTOPIA bus. The slave monitors these signals to determine when the cell starts and which port is sending the cell.

In shared UTOPIA mode, the master always drives the u_rxaddr[4:0], u_txaddr[4:0], u_txsoc, u_rxenb*[3:0], and u_txenb*[3:0] signals. These signals become high impedance on the slave when the slave_en bit in the main configuration/control register (address 0110h) is set. Both the master and slave drive the u_txprty and u_txdata[7:0] signals when they transmit a cell; therefore, these signals must go high impedance when not active. Clear the tx_utopia_hi_z bit in the main configuration 1 register (address 0100h) to force the u_txprty and u_txdata[7:0] signals to a high-impedance state when inactive.

5-7786bF

Figure 11. TX UTOPIA Bus Sharing for 8-Bit UTOPIA Mode

XH0H1H2 P46P47P44 P46 P47P45

QS[6]

R[0]

QS[4] QS[2] QS[0]

INVALID INVALIDQR0 QR4 QR8

U_TXCLK

U_TXENB

U_TXSOC

U_TXDATA[7:0]

U_TXPRTY

GRANT[0]

REQUEST[0]

INVALID INVALIDQR1 QR5 QR9REQUEST[1]

INVALID INVALIDQR2 QR6 QR10REQUEST[2]

INVALID INVALIDQR3 QR7 QR11REQUEST[3]

VALID

QS[5] QS[3] QS[1]

GRANT[1]

52 Agere Systems Inc.

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T8208

9 UTOPIA Interface (continued)

5-7786cF

Figure 12. TX UTOPIA Bus Sharing for 16-Bit UTOPIA Mode

9.6 UTOPIA Pin Modes

9.6.1 UTOPIA Pin Modes for 8-Bit UTOPIA Operation

In multi-PHY mode, the T8208 interfaces with up to 64 PHY ports in 8-bit UTOPIA operation. Each port is numbered and accessed using a certain combination of the cell available/enable (Clav/Enb*) and address (Addr) signals. The addr_clav_en bits in the main configuration 2 register (address 0112h) are used to select this combination of cell available/enable and address signals. Table 17 indicates the port numbering for each of the possible configurations for 8-bit UTOPIA operation.

The first selection of zero address and four cell available/enable signals (a value of “0000” in bits 3:0 of register 0112h) is used for connection to UTOPIA level one devices. Use this selection to connect from one to four PHY devices to the T8208 in ATM mode. If only one PHY is connected, any of the four cell available signals may be connected to the PHY. For two PHY devices, connect any two, (internal port number must be matched to the Clav being used). All unused u_rxclav inputs require connection to ground. Four queues are allocated per PHY in this configuration.

The second selection of one address and four cell available/enable signals (a value of “0010” in bits 3:0 of register 0112h) is used for connection to UTOPIA level two devices. The selection may be used for up to four PHY groups of two ports each. (See Appendix 1 of

The ATM Forum Technical Committee

UTOPIA Level 2, Version 1.0 specification.) All unused u_rxclav inputs require connection to ground. Four queues are allocated per PHY in this configuration.

P40/41

R[0]

QS[4] QS[2] QS[0]

INVALID INVALIDQR0 QR4 QR8

U_TXCLK

U_TXENB

U_TXSOC

U_TXDATA[15:0]

U_TXPRTY

GRANT[0]

REQUEST[0]

INVALID INVALIDQR1 QR5 QR9REQUEST[1]

INVALID INVALIDQR2 QR6 QR10REQUEST[2]

INVALID INVALIDQR3 QR7 QR11REQUEST[3]

VALID

QS[5] QS[3] QS[1]

GRANT[1]

P42/43 P44/45 P46/47 H0/1 H2/3 HEC/00 P46/47 P44/45

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9 UTOPIA Interface (continued)

The third selection of two address and four cell available/enable signals (a value of “0101” in bits 3:0 of register 0112h) is used for connection to four UTOPIA level 2 PHY groups of four ports each. Four queues are allocated per PHY in this configuration.

The fourth selection of four address and two cell available/enable signals (a value of “0011” in bits 3:0 of register 0112h) is used for connection to two UTOPIA level 2 PHY groups of sixteen ports each. All unused u_rxclav inputs require connection to ground. Four queues are allocated per PHY in this configuration.

The fifth selection of three address and four cell available/enable signals (a value of “1011” in bits 3:0 of register 0112h) is used for connection to four UTOPIA level 2 PHY groups of eight ports each. Four queues are allocated per PHY in this configuration.

The sixth selection of four address and four cell available/enable signals (a value of “1000” in bits 3:0 of register 0112h) is used for connection to four UTOPIA level 2 PHY groups of sixteen ports each. Two queues are allocated per PHY if the normal 64-port mode described in Section 11.4 Queuing is used or a programmable number of queues can be allocated per PHY based on the settings in registers 0170h—017Eh.

Table 17. Pin Configuration for 8-Bit UTOPIA

# of

addr

# of

clav/enb*

Ports 0—7

Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7

0 4 enb*[0],

clav[0],

addr = 0

— enb*[1],

clav[1],

addr = 0

— enb*[2],

clav[2],

addr = 0

— enb*[3],

clav[3],

addr = 0

—

1 4 enb*[0],

clav[0],

addr = 0

— enb*[0],

clav[0],

addr = 2

— enb*[1],

clav[1],

addr = 0

— enb*[1],

clav[1],

addr = 2

—

2 4 enb*[0],

clav[0],

addr = 0

— enb*[0],

clav[0],

addr = 2

— enb*[0],

clav[0],

addr = 4

— enb*[0],

clav[0],

addr = 6

—

4 2 enb*[0],

clav[0],

addr = 0

enb*[0],

clav[0],

addr = 1

enb*[0],

clav[0],

addr = 2

enb*[0],

clav[0],

addr = 3

enb*[0],

clav[0],

addr = 4

enb*[0],

clav[0],

addr = 5

enb*[0],

clav[0],

addr = 6

enb*[0],

clav[0],

addr = 7

3 4 enb*[0],

clav[0],

addr = 0

— enb*[0],

clav[0],

addr = 2

— enb*[0],

clav[0],

addr = 4

— enb*[0],

clav[0],

addr = 6

—

4 4 enb*[0],

clav[0],

addr = 0

enb*[0],

clav[0],

addr = 1

enb*[0],

clav[0],

addr = 2

enb*[0],

clav[0],

addr = 3

enb*[0],

clav[0],

addr = 4

enb*[0],

clav[0],

addr = 5

enb*[0],

clav[0],

addr = 6

enb*[0],

clav[0],

addr = 7

# of

addr

# of

clav/enb*

Ports 8—15

Port 8 Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15

04 ———————— 1 4 enb*[2],

clav[2],

addr = 0

— enb*[2],

clav[2],

addr = 2

— enb*[3],

clav[3],

addr = 0

— enb*[3],

clav[3],

addr = 2

—

2 4 enb*[1],

clav[1],

addr = 0

— enb*[1],

clav[1],

addr = 2

— enb*[1],

clav[1],

addr = 4

— enb*[1],

clav[1],

addr = 6

—

4 2 enb*[0],

clav[0],

addr = 8

enb*[0],

clav[0],

addr = 9

enb*[0],

clav[0],

addr = 10

enb*[0],

clav[0],

addr = 11

enb*[0],

clav[0],

addr = 12

enb*[0],

clav[0],

addr = 13

enb*[0],

clav[0],

addr = 14

enb*[0],

clav[0],

addr = 15

3 4 enb*[0],

clav[0],

addr = 8

— enb*[0],

clav[0],

addr = 10

— enb*[0],

clav[0],

addr = 12

— enb*[0],

clav[0],

addr = 14

—

4 4 enb*[0],

clav[0],

addr = 8

enb*[0],

clav[0],

addr = 9

enb*[0],

clav[0],

addr = 10

enb*[0],

clav[0],

addr = 11

enb*[0],

clav[0],

addr = 12

enb*[0],

clav[0],

addr = 13

enb*[0],

clav[0],

addr = 14

enb*[0],

clav[0],

addr = 15

54 Agere Systems Inc.

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T8208

9 UTOPIA Interface (continued)

Table 17. Pin Configuration for 8-Bit UTOPIA (continued)

# of

addr

# of

clav/enb*

Ports 16—23

Port 16 Port 17 Port 18 Port 19 Port 20 Port 21 Port 22 Port 23

04 ———————— 14 ———————— 2 4 enb*[2],

clav[2],

addr = 0

— enb*[2],

clav[2],

addr = 2

— enb*[2],

clav[2],

addr = 4

— enb*[2],

clav[2],

addr = 6

—

4 2 enb*[1],

clav[1],

addr = 0

enb*[1],

clav[1],

addr = 1

enb*[1],

clav[1],

addr = 2

enb*[1],

clav[1],

addr = 3

enb*[1],

clav[1],

addr = 4

enb*[1],

clav[1],

addr = 5

enb*[1],

clav[1],

addr = 6

enb*[1],

clav[1],

addr = 7

3 4 enb*[1],

clav[1],

addr = 0

— enb*[1],

clav[1],

addr = 2

— enb*[1],

clav[1],

addr = 4

— enb*[1],

clav[1],

addr = 6

—

4 4 enb*[1],

clav[1],

addr = 0

enb*[1],

clav[1],

addr = 1

enb*[1],

clav[1],

addr = 2

enb*[1],

clav[1],

addr = 3

enb*[1],

clav[1],

addr = 4

enb*[1],

clav[1],

addr = 5

enb*[1],

clav[1],

addr = 6

enb*[1],

clav[1],

addr = 7

# of

addr

# of

clav/enb*

Ports 24—31

Port 24 Port 25 Port 26 Port 27 Port 28 Port 29 Port 30 Port 31

04 ———————— 14 ———————— 2 4 enb*[3],

clav[3],

addr = 0

— enb*[3],

clav[3],

addr = 2

— enb*[3],

clav[3],

addr = 4

— enb*[3],

clav[3],

addr = 6

—

4 2 enb*[1],

clav[1],

addr = 8

enb*[1],

clav[1],

addr = 9

enb*[1],

clav[1],

addr = 10

enb*[1],

clav[1],

addr = 11

enb*[1],

clav[1],

addr = 12

enb*[1],

clav[1],

addr = 13

enb*[1],

clav[1],

addr = 14

enb*[1],

clav[1],

addr = 15

3 4 enb*[1],

clav[1],

addr = 8

— enb*[1],

clav[1],

addr = 10

— enb*[1],

clav[1],

addr = 12

— enb*[1],

clav[1],

addr = 14

—

4 4 enb*[1],

clav[1],

addr = 8

enb*[1],

clav[1],

addr = 9

enb*[1],

clav[1],

addr = 10

enb*[1],

clav[1],

addr = 11

enb*[1],

clav[1],

addr = 12

enb*[1],

clav[1],

addr = 13

enb*[1],

clav[1],

addr = 14

enb*[1],

clav[1],

addr = 15

# of

addr

# of

clav/enb*

Ports 32—39

Port 32 Port 33 Port 34 Port 35 Port 36 Port 37 Port 38 Port 39

04 ———————— 14 ———————— 24 ———————— 42 ———————— 3 4 enb*[2],

clav[2],

addr = 0

— enb*[2],

clav[2],

addr = 2

— enb*[2],

clav[2],

addr = 4

— enb*[2],

clav[2],

addr = 6

—

4 4 enb*[2],

clav[2],

addr = 0

enb*[2],

clav[2],

addr = 1

enb*[2],

clav[2],

addr = 2

enb*[2],

clav[2],

addr = 3

enb*[2],

clav[2],

addr = 4

enb*[2],

clav[2],

addr = 5

enb*[2],

clav[2],

addr = 6

enb*[2],

clav[2],

addr = 7

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T8208

9 UTOPIA Interface (continued)

Table 17. Pin Configuration for 8-Bit UTOPIA (continued)

# of

addr

# of

clav/enb*

Ports 40—47

Port 40 Port 41 Port 42 Port 43 Port 44 Port 45 Port 46 Port 47

04 ———————— 14 ———————— 24 ———————— 42 ———————— 3 4 enb*[2],

clav[2],

addr = 8

— enb*[2],

clav[2],

addr = 10

— enb*[2],

clav[2],

addr = 12

— enb*[2],

clav[2],

addr = 14

—

4 4 enb*[2],

clav[2],

addr = 8

enb*[2],

clav[2],

addr = 9

enb*[2],

clav[2],

addr = 10

enb*[2],

clav[2],

addr = 11

enb*[2],

clav[2],

addr = 12

enb*[2],

clav[2],

addr = 13

enb*[2],

clav[2],

addr = 14

enb*[2],

clav[2],

addr = 15

# of

addr

# of

clav/enb*

Ports 48—55

Port 48 Port 49 Port 50 Port 51 Port 52 Port 53 Port 54 Port 55

04 ———————— 14 ———————— 24 ———————— 42 ———————— 3 4 enb*[3],

clav[3],

addr = 0

— enb*[3],

clav[3],

addr = 2

— enb*[3],

clav[3],

addr = 4

— enb*[3],

clav[3],

addr = 6

—

4 4 enb*[3],

clav[3],

addr = 0

enb*[3],

clav[3],

addr = 1

enb*[3],

clav[3],

addr = 2

enb*[3],

clav[3],

addr = 3

enb*[3],

clav[3],

addr = 4

enb*[3],

clav[3],

addr = 5

enb*[3],

clav[3],

addr = 6

enb*[3],

clav[3],

addr = 7

# of

addr

# of

clav/enb*

Ports 56—63

Port 56 Port 57 Port 58 Port 59 Port 60 Port 61 Port 62 Port 63

04 ———————— 14 ———————— 24 ———————— 42 ———————— 3 4 enb*[3],

clav[3],

addr = 8

— enb*[3],

clav[3],

addr = 10

— enb*[3],

clav[3],

addr = 12

— enb*[3],

clav[3],

addr = 14

—

4 4 enb*[3],

clav[3],

addr = 8

enb*[3],

clav[3],

addr = 9

enb*[3],

clav[3],

addr = 10

enb*[3],

clav[3],

addr = 11

enb*[3],

clav[3],

addr = 12

enb*[3],

clav[3],

addr = 13

enb*[3],

clav[3],

addr = 14

enb*[3],

clav[3],

addr = 15

56 Agere Systems Inc.

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T8208

9 UTOPIA Interface (continued)

9.6.2 UTOPIA Pin Modes for 16-Bit UTOPIA Operation

In multi-PHY mode, the T8208 interfaces with up to 32 PHY ports in 16-bit UTOPIA operation. Each port is numbered and accessed using a certain combination of the cell available/enable (Clav/Enb*) and address (Addr) signals. The addr_clav_en bits in the main configuration 2 register (address 0112h) are used to select this combination of cell available/enable and address signals. Table 18 indicates the port numbering for each of the possible configurations for 16-bit UTOPIA operation.

The first selection of zero address and four cell available/enable signals (a value of “0000” in bits 3:0 of register 0112h) is used for connection to UTOPIA level one devices. Use this selection to connect from one to four PHY devices to the T8208 in ATM mode. If only one PHY is connected, any of the four cell available signals may be connected to the PHY. For two PHY devices, connect any two. All unused u_rxclav inputs require connection to ground. Four queues are allocated per PHY in this configuration.

The ATM Forum Technical Committee

UTOPIA Level 2, Version 1.0 specification.) All unused u_rxclav inputs require connection to ground. Four queues are allocated per PHY in this configuration.

The third selection of two address and four cell available/enable signals (a value of “0101” in bits 3:0 of register 01 12h) is used for connection to four UTOPIA level 2 PHY groups of four ports each. Four queues are allocated per PHY in this configuration.

The fourth selection of three address and four cell available/enable signals (a value of “1001” in bits 3:0 of register 0112h) is used for connection to four UTOPIA level 2 PHY groups of eight ports each. Two queues are allocated per PHY if the normal 64-port mode described in Section 11.4 Queuing is used or a programmable number of queues can be allocated per PHY based on the settings in registers 0170h—017Eh.

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T8208

9 UTOPIA Interface (continued)

Table 18. Pin Configuration for 16-Bit UTOPIA

# of

addr

# of

clav/enb*

Ports 0—7

Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7

0 4 enb*[0],

clav[0],

addr = 0

— enb*[1],

clav[1],

addr = 0

— enb*[2],

clav[2],

addr = 0

— enb*[3],

clav[3],

addr = 0

—

1 4 enb*[0],

clav[0],

addr = 0

— enb*[0],

clav[0],

addr = 2

— enb*[1],

clav[1],

addr = 0

— enb*[1],

clav[1],

addr = 2

—

2 4 enb*[0],

clav[0],

addr = 0

— enb*[0],

clav[0],

addr = 2

— enb*[0],

clav[0],

addr = 4

— enb*[0],

clav[0],

addr = 6

—

3 4 enb*[0],

clav[0],

addr = 0

enb*[0],

clav[0],

addr = 1

enb*[0],

clav[0],

addr = 2

enb*[0],

clav[0],

addr = 3

enb*[0],

clav[0],

addr = 4

enb*[0],

clav[0],

addr = 5

enb*[0],

clav[0],

addr = 6

enb*[0],

clav[0],

addr = 7

# of

addr

# of

clav/enb*

Ports 8—15

Port 8 Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15

04 ———————— 1 4 enb*[2],

clav[2],

addr = 0

— enb*[2],

clav[2],

addr = 2

— enb*[3],

clav[3],

addr = 0

— enb*[3],

clav[3],

addr = 2

—

2 4 enb*[1],

clav[1],

addr = 0

— enb*[1],

clav[1],

addr = 2

— enb*[1],

clav[1],

addr = 4

— enb*[1],

clav[1],

addr = 6

—

3 4 enb*[1],

clav[1],

addr = 0

enb*[1],

clav[1],

addr = 1

enb*[1],

clav[1],

addr = 2

enb*[1],

clav[1],

addr = 3

enb*[1],

clav[1],

addr = 4

enb*[1],

clav[1],

addr = 5

enb*[1],

clav[1],

addr = 6

enb*[1],

clav[1],

addr = 7

# of

addr

# of

clav/enb*

Ports 16—23

Port 16 Port 17 Port 18 Port 19 Port 20 Port 21 Port 22 Port 23

04 ———————— 14 ———————— 2 4 enb*[2],

clav[2],

addr = 0

— enb*[2],

clav[2],

addr = 2

— enb*[2],

clav[2],

addr = 4

— enb*[2],

clav[2],

addr = 6

—

3 4 enb*[2],

clav[2],

addr = 0

enb*[2],

clav[2],

addr = 1

enb*[2],

clav[2],

addr = 2

enb*[2],

clav[2],

addr = 3

enb*[2],

clav[2],

addr = 4

enb*[2],

clav[2],

addr = 5

enb*[2],

clav[2],

addr = 6

enb*[2],

clav[2],

addr = 7

# of

addr

# of

clav/enb*

Ports 24—31

Port 24 Port 25 Port 26 Port 27 Port 28 Port 29 Port 30 Port 31

04 ———————— 14 ———————— 2 4 enb*[3],

clav[3],

addr = 0

— enb*[3],

clav[3],

addr = 2

— enb*[3],

clav[3],

addr = 4

— enb*[3],

clav[3],

addr = 6

—

3 4 enb*[3],

clav[3],

addr = 0

enb*[3],

clav[3],

addr = 1

enb*[3],

clav[3],

addr = 2

enb*[3],

clav[3],

addr = 3

enb*[3],

clav[3],

addr = 4

enb*[3],

clav[3],

addr = 5

enb*[3],

clav[3],

addr = 6

enb*[3],

clav[3],

addr = 7

58 Agere Systems Inc.

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T8208

9 UTOPIA Interface (continued)

9.7 UTOPIA Clocking

All TX UTOPIA signals in the T8208 are clocked on the rising edge of the TX UTOPIA clock, and all RX UTOPIA signals are clocked on the rising edge of the RX UTOPIA clock.

The UTOPIA specifications state that the ATM layer supplies the transmit and receive UTOPIA interface clocks to the PHY layers. The T8208 may be configured to drive these clocks or to be driven by them.

In the T8208, the clocks for transmit and receive UTOPIA interfaces may be independently derived from several sources. In addition, each of these clocks may be independently configured. The TX UTOPIA clock configuration (address 010Ch) and RX UTOPIA clock configuration (address 010Eh) registers are used to select and configure the transmit UTOPIA interface and the receive UTOPIA interface clocks, respectively. See these register descriptions for more information.

9.8 Option for Counters to Clear on Read

All the counters (addresses 0600h—06FEh, 3000h—31FEh, 4000h—40FEh, and total and special cell counters of the look-up record if the extended records mode is selected) can be cleared automatically when read by the microprocessor, if the clear_on_read bit (bit 12 in register 0112h) is set to ‘1.’ Both the registers for every PHY (and every queue for dropped cell count) must be read consecutively, (bits 31:16 first, bits 15:0 next) so that both the registers can be cleared automatically.

If this bit (bit 12 in register 0112h) is cleared to ‘0’ then the microprocessor will have to clear the counters individually by writing a ‘0’ to them after reading, if it is needed.

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10 Cell Bus Interface

10.1 General Architecture

The high bandwidth, 32-bit cell bus is used to interconnect T8208 devices. Up to 32 devices may be connected to the bus, and cell exchange may occur between any of these devices. Each cell bus frame is 16 clock cycles, and during these 16 cycles, one cell is transmitted. The T8208 is designed to operate with a maximum cell bus frequency of 66 MHz, which translates to a cell bandwidth of 1.7 Gbits/s. The maximum achievable frequency for a given bus implementation is dependent on loading and other design considerations.

In addition to the 32 bits of data, the cell bus uses four additional control signals. The four signals include a read clock, a write clock, a frame synchronization signal, and an acknowledge signal.

The read and write clocks (cb_rc* and cb_wc* pins, respectively) establish the timing for reading and writing cells on the bus and can be generated internally from the T8208 device or from an external clock source. The internal clock source offers the capability to program the required timing skew between write and read clocks. Separate pins are provided for the read and write clock signals. The read clock is used to read the cell from the cell bus, and the write clock is used to write the cell to the cell bus. Because all devices on the cell bus read and write on the same clock edge, the write clock is delayed slightly, relative to the read clock, to ensure sufficient data hold time.

The active-low frame sync (cb_fs*) is generated by the bus arbiter and indicates the first cycle of the cell bus frame in 16-user mode or the first cycle of two cell bus frames for 32-user mode. This signal is generated every 16 clock cycles for 16-user mode or every 32 clock cycles for 32-user mode.

The acknowledge (cb_ack*) signal is used to acknowledge the successful receipt of a cell. This signal is asserted low during the next request cycle by the T8208 that receives the cell. This signal is not asserted for multicast or broadcast cells. In the event of an overflow in the control cell RX FIFO, the loopback FIFO, the TX PHY FIFO, or the cell bus input FIFO, the acknowledge signal will assert low. In the case of an overflow, this signal will not assert low for multicast and broadcast cells.

When cb_disable* is asserted, the device can receive data on the cb_d*[31:0] but cannot transmit data. The device cannot assert the cb_ack* even when a valid cell is received from the cell bus, if cb_disable* is asserted.

Several T8208 devices may reside on the cell bus, but one device must be configured as bus arbiter by clearing the cb_arb_sel bit in the cell bus configuration/status register (address 0130h) or by pulling the arb_en* lead low. The cell bus arbiter receives requests for access to the bus from all resident devices during the first cycle of the cell bus frame and grants one of these requests during the last cycle of the cell bus frame. Before issuing the grant and while a cell is transmitted on the cell bus, the arbiter executes its arbitration algorithm to determine the next device to transmit on the bus. The arbiter also generates the frame synchronization signal. Software will designate only one device as cell bus arbiter, at any given time, to ensure proper operation of the bus.

A 5-bit unit address is assigned to each device (up to 32) on the bus. Each device uses this address to request cell transmission and to identify incoming cells destined for them. Each device is given a unique unit address by individually tying each address (ua*[4:0]) input high or low. The unit address inputs are active-low; therefore, a device

with its ua*[4:0] inputs tied to “10000” has address 15. Each device can also be given a unique unit address by writing the address into bits 4:0 in register 0130h, provided bit 7 in register 0130h is also set to 1. The device makes a cell transmission request by driving the two assigned bits during the request cycle, which is the first cycle of a frame. For example, device 15 uses bits 30 and 31 of the request cycle as its request bits. (See Section 10.2, Cell Bus Frames.) Also, each device uses its unit address to determine if a received cell is destined for it. (See Section 10.3, Cell Bus Routing Headers.)

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10 Cell Bus Interface (continued)

The cell bus may be configured for 16-user or 32-user mode, using the cb_usr_mode bit in the cell bus configuration/status register (address 0130h). In 16-user mode, all 16 devices assert their transmission requests during the first cycle of each frame, and the transmission grant for the next frame is given during the last cycle of the frame. In 32-user mode, the frame synchronization signal is asserted every two cell bus frames. The two frames are termed the odd and even frames. The frame synchronization signal marks the beginning of the even frame, and the odd frame starts 16 clock cycles later. During the request cycle of the even frame, devices zero through 15 assert their transmission requests, and during the request cycle of the odd frame, devices 16 through 31 assert theirs. Requests received from odd and even frames are serviced as a group, and grants are given in the order that the requests are received with the highest priority serviced first with the same priority requests serviced using a round robin algorithm. Transmission grants for the next frame are always given at the end of the current frame.

Cells to be transmitted onto the cell bus come from three sources internal to the T8208. Data cells from the UTOPIA bus are placed in the RX PHY FIFO to await transmission onto the cell bus. Control cells from the microprocessor wait in the control cell TX FIFO, and loopback cells from the cell bus wait in the loopback FIFO. Cells from these three FIFOs are priority multiplexed onto the cell bus output FIFO to be transmitted onto the cell bus.

Optional high priority can be established for data cells or control cells sent to the cell bus. If bit 9 in register 0130h

is cleared to ‘0’ then cells from the RX PHY FIFO have the highest priority, cells from the control cell TX FIFO have next highest, and finally, cells from the loopback FIFO have the lowest. If bit 9 in register 0130h is set to ‘1,’ then cells from the control cell TX FIFO have the highest priority, cells from the RX PHY FIFO have the next highest priority, and finally, cells from the loopback FIFO have the lowest priority. This bit on default is ‘0.’

Incoming cells may be broadcast, multicast, or single address types. The T8208 receiving device accepts single

address cells with an address field in the cell bus routing header that matches the device’s unit address. In addition, the device accepts all broadcast cells and certain multicast cells that it is configured to accept. (See Section

10.3.4, Multicast Routing.) Before a cell is accepted, a check is done on the previous grant to verify whether it is a valid grant or not. The receiving device verifies the cell bus routing header cyclic redundancy check (CRC-4) value in the least significant 4 bits of the cell bus routing header. It also verifies the bit interleave parity (BIP-8) value from bits 24 to 31 of the last cell bus frame cycle. If either is corrupt, the cell is discarded. If kept, cells are routed to the loopback FIFO, control FIFO, or TX PHY FIFO, based on the information in its cell bus routing header. See Section

10.3, Cell Bus Routing Headers.

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10 Cell Bus Interface (continued)

10.2 Cell Bus Frames

A cell bus frame is always 16 clock cycles. The cell bus frame has three sections (request, bus cell, and grant). During the request section, which is the first clock cycle of the frame, 16 devices assert their transmission requests onto the bus. During the bus cell section, which is the next 14 clock cycles, a cell is transmitted on the cell bus. This bus cell includes the cell bus routing header, the tandem routing header, and the 52-byte body of the cell. During the grant section, which is the last clock cycle of the frame, the grant is asserted, indicating which device may transmit its cell during the next frame. Also, during this last clock cycle, a parity vector is placed on the bus by the transmitting device so that error detection can be performed on the cell. Figure 13 illustrates the format for the cell bus frame.

Figure 13. Cell Bus Frame Format (Bit Positions for 16-User Mode)

31 16 15 0

CYCLE 0 U15 U14 U13 U12 U11 U10 U9 U8 U7 U6 U5 U4 U3 U2 U1 U0 CYCLE 1 CELL BUS ROUTING HEADER TANDEM ROUTING HEADER

CYCLE 2

GFC/

VPI[11:8]

VPI[7:0] VCI[15:0] PTICL

P CYCLE 3 PAYLOAD BYTE 0 PAYLOAD BYTE 1 PAYLOAD BYTE 2 PAYLOAD BYTE 3 CYCLE 4 PAYLOAD BYTE 4 PAYLOAD BYTE 5 PAYLOAD BYTE 6 PAYLOAD BYTE 7 CYCLE 5 PAYLOAD BYTE 8 PAYLOAD BYTE 9 PAYLOAD BYTE 10 PAYLOAD BYTE 11 CYCLE 6 PAYLOAD BYTE 12 PAYLOAD BYTE 13 PAYLOAD BYTE 14 PAYLOAD BYTE 15 CYCLE 7 PAYLOAD BYTE 16 PAYLOAD BYTE 17 PAYLOAD BYTE 18 PAYLOAD BYTE 19 CYCLE 8 PAYLOAD BYTE 20 PAYLOAD BYTE 21 PAYLOAD BYTE 22 PAYLOAD BYTE 23 CYCLE 9 PAYLOAD BYTE 24 PAYLOAD BYTE 25 PAYLOAD BYTE 26 PAYLOAD BYTE 27

CYCLE 10 PAYLOAD BYTE 28 PAYLOAD BYTE 29 PAYLOAD BYTE 30 PAYLOAD BYTE 31

CYCLE 11 PAYLOAD BYTE 32 PAYLOAD BYTE 33 PAYLOAD BYTE 34 PAYLOAD BYTE 35 CYCLE 12 PAYLOAD BYTE 36 PAYLOAD BYTE 37 PAYLOAD BYTE 38 PAYLOAD BYTE 39 CYCLE 13 PAYLOAD BYTE 40 PAYLOAD BYTE 41 PAYLOAD BYTE 42 PAYLOAD BYTE 43 CYCLE 14 PAYLOAD BYTE 44 PAYLOAD BYTE 45 PAYLOAD BYTE 46 PAYLOAD BYTE 47

CYCLE 15 BIT INTERLEAVE PARITY

—————————————————

GPG

GRANT NUMBER

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T8208

10 Cell Bus Interface (continued)

Figure 14. Cell Bus Frame Format (Bit Positions for 32-User Mode)

31 16 15 0

CYCLE 0 U15 U14 U13 U12 U11 U10 U9 U8 U7 U6 U5 U4 U3 U2 U1 U0 CYCLE 1 CELL BUS ROUTING HEADER TANDEM ROUTING HEADER

CYCLE 2

GFC/

VPI[11:8]

VPI[7:0] VCI[15:0] PTICL

CYCLE 10 PAYLOAD BYTE 28 PAYLOAD BYTE 29 PAYLOAD BYTE 30 PAYLOAD BYTE 31 CYCLE 11 PAYLOAD BYTE 32 PAYLOAD BYTE 33 PAYLOAD BYTE 34 PAYLOAD BYTE 35 CYCLE 12 PAYLOAD BYTE 36 PAYLOAD BYTE 37 PAYLOAD BYTE 38 PAYLOAD BYTE 39 CYCLE 13 PAYLOAD BYTE 40 PAYLOAD BYTE 41 PAYLOAD BYTE 42 PAYLOAD BYTE 43 CYCLE 14 PAYLOAD BYTE 44 PAYLOAD BYTE 45 PAYLOAD BYTE 46 PAYLOAD BYTE 47

CYCLE 15 BIT INTERLEAVE PARITY

—————————————————

GPG

GRANT NUMBER

CYCLE 16 U31 U30 U29 U28 U27 U26 U25 U24 U23 U22 U21 U20 U19 U 18 U17 U16 CYCLE 17 CELL BUS ROUTING HEADER TANDEM ROUTING HEADER

CYCLE 18

GFC/

VPI[11:8]

VPI[7:0] VCI[15:0] PTICL

CYCLE 19 PAYLOAD BYTE 0 PAYLOAD BYTE 1 PAYLOAD BYTE 2 PAYLOAD BYTE 3 CYCLE 20 PAYLOAD BYTE 4 PAYLOAD BYTE 5 PAYLOAD BYTE 6 PAYLOAD BYTE 7 CYCLE 21 PAYLOAD BYTE 8 PAYLOAD BYTE 9 PAYLOAD BYTE 10 PAYLOAD BYTE 11 CYCLE 22 PAYLOAD BYTE 12 PAYLOAD BYTE 13 PAYLOAD BYTE 14 PAYLOAD BYTE 15 CYCLE 23 PAYLOAD BYTE 16 PAYLOAD BYTE 17 PAYLOAD BYTE 18 PAYLOAD BYTE 19 CYCLE 24 PAYLOAD BYTE 20 PAYLOAD BYTE 21 PAYLOAD BYTE 22 PAYLOAD BYTE 23 CYCLE 25 PAYLOAD BYTE 24 PAYLOAD BYTE 25 PAYLOAD BYTE 26 PAYLOAD BYTE 27 CYCLE 26 PAYLOAD BYTE 28 PAYLOAD BYTE 29 PAYLOAD BYTE 30 PAYLOAD BYTE 31 CYCLE 27 PAYLOAD BYTE 32 PAYLOAD BYTE 33 PAYLOAD BYTE 34 PAYLOAD BYTE 35 CYCLE 28 PAYLOAD BYTE 36 PAYLOAD BYTE 37 PAYLOAD BYTE 38 PAYLOAD BYTE 39 CYCLE 29 PAYLOAD BYTE 40 PAYLOAD BYTE 41 PAYLOAD BYTE 42 PAYLOAD BYTE 43 CYCLE 30 PAYLOAD BYTE 44 PAYLOAD BYTE 45 PAYLOAD BYTE 46 PAYLOAD BYTE 47

CYCLE 31 BIT INTERLEAVE PARITY

—————————————————

GPG

GRANT NUMBER

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T8208

10 Cell Bus Interface (continued)

Devices on the cell bus make their requests during the first cycle of each frame. In 16-user mode, each device asserts a request every frame. In 32-user mode, each device asserts a request every two frames. In 32-user mode, devices with unit addresses 0 through 15 assert their requests during the even frames, and devices with unit addresses 16 through 31 assert their requests during the odd frames. During cycle 0 of their assigned frame, each device drives two of the 32 data bits available. The position of the two request bits for each device is based

on the device’s unit address. The assigned bit positions for each device are illustrated in Figure 13 and Figure 14 for 16-user and 32-user modes, respectively. For example, in the figures, the device with unit address 0 makes its requests using the 2 bits labeled as U0. Two bits, instead of one, are used for each device so the priority of the request may be included. The priority of the request is set up using the cb_req_pr bits in the main configuration/control register (address 0110h). See Table 59 in

Section 14.3, Extended Memory Registers

, for more informa-

tion. During clock cycles 1 through 14, the device that was granted the bus at the end of the previous frame sends its

bus cell. The bus cell sent includes the cell bus routing header, the tandem routing header, and the original UTOPIA cell with the header error check (HEC) byte removed. The HEC byte is removed because the cell bus does its own error check over the complete cell using the bit interleave parity byte. The HEC byte is recreated and inserted before the received cell is placed on the UTOPIA bus.

The cell bus routing header indicates the type of the cell (data, control, loopback) and its destination (single, multicast, broadcast). See Section 10.3, Cell Bus Routing Headers, for more information on the cell bus routing header structure. The tandem routing header is configured by the user.

The 32 bits of the grant section of the frame (clock cycle 15) include the bit interleave parity (BIP-8) byte, the grant parity bit, the grant enable bit, and the grant number. The most significant 8 bits of the grant section of the frame is the BIP-8 byte. The BIP-8 byte is calculated over 54 bytes, starting with the first tandem routing header byte and ending with the last payload byte. To calculate this bit interleave parity, an exclusive-OR operation is performed on

the first byte of the tandem routing header and the value “11111111.” The exclusive-OR operation then is performed on this result and the following byte. The operation is then repeated with every successive byte through the last data byte of the payload. The resulting byte becomes the BIP-8 byte of the grant section. The next 17 bits of the grant section are unused. The least significant 7 bits of the grant section are used to grant transmission requests. The grant number is located in the least significant 5 bits of the grant section and is the unit address of the device that transmits a cell during the next frame. The grant enable, bit 5, is an active-high signal that indicates if the grant is valid. Finally, the grant parity, bit 6, is the odd parity check calculated over the other six grant bits.

64 Agere Systems Inc.

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T8208

10 Cell Bus Interface (continued)

10.3 Cell Bus Routing Headers

The cell bus routing header gives information about the cell and its routing. There are seven different formats for cell bus routing headers. See Figure 15. These headers cover broadcast, multicast, and single address routing. A T8208 device on the cell bus accepts all broadcast cells and certain multicast cells that it is configured to accept. Broadcast or multicast routed cells may be data cells or control cells. The T8208 receiving device accepts single

address cells with an address field in its cell bus routing header that matches the device’s unit address. Cells, routed as single address, may be data, control, or loopback cells.

Figure 15. Cell Bus Routing Headers

The H field (b0 to b3) is the cell bus routing header cyclic redundancy check (CRC-4) calculated over the other 12 bits (b4 to b15) of the header. It is provided for cell bus routing header error detection. When cells arrive from the cell bus, the receiving device calculates the CRC-4 over the most significant 12 bits of the cell bus routing header and compares its calculation to the CRC-4 value stored in the H field of the cell bus routing header. If the two do not match, the cell is discarded.

MULTICAST CONTROL CELL HEADER

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

11— — MULTICAST NET NUMBER H

MULTICAST DATA CELL HEADER

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

1 0 — — MULTICAST NET NUMBER H

SINGLE DESTINATION DATA CELL HEADER

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

0 0————0 UNIT ADDRESS H

SINGLE DESTINATION CONTROL CELL HEADER

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

0 1————0 UNIT ADDRESS H

SINGLE DESTINATION LOOPBACK CELL HEADER

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

0 0 0 — — — 1 UNIT ADDRESS H

BROADCAST DATA CELL HEADER

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

0 0 1 ———1 ————— H

BROADCAST CONTROL CELL HEADER

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

0 1 1 ———1 ————— H

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T8208

10 Cell Bus Interface (continued)

10.3.1 Control Cells

The microprocessor connected to the T8208 may send control cells to the cell bus by writing the cell to the control cell transmit direct memory at addresses A0h to D7h (or extended memory at addresses 0900h to 0936h). After the cell is written to memory, the microprocessor sets the cntl_cell_wr bit in the main configuration/control register (address 0110h). This bit returns to zero when the cell is transmitted and memory is available to load a new control cell into the device.

Control cells accepted from the cell bus are routed to the control cell RX FIFO. The microprocessor connected to the T8208 reads the control cell at the head of the FIFO using the control cell receive direct memory at addresses 5Ch to 93h (or extended memory at addresses 07FCh to 0832h). After the microprocessor reads the cell, it sets the cntl_cell_rd bit in the main configuration/control register (address 0110h) to remove the cell from the head of the FIFO.

The microprocessor connected to the T8208 can read the cell bus routing header [15:0] and the tandem routing header [15:0] of the received control cell. The cell bus routing header [7:0] is at address 5Ch and the cell bus routing header [15:8] is at address 5Dh. The tandem routing header [7:0] is at address 5Eh and the tandem routing header [15:8] is at address 5Fh.

10.3.2 Data Cells

Data cells accepted from the cell bus are routed to the TX PHY FIFO. From the TX PHY FIFO, the cell is routed to the appropriate transmit queue using the information about the cell’s priority and the queue group to which it is destined. The priority of the cell is indicated by 2 bits obtained from the first 64 bits of the bus cell (cell bus routing header, tandem routing header, and A TM cell header). The position of these 2 bits in the cell are user programmable during configuration using the prior0_sel[5:0] and prior1_sel[5:0] bits of the routing information 3 register (address 0204h). The queue group to which the cell is destined is indicated by 5 bits obtained from the first 64 bits of the bus cell (cell bus routing header, tandem routing header, and ATM cell header). The position of these 5 bits in these headers are user programmable using the mphy1_sel[5:0] and mphy2_sel[5:0] bits of the routing information 1 register (address 0200h), the mphy0_sel[5:0] bits of the routing information 2 register (address 0202h) and the mphy3_sel[5:0] and mphy4_sel[5:0] bits of the routing information 3 register (address 0214h). See Tables 139, 140, 141, and 149 in Section 14.3, Extended Memory Registers. None of the priority or MPHY bits are required to be adjacent. For more information on queue groups, see Section 1 1.4, Queuing.

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T8208

10 Cell Bus Interface (continued)

10.3.3 Loopback Cells

A loopback cell may be sent to the cell bus for diagnostic purposes. Initially, the loopback cell is sent from one T8208 (device 1) to a second T8208 (device 2). The second T8208 (device 2) returns the cell to the first T8208 (device 1), or, if desired, the second T8208 (device 2) may send the cell on to one or more entirely different T8208 devices. Device 2 accepts the loopback cell and replaces the most significant 12 bits of the cell bus routing header with the routing_header bits in its loopback register (address 0136h). The 12 routing_header bits in the loopback register correspond to the upper 12 bits of a single destination control cell header, a multicast control cell header, or a broadcast control cell header.

To create a loopback path from device 1 to device 2, and back to device 1, coordinated control of device 1 and device 2 is needed. First, the microprocessor connected to device 2 sets up the loopback by writing the routing_header bits in the loopback register of device 2. The routing_header bits indicate a single destination control cell with a unit address field for device 1. Second, the microprocessor connected to device 1 writes a loopback cell to the control cell transmit direct memory (addresses A0h to D7h) of device 1. (See Section 10.3.1, Control Cells, of this document.) The cell bus routing header of this cell is the single destination loopback type, and the unit

address section of the header contains the address of device 2. To send the loopback cell, a ‘1' is then written to the cntl_cell_wr bit of the main configuration/control register (address 0110h).

Care must be taken to ensure that the routing_header bits in a T8208 device are not changed until any previously set up loopback cell has been received and retransmitted. If these bits are changed prematurely, misrouting will occur.

Instead of having to program the loopback register (0136h) of device 2, the tandem routing header of the incoming loopback cell (into device 2) can be used as the new cell bus routing header of the outgoing loopback cell. If the insert_cb_lpbk_hdr bit (bit 8 in register 0130h) is cleared to ‘0’ then the T8208 device uses the tandem routing header of the incoming loopback cell as the new cell bus routing header of the outgoing loopback cell and as a result, also inserts the programmed loopback header (in register 0136h) as the tandem routing header of the outgoing loopback cell. If this bit (bit 8 in register 0130h) is set to ‘1’ the T8208 inserts the programmed loopback header (in register 0136h) as the new cell bus routing header of the loopback cell.

10.3.4 Multicast Routing

The T8208 may be programmed to accept certain multicast data cells using the multicast memories at addresses E0h through FFh (or C00h through C1Eh) and C20h through FFEh. The net numbers of accepted multicast control cells are programmed in the memory space E0h through FFh (or C00h through C1Eh) and C20h through FFEh. These memory spaces hold 256 bits each. Each bit represents a multicast net number from 0 to 255.

Note: To prevent potential multicast memory errors, these memory spaces should be cleared during the initializa-

tion process.

For 8-bit UTOPIA ATM mode, the net numbers of accepted multicast data cells are programmed in the multicast number memories, which are divided among 32 queue groups. If 64 ports are used, each memory space is shared between two ports, e.g., ports zero and one use the memory assigned to PHY 0, ports two and three use the memory assigned to PHY 1, and so on.

For 16-bit UTOPIA ATM mode, the net numbers of accepted multicast data cells are programmed in the multicast number memories, which are divided among 16 queue groups. If 32 ports are used, each memory space is shared between two ports, e.g., ports zero and one use the memory assigned to PHY 0, ports two and three use the memory assigned to PHY 1, and so on.

The cell priority bits select the specific queue in the queue group to which the cell is routed. (See Section 11.4, Queuing). Note that multicast control cells use the same multicast number memory as PHY 0 multicast data cells. See Table 176 in Section 14.3, Extended Memory Registers and Table 53 in Section 14.2, Direct Memory Access Registers, respectively.

For PHY mode, multicast cells are only transmitted to queue group 0, and only the PHY port 0 and control cell multicast direct memory at addresses E0h through FFh (or C00h through C1Eh) is used. The cell priority determines the specific queue in queue group 0 to which the cell is routed. (See Section 10.3.2, Data Cells.)

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T8208

10 Cell Bus Interface (continued)

10.3.5 Broadcast Routing

Broadcast control cells are transmitted and received as described in Section 10.3.1, Control Cells. The broadcast control cell bus routing header has a broadcast control cell header type.

For ATM mode, all PHY ports receive the broadcast data cell. The cell priority bits select the specific queue in the queue group to which the cell is routed.

For PHY mode, if SDRAM is bypassed, broadcast data cells are only transmitted to queue 0. If the SDRAM is

not bypassed, broadcast data cells are only transmitted to queue group 0, and only PHY port 0 is used (although the device will take the time to try to broadcast data cells to all the ports, cells will not be stored in queue groups other than 0).

10.4 Cell Bus Arbitration

One of the T8208 devices sharing the cell bus must be configured as bus arbiter by clearing the cb_arb_sel bit in the cell bus configuration/status register (address 0130h) or by pulling the arb_en* lead low. Using an arbitration algorithm, the arbiter decides the next device to transmit on the cell bus and issues the grant signals at the end of the cell bus frame. The arbiter also generates the active-low frame synchronization signal that occurs every 16 clock cycles in 16-user mode and every 32 clock cycles in 32-user mode.

To grant transmission requests, the arbiter must analyze requests received during the request section of the current frame for 16-user mode or during two request cycles for 32-user mode. The arbitration algorithm used is round robin and based on the priority of the request and the last request granted.

The arbiter circuitry in all T8208 devices on the cell bus will synchronize to the active arbiter on the cell bus. So, when an inactive device becomes the arbiter, it will begin sending frame synchronization signals that coincide to the clock cycle that the original arbiter would have sent its next frame synchronization signal. This prevents the new arbiter from misinterpreting random signals on its first request cycle as valid requests.

The T8208 that has been configured as the bus arbiter can mask (remove) any of the active devices on the cell bus from the arbitration logic so that they will never be granted the bus. If any of the bits are set in register 12Eh (en_req_low_bp[15:0]) and register 12Ch (en_req_up_bp[15:0]), then the cell bus access requests from the corre-

sponding unit address on the bus are enabled into the arbitration logic. If any of the bits are cleared to ‘0’, access requests are masked and ignored by the arbitration logic.

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T8208

10 Cell Bus Interface (continued)

10.5 Cell Bus Monitoring

Every T8208 device monitors the cell bus for proper operation. The monitoring section of the T8208 checks for the presence of the read clock, the write clock, and the frame synchronization signal. The cb_wc_miss bit in the main interrupt status 1 register (address 0102h) is set when the write clock is inactive for 32 mclk cycles. Likewise, the cb_rc_miss bit in the main interrupt status 1 register is set when the read clock is inactive for 32 mclk cycles. In addition, the cb_fs_miss bit in the main interrupt status 1 register is set when the frame synchronization signal is inactive for greater than 16 cell bus read clock cycles for 16-user mode or for greater than 32 read clock cycles for 32-user mode. This bit is also set when the cell bus write clock is inactive for 32 mclk cycles.

When cells arrive from the cell bus, the cell bus monitoring section of the receiving device calculates the bit interleave parity value over the 54-byte field from the first tandem routing header byte through the final payload byte. If this calculated value does not match the value in bits 24 through 31 of the final clock cycle of the frame, the cell is discarded.

The T8208 detects when a device asserts transmission requests and is not granted permission within a programmable time period. The cb_grnt_to bit in the main interrupt status 1 register (address 0102h) is set when a device has not been granted permission to transmit within the number of frames programmed in the cb_req_to bits of the main configuration 3 register (address 0116h).

10.6 GTL+ Logic

For the T8208, the cell bus data, frame sync, and acknowledge signals use onboard GTL+ transceivers, and the cell bus clock signals use onboard GTL+ receivers. The GTL+ bus drivers are open drain and require terminating resistors at both ends of each line. The terminating resistor (R) may be from 40 Ω to 50 Ω and should be pulled up to 1.5 V ±

10% (VTT). The actual value of the terminating resistors should be chosen to match the bus line imped-

ance. Figure 16A below illustrates the terminating resistors and the configuration of one GTL+ bus line. The termination resistors are typically placed at the ends of the bus of the backplane.

The signal rise and fall times from the transceivers are carefully controlled to minimize out-of-band signals without affecting the overall transmission rates. These controlled signal edges, in addition to proper resistive line termination, minimize noise and ringing. The slew rate of the GTL+ buffers can be programmed using bits [2:0] of register 2Eh.

The GTL+ receiver compares its input signal to a voltage reference, cb_vref, to determine the logic level of the input. The value of the voltage reference is 2/3 V

TT and is created using the voltage divider shown in Figure 16B.

The 1 kΩ resistors are 1% because the cb_vref voltage must track V

TT by 1%. The 0.01 µF capacitor is a decou-

pling capacitor on the cb_vref input.

Figure 16. GTL+ External Circuitry

5-8011a (F)

5-8012a(F)

A. GTL+ Bus with Terminating Resistors B. GTL+ Threshold Voltage Reference

TT VTT

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T8208

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1 k

Ω ± 1%

1 k

Ω ± 1%

1 k

Ω ± 1%

cb_vref

0.01 µF

cb_vref_vss

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T8208

10 Cell Bus Interface (continued)

10.7 Cell Bus Write and Read Clocks

The read and write clocks (cb_wc* and cb_rc* pins) are supplied from an external source. The write clock should be delayed 1.5 ns to 4 ns relative to the read clock to ensure sufficient data hold time. The position of the clock source relative to the cell bus devices on the card or on connecting cards determines the actual delay that should be used. When the clock source is centrally located among the cell bus devices, a longer delay may be used. When the clock source is at either end of the cell bus devices, a shorter delay is needed. Also, a higher clock frequency requires a shorter delay.

The T8208 can generate both the read and write clocks internally for the cell bus logic, if bit 6 in register 2Eh is

cleared to ‘0’ and bit 10 in register 122h is set to ‘1.’ It includes the ability to derive these clocks from several sources (PCLK or MCLK or PLL VCO frequency [twice the MCLK]) and set the skew between the read and write clocks with a programmable granularity (bits 15:13 in register 122h). This feature is useful if the digital loopback (see Section 10.9) is to be used when the card containing the T8208 is operated outside the system.

If bit 6 in register 2Eh is cleared to ‘0’ and bit 10 in register 0122h is set to ‘1,’ then the generated read and write cell bus clocks not only drive the internal cell bus logic of this device but also come out on pins cb_gen_rc and cb_gen_wc (pins B4 and A3, respectively) of this device which can then be used to drive the remaining devices on the backplane.

Note: Due to the inherent propagation delay between the clocks that drive the cell bus logic of the generating

device and the other devices on the backplane, it is recommended that customers set bit 6 in register 2Eh to ‘1’ and set bit 10 in register 0122h to ‘1’ and route these generated clocks (through a GTL+ driver) back to the cb_wc* and cb_rc* pins (pins A10 and B10, respectively).

If this bit (bit 10 in register 0122h) is cleared to

‘0’

these 2 pins, cb_gen_rc and cb_gen_wc, are inactive and are

3-stated. In this case, bit 6 in register 2Eh is set to ‘1’ to indicate that pins A10 and B10 will be receiving clocks from a different source on the board. Please see registers 2Eh and 0122h for more details.

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T8208

10 Cell Bus Interface (continued)

10.8 Modify Cell Bus Request Priority Based on RX PHY FIFO Threshold

This allows the T8208 device to modify the request priority for a cell on the cell bus, based on the RX PHY FIFO thresholds. This feature is useful to raise the priority of cells to avoid a situation where the queue is getting filled with low priority cells and hence the high priority cells are blocking low priority cells from being sent to the cell bus.

There are two thresholds. Threshold 1 to force request priority to MEDIUM and Threshold 2 to force request priority to HIGH.

Bit 4 in register 126h, cb_prio2_thr_en when set, enables the threshold 2. Bits [3:0] in register 0126h, cb_prio2_thr, set the threshold 2.

Bit 12 in register 126h, cb_prio1_thr_en when set, enables the threshold 1. Bits [11:8] in register 0126h, cb_prio1_thr, set the threshold 1.

Note: When bits 3:2 in register 0110h are set to ‘00’ (disabled) and this feature is enabled, cells are transmitted

onto the cell bus as soon as the priority medium is reached. To prevent this, either the feature needs to be disabled or cells should not be transmitted to this FIFO.

Note: These threshold levels cannot be changed when there is data flowing through the

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10.9 Digital Loopback Before Cell Bus

The digital loopback allows loopback of all cells without requiring the cell to be sent to the cell bus. The output of the cell bus output FIFO is connected to the input of the cell bus input FIFO internally, so that the cells do not have to go through the GTL+ buffers. The cells being received on the RX UTOPIA should still be addressed properly with in-range VPI/VCI and routing information for the device to be able to loopback the cells.

Bit 7 (dig_lpbk_en) in register 2Eh must be set to ‘1’

and bit 2 (GTLTPDN) in register 2Fh must be cleared to ‘0’ to

enable a digital loopback

Cell Bus Request Priority

Bits 3:2 in Register 110h

Priority when

Threshold 1 Is Reached

Priority when

Threshold 2 Is Reached

00 = disabled medium

high

01 = low priority medium

high

10 = medium priority medium

high

11 = high priority high

high

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11 SDRAM Interface

For outgoing UTOPIA cells, the TX UTOPIA cell buffer supports 128 queues. These queues are separated into 32 queue groups, each consisting of four different priority queues as described in Section 9.2.2, Outgoing ATM Mode (Cells Sent by T8208). This cell buffer holds 256 outgoing cells. Additional buffering is provided by an external SDRAM. Connection to an external SDRAM is selected by clearing the sdram_bypass bit in the main configuration 1 register (address 0100h).

If the SDRAM is not used, it is bypassed by setting the sdram_bypass bit in the main configuration 1 register at start-up. When the SDRAM is bypassed, the minimum number of queues that the TX UTOPIA cell buffer can be divided into is 1 queue and the maximum number of queues is 128 queues (ATM mode) or 4 queues (PHY mode). The buffering available in this mode is the 256-cell internal memory (TX PHY FIFO) and up to 256 cells of the TX UTOPIA cell buffer. (The two buffers are not concatenated.) The setting of the div_queue bits in the main configuration 2 register (address 0112h) determines the number of cell locations allocated to queues of the TX UTOPIA cell buffer.

11.1 Memory Configuration

The SDRAM interface supports from 2 Mbytes to 32 Mbytes of memory. This memory size is realized using 16 Mbit or 64 Mbit devices. Table 19 below outlines the various memory configurations supported.

Table 19. Supported Memory Configurations

11.2 Powerup Sequence

The powerup sequence for the SDRAM must be performed manually before the SDRAM is enabled. Using the idle state 1 and 2 registers (addresses 0420h and 0422h), the manual access state 1 and 2 registers (addresses 0424h and 0426h), and the gen_man_acc bit in the SDRAM control register (address 0400h), follow the powerup command sequence prescribed by the SDRAM manufacturer. The T8208 does not control the chip select, the clock enable, and the DQM inputs to the SDRAM. These signals should be externally tied to the appropriate logic level or external control signal.

To manually execute SDRAM commands, first set up the idle values for CAS*, RAS*, WE*, bank select (BS), and the address signals using the cas_idle, ras_idle, we_idle, bs_idle[1:0], and addr_idle[11:0] bits in the idle state 1 and 2 registers. Then manually set up the value of these signals for the first SDRAM command using the cas_man, ras_man, we_man, bs_man[1:0], and addr_man[11:0] bits in the manual access state 1 and 2 registers. Finally,

write a ‘1’ to the gen_man_acc bit in the SDRAM control register. Writing this ‘1’ drives the CAS, RAS, WE*, BS, and address values (in the manual access state 1 and 2 registers) onto the associated pins for one SDRAM clock cycle. After the one clock cycle, these signals return to their idle state. Repeat this process, making sure minimum timing between commands is met, until the powerup process has been completed.

In the powerup sequence, configure the mode register of the SDRAM for a burst length of one and a CAS latency of two or three. With a burst length of one, sequential and interleave addressing behave the same, so the SDRAM may be configured for either addressing mode.

Number of

Devices

Device Memory Size and Data

Bus Organization

Number of

Columns

Number of

Banks

Number of

Rows

Total

Memory

1 16 Mbit, 16-bit data bus 256 2 2048 2 Mbyte 2 16 Mbit, 8-bit data bus 512 2 2048 4 Mbyte 4 16 Mbit, 4-bit data bus 1024 2 2048 8 Mbyte 1 64 Mbit, 16-bit data bus 256 4 4096 8 Mbyte 2 64 Mbit, 8-bit data bus 512 4 4096 16 Mbyte 4 64 Mbit, 4-bit data bus 1024 4 4096 32 Mbyte

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11 SDRAM Interface (contin ued)

11.3 SDRAM Interface Timing

The mclk clock is the source of the SDRAM clock (sd_clk) from the T8208. Based on the frequency of the SDRAM clock and the speed grade of the SDRAM, four timing parameters must be programmed into the SDRAM configuration register at address 0408h. These timing parameters are specified in SDRAM (mclk) clock cycles and are listed below:

■ RAS inactive to CAS active (ras2cas)—its value may be set from two to four SDRAM clock cycles.

■ CAS inactive to precharge command active (cas2pre)—its value may be set from one to four SDRAM clock

cycles.

■ Precharge command inactive to next command active (pre2cmd)—its value may be set from one to four SDRAM

clock cycles.

■ CAS before RAS (CBR) refresh command inactive to next CBR refresh command active (ref2cmd)—its value

may be set to three, seven, or fifteen SDRAM clock cycles.

Actual values for these parameters are obtained from the data sheet of the SDRAM used. For optimum performance, these parameters should be programmed to the lowest acceptable values. The earliest time that a CAS may be asserted after an RAS may be obtained from the data sheet parameter that describes the minimum time from the activate command to the read/write command. Three parameters affect the earliest time that a precharge command may follow a CAS. For read commands, a precharge command may be issued one clock earlier than the last read data. The actual number of clock cycles depends on the CAS latency needed for the device. For write commands, the earliest time that a precharge command may be issued following a CAS may be obtained from the SDRAM data sheet parameter that describes the minimum time from the last data in to the precharge command. In addition to these two parameters, the minimum time from the activate command to the precharge command may need to be considered to obtain the value for cas2pre. If the SDRAM is only accessed for queuing purposes, 28 consecutive CAS commands will be executed between the activate command and the precharge command, and the minimum time from the activate command to the precharge command does not need to be considered. If the microprocessor reads and writes the SDRAM memory, only one CAS command will be executed between the activate command and the precharge command. In this case, the minimum time from the activate command to the precharge command is significant and must be considered. The minimum time from the precharge command to the next command may be obtained from the data sheet parameter that describes the minimum time from the precharge command to the activate command. The minimum time from the CBR refresh command to the next CBR refresh command may be obtained from the data sheet. In the T8208, the minimum time from CBR refresh to any other command is 15 SDRAM clock cycles. In the data sheet, the parameters may be specified in actual time units rather than clock cycles. T o determine the number of clock cycles, divide the parameter value by the SDRAM clock period. Figure 17 below illustrates these timing parameters and the number of clock cycles needed to read or write a cell using the default values for the parameters.

5-7785bF

Figure 17. SDRAM Timing Parameters

RAS

(1)

CBR

REFRESH

{2, 3, 4}

ras2cas

CAS

(1 TO 28)

{1, 2, 3, 4}

cas2pre

PRECHARGE

(1)

{3, 7, 15}

ref2cmd

{1, 2, 3, 4}

pre2cmd

COMMAND

SINGLE COMMAND

THE BOXES REPRESENT THE NUMBER

OF IDLE CYCLES BETWEEN STATES. DEFAULT

VALUES ARE IN BOLD FOR ras2cas, cas2pre, pre2cmd , AND ref 2cmd.

(1)

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11 SDRAM Interface (continued)

11.4 Queuing

For a device configured in ATM mode, up to 32 groups of queues with four priorities per group may be configured in the SDRAM for a total of 128 queues. Therefore, the five port group address bits point to one of 32 queue groups, and the two priority bits point to one of four queues in the group. (For a description of the port group address and priority bits, see Section 10.3.2, Data Cells.) Priority bits with a value of zero represent the highest priority, and those with a value of three, the lowest priority.

If an ATM is configured to support 32 PHY ports in 8-bit UTOPIA mode (a value of “0011” in bits 3:0 of register 0112h), each port is assigned to its associated queue group as illustrated in T able 20, regardless of the value of the port_rte[127:0] bits. In this case, port 0 is assigned to queue group 0, port 1 to queue group 1, and so on.

For an A TM configured to support 64 PHY ports in 8-bit UTOPIA mode and 32 PHY ports in 16-bit UTOPIA mode, each queue group is shared between two ports as specified in Section 9.2.2, Outgoing ATM Mode (cells sent by T8208), and the four queues may be split in any way between the two ports using the port_rte[127:0] bits. T able 21 illustrates the relationship between the queue organization and the port group address/priority bits for a device configured to support 64 PHY ports in 8-bit UTOPIA mode and 32 PHY ports in 16-bit UTOPIA mode, and whose port_rte[127:0] bits are programmed to the normal 64-port mode as described in Section 9.2.2, Outgoing ATM Mode (cells sent by T8208). See the TxPHY FIFO routing 7, 6, 5, 4, 3, 2, 1, and 0 registers at addresses 0170h, 0172h, 0174h, 0176h, 0178h, 017Ah, 017Ch, and 017Eh, respectively.

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11 SDRAM Interface (contin ued)

Table 20. Queue Organization and Port Group Address/Priority Bits for 32 Ports in 8-Bit UTOPIA Mode

Port Number Queue Group Queue Number Priority Port Group Address Bits Priority Bits

0 0 0 Highest “00000” “00” 0 0 1 High “00000” “01” 0 0 2 Low “00000” “10” 0 0 3 Lowest “00000” “11” 1 1 4 Highest “00001” “00” 1 1 5 High “00001” “01” 1 1 6 Low “00001” “10” 1 1 7 Lowest “00001” “11” 2 2 8 Highest “00010” “00” 2 2 9 High “00010” “01” 2 2 10 Low “00010” “10” 2 2 11 Lowest “00010” “11” 3 3 12 Highest “00011” “00” 3 3 13 High “00011” “01” 3 3 14 Low “00011” “10” 3 3 15 Lowest “00011” “1 1” 4 4 16 Highest “00100” “00” 4 4 17 High “00100” “01” 4 4 18 Low “00100” “10” 4 4 19 Lowest “00100” “11” 5 5 20 Highest “00101” “00” 5 5 21 High “00101” “01” 5 5 22 Low “00101” “10” 5 5 23 Lowest “00101” “11” 6 6 24 Highest “00110” “00” 6 6 25 High “00110” “01” 6 6 26 Low “00110” “10” 6 6 27 Lowest “00110” “1 1” 7 7 28 Highest “00111” “00” 7 7 29 High “00111” “01” 7 7 30 Low “00111” “10” 7 7 31 Lowest “00111” “11” 8 8 32 Highest “01000” “00” 8 8 33 High “01000” “01” 8 8 34 Low “01000” “10” 8 8 35 Lowest “01000” “11” 9 9 36 Highest “01001” “00” 9 9 37 High “01001” “01” 9 9 38 Low “01001” “10” 9 9 39 Lowest “01001” “11”

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11 SDRAM Interface (continued)

Table 20. Queue Organization and Port Group Address/Priority Bits for 32 Ports in 8-Bit UTOPIA Mode

(continued)

Port Number Queue Group Queue Number Priority Port Group Address Bits Priority Bits

10 10 40 Highest “01010” “00” 10 10 41 High “01010” “01” 10 10 42 Low “01010” “10” 10 10 43 Lowest “01010” “11” 11 11 44 Highest “01011” “00” 11 11 45 High “01011” “01” 11 11 46 Low “01011” “10” 11 11 47 Lowest “01011” “11” 12 12 48 Highest “01100” “00” 12 12 49 High “01100” “01” 12 12 50 Low “01100” “10” 12 12 51 Lowest “01100” “11” 13 13 52 Highest “01101” “00” 13 13 53 High “01101” “01” 13 13 54 Low “01101” “10” 13 13 55 Lowest “01101” “11” 14 14 56 Highest “01110” “00” 14 14 57 High “01110” “01” 14 14 58 Low “ 01110” “10” 14 14 59 Lowest “01110” “11” 15 15 60 Highest “01111” “00” 15 15 61 High “01111” “01” 15 15 62 Low “01111” “10” 15 15 63 Lowest “01111” “11” 16 16 64 Highest “10000” “00” 16 16 65 High “10000” “01” 16 16 66 Low “10000” “10” 16 16 67 Lowest “10000” “11” 17 17 68 Highest “10001” “00” 17 17 69 High “10001” “01” 17 17 70 Low “10001” “10” 17 17 71 Lowest “10001” “11” 18 18 72 Highest “10010” “00” 18 18 73 High “10010” “01” 18 18 74 Low “10010” “10” 18 18 75 Lowest “10010” “11” 19 19 76 Highest “10011” “00” 19 19 77 High “10011” “01” 19 19 78 Low “10011” “10” 19 19 79 Lowest “10011” “11” 20 20 80 Highest “10100” “00” 20 20 81 High “10100” “01” 20 20 82 Low “10100” “10” 20 20 83 Lowest “10100” “11”

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11 SDRAM Interface (contin ued)

Table 20. Queue Organization and Port Group Address/Priority Bits for 32 Ports in 8-Bit UTOPIA Mode

(continued)

Port Number Queue Group Queue Number Priority Port Group Address Bits Priority Bits

21 21 84 Highest “10101” “00” 21 21 85 High “10101” “01” 21 21 86 Low “10101” “10” 21 21 87 Lowest “10101” “11” 22 22 88 Highest “10110” “00” 22 22 89 High “10110” “01” 22 22 90 Low “10110” “10” 22 22 91 Lowest “10110” “11” 23 23 92 Highest “10111” “00” 23 23 93 High “10111” “01” 23 23 94 Low “10111” “10” 23 23 95 Lowest “10111” “11” 24 24 96 Highest “11000” “00” 24 24 97 High “11000” “01” 24 24 98 Low “11000” “10” 24 24 99 Lowest “11000” “11” 25 25 100 Highest “11001” “00” 25 25 101 High “11001” “01” 25 25 102 Low “11001” “10” 25 25 103 Lowest “11001” “11” 26 26 104 Highest “11010” “00” 26 26 105 High “11010” “01” 26 26 106 Low “11010” “10” 26 26 107 Lowest “11010” “11” 27 27 108 Highest “11011” “00” 27 27 109 High “11011” “01” 27 27 110 Low “11011” “10” 27 27 111 Lowest “11011” “11” 28 28 112 Highest “11100” “00” 28 28 113 High “11100” “01” 28 28 114 Low “11100” “10” 28 28 115 Lowest “11100” “11” 29 29 116 Highest “11101” “00” 29 29 117 High “11101” “01” 29 29 118 Low “11101” “10” 29 29 119 Lowest “11101” “11” 30 30 120 Highest “11110” “00” 30 30 121 High “11110” “01” 30 30 122 Low “11110” “10” 30 30 123 Lowest “11110” “11” 31 31 124 Highest “11111” “00” 31 31 125 High “11111” “01” 31 31 126 Low “11111” “10” 31 31 127 Lowest “11111” “11”

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11 SDRAM Interface (continued)

T able 21. Queue Organ ization and Port G roup Address/Priority Bits for 64 Port s in 8-Bit UT OPIA Mode and

32 Ports in 16-Bit UTOPIA Mode

Port Number Queue Group Queue Number Priority Port Group Address Bits Priority Bits

000High“00000” “00” 0 0 2 Low “00000” “10” 101High“00000” “01” 1 0 3 Low “00000” “11” 214High“00001” “00” 2 1 6 Low “00001” “10” 315High“00001” “01” 3 1 7 Low “00001” “11” 428High“00010” “00” 4 2 10 Low “00010” “10” 529High“00010” “01” 5 2 11 Low “00010” “11” 6 3 12 High “00011” “00” 6 3 14 Low “00011” “10” 7 3 13 High “00011” “01” 7 3 15 Low “00011” “11” 8 4 16 High “00100” “00” 8 4 18 Low “00100” “10” 9 4 17 High “00100” “01”

9 4 19 Low “00100” “11” 10 5 20 High “00101” “00” 10 5 22 Low “00101” “10” 11521High“00101” “01” 11523Low“00101” “11” 12 6 24 High “00110” “00” 12 6 26 Low “00110” “10” 13 6 25 High “00110” “01” 13 6 27 Low “00110” “11” 14 7 28 High “00111” “00” 14 7 30 Low “00111” “10” 15 7 29 High “00111” “01” 15 7 31 Low “00111” “11”

16 8 32 High “01000” “00” 16 8 34 Low “01000” “10” 17 8 33 High “01000” “01” 17 8 35 Low “01000” “11” 18 9 36 High “01001” “00” 18 9 38 Low “01001” “10” 19 9 37 High “01001” “01” 19 9 39 Low “01001” “11” 20 10 40 High “01010” “00” 20 10 42 Low “01010” “10” 21 10 41 High “01010” “01” 21 10 43 Low “01010” “11”

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11 SDRAM Interface (contin ued)

Table 21. Queue Organization and Port Group Address/Priority Bits for 64 Ports in 8-Bit UTOPIA Mode and

32 Ports in 16-Bit UTOPIA Mode

(continued)

Port Number Queue Group Queue Number Priority Port Group Address Bits Priority Bits

22 11 44 High “01011” “00” 22 11 46 Low “01011” “10” 23 11 45 High “01011” “01” 23 11 47 Low “01011” “11” 24 12 48 High “01100” “00” 24 12 50 Low “01100” “10” 25 12 49 High “01100” “01” 25 12 51 Low “01100” “11” 26 13 52 High “01101” “00” 26 13 54 Low “01101” “10” 27 13 53 High “01101” “01” 27 13 55 Low “01101” “11” 28 14 56 High “01110” “00” 28 14 58 Low “01110” “10” 29 14 57 High “01110” “01” 29 14 59 Low “01110” “11” 30 15 60 High “01111” “00” 30 15 62 Low “01111” “10” 31 15 61 High “01111” “01” 31 15 63 Low “01111” “11” 32 16 64 High “10000” “00” 32 16 66 Low “10000” “10” 33 16 65 High “10000” “01” 33 16 67 Low “10000” “11” 34 17 68 High “10001” “00” 34 17 70 Low “10001” “10” 35 17 69 High “10001” “01” 35 17 71 Low “10001” “11” 36 18 72 High “10010” “00” 36 18 74 Low “10010” “10” 37 18 73 High “10010” “01” 37 18 75 Low “10010” “11” 38 19 76 High “10011” “00” 38 19 78 Low “10011” “10” 39 19 77 High “10011” “01” 39 19 79 Low “10011” “11” 40 20 80 High “10100” “00” 40 20 82 Low “10100” “10” 41 20 81 High “10100” “01” 41 20 83 Low “10100” “11”

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11 SDRAM Interface (continued)

Table 21. Queue Organization and Port Group Address/Priority Bits for 64 Ports in 8-Bit UTOPIA Mode and

32 Ports in 16-Bit UTOPIA Mode

(continued)

Port Number Queue Group Queue Number Priority Port Group Address Bits Priority Bits

42 21 84 High “10101” “00” 42 21 86 Low “10101” “10” 43 21 85 High “10101” “01” 43 21 87 Low “10101” “11” 44 22 88 High “10110” “00” 44 22 90 Low “10110” “10” 45 22 89 High “10110” “01” 45 22 91 Low “10110” “11” 46 23 92 High “10111” “00” 46 23 94 Low “10111” “10” 47 23 93 High “10111” “01” 47 23 95 Low “10111” “11” 48 24 96 High “11000” “00” 48 24 98 Low “11000” “10” 49 24 97 High “11000” “01” 49 24 99 Low “11000” “11” 50 25 100 High “11001” “00” 50 25 102 Low “11001” “10” 51 25 101 High “11001” “01” 51 25 103 Low “11001” “11” 52 26 104 High “11010” “00” 52 26 106 Low “11010” “10” 53 26 105 High “11010” “01” 53 26 107 Low “11010” “11” 54 27 108 High “11011” “00” 54 27 110 Low “11011” “10” 55 27 109 High “11011” “01” 55 27 111 Low “11011” “11” 56 28 112 High “11100” “00” 56 28 114 Low “11100” “10” 57 28 113 High “11100” “01” 57 28 115 Low “11100” “11” 58 29 116 High “11101” “00” 58 29 118 Low “11101” “10” 59 29 117 High “11101” “01” 59 29 119 Low “11101” “11” 60 30 120 High “11110” “00” 60 30 122 Low “11110” “10” 61 30 121 High “11110” “01” 61 30 123 Low “11110” “1 1” 62 31 124 High “11111” “00” 62 31 126 Low “11111” “10” 63 31 125 High “11111” “01” 63 31 127 Low “11111” “11”

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11 SDRAM Interface (contin ued)

Of the four priority queues, the highest-priority (priority zero), lowest-delay queue may be used for constant bit rate (CBR) traffic. The other three queues, in descending order of priority, may be used for variable bit rate (VBR), available bit rate (ABR), and unspecified bit rate (UBR) traffic, respectively. Generally, as the priority becomes lower, the queues become larger because lower-priority cells are likely to accumulate while higher-priority cells are transmitted.

The size and location of each queue is programmable using the base_addressX[24:6] and end_addrX[24:6] bits in the Queue X Definition Structure, shown in Table 173. Using these base and end address registers, the size of each queue may be programmed to a minimum of four cells and up to a maximum of 512K cells in one-cell increments.

Each queue must be disabled during queue configuration by clearing the queueX_rd_en and queueX_wr_en bits in the queue X registers (addresses 0440h through 053Eh) (shown in Table 172).

Cells sent to write-disabled queues will be discarded. Cells sent to read-disabled queues will be written into the SDRAM but never transmitted to the TX UTOPIA port. Read-disabled queues may be used, as large external memory, to store cells bound for the microprocessor. The microprocessor may use as many queues as required for different type cells. Because the microprocessor reads only 2 bytes from the SDRAM per access, the cas2pre value (see Section 11.3, SDRAM Interface Timing) may need to be larger than that required for the transferring of cells only. Therefore, to maximize the bandwidth of the SDRAM for cell bus to UTOPIA traffic, restrict microprocessor access of the SDRAM to the initialization function (e.g., downloading microcode over the cell bus).

When the microprocessor increments the read pointer to read the SDRAM, it must first write the three least significant bits (rd_pntX[8:6]) of the read pointer for the appropriate queue followed by the 16 most significant bits (rd_pntX[24:9]). This order must be followed for proper operation. All queues used for microprocessor cell reception must be at least 32 cells long. (See Queue X Definition Structure, Table 173, for more information on these bits.)

11.5 SDRAM Refresh

The T8208 SDRAM interface performs CAS before RAS (CBR) refresh commands at a rate programmed in the ref_cnt bits of the refresh register (address 0410h). The value in the refresh register represents refresh cycles in SDRAM clock cycles. One refresh command is executed every ref_cnt clock cycles, on average, when the SDRAM is idle. In addition, the value programmed in the refresh lateness register (address 0412h) represents the maximum time, in programmed refresh cycles, between actual refresh cycles. If this limit is exceeded, the ref_late bit in the SDRAM interrupt status register (address 0402h) will be set, and if the ref_late interrupt is enabled, an interrupt will be generated. The ref_late indication is provided for diagnostic purposes and does not necessarily indicate a fatal error. Bit errors in the actual cell are reported in the crc8_err_even and crc8_err_odd bits of the SDRAM interrupt status register.

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11 SDRAM Interface (continued)

11 .6 SDRAM Throughput

The SDRAM clock frequency must be fast enough for cell transfers, to and from the SDRAM, to occur without overruns to the TX PHY FIFO. Using the default values for ras2cas, cas2pre, and pre2cmd, thirty-five clock cycles are required to transfer one cell (56 bytes) into or out of the SDRAM. The assumed efficiency rate is 90%. Therefore, the number of cells per second that can be read or written into the SDRAM is calculated using the following equation:

Cell Rate = (f

mclk/35 cycles per cell x 90%)

where f

mclk is the frequency of the SDRAM clock.

The maximum UTOPIA and cell bus bandwidths must be calculated to ensure that the SDRAM clock frequency supports these bandwidths. For example, assume that the total bandwidth on the UTOPIA bus is 64 Mbits/s and that the cell bus clock rate is 33 MHz. The maximum number of cells per second that the cell bus can send is:

= 2.06 Mcells per second.

On the UTOPIA port, the total number of cells that can be sent is:

= 151 Kcells per second.

Thus, the total number of cells per second from the cell bus and to the UTOPIA bus is 2.21 Mcells per second. For the cell rate equation above, the required SDRAM clock frequency is:

* 35 cycles per cell = 86 MHz.

This is a worst-case example and assumes that all potential cells on the cell bus are going to this one device. The SDRAM frequency calculation produces a lower frequency if the actual system characteristics are considered and if the distribution of cells is controlled.

33 MHz

16 cycles per cell

--------------------------------------------- -

64 Mbits/s

53 bytes per cell 8 bits per byte×

---------------------------------------------------------------------------------------

2.21 Mcells per second

0.9

-------------------------------------------------------------

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12 Traffic Management

12.1 Cell Loss Priority (CLP)

To avoid congestion, cells with their CLP bit set may be automatically discarded upon reception at the TX PHY FIFO or upon reception at a queue in the SDRAM. The cells are discarded if the TX PHY FIFO or SDRAM queue is filled beyond the programmed limit and this feature is enabled.

For the TX PHY FIFO, this limit is programmed in the clp_fill_limit bits of the main configuration/control register (address 0110h). The feature is enabled when the cell_drop_en bit in the main configuration/control register (address 0110h) is set.

For the SDRAM queues, this limit is programmed for each queue (X) in the clp_fillX[24:9] and clp_fillX[8:6] bits in Table 173. The feature is enabled when the queueX_clp_en bit in the queue X registers (address 0440h through 053Eh) is set. When a received cell exceeds the CLP fill level for a queue, the T8208 sets the corresponding queueX_clp_lim status bit in the queue X registers. If the fill level is set to zero, the corresponding queueX_clp_lim bit is set by the first received cell for the queue. Any fill greater than zero has an inherent inaccuracy of seven cells; therefore, a fill limit of eight or less is not meaningful. The number of cells in each queue may be determined by reading the value of the read and write pointers for the specific queue.

12.2 Forward Explicit Congestion Notification (FECN)

The T8208 supports FECN for data cells using the explicit forward congestion indication (EFCI) bit in the cell header PTI. If enabled, FECN indicates cells that have encountered congestion by setting their EFCI bit. The T8208 sets the EFCI bit in cells that leave a queue that is filled beyond the limit programmed in the fecn_fillX[24:9] and fecn_fillX[8:6] bits. The T8208 only sets the EFCI bit in cells when the function is enabled by the queueX_fecn_en bit in the queue X registers (address 0440h through 053Eh). When a received cell exceeds the FECN fill level for a queue, the T8208 sets the corresponding queueX_fecn_lim status bit in the queue X registers. If the fill level is set to zero, the corresponding queueX_fecn_lim bit is set by the first received cell for the queue. Any fill greater than zero has an inherent inaccuracy of seven cells; therefore, a fill limit of eight or less is not meaningful. The number of cells in each queue may be determined by reading the value of the read and write pointers for the specific queue.

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12 Traffic Management (continued)

12.3 Partial Packet Discard (PPD)

Partial packet discard (PPD) is accomplished through the cooperation of the T8208 (source), which places the cell on the cell bus and the T8208 (destination), which receives the cell from the bus. The source T8208 uses its translation RAM to place a unique ID (PPD pointer) and PPD enable bit in the cell for each AAL5 connection. The PPD pointer and PPD enable bit may consist of any bit in the first 64 bits of the bus cell (cell bus routing header, tandem routing header, and ATM cell header) and are created at connection establishment.

The destination T8208 uses the PPD state memory (address 1000h to 13FEh) to track the state of AAL5 virtual channels for partial packet discard. Each bit in the memory represents one of 8192 potential AAL5 virtual channels. When the virtual channel connection is initially established, the bit in PPD state memory pointed to by the PPD pointer should have been cleared. When a cell that has its PPD enabled is discarded, the bit pointed to by the PPD pointer becomes set. Once this bit is set, successive cells with the same PPD pointer will be discarded until the last cell is received. The last cell is identified using the SDU-type bit in the PTI of the cell header. When the last cell of the packet is received, the virtual channel’s corresponding bit in the PPD state memory is automatically cleared, and the last cell is transmitted.

The ppd_en_sel[5:0] bits in the PPD information 1 register specify which of the bus cell’s first 64 bits (cell bus routing header, tandem routing header, and ATM cell header) enable PPD. PPD is enabled when the associated bit in the headers is one. The partial packet discard bits specify which of the bus cell’s first 64 bits are used to create the PPD pointer. These pointer bits are ppd_pnt0_sel[5:0] through ppd_pnt12_sel[5:0] in the PPD information 1 through 7 registers (addresses 0206h through 0212h). When an AAL5 virtual channel connection is initially established, its PPD bit in the PPD state memory can be cleared using the write_pul, write_val, and write_addr bits in the PPD memory write register at address 0418h.

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13 JTAG Test Access Port

A 5-pin test access port, consisting of the jtag_tclk, jtag_tms, jtag_tdi, jtag_tdo, and jtag_trst signals, provides the standard interface to the test logic. The jtag_trst signal is active-low and resets the JTAG circuitry . When jtag_trst is high, the JTAG interface is enabled. If the JTAG port is not used, jtag_trst should be tied low.

JTAG may be used only to test the inputs, outputs, and their connection to the printed-wiring board. In JTAG, serial bit patterns are shifted into the device through the jtag_tdi pin, and the results can be observed at the I/O and at the corresponding JTAG serial output, jtag_tdo. Since this JTAG conforms to the JTAG standard, the jtag_tdi and jtag_tdo may be linked to the JTAG port of other devices for systemic testing. The boundary-scan description language may be found on the Agere website.

13.1 Instruction Register

The instruction register (IR) is 3 bits in length. The instructions are defined in Table 22.

Table 22. Instruction Regist er

Instruction Binary Code Description

EXTEST “000” Places the boundary-scan register in extest mode.

SAMPLE “001” Places the boundary-scan register in sample mode.

HIGHZ “010” Places the boundary-scan register in highz mode.

RUNBIST “100” Places the boundary-scan register in runbist mode.

IDCODE “101” Places the boundary-scan register in idcode mode. BYPASS “011,” “110,” “111” Places the bypass register in the scan chain.

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13 JTAG Test Access Port (continued)

13.2 Boundary-Scan Register

The boundary-scan register (BSR) is 245 bits in length. Table 23 gives descriptions of each cell in the boundaryscan chain beginning with the least significant bit.

Table 23. Boundary-Scan Register Descriptions

Boundary-Scan

Name Pin

Name

Description

0 TR_D_OE — TR_D(0:7) are inputs when TR_D_OE = 0.

1 TR_CONT_OE — TR_OE_N, TR_WE_N, TR_A(17:0), and TR_CS(1:0) are high

impedance when TR_CONT_OE = 0. 2 U_RXCLAV0_OE — U_RXCLV0 is an input when U_RXCLAV0_OE = 0. 3 U_RXENB0_OE — U_RXENB(0) is an input when U_RXENB0_OE = 0. 4 U_RXENB_OE — U_RXENB(1:3) are inputs when U_RXENB_OE = 0. 5 U_RXADDR_OE — U_ RXADD(0:4) are inputs whe n U_RXADDR_ OE = 0. 6 U_RXCLK_OE — U_RXCLK is an input when U_RXCLK_OE = 0. 7 GPIO_OE(7) — GPIO(7) is an input when GPIO_OE(7) = 0. 8 GPIO_OE(6) — GPIO(6) is an input when GPIO_OE(6) = 0. 9 GPIO_OE(5) — GPIO(5) is an input when GPIO_OE(5) = 0.

10 GPIO_OE(4) — GPIO(4) is an input when GPIO_OE(4) = 0. 11 GPIO_OE(3) — GPIO(3) is an input when GPIO_OE(3) = 0. 12 GPIO_OE(2) — GPIO(2) is an input when GPIO_OE(2) = 0. 13 GPIO_OE(1) — GPIO(1) is an input when GPIO_OE(1) = 0. 14 GPIO_OE(0) — GPIO(0) is an input when GPIO_OE(0) = 0. 15 D_OE — D(7:0) are inputs when D_OE = 0. 16 CKO_OE — CKO is high impedance when CKO_OE = 0. 17 RDY_DTACK_N_OE — RDYDTACK is high impedance when RDY_DTACK_N_OE = 0. 18 DEVHIZ_N_HIGH_DRIV

— INT_IRQ, SD_A(11:0), SD_BS(1:0), SD_CAS_N, SD_RAS_N,

and SD_WE_N are high impedance when

DEVHIZ_N_HIGH_DRIVE = 0. 19 U_SHR_GNT_OE — U_SHR_GNT(0:1) are inputs when U_SHR_GNT_OE = 0. 20 U_TXDATA_OE — U_TXDAT(15:0) are high impedance when U_TXDATA_OE = 0. 21 U_TXPRTY_OE — U_TXPRTY is an input when U_TXPRTY_OE = 0. 22 U_TXSOC_OE — U_TXSOC is high impedance when U_TXSOC_OE = 0. 23 U_TXCLK_OE — U_TXCLK is an input when U_TXCLK_OE = 0. 24 U_TXADDR_OE — U_TXADD(4:0) are inputs when U_TXADDR_OE = 0. 25 U_TXENB_OE — U_TXENB(3:1) are high impedance when U_TXENB_OE = 0. 26 U_TXENB0_OE — U_TXENB0 is an input when U_TXENB0_OE = 0. 27 U_TXCLAV0_OE — U_TXCLV0 is an input when U_TXCLAV0_OE = 0.

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13 JTAG Test Access Port (continued)

Table 23

. Boundary-Scan Register Descriptions (continued)

Boundary-Scan

Name Pin Name Description

28 SD_CLK_OE — SD_CLK is an input when SD_CLK_OE = 0. 29 SD_D_OE — SD_D(15:0) are inputs when SD_D_OE = 0. 30 CB_GEN_OE — CB_GEN_RC and CB_GEN_WC are inputs when

CB_GEN_OE = 0.

31 U_SHR_REQ_OE — U_SHR_REQ(0:3) are inputs when

U_SHR_REQ_OE = 0. 32-39 TR_D(0:7) tr_d[0:7] Bidirectional. 40-41 TR_CS(0:1) tr_cs*[0:1] 3-statable output.

42 TR_OE_N tr_oe* 3-statable output. 43 TR_WE_N tr_we* 3-statable output.

44-61 TR_A(0:17) tr_a[0:17] 3-statable output.

62 U_RXCLV0 u_rxclav[0] Bidirectional.

63-65 U_RXCLV(1:3) u_rxclav[1:3] Input.

66 U_RXENB(0) u_rxenb*[0] Bidirectional. 67-69 U_RXENB(1:3) u_rxenb*[1:3] Bidirectional. 70-74 U_RXADD(0:4) u_rxaddr[0:4] Bidirectional.

75 U_RXCLK T1 Bidirectional.

76 U_RXSOC u_rxsoc Input.

77 U_RXPRTY u_rxprty Input. 78-93 U_RXDAT(0:15) u_rxdata[0:15] Input.

94 GPIO(7) gpio[7] Bidirectional.

95 GPIO(6) gpio[6] Bidirectional.

96 GPIO(5) gpio[5] Bidirectional.

97 GPIO(4) gpio[4] Bidirectional.

98 GPIO(3) gpio[3] Bidirectional.

99 GPIO(2) gpio[2] Bidirectional.

100 GPIO(1) gpio[1] Bidirectional. 101 GPIO(0) gpio[0] Bidirectional.

102-109 A(7:0) a[7:1]

a[0]/ale

Input.

110-117 D(7:0) d[7:0] Bidirectional.

118 CKO cko 3-statable output. 119 CKOE cko_e Input. 120 RDYDTACK rdy_dtack* 3-statable output. 121 INT_IRQ int_irq* 3-statable output.

122 SEL_N sel* Input.

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13 JTAG Test Access Port (continued)

Table 23

. Boundary-Scan Register Descriptions (continued)

Boundary-Scan

Name Pin Name Description

123 WR_N wr*_ds* Input. 124 RD_WR_N rd*_rw* Input. 125 MOTO mot_sel Input. 126 MUX mux Input.

127 RESET_N reset* Input. 128-129 U_SHR_GNT(0:1) u_shr_gnt(0:1) Bidirectional. 130-145 U_TXDAT( 15:0 ) u_txdata[15:0] 3-statable output.

146 U_TXPRTY u_txprty Bidirectional.

147 U_TXSOC u_txsoc 3-statable output.

148 U_TXCLK u_txclk Bidirectional. 149-153 U_TXADD(4:0) u_txaddr[4:0] Bidirectional. 154-156 U_TXENB(3:1) u_txenb*[3:1] 3-statable output.

157 U_TXENB0 u_txenb*[0 ] Bidirectional. 158-160 U_TXCLV(3:1 ) u_txclav[3:1] Input.

161 U_TXCLV0 u_txclav[0] Bidirectional. 162-173 SD_A(11:0) sd_a[11:0] 3-statable output.

174 SD_CLK sd_clk Bidirectional. 175-176 SD_BS(1:0) sd_bs[1:0] 3-statable output.

177 SD_RAS_N sd_ras* 3-statable output.

178 SD_CAS_N sd_cas* 3-statable output.

179 SD_WE_N sd_we* 3-statable output. 180-195 SD_D(15:0) sd_d[15:0] Bidirectional. 196-200 UA_N(4:0) ua*[4:0] Input.

201 ENARB arb_enb* Input.

202 CB_DISBL cb_disable* Input.

203 CB_ACK_N cb_ack* Bidirectional.

204 CB_F_N cb_fs* Bidirection al. 205-220 CB_D_N(0:15) cb_d*[0:15] Bidirectional.

221 CB_WC_N cb_wc* Input.

222 CB_RC_N cb_rc* Input. 223-238 CB_D_N(16:31) cb_d*[16:31] Bidirectional.

239 CB_GEN_RC_N cb_gen_rc* Bidirectional.

240 CB_GEN_WC_N cb_gen_wc* Bidirection al. 241-244 U_SHR_RE Q( 0:3 ) u_shr_req(0:3) Bidirectional.

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14 Registers

The T8208 has two distinct memory spaces: the direct memory access registers and the extended memory registers. The direct memory access registers are directly addressed 8-bit (byte) registers and are mapped between addresses 00h and FFh. The extended memory registers are indirectly addressed and mapped between addresses 0100h and 3FFFFFEh. The extended memory registers are mapped into three major blocks: the main registers, the UTOPIA registers, and the SDRAM registers. They contain the SDRAM memory, the translation RAM, internal memories, and the device’s configuration, status, and control registers. Extended memory registers are 16 bits wide, and all accesses to the extended memory registers are executed internally as 16 bits. Direct memory access registers are located in Section 14.2, Direct Memory Access Registers, and extended memory registers are located in Section 14.3, Extended Memory Registers.

14.1 Register Types

Table 24. Register Map

Read/Write (RW):

These registers may be written or read.

Read Only (RO): These registers may only be read. Read-Only Latch

(ROL):

The read-only latch is used for interrupt status registers. Reading a read-only latch register has no effect on the contents. T o clear a bit set in an ROL register, a one must be written to the bit. Writing a zero to the bit has no effect. If the corresponding interrupt enable bit is set, an interrupt will be continuously generated until the bit in the ROL register is cleared.

Write Only (WO): These registers may only be written. The write only registers in the T8208 are a pulse type.

When they are written to one, they generate a pulse internally for one clock cycle and then return to zero.

Direct Configuration/Control Register (DCCR) 28h 93 Interrupt Service Request (ISREQ) 29h 94 mclk PLL Configuration 0 (MPLLCF0) 2Ah 94 mclk PLL Configuration 1 (MPLLCF1) 2Bh 95 GTL+ Slew Rate Configuration (GTLSRCF ) 2Eh 95 GTL+ Control (GTLCNTRL) 2Fh 96 Extended Memory Address 1 (Little Endian) (EMA1_LE) 30h 97 Extended Memory Address 2 (Little Endian) (EMA2_LE) 31h 97 Extended Memory Address 3 (Little Endian) (EMA3_LE) 32h 97 Extended Memory Address 4 (Little Endian) (EMA4_LE) 33h 97 Extended Memory Access (Little Endian) (EMA_LE) 34h 97 Extended Memory Data Low (Little Endian) (EMDL_LE) 36h 98 Extended Memory Data High (Little Endian) (EMDH_LE) 37h 98 Extended Memory Address 4 (Big Endian) (EMA4_BE) 30h 99 Extended Memory Address 3 (Big Endian) (EMA3_BE) 31h 99 Extended Memory Address 2 (Big Endian) (EMA2_BE) 32h 99 Extended Memory Address 1 (Big Endian) (EMA1_BE) 33h 99 Extended Memory Access (Big Endian) (EMA_BE) 34h 100 Extended Memory Data High (Big Endian) (EMDH_BE) 36h 100 Extended Memory Data Low (Big Endian) (EMDL_BE) 37h 100 GPIO Output Enable (GPIO_OE) 39h 101 GPIO Output Value (GPIO_OV) 3Bh 101 GPIO Input Value (GPIO_IV) 3Dh 101 Control Cell Receive Direct Memory (CCRXDM) 5Ch to 93h 102 Control Cell Transmit Direct Memory (CCTXDM) A0h to D7h 102 PHY Port 0 and Control Cells Multicast Direct Memory (PP0MDM) E0h to FFh 103

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Ta ble 24. Register Map

(continued)

Main Configuration 1 (MCF1) 0100h 104 Main Interrupt Status 1 (MIS1) 0102h 105 Main Interrupt Enable 1 (MIE1) 0104h 106 TX UTOPIA Clock Configuration (TXUCCF) 010Ch 107 RX UTOPIA Clock Configuration (RXUCCF) 010Eh 108 Main Configuration/Control (MCFCT) 0110h 109 Main Configuration 2 (MCF2) 0112h 110 UTOPIA Configuration (UCF) 0114h 113 Main Configuration 3 (MCF3) 0116h 113 UTOPIA Configuration 5 (UCF5) 0118h 114 UTOPIA Configuration 4 (UCF4) 011Ah 114 UTOPIA Configuration 3 (UCF3) 011Ch 114 UTOPIA Configuration 2 (UCF2) 011Eh 114 Extended LUT Control (ELUTCN) 0120h 115 Generated Cell Bus Clocks Control Register (GCBCCR) 0122h 116 RX PHY FIFO Thresholds to Change Cell Bus Request Priority (RXPFTCRP) 0126h 118 Enable Request on Upper Backplane (ERUB) 012Ch 119 Enable Request on Lower Backplane (ERLB) 012Eh 119 Cell Bus Configuration/Status (CBCFS) 0130h 120 Main Interrupt Status 2 (MIS2) 0132h 121 Main Interrupt Enable 2 (MIE2) 0134h 122 Loopback (LB) 0136h 122 Extended LUT Configuration (ELUTCF) 0138h 122 Misrouted Cell LUT 3 (MLUT3) 013Ch 123 Misrouted Cell LUT 2 (MLUT2) 013Eh 123 Misrouted Cell LUT 1 (MLUT1) 0140h 123 Misrouted Cell LUT 0 (MLUT0) 0142h 123 Misrouted Cell LUT 4 (MLUT4) 0144h 124 Misrouted Cell Header High (MCHH) 0146h 124 Misrouted Cell Header Low (MCHL) 0148h 124 HEC Interrupt Status 3 (HIS3) 0300h 125 HEC Interrupt Status 2 (HIS2) 0302h 125 HEC Interrupt Status 1 (HIS1) 0304h 125 HEC Interrupt Status 0 (HIS0) 0306h 125 HEC Interrupt Enable 3 (HIE3) 0308h 126 HEC Interrupt Enable 2 (HIE2) 030Ah 126 HEC Interrupt Enable 1 (HIE1) 030Ch 126 HEC Interrupt Enable 0 (HIE0) 030Eh 126 HEC Interrupt Enable 3 (HIE3) 0308h 126 HEC Interrupt Enable 2 (HIE2) 030Ah 126 HEC Interrupt Enable 1 (HIE1) 030Ch 126 HEC Interrupt Enable 0 (HIE0) 030Eh 126 LUT Interrupt Service Request 3 (LUTISR3) 0310h 127 LUT Interrupt Service Request 2 (LUTISR2) 0312h 127 LUT Interrupt Service Request 1 (LUTISR1) 0314h 127 LUT Interrupt Service Request 0 (LUTISR0) 0316h 127

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Table 24. Register Map

(continued)

LUT X Configuration/Status (LUTXCFS) 0320h to 039Eh 128 Master Queue 7 (MQ7) 0150h 130 Master Queue 6 (MQ6) 0152h 130 Master Queue 5 (MQ5) 0154h 130 Master Queue 4 (MQ4) 0156h 131 Master Queue 3 (MQ3) 0158h 131 Master Queue 2 (MQ2) 015Ah 131 Master Queue 1 (MQ1) 015Ch 132 Master Queue 0 (MQ0) 015Eh 132 Slave Queue 7 (SQ7) 0160h 133 Slave Queue 6 (SQ6) 0162h 133 Slave Queue 5 (SQ5) 0164h 134 Slave Queue 4 (SQ4) 0166h 134 Slave Queue 3 (SQ3) 0168h 134 Slave Queue 2 (SQ2) 016Ah 135 Slave Queue 1 (SQ1) 016Ch 135 Slave Queue 0 (SQ0) 016Eh 135 TX PHY FIFO Routing 7 (TXPFR7) 0170h 136 TX PHY FIFO Routing 6 (TXPFR6) 0172h 137 TX PHY FIFO Routing 5 (TXPFR5) 0174h 138 TX PHY FIFO Routing 4 (TXPFR4) 0176h 139 TX PHY FIFO Routing 3 (TXPFR3) 0178h 140 TX PHY FIFO Routing 2 (TXPFR2) 017Ah 141 TX PHY FIFO Routing 1 (TXPFR1) 017Ch 142 TX PHY FIFO Routing 0 (TXPFR0) 017Eh 143 Global Bypass SDRAM Control Register (GBSCR) 01B0h 144 Bypass SDRAM Service Request Register (BSSR) 01BEh 145 Bypass SDRAM Queue Interrupt Status Register 0 (BSQISR0) 01C0h 147 Bypass SDRAM Queue Interrupt Status Register 1 (BSQISR1) 01C2h 148 Bypass SDRAM Queue Interrupt Status Register 2 (BSQISR2) 01C4h 149 Bypass SDRAM Queue Interrupt Status Register 3 (BSQISR3) 01C6h 150 Bypass SDRAM Queue Interrupt Status Register 4 (BSQISR4) 01C8h 151 Bypass SDRAM Queue Interrupt Status Register 5 (BSQISR5) 01CAh 152 Bypass SDRAM Queue Interrupt Status Register 6 (BSQISR6) 01CCh 153 Bypass SDRAM Queue Interrupt Status Register 7 (BSQISR7) 01CEh 154 Bypass SDRAM Queue Interrupt Status Register 8 (BSQISR8) 01D0h 155 Bypass SDRAM Queue Interrupt Status Register 9 (BSQISR9) 01D2h 156 Bypass SDRAM Queue Interrupt Status Register 10 (BSQISR10) 01D4h 157 Bypass SDRAM Queue Interrupt Status Register 11 (BSQISR11) 01D6h 158 Bypass SDRAM Queue Interrupt Status Register 12 (BSQISR12) 01D8h 159 Bypass SDRAM Queue Interrupt Status Register 13 (BSQISR13) 01DAh 160 Bypass SDRAM Queue Interrupt Status Register 14 (BSQISR14) 01DCh 161 Bypass SDRAM Queue Interrupt Status Register 15 (BSQISR15) 01DEh 162

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Ta ble 24. Register Map

(continued)

Routing Information 1 (RI1) 0200h 163 Routing Information 2 (RI2) 0202h 164 Routing Information 3 (RI3) 0204h 165 PPD Information 1 (PPDI1) 0206h 166 PPD Information 2 (PPDI2) 0208h 167 PPD Information 3 (PPDI3) 020Ah 168 PPD Information 4 (PPDI4) 020Ch 169 PPD Information 5 (PPDI5) 020Eh 170 PPD Information 6 (PPDI6) 0210h 171 PPD Information 7 (PPDI7) 0212h 172 Routing Information 4 (RI4) 0214h 173 PPD Memory Write (PPDMW) 0418h 174 PHY Port X Transmit Count Structure (PPXTXCNT) 0600h to 06FEh 175 PHY Port X Receive Count Structure (PPXRXCNT) 4000h to 40FEh 176 PHY Port X Configuration Structure (PPXCF) 4200h to 42FEh 176 SDRAM Control (SCT) 0400h 179 SDRAM Interrupt Status (SIS) 0402h 179 SDRAM Interrupt Enable (SIE) 0404h 179 SDRAM Configuration (SCF) 0408h 180 Refresh (RFRSH) 0410h 181 Refresh Lateness (RFRSHL) 0412h 181 Idle State 1 (IS1) 0420h 181 Idle State 2 (IS2) 0422h 181 Manual Access State 1 (MAS1) 0424h 182 Manual Access State 2 (MAS2) 0426h 182 SDRAM Interrupt Service Request 7 (SISR7) 0430h 183 SDRAM Interrupt Service Request 6 (SISR6) 0432h 183 SDRAM Interrupt Service Request 5 (SISR5) 0434h 183 SDRAM Interrupt Service Request 4 (SISR4) 0436h 183 SDRAM Interrupt Service Request 3 (SISR3) 0438h 183 SDRAM Interrupt Service Request 2 (SISR2) 043Ah 184 SDRAM Interrupt Service Request 1 (SISR1) 043Ch 184 SDRAM Interrupt Service Request 0 (SISR0) 043Eh 184 Queue X (QX) 0440h to 053Eh 185 Queue X Definition Structure (QXDEF) 2000h to 2FFEh 187 Control Cell Receive Extended Memory (CCRXEM) 07FCh to 0832h 190 Control Cell Transmit Extended Memory (CCTXEM) 0900h to 0936h 190 PHY Port 0 and Control Cells Multicast Extended Memory (PP0MEM) 0C00h to 0C1Eh 191 PHY Port X Multicast Memory (PPXMM) 0C20h to 0FFEh 192 PPD Memory (PPDM) 1000h to 13FEh 193 Queue X Dropped Cell Count (QXDCC) 3000h to 31FEh 194 Translation RAM Memory (TRAM) 100000h to 17FFFEh 197 SDRAM (SDRAM) 2000000h to 3FFFFFEh 197

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14.2 Direct Memory Access Registers

The direct memory access registers are the only registers that can be directly addressed. These registers provide some status and initial control of the device. In addition, the direct memory access register set includes some extended memory access registers, which are used to indirectly access the extended memory registers. All unde-

fined addresses in the direct memory access registers’ memory map, 00h to FFh, are reserved and should not be accessed.

Table 25. Identification 0 (IDNT0) (00h)

Table 26. Identification 1 (IDNT1) (01h)

Table 27. Identification 2 (IDNT2) (02h)

1. RN represents the current revision number of the device.

Name Bit Pos. Type Reset Description

Device ID 0 7:0 RO 4Fh Device Identification 0.

Name Bit Pos. Type Reset Description

Device ID 1 7:0 RO 08h Device Identification 1.

Name Bit Pos. Type Reset Description

Revision 7:0 RO RN

Revision Number.

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Table 28. Direct Configuration/Control Register (DCCR) (28h)

Name Bit Pos. Type Reset Description

cyc_per_acc 0 RW 0

Cycles Per Access. This bit is used to indicate the number of cycles per read/write to the translation RAM.

‘0’

= 2 mclk cycles.

‘1’

= 3 mclk cycles.

srst_reg* 1 RW 0 Software Reset Main Registers. A logic level zero on this bit resets

the main registers only. The direct memory access registers (including this one) are not affected by this reset. This bit must be ‘0’ while the mclk PLL configuration 0 and 1 registers are being modified. Activelow.

srst* 2 RW 0 Software Reset. A logic level zero on this bit resets the entire device

except the direct memory registers and the main registers. This bit must be ‘0’ while the mclk PLL configuration 0 and 1 registers are being modified and clocks are not present. Active-low.

Reserved 3 RO 0 Reserved. This bit must be programmed to ‘1.’

rplc_gfc 4 RW 0 Replace GFC. If this bit is ‘1’ and the device is in UNI mode, the GFC

field of incoming cells will be replaced during a VPI-VCI translation. If this bit is ‘0’ and the device is in UNI mode, the GFC field will be left untouched. When the device is in NNI mode or when a VPI only translation is performed, this bit has no effect.

big_end 5 RW 0 Big Endian. If this bit is ‘0,’ register fields in the direct address space,

30h to 37h, will be in little-endian format. If ‘1,’ fields in the direct address space, 30h to 37h, will be in big-endian format.

Reserved 7:6 RW 0 Reserved. These bits must be written to ‘0.’

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Table 29. Interrupt Service Request (ISREQ) (29h)

Table 30. mclk PLL Configuration 0 (MPLLCF0) (2Ah)

Name Bit

Pos.

Type Reset Description

Reserved 0 RO 0

Reserved.

int_serv_mainreg 1 RO 0 Interrupt Service Request for Main Registers. When this bit is ‘1,’

an interrupt in the main register group of the extended memory registers needs servicing. The control cell sent and control cell available status bits do not affect this bit. Only enabled interrupts will cause this bit to become set.

int_serv_sdramreg 2 RO 0 Interrupt Service Request for SDRAM Registers. When this bit is

‘1,’ an interrupt in the SDRAM register group of the extended memory registers needs servicing. Only enabled interrupts will cause this bit to become set.

int_serv_utopiareg 3 RO 0 Interrupt Service Request for UTOPIA Registers. When this bit is

‘1,’ an interrupt in the UTOPIA register group of the extended memory registers needs servicing. Only enabled interrupts will cause this bit to become set.

int_serv

_sdrambypreg

4RO 0Interrupt Service Request for SDRAM Bypass Registers. When

this bit is ‘1,’ an interrupt in the SDRAM bypass register group of the extended memory registers needs servicing. Only enabled interrupts will cause this bit to become set.

ctrl_cell_sent_sr 5 RO 0 Control Cell Sent Interrupt Service Request. When this bit is ‘1,’

the control cell sent interrupt in the main interrupt status 1 register needs servicing. The corresponding interrupt does not need to be enabled for this bit to become set.

ctrl_cell_av_sr 6 RO 0 Control Cell Available Interrupt Service Request. When this bit is

‘1,’ the control cell available interrupt in the main interrupt status 1 register needs servicing. The corresponding interrupt does not need to be enabled for this bit to become set.

Reserved 7 RO 0 Reserved.

Name Bit Pos. Type Reset Description

lf[3:0] 3:0 RW 0

Loop Filter. See Section 5, PLL Configuration, for information on these bits.

Reserved 5:4 RO 0

Reserved.

bypb 6 RW 0 Bypass PLL. If this bit is ‘0,’ the PLL is bypassed. If ‘1,’ the output of the

PLL supplies mclk.

pllen 7 RW 0 PLL Enable. If this bit is ‘1,’ the PLL is enabled. If ‘0,’ the PLL is disabled.

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Table 31. mclk PLL Configuration 1 (MPLLCF1) (2Bh)

Table 32. GTL+ Slew Rate Configuration (GTLSRCF) (2Eh)

Name Bit Pos. Type Reset Description

pll_m[4:0] 4:0 RW 0

PLL M Count Value. See Section 5, PLL Configuration, for information on these bits.

pll_n[2:0] 7:5 RW 0 PLL N Count Value. See Section 5, PLL Configuration, for information on

these bits.

Name Bit Pos. Type Reset Description

slew_rate[2:0] 2:0 RW 4h GTL+ Slew Rate Control [2:0]. The slew rates of the GTL+

(cell bus) output signals are controlled by these bits. The minimum slew rate is 0.9 ns and the maximum slew rate is 3.3 ns.

“000” = Fastest slew rate “001” “010” “011” = Nominal slew rate (on fast side) “100” = Nominal slew rate (on slow side) “101” “110”

“111” = Slowest slew rate Reserved 3 RW 1 Reserved. Program to ‘1.’ Reserved 5:4 RW 0 Reserved. Program to ‘0.’

select_gtl_clocks 6 RW 1

Select GTL+ Clocks. When this bit is cleared to

‘0,’

the cell bus clocks that clock the internal cell bus interface and cell bus circuitry are no longer sourced from the GTL+ input (pins A10 and B10) but rather from the generated clocks (pins A3 and B4), if they are enabled (bit 10 in 0122h = 1).

If these generated clocks are disabled (bit 10 in 0122h = 0), then pins A3 and B4 become 3-stated.

When this bit is set to ‘1,’ the T8208 will receive the cell bus clocks from the GTL+ pins A10 and B10.

Note: Due to the inherent propagation delay between the

clocks that drive the cell bus logic of the generating device and the other devices on the backplane, it is recommended that customers set bit 6 in register 2Eh

to ‘1’ and set bit 10 in register 0122h to ‘1’ and route these generated clocks (through a GTL+ driver) back to the cb_wc* and cb_rc* pins (pins A10 and B10, respectively).

dig_lpbk_en 7 RW 0 Digital Loopback Enable. This bit must be set to ‘1’ and bit 2

(GTLTPDN) of register 2Fh must be cleared to ‘0’ to enable a digital loopback (loopback before the cell bus). The digital loopback allows loopback of all cells without requiring the cell to be sent to the cell bus. The output of the cell bus output FIFO is connected to the input of the cell bus input FIFO internally, so that the cells do not have to go through the GTL+ buffers. The cells being received on the RX UTOPIA should still be addressed properly with the in-range VPI/VCI and routing information for the device to be able to loopback the cells.

When this bit is cleared to ‘0,’ there is no digital loopback.

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Table 33. GTL+ Control (GTLCNTRL) (2Fh)

Name Bit Pos. Type Reset Description

Reserved 0 R 1 Reserved. Program to ‘1.’

GTLRPDN 1 RW 1 GTL+ Receive Powerdown. When this bit is cleared to ‘0,’ the

GTL+ receivers on the cell bus pins are powered down. Under this condition, no cells can be received from the backplane.

When this bit is set to ‘1,’ the GTL+ receivers are powered up and cells are received from the backplane.

GTLTPDN 2 RW 1 GTL+ Transmit Powerdown. When this bit is cleared to ‘0,’

the GTL+ transmitters on the cell bus pins are powered down. Under this condition, no cells can be transmitted to the backplane.

When this bit is set to ‘1,’ the GTL+ transmitters are powered

up and cells are transmitted to the backplane. Reserved 4:3 R 0 Reserved. Program to ‘0.’ Reserved 5 R 1 Reserved. Program to ‘1.’ Reserved 7:6 R 0 Reserved. Program to ‘0.’

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14.2.1 Little-Endian Format (big_end = 0) for Extended Memory Access Registers 30h—37h

Table 34. Extended Memory Address 1 (Little Endian) (EMA1_LE) (30h)

Table 35. Extended Memory Address 2 (Little Endian) (EMA2_LE) (31h)

Table 36. Extended Memory Address 3 (Little Endian) (EMA3_LE) (32h)

Table 37. Extended Memory Address 4 (Little Endian) (EMA4_LE) (33h)

T able 38. Extended Memory Access (Little Endian) (EMA_LE) (34h)

Name B it Pos. Type Reset Description

Reserved 4:0 RO 0

Reserved.

ext_a[8:6] 7:5 RW 0

Extended Access Address [8:6]. This extended access register points to words.

Name B it Pos. Type Reset Description

ext_a[16:9] 7:0 RW 0

Extended Access Address [16:9]. This extended access register points to words.

Name B it Pos. Type Reset Description

ext_a[24:17] 7:0 RW 0

Extended Access Address [24:17]. This extended access register points to words.

Name B it Pos. Type Reset Description

ext_a[25] 0 RW 0

Extended Access Address [25]. This extended access register points to words.

Reserved 7:1 RO 0 Reserved.

Name B it Pos. Type Reset Description

ext_a[5:1] 4:0 RW 0

Extended Access Address [5:1]. This extended access register points to words. ext_a[0] is

hardwired to ‘0.’

ext_we[1:0] 6:5 RW 0

Extended Access Write Enable. These bits are active-high write enables for word accesses. If both bits are low, a read is performed. If ext_we[1] is high, the contents of ext_d[15:8] is written, and if ext_we[0] is high, the contents of ext_d[7:0] is written. If both bits are high, both data bytes are written.

ext_strt_acc 7 RW 0

Start Access to Extended Memory. Write a ‘1’ to this bit to start the access to the extended memory registers. This bit is automatically cleared when the access is complete.

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Table 39. Extended Memory Data Low (Little Endian) (EMDL_LE) (36h)

Table 40. Extended Memory Data High (Little Endian) (EMDH_LE) (37h)

Name Bit Pos. Type Reset Description

ext_d[7:0] 7:0 RW 0

Extended Access Data Low. The least significant byte of data to be written to extended memory is written here before the extended write begins. The least significant byte of data read from extended memory is available here after the extended read is complete.

Name Bit Pos. Type Reset Description

ext_d[15:8] 7:0 RW 0

Extended Access Data High. The most significant byte of data to be written to extended memory is written here before the extended write begins. The most significant byte of data read from extended memory is available here after the extended read is complete.

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14.2.2 Big-Endian Format (big_end = 1) for Extended Memory Access Registers 30h—37h

T able 41. Extended Memory Address 4 (Big Endian) (EMA4_BE) (30h)

T able 42. Extended Memory Address 3 (Big Endian) (EMA3_BE) (31h)

T able 43. Extended Memory Address 2 (Big Endian) (EMA2_BE) (32h)

T able 44. Extended Memory Address 1 (Big Endian) (EMA1_BE) (33h)

Name B it Pos. Type Reset D esc ription

ext_a[25] 0 RW 0

Extended Access Address [25]. This extended access register points to words.

Reserved 7:1 RO 0 Reserved.

Name B it Pos. Type Reset D esc ription

ext_a[24:17] 7:0 RW 0

Extended Access Address [24:17]. This extended access register points to words.

Name B it Pos. Type Reset D esc ription

ext_a[16:9] 7:0 RW 0

Extended Access Address [16:9]. This extended access register points to words.

Name B it Pos. Type Reset Desc ription

Reserved 4:0 RO 0

Reserved.

ext_a[8:6] 7:5 RW 0

Extended Access Address [8:6]. This extended access register points to words.

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Table 45. Extended Memory Access (Big Endian) (EMA_BE) (34h)

Table 46. Extended Memory Data High (Big Endian) (EMDH_BE) (36h)

Table 47. Extended Memory Data Low (Big Endian) (EMDL_BE) (37h)

Name Bit Pos. Type Reset Description

ext_a[5:1] 4:0 RW 0 Extended Access Address [5:1]. This extended access register points

to words. ext_a[0] is hardwired to ‘0.’

ext_we[1:0] 6:5 RW 0

ext_strt_acc 7 RW 0

Start Access to Extended Memory. Write a ‘1’ to this bit to start the access to the extended memory registers. This bit is automatically cleared when the access is complete.

Name Bit Pos. Type Reset Description

ext_d[15:8] 7:0 RW 0

Name Bit

Pos.

Type Reset Description

ext_d[7:0] 7:0 RW 0

Lucent Technologies Inc T8208-BAL-DB Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual