Lucent Technologies Inc T7570-ML2 Datasheet

Data Sheet October 1996
T7570 Programmable PCM Codec
with Hybrid-Balance Filter
Features
Programmable internal hybrid-balance network
Programmable transmit gain — 19.4 dB range, 0.1 dB step size
Programmable receive gain — 19.4 dB range, 0.1 dB step size
Dual-programmable PCM interface — Up to 64 time slots per frame — Variable data rate (64 kHz to 4.096 MHz) — Two timing modes
Programmable µ -law or A-law companding
300 drive receive amplifier
Analog and digital loopbacks
On-chip sample-and-hold, autozero, and precision voltage reference
Single 5 V power supply
Latch-up free, low-power CMOS technology — 70 mW typical operating power dissipation — 1.5 mW typical standby power dissipation
Serial microprocessor-control interface
6-pin parallel I/O latch
TTL- and CMOS-compatible digital I/O
Meets or exceeds D3/D4 (as per Lucent PUB
43801), ITU-T (formerly CCITT) G.711—G.714, and LSSGR requirements
Operating temperature range: –40 ° C to +85 ° C
Description
The Lucent Technologies Microelectronics Group T7570 Programmable PCM Codec with Hybrid-Bal­ance Filter is a programmable PCM codec with an internal hybrid-balance network filter. It provides ana­log-to-digital and digital-to-analog conversion, as well as the transmit and receive filtering necessary to interface a voice telephone circuit to a time-division multiplexed (TDM) system. Programmable features include transmit gain setting over a 19.4 dB range and receive gain setting over a 19.4 dB range. An internal filter can be programmed to provide hybrid balancing over a wide range of loop impedances for both active and transformer subscriber line interface circuits (SLIC).
The device is programmed over a low pin-count, standard, serial, microprocessor-control interface. A 6-pin parallel input/output latch is provided to control interface circuits. Each of these pins can be individu­ally programmed to be an input or an output.
The T7570 is f abricated by using a lo w-po wer CMOS technology, requires a single 5 V supply, and is avail­able in a 28-pin PLCC package for surf ace mounting.
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Lucent Technologies Inc.
T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996
Table of Contents
Content Page
Features ...................................................................................................................................................................1
Description ...............................................................................................................................................................1
Pin Information .........................................................................................................................................................3
Functional Description ..............................................................................................................................................5
Powerup Initialization ............................................................................................................................................5
Powerdown State ..................................................................................................................................................5
Transmit Filter and Encoder ..................................................................................................................................5
Decoder and Receive Filter ..................................................................................................................................6
PCM Interface .......................................................................................................................................................6
Serial Control Port ................................................................................................................................................6
Programmable Functions ......................................................................................................................................7
Hybrid-Balance Filter ..........................................................................................................................................11
Programming the Filter .......................................................................................................................................12
Absolute Maximum Ratings ....................................................................................................................................13
Handling Precautions .............................................................................................................................................13
Electrical Characteristics ........................................................................................................................................14
dc Characteristics ...............................................................................................................................................14
Transmission Characteristics ..................................................................................................................................15
Timing Characteristics ............................................................................................................................................20
Applications ............................................................................................................................................................25
Outline Diagrams ....................................................................................................................................................26
28-Pin PLCC .......................................................................................................................................................26
Ordering Information ...............................................................................................................................................27
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Lucent Technologies Inc.
Data Sheet T7570 Programmable PCM Codec October 1996 with Hybrid-Balance Filter
Description
(continued)
5-2786 (C)
Figure 1. Block Diagram
Pin Information
5-2787 (C)
Figure 2. Pin Diagram
HYBRID
BALANCE
FILTER
V
REF
TRANSMIT
FILTER
ANALOG LOOPBACK
RECEIVE
FILTER
IL5 IL4 IL3 IL2 IL1 IL0
INTERFACE
LATCHES
DECODER
CI
CO
CCLKCONTROL
REGISTER
RX REGISTER
D
R0
D
R1
MCLK MR
FSX BCLK FS
R
DX0 D
X1
TIME-SLOT
ASSIGN-
MENT
AZ
TX REGISTER
VFRO
DIGITAL
LOOPBACK
ENCODER
TSX0 TSX1
CS
VFXI
CI
CCLK
MR
MCLK
BCLK
D
X0
CS
12
13
14
15
16
17
18
NC
NC
VF
RO
GND
V
DD
VFXI
IL0
5 6 7 8 9 10 11
NC IL3 IL2
FSR DR1 DR0
CO
IL1 IL4 IL5 FSX
DX1
TSX1 TSX0
25 24 23 22 21 20 19
4
3
2
1
272826
T7570 --- ML2
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Lucent Technologies Inc.
T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996
Pin Information
(continued)
Table 1. Pin Description
Pin Symbol Type Name/Description
1 GND Ground . All analog and digital signals are referenced to this pin. 2VF
R
OO
Receive Analog Power Amplifier Output. This pin can drive load impedances as lo w
as 300
. PCM data received on the assigned D
R
pin is decoded and appears at this
output as a voice-frequency signal.
3NC—
No Connect. Connections may be made to or traces may be routed through this pin.
4 5
NC No Connects. Do not make connections to or route traces through pins 4 and 5.
6 7
IL3 IL2
I/O I/O
Interface Latch I/O. These pins can be individually programmed as inputs or outputs
as determined by the state of the corresponding bits in the latch direction register (LDR). For pins configured as inputs, the logic state sensed on each input is latched into the interface latch register (ILR) whenev er control data is written to the T7570, and the information is shifted out on the CO pin. When configured as outputs, control data written into the ILR appears at the corresponding IL pins.
8FS
R
I
Receive Frame-Sync Input. A pulse or square-wave waveform with an 8 kHz repeti-
tion rate is applied to this input to define the start of the receive time slot assigned to this device (nondelayed frame mode), or the start of the receive frame (delayed frame mode using the internal time-slot assignment counter).
9
10
D
R
1
D
R
0
I I
Receive PCM Inputs. These receive data input(s) are inactive except during the
assigned receive time slot of the assigned port when the receive PCM data is shifted in on the falling edges of BCLK.
11 CO O Control Output. Serial control information is shifted out from the T7570 on this pin
when is low. It can be connected to CI if required.
12 CI I
Control Input. Serial control information is shifted into the T7570 on this pin when
is low. It can be connected to CO if required.
13 CCLK I Control Clock. This cloc k shifts serial control information into CI or out from CO when
the is low, depending on the current instruction. CCLK can be asynchronous with the other system clocks.
14 I
Chip Select (Active-Low). When this pin is low, control information can be written into
or read from the T7570 via the CI and CO pins.
15 MR I Master Reset. This logic input must be pulled low for normal operation of the T7570.
When pulled momentarily high (at least 1 µ s), all programmable registers in the device are reset to the states specified under powerup initialization.
16 BCLK I
Bit Clock Input. This pin shifts PCM data into and out of the D
R
and
D
X
pins. BCLK can vary from 64 kHz to 4.096 MHz in 8 kHz increments and must be synchronous with MCLK at the start of each frame. MCLK can be used as BCLK.
17 MCLK I
Master Clock. The master-cloc k input is used by the switched capacitor filters and the
encoder and decoder sequencing logic. It must be 1.536 MHz, 1.544 MHz,
2.048 MHz, or 4.096 MHz and must be synchronous with BCLK at the start of each frame.
18 19
D
X
0
D
X
1
O O
Transmit PCM Output. These transmit-data, high-impedance state outputs remain in
the high-impedance state except during the assigned transmit time slot on the assigned port, during which the transmit PCM data byte is shifted out on the rising edges of BCLK.
20 21
X
0
X
1
O O
Backplane Line Driver Enable (Active-Low). Normally , these open-drain outputs are
floating in a high-impedance state. When a time slot is active on one of the D
X
outputs,
the appropriate
X
output pulls low to enable a backplane line driver.
CS
CS
CS
CS
TS TS
TS
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Lucent Technologies Inc.
Data Sheet T7570 Programmable PCM Codec October 1996 with Hybrid-Balance Filter
Pin Information
(continued)
Table 1. Pin Description (continued)
Pin Symbol Type Name/Description
22 FS
X
I
Transmit Frame-Sync Input. A pulse or square-wave waveform
with an 8 kHz repetition rate is applied to this input to define the start of the transmit time slot assigned to this device (nondelayed frame mode) or the start of the transmit frame (delayed frame mode using the internal time-slot assignment counter). If only the receive chan­nel is being used, it is still necessary to apply the transmit frame­sync every frame.
23 24 25 26
IL5 IL4 IL1 IL0
I/O I/O I/O I/O
Interface Latch. See pin 6.
27 V
DD
5 V ± 5% Power Supply.
28 VF
X
II
Transmit Analog High-Impedance Input. V oice-frequency signals
present on this input are encoded as an A-law or µ -law PCM bit stream and are shifted out on the selected D
X
pin.
Functional Description
Powerup Initialization
When power is first applied, powerup reset circuitry ini­tializes the T7570 and puts it into the po w erdown state . The gain control registers for the transmit and receive gain sections are programmed to off, the hybrid­balance circuit is turned off, the power amp is disabled, and the device is in the nondelayed timing mode. The latch direction register (LDR) is preset with all IL pins programmed as inputs, placing the interface pins in a high-impedance state. The CI is ready for the first con­trol byte of the initialization sequence. Other initial states in the control register are indicated in the Control Register Instruction section under Programmable Functions.
A reset to these same initial conditions can also be forced by driving the MR pin momentarily high for at least 1 µ s. This can be done either on powerup or pow­erdown. For normal operation, this pin must be pulled low.
The desired modes for all programmable functions can be initialized via the serial control port prior to a pow­erup command.
Powerdown State
Following a period of activity in the powerup state, the powerdown state can be entered by writing any of the
control instructions into the serial control port with the P bit set to 1, as indicated in Table 2.
The powerdown instruction can be included within any other instruction code. It is recommended that the chip be powered down before executing any instructions. In the powerdown state, all nonessential circuitry is de­activated and the D
X
0 and D
X
1 outputs are in the high-
impedance condition. The coefficients stored in the hybrid-balance circuit and
the gain control registers, the data in the LDR and ILR, and all control bits remain unchanged in the power­down state unless changed by writing new data via the serial control port, which remains active. The outputs of the interface latches also remain active, maintaining the ability to monitor and control interface circuits like a SLIC.
Transmit Filter and Encoder
The transmit section input, VF
X
I, provides a high-
impedance load to the line-interface circuit. The input signal is summed with the internal hybrid cancellation signal. The resulting signal is the input to a programma­ble gain or attenuation amplifier that is controlled by the contents of the transmit gain register (see Programma­ble Functions section). The signal is then passed through an antialiasing filter followed by a fifth-order, low-pass and third-order, high-pass , switched-capacitor filter. After the filter, the A/D converter translates the signal into PCM data for transmission. The A/D
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Lucent Technologies Inc.
T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996
Functional Description
(continued)
Transmit Filter and Encoder
(continued)
converter has a compressing characteristic according to the standard ITU-T A- or µ -coding laws selected by a control instruction (see Tables 2 and 3). A precision on­chip voltage reference helps ensure accurate and highly stable transmission levels. Any offset voltage arising in the gain-set amplifier, the filters, or the com­parator is canceled by an internal autozero circuit.
Decoder and Receive Filter
PCM data is shifted into the decoder's receive PCM register via the D
R
0 or D
R
1 pin during the selected time slot on eight falling edges of BCLK. The decoder con­sists of an expanding digital-to-analog convertor with either A- or µ -law decoding characteristic, which is selected by the same control instruction used to select the encode law. Following the decoder is a fifth-order, low-pass, switched-capacitor filter with Sin(x)/x correc­tion for the 8 kHz sample and hold. A programmable gain amplifier that is set by writing to the receive gain register is included, followed b y a pow er amplifier capa­ble of driving a 300 load to 4.0 V peak to peak.
PCM Interface
The FS
X
and FS
R
frame-sync inputs determine the beginning of the 8-bit transmit and receive time slots, respectively. They can have any duration from a single cycle of BCLK high to one MCLK period low. Two differ­ent relationships can be established between the frame-sync inputs and the actual time slots on the PCM buses by setting bit 3 in the control register (see Table 3). Nondelayed data mode is similar to long­frame timing of other codecs for which time slots begin nominally coincident with the rising edge of the appro­priate FS input. The alternative is to use delayed-data mode in which each FS input must be high at least a half-cycle of BCLK earlier than the time slot. The time­slot assignment circuit on the device can only be used with delayed-data timing.
The time-slot assignment capability of this device is a subset of the Lucent concentration highway interface. The beginning of the first time slot in a frame is identi­fied by the appropriate FS input. The actual transmit and receive time slots are then determined by the inter­nal time-slot assignment counters.
Transmit and receive frames and time slots can be skewed from each other by an y number of BCLK cycles by offsetting FS
R
and FS
X
. During each assigned trans-
mit time slot, the selected D
X
0/1 output shifts data out
from the PCM register on the rising edges of BCLK.
X
0 (or
X
1 as appropriate) also pulls low for the first 7.5 bit times of the time slot to control the high­impedance state enable of a backplane line driver. Serial PCM data is shifted into the selected D
R
0/1 input during each assigned receive time slot on the falling edges of BCLK. D
X
0 or D
X
1 and D
R
0 or D
R
1 are select­able on the T7570 (see the Port Selection section under Programmable Functions).
Serial Control Port
Programmable register instructions (Table 2) are writ­ten into or read back from the T7570 via the serial con­trol port consisting of the control clock (CCLK), the serial data input (CI) and output (CO), and the chip­select input ( ) (see Figure 6). All instructions require 2 bytes, with the exception of a single-byte powerup/powerdown command. The bits in byte 1 are defined as follows: bit 7 specifies powerup or power­down; bits 6, 5, 4, and 3 specify the register address; bit 2 specifies whether the instruction is a read or a write; bit 1 specifies a one- or two-byte instruction; and bit 0 is not used.
To shift control data into the T7570, CCLK must be pulsed high eight times while is low . Data on the CI input is shifted into the serial input register on the fall­ing edge of each CCLK pulse. After all data is shifted in, the contents of the input shift register are decoded and can indicate that a second byte of control data follows. This second byte can either be defined by a second byte wide pulse or can follow the first con­tiguously; it is not mandatory for to return high between the first and second control bytes.
At the end of the eighth CCLK pulse in the second con­trol byte, the data is loaded into the appropriate pro­grammable register. can remain low continuously when programming successive registers, if desired. However, should be set high when no data trans­fers are in progress.
To read back interface latch data or status information from the T7570, the first b yte of the appropriate instruc­tion, as defined in Table 2, is strobed in during the first
pulse. must then be taken low for a further eight CCLK cycles, during which the data is shifted onto the CO pin on the rising edges of CCLK. When
is high, the CO pin is in the high-impedance state, enabling the CO pins of many devices to be m ultiplex ed together.
TS
TS
CS
CS
CS
CS
CS
CS
CS CS
CS
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Lucent Technologies Inc.
Data Sheet T7570 Programmable PCM Codec October 1996 with Hybrid-Balance Filter
Functional Description (continued)
Programmable Functions
Any of the programmable registers can be modified while the device is powered up or down.
Powerup/Powerdown Control
Following powerup initialization, powerup and power­down control can be accomplished by writing any of the control instructions listed in Table 2 into the T7570, with the P bit set to 0 for powerup or 1 for powerdown. Nor­mally, it is recommended that all programmable func­tions be initially programmed while the device is powered down. Power-state control can then be
included with the last programming instruction or in a separate single-byte instruction. When the powerup or powerdown control is entered as a single-byte instruc­tion, bit 1 must be 0.
When a powerup command is given, all deactivated circuits are activated, but the PCM outputs, DX0 and DX1, remain in the high-impedance state until the sec­ond FSX pulse after powerup.
Control Register Instruction
The first byte of a read or write instruction to the control register is as shown in Table 2. The second byte has the bit functions shown in Tables 3, 5, 6, 7, 8, and 9.
Table 2. Programmable Register Instructions
Notes: Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI and CO pins. X = don't care.
P is the powerup/down control bit (0 = powerup, 1 = powerdown); see Powerup/Powerdown Control section. Other register address codes are invalid and should not be used.
Function Byte 1 Byte 2
PDN Address R/W P2 X
DATA
76543210
Single-byte Powerup/Powerdown PXXXXX0XNone Write Control Register P 000001XSee Table 3. Read Control Register P 000011X Write Interface Latch Register P 000101XSee Table 6. Read Interface Latch Register P 000111X Write Latch Direction Register P 001001XSee Table 5. Read Latch Direction Register P 001011X Write Receive Gain Register P 010001XSee Table 9. Read Receive Gain Register P 010011X Write Transmit Gain Register P 010101XSee Table 8. Read Transmit Gain Register P 010111X Write Hybrid-balance Register 1 P 011001XThese bits are defined by
the Lucent T7570 hybrid­balance software pro­gram. Contact your Lucent-ME Account Rep­resentative for a copy of this software.
Read Hybrid-balance Register 1 P 011011X Write Hybrid-balance Register 2 P 011101X Read Hybrid-balance Register 2 P 011111X Write Hybrid-balance Register 3 P 100001X Read Hybrid-balance Register 3 P 100011X
Write Receive Time Slot/Port P 100101XSee Table 7. Read Receive Time Slot/Port P 100111X(receive instruction) Write T ransmit Time Slot/Port P 101001XSee Table 7. Read Transmit Time Slot/Port P 101011X(transmit instruction)
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Lucent Technologies Inc.
T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996
Functional Description (continued)
Programmable Functions (continued)
Control Register Instruction (continued)
Table 3. Control Register Byte 2 Functions
* State at powerup initialization (bit 4 = 0).
Table 4. Coding Law Conventions
Note: The MSB is always the first PCM bit shifted in or out of the T7570.
Bit Number and Name
Function76543210
F
1 F0MA IA DN DL AL PP
0 0 ——————Reserved 0 1 ——————MCLK = 1.536 MHz or 1.544 MHz 1 0 ——————MCLK = 2.048 MHz*
1 1 ——————MCLK = 4.096 MHz —— 0 X————µ-law* —— 1 0 ————A-law, Including Even Bit Inversion —— 1 1 ————A-law, No Even Bit Inversion — 0 Delayed Data Timing — 1 Nondelayed Data Timing* ————— 0 0 —Normal Operation* ————— 1 X—Digital Loopback ————— 0 1 —Analog Loopback ——————— 0Power Amp Enabled in Powerdown ——————— 1Power Amp Disabled in Powerdown*
V
IN
µ-Law
MSB LSB
True A-Law With
Even Bit Inversion
MSB LSB
A-Law Without
Even Bit Inversion
MSB LSB
VIN = + Full Scale VIN = 0 V VIN = – Full Scale
10000000 11111111 00000000
10101010 11010101 00101010
111111111
10000000 01111111
Master Clock Frequency Selection
A master clock must be provided to the T7570 for oper­ation of the filter and coding/decoding functions. The MCLK frequency must be either 1.536 MHz,
1.544 MHz, 2.048 MHz, or 4.096 MHz and must be synchronous with BCLK at the start of each frame. Bits F0 and F1 (see Tab le 3) m ust be set during initialization to select the correct internal divider.
Coding Law Selection
Bits MA and IA in Table 3 permit the selection of µ-law coding or A-law coding, with or without even bit inver­sion.
Analog Loopback
The analog loopback mode is entered by setting the AL and DL bits in the control register as shown in Table 3. In the analog loopback mode, the transmit input VFXI is isolated from the input pin and internally connected to the VFRO output, forming a loop from the receive PCM register back to the transmit PCM register. The VFRO pin remains active, and the programmed settings of the transmit and receive gains remain unchanged; there­fore, care must be taken to ensure that overload levels are not exceeded anywhere in the loop. It is recom­mended that the hybrid-balance filter be disabled dur­ing analog loopback.
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Lucent Technologies Inc.
Data Sheet T7570 Programmable PCM Codec October 1996 with Hybrid-Balance Filter
Functional Description (continued)
Programmable Functions (continued)
Digital Loopback
The digital loopback mode is entered by setting the AL and DL bits in the control register as shown in Table 3. This mode provides another stage of path verification by enabling data written into the receive PCM register to be read back from that register in any transmit time slot at D
X0/1. In digital loopback mode, the decoder
remains functional and outputs a signal at VF RO. If this is undesirable, the receive output can be disabled by programming the receive gain register to all 0s.
Interface Latch Directions
Immediately following powerup, all interface latches assume they are inputs and, therefore, all IL pins are in a high-impedance state. Each IL pin can be individually programmed as a logic input or output by writing the appropriate instruction to the LDR (see Tables 2 and 5). For minimum power dissipation, unconnected latch pins should be programmed as outputs.
Bits L
5—L0 must be set by writing the specified instruc-
tion to the LDR with the L bits in the second byte set as follows.
Table 5. Byte 2 Functions of Latch Direction
Register
Note: X = don't care.
Interface Latch States
Interface latches configured as outputs assume the state determined by the appropriate data bit in the 2-byte instruction written to the interface latch register (ILR) as shown in Tables 2 and 6. Latches configured as inputs sense the state applied by an external source, such as the off-hook detect output of a SLIC. All bits of the ILR, i.e., sensed inputs and the pro­grammed state of outputs, can be read back in the sec­ond byte of a read of the ILR.
It is recommended that during initialization, the state of IL pins to be configured as outputs should be pro­grammed first, followed immediately by the LDR.
Table 6. Interface Latch Data Bit Order Bit Number
Time-Slot Assignment
The T7570 can operate in either fixed time-slot or time­slot assignment mode for selecting the transmit and receive PCM time slots. Following powerup, the device is automatically in nondelayed timing mode, in which the time slot always begins with the leading (rising) edge of frame-sync inputs FSX and FSR. Time-slot assignment can only be used with delayed-data timing (see Figure 5). FSX and FSR can have any phase rela­tionship with each other in BCLK period increments. Alternatively , the internal time-slot assignment counters and comparators can be used to access any time slot in a frame by using the frame-sync inputs as marker pulses for the beginning of transmit and receive time slots of 8 bits each. A time slot is assigned by a 2-byte instruction as shown in Tables 2 and 7. The last 6 bits of the second byte indicate the selected time slot from 0 to 63 using straight binary notation. A new assign­ment becomes active on the second frame following the end of the for the second control byte. The EN bit allows the PCM inputs, DR0/1, or outputs, DX0/1, as appropriate, to be enabled or disabled. Time-slot assignment mode requires that the FSX and FSR pulses must conform to the delayed-data timing format shown in Figure 5.
Port Selection
Two transmit serial PCM ports, DX0 and DX1, and two receive serial PCM ports, DR0 and DR1, are provided to enable two-way space switching to be implemented. Port selections for transmit and receive are made within the appropriate time-slot assignment instruction using the PS bit in the second byte. Port selection can only be used in delayed-data timing mode.
Table 7 shows the format of the second byte of both transmit and receive time-slot and port assignment instructions.
Byte 2 Bit Number
76543210
L0 L1 L2 L3 L4 L5 XX
Ln Bit IL Direction
0 Input 1 Output
Bit Number
76543210
D0 D1 D2 D3 D4 D5 XX
CS
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Lucent Technologies Inc.
T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996
Functional Description (continued)
Programmable Functions (continued)
Table 7. Time-Slot and Port Assignment Instruction
* T5 is the MSB of the time-slot assignment.
Bit Number and Name
76543210
EN PS T5* T4 T3 T2 T1 T0 Function
00XXXXXXDisable DX0 Output (transmit instruction)
Disable DR0 Input (receive instruction)
01XXXXXXDisable DX1 Output (transmit instruction)
Disable DR1 Input (receive instruction)
1 0 Assign One Binary-coded Time Slot from 0—63 Enable DX0 Output (transmit instruction)
Enable DR0 Input (receive instruction)
1 1 Assign One Binary-coded Time Slot from 0—63 Enable DX1 Output (transmit instruction)
Enable D
R1 Input (receive instruction)
Transmit Gain Instruction Byte 2
The transmit gain can be programmed in 0.1 dB steps from –0.4 dB to +19.0 dB by writing to the transmit gain register as defined in Tab les 2 and 8. This corresponds to a range of 0 dBm0 levels at VFXI between
0.811 Vrms and 0.087 Vrms (equivalent to +0.4 dBm to –19.0 dBm into 600 ).
To set transmit gain, determine the gain required of the codec in order to achieve the overall desired transmis­sion level point (TLP) at the PCM interface (usually 0 dBm or –2 dBm).
In order for the internal hybrid-balance circuitry to be effective, the portion of VFRO returned to the codec analog input must be between –2.5 dB to –10.25 dB of the VFRO output. For instance, if a SLIC presents a –6 dBm signal to VFXI when VFRO produces 0 dBm, good hybrid balance can be achieved. If the returned signal requires amplification to satisfy this requirement, then an additional op amp in the transmit path would be required. The T7570 will accommodate the phase inversion. A spare op amp is provided in some Lucent SLICs.
Once the codec gain is chosen, determine what signal level at VFXI would provide the desired TLP output at Dx. For our example of +6 dB gain (Gx) providing a 0 dBm TLP and working backwards from Dx, take the antilog of minus 6 dB divided by 20 and multiply by the
0.7746 reference lev el to obtain the signal level at VFXI in Vrms. As follows:
(1) antilog10 (–Gx / 20) * 0.7746 = Vrms
Finally, convert the signal level to a decimal number (n) using the following formula:
(2) 200 * log10 (Vrms / 0.08592) = n Round n to the nearest integer and convert to binary.
This is the code required by byte 2 of this instruction. Some examples are given in Table 8.
Table 8. Byte 2 of Transmit Gain Instructions
* 0 dB path gain setting. †Programming values greater than those listed in this table are
permitted. However, large signals may cause overload.
Receive Gain Instruction Byte 2
The receive gain can be programmed in 0.1 dB steps from –17.3 dB to +2.1 dB by writing to the receive gain register as defined in Tab les 2 and 9. This corresponds to a range of 0 dBm0 levels at VFRO between
0.987 Vrms and 0.106 Vrms (equivalent to +2.1 dBm to –17.3 dBm into 600 ).
Bit Number 0 dBm0 Test Level (Vrms)
7 6 5 4 3 2 1 0 at VFXI
0 0 0 0 0 0 0 0 No Output 0 0 0 0 0 0 0 1 0.087 0 0 0 0 0 0 1 0 0.088
——
1 0 1 1 1 1 1 1* 0.7746
——
1 1 0 0 0 0 1 0 0.802
1 1 0 0 0 0 1 1
0.811
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Lucent Technologies Inc.
Data Sheet T7570 Programmable PCM Codec October 1996 with Hybrid-Balance Filter
Functional Description (continued)
Programmable Functions (continued)
To set receive gain, first determine the gain required of the codec. For line card use, determine the codec’s allocation to set the overall transmission level point (TLP) at Tip\Ring accordingly (usually 0 dBm or –4 dBm).
Once the codec gain is chosen, determine the signal level that would be delivered to VF
RO when the refer-
ence TLP appears at DR. Tak e the antilog of the gain in dB (GR) divided by 20 and multiply by the 0.7746 refer­ence level to obtain the signal le vel at VFRO in Vrms. As follows:
(3) antilog10 (GR / 20) * 0.7746 = Vrms Finally, convert the signal level output to a decimal
number (n) using the following formula: (4) 200 * log10 (Vrms / 0.1045) = n Round n to the nearest integer and convert to binary.
This is the code required by byte 2 of this instruction. Some examples are given in Table 9.
Table 9. Byte 2 of Receive Gain Instructions
* 0 dB path gain setting. †Programming values greater than those listed in this table are
permitted. However, large signals may cause overload.
Hybrid-Balance Filter
The hybrid-balance filter on the T7570 is a programma­ble filter consisting of a second-order section, Hybal1, followed by a first-order section, Hybal2, and a pro­grammable attenuator. Either of the filter sections can be bypassed if only one is required to achieve good cancellation. A selectable 180° inverting stage is included to compensate for interface circuits that invert the transmit input relative to the receive output signal. The second-order section is intended mainly to balance
Bit Number 0 dBm0 Test Level (Vrms)
7 6 5 4 3 2 1 0 at VF
RI
0 0 0 0 0 0 0 0 No Output (low Z to GND) 0 0 0 0 0 0 0 1 0.106 0 0 0 0 0 0 1 0 0.107
——
1 0 1 0 1 1 1 0* 0.7746
——
1 1 0 0 0 0 1 0 0.975
1 1 0 0 0 0 1 1
0.987
low-frequency signals across a transformer SLIC, and the first-order section is intended to balance midrange to higher audio-frequency signals.
As a second-order section, Hybal1 has a pair of low­frequency zeros and a pair of complex conjugate poles. When configuring the Hybal1, matching the phase of the hybrid at low- to midband frequencies is most critical. Once the echo path is correctly balanced in phase, the magnitude of the cancellation signal can be corrected by the programmable attenuator.
The second-order mode of Hybal1 is most suitable for balancing interfaces with transformers having high inductance of 1.5 H or more. An alternative configura­tion for smaller transformers is available by converting Hybal1 to a simple first-order section with a single real low-frequency pole and zero. In this mode, the pole/zero frequency can be programmed.
Many line interfaces can be adequately balanced by use of the Hybal1 filter only, in which case the Hybal2 filter should be deselected to bypass it.
Hybal2, the higher-frequency first-order section, is pro­vided for balancing an electronic SLIC and is also help­ful with a transformer SLIC in providing additional phase correction for mid- and high-band frequencies, typically 1 kHz to 3.4 kHz. Such a correction is particu­larly useful if the test balance impedance includes a capacitor of 100 nF or less, such as the loaded and nonloaded loop test networks in the United States. Independent placement of the pole and zero location is provided.
Figure 3 shows a simplified diagram of the local echo­path for a typical application with a transformer inter­face. The magnitude and phase of the local echo sig­nal, measured at VF
XI, are a function of the termination
impedance ZT, the line transformer, and the impedance of the two-wire loop, ZL. If the impedance reflected back into the transformer primary is expressed as ZL', then the echo path transfer function from VFRO to VF XI is the following:
(5) H(W) = ZL' /(ZT + ZL') The signal level returned at VFXI must be between
–2.5 dB to –10.25 dB over the voice band, relative to the output at VFRO, in order for the hybrid balance function to be effective. Signals outside this range exceed the range of programmability of the hybrid path, and the software will provide unacceptable h ybrid balance performance over the voice band.
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Lucent Technologies Inc.
T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996
Functional Description (continued)
Hybrid-Balance Filter (continued)
5-2788 (C)
Figure 3. Block Diagram Hybrid-Balance Filter Network
TIP
RING
ZL
ZL'
Z
T
VFXI
VF
RO
– +
TO TX GAIN BLOCK
HYBAL2
1ST-ORDER
HI FREQ.
FILTER
(REG 3)
HYBAL1
1ST- OR
2ND-ORDER
FILTER
(REG 2)
±1
FROM RX GAIN BLOCK
ATTENUATOR GAIN
RVFXI
2.4
+2.4
SEL
INV
SEL 2 SET IN REG 2
Programming the Filter
On initial powerup, the h ybrid-balance filter is disab led. Before the hybrid-balance filter can be programmed, it is necessary to design the transformer and termination impedance to meet system 2-wire input return loss specifications, which are normally measured against a fixed test impedance (600 or 900 in most coun­tries). Only then can the echo path be modeled and the hybrid-balance filter programmed. Hybrid balancing is also measured against a fixed test impedance, speci­fied by each national telecommunication administration to provide adequate control of talker and listener echo over the majority of their network connections. This test impedance is ZL in Figure 3. The echo signal and the degree of transhybrid loss obtained by the programma­ble filter must be measured from the PCM digital input, DR0/1, to the PCM digital output, DX0/1, either by digital test signal analysis or by conversion back to analog by a PCM codec/filter.
Three registers must be programmed in the T7570 to fully configure the hybrid-balance filter (refer to Table 2 for Byte 1 addressing):
Register 1: Select/deselect hybrid-balance filter;
invert/noninvert cancellation signal; select/deselect Hybal2 filter section; set attenuator.
Register 2: Select/deselect Hybal1 filter;
set Hybal1 to biquad or first order; select pole and zero frequency.
Register 3: Program pole frequency in Hybal2 filter;
program zero frequency in Hybal2 filter.
Standard filter design techniques can be used to model the echo path (see Equation 5) and design a matching hybrid-balance filter configuration. Alternatively, the fre­quency response of the echo path can be measured and the hybrid-balance filter designed to replicate it.
T7570 hybrid-balance software is available from your Lucent Account Representative to aid in selecting the best balance filter register settings.
Byte 2 of Register 1
765 43210
SEL INV SEL2 GAIN (All “0” = MAX)
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Lucent Technologies Inc.
Data Sheet T7570 Programmable PCM Codec October 1996 with Hybrid-Balance Filter
Functional Description (continued)
Hybrid-Balance Filter (continued)
Power Supply
While the pins of the T7570 devices are well protected against electrical misuse, it is recommended that the stan­dard CMOS practice of applying GND to the device before any other connections are made should always be fol­lowed. In applications where the printed-circuit card can be plugged into a hot socket with power and clocks already present, an extra-long ground pin on the connector should be used.
To minimize noise sources, all ground connections to each device should meet at a common point as close as pos­sible to the device GND pin to prevent the interaction of ground return currents flowing through a common-bus impedance. A power-supply decoupling capacitor of 0.1 µF should be connected from this common point to V
DD, as
close to the device pins as possible. The power supply should also be decoupled with a low, effective series resis­tance capacitor of at least 10 µF, located near the card edge connector.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso­lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to av oid e xpo­sure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and a charged-device model (CDM) for ESD susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely used and therefore can be used for comparison purposes. The HBM ESD threshold presented here was obtained using these circuit parameters.
Table 10. Human-Body Model ESD Threshold
Parameter Symbol Min Max Unit
Storage Temperature Range Tstg –55 150 °C Power Supply Voltage VDD 6.5 V Voltage on Any Pin with Respect to Ground –0.5 0.5 + VDD V Maximum Power Dissipation (package limit) PDISS 600 mW
Device Voltage
T7570 2000 V
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Lucent Technologies Inc.
T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996
Electrical Characteristics
For all tests, T A = –40 °C to +85 °C, VDD = 5 V ± 5%, and GND = 0 V, unless otherwise noted. Typical values are for TA = 25 °C and nominal supply values.
dc Characteristics
Table 11. Digital Interface
Table 12. Power Dissipation
Parameter Symbol Test Conditions TA (°C) Min Max Unit
Input V oltage Low VIL All digital inputs 0.7 V
High VIH All digital inputs 2.0 V
Output V oltage
Low VOL DX0, DX1, CO, IL = 3.2 mA 0.4 V
All other digital outputs, IL = –1 mA 0.4 V
High VOH DX0, DX1, CO, IL = 3.2 mA 2.4 V
All other digital outputs except X, IL = –1 mA
2.4 V
All digital outputs, IL = –100 µA—VCC – 0.5 V
Input Current
Low IIL Any digital input, GND < VIN < VIL –10 10 µA High IIH Any digital input except MR,
VIH < VIN < VCC
–10 10 µA
MR only –10 100 µA
Output Current
in High­impedance State
IOZ DX0, DX1, CO,
IL5—IL0 when selected as inputs, GND < VOUT < VCC
–40 to 0 –30 30 µA
0 to 85 –10 10 µA
Parameter Symbol Test Conditions Typ Max Unit
Powerdown Current IDD0
CCLK, CI, CO = 0.4 V, = 2.4 V, interface latches set as outputs with no load, all other inputs active, power amp disabled
0.3 0.9 mA
Powerup Current IDD1
CCLK, CI, CO = 0.4 V, = 2.4 V, no load on power amp, interface latches set as outputs with no load
14.0 20.0 mA
Powerdown Current IDD2
CCLK, CI, CO = 0.4 V, = 2.4 V, interface latches set as outputs with no load, all other inputs active, power amp disabled, no load on power amp
4.0 6.0 mA
TS
CS
CS
CS
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Lucent Technologies Inc.
Data Sheet T7570 Programmable PCM Codec October 1996 with Hybrid-Balance Filter
Transmission Characteristics
Table 13. Analog Interface
Table 14. Gain and Dynamic Range
Parameter Symbol Test Conditions Min Typ Max Unit
Input Resistance RVFXI 0.25 V < VFXI < 4.75 V 390 585 k Input Offset Voltage at VFXIVOSX 2.3 2.5 V Load Resistance RLVFRO 300 Load Capacitance CLVFRO RLVFRO 300
CLVFRO from VFRO to GND
200 pF
Output Resistance ROVFRO Steady zero PCM code applied to DR0 or DR1 1.6 3.0 Output Offset Voltage
at VFRO
VOSR Alternating ± zero PCM code applied to DR0
or DR1, maximum receive gain
2.3 2.5 V
Output Offset Voltage at
VFRO, Powerdown
VOSRPD Control register byte 2, bit 7 = 0 2.3 2.5 V
Output V oltage Swing VSWR RL = 300 Ω, maximum receive gain 4.01 VPP
Parameter Symbol Test Conditions TA (°C) Min Typ Max Unit
Absolute Levels GAL Maximum 0 dBm0 levels:
VFXI (gain set to 11000011) 0.811 Vrms VFRO (gain set to 11000011) 0.987 Vrms
Minimum 0 dBm0 levels:
VFXI (gain set to 00000001) 87.0 mVrms VFRO (gain set to 00000001) 106.0 mVrms
Transmit Gain GXA Transmit gain programmed for
maximum 0 dBm0 test level, measured deviation of digital code from ideal 0 dBm0 PCM code at DX0/1, T A = 25 °C
–0.15 0.15 dB
Absolute Accuracy
Transmit Gain Variation
with Temperature
GXA T Measured relative to GXA,
VDD = 5 V, minimum gain < GX < maximum gain
–40 to 0 –0.15 0.15 dB
0 to 85 –0.1 0.1 dB
Transmit Gain Variation
with Programmed Gain
GXAG Measured transmit gain over
the range from maximum to minimum, calculated the devia­tion from the programmed gain relative to GXA (i.e., GXAF = Gactual – Gprog – GXA), TA = 25 °C, VDD = 5 V
–0.1 0.1 dB
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Lucent Technologies Inc.
T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996
Transmission Characteristics (continued)
Table 14. Gain and Dynamic Range (continued)
Parameter Symbol Test Conditions TA (°C) Min Typ Max Unit
Transmit Gain Variation
with Frequency
GXAF Relative to 1020 Hz, minimum
gain < GX < maximum gain, DR0 or DR1 = 0 dBm0 code:
f = 16.67 Hz –35 –30 dB f = 50 Hz –33 –30 dB f = 60 Hz –40 –30 dB f = 200 Hz –1.8 –0.5 0 dB f = 300 Hz to 3000 Hz –0.125 ±0.04 0.125 dB f = 3140 Hz –0.57 0.01 0.125 dB f = 3380 Hz –0.885 –0.6 0.012 dB f = 3860 Hz –9.9 –8.98 dB f 4600 Hz (measured
response at alias frequency from 0 kHz to 4 kHz)
–32 dB
Transmit Gain Variation
with Signal Level
GXAL Sinusoidal test method, refer-
ence level = 0 dBm0: VFXI = –40 dBm0 to +3 dBm0 –0.2 0.2 dB VFXI = –50 dBm0 to –40 dBm0 –0.4 0.4 dB VFXI = –55 dBm0 to –50 dBm0 –1.2 1.2 dB
Receive Gain Absolute
Accuracy
GRA Receive gain programmed for
maximum 0 dBm0 test level, applied 0 dBm0 PCM code to DR0 or DR1, measured VFRO, TA = 25 °C, load = 10 k
–0.15 0.15 dB
Receive Gain
Variation with Temperature
GRAT Measured relative to GRA, VDD =
5 V, minimum gain < GR < maxi­mum gain
–40 to 0 –0.15 0.15 dB
0 to 85 –0.1 0.1 dB
Receive Gain Variation
with Programmed Gain
GRAG Measured receive gain over the
range from maximum to mini­mum setting, calculated the deviation from the programmed gain relative to GRA, i.e., GRAG = Gactual – Gprog – GRA, TA = 25 °C, VDD = 5 V
–0.1 0.1 dB
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Lucent Technologies Inc.
Data Sheet T7570 Programmable PCM Codec October 1996 with Hybrid-Balance Filter
Transmission Characteristics (continued)
Table 14. Gain and Dynamic Range (continued)
Table 15. Envelope Delay Distortion
Parameter Symbol Test Conditions TA (°C) Min Typ Max Unit
Receive Gain
Variation with Frequency
GRAF Relative to 1020 Hz,
DR0 or DR1 = 0 dBm0 code,
minimum gain < GR < maximum gain: f ≤ 3000 Hz –0.125 ±0.04 0.125 dB f = 3140 Hz –0.57 0.01 0.125 dB f = 3380 Hz –0.885 –0.58 +0.012 dB f = 3860 Hz –10.7 –8.98 dB f ≥ 4600 Hz –28 dB Receive Gain
Variation with Signal Level
GRAL Sinusoidal test method,
reference level = 0 dBm0:
DR0 = –40 dBm0 to +3 dBm0 –0.2 0.2 dB DR0 = –50 dBm0 to –40 dBm0 –0.4 0.4 dB DR0 = –55 dBm0 to –50 dBm0 –1.2 1.2 dB
Parameter Symbol Test Conditions Min Max Unit
Tx Delay, Absolute DXA f = 1600 Hz 315 µs Tx Delay, Relative
to 1600 Hz
DXR f = 500 Hz—600 Hz 220 µs
f = 600 Hz—800 Hz 145 µs f = 800 Hz—1000 Hz 75 µs f = 1000 Hz—1600 Hz 40 µs f = 1600 Hz—2600 Hz 75 µs f = 2600 Hz—2800 Hz 105 µs
f = 2800 Hz—3000 Hz 155 µs Rx Delay, Absolute DRA f = 1600 Hz 200 µs Rx Delay, Relative
to 1600 Hz
DRR f = 500 Hz—1000 Hz –40 µs
f = 1000 Hz—1600 Hz –30 µs
f = 1600 Hz—2600 Hz 90 µs
f = 2600 Hz—2800 Hz 125 µs
f = 2800 Hz—3000 Hz 175 µs
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Lucent Technologies Inc.
T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996
Transmission Characteristics (continued)
Table 16. Noise
* PPSRX is measured with a –50 dBm0 activation signal applied to VFXI.
Parameter Symbol Test Conditions Min Typ Max Unit
Transmit Noise, C Message
Weighted, µ-law Selected
NXC All 1s in gain register 15 dBrnC0
Transmit Noise, P Message
Weighted, A-law Selected
NXP All 1s in gain register –67 dBm0p
Receive Noise, C Message
Weighted, µ-law Selected
NRC PCM code is alternating positive and
negative zeros
13 dBrnC0
Receive Noise, P Message
Weighted, A-law Selected
NRP PCM code equals positive one LSB –79 dBm0p
Noise, Single Frequency NRS f = 0 kHz—100 kHz, analog to analog
measurement (DX0 is externally con­nected to DR0), VFXI = 0 Vrms
–53 dBm0
Power Supply Rejection, Transmit PPSRX VDD = 5.0 Vdc + 100 mVrms:
f = 0 kHz—4 kHz* f = 4 kHz—50 kHz
3630———
dBC dBC
Power Supply Rejection, Receive PPSRR PCM code equals positive one LSB,
VDD = 5.0 + 100 mVrms, measured VFRO:
f = 0 Hz—4000 Hz 36 dBC f = 4 kHz—25 kHz 40 dB f = 25 kHz—50 kHz 36 dB
Spurious Out-of-Band Signals at
the Channel Output
SOS 0 dBm0, 300 Hz—3400 Hz input
PCM code applied at DR0 (or DR1):
4600 Hz—7600 Hz –30 dB
7600 Hz—8400 Hz –40 dB
8400 Hz—50,000 Hz — — –30 dB
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Lucent Technologies Inc.
Data Sheet T7570 Programmable PCM Codec October 1996 with Hybrid-Balance Filter
Transmission Characteristics (continued)
Table 17. Distortion
Table 18. Crosstalk
* CTR–X and PPSRX are measured with a –50 dBm0 activation signal applied to VFXI.
Parameter Symbol Test Conditions Min Max Unit
Signal to Total Distortion STDX Sinusoidal test method level:
Transmit or Receive STDR 3.0 dBm0 33 dBC Half-channel, µ-law Selected 0 dBm0 to –30 dBm0 36 dBC
–40 dBm0 30 dBC –45 dBm0 25 dBC
Single Frequency Distortion,
Transmit
SFDX –46 dB
Single Frequency Distortion,
Receive
SFDR –46 dB
Intermodulation Distortion IMD Transmit or receive two frequencies
in the range (300 Hz—3400 Hz)
–41 dB
Parameter Symbol Test Conditions Typ Max Unit
Transmit to Receive Crosstalk,
0 dBm0 Transmit Level
CTX–R f = 300 Hz—3400 Hz
DR = steady PCM code
–90 –75 dB
Receive to Transmit Crosstalk,
0 dBm0 Receive Level
CTR–X f = 300 Hz—3400 Hz* –90 –70 dB
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Lucent Technologies Inc.
T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996
Timing Characteristics
A signal is valid if it is above VIH or below VIL and invalid if it is between VIL and VIH. For the purposes of this specifi­cation, the following conditions apply:
All input signals are defined as VIL = 0.4 V, VIH = 2.7 V, tR < 10 ns, tF < 10 ns.
tR is measured from VIL to VIH. tF is measured from VIH to VIL.
Delay times are measured from the input signal valid to the output signal valid.
Setup times are measured from the data input valid to the clock input invalid.
Hold times are measured from the clock signal valid to the data input invalid.
Pulse widths are measured from VIL to VIL or from VIH to VIH.
Table 19. Master Clock Timing (See Figures 4 and 5.)
Symbol Parameter Test Conditions Min Typ Max Unit
fMCLK Frequency of MCLK—Selection
Frequency Is Programmable (See Table 3.)
——
— — —
1536 1544 2048 4096
— — — —
kHz kHz kHz
kHz tMCHMCL Time of MCLK High Measured from VIH to VIH 80 ns tMCLMCH Time of MCLK Low Measured from VIL to VIL 80 ns
tMCH1MCH2 Rise Time of MCLK Measured from VIL to VIH 30 ns
tMCL2MCL1 Fall Time of MCLK Measured from VIH to VIL 30 ns
tBCLMCH Hold Time, BCLK Low to MCLK
High
—50ns
tFSLFSH Period of FSX or FSR Low Measured from VIL to VIL 1 MCLK
Period
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Lucent Technologies Inc.
Data Sheet T7570 Programmable PCM Codec October 1996 with Hybrid-Balance Filter
Timing Characteristics (continued)
Table 20. PCM Interface Timing (See Figures 4 and 5.)
Symbol Parameter Test Conditions TA (°C) Min Max Unit
fBCLK Frequency of BCLK (can vary
from 64 kHz to 4096 kHz in 8 kHz increments)
64 4096 kHz
tBCHBCL Time of BCLK High Measured from VIH to VIH —80—ns tBCLBCH Time of BCLK Low Measured from VIL to VIL —80—ns
tBCH1BCH2 Rise Time of BCLK Measured from VIL to VIH 30 ns
tBCL2BCL1 Fall Time of BCLK Measured from VIH to VIL 30 ns
tBCLFXL tBCLFRL
Hold Time, BCLK Low
FSX/R to High or Low
30 ns
tFXHBCL tFRHBCL
Setup Time FSX/R,
High to BCLK Low
30 ns
tBCHDXV Delay Time, BCLK High
to Data Valid
Load = 100 pF plus two LSTTL loads
90 ns
tBCLDXZ Delay Time, BCLK Low to
DX0/1 Disabled if FSX Low, FSX Low to DX0/1 Disabled if Eighth BCLK Low, or BCLK High to DX0/1 Disabled if FSX High
–40 to 0 10 80 ns
0 to 85 15 80 ns
tBCHTXL
Delay Time , BCLK High to X
Low if FSX High, or FSX High to X Low if BCLK High
Load = 100 pF plus two LSTTL loads
60 ns
tBCL TXH High-impedance Time, BCLK
Low to X High if FSX Low, or FSX BCLK High to X High if FSX High
15 60 ns
tFXHDXV Delay Time, FSX/R
High to Data Valid
Load = 100 pF plus two LSTTL loads, applies if FSX/R rises later than BCLK rising edge in nondelayed-data mode only
80 ns
tDRVBCL Setup Time, DR0/1
Valid to BCLK Low
30 ns
tBCLDRX Hold Time, BCLK Low to DR0/1
Invalid
–40 to 0 15 ns
0 to 85 20 ns
tBCLMCH BCLK Low to MCLK High at the
End of the First Data Bit Period
50 ns
TS
TS
TS
TS
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Lucent Technologies Inc.
T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996
Timing Characteristics (continued)
5-2789 (C)
Note: Bit 1 = sign bit.
Figure 4. Nondelayed-Data Timing Mode
5-2790 (C)
Note: Bit 1 = sign bit.
Figure 5. Delayed-Data Timing Mode
MCLK
(MC)
BCLK
(BC)
FS
X
(FX)
D
X0/1
(DX)
FS
R
(FR)
D
R0/1
(DR)
TS
X0/1
(TX)
12 3 456789
tMCHMCL
tMCLMCH
tBCLBCH
tBCHBCL
tBCL2BCL1
tBCH1BCH2
tMCL2MCL1
tBCLMCH
tMCH1MCH2
tBCLFXL
tFXHBCL
tBCHDXV
tFXHDXV
tBCHTXL
tBCHTXL
tBCLFRL
tFRHBCL
tDRVBCL tBCLDRX
tBCLDXZ
tBCLTXH
1234567 8
12345678
MCLK
(MC)
BCLK
(BC)
FS
X
(FX)
DX0/1
(DX)
FS
R
(FR)
D
R0/1
(DR)
TS
X0/1
(TX)
tBCHBCL
12 3 45789
tMCL2MCL1
tBCLMCH
tMCH1MCH2
tBCHTXL
tDRVBCL tBCLDRX
tBCLTXH
12345678
12345678
tBCH1BCH2
tBCL2BCL1
tMCHMCL
tMCLMCH
6
tBCLBCH
tBCLDXZ
tBCLFRL
tBCHDXV
tBCLFXL
tFRHBCL
tFXHBCL
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Lucent Technologies Inc.
Data Sheet T7570 Programmable PCM Codec October 1996 with Hybrid-Balance Filter
Timing Characteristics (continued)
Table 21. Serial Control Port Timing (See Figure 6.)
Table 22. Interface Latch Timing (See Figure 6.)
Table 23. Master Reset Pin
Symbol Parameter Test Conditions Min Max Unit
fCCLK Frequency of CCLK 2048 kHz tCCHCCL Time of CCLK High Measured from VIH to VIH 160 ns tCCLCCH Time of CCLK Low Measured from VIL to VIL 160 ns
tCCH1CCH2 Rise Time of CCLK Measured from VIL to VIH 50 ns
tCCL2CCL1 Fall Time of CCLK Measured from VIH to VIL —50ns
tCCLCSL Hold Time, CCLK Low to
Low
Measured from first CCLK low transition 10 ns
tCCLCSH Hold Time, CCLK Low to
High
Measured from eighth CCLK low transition 100 ns
tCSLCCH
Setup Time, T ransi-
tion to CCLK Low
—60ns
tCSHCCH
Setup Time, T ransi-
tion to CCLK High
—50ns
tCIVCCL Setup Time, CI Data In to
CCLK Low
—50ns
tCCLCIX Hold Time, CCLK Low to
CI Invalid
—50ns
tCCHCOV Delay Time, CCLK High to
CO Data Out Valid
Load = 100 pF plus 2 LSTTL loads 80 ns
tCSLCOV
Delay Time, Low to
CO V alid
Applies only if separate used for byte 2
80 ns
tCSHCOZ
Delay Time, High to
CO High Impedance
Applies when high occurs before ninth CCLK high
15 80 ns
Symbol Parameter Test Conditions Min Max Unit
tILXCCL Setup Time, IL to Eighth
CCLK of Byte 1
Interface latch inputs only 100 ns
tCCLILX Hold Time, IL Valid from
Eighth CCLK Low (byte 1)
—50ns
tCCLILV Delay Time CCLK 8 of
Byte 2 to IL
Interface latch outputs only CL = 50 pF 200 ns
Symbol Parameter Min Max Unit
tMRHRML Duration of Master Reset High 1 µs
CS
CS
CS
CS
CS CS
CS CS
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Lucent Technologies Inc.
T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996
Timing Characteristics (continued)
5-2791 (C)
Figure 6. Serial Control Port Timing
CCLK
(CC)
CI:
BYTE 1 &
BYTE 2 WHEN
INPUT TO CI
CO: BYTE 2
WHEN OUTPUT
FROM CO
(CO)
IL5—IL0
(IL)
CS
1
2345678 12345678
76543210 76543210
7654 321 0
tCCLCSL
tCSLCCH
tCIVCCL
tCCLCIX
tCCHCCL
tCCLCCH
tCCLCSL
tCCLCSH
tCSLCCH
tCCH1CCH2
tCCL2CCL1
tCCLCSH
tCCLILV
OUTPUTS ONLY
BYTE 2
tILXCCL
tCCLILX
INPUTS ONLY
tCSHCCH
tCSLCOV
tCCHCOV
tCSHCOZ
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Lucent Technologies Inc.
Data Sheet T7570 Programmable PCM Codec October 1996 with Hybrid-Balance Filter
Applications
Figure 7 illustrates a T7570 codec interfaced to a Lucent L7554 SLIC. Interface components were chosen for a basic 600 resistive only termination and balance network. Ov erall receiv e path gain is 0 dB (PCM to T/R). Over all transmit path gain is –2 dB (T/R to PCM). Codec receive gain is 0 dB. The signal level returned to VFXI is –3.658 dBm. This satisfies the transmission level point requirement for hybrid cancellation. That is, the signal at VFXI relative to the output at VFRO must be within –2.5 dB to –10.25 dB. Transmit gain of the codec is set at +1.658 dB in order to achieve a transmission level point at Dx of –2 dBm.
Transmit and receive paths are capacitively coupled to accommodate different SLIC and codec bias levels. The codec’s inputs are self-biased so that no additional external resistors are necessary with ac coupling. Capacitor values are sized appropriately to pass low-frequency requirements of relevant gain versus frequency templates. Resistive values were ascertained from SLIC documentation.
An optional 20 k resistor from RCVN to ground and a 30 pF capacitor across RGP can be added for stability. Gain and hybrid-balance register values are shown in he x. Gain values were obtained from Tables 8 and 9. Hybrid-
balance values were obtained by removing the codec and inserting a network analyzer to measure the phase and gain returned by the loop to VFXI when a signal is injected at VFRO. Gain and phase are then measured at 14 fre­quencies. The results obtained from this exercise are plugged into the hybrid-balance software that provides the register settings as shown.
5-4716.a C
Figure 7. 600 Resistive SLIC Interface
Register Settings
Register Register Number Value Description
RX GAIN 04 AE 0 dB
TX GAIN 05 AE 1.658 dB HYBRID 1 06 A4 — HYBRID 2 07 51 — HYBRID 3 08 88
L7554
RGP 20 k
CC1
0.47 µF
VITR
CRCV1
0.1 µF
VFXI
VFRO
2.4 V
T7570
RRCV
48.7 k
RT1
86.6 k
RCVN RCVP
RPT 35
TZ
600
RPT 35
SLIC CODEC
PT
PR
SEE REGISTER
SETTINGS
BELOW
26
Lucent Technologies Inc.
T7570 Programmable PCM Codec Data Sheet with Hybrid-Balance Filter October 1996
Outline Diagrams
28-Pin PLCC
Dimensions are shown in inches.
5-2608r.4
1.27 TYP
0.53 MAX
4.57 MAX
0.10
SEATING PLANE
0.51 MIN TYP
12 18
11
5
4126
25
19
11.58 MAX
12.57 MAX
11.58 MAX
12.57 MAX
PIN #1 IDENTIFIER
ZONE
27
Lucent Technologies Inc.
Data Sheet T7570 Programmable PCM Codec October 1996 with Hybrid-Balance Filter
Ordering Information
Device Code Package Temperature Comcode
T - 7570 - - - ML2 28-Pin PLCC –40 °C to +85 °C 107055782
T - 7570 - - - ML2 -TR 28-Pin PLCC, Tape and Reel –40 °C to +85 °C 107056525
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET: http://www.lucent.com/micro U.S.A.:Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103,
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106), e-mail docmaster@micro.lucent.com
ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
JAPAN:Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
For data requests in Europe:
MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 324 299, FAX (44) 1734 328 148
For technical inquiries in Europe:
CENTRAL EUROPE: (49) 89 95086 0 (Munich), NORTHERN EUROPE: (44) 1344 865 900 (Bracknell UK),
FRANCE: (33) 1 47 67 47 67 (Paris), SOUTHERN EUROPE: (39) 2 6601 1800 (Milan) or (34) 1 807 1700 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright © 1996 Lucent Technologies Inc. All Rights Reserved
October 1996 DS96-223ALC (Replaces DS92-224TCOM and AY93-026TCOM)
Printed On
Recycled Paper
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