LSI SYM53C040 Technical Manual

®

Symbios

SYM53C040
Enclosure Services
Processor

Technical Manual

February 2000

Version 2.5

Order Number S14042

®

This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.

Document DB14-000125-00, Second Edition (February 2000)
This document describes revision C.1 of LSI Logic Corporation’s Symbios

®

SYM53C040 Enclosure Services Processor and will remain the official reference
source for all revisions/releases of this product until rescinded by an update.

To receive product literature, visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third par ties.

Copyright © 1998–2000 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT

The LSI Logic logo design, LVD Link, Symbios, and TolerANT are trademarks or
registered trademarks of LSI Logic Corporation. MCS is a registered trademark
of Intel Corporation. All other brand and product names may be trademarks of
their respective companies.

DB

ii

Contents

Chapter 1 Introduction

1.1 SYM53C040 Overview 1-1

1.2 SCSI Mode 1-2

1.3 SFF-8067 Mode 1-3

1.4 Features Summary 1-4

Chapter 2 Functional Description

2.1 Functional Blocks 2-3

2.1.1 SYM53C80-Based SCSI Control Logic 2-3

2.1.2 80C32 Microcontroller Core 2-3

2.1.3 Two-Wire Serial Interface 2-3

2.1.4 SFF-8067 Interface 2-4

2.1.5 16 Kbytes SRAM 2-4

2.1.6 DMA Function 2-4

2.2 Memory Map 2-4

2.3 SCSI Core Operation 2-5

2.3.1 Recommended Use of SCSI High ID Pins 2-5

2.3.2 LVD Link™ Technology 2-8

2.3.3 Programmed I/O Transfers 2-8

2.3.4 SCSI - DMA Transfers 2-11

2.4 DMA Function 2-13

2.5 Microcontroller Operation 2-14

2.5.1 ONCE Mode 2-14

2.6 Two-Wire Serial Interface Operation 2-15

2.6.1 Two-Wire Serial Interface Transfer Rate 2-16

2.6.2 Power-On Serial ROM Download 2-16

2.6.3 Address and Length Download Configuration 2-17

2.6.4 Firmware Download and Checksum 2-18

Contents iii

2.6.5 Manually Accessing External Two-Wire Serial
Devices 2-18

2.7 Power-On Configuration Options 2-21

2.7.1 Automatic Branch Generation 2-21

2.7.2 External Serial ROM Configuration 2-22

2.7.3 Serial ROM Chip Address 2-22

2.7.4 Download Port Select 2-23

2.8 Resets 2-23

2.9 SFF-8067 Mode 2-24

2.10 Interrupts 2-27

2.10.1 Microcontroller Interrupts 2-27

2.10.2 DMA and SCSI Interrupts 2-29

2.10.3 SFF-8067 Interrupts 2-31

2.10.4 Two-Wire Serial Interrupts 2-31

2.10.5 Masking and Enabling Interrupts 2-32

2.10.6 Polling and Hardware Interrupts 2-32

2.10.7 Interrupt Service Routine 2-32

2.11 JTAG Boundary Scan Testing 2-34

Chapter 3 Signal Descriptions

3.1 Safety Mode Signals 3-9

3.1.1 Miscellaneous Signals 3-9

3.1.2 SCSI Signals 3-13

3.1.3 JTAG Signals 3-16

3.1.4 Power and Ground Signals 3-17

3.2 SFF-8067 Mode 3-18

Chapter 4 SCSI and DMA Registers

Chapter 5 SFF-8067 Registers

Chapter 6 Two-Wire Serial Registers

Chapter 7 Miscellaneous Registers

iv Contents

Chapter 8 System Registers

Chapter 9 Electrical Characteristics

9.1 Operating Requirements 9-2

9.2 3.3 Volt DC Specifications 9-3

9.3 AC Characteristics 9-7

9.3.1 Clock Timing 9-7

9.3.2 Reset Signal 9-8

9.4 Microcontroller Interface Timings 9-9

9.4.1 External Memory Interf ace 9-9

9.4.2 External Data Read Cycle 9-10

9.4.3 External Data Write Cycle 9-11

9.5 Multipurpose Register Access 9-12

9.6 Two-Wire Serial Timings 9-13

9.7 SFF-8067 Interface Timings 9-14

9.8 SCSI Timings 9-16

9.8.1 Initiator Asynchronous Send 9-16

9.8.2 Initiator Asynchronous Receive 9-17

9.8.3 Target Asynchronous Send 9-18

9.8.4 Target Asynchronous Receive 9-19

9.9 Mechanical Drawings 9-20

Appendix A Register Summary

Index

Customer Feedback

Figures

1.1 SCSI/SAF-TE Enclosure Implementation 1-2

1.2 SFF-8067/SES Enclosure Implementation 1-3

2.1 SYM53C040 Block Diagram 2-2

2.2 SYM53C040 Memory Map 2-5

2.3 Initiating Arbitration and Selection/Reselection 2-7

2.4 LVD Resistor Value 2-8

Contents v

2.5 Programmed I/O Target Transfers 2-10

2.6 DMA Target Mode Transfers 2-12

2.7 DMA External Memory Access 2-14

2.8 Serial Read Operation 2-15

2.9 Serial Write Operation 2-15

2.10 Serial ROM Download 2-17

2.11 Two-Wire Serial Slave Data Transmit and Receive 2-19

2.12 Two-Wire Serial Master Data T ransmit and Receive 2-20

2.13 SYM53C040 SFF-8067 Interface Control State Diagram 2-26

3.1 SYM53C040, 160-Pin QFP Option 3-2

3.2 SYM53C040 169-Ball BGA Top View 3-5

3.3 SYM53C040 Functional Pin Description 3-8

4.1 Register Set Overview 4-1

5.1 Register Set Overview 5-1

6.1 Register Set Overview 6-1

7.1 Register Set Overview 7-1

8.1 Register Set Overview 8-1

9.1 LVD Driver 9-3

9.2 LVD Receiver 9-4

9.3 SYM53C040 Clock Waveforms 9-7

9.4 Reset Waveforms 9-8

9.5 External Memory Interface Waveforms 9-9

9.6 External Data Read Waveforms 9-10

9.7 External Data Write Waveforms 9-11

9.8 Two-Wire Serial Bus Timings 9-13

9.9 SFF-8067 Discovery Phase Waveforms 9-14

9.10 SFF-8067 Write Phase Waveforms 9-14

9.11 SFF-8067 Read Waveforms 9-15

9.12 Initiator Asynchronous Send Waveforms 9-16

9.13 Initiator Asynchronous Receive Wav eforms 9-17

9.14 Target Asynchronous Send Waveforms 9-18

9.15 Target Asynchronous Receive Waveforms 9-19

9.16 160 LD-Pin PQFP (PZ) Mechanical Drawing (Sheet 1 of 2) 9-21

9.17 169-Pin PBGA (GV) Mechanical Drawing 9-23

vi Contents

Tables

2.1 Initial ROM Download Contents 2-17

2.2 Power-On Configuration Pins and Options 2-21

2.3 External Pull-up Values for Automatic Branch Generation 2-22

2.4 Serial ROM Chip Addresses 2-23

2.5 Register Bits for Interrupt Handling 2-28

2.6 Interrupt Handling 2-33

3.1 SYM53C040 160-Pin QFP Pin List (Alphabetically by
Signal Name) 3-3

3.2 SYM53C040 160-Pin QFP Pin List (Numerically by
Pin Number) 3-4

3.5 Miscellaneous Signals 3-9

3.6 SCSI Signals 3-13

3.7 JTAG Signals 3-16

3.8 Power and Grounds Signals 3-17

3.9 Pin Assignments for SFF-8067 Mode 3-18

4.1 SCSI and DMA Registers 4-2

4.2 SCSI Phase Bit Values 4-9

5.1 SFF-8067 Interface Registers 5-2

6.1 Two-Wire Serial Registers 6-2

7.1 Miscellaneous Registers 7-2

7.3 Possible Watchdog Timer Values (40 MHz Internal Clock) 7-4

8.1 System Registers 8-2

8.2 Automatic Branch Destination Address 8-5

8.3 Fast LED Blink Rates (40 MHz Internal Clock) 8-7

8.4 Slow LED Blink Rates (20 MHz Internal Clock) 8-7

8.5 LED Behavior 8-21

8.6 LED Bank 1 Behavior 8-25

8.7 LED Bank 2 Behavior 8-29

9.1 Absolute Maximum Stress Ratings 9-2

9.2 Operating Conditions 9-2

9.3 LVD Driver SCSI Signals—SD[7:0]+ SD[7:0]
SDP0

−,SREQ+,SREQ−,SACK/+,SACK/−, SHID[2:0]+,

SHID[2:0]
SCD/
SSEL/

−, SMSG/+, SMSG/−, SIO/+, SIO/−,SCD/+,

−,SATN/+,SATN/−, SBSY/+, SBSY/−, SSEL/+,

−,SRST/+,SRST/− 9-3

−,SDP0+,

Contents vii

9.4 LVD Receiver SCSI Signals—SD[7:0]+, SD[7:0]−,SDP0+,

−, SREQ/+, SREQ/−, SACK/+, SACK/−,SMSG/+,

SDP0
SMSG/
SBSY/+, SBSY/
SHID[2:0]+, SHID[2:0]

9.5 SE SCSI and SFF-8067 Signals—SD[7:0]+, SD[7:0]
SHID[2:0]+, SHID[2:0]
SREQ

−, SIO/+, SIO/−, SCD/+, SCD/−,SATN/+,SATN/−,

−, SSEL/+, SSEL/−,SRST/+,SRST/−,

− 9-4

−,

−,SDP0+,SDP0−,SREQ+,

−,SACK+,SACK− 9-4

9.6 SCSI Signals—DIFFSENS 9-5

9.7 Bidirectional 80C32 Signals—AD[7:0], A[15:8], ALE,
PSEN/, RD/, WR/ 9-5

9.8 Input Signals—CLK, TCK, TMS, TDI, TRST/, TESTIN 9-5

9.9 Bidirectional Signals—RESET/, TESTOUT, CL0, SDA0,
SCL1, SDA1 9-6

9.10 Bidirectional Signals—MPIO0[7:0], MPIO1[7:0],
MPIO2[7:0], MPIO3[3:0] 9-6

9.11 Bidirectional Signals—MPLED0[7:0], MPLED1[7:0],
MPLED2[7:0] 9-6

9.12 SYM53C040 Clock Timings 9-7

9.13 Reset Timings 9-8

9.14 External Memory Interface Timings 9-9

9.15 External Data Read Timings 9-10

9.16 External Data Write Timings 9-11

9.17 Multipurpose I/O and LED Timings 9-12

9.18 Two-Wire Serial Interface Timings, Normal Mode
(100 KHz Clock) 9-13

9.19 Two-Wire Interface Timings, Fast Mode (400 KHz Clock) 9-13

9.20 SFF-8067 Interface Timings 9-15

9.21 Initiator Asynchronous Send Timings 9-16

9.22 Initiator Asynchronous Receive Timings 9-17

9.23 Target Asynchronous Send Timings 9-18

9.24 Target Asynchronous Receive Timings 9-19

A.1 Register Summary by Description A-1
A.2 Register Summary by Address A-5

viii Contents

Preface

Audience

Organization

This technical manual provides reference information on the Symbios
SYM53C040 Enclosure Services Processor. It contains a complete
functional description for the product and includes complete physical and
electrical specifications for it.

This manual assumes some prior knowledge of current and proposed
SCSI, I
standards for parallel SCSI devices, as well as a detailed understanding
of serial data communication. It is intended for system designers who are
using this device to manage SCSI or Fibre Channel peripheral device
enclosures.

This document has the following chapters and appendix:

2

C, and SFF-8067 standards, including the SAF-TE and SES

®

• Chapter 1, Introduction, contains general information about the

SYM53C040, including an overview of its features and functions.

• Chapter 2, Functional Description, describes the main functions of

the chip in more detail, including the major interfaces.

• Chapter 3, Signal Descriptions, contains the pin diagrams and

descriptions of each signal.

• Chapter 4, SCSI and DMA Registers

• Chapter 5, SFF-8067 Registers

• Chapter 6, Two-Wire Serial Registers

• Chapter 7, Miscellaneous Registers

• Chapter 8, System Registers

Preface ix

• Chapter 9, Electrical Characteristics, contains the operating

• Appendix A, Register Summary

Related Publications

For background information, please contact:

ANSI

11 West 42nd Street
New York, NY 10036
[phone]
Ask for document number X3.131-199X (SCSI-2)

Global Engineering Documents

15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
Ask for document number X3.131-1994 (SCSI-2); X3.253 (SCSI-3

Parallel Interface); or NCITS 305-199x (SCSI-3 Enclosure Services
(SES) Specification working draft)

SCSI Accessed Fault-Tolerant Enclosures (SAF-TE) Specification

This document can be downloaded from www.safte.org

conditions and AC timings for the chip and mechanical drawings.

Symbios Electronic Bulletin Board

[phone]

SCSI Electronic Bulletin Board

[phone]

Symbios World Wide Web Home Page

www.symbios.com

Symbios Internet Anonymous FTP Site

ftp.symbios.com (204.131.200.1)
Directory: /pub/symchips/scs i

SFF-8067 Specification

ENDL Fax Access
[phone] (call from a FAX machine)

xPreface

I2C Bus Specification

2

For general information about the I

C bus, contact Philips

Semiconductors at www.semiconductors.philips.com

Conventions Used in This Manual

The first time a word or phrase is defined in this manual, it is italicized.
The word assert means to drive a signal true or active. The word

deassert means to drive a signal false or inactive. Signals that are active
LOWendina“/.”

Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.

Revision Record

Page No. Date Remarks

all April 1998 Initial Release
all December 1998 Preliminary Revision 2.0
all February 2000 Version 2.5

Preface xi

xii Preface

Chapter 1
Introduction

This chapter provides general overview information on the SYM53040
Enclosure Services Processor. The chapter contains the following
sections:

• Section 1.1, “SYM53C040 Overview”

• Section 1.2, “SCSI Mode”

• Section 1.3, “SFF-8067 Mode”

• Section 1.4, “Features Summary”

1.1 SYM53C040 Overview

The SYM53C040 is an integrated Enclosure Services Processor (ESP)
device that provides enclosure monitoring services for SCSI and Fibre
Channel enclosures. It supports the SCSI Accessed Fault-Tolerant
Enclosures (SAF-TE) and SCSI-3 Enclosure Services (SES) enclosure
specifications.

The enclosure monitoring services in the SYM53C040 allow a single chip
solution for monitoring disk drives, power supplies, cooling systems, and
other system services. Support for standard protocols such as SAF-TE
and SES provide a nonproprietary way for third party disk and RAID
controllers to be automatically integrated with peripheral enclosures that
support status signals, hot swapping of hard drives, and monitoring of
enclosure components. This decreases component cost and increases
system reliability in distributed storage environments where status
information on system resources, such as disk drives, must be available
to multiple controllers. SCSI/SAF-TE Enclosure Implementation.

Symbios SYM53C040 Enclosure Services Processor Technical Manual 1-1

1.2 SCSI Mode

The SYM53C040 uses the SCSI bus to report system information such
as enclosure temperature, power supply status, and disk slot status to
the host SCSI controller. It also responds to host SCSI controller
commands by generating control outputs to enable and disable disk
slots, drive indicator displays, or perform other system tasks. The
SYM53C040 supports Low Voltage Differential (LVD) access as well as
Single-Ended (SE) SCSI access without the need for external
transceivers. Figure 1.1 shows a typical SCSI enclosure implementation
with the SYM53C040.

Figure 1.1 SCSI/SAF-TE Enclosure Implementation

SCSI Drive Enclosure

SCSI or PCI RAID

Host Adapter

LVD SCSI

LVD

SYM53C040

Enclosures Ser vices

SE

SAF-TE

SYM53C141

Isolation and Conversion

SAF-TE

SE

Drive
Drive
Drive
Drive
Drive

Drive
Drive
Drive
Drive
Drive

Primary
Power 1

Primary

Power N

Fan 1

Fan N

Temp

Sensor

Door
Lock

1-2 Introduction

1.3 SFF-8067 Mode

As an alternative to SCSI, the two SFF-8067 interfaces in the
SYM53C040 allow it to communicate data between a Fibre Channel
enclosure and the Fibre Channel host, using the SFF-8067 physical
interface and the SES protocol to monitor the power supply, cooling
system, and other alarms or status indicators in the enclosure. It also
reports this information to the Fibre Channel host controller and
generates control outputs to control system components, in response to
host commands. Figure 1.2 shows a typical Fibre Channel enclosure
design.

Figure 1.2 SFF-8067/SES Enclosure Implementation

SYM40920

Fibre Channel

Host Adapter

Thermometer

TX
RX

RX

TX TXTX

NL_Port

NVRAM

Detail

TWS Serial Bus (Primary)

TWS Serial Bus (Secondary)

RX RX RX

8067

Interface

RX

8067

Interface

SYM53C040

Enclosure

Services

Processor

MPIO/MPLED Pins

RX

8067

Interface

TX

Primary

8067

Interface

RX

SFF-8067

RX

TX

Secondary

8067

Interface

SFF-8067 Mode 1-3

1.4 Features Summary

The following are the key features of the SYM53C040 as they relate to
flexibility, integration, ease of use, reliability and performance.

• Supports the SAF-TE protocol in SCSI environments, and the SES

protocol in either SCSI or Fibre Channel environments

• Two SFF-8067 interfaces provided for Fibre Channel Enclosure

applications

• 28 multipurpose I/O pins and 24 multipurpose LED drivers for flexible

configurations

• TwoprogrammableLEDblinkrates

• Watchdog timer with time-out values programmable between 20 ms

and 300 ms

• Two on-chip timers external to the microcontroller

• Downloadable/upgradable firmware

• On-chip SE and LVD SCSI transceivers for direct attach to either LVD

or SE SCSI bus

• 16 Kbytes of onboard static RAM

• Two multimaster, two-wire serial interfaces for automatic download of

external firmware, and access to external two-wire serial peripherals

• Integrated 80C32 (MCS 51 compatible) microcontroller

• 160-pin QFP or 169-ball BGA packaging

• Two-wire serial interface for automatic download of external firmware

• Full featured SAF-TE firmware provided by LSI Logic

• Proven SYM53C80 core for basic SCSI protocol management

• 16 mA open drain LED drivers

• 5 Volt tolerant inputs (except DIFFSENS)

• IEEE 1149.1 JTAG compliant

• Hardware DMA function for increased SCSI throughput

• Support for 11 LVD SCSI IDs (0–7 plus three high IDs)

1-4 Introduction

Chapter 2
Functional Description

This chapter describes the main functional blocks of the SYM53C040.

Figure 2.1 is a high-level functional overview of the device, followed by a

high-level description of each item. The remainder of the chapter
describes these functional areas in more detail.

• Section 2.1, “Functional Blocks”

• Section 2.2, “Memory Map”

• Section 2.3, “SCSI Core Operation”

• Section 2.4, “DMA Function”

• Section 2.5, “Microcontroller Operation”

• Section 2.6, “Two-Wire Serial Interface Operation”

• Section 2.7, “Power-On Configuration Options”

• Section 2.8, “Resets”

• Section 2.9, “SFF-8067 Mode”

• Section 2.10, “Interrupts”

• Section 2.11, “JTAG Boundary Scan Testing”

Symbios SYM53C040 Enclosure Services Processor Technical Manual 2-1

Figure 2.1 SYM53C040 Block Diagram

External Firmware

Storage and/or

Two-Wire Peripheral

Devices

Microcontroller

Address/Data Bus

External RAM or

ROM (Optional)

16 K SRAM

SCSI Control

SE

or LVD 8-Bit

SCSI Bus

SYM53C80-

Based

Logic

Mux

Two SSF8067

or

80C32

Microcontroller

SFF8067 Mode

Control Logic

Bidirectional
Connections

DMA

Function

Two-Wire

Serial

Interface

Two-Wire

Serial

Interface

Multiplexed

I/O Register Set

(Accessible by

Firmware Only)

External Control of

Sensors, LEDs, etc.

2-2 Functional Description

2.1 Functional Blocks

Following are brief descriptions of the main functional blocks comprising
the SYM53C040.

2.1.1 SYM53C80-Based SCSI Control Logic

The SCSI core in the SYM53C040 is based on the SYM53C80 SCSI
controller. The SYM53C80 is a first generation SCSI protocol controller
that provides simple, register-based access to SCSI control and data
signals. This core provides additional support for parity checking and a
DMA function. It supports only asynchronous SCSI transfers. It supports
both SE and LVD SCSI transfers. The SYM53C80 register set is mapped
into the Internal Features register block as shown on the memory map
in Figure 2.2. These registers are described in Chapter 4.

2.1.2 80C32 Microcontroller Core

The 80C32 microcontroller core used in the SYM53C040 is an 8-bit Intel
MCS 51 family compatible device with 256 bytes of internal scratch RAM.
This microcontroller uses a shared address/data bus and can address
either 64 Kbytes of shared program and data memory or 16 Kbytes of
internal memory and 47 Kbytes each of external program and data
memory spaces. The microcontroller executes one instruction every 12
clocks. Additional functionality includes two 16-bit timers, a full-duplex
UART, and two additional external interrupt sources (five interrupt
sources total).

2.1.3 Two-Wire Serial Interface

The SYM53C040 has 2 Two-Wire Serial interface blocks that provide
access to external serial EEPROM storage and any other user-defined,
two-wire peripheral devices. The SYM53C040 can attempt to download
from an external serial ROM through one interface at power-on or reset.
External two-wire devices are connected to the SDA and SCL signal pins
on the SYM53C040. The Two-Wire Serial interface blocks are controlled
by a set of control registers in the Internal Features register block as
shown on the memory map in Figure 2.2. These registers are described
in Chapter 6.

Functional Blocks 2-3

2.1.4 SFF-8067 Interface

The twoSFF-8067 interfaces allow the SYM53C040 to communicate with
Fibre Channel SCA-2 devices to transfer SES information to/from Fibre
Channel host controllers. The information is transferred across the signal
pins used to provide the loop identifier to the SCSI device. Details of the
protocol are provided in the SFF-8067 draft specification.

2.1.5 16KbytesSRAM

The SYM53C040 contains 16 Kbytes of internal static RAM for data and
firmware storage. Under microcontroller control, the internal RAM may be
loaded with additional firmware from an external parallel ROM, or
automatically from a serial EEPROM using the Two-Wire Serial interface.

2.1.6 DMA Function

The DMA block provides memory access from and to the SCSI core.
During DMA operations, the microcontroller is put in an idle state and the
internal bus is driven by the DMA block. External memory access by the
DMA block happens in the same way that microcontroller memory
accesses occur. Control of the DMA block is achieved through a set of
control registers shown on the memory map in Figure 2.2 and is
described in Chapter 4.

2.2 Memory Map

All memory accesses are visible on the external microcontroller memory
bus. Figure 2.2 is the memory map of the SYM53C040.

Note:

Note:

The external parallel ROM must not be mapped into the
first 16 Kbytes or the last 1 Kbyte of the external memory.

It is the responsibility of the system designer to prevent
other external devices from conflicting with internal memory
options.

2-4 Functional Description

Figure 2.2 SYM53C040 Memory Map

0x0000
0x0032

0x0033

0x3FFF

0x4000

0xFBFF
0xFC00

0xFFFF

Interrupt Vectors

16 Kbytes Internal RAM

47 Kbytes Externa l

Address Space

1 Kbyte Internal

Features Registers

The address decode block in the SYM53C040 decodes addresses
generated by the microcontroller and multiplexes memory space
accesses between the different register and memory blocks according to
the memory map.

2.3 SCSI Core Operation

The SYM53C040 uses a SCSI core based on the SYM53C80 first
generation SCSI architecture. The SYM53C80 architecture supports
8-bit, asynchronous only SCSI data transfers. It supports both SE and
LVD SCSI transfers. The core contains support for parity generation and
checking, initiator and target operation, arbitration, and interrupts to the
microcontroller. The core is controlled by several registers that are
described in Chapter 4.

2.3.1 Recommended Use of SCSI High ID Pins

The SCSI core in the SYM53C040 is designed for 8-bit SCSI applications
only. However, the SYM53C040 contains some additional logic that
allows the device to have three SCSI high IDs, in addition to 0–7, so that
the SYM53C040 can be given lower priority on a wide SCSI bus.
However, the SYM53C040 cannot perform selection or reselection on a
wide bus; parity checking during the selection/reselection phase may be

SCSI Core Operation 2-5

in error and should not be monitored. This limits the SYM53C040 to only
target applications, with no disconnects, on a wide bus.

To select a high ID for the SYM53C040, connect any of the SCSI high
data lines (8–15) to one of the SHID[2:0] pins. The user can monitor the
value of the SHID[2:0] pins by reading the SHID[2:0] bits in the Current

SCSI Data High (CSDHI) register (0xFC08). The Select Enable High
(SENHI) register allows a bit to be set that corresponds to the device

SCSI ID. This allows an interrupt to be generated if the corresponding
data line is driven during selection, if the data line is connected to the
appropriate SHIDx pin. Figure 2.3on page 2-7 illustratesSCSI arbitration
and selection/reselection and DMA target transfers.

2-6 Functional Description

Figure 2.3 Initiating Arbitration and Selection/Reselection

Reset ARB

(0xFC02 Bit 0)

Write ID Bit to

Output Data Register

(Reg. 0xFC00)

Set ARB

(0xFC02 Bit 0)

Set AS_LVD

(0xFC02 Bit 7)***

Check

Arb. In Prog. Bit

(0xFC01 Bit 6)

A

Wait 2.2 s

Arbitration Delay

1

Yes

Check

Lost Arb.Bit

(0xFC01 Bit 5)

Read 0xFC00to See
If a Higher Priority ID

Is Present

Higher

Priority ID

Present

B

SetAssertSEL/Bit

(0xFC01 Bit 2)

1

Reset SEL

(0xFC01 Bit 2)

0

1

0

?

No

A

B

Check

Lost Arb.Bit

(0xFC01 Bit 5)

0

Wait 1.2

(Bus Clear + Settle)

Set Target Mode Bit

(0xFC03 Bit 1)***

SetAssertI_O/Bit

(0xFC01 Bits 3, 0)

µsMin.

(0xFC02 Bit 6)*

Set TE

(0xFC03 Bit 0)*

Write Target and
Initiator’s ID Bits

to Output Reg.
(Reg. 0xFC00)

Assert BSY/ and
Assert Data Bus

Reset ARB Bit

(0xFC02 Bit 0)

Information TransferPhases

* Reselection Only
** Poll Interrupt

*** LVD operation only

C

Reset Assert BSY/

Bit (0xFC01 Bit 3)

Selection/

Reselection

Complete?

**

Yes

BSY/

Asserted within

250 ms

?

Yes

Reset the Select

Enable Register

(Reg. 0xFC04)

Set Assert BSY/

(0xFC01 Bit 3)*

Reset SEL/ and

Assert Data Bus

(0xFC01 Bits 2, 0)

Reset AS_LVD

(0xFC02 Bit 7)***

Request Active Bit or
wait for interrupt

No

No

Selection
Time-out

C

SCSI Core Operation 2-7

2.3.2 LVD Link™ Technology

To support greater device connectivity and a longer SCSI cable, the
SYM53C040 includes LVD Link technology ,the LSI Logic implementation
of LVD SCSI. LVD Link transceivers provide the inherent reliability of
differential SCSI, and a long-term migration path for faster SCSI transfer
rates.

LVD Link technology is based on current drive; its low output current
reduces the power needed to drive the SCSI bus, so that the I/O drivers
can be integrated directly onto the chip. This reduces cost and
complexity compared to high-power differential designs. LVD Link lowers
the amplitude of noise reflections and allows higher transmission
frequencies.

The LSI Logic LVD Link transceivers operate in LVD and SE modes. The
SYM53C040 automatically detects which type of signal is connected,
based on voltage detected by the DIFFSENS pin.

The RBIAS+ and RBIAS
operation. A resistor value of 9.76 k
illustrated in Figure 2.4.

Figure 2.4 LVD Resistor Value

3.3 V

9.76 kΩ
RBIAS +

RBIAS −

2.3.3 Programmed I/O Transfers

Programmed I/O is the most primitive form of data transfer. The REQ/
and ACK/ handshake signals are individually monitored and asserted by
reading and writing the appropriate register bits. This type of transfer is
normally used when transferring small blocks of data such as command
blocks or message and status bytes. Figure 2.5 illustrates a programmed
I/O transfer.

A Target Send operation begins when the ACD (Assert C_D/), AIO
(AssertI_O/),andAMSG(AssertMSG/)bitsintheTarget Command

− signals are the bias resistors for LVD
Ω,= ±=1%, is recommended, as

2-8 Functional Description

(TC) register are set to the correct state so that a phase match exists. In

addition to the phase match condition, the Assert Data Bus bit (bit 0 in
register 0xFC01) must be set and the I/O signals must be deasserted for
theSCSIcoretosenddata.

For each transfer, the data is loaded into the Output Data (ODR) register
(0xFC00) and the Assert REQ/ bit (0xFC03, bit 3) is set. The
microcontroller must then wait for the REQ/ bit (0xFC04, bit 5) to become
active. Once REQ/ goes active, the Phase Match bit (0xFC05, bit 3) is
checked and the Assert ACK/ bit (0xFC01, bit 4) is set. The REQ/ bit is
sampled until it becomes false and the microcontroller resets the Assert
ACK/ bit to complete the transfer.

In addition to target send, programmed I/O transfers can also be used
for target receive, initiator send, and initiator receive operations.

Figure 2.5 illustrates target send and receive operations.

SCSI Core Operation 2-9

Figure 2.5 Programmed I/O Target Transfers

Target Receive

Set Info. Transfer

Phase

(0xFC03 Bits [2:0]

Target Send Only

Output Data Reg.

Target Send Only

Set Assert Data

(Reg. 0xFC01, Bit 0)

(0xFC03 Bits [2:0]

Set Transfer

Counter in

Memory

WriteDatato

(Reg. 0xFC00)

Bus Bit

Set Assert

REQ/ Bit

(0xFC03, Bit 3)

ACK/

Active?

(0xFC05, Bit 0)

Target Send

Set Info. Transfer

Phase

No

No

A

ACK/

Inactive?

(0xFC05, Bit 0)

Yes

Decrement

Transfer Counter

In Memory

Tra nsfer
Counter

Equal Zero

?

Yes

Go to Next Phase

No

Target Receive Only

Yes

Read Data from
SCSI Data Reg.

(Reg. 0xFC00)

Reset Assert

REQ/ Bit

(0xFC03, Bit 3)

A

2-10 Functional Description

2.3.4 SCSI - DMA Transfers

In the SYM53C040, DMA handshaking with the SCSI core is handled
automatically by the DMA function. In order to initiate a DMA transfer to
the SCSI core using the DMA function in the SYM53C040, the following
sequence must be performed:

1. The DMA Transfer Length (DTL) register and the DMA

Source/Destination Low (DSDL) and DMA Source/Destination High
(DSDH) address registers (0xFC11–0xFC13) must be written.

2. The DMA Status (DS) register (0xFC10)iswrittenwitha1inthebit
0 (TIP) position.

3. The firmware sets bit 0 in register 0x87 of the microcontroller core to
place the core in idle mode.

4. The DMA waits for the microcontroller to enter the idle mode before
taking over the internal bus for memory reads or writes.

5. Once the DMA receives a request from the SCSI core, the transfer
begins.

Figure 2.6 illustrates a target mode DMA transfer .

2.3.4.1 Halting a DMA Operation

Any SCSI or DMA interrupt, if enabled in the Interrupt Mask (IMR)
register, terminates the DMA cycle for the current bus phase. It is
recommended that the DMA Mode bit be reset after receiving an
interrupt. The DMA Mode bit must be set before writing any of the Start
DMA registers for subsequent bus phases.

SCSI Core Operation 2-11

Figure 2.6 DMA Target Mode Transfers

Write IMR

(0xFE0D) to Enable
only DMA Interrupts

A

Write Transfer

Length to DTL

Register (0xFC11)

Write Source/

DestinationAddresses

to 0xFC12, 0xFC13

Set TIP Bit In
0xFC10 Bit 0

Set DM, and

TGTM Bits

(0xFC02 Bits 6, 1)

Enable Parity Checking, Enable Parity

InterruptsMayBeSetatthisTime

Target Receive

(Data Out Phase)

Reset Assert I_O/,

MSG/, and C_D/ Bits

(0xFC03 Bits [2:0]

Target Send

(Data In Phase)

SetAssertI_OBit

Reset C_D/

and MSG/

(0xFC03 Bits [2:0]

Set ADB Bit

(Reg. 0xFC01, Bit 0)

SetBit1inRegister

Microprocessor

Core to Put It into

Power Down Mode

Wait for an Interrupt

ISR - Clear Interrupt

(0xFC10 Bit 3)

(0xFC02 Bit 1)

Reset Assert
Data Bus Bit

(0xFC01 Bit 0)

0x87 of the

DMA

Interrupt

?

Yes

(0xFC0E)

TC Bit Set?

Yes

Reset DMA

Mode Bit

No

Error Recovery

Target Send Only

Write to Start DMA

Target Receive

Register (0xFC06)

Write to DMA Send

Register (0xFC05)

A

2-12 Functional Description

Enable Other

Necessary Interrupts

That Were Disabled

for DMA Transfer

2.4 DMA Function

The SYM53C040 DMA function is designed to automatically handshake
with the SCSI core forSCSI send and receive operations.For SCSI send
operations, the DMA reads a byte from memory and writes it to the SCSI
core when requested. For receive operations, the DMA receives a byte
from the SCSI core and writes it to memory.

After setting up the transfer length and source/destination addresses, a
DMA operation begins with the microcontroller setting the TIP bit in the

DMA Status (DS) register.Next,thefirmwaresetsbit1inregister0x87

of the microcontroller core to place the core into idle mode while the
DMA waits for the microcontroller to halt. With the microcontroller halted,
the DMA has control of the internal bus. For a send, the DMA first reads
a byte of data from internal or external memory. After each byte transfer,
the DMA Transfer Length (DTL) register will be decremented and the
address register incremented.

Note:

This cycle repeats until the transfer length is zero, which indicates the
last byte is being transferred.

A DMA receive operation happens in much the same way. This data byte
is written to the memory address pointed to by the DMA address
registers. Finally, the DMA TransferLength (DTL) register is decremented
and the address pointer register is incremented.

This cycle repeats until the transfer length is zero. This indicates the last
byte is being transferred.

If any interrupt not masked in the Interrupt Mask (IMR) register is
generated during a DMA transfer, the microcontroller will come out of idle
mode and the DMA transfer will be halted. The DMA address pointer and
transfer length registers will not be cleared, so that the microcontroller
can determine at what point the transfer was interrupted.

During DMA transfers, the DMA block controls the internal bus and the
pins that bring these signals out to external memory. External memory
accesses function as illustrated in Figure 2.7.

The entire address, which is a combination of two byte-wide
registers, will be incremented.

DMA Function 2-13

Figure 2.7 DMA External Memory Access

ALE

WR/orRD/

AD[7:0]

A[15:8]

2.5 Microcontroller Operation

The 80C32 microcontroller core used in the SYM53C040 is an 8-bit Intel
MCS51familycompatibledevicewith256bytesofinternalscratchRAM
and no internal ROM. This microcontroller uses a shared address/data
bus and can address either 64 Kbytes of shared program and data
memory or 16 Kbytes of internal memory and 47 Kbytes each of external
program and data memory spaces. The microcontroller executes one
instruction every 12 clocks. Additional functionality includes two 16-bit
timers, a full-duplex UART, and two additional external interrupt sources
(five interrupt sources total).

For more information on the operation of the microcontroller core, refer
to documentation on the Intel MCS 51 embedded microcontroller family.

The microcontroller core has two external interrupt functions as well as
the TXD and RXD serial port functions. The user can access these
functions on the microcontroller core by setting the External Interrupt
Enable and Serial Port Enable bits in the System Control (SYSCTRL)
register (0xFF05).

AddressAddress Data/Input

High Address

2.5.1 ONCE Mode

ONCE mode is available for use as in any standard Intel 80C32
microcontroller. However, the DMA feature cannot be used when the
microcontroller is in ONCE mode. This is because the DMA logic inside
the SYM53C040 looks for a signal from the microcontroller to indicate
that it is halted before beginning any DMA operation. ONCE mode does
not provide this signal to the DMA logic.

2-14 Functional Description

To enter ONCE mode, hold ALE low while bringing RESET/ to low, then
releasing it to high. ONCE mode should be used for testing or diagnostic
purposes only, and should be disabled during normal chip operation.

2.6 Two-Wire Serial Interface Operation

The Two-Wire Serial interface performs two main functions: it
automatically downloads firmware from an external serial EEPROM
device, and it serves as a Two-Wire Serial port with full multimaster and
slave capability that can communicate with external Two-Wire Serial
devices. The Two-Wire Serial interface in the SYM53C040 provides the
microcontroller an additional means to gather external system
information. The Two-Wire Serial interface supported by the SYM53C040
is compliant with the I
illustrates serial busactivityduring a readoperation. Figure 2.9 illustrates
serial bus activity during a write operation.

Figure 2.8 Serial Read Operation

2

C bus defined by Philips Electronics. Figure 2.8

Master

Slave

Control Byte

Device ID

Start Condition

Address Byte
(1 or 2 Bytes)

0

R/W

Bit

ACK

ACK ACK

Figure 2.9 Serial Write Operation

Master

Slave

Control Byte

Device ID

Start Condition

Address Byte

0

R/W

Bit

ACK

ACK ACK

Control Byte

Device ID

Repeated Start Condition

Data Byte

1

Data Byte Last Data Byte

by an ACK, up

(Moredata bytes

ACK No

(More data

bytes may be

transferred,

each followed

to capacity of

slave device)

may be

transferred,

each followedby

an ACK)

Last Data Byte

ACK

ACK

Stop Condition

Stop Condition

Two-Wire Serial Interface Operation 2-15

2.6.1 Two-Wire Serial Interface Transfer Rate

The Two-Wire Serial interface performs all initial downloads at a

78.125 kHz SCL clock rate (with a 40 MHz system clock). At 78.125 kHz,

an entire 64 Kbit (8 Kbit x 8) serial EEPROM device can be downloaded
in under 945 ms. Other SCL clock rates can be achieved by
programming the Clock (ES0, ES1, ES2 = 010) register
(0xFD00/0xFD02). See Chapter 6 for more information on the Clock
register in the Two-Wire Serial register block.

2.6.2 Power-On Serial ROM Download

At power-on, the Two-Wire Serial interface in the SYM53C040 attempts
to read from a serial EEPROM with slave address 0b1010, and a chip
address defined at power-on through the use of external pull-up/pull­down options on signal pins A10, A9 and A8. These options are
summarized in Table 2.4. The initial download attempt can also be
skipped if no pull-up resistor is used on signal pin AD5. Signal pin A11
indicates which serial interface will perform the initial download if the AD5
signal is high. A low on pin A11 indicates the download will occur through
serial port 0 while a high indicates the download will occur through serial
port 1. If an initial serial ROM download is attempted, the microcontroller
core will be delayed in fetching its first instruction until the download has
completed, so that firmware downloaded from the serial ROM can be
executed first if desired. Table 2.1 lists the contents of the initial ROM
download to the SYM53C040. Figure 2.10 illustrates a typical download
sequence. The device ID to download from is 1010abc. The 0b1010
denotes a ROM device, and the “abc” value is the serial ROM chip
address, determined by the configuration of the A[10:8] pins as
presented in Table 2.4.

2-16 Functional Description

Figure 2.10 Serial ROM Download

Address Low Byte

Register 0xFD06

RAL[7:0]

ACK ACK

Master

Slave

Device ID 0

Start Condition

Address High Byte

Register0xFD05

RAH[7:0]

R/W

Bit

ACK

On a power-on reset or on a soft-chip reset (watchdog timer expires or
the RESET/ pin toggles), the download logic will download data
beginning at address 0x00 of the two-wire slave ROM device.

Table 2.1 Initial ROM Download Contents

Byte Contents

0 Destination address low
1 Destination address high
2 Firmware length (n) low (includes checksum byte but not destination address bytes)

1010abc

EEPROM
Device ID

Repeated Start Condition

ACK

(More data

1

Chip
Addr

Data Byte Last Data Byte

bytes may be

transferred,

each followed

by an ACK)

ACK

Register 0xFD00Register 0xFD00

D[7:0] D[7:0]

No

ACK

Stop Condition

3 Firmware length (n) high

4throughn+2 Firmware

n + 3 Checksum for firmware (up to maximum supported ROM size)

2.6.3 Address and Length Download Configuration

The first four bytes read from the two-wire external ROM contain the
download destination address and the number of bytes to be
downloaded. The first byte is the destination address low byte. The
second byte is the destination address high byte. The third byte is the
firmware length low byte, and the fourth byte is the firmware length high
byte. The firmware length is the number of bytes of code not including
the two bytes of destination address, or the two bytes of firmware length.
The length does include the final checksum byte. The minimum firmware
length is three bytes.

Two-Wire Serial Interface Operation 2-17

2.6.4 Firmware Download and Checksum

The first step in the download is to read in the destination address and
firmware length. Then the firmware will be read in and written out starting
at the destination address. Each byte is bit wise XORed with the previous
checksum, starting with zeros. The final byte read is the checksum value.
This byte is compared to the calculated checksum. Bit 0 of the

Miscellaneous register (0xFD04) indicates a checksum error. If this bit is

high after download, there was a difference between the calculated
checksum and the last byte read in at download.

2.6.5 Manually Accessing External Two-Wire Serial Devices

The SYM53C040 Two-Wire Serial interface allows the microcontroller
core to manually access external two-wire devices such as temperature
sensors, A/D converters, memory devices or any other I/O device that
adheres to the standard Two-Wire Serial protocol. The SYM53C040 Two­Wire Serial interface always performs single byte read and write
operations when accessed through the register interface, so it is not
intended for maximum throughput with large blocks of data. Figure 2.11
and Figure 2.12 are flowcharts of SYM53C040 serial transmit and
receive operations.

2-18 Functional Description

Figure 2.11 Two-Wire Serial Slave Data Transmit and Receive

Read Byte from

Control/Status

Register

No

Read Byte From

Control/Status

Register

PINBit=0?

Yes

PINBit=0

?

Yes

Read Device

AddressFromData

Register

AAS

Bit Set?

(0xFC03 Bit 2)

Yes

Read

or Write?

(LSB = 1 or 0)

No

No

Interrupt Service

R/W =0R/W =1

Read Byte From

Control/Status

Register

PINBit=0?

Routine

Slave ReceiveSlave Transmit

No

Yes

Yes

ACKReceived?

WriteDatatoData

Write Dummy Byte

(0xFF) to Data

End Transmit

No

(LRB = 1?)

No

Register

Register

PIN deactivated

(set to 1),

SYM53C040

goes into slave

receiver mode

Stop

Detected?

(STS = 1?)

No

Read Data From

Data Register

Read Last Data
Byte From Data

Register

End Receive

Yes

Two-Wire Serial Interface Operation 2-19

Figure 2.12 Two-Wire Serial Master Data Transmit and Receive

Set ES0 Bit In

Register 0xFD01

Read Status

Register (0xFD01)

BB_N=0?

(0xFD01 Bit 0)

No

Write Device ID To

Data Register (0xFD00)

Set Star t Bit In Control

Register (0xFD01)

Read Status

Register (0xFD01)

PINBit=0?
(FC01 Bit 7)

No

Yes

One Byte Left?

Yes

Clear ACK Bit In

Control Register

First Byte?

No

Read Data From Data

Register (0xFD00)

Read Status

Register (0xFD01)

A

Read

or Write?

(LSB = 1 or

0?)

No

Yes

Read Dummy Byte

From Data Register

WriteRead

WriteDatatoData

Register (0xFC00)

Read Status

Register (0xFD01)

PINBit=0?

(0xFD01 Bit 7)

Yes

Last Byte?

Yes

WriteStopBitIn

Control Register

(0xFD01)

Master Transmit

No

No

Yes

PINBit=0?

(0xFD01 Bit 7)

A

Master Receive

No

Last Byte?

Write StopBit In Control

Register (0xFD01)

Read Last Byte From

Data Register (0xFD00)

End Read

2-20 Functional Description

Yes

Yes

No

End Write

Note: All register locations given

are for2-wire serialport 0.
Two-wire serial port 1
transfers operate in similar
fashion.

2.7 Power-On Configuration Options

The power-on configuration of the SYM53C040 can be customized for
different applications using the AD5, AD[1:0], and A[11:8] pins. Table 2.2
summarizes the functionality that is enabled or disabled by using pull-up
resistors on these pins.

Table 2.2 Power-On Configuration Pins and Options

Signal Name Function Pull-up Use

AD[1:0] Automatic branch generation See Table 2.3.
AD5 Serial ROM automaticdownload Enable with external pull-up.
A[10:8] Download configuration address See Table 2.4.

2

A11

1. The values of these pins are latched into the Power-On Configuration Registers (System registers
0xFF01, 0xFF03).

Download serial port select Pull-up resistor changes serial ROM download

from Two-Wire Serial port 0 to port 1.

1

2.7.1 Automatic Branch Generation

At reset, the microcontroller core fetches its first instruction from address
0x0000. Because the interrupt vectors are mapped to locations 0x0003
through 0x0032, an unconditional jump instruction must be issued as the
first instruction fetched from address 0x0000. The SYM53C040 address
decode logic automatically generates this jump instruction when the
microcontroller core accesses address locations 0x0000 through 0x0002
during its initial instruction fetch, if automatic branch generation is
enabled. Three address destinations are possible for this initial automatic
jump, configurable by external pull-up resistors on the AD0 and AD1 pins.
The states of these pins are checked on chip reset. In the SYM53C040,
the AD0 and AD1 signal pins have internal pull-down resistors, so these
pins power-up deasserted if no external pull-up is used. They power-up
asserted with an external pull-up resistor . If an external pull-up resistor
is detected on either of these pins, the internal pull-down resistor will be
disabled to reduce power dissipation. The destination of the first
instruction jump is determined by the power-on values of the AD0 and
AD1 pins, as described in Table 2.3.

Power-On Configuration Options 2-21

Table 2.3 External Pull-up Values for Automatic Branch Generation

External Pull-up on AD1/AD0 First instruction Branch Destination

Pull-up/Pull-up 0x8000

Pull-up/None 0x4000
None/Pull-up 0x0033

None/None Fetched from 0x0000

Address locations 0x0033 and 0x0000 correspond to the internal RAM.
Address locations 0x8000 and 0x4000 correspond to external memory
accesses. Using no external pull-up resistors on AD0 and AD1 disables
the automatic branch instruction generation, and the microcontroller
fetches its first instruction from address 0x0000. If automatic branch
generation is disabled, a branch instruction must be downloaded into
address 0x0000, using an external serial ROM. The power-on setting of
AD0 and AD1 can be read in the Power-On Configuration Zero (POC0)
register (0xFF01) bits 0 and 1, respectively.

2.7.2 External Serial ROM Configuration

The SYM53C040 can attempt to download firmware from a serial ROM
at power-on, through the Two-Wire Serial interface. The serial ROM
download is performed immediately at power-on or after a reset, and the
microcontroller will hold off from fetching its first instruction until the
download completes.

The initial ROM download will be skipped if no external pull-up is used
on the AD5 signal pin (the pin has an internal pull-down). If a pull-up is
detected on the AD5 signal pin, the download will be attempted and the
internal pull-down will be disabled to reduce power dissipation.

2.7.3 Serial ROM Chip Address

The chip address of the serial ROM to be used in the power-on download
can be defined by using pull-up resistors on the A8, A9, and A10 signal
pins. There are eight possible chip addresses for most popular Tw o-Wire
Serial EEPROM devices. Table 2.4 describes the address of the serial
EEPROM device from which the SYM53C040 will attempt the initial
configuration download, based on the values of the A[10:8] signal pins.

2-22 Functional Description

As indicated in the table, the serial ROM chip address mapping is
equivalent to the power-on value of signal pins A[10:8].

T able 2.4 Serial ROM Chip Addresses

Serial ROM Chip Address AD10 Pull-up AD9 Pull-up AD8 Pull-up

1010 000 None None None
1010 001 None None Pull-up
1010 010 None Pull-up None
1010 011 None Pull-up Pull-up
1010 100 Pull-up None None
1010 101 Pull-up None Pull-up
1010 110 Pull-up Pull-up None
1010 111 Pull-up Pull-up Pull-up

2.7.4 Download Port Select

The A11 pin selects which of the Two-Wire Serial interfaces will perform
the initial download. The default for the download is Two-Wire Serial
port 0. A pull-up resistor on the A11 pin starts the download from Two­Wire Serial port 1, after a reset or at power-on.

2.8 Resets

The SYM53C040 can be reset in three different ways: power-on reset,
asserting the reset pin, and an internal chip reset forced by expiration of
the watchdog timer. A power-on reset initializes all chip registers to their
default values and returns the Two-Wire Serial port and the SCSI or
SFF-8067 interfaces to idle states. A power-on reset is caused when
power to the chip has been turned off and is turned back on. Manually
asserting the RESET/ pin triggers a soft reset. This can be done to
initiate a second configuration ROM download for the purpose of adding
more firmware or changing default register values before the chip begins
normal operation.

If the watchdog timer is used and it expires, it causes an internal soft
reset. If the Enable Reset Output bit is also set (0xFF05, bit 7), the

Resets 2-23

RESET/ pin is asserted low (0) to reset external devices. The Watchdog
Reboot bit is set (0xFE00, bit 7) to indicate that the SYM53C040 has
performed a soft reset due to expiration of the watchdog timer. Not all
register values in the SYM53C040 are affected by a soft reset. The
following bits/registers require a power-on reset to return to their default
values:

• 0xFE00, Watchdog Timer Control (WDTC)

• 0xFE02, Watchdog Final Chain (WDFC)

• 0xFF03, Power-On Configuration One (POC1)

• Bit 7, Enable Reset Output, in register 0xFF05, System Control

(SYSCTRL)

2.9 SFF-8067 Mode

The twoSFF-8067 interfaces allow the SYM53C040 to communicate with
Fibre Channel SCA-2 devices. Details of the protocol are provided in the
SFF-8067 specification.

The SFF-8067 port 0 and port 1 interfaces can be controlled either
manually by the microcontroller through direct control of the interface
pins; or automatically by the SFF-8067 interface control logic, which has
the ability to interrupt the microcontroller when input data has been
received over one of the ports or when output data has been requested
at one of the ports.

The SFF-8067 interface is enabled when the DIFFSENS pin is set to
V

. The SCSI pins are reassigned to SFF-8067 pins, as indicated in

DD

Chapter 3.

A simple ping-pong arbitration scheme provides equal priority access
between the two ports, since only one of them can be active at a time.
A drive requests access to the SYM53C040 by asserting the PARALLEL
ESI/ pin on its respective port. If the other port is not being used, the
Discovery and Data Transfer phases can proceed as described in the
SFF-8067 specification. A request for access of the other port will not be
acknowledged until the PARALLEL ESI/ pin is deasserted on the port
that is currently in use.

2-24 Functional Description

Interrupts notify the microcontroller of port access. The Read interrupt
notifies the microcontroller that the Fibre Channel device is requesting
data. The microcontroller responds by clearing the interrupt and writing
one byte of data to the RDATA register which will then be transferred to
the requesting Fibre Channel device. The write interrupt notifies the
microcontroller that the Fibre Channel device has written a byte of data
to the interface. The microcontroller responds by clearing the interrupt
and reading the WDATA register. The SYM53C040 SFF-8067 interface
control is illustrated in a state diagram in Figure 2.13.

Port access is terminated when the PARALLEL ESI/ pin is deasserted. If
the PARALLEL ESI/ pin of the other port is asserted at that time it will
be granted access.

Refer to Chapter 5 for SFF-8067 interface register descriptions.

SFF-8067 Mode 2-25

Figure 2.13 SYM53C040 SFF-8067 Interface Control State Diagram

RESET/ or PESI/ High

8067
IDLE

SEL[6:0] =

PA[6:0]

Discovery

Phase

PESI/ Asserted
(Low)

SEL[3:0] =

PA[3:0]

ENCL_ACK/

Asserted

DSK_RD/ & DSK_WR/
Asserted

SEL[3:0] &

ENCL_ACK/

Deasserted

DSK_RD/ & DSK_WR/ Deasserted

DSK_RD/ Asserted

ENCL_ACK/

Deasserted

DSK_RD/ Deasserted

ENCL_ACK/

Asserted

D[3:0] =

RDATA[7:4]

Write RDATA Register*

Interrupt

RINT Bit = 1

(0xFC22,

Bit 1)*

DSK_RD Asserted

START

TRANSFER

DSK_WR/ Asserted

WDATA[7:4]

= D[3:0]

ENCL_ACK/

Asserted

DSK_WR/ Deasserted

8067 Read

D[3:0]

RDATA[3:0]

ENCL_ACK/

Asserted

DSK_RD/ Deasserted

ENCL_ACK/

Deasserted

Read WDATA Register*

Interrupt

WINT Bit = 1

(0xFC22, Bit 0)*

ENCL_ACK/

Asserted

DSK_WR/Deasserted

Signal Name Asserted

PESI/ (PARALLEL_ESI/) Drive
D[3:0] SYM53C040 or

ENCL_ACK/ SYM53C040
DSK_RD/ Drive
DSK_WR/ Drive

*Items marked with an asterisk require action
by the firmware. All other activities are part of
standard SFF-8067 interface operation.

2-26 Functional Description

Drive

ENCL_ACK/

Deasserted

DSK_WR/ Asserted

WRF Bit = 1

(0xFC22,

Bit 1)

WDATA[3:0]

= D[3:0]

ENCL_ACK/

Asserted

8067 Write

2.10 Interrupts

The SYM53C040 supports the following type of interrupts:

• Microcontroller

• DMA and SCSI

• SFF-8067

• Two-Wire Serial

• Masking and Enabling

• Polling and Hardware

2.10.1 Microcontroller Interrupts

The microcontroller core has two interrupt inputs through which interrupt
requests are presented. The SCSI core, DMA core, the Two-Wire Serial
cores, the two timers, the two SFF-8067 ports, and the two external
interrupt ports all generate interrupts that can be individually routed to
either of the two internal interrupt ports of the microcontroller core. The
MPIO3_[1:0] pins are used as the external interrupt lines. Refer to these
pin descriptions for additional information. The Interrupt Status (ISR)
register (0xFE04), allows the SYM53C040 to quickly determine the
source of an interrupt. The Interrupt Mask (IMR) register (0xFE0D),
allows the corresponding interrupts in the ISR to be masked by writing a
0 to the bit location. All interrupts are disabled by default. The Interrupt

Destination (IDR) register (0xFE0E), allows the corresponding interrupts

of the ISR to be routed to either of the two interrupt inputs of the
microcontroller core.

During DMA operation, the Two-Wire Serial interrupts and the Timer 2
interrupts should be masked from the microcontroller core so it will not
be interrupted until the DMA transfer is complete or interrupted by the
SCSI core or Timer 1. Other interrupts can also bring the microcontroller
core out of idle mode, but only if they occur during the DMA operation.

Table 2.5 summarizes the primary registers and bits that are u sed in

detecting and handling interrupts. The DMA core will pass any SCSI
interrupt along to the microcontroller.

Interrupts 2-27

Table 2.5 Register Bits for Interrupt Handling

Register Bit
Location

0xFE04 Interrupt Status Reports to the microcontroller which blockasserted the interrupt.

0xFE0D Interrupt Mask Clearing individual bits in this register masks the corresponding

0xFE0E Interrupt

0xFC05, bit 7 End of DMA

0xFC02, bit 4 Enable Parity

0xFC02, bit 2 Monitor Busy When set, causes an interrupt from the SCSI core to be

0xFC07 (Read
register)

0xFC10, bit 1 DMA Interrupt

Register or Bit
Name Function

Individual bits in this register may be written to force an interrupt
on the corresponding bit. Refer to the register description for
complete information.

interrupts in the Interrupt Status (ISR) register from being sent
to the microcontroller.

Destination

Transfer

Interrupt

Reset
Parity/Interrupt
Register

Enable

The bits in this register can be set or cleared to route interrupts
to either of the two interrupt sources to the microcontroller core.

This bit is set when the DMA transfer is complete.

When set, causes an interrupt from the SCSI core to occur if a
parity error is detected. The Enable Parity Checking bit must
also be set.

generated for an unexpected loss of BSY/.
Any read to this register resets the Interrupt Request Active bit

(0xFC05, bit 4).

When set, the DMA function will generate an interrupt whenever
the TIP bit (bit 0) transitions from 1 to 0. This signifies that the
transfer completed normally, or was interrupted.

0xFC14, bit 0 DMA Interrupt This is the interrupt value for the DMAfunction.This interrupt will

only be enabled if the IEN bit (bit 1 in register 0xFC10) is set.

2.10.1.1 Interrupt Status Register (0xFE04)

The bits in this register are set when the corresponding interrupt
condition occurs. They are cleared when the interrupt is cleared by the
microcontroller. The register contains interrupt bits for the two SFF-8067
ports or MPIO3_[1:0]; the two programmable timers; the DMA core; the
Two-Wire Serial interfaces; and the SCSI core.

2-28 Functional Description

2.10.1.2 Interrupt Mask Register (0xFE0D)

Clearing the bits in this register masks the interrupts corresponding to
the bits in the Interrupt Status (ISR) register.

2.10.1.3 Interrupt Destination Register (0xFE0E)

This register provides the ability to route an interrupt to either of the two
external interrupt inputs of the microcontroller core. The bits correspond
to the interrupts in the Interrupt Status (ISR) register. Clearing the bit
routes the interrupt to external interrupt 0, and setting the bit routes it to
external interrupt 1.

2.10.2 DMA and SCSI Interrupts

The SCSI core provides an interrupt output to indicate task completion
or an abnormal bus occurrence. The use of interrupts is optional and
may be disabled by resetting the appropriate bits in the Mode (MR)
register (0xFC02)ortheSelect Enable (SER) register (0xFC04).

When an interrupt occurs, the Bus and Status (BSR) register and the

Current SCSI Bus Status (CSBS) register must be read to determine

which condition created the interrupt. The interrupt can be reset by
simply reading the Reset Parity/Interrupt (RPI) register (0xFC07)orby
an external chip reset.

If the SCSI core has been properly initialized, an interrupt will be
generated in the following cases:

• the chip is selected/reselected

• a DMA transfer completes

• aSCSIbusresetoccurs

• a parity error occurs during a data transfer

• a bus phase mismatch occurs

• a SCSI bus disconnection occurs

2.10.2.1 End of DMA Transfer Interrupt

The End of DMA bit determines when a block data transfer is complete.
Receive operations are complete when there is no data left in the SCSI
core and no additional handshakes occurring.

Interrupts 2-29

For send operations, the End of DMA bit is set when the DMA finishes
its transfer, but the SCSI transfer may still be in progress. If connected
as a target, REQ/ and ACK/ should be sampled until both are false. In
the SYM53C040 SCSI core, the Last Byte Sent (bit 7 of the Target

Command (TC) register) may be sampled to determine when the last

byte was transferred.

2.10.2.2 SCSI Bus Reset Interrupt

The SCSI core generates an interrupt when the RST/ signal transitions
to asserted. The device releases all bus signals within a bus clear delay
(800 ns) of this transition. This interrupt also occurs after setting the
Assert RST/ bit (bit 7 of register 0xFC01).

Note:

TheRST/signalisnotlatchedinbit7oftheCurrent SCSI

Bus Status (CSBS) register and may not be active when

this bit is read. For this case, the Bus Reset interrupt may
be determined by default.

2.10.2.3 Parity Error Interrupt

An interrupt is generated for a received parity error if the Enable Parity
Check bit (bit 5) and the Enable Parity Interrupt bit (bit 4) are set in the

Mode (MR) register (0xFC02). Parity is checked during a read of the
Current SCSI Data (CSD) register (0xFC00) and during a DMA receive

operation. A parity error can be detected without generating an interrupt
by disabling the Enable Parity Interrupt bit and checking the Parity Error
flag(bit5inregister0xFC05).

2.10.2.4 Bus Phase Mismatch Interrupt

The SCSI phase lines are the I_O/, C_D/, and MSG/ bus signals. These
signals are compared with the corresponding bits in the Target Command

(TC) register: Assert I_O/ (bit 0), Assert C_D/ (bit 1), and Assert MSG/

(bit 2). The comparison occurs continually and is reflected in the Phase
Mismatchbit(bit3)oftheBus and Status (BSR) register (0xFC05). If the
DMA Mode bit (bit 1 in register 0xFC02) is active and a phase mismatch
occurs when REQ/ transitions from HIGH to LOW, an interrupt (IRQ) is
generated.

A phase mismatch prevents the recognition of REQ/ and removes the
chip from the bus during an initiator send operation. DB0/ through DB7/

2-30 Functional Description

and DBP/ will not be driven even though the Assert Data Bus bit is active.
This interrupt is only significant when the SYM53C040 is connected as
an initiator. It may be disabled by clearing the DMA Mode bit.

Note:

2.10.2.5 Loss of BSY/ Interrupt

If the Monitor Busy bit (bit 2) in the Mode (MR) register (0xFC02)is
active, an interrupt will be generated if the BSY/ signal is asserted for at
least a bus settle delay (400 ns). This interrupt may be disabled by
resetting the Monitor Busy bit.

2.10.3 SFF-8067 Interrupts

The SFF-8067 interfacegenerates two types of interrupts: read interrupts
and write interrupts. The read interrupt notifies the SYM53C040 that the
Fibre Channel device is requesting data. The SYM53C040
microcontroller core should respond by clearing the interrupt and writing
one byte of data to the RDATA register, which is transferred to the
requesting drive. The write interrupt notifies the SYM53C040 that the
drive has written a byte of data to the interface. The SYM53C040
microcontroller core should respond by clearing the interrupt and reading
the WDATA register. The Port Control/Status (PCST0/PCST1) registers
(0xFC22/0xFC2A), bits [1:0] indicate whether a read or write interrupt
has occurred.

It is possible for this interrupt to occur when connected as
a target if another device is driving the phase lines to a
different state.

2.10.4 Two-Wire Serial Interrupts

An interrupt from the Two-Wire Serial block is caused by one of the
following conditions:

• A byte has been transferred (Status register 0xFD01/0xFD03, bit 3)

• A Two-Wire Serial bus error (register 0xFD01/0xFD03, bit 4)

• The chip is addressed as a slave (register 0xFD01/0xFD03, bit 2)

The External Interrupt Enable bit (0xFD01/0xFD03, bit 3) enables the
interrupt output to the microcontroller , while the Pending Interrupt bit (bit 7)
is clear. The PIN bit is active when the Two-Wire Serial interface has
completed an operation and requires processor intervention to continue.

Interrupts 2-31

2.10.5 Masking and Enabling Interrupts

Table 2.5 lists the registers used for masking and enabling interrupts. For

testing purposes, certain types of interrupts can be forced by writing
individual bits in the Interrupt Status (ISR) register (0xFE04). These
interrupts can be masked by clearing the corresponding bit in the

Interrupt Mask (IMR) register (0xFE0D). Even if the interrupt is masked,

the corresponding bit in the ISR will be set if the interrupting condition
occurs.

Masking an interrupt prevents it from being seen by the microcontroller
core in the SYM53C040. You can allow hardware interrupts either by
enabling them in the appropriate register bits, or by masking the
interrupts and polling for them. In general, it is recommended to enable
as few interrupts as possible and mask/poll for them instead. With the
microcontroller and the serial transfer rates on the Two-Wire Serial bus,
masking and polling for interrupts is less disruptive to the microcontroller
and does not impede performance. An exception to this recommendation
would be SCSI and 8067 interrupts, since the bus speeds and the need
to complete transfers quickly suggest that interrupts should be enabled.

2.10.6 Polling and Hardware Interrupts

The microcontroller core is informed of an interrupt condition by polling
or hardware interrupts. Polling means that the microcontroller must
continually loop and read a register until it detects a bit set that indicates
an interrupt. This method is the fastest, but consumes microcontroller
time that could be used for other tasks. The other method for detecting
interrupts is hardware interrupts, where the interrupting condition asserts
one of the microcontroller external interrupt signals. This interrupts the
microcontroller, and causes it to execute an interrupt service routine. A
hybrid approach is common, using hardware interrupts for conditions that
might occur infrequently or after a long wait; and polling for interrupts that
typically occur after only a short wait.

2.10.7 Interrupt Service Routine

When the microcontroller core receives an interrupt, it reads the Interrupt

Status (ISR) register (0xFE04) to determine the source of the interrupt.

Once it determines the source of the interrupt, it reads the appropriate

2-32 Functional Description

bits for determining the exact cause of the interrupt. This activity is
described in Table 2.6.

Table 2.6 Interrupt Handling

ISR Bit

Number Interrupt Source

7 SCSI core BSR (0xFC05) Monitors SCSI bus control

6 Two-wire serial port 0 Status (0xFD01) Contains PIN bit plus other

5 Two-wire serial port 1 Status (0xFD03) Contains PIN bit plus other

4 DMA core DMAI (0xFC14) Enables DMA interrupt.
3

Timer 2

2

Timer 1

Locationtoreadto

determine cause of

interrupt Description

signals not found in CSBS,
plus six other status bits.

CSBS (0xFC04) Monitors SCSI bus control

lines plus data parity bit.

CSD (0xFC00), CSDHI
(0xFC08)

T2C (0xFE09) Programs Timer 2, and

T1C (0xFE05) Programs Timer 1, and

Reads the active SCSI bus.

status bits.

status bits.

enables an interrupt upon
expiration of the timer.

enables an interrupt upon
expiration of the timer.

1 8067 Port 1 or MPIO3_1 MPI3 Reads the values of

MPIO3_[1:0]pins, whichalso
serve as external interrupt
lines to the microcontroller
core.

PCST1 (0xFC2A) Read Interrupt and Write

0 8067 Port 0 or MPIO3_0 MPI3 Reads the values of

PCST0 (0xFC22) Read Interrupt and Write

Interrupts 2-33

Interrupt status bits.

MPIO3_[1:0]pins, whichalso
serve as external interrupt
lines to microcontroller core.

Interrupt status bits.

2.11 JTAG Boundary Scan Testing

The SYM53C040 includes support for JTAG boundary scan testing in
accordance with the IEEE 1149.1 specification. The device can accept
all required boundary scan instructions, as well as the optional CLAMP,
HIGH-Z, and IDCODE instructions.

The SYM53C040 uses an 8-bit instruction register to support all
boundary scan instructions. The data registers included in the device are
the Boundary Data register, the IDCODE register, and the Bypass
register. The device can handle a 10 MHz TCK frequency for TDO and
TDI.

2-34 Functional Description

Chapter 3
Signal Descriptions

This chapter presents the SYM53C040 pin configurations and signal
definitions using tables and illustrations. Figure 3.1 through Figure 3.2
are the pin diagrams for all versions of the SYM53C040, Table 3.1
through Table 3.4 show a alphabetical listing and numerical listing for
each version, and Figure 3.3 is the functional signal grouping. The pin
definitions are presented in Table 3.5 through Table 3.9, organized in
functional groups.

• Section 3.1, “Safety Mode Signals”

• Section 3.2, “SFF-8067 Mode”

A slash (/) at the end of a signal name indicates that the active state
occurs when the signal is at a low voltage. When the slash is absent, the
signal is active at a high voltage.

Symbios SYM53C040 Enclosure Services Processor Technical Manual 3-1

Figure 3.1 SYM53C040, 160-Pin QFP Option

RD/

VDD_CORE

WR/

CLK_SEL

VSS_CORE

TESTIN

VDD_IO

RESET/

CLK

TRST/

SDA1

SCL1

VDD_SCSI

SD0+

SD0−SD1+

SD1−VSS_SCSI

SD2+

SD2−SD3+

SD3−VDD_SCSI

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

VSS_IO

A10
A11
A12
A13
A14
A15

PSEN/

ALE

VDD_IO

AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

VSS_IO

SCL0
SDA0

VDD_IO
MPIO0_0
MPIO0_1
MPIO0_2
MPIO0_3
MPIO0_4
MPIO0_5
MPIO0_6
MPIO0_7

VSS_IO
MPLED0_0
MPLED0_1
MPLED0_2
MPLED0_3

VSS_IO
MPLED0_4
MPLED0_5

1

A8
A9

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

414243444546474849505152535455565758596061626364656667686970717273747576777879

SYM53C040

160-Pin QFP

139

Top View

−

SD4+

SD4−SD5+

SD5−VSS_SCSI

SD6+

SD6−SD7+

SD7−VDD_SCSI

SDP0+

SDP0−SATN+

SATN−VSS_SCSI

RBIAS+

RBIAS

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

1
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

80

VSS_SCSI

20

SBSY+
SBSY−
SACK+
SACK−
VDD_SCSI
SRST+
SRST−
SMSG+
SMSG−
VSS_SCSI
SSEL+
SSEL−
SCD+
SCD−
VDD_SCSI
SREQ+
SREQ−
SIO+
SIO−
VSS_SCSI

99

SHID0+

98

SHID0−

97

SHID1+

96

SHID1−

95

SHID2+

94

SHID2−

93

DIFFSENS

92

TDI

91

TCK

90

TMS

89

TDO

88

VDD_IO

87

MPIO3_3

86

MPIO3_2

85

MPIO3_1

84

MPIO3_0

83

VSS_IO

82

MPLED2_7

81

MPLED2_6

MPLED0_6

MPLED0_7

VDD_IO

MPIO1_0

MPIO1_1

MPIO1_2

MPIO1_3

MPIO1_4

MPIO1_5

VSS_IO

MPIO1_6

MPIO1_7

MPLED1_0

MPLED1_1

3-2 Signal Descriptions

MPLED1_2

MPLED1_3

VSS_IO

MPLED1_4

MPLED1_5

MPLED1_6

MPLED1_7

VSS_IO

MPIO2_0

MPIO2_1

MPIO2_2

VSS_CORE

MPIO2_3

VDD_CORE

MPIO2_4

MPIO2_5

VDD_IO

MPIO2_6

MPIO2_7

MPLED2_0

MPLED2_1

VSS_IO

MPLED2_2

MPLED2_3

MPLED2_4

MPLED2_5

Table 3.1 SYM53C040 160-Pin QFP Pin List (Alphabetically by Signal Name)

Signal PinSignal Pin

SRST− 113
SSEL+ 109
SSEL− 108
TCK 91
TDI 92
TDO 89
TESTIN 155
TMS 90
TRST/ 151
VDD_CORE 68
VDD_CORE 159
VDD_IO 12
VDD_IO 24
VDD_IO 43
VDD_IO 71
VDD_IO 88
VDD_IO 154
VDD_SCSI 105
VDD_SCSI 115
VDD_SCSI 128
VDD_SCSI 138
VDD_SCSI 148
VSS_CORE 65
VSS_CORE 156
VSS_IO 1
VSS_IO 21
VSS_IO 33
VSS_IO 38
VSS_IO 50
VSS_IO 57
VSS_IO 62
VSS_IO 76
VSS_IO 83
VSS_SCSI 100
VSS_SCSI 110
VSS_SCSI 120
VSS_SCSI 123
VSS_SCSI 133
VSS_SCSI 143
WR/ 158

A10 4
A11 5
A12 6
A13 7
A14 8
A15 9
A8 2
A9 3
AD0 20
AD1 19
AD2 18
AD3 17
AD4 16
AD5 15
AD6 14
AD7 13
ALE 11
CLK 152
CLK_SEL 157
DIFFSENS 93
MPIO0_0 25
MPIO0_1 26
MPIO0_2 27
MPIO0_3 28
MPIO0_4 29
MPIO0_5 30
MPIO0_6 31
MPIO0_7 32
MPIO1_0 44
MPIO1_1 45
MPIO1_2 46
MPIO1_3 47
MPIO1_4 48
MPIO1_5 49
MPIO1_6 51
MPIO1_7 52
MPIO2_0 63
MPIO2_1 64
MPIO2_2 66
MPIO2_3 67

Signal Pin Signal Pin

MPIO2_4 69
MPIO2_5 70
MPIO2_6 72
MPIO2_7 73
MPIO3_0 84
MPIO3_1 85
MPIO3_2 86
MPIO3_3 87
MPLED0_0 34
MPLED0_1 35
MPLED0_2 36
MPLED0_3 37
MPLED0_4 39
MPLED0_5 40
MPLED0_6 41
MPLED0_7 42
MPLED1_0 53
MPLED1_1 54
MPLED1_2 55
MPLED1_3 56
MPLED1_4 58
MPLED1_5 59
MPLED1_6 60
MPLED1_7 61
MPLED2_0 74
MPLED2_1 75
MPLED2_2 77
MPLED2_3 78
MPLED2_4 79
MPLED2_5 80
MPLED2_6 81
MPLED2_7 82
PSEN/ 10
RBIAS+ 122
RBIAS− 121
RD/ 160
RESET/ 153
SACK+ 117
SACK− 116
SATN+ 125

SATN− 124
SBSY+ 119
SBSY− 118
SCD+ 107
SCD− 106
SCL0 22
SCL1 149
SD0+ 147
SD0− 146
SD1+ 145
SD1− 144
SD2+ 142
SD2− 141
SD3+ 140
SD3− 139
SD4+ 137
SD4− 136
SD5+ 135
SD5− 134
SD6+ 132
SD6− 131
SD7+ 130
SD7− 129
SDA0 23
SDA1 150
SDP0+ 127
SDP0− 126
SHID0+ 99
SHID0− 98
SHID1+ 97
SHID1− 96
SHID2+ 95
SHID2− 94
SIO+ 102
SIO− 101
SMSG+ 112
SMSG− 111
SREQ+ 104
SREQ− 103
SRST+ 114

3-3

Table 3.2 SYM53C040 160-Pin QFP Pin List (Numerically by Pin Number)

Pin Signal Pin Signal

1 VSS_IO
2A8
3A9
4A10
5A11
6A12
7A13
8A14
9A15
10 PSEN/
11 ALE
12 VDD_IO
13 AD7
14 AD6
15 AD5
16 AD4
17 AD3
18 AD2
19 AD1
20 AD0
21 VSS_IO
22 SCL0
23 SDA0
24 VDD_IO
25 MPIO0_0
26 MPIO0_1
27 MPIO0_2
28 MPIO0_3
29 MPIO0_4
30 MPIO0_5
31 MPIO0_6
32 MPIO0_7
33 VSS_IO
34 MPLED0_0
35 MPLED0_1
36 MPLED0_2
37 MPLED0_3
38 VSS_IO
39 MPLED0_4
40 MPLED0_5

41 MPLED0_6
42 MPLED0_7
43 VDD_IO
44 MPIO1_0
45 MPIO1_1
46 MPIO1_2
47 MPIO1_3
48 MPIO1_4
49 MPIO1_5
50 VSS_IO
51 MPIO1_6
52 MPIO1_7
53 MPLED1_0
54 MPLED1_1
55 MPLED1_2
56 MPLED1_3
57 VSS_IO
58 MPLED1_4
59 MPLED1_5
60 MPLED1_6
61 MPLED1_7
62 VSS_IO
63 MPIO2_0
64 MPIO2_1
65 VSS_CORE
66 MPIO2_2
67 MPIO2_3
68 VDD_CORE
69 MPIO2_4
70 MPIO2_5
71 VDD_IO
72 MPIO2_6
73 MPIO2_7
74 MPLED2_0
75 MPLED2_1
76 VSS_IO
77 MPLED2_2
78 MPLED2_3
79 MPLED2_4
80 MPLED2_5

81 MPLED2_6
82 MPLED2_7
83 VSS_IO
84 MPIO3_0
85 MPIO3_1
86 MPIO3_2
87 MPIO3_3
88 VDD_IO
89 TDO
90 TMS
91 TCK
92 TDI
93 DIFFSENS
94 SHID2−
95 SHID2+
96 SHID1−
97 SHID1+
98 SHID0−
99 SHID0+
100 VSS_SCSI
101 SIO−
102 SIO+
103 SREQ−
104 SREQ+
105 VDD_SCSI
106 SCD−
107 SCD+
108 SSEL−
109 SSEL+
110 VSS_SCSI
111 SMSG−
112 SMSG+
113 SRST−
114 SRST+
115 VDD_SCSI
116 SACK−
117 SACK+
118 SBSY−
119 SBSY+
120 VSS_SCSI

Pin SignalPin Signal

121 RBIAS−
122 RBIAS+
123 VSS_SCSI
124 SATN−
125 SATN+
126 SDP0−
127 SDP0+
128 VDD_SCSI
129 SD7−
130 SD7+
131 SD6−
132 SD6+
133 VSS_SCSI
134 SD5−
135 SD5+
136 SD4−
137 SD4+
138 VDD_SCSI
139 SD3−
140 SD3+
141 SD2−
142 SD2+
143 VSS_SCSI
144 SD1−
145 SD1+
146 SD0−
147 SD0+
148 VDD_SCSI
149 SCL1
150 SDA1
151 TRST/
152 CLK
15 3RESET/
154 VDD_IO
155 TESTIN
156 VSS_CORE
157 CLK_SEL
158 WR/
159 VDD_CORE
160 RD/

3-4 Signal Descriptions

3-5

Figure 3.2 SYM53C040 169-Ball BGA Top View

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13

NC RD/ VSS_CORE RESET/ S CL1 SD1+ SD3+ SD4− SD6− VDD_SCSI SATN− NC NC

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13

NC NC WR/ VDD_IO SDA1 SD1− SD3− SD5+ SD7+ SDP0− NC NC NC

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13

A10 NC A8 CLK_SEL TRST/ SD0− VDD_SCSI SD5− SD7− SATN+ RBIAS− SBSY− SACK−

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13

A14 A12 A11 VDD_CORE TESTIN SD0+ SD2− SD6+ SDP0+ SBSY+ SACK+ SRST+ SRST−

E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13

−

SMSG−

VDD_SCSI

SHID1+

DIFFSENS

SSEL+

SREQ

SHID0−

SHID2−

ALE PSEN/ A15 A13 A9 VDD_SCSI SD2+ SD4+ RBIAS+ VDD_SCSI

F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13

AD5 AD6 AD7 VDD_IO AD4 CLK VSS_IO SMSG+ SCD+

G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13

AD1 AD2 AD3 AD0 SCL0 VSS_IO VSS_IO VSS_IO SIO+

H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13

VDD_IO SDA0 MPIO0_0 MPIO0_1 MPIO0_2 MPIO0_6 VSS_IO MPIO2_6

J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13

SHID1

SCD

SIO−

−

TDI

MPIO0_3 MPIO0_4 MPIO0_5 MPLED0_1 MPLED0_7 MPLED1_3 MPIO2_0 VDD_CORE MPLED2_7 MPIO3_3 TDO TMS TCK

K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13

MPIO0_7 MPLED0_0 MPLED0_3 MPLED0_5 MPIO1_2 MPIO1_7 MPLED1_7 MPIO2_3 MPLED2_1 MPLED2_5 MPIO3_1 MPIO3_2 VDD_IO

L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13

MPLED0_2 MPLED0_4 MPLED0_6 MPIO1_0 MPIO1_4 MPLED1_0 MPLED1_4 MPIO2_2 VDD_IO MPLED2_3 MPLED2_6 NC MPIO3_0

M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13

NC NC NC MPIO1_1 MPIO1_5 MPLED1_1 MPLED1_5 MPIO2_1 MPIO2_5 MPLED2_0 MPLED2_4 NC NC

N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13

NC NC VDD_IO MPIO1_3 MPIO1_6 MPLED1_2 MPLED1_6 VSS_CORE MPIO2_4 MPIO2_7 MPLED2_2 N C NC

SSEL−

−

SREQ+

SHID0+

SHID2+

Table 3.3 169-Ball BGA List (Alphabetically by Ball Grid Location)

Ball # Signal

A1 NC
A2 RD/
A3 VSS_CORE
A4 RESET/
A5 SCL1
A6 SD1+
A7 SD3+
A8 SD4−
A9 SD6−
A10 VDD_SCSI
A11 SATN−
A12 NC
A13 NC
B1 NC
B2 NC
B3 WR/
B4 VDD_IO
B5 SDA1
B6 SD1−
B7 SD3−
B8 SD5+
B9 SD7+
B10 SDP0−
B11 NC
B12 NC
B13 NC
C1 A10
C2 NC
C3 A8
C4 CLK_SEL
C5 TRST/
C6 SD0−
C7 VDD_SCSI
C8 SD5−

Ball # Signal Ball # Signal Ball # Signal

C9 SD7−
C10 SATN+
C11 RBIAS−
C12 SBSY−
C13 SACK−
D1 A14
D2 A12
D3 A11
D4 VDD_CORE
D5 TESTIN
D6 SD0+
D7 SD2−
D8 SD6+
D9 SDP0+
D10 SBSY+
D11 SACK+
D12 SRST+
D13 SRST−
E1 ALE
E2 PSEN/
E3 A15
E4 A13
E5 A9
E6 VDD_SCSI
E7 SD2+
E8 SD4+
E9 RBIAS+
E10 VDD_SCSI
E11 SMSG−
E12 SSEL+
E13 SSEL−
F1 AD5
F2 AD6
F3 AD7

F4 VDD_IO
F5 AD4
F6 CLK
F7 VSS_IO
F8 SMSG+
F9 SCD+
F10 SCD­F11 VDD_SCSI
F12 SREQ−
F13 SREQ+
G1 AD1
G2 AD2
G3 AD3
G4 AD0
G5 SCL0
G6 VSS_IO
G7 VSS_IO
G8 VSS_IO
G9 SIO+
G10 SIO−
G11 SHID1+
G12 SHID0−
G13 SHID0+
H1 VDD_IO
H2 SDA0
H3 MPIO0_0
H4 MPIO0_1
H5 MPIO0_2
H6 MPIO0_6
H7 VSS_IO
H8 MPIO2_6
H9 SHID1−
H10 TDI
H11 DIFFSENS

H12 SHID2−
H13 SHID2+
J1 MPIO0_3
J2 MPIO0_4
J3 MPIO0_5
J4 MPLED0_1
J5 MPLED0_7
J6 MPLED1_3
J7 MPIO2_0
J8 VDD_CORE
J9 MPLED2_7
J10 MPIO3_3
J11 TDO
J12 TMS
J13 TCK
K1 MPIO0_7
K2 MPLED0_0
K3 MPLED0_3
K4 MPLED0_5
K5 MPIO1_2
K6 MPIO1_7
K7 MPLED1_7
K8 MPIO2_3
K9 MPLED2_1
K10 MPLED2_5
K11 MPIO3_1
K12 MPIO3_2
K13 VDD_IO
L1 MPLED0_2
L2 MPLED0_4
L3 MPLED0_6
L4 MPIO1_0
L5 MPIO1_4
L6 MPLED1_0

Ball # Signal

L7 MPLED1_4
L8 MPIO2_2
L9 VDD_IO
L10 MPLED2_3
L11 MPLED2_6
L12 NC
L13 MPIO3_0
M1 NC
M2 NC
M3 NC
M4 MPIO1_1
M5 MPIO1_5
M6 MPLED1_1
M7 MPLED1_5
M8 MPIO2_1
M9 MPIO2_5
M10 MPLED2_0
M11 MPLED2_4
M12 NC
M13 NC
N1 NC
N2 NC
N3 VDD_IO
N4 MPIO1_3
N5 MPIO1_6
N6 MPLED1_2
N7 MPLED1_6
N8 VSS_CORE
N9 MPIO2_4
N10 MPIO2_7
N11 MPLED2_2
N12 NC
N13 NC

1. NC pins are not connected.

3-6 Signal Descriptions

Table 3.4 169-Ball BGA List (Alphabetically by Signal Name)

Signal Ball #

A8 C3
A9 E5
A10 C1
A11 D3
A12 D2
A13 E4
A14 D1
A15 E3
AD0 G4
AD1 G1
AD2 G2
AD3 G3
AD4 F5
AD5 F1
AD6 F2
AD7 F3
ALE E1
CLK F6
CLK_SEL C4
DIFFSENS H11
MPIO0_0 H3
MPIO0_1 H4
MPIO0_2 H5
MPIO0_3 J1
MPIO0_4 J2
MPIO0_5 J3
MPIO0_6 H6
MPIO0_7 K1
MPIO1_0 L4
MPIO1_1 M4
MPIO1_2 K5
MPIO1_3 N4
MPIO1_4 L5
MPIO1_5 M5

Signal Ball # Signal Ball # Signal Ball #

MPIO1_6 N5
MPIO1_7 K6
MPIO2_0 J7
MPIO2_1 M8
MPIO2_2 L8
MPIO2_3 K8
MPIO2_4 N9
MPIO2_5 M9
MPIO2_6 H8
MPIO2_7 N10
MPIO3_0 L13
MPIO3_1 K11
MPIO3_2 K12
MPIO3_3 J10
MPLED0_0 K2
MPLED0_1 J4
MPLED0_2 L1
MPLED0_3 K3
MPLED0_4 L2
MPLED0_5 K4
MPLED0_6 L3
MPLED0_7 J5
MPLED1_0 L6
MPLED1_1 M6
MPLED1_2 N6
MPLED1_3 J6
MPLED1_4 L7
MPLED1_5 M7
MPLED1_6 N7
MPLED1_7 K7
MPLED2_0 M10
MPLED2_1 K9
MPLED2_2 N11
MPLED2_3 L10

MPLED2_4 M11
MPLED2_5 K10
MPLED2_6 L11
MPLED2_7 J9
NC A1
NC A12
NC A13
NC B1
NC B2
NC B11
NC B12
NC B13
NC C2
NC L12
NC M1
NC M2
NC M3
NC M12
NC M13
NC N1
NC N2
NC N12
NC N13
PSEN/ E2
RBIAS− C11
RBIAS+ E9
RD/ A2
RESET/ A4
SACK− C13
SACK+ D11
SATN− A11
SATN+ C10
SBSY− C12
SBSY+ D10

SCD− F10
SCD+ F9
SCL0 G5
SCL1 A5
SD0− C6
SD0+ D6
SD1− B6
SD1+ A6
SD2− D7
SD2+ E7
SD3− B7
SD3+ A7
SD4− A8
SD4+ E8
SD5− C8
SD5+ B8
SD6− A9
SD6+ D8
SD7− C9
SD7+ B9
SDA0 H2
SDA1 B5
SDP0− B10
SDP0+ D9
SHID0− G12
SHID0+ G13
SHID1− H9
SHID1+ G11
SHID2− H12
SHID2+ H13
SIO− G10
SIO+ G9
SMSG− E11
SMSG+ F8

Signal Ball #

SREQ− F12
SREQ+ F13
SRST− D13
SRST+ D12
SSEL− E13
SSEL+ E12
TCK J13
TDI H10
TDO J11
TESTIN D5
TMS J12
TRST/ C5
VDD_CORE D4
VDD_CORE J8
VDD_IO B4
VDD_IO F4
VDD_IO H1
VDD_IO K13
VDD_IO L9
VDD_IO N3
VDD_SCSI A10
VDD_SCSI C7
VDD_SCSI E6
VDD_SCSI E10
VDD_SCSI F11
VSS_CORE A3
VSS_CORE N8
VSS_IO F7
VSS_IO G6
VSS_IO G7
VSS_IO G8
VSS_IO H7
WR/ B3

1. NC pins are not connected.

3-7

Figure 3.3 SYM53C040 Functional Pin Description

LVD/SE

SCSI

Interface

SSEL+
SSEL−
SBSY+
SBSY−
SRST+
SRST

−

SREQ+

−

SREQ
SACK+
SACK−
SMSG+
SMSG−
SCD+
SCD−
SIO+

−

SIO
SATN+
SATN

−

SDP0+
SDP0−
SD[7:0]+
SD[7:0]−
DIFFSENS
SHID[2:0]
SHID[2:0]−

RBIAS+
RBIAS−

+

SYM53C040

160-Pin QFPor

169-Ball BGA

MPIO0[7:0]
MPIO1[7:0]
MPIO2[7:0]
MPIO3[3:0]

MPLED0[7:0]
MPLED1[7:0]
MPLED2[7:0]

SCL0

SDA0

SCL1

SDA1

TCK
TMS

TDI

TDO

TRST/

MPIO Pin
Control

MPLED Pin
Control

TWS Interface
(Primary)

TWS Interface
(Secondary)

JTAG

3-8 Signal Descriptions

AD[7:0]

A[15:8]

ALE/

PSEN/

WR/

RD/

CLK_SEL

CLK

RESET/

Microcontroller
Interface

Clock
Input

3.1 Safety Mode Signals

The Safety Mode Signals section contains tables describing the signals
for the following signal groups: Miscellaneous Signals, SCSI Signals,

JTAG Signals and Power and Ground Signals.

3.1.1 Miscellaneous Signals

Table 3.5 describes the signals for the Miscellaneous Signals group.

Table 3.5 Miscellaneous Signals

Pin

Name

A8

A9
A10
A11
A12
A13
A14
A15

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

Pin

Number

2
3
4
5
6
7
8
9

20
19
18
17
16
15
14
13

BGABall

Number Description Pad Type

C3

E5
C1
D3
D2

E4
D1

E3

G4
G1
G2
G3

F5

F1

F2

F3

High byte of the
microcontroller address bus.
Anexternalpull-upontheA11
pin causes the serial ROM
download to use the 2-wire
serialinterface1.Ifno
external pull-up is used the
download will use the 2-wire
serial interface 0.
A[10:8] are used to select a
chip address for the serial
ROM. For more information on
the possible addresses, see

Table 2.4.

For more information on these
power-up options, see

Chapter 2.

Low byte of the
microcontroller multiplexed
address/data bus.
An external pull-up on AD[1:0]
enables automatic branch
generation.Forinformation on
the branch values, see

Table 2.3.

An external pull-up on AD5
causes the SYM53C040 to
download firmware from a
serial ROM at power on.
For more information on these
power-up options, see

Chapter 2.

4mA,5Vtolerant
TTL bidirectional

4mA,5Vtolerant
TTL bidirectional

Internal

Resistor

100 µA
pull­down

100 µA
pull­down

Safety Mode Signals 3-9

Table 3.5 Miscellaneous Signals (Cont.)

Pin

Name

PSEN/ 10 E2 Active low microcontroller

WR/ 158 B3 Active low microcontroller

RD/ 160 A2 Active low microcontroller

ALE 11 E1 Address latch enable for

SCL0
SCL1

SDA0
SDA1

MPIO0_

[7:0]

Pin

Number

22

149

23

150

32, 31, 30,
29, 28, 27,

26, 25

BGABall

Number Description Pad Type

Program Space Enable
output.

write output.

read output.

microcontroller bus.

G5

A5

H2

B5

K1, H6,

J3, J2,
J1, H5,
H4, H3

Two-Wire Serial Port 0 Clock
Two-Wire Serial Port 1 Clock

Two-Wire Serial Port 0 Data
Two-Wire Serial Port 1 Data

Multipurpose I/O bank 0 4 mA, 5 V tolerant

4mA,5Vtolerant
TTL bidirectional

4mA,5Vtolerant
TTL bidirectional

4mA,5Vtolerant
TTL bidirectional

4mA,5Vtolerant
TTL bidirectional

2mA,5Vtolerant
TTL Schmitt open
drain bidirectional

2mA,5Vtolerant
TTL Schmitt open
drain bidirectional

TTL bidirectional

Internal

Resistor

None

None

None

None

None
(external
pull-up
required)

None
(external
pull-up
required)

25 µA
pull­down

MPIO1_

[7:0]

MPIO2_

[7:0]

3-10 Signal Descriptions

52, 51, 49,
48, 47, 46,

45, 44

73, 72, 70,
69, 67, 66,

64, 63

K6, N5,
M5, L5,
N4, K5,

M4, L4

N10, H8,

M9, N9,

K8, L8,

M8, J7

Multipurpose I/O bank 1 4 mA, 5 V tolerant

Multipurpose I/O bank 2 4 mA, 5 V tolerant

TTL bidirectional

TTL bidirectional

25 µA
pull­down

25 µA
pull­down

Table 3.5 Miscellaneous Signals (Cont.)

Pin

Name

MPIO3_

[3:0]

MPLED

0_

[7:0]

MPLED

1_

[7:0]

MPLED

2_

[7:0]

Pin

Number

87
86
85
84

42, 41, 40,
39, 37, 36,

35, 34

61, 60, 59,
58, 56, 55,

54, 53

82, 81, 80,
79, 78, 77,

75, 74

BGABall

Number Description Pad Type

J10
K12
K11
L13

Multipurpose I/O bank 3
MPIO3_0 = INT0/ to
microcontroller, if 0xFF05 bit 0
is set (active low).

4mA,5Vtolerant
TTL bidirectional

MPIO3_1 = INT1/ to
microcontroller, if 0xFF05 bit 0
is set (active low).
MPIO3_2 = TXD from
microcontroller, if 0xFF05 bit 1
is set.
MPIO3_3 = RXD to
microcontroller, if 0xFF05 bit 1
is set.

J5, L3,
K4, L2,
K3, L1,

J4, K2

K7, N7,
M7, L7,
J6, N6,

M6, L6

J9, L11,

K10,

M11,

L10,N11,

K9, M10

Open drain multipurpose LED
bank 0 outputs. Any unused
LED outputs must be tied to

or resistively pulled H IGH.

V

SS

Open drain multipurpose LED
bank 1 outputs. Any unused
LED outputs must be tied to

HIGH.

V

SS

Open drain multipurpose LED
bank 2 outputs. Any unused
LED outputs must be tied to

or resistively pulled HIGH.

V

SS

16 mA, 5 V tolerant
TTL open drain
bidirectional

16 mA, 5 V tolerant
TTL open drain
bidirectional

16 mA, 5 V tolerant
TTL open drain
bidirectional

Internal

Resistor

25 µA
pull­down

None

None

None

TESTIN 155 D5 This pin should be tied LOW

during normal operation.

CLK_S

EL

157 C4 When this signal is tied HIGH,

the internal clock will be the

5 V tolerant TTL
input

5Vtolerant withTTL

input bidirectional
same as the external. When
LOW,the external frequencyis
divided by 2.

CLK 152 F6 40 MHz system clock input. 5 V tolerantTTL

input

Safety Mode Signals 3-11

None

100 µA
pull-up

None

Table 3.5 Miscellaneous Signals (Cont.)

Pin

Name

RESET/ 153 A4 Activelow chip reset input.

Pin

Number

BGABall

Number Description Pad Type

The SYM53C040 has an
internal power-on reset circuit
which can be relied upon for
initializing the chip. If the
SYM53C040 watchdog timer
is used and it expires, it can
force an internal chip reset
and asser t the RESET/ pin
LOW to reset external devices
(ifbit7inregister0xFF05is
set).

4 mA open drain

output, 5 V tolerant

with TTL input

bidirectional

Internal

Resistor

None

3-12 Signal Descriptions

3.1.2 SCSI Signals

Table 3.6 describes the signals for the SCSI Signals group.

Table 3.6 SCSI Signals

Pin

Name

DIFFSENS 93 H11 SCSI DIFFSENS signal. A low level

SHID2−
SHID2+

SHID1−
SHID1+

Pin

Number

94
95

96
97

BGA Ball

Number Description Pad Type

input enables SCSI SE mode. A mid­range level input enables SCSI LVD
mode. A high level input enables

H12
H13

H9

G11

SFF-8067 Mode. Tie this pin to V
to enable SFF-8067 mode.

SCSI High ID 2. This LVD SCSI pair
maybe connected to any of the SCSI
data signals from data bit 8 through

15. This provides the means for the
SCSI core to respond to selection as
a device with an ID greater than 7.
In SE mode, the SHID2− pin is the
SE signal pin, and the SHID2+ pin
should be connected as a virtual
ground on the SCSI connector.

SCSI High ID 1. This LVD SCSI pair
maybe connected to any of the SCSI
data signals from data bit 8 through

15. This enables the SCSI core to
respond to selection as a device with
an ID greater than 7.
In SE mode, the SHID1− pin is the
SE signal pin, and the SHID1+ pin
should be connected as a virtual
ground on the SCSI connector.

DD

Analog
input

SE or LVD
SCSI I/O

SE or LVD
SCSI I/O

Internal

Resistor

–

None

None

SHID0−
SHID0+

98
99

Safety Mode Signals 3-13

G12
G13

SCSI High ID 0. This LVD SCSI pair
maybe connected to any of the SCSI
data signals from data bit 8 through

15. This enables the SCSI core to
respond to selection as a device with
an ID greater than 7.
In SE mode, the SHID0− pin is the
SE signal pin, and the SHID0+ pin
should be connected as a virtual
ground on the SCSI connector.

SE or LVD
SCSI I/O

None

Table 3.6 SCSI Signals (Cont.)

Pin

Name

SIO−
SIO+

SREQ−
SREQ+

SCD−
SCD+

SSEL−
SSEL+

SMSG−
SMSG+

Pin

Number

101
102

103
104

106
107

108
109

111
112

BGA Ball

Number Description Pad Type

G10

G9

F12
F13

F10

F9

E13
E12

E11

F8

SCSI I/O signal. In SE mode, the
SIO− pin is the SE signal pin, and the
SIO+ pin should be connected as a
virtualgroundontheSCSI
connector.

SCSI REQ signal. In SE mode, the
SREQ− pin is the SE signal pin, and
the SREQ+ pin should be connected
as a virtual ground on the SCSI
connector.

SCSI C/D signal. In SE mode, the
SCD− pin is the SE signal pin, and
the SCD+ pin should be connected
as a virtual ground on the SCSI
connector.

SCSI SEL signal. In SE mode, the
SSEL− pin is the SE signal pin, and
the SSEL+ pin should be connected
as a virtual ground on the SCSI
connector.

SCSI MSG signal. In SE mode, the
SMSG− pin is the SE signal pin, and
the SMSG+ pin should be connected
as a virtual ground on the SCSI
connector.

SE or LVD
SCSI I/O

SE or LVD
SCSI I/O

SE or LVD
SCSI I/O

SE or LVD
SCSI I/O

SE or LVD
SCSI I/O

Internal

Resistor

None

None

None

None

None

SRST−
SRST+

SACK−
SACK+

SBSY−
SBSY+

3-14 Signal Descriptions

113
114

116
117

118
119

D13
D12

C13
D11

C12
D10

SCSI RST signal. In SE mode, the
SRST− pin is the SE signal pin, and
the SRST+ pin should be connected
as a virtual ground on the SCSI
connector.

SCSI ACK signal. In SE mode, the
SACK− pin is the SE signal pin, and
the SACK+ pin should be connected
as a virtual ground on the SCSI
connector.

SCSI BSY signal. In SE mode, the
SBSY− pin is the SE signal pin, and
the SBSY+ pin should be connected
as a virtual ground on the SCSI
connector.

SE or LVD
SCSI I/O

SE or LVD
SCSI I/O

SE or LVD
SCSI I/O

None

None

None

Table 3.6 SCSI Signals (Cont.)

Pin

Name

RBIAS−
RBIAS+

SATN−
SATN+

SDP0−
SDP0+

SD7−,

SD7+,

SD6−,

SD6+,

SD5−,

SD5+,

SD4−,

SD4+,

SD3−,

SD3+,

SD2−,

SD2+,

SD1−,

SD1+,

SD0−,

SD0+

Pin

Number

121
122

124
125

126
127

129,130,
131,132,
134,135,
136,137,
139,140,
141,142,
144,145,

146,147

BGA Ball

Number Description Pad Type

C11

E9

A11
C10

B10

D9

C9, B9,
A9, D8,
C8, B8,
A8, E8,
B7, A7,
D7, E7,
B6, A6,

C6, D6

Bias resistor for LVD operation. See

Figure 2.4 for a suggested

implementation.
SCSI ATN signal. In SE mode, the

SATN− pin is the SE signal pin, and
the SATN+ pin should be connected
as a virtual ground on the SCSI
connector.

SCSI low data byte parity signal. In
SE mode, the SDP0− pin is the SE
signal pin, and the SDP0+ pin should
be connected as a vir tual ground on
the SCSI connector.

SCSI low data byte signals. In SE
mode, the SDx− pin is the SE signal
pin, and the SDx+ pin should be
connected as a virtual ground on the
SCSI connector.

Custom
Input

SE or LVD
SCSI I/O

SE or LVD
SCSI I/O

SE or LVD
SCSI I/O

Internal

Resistor

None

None

None

None

Safety Mode Signals 3-15

3.1.3 JTAG Signals

Table 3.7 describes the signals for the JTAG Signals group.

Table 3.7 JTAG Signals

Pin

Name

TCK 91 J13 Test Clock. The Test Clock pin

TMS 90 J12 Test Mode Select. The Test Mode

TDI 92 H10 Test Data In. The Test Data In pin

TDO 89 J11 Test Data Out. The Test Data Out pin

TRST/ 151 C5 Test Reset. The Test Reset pin

Pin

Number

BGA Ball

Number Description Pad Type

provides clocking for the JTAG test
logic and boundary scan.

Select pin receives a signal to
control the JTAG test operations and
boundary scans.

receives serial input data and
commands for JTAG test operations
and boundary scans.

provides serial output data for JTAG
test operations and boundary scans.

receives a signal to reset the JTAG
TAP controller. It also simulates a
power-onreset for core logic (NOTE:
not JTAG compliant).

5V
tolerant
TTL input

5V
tolerant
TTL input

5V
tolerant
TTL input

4mA
Output

5V
tolerant
TTL input

Internal

Resistor

100 µA
pull-up

100 µA
pull-up

100 µA
pull-up

None

100 µA
pull-up

3-16 Signal Descriptions

3.1.4 Power and Ground Signals

Table 3.8 describes the signals for the Power and Ground Signals group.

Table 3.8 Power and Grounds Signals

Pin

Name

VSS_IO 1, 21, 33,

VDD_IO 12, 24, 43,

Pin

Number

38, 50, 57,

62, 76, 83

71, 88, 154

BGA Ball

Number Description Pad Type

F7, G6,

G7, G8,

VSSsupply for I/O signal pins. Must
be connected to ground.

H7

B4, F4,

H1, K13,

V
be connected to + 3.3 V power supply.

1

supply for I/O signal pins. Must

DD

Internal

Resistor

V

SS

V

DD

–

–

L9, N3

VSS_

SCSI

100, 110,
120, 123,

V

supply for SCSI I/O signal pins.

SS

Must be connected to ground.

V

SS

–

133, 143

VDD_

SCSI

VSS_

CORE

VDD_

CORE

105, 115,
128, 138,

148

A10, C7,
E6, E10,

F11

65, 156 A3, N8 V

68, 159 J8, D4 V

V

supply for SCSI I/O signal pins.

DD

Must be connected to + 3.3 V power
supply.

supply for core logic. Must be

SS

connected to ground.

supply for core logic. Must be

DD

connected to + 3.3 V power supply.

V

DD

V

SS

V

DD

–

–

–

1. For optimal operation, the power pins should be powered up at the same time or in this order:
VDD_CORE, VDD_IO, VDD_SCSI.

Safety Mode Signals 3-17

3.2 SFF-8067 Mode

The SFF-8067 interface is enabled when the DIFFSENS pin is tied to
V

. The SCSI pin functions are reassigned to SFF-8067 port functions

DD

as indicated in Table 3.9.

Table 3.9 Pin Assignments for SFF-8067 Mode

Pin/Ball

Signal Name

D0, SEL_0 147/D6 When PARALLEL_ESI/ is asserted,

D1, SEL_1 146/C6 When PARALLEL_ESI/ is asserted,

D2, SEL_2 145/A6 When PARALLEL_ESI/ is asserted,

D3, SEL_3 144/B6 When PARALLEL_ESI/ is asserted,

No. Description 8067 Port

this signal contains bit 0 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_0
signal,includedfor compatibility with
SFF-8045.

this signal contains bit 1 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_1
signal,includedfor compatibility with
SFF-8045.

this signal contains bit 2 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_2
signal,includedfor compatibility with
SFF-8045.

this signal contains bit 3 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_3
signal,includedfor compatibility with
SFF-8045.

Pad

Configuration

Port 0 4 mA open drain

bidirectional

Port 0 4 mA open drain

bidirectional

Port 0 4 mA open drain

bidirectional

Port 0 4 mA open drain

bidirectional

3-18 Signal Descriptions

Table 3.9 Pin Assignments for SFF-8067 Mode (Cont.)

Signal Name

ENCL_ACK/,
SEL_4

DSK_RD/,
SEL_5

DSK_WR/,
SEL_6

Pin/Ball

No. Description 8067 Port

142/E7 When PARALLEL_ESI/ is asserted,

this is an active low acknowledge
signal sourced by the SYM53C040
back to the Fibre Channel device.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_4
signal,includedfor compatibility with
SFF-8045.

141/D7 When PARALLEL_ESI/ is asserted,

this is an active low control signal
sourced by the drive to the
SYM53C040 to indicate the device
is ready to read data. When
PARALLEL_ESI/ is deasserted, this
signal is the SEL_5 signal, included
for compatibility with SFF-8045.

140/A7 When PARALLEL_ESI/ is asserted,

this is an active low control signal
sourced by the drive to the
SYM53C040 to indicate the device
is ready to write data. When
PARALLEL_ESI/ is deasserted, this
signal is the SEL_6 signal, included
for compatibility with SFF-8045.

Port 0 4 mA open drain

Port 0 4 mA open drain

Port 0 4 mA open drain

Pad

Configuration

bidirectional

bidirectional

bidirectional

PARALLEL_
ESI/

D0, SEL_0 137/E8 When PARALLEL_ESI/ is asserted,

139/B7 Used to select between the SEL_ID

and the bidirectional interface. Pull­up resistors on the interface are 3.3
kΩ minimum. When this pin is
asserted, the drive begins the
discovery process and prepares to
read or write data. When this pin is
deasserted, the drive is presented
with SEL_ID. All SFF-8067
transactions are terminated,
regardless of the state of the
protocol.

this signal contains bit 0 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_0
signal,includedfor compatibility with
SFF-8045.

SFF-8067 Mode 3-19

Port 0 4 mA open drain

bidirectional

Port 1 4 mA open drain

bidirectional

Table 3.9 Pin Assignments for SFF-8067 Mode (Cont.)

Signal Name

D1, SEL_1 136/A8 When PARALLEL_ESI/ is asserted,

D2, SEL_2 135/B8 When PARALLEL_ESI/ is asserted,

D3, SEL_3 134/C8 When PARALLEL_ESI/ is asserted,

ENCL_ACK/,
SEL_4

Pin/Ball

No. Description 8067 Port

this signal contains bit 1 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_1
signal,includedfor compatibility with
SFF-8045.

this signal contains bit 2 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_2
signal,includedfor compatibility with
SFF-8045.

this signal contains bit 3 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_3
signal,includedfor compatibility with
SFF-8045.

132/D8 When PARALLEL_ESI/ is asserted,

this is an active low acknowledge
signal sourced by the SYM53C040
back to the Fibre Channel device.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_4
signal,includedfor compatibility with
SFF-8045.

Pad

Configuration

Port 1 4 mA open drain

bidirectional

Port 1 4 mA open drain

bidirectional

Port 1 4 mA open drain

bidirectional

Port 1 4 mA open drain

bidirectional

DSK_RD/,
SEL_5

3-20 Signal Descriptions

131/A9 When PARALLEL_ESI/ is asserted,

this is an active low control signal
sourced by the drive to the
SYM53C040 to indicate the device
is ready to read data. When
PARALLEL_ESI/ is deasserted, this
signal is the SEL_5 signal, included
for compatibility with SFF-8045.

Port 1 4 mA open drain

bidirectional

Table 3.9 Pin Assignments for SFF-8067 Mode (Cont.)

Signal Name

DSK_WR/,
SEL_6

No. Description 8067 Port

130/B9 When PARALLEL_ESI/ is asserted,

this is an active low control signal
sourced by the drive to the
SYM53C040 to indicate the device
is ready to write data. When
PARALLEL_ESI/ is deasserted, this
signal is the SEL_6 signal, included
for compatibility with SFF-8045.

Pin/Ball

PARALLEL_
ESI/

129/C9 Used to select between the SEL_ID

and the bidirectional interface. Pull­up resistors on the interface are 3.3
kΩζ minimum. When this pin is
asserted, the drive begins the
discovery process and prepares to
read or write data. When this pin is
deasserted, the drive is presented
with SEL_ID. All SFF-8067
transactions are terminated,
regardless of the state of the
protocol.

PA0 127/D9 This pin contains bit 0 of the

physical address of the enclosure.

PA1 126/B10 This pin contains bit 1 of the

physical address of the enclosure.

Pad

Configuration

Port 1 4 mA open drain

bidirectional

Port 1 4 mA open drain

bidirectional

Port 0 Input

Port 0 Input

PA2 125/C10 This pin contains bit 2 of the

physical address of the enclosure.

PA3 124/A11 This pin contains bit 3 of the

physical address of the enclosure.

PA4 119/D10 This pin contains bit 4 of the

physical address of the enclosure.

PA5 118/C12 This pin contains bit 5 of the

physical address of the enclosure.

PA6 117/D11 This pin contains bit 6 of the

physical address of the enclosure.
tied to V
tied to V
tied to V

DD

DD

DD

116/C13 – N/A Input
114/D12 – N/A Input
113/D3 – N/A Input

SFF-8067 Mode 3-21

Port 0 Input

Port 0 Input

Port 0 Input

Port 0 Input

Port 0 Input

Table 3.9 Pin Assignments for SFF-8067 Mode (Cont.)

Signal Name

No. Description 8067 Port

PA0 112/F8 This pin contains bit 0 of the

physical address of the enclosure.
PA1 111/E11 This pin contains bit 1 of the

physical address of the enclosure.
PA2 109/E12 This pin contains bit 2 of the

physical address of the enclosure.
PA3 108/E13 This pin contains bit 3 of the

physical address of the enclosure.
PA4 107/F9 This pin contains bit 4 of the

physical address of the enclosure.
PA5 106/F10 This pin contains bit 5 of the

physical address of the enclosure.
PA6 104/F13 This pin contains bit 6 of the

physical address of the enclosure.

Pin/Ball

Tied to V
Tied to V
Tied to V
Tied to V
Tied to V
Tied to V
Tied to V
Tied to V
Tied to V

DD

DD

DD

DD

DD

DD

DD

DD

DD

103/F12 – N/A Input
102/G9 – N/A Input
101/G10 – N/A Input
99/G13 – N/A Input
98/G12 – N/A Input
97/G11 – N/A Input
96/H9 – N/A Input
95/H13 – N/A Input
94/H12 – N/A Input

Pad

Configuration

Port 1 Input

Port 1 Input

Port 1 Input

Port 1 Input

Port 1 Input

Port 1 Input

Port 1 Input

3-22 Signal Descriptions

Chapter 4
SCSI and DMA
Registers

This chapter contains descriptions of the SYM53C040 SCSI and DMA
registers. The SFF-8067 registers, Two-Wire Serial registers,
Miscellaneous registers, and System registers are described in

Chapter 5 through Chapter 8. The term “set” is used to refer to bits that

are programmed to a binary one, while the terms “reset” or “clear” are
used to refer to bits that are programmed to binary zero. Any bits marked
as reserved should always be written to zero; mask all information read
from them. Reserved bit functions may change at any time. Unless
otherwise indicated, all bits in registers are activehigh; that is, the feature
is enabled by setting the bit. The bottom row of every register diagram
shows the default bit values, which are enabled after the chip is powered
on or reset.

Figure 4.1 summarizes the entire SYM53C040 register set.

Figure 4.1 Register Set Overview

0xFC00
0xFC1F

0xFC20
0xFCFF

0xFD00
0xFDFF

0xFE00

0xFEFF

0xFF00

0xFFFF

Symbios SYM53C040 Enclosure Services Processor Technical Manual 4-1

SCSI Core and DMA Registers

SFF-8067 Registers

Two-Wire Serial Interface R egisters

Miscellaneous Registers

System Registers

Table 4.1, the register map, summarizes the SCSI and DMA registers in

graphical form.

Table 4.1 SCSI and DMA Registers

31 16 15 0 Address

Current SCSI Data (CSD) (Read) Output Data (ODR) (Write) 0xFC00

Initiator Command (ICR) 0xFC01

Mode (MR) 0xFC02

Target Command (TC) 0xFC03

Current SCSI Bus Status (CSBS) (Read) Select Enable (SER) (Write) 0xFC04

Bus and Status (BSR) (Read) DMA Send (DSR) (Write) 0xFC05

Start DMA Target Receive (S DTR) 0xFC06

Reset Parity/Interrupt (RPI) (Read) Start DMA Initiator Receive (SDIR) (Write) 0xFC07

Current SCSI Data High (CSDHI) 0xFC08

Reserved 0xFC09–0xFC0B

Select Enable High (SENHI) 0xFC0C

Reserved 0xF C 0D–0xFC0F

DMA Status (DS) 0xFC10

DMA Transfer Length (DTL) 0xFC11

DMA Source/Destination Low (DSDL) 0xFC12

DMA Source/Destination High (DSDH) 0xFC13

DMA Interrupt (DMAI) 0xFC14

Reserved 0xFC15–0xFC1F

4-2 SCSI and DMA Registers

Register: 0xFC00

Current SCSI Data (CSD)
Read Only

7 1

DB[7:0]
Default:

xxxxxxx

DB[7:0] Current SCSI Data [7:0]

The Current SCSI Data register is a read only register
that allows the microcontroller to read the active SCSI
data bus. Whenever a 1 is read in one of these bits, the
corresponding data signal is asserted on the SCSI bus.
If parity checking is enabled, the SCSI bus parity is
checked at the beginning of the read cycle. This register
is used during arbitration to check for higher priority
arbitrating devices. Parity is not guaranteed valid during
arbitration.

Register: 0xFC00

Output Data (ODR)
Write Only

7 1

DB[7:0]
Default:

xxxxxxx

DB[7:0] SCSI Output Data [7:0]

The Output Data register is a write only register that is
used to send data to the SCSI bus. This register is also
used to assert the proper ID bits on the SCSI bus during
the arbitration and selection phases. Writing a 1 to one
of these bits causes the corresponding data signal to be
asserted on the SCSI bus. This register is only asserted
on the SCSI bus when the ADB bit (0xFC01, bit 0) is set.

4-3

Register: 0xFC01

Initiator Command (ICR)
Read/Write

76543210

ARST AIP LA AACK ABSY ASEL AATN ADB

Defaults:

00000000

ARST Assert SRST 7

Whenever a 1 is written to this bit, the SRST signal is
asserted on the SCSI bus. The SRST signal will remain
asserted until this bit is reset or until an external chip
reset occurs. After this bit is set, the IRQ output goes
active and all internal logic and control registers are reset
(except for the interrupt latch and the Assert SRST bit).
Writing a 0 to this bit deasserts the SRST signal. Reading
this register bit simply reflects the status of this bit.

AIP Arbitration In Progress (read only) 6

This bit is used to determine if arbitration is in progress.
For this bit to be active, the ARB bit (Mode Register
0xFC02, bit 0) must hav e been set previously. It indicates
that a bus free condition has been detected and that the
chip has asserted BSY/ and the contents of the Output

Data (ODR) register (0xFC00) onto the SCSI bus. The

AIP bit will remain active until the Arbitrate bit is reset.

LA Lost Arbitration 5

When active, this read only bit indicates that the SCSI
core has detected a bus free condition, arbitrated for use
of the bus by asserting BSY/ and its ID on the data bus,
and lost arbitration due to SEL/ being asserted by
another bus device. For this bit to be active, the ARB bit
(Mode register 0xFC02, bit 0) must be active.

AACK Assert ACK/ 4

This bit is used by the bus initiator to assert the ACK/ pin
on the SCSI bus. In order to assert ACK/, the Target
Mode bit (Mode register 0xFC02, bit 6) must be false.
Writing a zero to this bit resets ACK/ on the SCSI bus.
Reading this register bit simply reflects the status of this
bit.

4-4 SCSI and DMA Registers

ABSY Assert BSY/ 3

Writinga1intothisbitassertstheBSY/pinontothe
SCSI bus. Conversely, a 0 resets the BSY/ signal.
Asserting BSY/ indicates a successful selection or
reselection, and resetting this bit creates a bus
disconnect condition. Reading this bit reflects the status
of this bit without changing the value.

ASEL Assert SEL/ 2

Writing a 1 into this bit asserts the SEL/ pin onto the
SCSI bus. SEL/ is normally asserted after arbitration has
been successfully completed. SEL/ may be deasserted
by resetting this bit to a zero. A read of this register bit
simply reflects the status of this bit.

AATN Assert ATN/ 1

The ATN/ pin may be asserted on the SCSI bus by
setting this bit to a 1 if the Target Mode bit (Mode register
0xFC02, bit 6) is false. ATN/ is normally asserted by the
initiator to request a Message Out bus phase. Note that
since Assert SEL/ and Assert ATN/ are in the same
register, a select with ATN/ may be implemented with one
MPU write. ATN/ may be deasserted by resetting this bit
to a 0. A read of this register bit simply reflects the status
of this bit.

ADB Assert Data Bus 0

When set, the Assert Data Bus bit allows the contents of
the Output Data (ODR) register to be enabled as chip
outputs on the signals DB0/–DB7/. Parity is also
generated and asserted on DBP/. Resetting this bit
disables the output data bus.

When the SYM53C040 is connected as an Initiator, the
outputs are only enabled if the Target Mode bit (Mode
register 0xFC02, bit 6) is false, the received SCSI I/O
signal is false, and the phase signals (C/D, I/O and MSG)
match the contents of the Assert C_D/, Assert I_O/, and
Assert MSG/ in the Target Command (TC) register
(0xFC03).

This bit should also be set during DMA send operations.

4-5

Register: 0xFC02

Mode (MR)
Read/Write

76543210

AS_LVD TGTM EPC EPI

Defaults:

0000

AS_LVD Arbitration/Selection LVD 7

This bit must be set to perform arbitration, selection, and
reselection, and must be cleared upon successful
completion of selection or reselection prior to asserting
the data bus for any information transfer phases. When
set, this bit causes the SCSI data bus to operate in open
drain mode, which is a requirement of LVD SCSI as
defined in the SPI-2 draft standard. Operation of this bit
does not effect SCSI SE mode.

TGTM Target Mode 6

The Target Mode bit allows the SCSI core to operate as
either a SCSI bus initiator (bit reset to 0) or as a SCSI
bus target device (bit set to 1). In order for the signals
ATN/ and ACK/ to be asserted on the SCSI bus, the
Target Mode bit must be reset (0). In order for the signals
C_D/, I_O/, MSG/ and REQ/ to be asserted on the SCSI
bus, the Target Mode bit must be set (1).

RMBDMARB

0000

EPC EnableParityChecking 5

The Enable Parity Checking bit determines whether parity
errors will be ignored or saved in the parity error latch. If
this bit is reset (0), parity will be ignored. Conversely, if
this bit is set (1), parity errors will be saved.

EPI Enable Parity Interrupt 4

The Enable Parity Interrupt bit, when set to a 1, causes
an interrupt to occur if a parity error is detected. A parity
interrupt will only be generated if the Enable Parity
Checking bit (bit 5) is also enabled.

R Reserved 3

This bit must be cleared to 0.

4-6 SCSI and DMA Registers

MB Monitor Busy 2

The Monitor Busy bit, when set to a 1, causes an
interrupt to be generated for an unexpected loss of BSY/.
When the interrupt is generated due to loss of BSY/, the
lower 6 bits of the Initiator Command (ICR) register
(0xFC01) are reset and all signals are removed from the
SCSI bus.

DM DMA Mode 1

The DMA Mode bit is used to enable a DMA transfer and
must be set to 1 prior to writing SCSI registers 0xFC05
through 0xFC07 to start DMA transfers. T he Target Mode
bit (Mode register 0xFC02, bit 6) must be consistent with
writes to registers 0xFC06 and 0xFC07 (i.e., set to 1 for
a write to register 0xFC06 and reset for a write to register
0xFC07). The Assert Data Bus bit (register 0xFC01, bit

0) must be set to 1 for all DMA send operations. In the
DMA mode, REQ/ and ACK/ are automatically controlled.

The DMA Mode bit is not reset at the end of a DMA
transfer; DMA mode must be turned off by writing a 0 into
this bit location. However, care must be taken not to write
to any SCSI register during a DMA byte transfer.

Note:

The BSY/ signal must be active in order to set the DMA
Mode bit.

ARB Arbitrate 0

The Arbitrate bit is set to 1 to start the arbitration process.
Prior to setting this bit, the Output Data (ODR) register
should contain the proper SCSI device ID value. Only one
data bit should be active for SCSI bus arbitration. The
SCSI core will wait for a bus free condition for entering
the arbitration phase. The results of the arbitration phase
may be determined by reading the status bits LA and AIP
(ICR register 0xFC01, bits 5 and 6 respectively). Write a
0 to this bit after completion of the arbitration phase.

4-7

Register: 0xFC03

Target Command (TC)
Read/Write

76 43210

LBS

0

0 0 00000

When connected as a target device, the Target Command register allows
the microcontroller to control the SCSI bus information transfer phase
and/or to assert REQ/ simply by writing this register. The Target Mode
bit (register 0xFC02, bit 6) must be set (1) for bus assertion to occur.
When connected as an initiator with DMA Mode true, if the phase lines
(I_O/, C_D/ and MSG/) do not match the phase bits in this register, a
phase mismatch interrupt is generated when REQ/ goes active. In order
to send data as an initiator, the Assert I_O/, Assert C_D/ and Assert
MSG/ bits must match the corresponding bits in the Current SCSI Bus

Status (CSBS) register (0xFC04). The Assert REQ/ b it (bit 3) has no

meaning when the SYM53C040 is operating as an initiator.

LBS Last Byte Sent 7

RAREQAMSGACDAIO

Defaults:

In initiator mode, the SCSI core uses this bit to determine
whenthelastbyteofaDMAtransferissenttotheSCSI
bus. This flag is necessary since the End of DMA bit in
the Bus and Status (BSR) register only reflects when the
last byte was received from the DMA function.

R Reserved [6:4]
AREQ Assert REQ/ 3
AMSG Assert MSG/ 2
ACD Assert C_D/ 1
AIO Assert I_O/ 0

These bits, when read together, give the current SCSI
bus phase. Table 4.2 describes the SCSI bus phases that
correspond to all possible values of these bits.

4-8 SCSI and DMA Registers

Table 4.2 SCSI Phase Bit Values

Bus Phase Assert MSG/ Assert CD/ Assert IO/

DataOut 000
Undefined 1 0 0
Command 0 1 0
MessageOut110
DataIn 001
Undefined 1 0 1
Status 011
MessageIn 111

Register: 0xFC04

Current SCSI Bus Status (CSBS)
Read Only

76543210

RST BSY REQ MSG C_D I_O SEL DBP

Defaults:

xxxxxxxx

The Current SCSI Bus Status register is a read only register that
monitors seven SCSI bus control signals plus the data bus parity bit. For
example, an initiator device can use this register to determine the current
bus phase and to poll REQ/ for pending data transfers. The SCSI bus
status information in this register may also help determine why a
particular interrupt occurred.

RST SCSI Reset 7
BSY Busy 6
REQ Request 5
MSG Message 4
C_D Command/Data 3
I_O Input/Output 2

4-9

SEL Select 1
DBP Data Bus Parity 0

Register: 0xFC04

Select Enable (SER)
Write Only

7 0

SE[7:0]

Defaults:

xxxxxxxx

SE[7:0] Selection ID bits [7:0]

The Select Enable register is a write only register that is
used as a mask to monitor a single ID during a selection
attempt. The simultaneous occurrence of the
corresponding ID bit, BSY/ false and SEL/ true will cause
an interrupt. This interrupt can be disabledby resetting all
bits in this register and in the Select Enable High (SENHI)
register (0xFC0C). If the Enable Parity Checking bit
(register 0xFC02, bit 5) is active (1), parity will be
checked during selection.

Register: 0xFC05

Bus and Status (BSR)
Read Only

7654 3210

EOD

0

The Bus and Status register is a read only register that can be used to
monitor the remaining SCSI control signals not found in the Current SCSI

Bus Status (CSBS) register (ATN/ and ACK/), as well as six other status

bits.

EOD End of DMA Transfer 7

4-10 SCSI and DMA Registers

R PERR IRA PMATCH BERR ATN ACK

0 0 0 x 0 SATN/ SACK/

The End of DMA Transfer bit is set when a DMA transfer
completes. The REQ/ and ACK/ signals should be
monitored to ensure that the last byte has been

Defaults:

transferred. This bit is reset when the DMA Mode bit is
reset (0) in the Mode (MR) register (0xFC02).

The SCSI core contains a true End of DMA Status bit
(last byte sent) in bit 7 of the Target Command (TC)
register.

R Reserved 6
PERR Parity Error 5

This bit is set if a parity error occurs during a data receive
or a device selection. The Parity Error bit can only be set
(1) if the Enable Parity Check bit (register 0xFC02, bit 5)
is active (1). This bit may be cleared by reading the Reset

Parity/Interrupt (RPI) register (0xFC07).

IRA Interrupt Request Active 4

This bit is set if an enabled interrupt condition occurs. It
can be cleared by reading the Reset Parity/Interrupt (RPI)
register (0xFC07).

PMATCH Phase Match 3

The SCSI signals MSG/, C_D/ and I_O/ represent the
current information transfer phase. The Phase Match bit
indicates whether the current SCSI bus phase matches
the lower three bits of the Target Command (TC) register.
Phase Match is continuously updated and is only
significant when the SYM53C040 is operating as a bus
initiator. A phase match is required for data transfers to
occur on the SCSI bus.

BERR Busy Error 2

The Busy Error bit is active if an unexpected loss of the
BSY/ signal has occurred. This level sensitive latch is set
whenever the Monitor Busy bit (register 0xFC02, bit 2) is
true and BSY/ is asserted. An unexpected loss of BSY/
will disable any SCSI outputs and will reset the DMA
Mode bit (register 0xFC02, bit 1).

ATN Attention 1

This bit reflects the condition of the SCSI bus control
signal ATN/. This signal is normally monitored by a target
device.

4-11

ACK Acknowledge 0

This bit reflects the condition of the SCSI bus control
signal ACK/. This signal is normally monitored by a target
device.

Register: 0xFC05

DMA Send (DSR)
Write Only

This register does not have individual bit definitions. Any write to this
register will initiate a DMA send, from the DMA core to the SCSI bus, for
either initiator or target role operations. The DMA Mode bit (register
0xFC02, bit 1) must be set prior to writing this register.

Register: 0xFC06

Start DMA Target Receive (SDTR)
Write Only

This register does not have individual bit definitions. Any write to this
register will initiate a DMA receive, from the SCSI bus to the DMA core,
for target operation only. The DMA Mode bit (register 0xFC02, bit 1) and
the Target Mode bit (register 0xFC02, bit 6) must both be set prior to
writing this register.

Register: 0xFC07

Reset Parity/Interrupt (RPI)
Read Only

This register does not have individual bit definitions. Any read to this
register resets the Parity Error bit (register 0xFC05, bit 5), the Interrupt
Request Active bit (register 0xFC05, bit 4) and the Busy Error bit
(register 0xFC05, bit 2).

Register: 0xFC07

Start DMA Initiator Receive (SDIR)
Write Only

This register does not have individual bit definitions. Any write to this
register will initiate a DMA receive from the SCSI bus, for initiator
operation only. The DMA Mode bit (register 0xFC02, bit 1) must be set
(1) and the Target Mode bit (register 0xFC02, bit 6) must be clear (0)
prior to writing this register.

4-12 SCSI and DMA Registers

Register: 0xFC08

Current SCSI Data High (CSDHI)
Read Only

7654 0

SHID2 SHID1 SHID0

000

Defaults:

0 0 0 0 0

R

SHID[2:0] Current SCSI Data High [7:5]

The Current SCSI Data High register is a read only
register that allows the microcontroller to read the active
SCSI High ID data bus. This register is used during
arbitration to check for higher priority arbitrating devices.
No parity is generated because only three of the lines are
valid.

R Reserved [4:0]

Register: 0xFC0C

Select Enable High (SENHI)
Write Only

7654 0

SHID2 SHID1 SHID0

xxx

Defaults:

0 0 0 0 0

R

SHID[2:0] SCSI High ID [7:5]

The Select Enable Register High for the SCSI High ID
lines is a write only register that is used as a mask to
monitor a single ID during a selection attempt. The
simultaneous occurrence of BSY/ false and SEL/ true and
the correct ID bit, will cause an interrupt. This interrupt
can be disabled by resetting all bits in this register and in
the Select Enable (SER) register (0xFC04). No parity is
generated because only three of the lines are valid.

R Reserved [4:0]

4-13

Register: 0xFC10

DMA Status (DS)
Read/Write

7 543210

RIODTCRIENTIP

Defaults:

0 0 0xx0xx

The DMA function in the SYM53C040 provides the capability of
transferring up to 256 bytes from memory to the SCSI port or vice versa.
The DMA function is designed to handshake automatically with the SCSI
core, to offload the microcontroller and increase SCSI throughput. The
DS register provides basic control of the DMA function, the DMA Transfer

Length (DTL) register sets the 8-bit transfer length (1 to 256), and the
DMA Source/Destination Low (DSDL) (0xFC12)andDMA
Source/Destination High (DSDH) (0xFC13) registers set the 16-bit

source or destination address for the data to be transferred. The DMA
function does not provide any additional capability for handling SCSI
protocol, so all phase changes and error conditions must still be handled
manually by the microcontroller. The DMA direction is based solely on
the SCSI I/O phase lines.

R Reserved [7:5]
IOD I/O Direction 4

This status bit will indicate the current DMA direction.
This bit is written by the microcontroller. A high on this bit
indicates the DMA is reading bytes from the SCSI core
and writing them to memory. A low on this bit indicates
the DMA is reading bytes from memory and writing them
to the SCSI core.

TC Transfer Complete 3

Thisreadonlystatusbitwillreada1followingthenormal
completion of a DMA transfer.

R Reserved 2
IEN Interrupt Enable 1

When this bit is set to a 1, the DMA function will generate
an interrupt whenever the TIP bit transitions from a 1 to
a 0. This signifies that (1) the transfer completed

4-14 SCSI and DMA Registers

normally, or (2) the TIP bit was written to a 0, which
manually interrupted the transfer.

TIP Transfer in Progress 0

When this bit is written to a 1, the DMA function will begin
atransfer.ThetransferlengthisspecifiedintheDMA

Transfer Length (DTL) register (0xFC11) and the data

source or destination addresses are specified in the DMA

Source/Destination Low (DSDL) (0xFC12)andDMA
Source/Destination High (DSDH) (0xFC13) registers. The

read value of this bit will stay 1 until either (1) the transfer
completes normally, or (2) this bit is written to a 0, which
can only be done when the DMA is not active. While this
bit is 0, the other status bits in this register will be valid
and the DTL register will hold the remaining transfer
count. Conditions for which the SCSI core will interrupt
are discussed in Chapter 2.

Register: 0xFC11

DMA Transfer Length (DTL)
Read/Write

76543210

DTL7 DTL6 DTL5 DTL4 DTL3 DTL2 DTL1 DTL0

Defaults:

00000000

DTL[7:0] Data Transfer Length [7:0]

These register bits store the 8-bit transfer length for the
DMA function. This register should be set to a value
between 0x00 and 0xFF prior to setting bit 0 (TIP) of the

DMA Status (DS) register to initiate a transfer. Setting this

register to a value of 0 corresponds to a desired transfer
length of 256 bytes. When the transfer ends or is
interrupted, this register will read the value of the number
of bytes remaining in the transfer.

4-15

Register: 0xFC12

DMA Source/Destination Low (DSDL)
Read/Write

76543210

DSDL7 DSDL6 DSDL5 DSDL4 DSDL3 DSDL2 DSD L1 DSDL0

Defaults:

00000000

DSDL[7:0] DMA Source/Destination Low [7:0]

These register bits store the least significant byte of the
DMA function’s source address for send transfers and
destination address for receive transfers. The read value
of the DSDL and DMA Source/Destination High (DSDH)
registers tracks the current source/destination address of
the transfer. If the transfer is interrupted for any reason,
the DSDL and DSDH registers will hold the next address
required, in case the interrupted transfer resumes.

Register: 0xFC13

DMA Source/Destination High (DSDH)
Read/Write

76543210

DSDH7 DSDH6 DSDH5 DSDH4 DSDH3 DSDH2 DSDH0 DSDH0

Defaults:

00000000

DSDH[7:0] DMA Source/Destination High [7:0]

These register bits store the most significant byte of the
DMA function’s source address for send transfers and
destination address for receive transfers. The read value
of the DMA Source/Destination Low (DSDL) and DSDH
registers tracks the current source/destination address of
the transfer. If the transfer is interrupted for any reason,
the DSDL and DSDH registers hold the next address
required, in case the interrupted transfer resumes.

4-16 SCSI and DMA Registers

Register: 0xFC14

DMA Interrupt (DMAI)
Read/Write

710

RINT

Defaults:

0 0 0 0 0 0 0

R Reserved [7:1]
INT DMA Interrupt 0

This register bit is the interrupt value for the DMA. This
interrupt will only be enabled if the IEN bit in the DMA
Status register is set.

4-17

4-18 SCSI and DMA Registers

Chapter 5
SFF-8067 Registers

This chapter contains descriptions of the SYM53C040 SFF-8067
registers. The SCSI/DMA registers, Two-Wire Serial registers,
Miscellaneous registers, and System registers are described in

Chapter 4 and Chapter 6 through Chapter 8. The term “set” is used to

refer to bits that are programmed to a binary one, while the terms “reset”
or “clear” are used to refer to bits that are programmed to binary zero.
Any bits marked as reserved should always be written to zero; mask all
information read from them. Reserved bit functions may change at any
time. Unless otherwise indicated, all bits in registers are active high, that
is, the feature is enabled by setting the bit. The bottom row of every
register diagram shows the default bit values, which are enabled after the
chip is powered on or reset.

Figure 5.1 summarizes the entire SYM53C040 register set.

Figure 5.1 Register Set Overview

0xFC00
0xFC1F

0xFC20
0xFCFF

0xFD00
0xFDFF

0xFE00

0xFEFF

0xFF00

0xFFFF

Symbios SYM53C040 Enclosure Services Processor Technical Manual 5-1

SCSI Core and DMA Registers

SFF-8067 Registers

Two-Wire Serial Interface R egisters

Miscellaneous Registers

System Registers

The SFF-8067 Interface register set allows observation and control of the
two SFF-8067 interface ports which are designated as port 0 and port 1.
The registers associated with port 0 occupy addresses 0xFC20 through
0xFC27 and the registers associated with port 1 occupy addresses
0xFC28 through 0xFC2F. To conserve space, the register descriptions
only appear once in this chapter. The two applicable locations are
separated by a slash (/), with the port 0 address listed first.

Table 5.1, the register map, summarizes the SFF-8067 registers in

graphical form.

Table 5.1 SFF-8067 Interface Registers

31 16 15 0 Port Address

Read Data (RDATA0) 0 0xFC20

WriteData(WDATA0) 0 0xFC21

Port Control/Status (PCST0) 0 0xFC22

Physical Address (PHAD0) 0 0xFC23

Live ESI (LESI0) 0 0xFC24

Manual Data Output (MDATA0) 0 0xFC25

Reserved – 0xFC26–0xFC27

Read Data (RDATA1) 1 0xFC28

WriteData(WDATA1) 1 0xFC29

Port Control/Status (PCST1) 1 0xFC2A

Physical Address (PHAD1) 1 0xFC2B

Live ESI (LESI1) 1 0xFC2C

Manual Data Output (MDATA1) 1 0xFC2D

Reserved – 0xFC2E–0xFC2F

5-2 SFF-8067 Registers

Register: 0xFC20/0xFC28

Read Data (RDATA0/RDATA1)
Read/Write

76543210

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Defaults:

00000000

DB[7:0] 8067 Read Data [7:0]

The Read Data bits are read/write bits that contain data
to be transferred out on the associated 8067 port in
response to a read request at that port.

Register: 0xFC21/0xFC29

Write Data (WDATA0/WDATA1)
Read/Write

76543210

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Defaults:

00000000

DB[7:0] 8067 Write Data [7:0]

The Write Data registers are read/write registers that
contain data which is transferred in on the associated
8067 port in response to a write request at that port.

Register: 0xFC22/0xFC2A

Port Control/Status (PCST0/PCST1)
Read/Write

76543210

PME

0

PME Port Manual Enable 7

R BSY RRF WRF RINT WINT

Defaults:

0 000000

The microcontroller sets this bit to enable 8067 manual
mode for the associated port. When manual mode is
enabled the microcontroller has direct control over the

5-3

associated 8067 port using the MDATA
(0xFC25/0xFC2D) register, which contains output data,
and the LESI (0xFC24/0xFC2C) register, which is used to
read the port pins. Setting this bit disables automatic
receive or transmit over the 8067 interface.

R Reserved (read only) [6:5]
BSY Port Busy Flag 4

This bit is set to a 1 when the associated 8067 port is in
any state other than idle. Writing a 0 to this bit will remove
the lockout to the other 8067 port. This bit should only be
cleared when the device connected to this port is not
responding. Therefore, a 0x10 should be written to this
register when clearing interrupts.

RRF Read Register Full (read only) 3

This read only bit is written to a 1 when a read request
has been made from the associated 8067 port and the
microcontroller loads the RDATAx (0xFC20/0xFC28)
register. This bit is cleared by the associated 8067 port
when the register data has been transferred onto the
associated 8067 port and acknowledged.

WRF Write Register Full (read only) 2

This bit is written to a 1 by the associated 8067 port when
a byte of data has been loaded into the WDATAx
(0xFC21/0xFC29) register from the associated 8067 port.
When the microcontroller reads the WDATAx
(0xFC21/0xFC29) register this bit will be automatically
cleared. This bit is read only.

RINT Read Interrupt 1

This bit is written to a 1 by the associated 8067 port when
a read request has been made from the associated 8067
port. This notifies the microcontroller to load the RDATAx
(0xFC20/0xFC28) register. The WINT and the RINT bits
are ORed together to generate the port interrupt, which
goes to the microcontroller using the Interrupt Status

(ISR) register (0xFE04).

WINT Write Interrupt 0

This bit is written to a 1 by the associated 8067 port when
a byte of data has been loaded into the WDATAx
(0xFC21/0xFC29) register from the associated 8067 port.

5-4 SFF-8067 Registers

This notifies the microcontroller to read the WDATAx
(0xFC21/0xFC29) register. The WINT and the RINT bits
are ORed together to generate the port interrupt, which
goes to the microcontroller using the Interrupt Status

(ISR) register.

Note:

The RINT and WINT bits are not self-clearing, so the
microcontroller must clear this bit if the port is interrupt
driven.

Register: 0xFC23/0xFC2B

Physical Address (PHAD0/PHAD1)
Read Only

76543210

PA7PA6PA5PA4PA3PA2PA1PA0

Default:

xxxxxxxx

PA[7:0] Physical Address [7:0]

The Physical Address registers are read only registers
that contain values of the PA inputs.

Register: 0xFC24/0xFC2C

Live ESI (LESI0/LESI1)
Read Only

76543210

PESI/ DWR/ RD/ ACK/ D3 D2 D1 D0

Defaults:

xxxxxxxx

PESI/ PARALLEL_ESI/ Value 7

Reading this active low bit gives the state of the PESI/
signal, which is used to select between the SEL_ID and
the bidirectional interface that distinguishesthe SFF-8067
interface from SFF-8045.

DWR/ DSK_WR/ Value 6

Reading this active low bit gives the state of the
DSK_WR/ signal on the SFF-8067 interface. When this
active low bit is cleared, the drive is ready to write data

5-5

to the SYM53C040. It will be cleared (0) if the PESI/ bit
is cleared (0). If PESI/ is 1, this bit reflects the value of
the PA6 signal.

RD/ DSK_RD/ Value 5

Reading this active low bit gives the state of the
DSK_RD/ signal on the SFF-8067 interface. When this
active low bit is cleared, the drive is ready to read data
from the SYM53C040. It will be cleared (0) if the PESI/
bit is cleared (0). If PESI/ is 1, this bit reflects the value
of the PA5 signal.

ACK/ ENCL_ACK/ Value 4

Reading this active low bit gives the state of the
ENCL_ACK/ signal on the SFF-8067 interface . It will be
cleared (0) if the PESI/ bit is cleared (0). If PESI/ is 1, this
bit reflects the value of the PA4 signal.

D[3:0] 8067 Interface Data Nibble Bits [3:0]

Reading these bits gives the contents of the D[3:0]
signals on the SFF-8067 interface. If PESI/ is 1, these
bits reflect the value of the PA[3:0] signals.

Register: 0xFC25/0xFC2D

Manual Data Output (MDATA0/MDATA1)
Read/Write

76543210

PESI/ DWR/ RD/ ACK/ D3 D2 D1 D0

11111111

The values in these registers are asserted onto the SFF-8067 bus when
the PME bit is set in the PCSTx registers (0xFC22/0xFC2A). These
signals are open drain on the SFF-8067 bus. Therefore, a 1 written to
this register is considered a “soft” value and can be pulled low by another
device on the bus.

PESI/ PARALLEL_ESI/ Value 7

This active low bit is used to change the state of the
PESI/ signal, which is used to select between the SEL_ID
and the bidirectional interface that distinguishes the
SFF-8067 interface from SFF-8045.

5-6 SFF-8067 Registers

Defaults:

DWR/ DSK_WR/ Value 6

When this active low bit is cleared, the drive is ready to
write data to the SYM53C040.

RD/ DSK_RD/ Value 5

When this active low bit is cleared, the drive is ready to
read data from the SYM53C040.

ACK/ ENCL_ACK/ Value 4

This active low bit is cleared as an acknowledge signal
driven by the SYM53C040 in discovery, read, and write
operations.

D[3:0] 8067 Interface Data Nibble Bits [3:0]

These bits contain the current data nibble for the D[3:0]
signals in read/write operations.

5-7

5-8 SFF-8067 Registers

Chapter 6
Two-Wire Serial
Registers

This chapter contains descriptions of the SYM53C040 Tw o-Wire Serial
interface registers. The SCSI/DMA registers, SFF-8067 registers,
Miscellaneous registers, and System registers are described in Chapter 4,

Chapter 5, Chapter 7,andChapter 8. The term “set” is used to refer to

bits that are programmed to a binary one, while the terms“reset” or “clear”
are used to refer to bits that are programmed to binary zero. Any bits
marked as reserved should alwaysbe written to zero; mask all information
read from them. Unless otherwise indicated, all bits in registers are active
high, that is, the feature is enabled by setting the bit. The bottom row of
every register diagram shows the default bit values , which are enabled
after the chip is powered on or reset.

Figure 6.1 summarizes the entire SYM53C040 register set.

Figure 6.1 Register Set Overview

0xFC00
0xFC1F

0xFC20
0xFCFF

0xFD00
0xFDFF

0xFE00

0xFEFF

0xFF00

0xFFFF

Symbios SYM53C040 Enclosure Services Processor Technical Manual 6-1

SCSI Core and DMA Registers

SFF-8067 Registers

Two-Wire Serial Interface R egisters

Miscellaneous Registers

System Registers

All registers for the Two-Wire Serial interface 0, other than the Control
register, are accessed through Register 0xFD00. All registers for the
Two-Wire Serial interface 1, other than the Control register, are accessed
through Register 0xFD02. To select one of the three registers available
at address 0xFD00 or 0xFD02, write the desired value to the ES[0:2] bits
in the Control register (0xFD01 or 0xFD03). To conserve space, the
register descriptions only appear once in this chapter. The two applicable
locations are separated by a slash, with the Two-Wire Serial interface 0
address listed first.

Table 6.1, the register map, summarizes the Two-Wire Serial registers in

graphical form.

Table 6.1 Two-Wire Serial Registers

31 16 15 0 ES[0:2] Definition Address

Two-Wire Serial Interface 0 Register Access

Two-Wire Serial Interface 0 Control/Status

Two-Wire Serial Interface 1 Register Access

Two-Wire Serial Interface 1 Control/Status

MISC N/A Miscellaneous 0xFD04
Two-Wire Serial Interface 0 Manual Control N/A TWS Manual Control 0xFD05
Two-Wire Serial Interface 1 Manual Control N/A TWS Manual Control 0xFD06

000 Own Address 0xFD00
010 Clock
100 Data

N/A Control and Status Write 0xFD01
0xx (ES0 = 0) Control Reads
1xx (ES0 = 1) Status Reads

000 Own Address 0xFD02

010 Clock

100 Data

N/A Control and Status Write 0xFD03
0xx (ES0 = 0) Control Reads
1xx (ES0 = 1) Status Reads

6-2 Two-Wire Serial Registers