LSI LSIFC929 Technical Manual

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Technical

Manual

LSIFC929DualChannel Fibre Channel I/O Processor

Revision 2.0

August 2001

S14073

Electromagnetic Compatibility Notices

This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

1. This device may not cause harmful interference, and

2. This device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15

of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guaranteethat interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

• Reorient or relocate the receiving antenna.

• Increase the separation between the equipment and the receiver.

• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

• Consult the dealer or an experienced radio/TV technician for help.

Shielded cables for SCSI connection external to the cabinet are used in the compliance testing of this Product. LSI Logic is not responsible for any radio or television interference caused by unauthorized modiﬁcation of this equipment or the substitution or attachment of connecting cables and equipment other than those speciﬁed by LSI Logic. The correction of interferences caused by such unauthorized modiﬁcation, substitution, or attachment will be the responsibility of the user.

The LSI Logic LSIFC929 is tested to comply with FCC standards for home or ofﬁce use.

This Class B digital apparatus meets all requirements of the Canadian Interference-Causing Equipment Regulations. Cet appareil numérique de la classe B respecte toutes les exigences du Règlement sur le matériel brouilleur du

Canada.

This is a Class B product based on the standard of the Voluntary Control Council for Interference from Information Technology Equipment (VCCI). If this is used near a radio or television receiver in a domestic environment, it may cause radio interference. Install and use the equipment according to the instruction manual.

LSI Logic Corporation North American Headquarters Milpitas, CA

408.433.8000

This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not veriﬁed either the functional descriptions, or the electrical and mechanical speciﬁcations using production parts.

This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties

LSI Logic products are not intended for use in life-support appliances, devices, or systems. Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic ofﬁcer is prohibited.

DB14-000135-02, Third Edition (August 2001) This document describes LSI Logic Corporation’s LSIFC929 Dual Channel Fibre Channel I/O Processor and will remain the ofﬁcial reference source for all revisions/releases of this product until rescinded by an update.

LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.

The LSI Logic logo design and GigaBlaze are registered trademarks of LSI Logic Corporation. ARM is a registered trademark of ARM Ltd.,, used under license. All other brand and product names may be trademarks of their respective companies.

To receive product literature, visit us at http://www.lsilogic.com. For a current list of our distributors, sales ofﬁces, and design resource

centers, view our web page located at http://www.lsilogic.com/contacts/na_salesofﬁces.html

iii

Audience

Preface

This book is the primary reference and technical manual for the LSIFC929 Fibre Channel I/O Processor. It contains a complete functional description for the LSIFC929 and includes complete physical and electrical speciﬁcations for the product.

This document was prepared for logic designers and applications engineers and is intended to provide an overview of the LSI Logic LSIFC929 and to explain how to use the LSIFC929 in the initial stages of system design.

This document assumes that you have some familiarity with microprocessors and related support devices. The people who beneﬁt from this book are:

Organization

• Engineers and managers who are evaluating the LSIFC929 for

possible use in a system

• Engineers who are designing the LSIFC929 into a system

This document has the following chapters and appendixes:

• Chapter 1, Introduction, provides a general description of the

LSIFC929.

• Chapter 2, Fibre Channel Overview, brieﬂy describes some key

elements of Fibre Channel, including Layers, Topologies, and Classes of Service.

LSIFC929 Dual Channel Fibre Channel I/O Processor v

• Chapter 3, LSIFC929 Overview, provides an introduction to the

• Chapter 4, Signal Descriptions, lists and describes the signals on

• Chapter 5, Register Descriptions, brieﬂy describes the PCI address

• Chapter 6, Speciﬁcations, describes the electrical speciﬁcations of

• Appendix A, Register Summary, is a register summary.

• Appendix B, Reference Speciﬁcations, lists several speciﬁcations

• Appendix C, Glossary of Terms and Abbreviations, is a glossary

Related Publications

Fusion-MPT Message Passing Interface Speciﬁcation, Number DB14-000174-00

basic features of the LSIFC929, including the host interface, protocol assist engines, and support components.

the LSIFC929.

space, the Conﬁguration Registers, and the Host Interface Registers.

the LSIFC929, and provides pinout information and packaging dimensions.

and applicable World Wide Web URLs that may be of beneﬁt to the reader.

of terms and abbreviations.

Conventions Used in This Manual

The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Signals that are active

LOW end in an “/.” Hexadecimal numbers are indicated by the preﬁx “0x” —for example,

0x32CF. Binary numbers are indicated by the preﬁx “0b” —for example, 0b0011.0010.1100.1111.

vi Preface

Revision Record

Revision Date Remarks

0.3 04/2000 First Advance Information printing.

1.0 05/2001 First Preliminary release. Changes: Converted the Manual to LSI format. Table 4.2 - RTRIM description changed. Table 4.2 - RXLOS0 and RXLOS1 descriptions changed. Table 4.4 - Test Modes removed from MODE[7:0] description. Section 5.3.2 - Note reworded. Register 0x00C, page 5-14 - Cache Line Size description modiﬁed. Register 0x040, page 5-31 - Changed this register from Read/Write to Write Only. Table 6.8 - Min/Max values and test conditions changed. Figure 4.1 and Tables 4.1 and 4.2 have been moved to the end of Chapter 6, making the layout of this Manual consistent with our current guidelines.

They are now Figure 6.16 and Tables 6.16 and 6.17

Table 4.1 - new signals are added to the device, incorporating hot swap capabilities. They are also added to Figure 6.16 and Tables 6.16 and 6.17.

2.0 07/2001 Release of Final Manual. Changes: Deleted Section 1.7. Removed “Draft” references from Manual. Table 6.1 - Changed ESD maximum spec to 1.5 kV. Section 6.2.2 - Referred user to the Fibre Channel Physical Interfaces speciﬁcation (FC-PI, Rev. 11) for Fibre Channel Interface Timings. Appendix B, Table 6.8 - Updated the list of Reference Speciﬁcations.

Preface vii

viii Preface

Contents

Chapter 1 Introduction

1.1 Overview 1-1

1.1.1 Hardware Features 1-1

1.1.2 FC Features 1-2

1.1.3 Software Features 1-3

1.1.4 OS Support 1-3

1.1.5 Targeted Applications 1-3

1.2 General Description 1-4

1.2.1 Multifunction PCI 1-5

1.2.2 Simple Autospeed Negotiation Algorithm 1-5

1.2.3 Failover 1-5

1.3 Hardware Overview 1-6

1.3.1 PCI Interface 1-7

1.3.2 32-Bit Memory Controller 1-7

1.3.3 I/O Processor 1-8

1.3.4 System Interface 1-8

1.3.5 Integrated 2 Gbaud Transceivers 1-8

1.3.6 Link Controllers 1-8

1.3.7 Transmitters 1-9

1.3.8 Receivers 1-9

1.3.9 Context Managers 1-9

1.4 Initiator Operations 1-9

1.5 Target Operations 1-9

1.6 Diagnostics 1-9

Chapter 2 Fibre Channel Overview

2.1 Introduction 2-1

2.2 FC Layers 2-2

2.3 Frames 2-3

LSIFC929 Dual Channel Fibre Channel I/O Processor ix

2.4 Exchanges 2-4

2.5 FC Ports 2-7

2.6 FC Topologies 2-7

2.6.1 Point-to-Point Topology 2-8

2.6.2 Fabric Topology 2-8

2.6.3 Arbitrated Loop Topology 2-8

2.7 Classes of Service 2-9

Chapter 3 LSIFC929 Overview

3.1 Introduction 3-1

3.1.1 Data Flows 3-2

3.2 Message Interface 3-3

3.2.1 Messages 3-3

3.2.2 Message Flow 3-4

3.3 SCSI Message Class 3-5

3.4 LAN Message Class 3-6

3.5 Target Message Class 3-7

3.6 Support Components 3-8

3.6.1 SSRAM Memory 3-8

3.6.2 Flash ROM 3-9

3.6.3 Serial EEPROM 3-9

Chapter 4 Signal Descriptions

Chapter 5 Registers

5.1 PCI Addressing 5-1

5.2 PCI Bus Commands Supported 5-2

5.3 PCI Cache Mode 5-3

5.3.1 Support for PCI Cache Line Size Register 5-4

5.3.2 Selection of Cache Line Size 5-4

5.3.3 Memory Write and Invalidate Command 5-4

5.3.4 Read Commands 5-6

5.4 Unsupported PCI Commands 5-7

5.5 Programming Model 5-7

5.6 PCI/Multifunction PCI Conﬁguration Registers 5-7

5.6.1 Multifunction PCI 5-8

5.7 Host Interface Registers 5-24

5.8 Shared Memory 5-32

x Contents

Chapter 6 Speciﬁcations

6.1 Electrical Requirements 6-1

6.2 AC Timing 6-6

6.2.1 PCI Interface Timing Diagrams 6-6

6.2.2 Fibre Channel Interface Timings 6-18

6.2.3 Memory Interface Timings 6-19

6.3 Packaging 6-22

6.4 Mechanical Drawing 6-26

6.5 Package Thermal Considerations 6-27

Appendix A Register Summary

Appendix B Reference Speciﬁcations

Appendix C Glossary of Terms and Abbreviations

Index

Customer Feedback

Figures

1.1 LSIFC929 Typical Implementation 1-5

1.2 LSIFC929 Block Diagram 1-7

2.1 FC Layers 2-2

2.2 Link Control Frame 2-3

2.3 Data Frame 2-4

2.4 Exchange to Character 2-5

2.5 FCP Exchange 2-6

2.6 Write Event Trellis 2-7

2.7 Point-to-Point Topology 2-8

2.8 Fabric Topology 2-8

2.9 Arbitrated Loop Topology 2-9

3.1 LSIFC929 Block Diagram 3-2

3.2 LSIFC929 Message Flow 3-5

Contents xi

Tables

3.3 LAN Protocol Stack 3-7

3.4 LSIFC929 Typical Implementation 3-8

4.1 LSIFC929 Functional Signal Grouping 4-2

6.1 Conﬁguration Register Read 6-7

6.2 Conﬁguration Register Write 6-8

6.3 Operating Register Read 6-9

6.4 Operating Register Write 6-10

6.5 Back-to-Back Read 6-11

6.6 Back-to-Back Write 6-12

6.7 Burst Read 6-13

6.8 Burst Write 6-14

6.9 Read With 64-Bit Initiator and 64-Bit Target 6-15

6.10 64-Bit Dual-Address Cycle 6-16

6.11 SSRAM Read/Write/Read Timing Waveforms 6-19

6.12 FLASH ROM Read Timing Waveforms 6-20

6.13 FLASH ROM Write Timing Waveforms 6-21

6.14 LSIFC929 Pinout (329-Pin BGA) Top View 6-22

6.15 329-Pad Plastic Ball Grid Array 6-26

4.1 PCI Interface 4-3

4.2 Fibre Channel Interface 4-8

4.3 Memory Interface 4-10

4.4 Conﬁguration Signals 4-12

4.5 Miscellaneous Signals 4-14

4.6 JTAG Test and I/O Processor Debug 4-15

4.7 Power and Ground Pins 4-16

5.1 PCI Bus Commands and Encoding Types 5-3

5.2 LSIFC929 PCI Conﬁguration Register Map 5-8

5.3 PCI Memory 0 Address Map 5-24

6.1 Absolute Maximum Stress Ratings 6-1

6.3 Capacitance 6-2

6.4 Input Signals (FAULT1/, FAULT0/, ROMSIZE[1:0], ARMEN/, FSELZ[1:0], MODE[7:0], SWITCH, HOTSWAPEN/) 6-2

6.2 Operating Conditions 6-2

6.5 Schmitt Input Signals (REFCLK, TESTRESET/, ZCLK, TCK, TDI, TRST/, TMS_CHIP, TMS_ICE) 6-3

xii Contents

6.6 4 mA Bidirectional Signals (LIPRESET/, ODIS1, ODIS0, BYPASS1/, BYPASS0/, MD[31:0], MA[21:0], MWE[1:0]/, FLASHCS/, BWE[3:0]/, RAMCS/, ZZ, MP[3:0], SCL, SDA, RXLOS1, RXLOS0, ADSC/, ADV/, TDO) 6-3

6.7 8 mA Bidirectional Signals (MODDEF1[2:0], MODDEF0[2:0], GPIO[3:0], MOE[1:0]/, LED[4:0]/, MCLK) 6-3

6.8 PCI Input Signals (PCICLK, GNT/, IDSEL, RST/) 6-4

6.9 PCI Bidirectional Signals (AD[63:0], C_BE[7:0]/, FRAME/, IRDY/, TRDY/, STOP/, PERR/, PAR, ACK64/, ENUM/, 64EN/) 6-4

6.10 PCI Output Signals (PAR64, REQ/, REQ64/, DEVSEL/, SERR/, INTA/, INTB/) 6-5

6.11 PCI Interface Timings 6-17

6.12 SSRAM Read/Write/Read Timings 6-19

6.13 FLASH ROM Read Timings 6-20

6.14 FLASH ROM Write Timings 6-21

6.15 Alphanumeric Pad Listing by BGA Position 6-24

6.16 Alphanumeric Pad Listing by Signal Name 6-25

6.17 Maximum Allowable Ambient Temperature vs. Airﬂow 6-27

A.1 LSIFC929 Multifunction PCI Registers A-1 A.2 LSIFC929 Host Interface Registers A-2 B.1 Reference Speciﬁcations B-1

Contents xiii

xiv Contents

1.1 Overview

Chapter 1 Introduction

This chapter provides general overview information on the LSIFC929 Dual Channel Fibre Channel I/O Processor chip. The chapter contains the following sections:

• Section 1.1, “Overview”

• Section 1.2, “General Description”

• Section 1.3, “Hardware Overview”

• Section 1.4, “Initiator Operations”

• Section 1.5, “Target Operations”

• Section 1.6, “Diagnostics”

The LSIFC929 is a high-performance, cost effective Dual Channel Fibre Channel (FC) I/O Processor. It represents the very latest system level integration technology in intelligent I/O processors from LSI Logic. The Storage Area Network (SAN) environment is fully supported with both Fibre Channel Protocol for SCSI (FCP) and LAN/IP.

1.1.1 Hardware Features

Following is a list of hardware features supported by the LSIFC929.

• Highly integrated full duplex Dual Channel Fibre Channel I/O

Processor

• Integrated 2 Gbaud Dual Channel FC serial link

• 64-bit/66 MHz host PCI bus (backward compatible with

32-bit/33 MHz)

LSIFC929 Dual Channel Fibre Channel I/O Processor 1-1

• Integrated BER link testing

• 32-bit ARM RISC processor

• Intelligent high-performance context management

• Synchronous SRAM external memory interface

• Full simultaneous target and initiator operations

• Implements common Message Passing Interface (MPI)

• Failover

• Load Balancing

• Firmware supports up to 2000 concurrent host commands

• PC01 compliant

• PCI 2.2 compliant

• JTAG debug interface

• 329-pin BGA

1.1.2 FC Features

Following is a list of Fibre Channel features supported by the LSIFC929.

• Class 2 support and Class 3 support (with optional conﬁrmed

delivery)

• BB credit of 3, alternate login of 1 (each channel)

• FC-PH compliance

• FC-AL 7.0 compliance

• FC-FCP, FC-PLDA compliance

• FC-FLA compliance

• FCA-IP, IETF-IPFC compliance

• NL_Port (NL_Port Attach)

• FL_Port (Public Loop Attach)

• F_Port (Fabric Attach)

• N-Port (Point-to-Point)

• Autonegotiate between 1 Gbit/s and 2Gbit/s link speeds under

ﬁrmware control for easy updating

1-2 Introduction

1.1.3 Software Features

Following is a list of software features supported by the LSIFC929.

• Fusion-MPT drivers

• Supports optimum server I/O proﬁle with low CPU utilization

• Supports optimum workstation I/O proﬁle with maximum I/O

performance

• Remote diagnostic capability

• OS drivers support fail over and load balancing

• SAN Storage Management

1.1.4 OS Support

Following is a list of operating systems supported by the LSIFC929.

• Windows 2000

• Windows NT 4.0 SP4 and NT 5.0

• Windows XP

• NetWare 4.11 and 5.0

• UnixWare 2.12 and Gemini

• Solaris 2.6, 2.7 – X86

• Linux

1.1.5 Targeted Applications

Following is a list of key applications targeted by the LSIFC929.

• SANs

• Server clustering environments

• Embedded RAID

• Low cost PCI/FC host adapters

• Host main boards

• Routers and bridges

Overview 1-3

1.2 General Description

The LSI Logic LSIFC929 Dual Channel Fibre Channel I/O Processor is a high-performance, Intelligent I/O Processor (IOP) designed to simultaneously support mass storage and IP protocols on a full duplex 2 GBaud FC Link. The sophisticated design and local memory architecture work together to reduce the host CPU and PCI bandwidth required to support FC I/O operations.

From the host CPU perspective, the LSIFC929 manages the FC Link at the exchange level for mass storage (FCP) protocols. The LSIFC929 supports multiple I/O requests per host interrupt in most applications.

From the FC Link perspective, the LSIFC929 is a highly efﬁcient NL_Port supporting point-to-point, and public and private loop topologies, as well as the FC switch/attach topology deﬁned under the ANSI X3T11 FC-PH standard. The LSIFC929 contains sufﬁcient hardware support to perform Class 3 service. The LSIFC929 is uniquely designed to support FC environments where independent, full duplex transmission is required for maximum FC Link efﬁciency. Special attention has been given to the design to accelerate context switching and Link utilization.

The LSIFC929 includes a 64-bit, 66 MHz PCI interface to the host environment. The host interface is designed to minimize the amount of time spent on the PCI bus for nondata moving activities such as initialization, command and error recovery. In addition, the host interface has inherent ﬂexibility to support the OEM’s implementation trade-offs between CPU, PCI, and I/O bandwidth.

The high level of integration in the LSIFC929 Controller enables low cost FC implementations. Figure 1.1 shows a typical board conﬁguration incorporating the LSIFC929 Controller.

1-4 Introduction

Figure 1.1 LSIFC929 Typical Implementation

Channel 0

Channel 1

2 2 2

Clock

(106 MHz)

(1 Mbyte typ.)

1.2.1 Multifunction PCI

Coupled with the dual channel operation, the LSIFC929 adds multifunction capability on the PCI bus. This capability allows the host to see two distinct “channels” or host adapters. Each channel provides full, concurrent support for FCP Initiator, Target, and LAN protocols.

SSRAM

Integrated

Transceiver

Integrated

Transceiver

Flash

(1 Mbyte)

LSIFC929

Memory

Controller

EEPROM

(2 Kbyte)

PCI Bus

32/64

Serial

1.2.2 Simple Autospeed Negotiation Algorithm

Backward compatibility with 1 Gbit/s FC devices is maintained through the use of the “Simple Autospeed Negotiation Algorithm.” After a power-on, loss of signal, or loss of word synchronization for longer than the R_T_TOV time-out, the LSIFC929 will perform this operation to determine whether a point-to-point device or all of the devices on a loop are either 1 Gbit/s or 2 Gbits/s devices.

1.2.3 Failover

The LSIFC929 supports two PCI functions and FC ports, which improves performance and provides a redundant path in high-availability systems that require failover capabilities. In case of a Link Failure, the LSIFC929 architecture allows the OS driver to support automatic failover, without the need for IOC intervention.

General Description 1-5

1.3 Hardware Overview

In today’s fast growing server, RAID, and workstation marketplaces, higher levels of performance, scalability and reliability are required to stay competitive in the SAN market.

The LSIFC929 provides the performance and ﬂexibility to meet tomorrow’s FC connectivity requirements.

The LSIFC929 and the LSI Logic software drivers provide superior performance and lower host CPU overhead than other competitive solutions. Because of its high level of integration and streamlined architecture, the LSIFC929 provides the highest level of performance in a more cost effective FC solution.

Figure 1.2 shows the functional block diagram for the LSIFC929. The

architecture maximizes performance and ﬂexibility by deploying ﬁxed gates in critical performance areas and utilizing multiple ARM RISC processors (two for context management and an additional one for the I/O Processor). Each of the major blocks is brieﬂy described below.

1-6 Introduction

Figure 1.2 LSIFC929 Block Diagram

Channel [0]

SerDes

Giga

Blaze

Channel [0] ZBus

SerDes

Giga

Blaze

Channel [1] ZBus

Channel [1]

Link

Control

Link

Control

CtxMgr

Transmitter

Receiver

ZArbiter

Transmitter

Receiver

ZArbiter

Channel

Arbiter/

Mux

Zbridge

ZQman

Channel

Arbiter/

Mux

Zbridge

ZQman

DMA[0]

DMA[1]

PCI

Arbitrator

System

Interface

IOP

ZArbiter

TimerCfg

XMem

PBSRAM

PCI

Interface

PCI

1.3.1 PCI Interface

The LSIFC929 uses a 64-bit (33 MHz or 64 MHz) PCI interface or a 32-bit (33 MHz or 64 MHz) PCI interface. In addition, support is provided for Dual Address Cycle (DAC), PCI power management, Subsystem Vendor ID and Vendor Product Data (VPD). Extended access cycles (MRL, MRM, MWI) are also supported.

1.3.2 32-Bit Memory Controller

The memory controller provides access to Flash ROM and 32-bit Synchronous SRAM. It supports both interleaved and noninterleaved conﬁgurations up to a maximum of 4 Mbytes of synchronous SRAM. A

Hardware Overview 1-7

general purpose memory expansion bus supports up to 1 Mbyte of Flash ROM.

1.3.3 I/O Processor

The LSIFC929 uses a 32-bit ARM RISC processor to control all system interface and message transport functionality. This frees the host CPU for other processing activity and improves overall I/O performance. The RISC processor and associated ﬁrmware have the ability to manage an I/O from start to ﬁnish without host intervention. The RISC processor also manages the message passing interface.

1.3.4 System Interface

The system interface efﬁciently passes messages between the LSIFC929 and other I/O agents. It consists of four hardware FIFOs for the message queuing lists: Request Free, Request Post, Reply Free, and Reply Post. Control logic for the FIFOs is provided within the LSIFC929 system interface with messages stored in external memory.

1.3.5 Integrated 2 Gbaud Transceivers

The LSIFC929 implements LSI Logic’s GigaBlaze®2 Gbaud integrated transceivers. GigaBlaze is backward compatible with 1Gbaud systems, using a ﬁrmware-implemented “Simple Autospeed Negotiation Algorithm” for easy updates. The integrated 2 Gbaud transceivers provide a FC compliant physical interface for cost conscious and real estate limited applications.

1.3.6 Link Controllers

The integrated link controller is FC-AL-2 (Rev. 7.0) compatible and performs all link operations. The controller monitors the Link State and strictly adheres to the Loop Port State Machine ensuring maximum system interoperability. The link control interfaces to the integrated transceiver.

1-8 Introduction

1.3.7 Transmitters

The transmitter builds sequences based on context information and transmits resulting frames to the FC link using the Link Controller. Each transmitter includes two 2 Kbyte buffers to support frame payloads.

1.3.8 Receivers

The receivers accept frame data from the Link Controller and DMAs the encapsulated information to local or system memory. Each receiver contains three 2 Kbyte buffers which support a BB-Credit of up to three or an Alternate Login BB-Credit of 1 on each channel.

1.3.9 Context Managers

The LSIFC929 uses an ARM RISC processor in each channel to support I/O context swap to external memory and FCP management for both Initiator and Target applications. Context operations include support for transmit and resource queue management as well as scatter/gather list management.

1.4 Initiator Operations

The LSIFC929 autonomously handles FCP exchanges upon request from the host. The LSIFC929 generates appropriate sequences and frames necessary to complete the request and provides feedback to the host on the status of the request.

1.5 Target Operations

The LSIFC929 provides for general purpose target functions such as those required for front-end RAID applications.

1.6 Diagnostics

The LSIFC929 provides the capabilities to do a simpliﬁed “Link Check” Bit Error Rate (BER) test on the link for diagnostic purposes. In a special test mode the controller can transmit and verify a programmed data pattern for link evaluation.

Initiator Operations 1-9

1-10 Introduction

Chapter 2 Fibre Channel Overview

This chapter provides general overview information on Fibre Channel (FC). The chapter contains the following sections:

• Section 2.1, “Introduction”

• Section 2.2, “FC Layers”

• Section 2.3, “Frames”

• Section 2.4, “Exchanges”

• Section 2.5, “FC Ports”

• Section 2.6, “FC Topologies”

• Section 2.7, “Classes of Service”

2.1 Introduction

FC is a high-performance, hybrid interface. It is both a channel and a network interface that contains network features to provide the required connectivity, distance, protocol multiplexing, as well as traditional channel features to retain the required simplicity, repeatable performance, and guaranteed delivery. Popular industry standard networking protocols such as Internet Protocol (IP) and channel protocols such as Small Computer System Interface (SCSI) have been mapped to the FC standard.

The FC structure is defined by five functional layers. These layers, shown in Figure 2.1, define the physical media and transmission rates, encoding scheme, framing protocol and flow control, common services, and the Upper Level Protocol (ULP) interfaces.

LSIFC929 Dual Channel Fibre Channel I/O Processor 2-1

Figure 2.1 FC Layers

Behaviors

System

Interface

Logical

Layers

FC-4

Upper Layer Protocol (ULP)

IPESCONHIPPIIPI-3FCP

2.2 FC Layers

Common Services - e.g.,...Striping (not deﬁned)

Framing Protocol/Flow Control

8b/10b Encode/Decode

8496424821241062

Mbits/s (Full Duplex) FC-PH-2

100 200 400 800

Physical

Layers

MBytes/s

FC-3

FC-2

FC-1

FC-0

The lowest layer, FC-0, is the media interface layer. It deﬁnes the physical characteristics of the interface. It includes transceivers, copper-to-optical transducers, connectors, and any other associated circuitry necessary to transmit or receive at 1062 or greater Mbaud/s rates over copper or optical cable.

The FC-1 layer deﬁnes the 8b/10b encoding/decoding scheme, the transmission protocol necessary to integrate the data and transmit clock, and the receive clock recovery. Implementation of this layer is usually divided between the hardware implementing the FC-0 layer in a transceiver, and the protocol device which implements the FC-2 layer. Speciﬁcally, the FC-0 transceivers can include the clock recovery circuitry while the 8b/10b encoding/decoding is provided in the protocol device.

The FC-2 layer deﬁnes the rules for the signaling protocol and describes transfer of the Frames, Sequences, and Exchanges. The meaning of the data being transmitted or received is transparent to the FC-2 layer. However, the context between any given set of frames is maintained at

2-2 Fibre Channel Overview

2.3 Frames

the FC-2 layer through the Sequence and Exchange constructs. The framing protocol creates the constructs necessary to form frames with the data being packetized within each frame’s payload.

The FC-3 layer provides common services that span multiple N_Ports (see Section 2.5, “FC Ports,” page 2-7). Some of these services include Striping, Hunt Groups, and Multicasting. All of these services allow a single port or fabric to communicate to several N_Ports at one time.

The top layer deﬁned in FC is the FC-4 layer. The FC-4 layer provides a seamless integration of existing standards. It speciﬁes the mapping of Upper Layer Protocols (ULPs) to the layers below. Some of these ULPs include SCSI and IP. Each of these ULPs is deﬁned in its own ANSI document.

There are two types of frames used in FC: Link Control frames and Data frames. Link Control frames contain no payload and are ﬂow control responses to Data frames. An example of a Link Control frame is the ACK frame.

Figure 2.2 Link Control Frame

Start

Frame

(4)

( ) = Number of Bytes

Frame

Header

(24)

CRC

(4)

End

Frame

(4)

A Data frame is any frame which contains data in the payload ﬁeld. An example of a Data frame is the LOGIN frame.

Frames 2-3

Figure 2.3 Data Frame

( ) = Number of Bytes

In FC, an Ordered Set is a group of four 10-bit characters that provide low level Link functions, such as frame demarcation and signaling between two ends of a Link. All frames start with a Start-of-Frame (SOF) and end with an End-of-Frame (EOF) Ordered Set. Each frame contains at least a 24-byte header deﬁning such things as Destination and Source ID, Class of Service and type of frame (e.g., FCP or FC-LE). The biggest ﬁeld within a frame can be the payload ﬁeld. If the frame is a Link Control frame, then there is no payload. If it is a Data frame, then the frame will contain a Payload ﬁeld of up to 2112 bytes. Finally, the frame includes a Cyclic Redundancy Check (CRC) ﬁeld used for detection of transmission errors, followed by the EOF Ordered Set.

2.4 Exchanges

Figure 2.4 outlines the FC hierarchical Data structures. At the most

elemental level, four 8b/10b encoded characters make up a FC Word. A FC Frame is a collection of FC words. A FC Sequence is made up of one or more frames, and a FC Exchange is made up of one or more sequences.

Start

Frame

(4)

Frame

Header

(24)

Data Field

(Optional Headers and

Payload)

(0 to 2112)

CRC

(4)

End

Frame

(4)

2-4 Fibre Channel Overview

Figure 2.4 Exchange to Character

EXCHANGE

SEQ 1 SEQ 2 SEQ 4 SEQ N

FRAME 1 FRAME 2 FRAME 4 FRAME N

SOF HEADER DATA CRC EOF Frame

K28.5 D21.5 D23.0 WordD23.0

0 Character0 1 1 1 1 1 0 1 0

SEQ 3

FRAME 3

The following discussion illustrates an Exchange by considering a typical parallel SCSI I/O. In parallel SCSI, there are several phases which make up the I/O. These phases include Command, Data, Message, and Status phases.

Using the FCP for the SCSI ULP, these phases can be mapped into the other lower FC layers. Figure 2.5 shows the components that make up the FCP exchange.

Exchanges 2-5

Figure 2.5 FCP Exchange

FCP EXCHANGE

CMDSEQ DataReqSEQ

FRAME 1

FRAME 1 FRAME 1

FRAME 2 FRAMEnFRAME 1

ResponseSEQDataSEQ

Figure 2.6 shows how the Exchange ﬂows between the Initiator and

Target. The Initiator starts the FCP exchange by sending a Command Sequence containing one frame to the Target. The Frame’s payload contains the Command Descriptor Block (CDB). The Target will then respond with a Data Delivery Request Sequence containing one Frame. The payload of this Frame contains a XFER_RDY response. Once the Initiator receives the Target’s response, it will begin sending the Data Sequence(s), which may contain one or more Frames. This is analogous to parallel SCSI’s DATA_OUT phase. When the Target has received the last Frame of the Data Sequence(s), it will send a Response Sequence containing one Frame to the Initiator, thus concluding the FCP Exchange.

2-6 Fibre Channel Overview

+ 112 hidden pages

LSI LSIFC929 Technical Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 Overview

1.1.1 Hardware Features

1.1.2 FC Features

1.1.3 Software Features

1.1.4 OS Support

1.1.5 Targeted Applications

1.2 General Description

1.2.1 Multifunction PCI

1.2.2 Simple Autospeed Negotiation Algorithm

1.2.3 Failover

1.3 Hardware Overview

1.3.1 PCI Interface

1.3.2 32-Bit Memory Controller

1.3.3 I/O Processor

1.3.4 System Interface

1.3.5 Integrated 2 Gbaud Transceivers

1.3.6 Link Controllers

1.3.7 Transmitters

1.3.8 Receivers

1.3.9 Context Managers

1.4 Initiator Operations

1.5 Target Operations

1.6 Diagnostics

2.1 Introduction

2.2 FC Layers

2.3 Frames

2.4 Exchanges