LSI LSI53C896 Technical Manual

TECHNICAL

*

MANUAL

LSI53C896
PCI to Dual Channel
Ultra2 SCSI
Multifunction Controller

Version 3.2

April 2001

®

This document contains proprietary information of LSI Logic Corporation. The

*

information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.

Document DB14-000083-03, Fourth Edition (April 2001)
This document describes the LSI Logic LSI53C896 PCI to Dual Channel Ultra2
SCSI Multifunction Controller and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.

To receive product literature, visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.

Ultra SCSI is the term used by the SCSI Trade Association (STA) to describe
Fast-20 SCSI, as documented in the SCSI-3 Fast-20 Parallel Interface standard,
X3.277-199X.

Ultra2 SCSI is the term used by the SCSI Trade Association (STA) to describe
Fast-40 SCSI, as documented in the SCSI Parallel Interface–2 standard, (SPI–2)
X3T10/1142D.

Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT

The LSI Logic logo design, TolerANT, LVDlink, and SCRIPTS are registered
trademarks or trademarks of LSI Logic Corporation. All other brand and product
names may be trademarks of their respective companies.

ii

Audience

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Organization

Preface

This book is the primary reference and technical manual for the LSI Logic
Corporation LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction
Controller. It contains a complete functional description for the product
and includes complete physical and electrical specifications.

This document was prepared for system designers and programmers
who are using this device to design an Ultra2 SCSI port for PCI-based
personal computers, workstations, servers or embedded applications.

This document has the following chapters and appendixes:

• Chapter 1, Introduction, describes the general information about the

LSI53C896.

• Chapter 2, Functional Description, describes the main functional

areas of the chip in more detail, including the interfaces to the SCSI
bus and external memory.

• Chapter 3, Signal Descriptions, contains the pin diagram and signal

descriptions.

• Chapter 4, Registers, describes each bit in the operating registers,

and is organized by register address.

• Chapter 5, SCSI SCRIPTS Instruction Set, defines all of the SCSI

SCRIPTS instructions that are supported by the LSI53C896.

• Chapter 6, Specifications, contains the electrical characteristics and

AC timing diagrams.

• Appendix A, Register Summary, is a register summary.

Preface iii

• Appendix B, External Memory Interface Diagram Examples,

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Related Publications

For background information, please contact:

ANSI

11 West 42nd Street
New York, NY 10036
[phone]
Ask for document number X3.131-199X (SCSI-2)

Global Engineering Documents

15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
Ask for document number X3.131-1994 (SCSI-2); X3.253
(SCSI-3 Parallel Interface)

ENDL Publications

14426 Black Walnut Court
Saratoga, CA 95070
[phone]
Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI

Tutor

contains several example interface drawings for connecting the
LSI53C896 to external ROMs.

Prentice Hall

113 Sylvan Avenue
Englewood Cliffs, NJ 07632
[phone]
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding

the Small Computer System Interface

LSI Logic World Wide Web Home Page

www.lsilogic.com
SCSI SCRIPTS™ Processors Programming Guide, Version 2.2,

Order Number S14044.A

iv Preface

PCI Special Interest Group

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2575 N. E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]

Conventions Used in This Manual

The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.

Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.

Revision Record

Revision Date Remarks

0.5 7/97 Advanced Information Data. Contains Signal Descriptions, Registers, and

0.6 10/22/97 First Draft. Added Introduction, Functional Description, SCSI SCRIPTS

1.0 3/11/98 Changes throughout to reflect manual review process and preproduction

2.0 1/18/99 Miscellaneous changes/corrections to reflect product qualification. A table

2.1 4/12/99 Miscellaneous cosmetic/format changes.

3.0 11/99 Final version.

3.1 1/01 All product names changed from SYM to LSI.

3.2 4/01 Changes made to Chapter 6 to DC Characteristics.

Mechanical Drawings.

Instruction Set, Electrical Characteristics, Register Summary, and External
Memory Interface Diagram Examples.

chip revisions.

showing LSI53C896 internal pull-up and pull-downs has been added to
Chapter 3.

Preface v

vi Preface

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Contents

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Chapter 1 Introduction

1.1 General Description 1-1

1.1.1 New Features in the LSI53C896 1-3

1.2 Benefits of Ultra2 SCSI 1-4

1.3 Benefits of LVDlink 1-4

1.4 TolerANT®Technology 1-5

1.5 LSI53C896 Benefits Summary 1-6

1.5.1 SCSI Performance 1-6

1.5.2 PCI Performance 1-7

1.5.3 Integration 1-8

1.5.4 Ease of Use 1-8

1.5.5 Flexibility 1-8

1.5.6 Reliability 1-9

1.5.7 Testability 1-10

Chapter 2 Functional Description

2.1 PCI Functional Description 2-2

2.1.1 PCI Addressing 2-3

2.1.2 PCI Bus Commands and Functions Supported 2-4

2.1.3 Internal Arbiter 2-11

2.1.4 PCI Cache Mode 2-11

2.2 SCSI Functional Description 2-19

2.2.1 SCRIPTS Processor 2-20

2.2.2 Internal SCRIPTS RAM 2-21

2.2.3 64-Bit Addressing in SCRIPTS 2-22

2.2.4 Hardware Control of SCSI Activity LED 2-22

2.2.5 Designing an Ultra2 SCSI System 2-23

2.2.6 Prefetching SCRIPTS Instructions 2-24

2.2.7 Opcode Fetch Burst Capability 2-25

Contents vii

2.2.8 Load/Store Instructions 2-26

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2.2.9 JTAG Boundary Scan Testing 2-26

2.2.10 SCSI Loopback Mode 2-27

2.2.11 Parity Options 2-27

2.2.12 DMA FIFO 2-30

2.2.13 SCSI Bus Interface 2-35

2.2.14 Select/Reselect During Selection/Reselection 2-40

2.2.15 Synchronous Operation 2-40

2.2.16 Interrupt Handling 2-43

2.2.17 Interrupt Routing 2-50

2.2.18 Chained Block Moves 2-52

2.3 Parallel ROM Interface 2-56

2.4 Serial EEPROM Interface 2-58

2.4.1 Default Download Mode 2-58

2.4.2 No Download Mode 2-59

2.5 Power Management 2-59

2.5.1 Power State D0 2-60

2.5.2 Power State D1 2-61

2.5.3 Power State D2 2-61

2.5.4 Power State D3 2-61

Chapter 3 Signal Descriptions

3.1 Internal Pull-ups on LSI53C896 Signals 3-4

3.2 PCI Bus Interface Signals 3-5

3.2.1 System Signals 3-5

3.2.2 Address and Data Signals 3-6

3.2.3 Interface Control Signals 3-7

3.2.4 Arbitration Signals 3-8

3.2.5 Error Reporting Signals 3-9

3.2.6 Interrupt Signals 3-10

3.2.7 SCSI Function A GPIO Signals 3-11

3.2.8 SCSI Function B GPIO Signals 3-12

3.3 SCSI Bus Interface Signals 3-13

3.3.1 SCSI Function A Signals 3-13

3.3.2 SCSI Function B Signals 3-16

3.4 Flash ROM and Memory Interface Signals 3-19

3.5 Test Interface Signals 3-20

viii Contents

3.6 Power and Ground Signals 3-21

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3.7 MAD Bus Programming 3-22

Chapter 4 Registers

4.1 PCI Configuration Registers 4-1

4.2 SCSI Registers 4-19

4.3 64-Bit SCRIPTS Selectors 4-107

4.4 Phase Mismatch Jump Registers 4-111

Chapter 5 SCSI SCRIPTS Instruction Set

5.1 SCSI SCRIPTS 5-1

5.1.1 Sample Operation 5-3

5.2 Block Move Instructions 5-4

5.2.1 First Dword 5-5

5.2.2 Second Dword 5-14

5.2.3 Third Dword 5-14

5.3 I/O Instructions 5-15

5.3.1 First Dword 5-15

5.3.2 Second Dword 5-22

5.4 Read/Write Instructions 5-23

5.4.1 First Dword 5-23

5.4.2 Second Dword 5-24

5.4.3 Read-Modify-Write Cycles 5-24

5.4.4 Move To/From SFBR Cycles 5-24

5.5 Transfer Control Instructions 5-26

5.5.1 First Dword 5-27

5.5.2 Second Dword 5-33

5.5.3 Third Dword 5-33

5.6 Memory Move Instructions 5-34

5.6.1 First Dword 5-35

5.6.2 Read/Write System Memory from a SCRIPTS 5-35

5.6.3 Second Dword 5-36

5.6.4 Third Dword 5-37

5.7 Load/Store Instructions 5-37

5.7.1 First Dword 5-38

5.7.2 Second Dword 5-40

Contents ix

Chapter 6 Specifications

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6.1 DC Characteristics 6-1

6.2 TolerANT Technology Electrical Characteristics 6-8

6.3 AC Characteristics 6-11

6.4 PCI and External Memory Interface Timing Diagrams 6-14

6.4.1 Target Timing 6-15

6.4.2 Initiator Timing 6-22

6.4.3 External Memory Timing 6-39

6.5 SCSI Timing Diagrams 6-60

6.6 Package Drawings 6-67

Appendix A Register Summary

Appendix B External Memory Interface Diagram Examples

Index

Customer Feedback

Figures

1.1 Typical LSI53C896 System Application 1-2

1.2 Typical LSI53C896 Board Application 1-3

2.1 LSI53C896 Block Diagram 2-2

2.2 Parity Checking/Generation 2-30

2.3 DMA FIFO Sections 2-31

2.4 LSI53C896 Host Interface SCSI Data Paths 2-32

2.5 8-Bit HVD Wiring Diagram for Ultra SCSI 2-37

2.6 Regulated Termination for Ultra2 SCSI 2-39

2.7 Determining the Synchronous Transfer Rate 2-41

2.8 Interrupt Routing Hardware Using the LSI53C896 2-51

2.9 Block Move and Chained Block Move Instructions 2-53

3.1 LSI53C896 Functional Signal Grouping 3-2

5.1 SCRIPTS Overview 5-4

5.2 Block Move Instruction - First Dword 5-5

5.3 Block Move Instruction - Second Dword 5-14

x Contents

5.4 Block Move Instruction - Third Dword 5-14

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5.5 First 32-Bit Word of the I/O Instruction 5-15

5.6 Second 32-Bit Word of the I/O Instruction 5-22

5.7 Read/Write Instruction - First Dword 5-23

5.8 Read/Write Instruction - Second Dword 5-24

5.9 Transfer Control Instructions - First Dword 5-27

5.10 Transfer Control Instructions - Second Dword 5-33

5.11 Transfer Control Instructions - Third Dword 5-33

5.12 Memory Move Instructions - First Dword 5-35

5.13 Memory Move Instructions - Second Dword 5-36

5.14 Memory Move Instructions - Third Dword 5-37

5.15 Load/Store Instruction - First Dword 5-38

5.16 Load/Store Instructions - Second Dword 5-40

6.1 LVD Driver 6-3

6.2 LVD Receiver 6-4

6.3 Rise and Fall Time Test Condition 6-9

6.4 SCSI Input Filtering 6-9

6.5 Hysteresis of SCSI Receivers 6-10

6.6 Input Current as a Function of Input Voltage 6-10

6.7 Output Current as a Function of Output Voltage 6-11

6.8 External Clock 6-12

6.9 Reset Input 6-13

6.10 Interrupt Output 6-14

6.11 PCI Configuration Register Read 6-16

6.12 PCI Configuration Register Write 6-17

6.13 Operating Registers/SCRIPTS RAM Read, 32-Bit 6-18

6.14 Operating Register/SCRIPTS RAM Read, 64-Bit 6-19

6.15 Operating Register/SCRIPTS RAM Write, 32-Bit 6-20

6.16 Operating Register/SCRIPTS RAM Write, 64-Bit 6-21

6.17 Nonburst Opcode Fetch, 32-Bit Address and Data 6-23

6.18 Burst Opcode Fetch, 32-Bit Address and Data 6-25

6.19 Back to Back Read, 32-Bit Address and Data 6-27

6.20 Back to Back Write, 32-Bit Address and Data 6-29

6.21 Burst Read, 32-Bit Address and Data 6-31

6.22 Burst Read, 64-Bit Address and Data 6-33

6.23 Burst Write, 32-Bit Address and Data 6-35

6.24 Burst Write, 64-Bit Address and Data 6-37

6.25 External Memory Read 6-40

Contents xi

6.26 External Memory Write 6-44

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6.27 Normal/Fast Memory (≥ 128 Kbytes) Single Byte
Access Read Cycle 6-46

6.28 Normal/Fast Memory (≥ 128 Kbytes) Single Byte
Access Write Cycle 6-48

6.29 Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte
Access Read Cycle 6-50

6.30 Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte
Access Write Cycle 6-52

6.31 Slow Memory (≥ 128 Kbytes) Read Cycle 6-54

6.32 Slow Memory (≥ 128 Kbytes) Write Cycle 6-56

6.33 ≤ 64 Kbytes ROM Read Cycle 6-58

6.34 ≤ 64 Kbytes ROM Write Cycle 6-59

6.35 Initiator Asynchronous Send 6-60

6.36 Initiator Asynchronous Receive 6-61

6.37 Target Asynchronous Send 6-61

6.38 Target Asynchronous Receive 6-62

6.39 Initiator and Target Synchronous Transfer 6-66

6.40 LSI53C896 329 BGA (Bottom View) 6-70

6.41 LSI53C896 329 BGA Mechanical Drawing 6-71

B.1 16 Kbyte Interface with 200 ns Memory B-1
B.2 64 Kbyte Interface with 150 ns Memory B-2
B.3 128, 256, 512 Kbyte or 1 Mbyte Interface with

150 ns Memory B-3

B.4 512 Kbyte Interface with 150 ns Memory B-4

Tables

2.1 PCI Bus Commands and Encoding Types for the
LSI53C896 2-5

2.2 PCI Cache Mode Alignment 2-14

2.3 Bits Used for Parity Control and Generation 2-28

2.4 SCSI Parity Control 2-29

2.5 SCSI Parity Errors and Interrupts 2-29

2.6 HVD Signals 2-36

2.7 Parallel ROM Support 2-57

2.8 Mode A Serial EEPROM Data Format 2-59

2.9 Power States 2-60

3.1 LSI53C896 Internal Pull-ups and Pull-downs 3-4

xii Contents

3.2 System Signals 3-5

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3.3 Address and Data Signals 3-6

3.4 Interface Control Signals 3-7

3.5 Arbitration Signals 3-8

3.6 Error Reporting Signals 3-9

3.7 Interrupt Signals 3-10

3.8 SCSI Function A GPIO Signals 3-11

3.9 SCSI Function B GPIO Signals 3-12

3.10 SCSI Bus Interface Signals 3-13

3.11 SCSI Function A Signals 3-14

3.12 SCSI Function A_SCTRL Signals 3-15

3.13 SCSI Function B Signals 3-16

3.14 SCSI Function B_SCRTL Signals 3-18

3.15 Flash ROM and Memory Interface Signals 3-19

3.16 Test Interface Signals 3-20

3.17 Power and Ground Signals 3-21

3.18 Decode of MAD[3:1] Pins 3-23

4.1 PCI Configuration Register Map 4-2

4.2 SCSI Register Map 4-20

4.3 Examples of Synchronous Transfer Periods and
Rates for SCSI-1 4-34

4.4 Example Transfer Periods and Rates for Fast SCSI-2,
Ultra, and Ultra2 4-35

4.5 Maximum Synchronous Offset 4-36

4.6 SCSI Synchronous Data FIFO Word Count 4-46

5.1 Read/Write Instructions 5-25

6.1 Absolute Maximum Stress Ratings 6-2

6.2 Operating Conditions 6-2

6.3 LVD Driver SCSI Signals—SD[15:0], SDP[1:0], SREQ/,
SREQ2/, SACK/, SACK2/, SMSG/, SIO/, SCD/, SATN/,
SBSY/, SSEL/, SRST/ 6-3

6.4 LVD Receiver SCSI Signals—SD[15:0], SDP[1:0],
SREQ/, SREQ2/, SACK/, SACK2/, SMSG/, SIO/,
SCD/, SATN/, SBSY/, SSEL/, SRST/ 6-3

6.5 A and B DIFFSENS SCSI Signals 6-4

6.6 Input Capacitance 6-4

6.7 Bidirectional Signals—GPIO0_FETCH/,
GPIO1_MASTER/, GPIO2, GPIO3, GPIO4, MAD[7:0] 6-5

Contents xiii

6.8 Output Signals—MAS/[1:0], MCE/, MOE/_TESTOUT,

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MWE/, TDO 6-5

6.9 Bidirectional Signals—AD[63:0], C_BE[7:0]/, FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR, PAR64,
REQ64/, ACK64/ 6-6

6.10 Input Signals—CLK, GNT/, IDSEL, INT_DIR, RST/,
SCLK, TCK, TDI, TEST_HSC, TEST_RST/, TMS 6-6

6.11 Output Signals—INTA, INTB, ALT_INTA, ALT_INTB,
REQ/ 6-7

6.12 Output Signal—SERR/ 6-7

6.13 TolerANT Technology Electrical Characteristics for SE
SCSI Signals 6-8

6.14 External Clock 6-12

6.15 Reset Input 6-13

6.16 Interrupt Output 6-14

6.17 PCI Configuration Register Read 6-16

6.18 PCI Configuration Register Write 6-17

6.19 Operating Register/SCRIPTS RAM Read, 32-Bit 6-18

6.20 Operating Register/SCRIPTS RAM Read, 64-Bit 6-19

6.21 Operating Register/SCRIPTS RAM Write, 32-Bit 6-20

6.22 Operating Register/SCRIPTS RAM Write, 64-Bit 6-21

6.23 Nonburst Opcode Fetch, 32-Bit Address and Data 6-22

6.24 Burst Opcode Fetch, 32-Bit Address and Data 6-24

6.25 Back to Back Read, 32-Bit Address and Data 6-26

6.26 Back to Back Write, 32-Bit Address and Data 6-28

6.27 Burst Read, 32-Bit Address and Data 6-30

6.28 Burst Read, 64-Bit Address and Data 6-32

6.29 Burst Write, 32-Bit Address and Data 6-34

6.30 Burst Write, 64-Bit Address and Data 6-36

6.31 External Memory Read 6-39

6.32 External Memory Write 6-43

6.33 Normal/Fast Memory (≥ 128 Kbytes) Single Byte
Access Read Cycle 6-46

6.34 Normal/Fast Memory (≥ 128 Kbytes) Single Byte
Access Write Cycle 6-48

6.35 Slow Memory (≥ 128 Kbytes) Read Cycle 6-54

6.36 Slow Memory (≥ 128 Kbytes) Write Cycle 6-56

6.37 ≤ 64 Kbytes ROM Read Cycle 6-58

xiv Contents

6.38 ≤ 64 Kbytes ROM Write Cycle 6-59

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6.39 Initiator Asynchronous Send 6-60

6.40 Initiator Asynchronous Receive 6-61

6.41 Target Asynchronous Send 6-61

6.42 Target Asynchronous Receive 6-62

6.43 SCSI-1 Transfers (SE 5.0 Mbytes) 6-63

6.44 SCSI-1 Transfers (Differential 4.17 Mbytes) 6-63

6.45 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or

20.0 Mbytes (16-Bit Transfers) 40 MHz Clock 6-64

6.46 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or

20.0 Mbytes (16-Bit Transfers) 50 MHz Clock 6-64

6.47 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers)
or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz
Clock 6-65

6.48 Ultra SCSI HVD Transfers 20.0 Mbytes (8-Bit Transfers)
or 40.0 Mbytes (16-Bit Transfers) 80 MHz Clock 6-65

6.49 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or

80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock 6-66

6.50 Signal Names and BGA Position 6-68

6.51 Signal Names by BGA Position 6-69

A.1 LSI53C896 Register Map A-1

Contents xv

xvi Contents

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Chapter 1

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Introduction

This chapter provides a general overview of the LSI53C896 PCI to Dual
Channel Ultra2 SCSI Multifunction Controller. The chapter contains the
following sections:

• Section 1.1, “General Description”

• Section 1.2, “Benefits of Ultra2 SCSI”

• Section 1.3, “Benefits of L VDlink”

• Section 1.4, “TolerANT

• Section 1.5, “LSI53C896 Benefits Summary”

1.1 General Description

®

Technology”

The LSI53C896 brings Ultra2 SCSI performance to host adapter,
workstation, and general computer designs, making it easy to add a
high-performance SCSI bus to any PCI system. It supports Ultra2 SCSI
transfer rates and allows increased SCSI connectivity and cable length
with Low Voltage Differential (LVD) signaling for SCSI devices.

The LSI53C896 has a local memory bus for local storage of the device’s
BIOS ROM in flash memory or standard EPROMs. The LSI53C896
supports programming of local flash memory for updates to BIOS. The
chip is packaged in a 329 Ball Grid Array (BGA) package. System
diagrams showing the connections of the LSI53C896 with an external
ROM or flash memory are shown in Appendix B, “External Memory

Interface Diagram Examples. ”

LVDlink™ technology is the LSI Logic implementation of LVD. LVDlink
transceivers allow the LSI53C896 to perform either Single-Ended (SE) or
LVD transfers, and support external High Voltage Differential (HVD)
transceivers. The LSI53C896 integrates a high-performance SCSI core,
a 64-bit PCI bus master DMA core, and the LSI Logic SCSI SCRIPTS™

LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller 1-1

processor to meet the flexibility requirements of SCSI-3 and Ultra2 SCSI

*

standards. It is designed to implement multithreaded I/O algorithms with
a minimum of processor intervention, solving the protocol overhead
problems of previous intelligent and nonintelligent adapter designs.

Figure 1.1 illustrates a typical LSI53C896 system and Figure 1.2

illustrates a typical LSI53C896 board application.

Figure 1.1 Typical LSI53C896 System Application

PCI Bus

Interface

Controller

Processor Bus

Central

Processing

Unit

(CPU)

Typical PCI Computer

System Architecture

LSI53C896 PCI

to Wide Ultra2 SCSI

Function A

and

LSI53C896 PCI

to Wide Ultra2 SCSI

Function B

One PCI Bus Load

PCI Graphic Accelerator

PCI Fast Ethernet

Memory

Controller

Memory

SCSI Bus

SCSI Bus

Fixed Disk, Optical Disk,

Printer, Tape, and Other

Peripherals

Fixed Disk, Optical Disk,

Printer, Tape, and Other

Peripherals

1-2 Introduction

Figure 1.2 Typical LSI53C896 Board Application

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SCSI Data,

Function A

68 Pin

Wide SCSI

Connector

Function B

68 Pin

Wide SCSI

Connector

Parity, and

Control Signals

LSI53C896

64-Bit PCI

SCSI Data,

Parity, and

Control Signals

PCI Address, Data, Parity and Control Signals

Dual Channel SCSI

to

Controller

PCI Interface

1.1.1 New Features in the LSI53C896

The LSI53C896 is functionally similar to the LSI53C876 PCI to Dual
Channel SCSI Multifunction Controller, with added support for Ultra2
SCSI. Some software enhancements, and the use of LVD, are needed to
enable the chip to transfer data at Ultra2 SCSI transfer rates.

Memory

Address/Data

Bus

A_GPIO/[1:0]

B_GPIO/[1:0]

Memory Control

Block

Flash EEPROM

Serial EEPROM

Function A

Serial EEPROM

Function B

• 64-bit PCI Interface.

• Able to handle SCSI phase mismatches in SCRIPTS without

interrupting the CPU.

• Two wide Ultra2 SCSI channels in a single package.

• Separate 8 Kbyte internal SCRIPTS RAMs.

• JTAG boundary scanning.

• RAID ready alternative interrupt signaling.

• PC99 Power Management - including automatic download of

Subsystem Vendor ID and Subsystem ID, and PCI power
management levels D0, D1, D2, and D3.

General Description 1-3

• Improved PCI Caching design - improves PCI bus efficiency.

*

• Load/Store data transferred to or from SCRIPTS RAM internal to

chip.

• Hardware control of SCSI activity LED.

• Optional 944 byte DMA FIFO supports large block transfers at Ultra2

SCSI speeds. The default FIFO size of 112 bytes is also supported.

• 32-bit ISTAT registers (Interrupt Status Zero (ISTAT0), Interrupt Status

One (ISTAT1), Mailbox Zero (MBOX0), and Mailbox One (MBOX1)).

1.2 Benefits of Ultra2 SCSI

Ultra2 SCSI is an extension of the SPI-2 draft standard that allows faster
synchronous SCSI transfer rates and defines a new physical layer, LVD
SCSI, that provides an incremental evolution from SCSI-2 and Ultra
SCSI. When enabled, Ultra2 SCSI performs 40 mega transfers per
second, which results in approximately double the synchronous transfer
rates of Ultra SCSI. The LSI53C896 can perform 16-bit, Ultra2 SCSI
synchronous transfers as fast as 80 Mbytes/s on each channel for a total
bandwidth of 160 Mbytes/s. This advantage is most noticeable in heavily
loaded systems, or large block size applications such as video
on-demand and image processing.

An advantage of Ultra2 SCSI is that it significantly improves SCSI
bandwidth while preserving existing hardware and software investments.
The primary software changes required are to enable the chip to perform
synchronous negotiations for Ultra2 SCSI rates, and to enable the clock
quadrupler. Ultra2 SCSI uses the same connectors as Ultra SCSI, but
can operate with longer cables and more devices on the bus. Chapter 2,

“Functional Description,” contains more information on migrating an Ultra

SCSI design to an Ultra2 SCSI design.

1.3 Benefits of LVDlink

The LSI53C896 supports LVD for SCSI, a signaling technology that
increases the reliability of SCSI data transfers over longer distances than
are supported by SE SCSI. The low current output of LVD allows the I/O
transceivers to be integrated directly onto the chip. LVD provides the

1-4 Introduction

reliability of HVD SCSI without the added cost of external differential

*

transceivers. Ultra2 SCSI with LVD allows a longer SCSI cable and more
devices on the bus, with the same cables defined in the SCSI-3 Parallel
Interface standard for Fast-20 (Ultra SCSI). LVD provides a long-term
migration path to even faster SCSI transfer rates without compromising
signal integrity, cable length, or connectivity.

For backward compatibility to existing SE devices, the LSI53C896
features universal LVDlink transceivers that can support LVD SCSI, SE,
and HVD modes. The LVDlink technology also supports HVD signaling
in legacy systems, when external transceivers are connected to the
LSI53C896. This allows the LSI53C896 to be used in both legacy and
Ultra2 SCSI applications.

1.4 TolerANT®Technology

The LSI53C896 features TolerANT technology, which includes active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation causes the SCSI Request, Acknowledge,
Data, and Parity signals to be actively driven HIGH rather than passively
pulled up by terminators. Active negation is enabled by setting bit 7 in
the SCSI T est Three (STEST3) register.

TolerANT receiver technology improves data integrity in unreliable
cabling environments, where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions, without the long signal delay associated with
RC-type input filters. This improved driver and receiver technology helps
eliminate double clocking of data, the single biggest reliability issue with
SCSI operations. TolerANT input signal filtering is a built-in feature of the
LSI53C896 and all LSI Logic fast SCSI, Ultra SCSI, and Ultra2 SCSI
devices.

The benefits of TolerANT technology include increased immunity to noise
when the signal is going HIGH, better performance due to balanced duty
cycles, and improvedfast SCSI transfer rates.Inaddition,TolerANT SCSI
devices do not cause glitches on the SCSI bus at power-up or
power-down, so other devices on the bus are also protected from data
corruption. When it is used with the LVDlink transceivers, TolerANT
technology provides excellent signal quality and data reliability in real

TolerANT®Technology 1-5

world cabling environments. TolerANT technology is compatible with both

*

the Alternative One and Alternative Two termination schemes proposed
by the American National Standards Institute.

1.5 LSI53C896 Benefits Summary

This section provides an overview of the LSI53C896 features and
benefits. It contains information on SCSI Performance, PCI Performance,

Integration, Ease of Use, Flexibility, Reliability, and Testability.

1.5.1 SCSI Performance

• Has integrated LVDlink universal transceivers which:

– Support SE, LVD, and HVD signals (with external transceivers).
– Allow greater device connectivity and longer cable length.
– LVDlink transceivers save the cost of external differential

transceivers.

– Supports a long-term performance migration path.

• With a 944 byte FIFO, the chip can efficiently burst up to 512 bytes

across the PCI bus.

• Two separate SCSI channels on one chip.

• Performs wide, Ultra2 SCSI synchronous transfers as fast as

80 Mbytes/s on each SCSI channel for a total of 160 Mbytes/s.

• Can handle phase mismatches in SCRIPTS without interrupting the

system processor.

• On-chip SCSI clock quadrupler allows the chip to achieve Ultra2

SCSI transfer rates with an input frequency of 40 MHz.

• Includes 8 Kbytes of internal RAM for SCRIPTS instruction storage

for each SCSI channel.

• 31 levels of SCSI synchronous offset.

• Supports variable block size and scatter/gather data transfers.

• Performs sustained memory-to-memory DMA transfers to

approximately 100 Mbytes/s.

• Minimizes SCSI I/O start latency.

1-6 Introduction

• Performs complex bus sequences without interrupts, including

*

restoring data pointers.

• Reduces ISR overhead through a unique interrupt status reporting

method.

• Load/Store SCRIPTS instructions increase performance of data

transfers to and from the chip registers without using PCI cycles.

• SCRIPTS support of 64-bit addressing.

• Supports target disconnect and later reconnect with no interrupt to

the system processor.

• Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast

I/O context switching.

• Expanded Register Move instruction supports additional arithmetic

capability.

1.5.2 PCI Performance

• Complies with the PCI 2.1 specification.

• 64-bit or 32-bit 33 MHz PCI interface.

– Dual Address Cycle (DAC) can be generated for all SCRIPTS.
– True PCI Multifunction Device - presents one electrical load to

the PCI Bus.

• Bursts 2/4, 4/8, 8/16, 16/32, 32/64, or 64/128 Qword/Dword transfers

across the PCI bus.

• Supports 64-bit or 32-bit word data bursts with variable burst lengths.

• Prefetches up to 8 Dwords of SCRIPTS instructions.

• Bursts SCRIPTS opcode fetches across the PCI bus.

• Performs zero wait-state bus master data bursts up to 264 Mbytes/s

(@ 33 MHz).

• Supports PCI Cache Line Size register.

• Supports PCI Write and Invalidate, Read Line, and Read Multiple

commands.

• Complies with PCI Bus Power Management Specification

Revision 1.1.

LSI53C896 Benefits Summary 1-7

1.5.3 Integration

*

• Dual channel Ultra2 SCSI PCI Multifunction controller.

• Integrated LVD transceivers.

• Full 64-bit or 32-bit PCI DMA bus master.

• Can be used as a third-party PCI bus DMA controller by using

• Integrated SCRIPTS processor.

1.5.4 Ease of Use

• Up to one megabyte of add-in memory support for BIOS and

• Direct PCI to SCSI connection.

• Reduced SCSI development effort.

• Compiler-compatible with existing LSI53C7XX and LSI53C8XX

• Direct connection to PCI and SCSI SE, LVD and HVD (needs

• Development tools and sample SCSI SCRIPTS available.

Memory-to-Memory Move instructions.

SCRIPTS storage.

family SCRIPTS.

external transceivers).

• Maskable and pollable interrupts.

• Wide SCSI, A or P cable, and up to 15 devices per SCSI channel

supported.

• Three programmable SCSI timers: Select/Reselect,

Handshake-to-Handshake, and General Purpose. The time-out
period is programmable from 100 µs to greater than 25.6 seconds.

• Software for PC-based operating system support.

• Support for relative jumps.

• SCSI Selected As ID bits for responding with multiple IDs.

1.5.5 Flexibility

• Universal LVD transceivers are backward compatible with SE or HVD

devices.

• High level programming interface (SCSI SCRIPTS).

1-8 Introduction

1.5.6 Reliability

*

• Programs local and bus flash memory.

• Selectable 112 or 944 byte DMA FIFO for backward compatibility.

• Tailored SCSI sequences execute from main system RAM or internal

SCRIPTS RAM.

• Flexible programming interface to tune I/O performance or to adapt

to unique SCSI devices.

• Support for changes in the logical I/O interface definition.

• Low level access to all registers and all SCSI bus signals.

• Fetch, Master, and Memory Access control pins.

• Separate SCSI and system clocks.

• SCSI clock quadrupler bits enable Ultra2 SCSI transfer rates with a

40 MHz SCSI clock input.

• Selectable IRQ pin disable bit.

• Ability to route system clock to SCSI clock.

• Compatible with 3.3 V and 5 V PCI.

• 2 kV ESD protection on SCSI signals.

• Protection against bus reflections due to impedance mismatches.

• Controlled bus assertion times (reduces RFI, improves reliability,and

eases FCC certification).

• Latch-up protection greater than 150 mA.

• Voltage feed-through protection (minimum leakage current through

SCSI pads).

• More than 25% of pins are power and ground.

• Power and ground isolation of I/O pads and internal chip logic.

• TolerANT technology provides:

– Active negation of SCSI Data, Parity, Request, and Acknowledge

signals for improved fast SCSI transfer rates.

– Input signal filtering on SCSI receivers improves data integrity,

even in noisy cabling environments.

LSI53C896 Benefits Summary 1-9

1.5.7 Testability

*

• All SCSI signals accessible through programmed I/O.

• SCSI loopback diagnostics.

• SCSI bus signal continuity checking.

• Support for single step mode operation.

• JTAG boundary scan.

1-10 Introduction

Chapter 2

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Functional Description

Chapter 2 is divided into the following sections:

• Section 2.1, “PCI Functional Description”

• Section 2.2, “SCSI Functional Description”

• Section 2.3, “Parallel ROM Interface”

• Section 2.4, “Serial EEPROM Interface”

• Section 2.5, “Power Management”

The LSI53C896 is composed of the following modules:

• 64-bit PCI Interface.

• Two independent PCI-to-Wide Ultra2 SCSI Controllers.

• ROM/Flash Memory Controller.

• Serial EEPROM Controller.

Figure 2.1 illustrates the relationship between these modules.

LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller 2-1

Figure 2.1 LSI53C896 Block Diagram

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64-Bit PCI Interface, PCI Configuration Registers (2 sets)

PCI Bus

Wide Ultra2 SCSI Controller

8 Kbyte

SCRIPTS RAM

944 Byte

DMA FIFO

SCSI FIFO and SCSI Control Block

JTAG

JTAG

Bus

8 Dword SCRIPTS

Prefetch Buffer

Registers

Processor

SCSI SCRIPTS

Universal TolerANT

Drivers and Receivers

SCSI Function A

Wide Ultra2

SCSI Bus

Operating

Local

Memory

ROM/Flash

Memory

Bus

ROM/Flash Memory Control

Bus

2-Wire Serial

EEPROM Bus

(Function A)

SCRIPTS RAM

and Autoconfiguration

Serial EEPROM Controller

Wide Ultra2 SCSI Controller

8 Kbyte

Registers

Operating

SCSI FIFO and SCSI Control Block

2-Wire Serial

EEPROM Bus

(Function B)

8 Dword SCRIPTS

Prefetch Buffer

Processor

SCSI SCRIPTS

Universal TolerANT

Drivers and Receivers

SCSI Function B

Wide Ultra2

SCSI Bus

944 Byte

DMA FIFO

2.1 PCI Functional Description

The LSI53C896 implements two PCI-to-Wide Ultra2 SCSI controllers in
a single package. This configuration presents only one load to the PCI
bus and uses one REQ/ - GNT/ pair to arbitrate for PCI bus mastership.
However, separate interrupt signals are generated for SCSI Function A
and SCSI Function B.

2-2 Functional Description

2.1.1 PCI Addressing

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There are three physical PCI-defined address spaces:

• PCI Configuration Space.

• I/O Space for operating registers.

• Memory Space for operating registers.

2.1.1.1 Configuration Space

The host processor uses this configuration space to initialize the
LSI53C896. Two independent sets of configuration space registers are
defined, one set for each SCSI function. The Configuration registers are
accessible only by system BIOS during PCI configuration cycles. Each
configuration space is a contiguous 256 X 8-bit set of addresses.
Decoding C_BE[3:0]/ determines if a PCI cycle is intended to access the
configuration register space. The IDSEL bus signal is a “chip select” that
allows access to the configuration register space only. A configuration
read/write cycle without IDSEL is ignored. The eight lower order address
bits (AD[7:0]) are used to select a specific 8-bit register. Since the
LSI53C896 is a PCI multifunction device, bits AD[10:8] decode either
SCSI Function A Configuration register (AD[10:8] = 0b000) or SCSI
Function B Configuration register (AD[10:8] = 0b001).

At initialization time, each PCI device is assigned a base address (in the
case of the LSI53C896, the upper 24 bits of the address are selected)
for memory accesses and I/O accesses. On every access, the
LSI53C896 compares its assigned base addresses with the value on the
Address/Data bus during the PCI address phase. If there is a match of
the upper 24 bits, the access is for the LSI53C896 and the low-order
eight bits define the register to be accessed. A decode of C_BE[3:0]/
determines which registers and what type of access is to be performed.

2.1.1.2 I/O Space

The PCI specification defines I/O space as a contiguous 32-bit I/O
address that is shared by all system resources, including the LSI53C896.

Base Address Register Zero (I/O) determines which 256-byte I/O area

this device occupies.

PCI Functional Description 2-3

2.1.1.3 Memory Space

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The PCI specification defines memory space as a contiguous 64-bit
memory address that is shared by all system resources, including the
LSI53C896. Base Address Register One (MEMORY) determines which
1 Kbyte memory area this device occupies. Each SCSI function uses a
8 Kbyte SCRIPTS RAM memory space.Base Address Register Two

(SCRIPTS RAM) determines the 8 Kbyte memory area the SCRIPTS

RAM occupies.

2.1.2 PCI Bus Commands and Functions Supported

Bus commands indicate to the target the type of transaction the master
is requesting. Bus commands are encoded on the C_BE[3:0]/ lines
during the address phase. PCI bus commands and encoding types
appear in Table 2.1.

2-4 Functional Description