LSI LSI53C896 Technical Manual

TECHNICAL

*

MANUAL

LSI53C896
PCI to Dual Channel
Ultra2 SCSI
Multifunction Controller

Version 3.2

April 2001

®

This document contains proprietary information of LSI Logic Corporation. The

*

information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.

Document DB14-000083-03, Fourth Edition (April 2001)
This document describes the LSI Logic LSI53C896 PCI to Dual Channel Ultra2
SCSI Multifunction Controller and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.

To receive product literature, visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.

Ultra SCSI is the term used by the SCSI Trade Association (STA) to describe
Fast-20 SCSI, as documented in the SCSI-3 Fast-20 Parallel Interface standard,
X3.277-199X.

Ultra2 SCSI is the term used by the SCSI Trade Association (STA) to describe
Fast-40 SCSI, as documented in the SCSI Parallel Interface–2 standard, (SPI–2)
X3T10/1142D.

Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT

The LSI Logic logo design, TolerANT, LVDlink, and SCRIPTS are registered
trademarks or trademarks of LSI Logic Corporation. All other brand and product
names may be trademarks of their respective companies.

ii

Audience

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Organization

Preface

This book is the primary reference and technical manual for the LSI Logic
Corporation LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction
Controller. It contains a complete functional description for the product
and includes complete physical and electrical specifications.

This document was prepared for system designers and programmers
who are using this device to design an Ultra2 SCSI port for PCI-based
personal computers, workstations, servers or embedded applications.

This document has the following chapters and appendixes:

• Chapter 1, Introduction, describes the general information about the

LSI53C896.

• Chapter 2, Functional Description, describes the main functional

areas of the chip in more detail, including the interfaces to the SCSI
bus and external memory.

• Chapter 3, Signal Descriptions, contains the pin diagram and signal

descriptions.

• Chapter 4, Registers, describes each bit in the operating registers,

and is organized by register address.

• Chapter 5, SCSI SCRIPTS Instruction Set, defines all of the SCSI

SCRIPTS instructions that are supported by the LSI53C896.

• Chapter 6, Specifications, contains the electrical characteristics and

AC timing diagrams.

• Appendix A, Register Summary, is a register summary.

Preface iii

• Appendix B, External Memory Interface Diagram Examples,

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Related Publications

For background information, please contact:

ANSI

11 West 42nd Street
New York, NY 10036
[phone]
Ask for document number X3.131-199X (SCSI-2)

Global Engineering Documents

15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
Ask for document number X3.131-1994 (SCSI-2); X3.253
(SCSI-3 Parallel Interface)

ENDL Publications

14426 Black Walnut Court
Saratoga, CA 95070
[phone]
Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI

Tutor

contains several example interface drawings for connecting the
LSI53C896 to external ROMs.

Prentice Hall

113 Sylvan Avenue
Englewood Cliffs, NJ 07632
[phone]
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding

the Small Computer System Interface

LSI Logic World Wide Web Home Page

www.lsilogic.com
SCSI SCRIPTS™ Processors Programming Guide, Version 2.2,

Order Number S14044.A

iv Preface

PCI Special Interest Group

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2575 N. E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]

Conventions Used in This Manual

The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.

Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.

Revision Record

Revision Date Remarks

0.5 7/97 Advanced Information Data. Contains Signal Descriptions, Registers, and

0.6 10/22/97 First Draft. Added Introduction, Functional Description, SCSI SCRIPTS

1.0 3/11/98 Changes throughout to reflect manual review process and preproduction

2.0 1/18/99 Miscellaneous changes/corrections to reflect product qualification. A table

2.1 4/12/99 Miscellaneous cosmetic/format changes.

3.0 11/99 Final version.

3.1 1/01 All product names changed from SYM to LSI.

3.2 4/01 Changes made to Chapter 6 to DC Characteristics.

Mechanical Drawings.

Instruction Set, Electrical Characteristics, Register Summary, and External
Memory Interface Diagram Examples.

chip revisions.

showing LSI53C896 internal pull-up and pull-downs has been added to
Chapter 3.

Preface v

vi Preface

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Contents

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Chapter 1 Introduction

1.1 General Description 1-1

1.1.1 New Features in the LSI53C896 1-3

1.2 Benefits of Ultra2 SCSI 1-4

1.3 Benefits of LVDlink 1-4

1.4 TolerANT®Technology 1-5

1.5 LSI53C896 Benefits Summary 1-6

1.5.1 SCSI Performance 1-6

1.5.2 PCI Performance 1-7

1.5.3 Integration 1-8

1.5.4 Ease of Use 1-8

1.5.5 Flexibility 1-8

1.5.6 Reliability 1-9

1.5.7 Testability 1-10

Chapter 2 Functional Description

2.1 PCI Functional Description 2-2

2.1.1 PCI Addressing 2-3

2.1.2 PCI Bus Commands and Functions Supported 2-4

2.1.3 Internal Arbiter 2-11

2.1.4 PCI Cache Mode 2-11

2.2 SCSI Functional Description 2-19

2.2.1 SCRIPTS Processor 2-20

2.2.2 Internal SCRIPTS RAM 2-21

2.2.3 64-Bit Addressing in SCRIPTS 2-22

2.2.4 Hardware Control of SCSI Activity LED 2-22

2.2.5 Designing an Ultra2 SCSI System 2-23

2.2.6 Prefetching SCRIPTS Instructions 2-24

2.2.7 Opcode Fetch Burst Capability 2-25

Contents vii

2.2.8 Load/Store Instructions 2-26

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2.2.9 JTAG Boundary Scan Testing 2-26

2.2.10 SCSI Loopback Mode 2-27

2.2.11 Parity Options 2-27

2.2.12 DMA FIFO 2-30

2.2.13 SCSI Bus Interface 2-35

2.2.14 Select/Reselect During Selection/Reselection 2-40

2.2.15 Synchronous Operation 2-40

2.2.16 Interrupt Handling 2-43

2.2.17 Interrupt Routing 2-50

2.2.18 Chained Block Moves 2-52

2.3 Parallel ROM Interface 2-56

2.4 Serial EEPROM Interface 2-58

2.4.1 Default Download Mode 2-58

2.4.2 No Download Mode 2-59

2.5 Power Management 2-59

2.5.1 Power State D0 2-60

2.5.2 Power State D1 2-61

2.5.3 Power State D2 2-61

2.5.4 Power State D3 2-61

Chapter 3 Signal Descriptions

3.1 Internal Pull-ups on LSI53C896 Signals 3-4

3.2 PCI Bus Interface Signals 3-5

3.2.1 System Signals 3-5

3.2.2 Address and Data Signals 3-6

3.2.3 Interface Control Signals 3-7

3.2.4 Arbitration Signals 3-8

3.2.5 Error Reporting Signals 3-9

3.2.6 Interrupt Signals 3-10

3.2.7 SCSI Function A GPIO Signals 3-11

3.2.8 SCSI Function B GPIO Signals 3-12

3.3 SCSI Bus Interface Signals 3-13

3.3.1 SCSI Function A Signals 3-13

3.3.2 SCSI Function B Signals 3-16

3.4 Flash ROM and Memory Interface Signals 3-19

3.5 Test Interface Signals 3-20

viii Contents

3.6 Power and Ground Signals 3-21

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3.7 MAD Bus Programming 3-22

Chapter 4 Registers

4.1 PCI Configuration Registers 4-1

4.2 SCSI Registers 4-19

4.3 64-Bit SCRIPTS Selectors 4-107

4.4 Phase Mismatch Jump Registers 4-111

Chapter 5 SCSI SCRIPTS Instruction Set

5.1 SCSI SCRIPTS 5-1

5.1.1 Sample Operation 5-3

5.2 Block Move Instructions 5-4

5.2.1 First Dword 5-5

5.2.2 Second Dword 5-14

5.2.3 Third Dword 5-14

5.3 I/O Instructions 5-15

5.3.1 First Dword 5-15

5.3.2 Second Dword 5-22

5.4 Read/Write Instructions 5-23

5.4.1 First Dword 5-23

5.4.2 Second Dword 5-24

5.4.3 Read-Modify-Write Cycles 5-24

5.4.4 Move To/From SFBR Cycles 5-24

5.5 Transfer Control Instructions 5-26

5.5.1 First Dword 5-27

5.5.2 Second Dword 5-33

5.5.3 Third Dword 5-33

5.6 Memory Move Instructions 5-34

5.6.1 First Dword 5-35

5.6.2 Read/Write System Memory from a SCRIPTS 5-35

5.6.3 Second Dword 5-36

5.6.4 Third Dword 5-37

5.7 Load/Store Instructions 5-37

5.7.1 First Dword 5-38

5.7.2 Second Dword 5-40

Contents ix

Chapter 6 Specifications

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6.1 DC Characteristics 6-1

6.2 TolerANT Technology Electrical Characteristics 6-8

6.3 AC Characteristics 6-11

6.4 PCI and External Memory Interface Timing Diagrams 6-14

6.4.1 Target Timing 6-15

6.4.2 Initiator Timing 6-22

6.4.3 External Memory Timing 6-39

6.5 SCSI Timing Diagrams 6-60

6.6 Package Drawings 6-67

Appendix A Register Summary

Appendix B External Memory Interface Diagram Examples

Index

Customer Feedback

Figures

1.1 Typical LSI53C896 System Application 1-2

1.2 Typical LSI53C896 Board Application 1-3

2.1 LSI53C896 Block Diagram 2-2

2.2 Parity Checking/Generation 2-30

2.3 DMA FIFO Sections 2-31

2.4 LSI53C896 Host Interface SCSI Data Paths 2-32

2.5 8-Bit HVD Wiring Diagram for Ultra SCSI 2-37

2.6 Regulated Termination for Ultra2 SCSI 2-39

2.7 Determining the Synchronous Transfer Rate 2-41

2.8 Interrupt Routing Hardware Using the LSI53C896 2-51

2.9 Block Move and Chained Block Move Instructions 2-53

3.1 LSI53C896 Functional Signal Grouping 3-2

5.1 SCRIPTS Overview 5-4

5.2 Block Move Instruction - First Dword 5-5

5.3 Block Move Instruction - Second Dword 5-14

x Contents

5.4 Block Move Instruction - Third Dword 5-14

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5.5 First 32-Bit Word of the I/O Instruction 5-15

5.6 Second 32-Bit Word of the I/O Instruction 5-22

5.7 Read/Write Instruction - First Dword 5-23

5.8 Read/Write Instruction - Second Dword 5-24

5.9 Transfer Control Instructions - First Dword 5-27

5.10 Transfer Control Instructions - Second Dword 5-33

5.11 Transfer Control Instructions - Third Dword 5-33

5.12 Memory Move Instructions - First Dword 5-35

5.13 Memory Move Instructions - Second Dword 5-36

5.14 Memory Move Instructions - Third Dword 5-37

5.15 Load/Store Instruction - First Dword 5-38

5.16 Load/Store Instructions - Second Dword 5-40

6.1 LVD Driver 6-3

6.2 LVD Receiver 6-4

6.3 Rise and Fall Time Test Condition 6-9

6.4 SCSI Input Filtering 6-9

6.5 Hysteresis of SCSI Receivers 6-10

6.6 Input Current as a Function of Input Voltage 6-10

6.7 Output Current as a Function of Output Voltage 6-11

6.8 External Clock 6-12

6.9 Reset Input 6-13

6.10 Interrupt Output 6-14

6.11 PCI Configuration Register Read 6-16

6.12 PCI Configuration Register Write 6-17

6.13 Operating Registers/SCRIPTS RAM Read, 32-Bit 6-18

6.14 Operating Register/SCRIPTS RAM Read, 64-Bit 6-19

6.15 Operating Register/SCRIPTS RAM Write, 32-Bit 6-20

6.16 Operating Register/SCRIPTS RAM Write, 64-Bit 6-21

6.17 Nonburst Opcode Fetch, 32-Bit Address and Data 6-23

6.18 Burst Opcode Fetch, 32-Bit Address and Data 6-25

6.19 Back to Back Read, 32-Bit Address and Data 6-27

6.20 Back to Back Write, 32-Bit Address and Data 6-29

6.21 Burst Read, 32-Bit Address and Data 6-31

6.22 Burst Read, 64-Bit Address and Data 6-33

6.23 Burst Write, 32-Bit Address and Data 6-35

6.24 Burst Write, 64-Bit Address and Data 6-37

6.25 External Memory Read 6-40

Contents xi

6.26 External Memory Write 6-44

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6.27 Normal/Fast Memory (≥ 128 Kbytes) Single Byte
Access Read Cycle 6-46

6.28 Normal/Fast Memory (≥ 128 Kbytes) Single Byte
Access Write Cycle 6-48

6.29 Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte
Access Read Cycle 6-50

6.30 Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte
Access Write Cycle 6-52

6.31 Slow Memory (≥ 128 Kbytes) Read Cycle 6-54

6.32 Slow Memory (≥ 128 Kbytes) Write Cycle 6-56

6.33 ≤ 64 Kbytes ROM Read Cycle 6-58

6.34 ≤ 64 Kbytes ROM Write Cycle 6-59

6.35 Initiator Asynchronous Send 6-60

6.36 Initiator Asynchronous Receive 6-61

6.37 Target Asynchronous Send 6-61

6.38 Target Asynchronous Receive 6-62

6.39 Initiator and Target Synchronous Transfer 6-66

6.40 LSI53C896 329 BGA (Bottom View) 6-70

6.41 LSI53C896 329 BGA Mechanical Drawing 6-71

B.1 16 Kbyte Interface with 200 ns Memory B-1
B.2 64 Kbyte Interface with 150 ns Memory B-2
B.3 128, 256, 512 Kbyte or 1 Mbyte Interface with

150 ns Memory B-3

B.4 512 Kbyte Interface with 150 ns Memory B-4

Tables

2.1 PCI Bus Commands and Encoding Types for the
LSI53C896 2-5

2.2 PCI Cache Mode Alignment 2-14

2.3 Bits Used for Parity Control and Generation 2-28

2.4 SCSI Parity Control 2-29

2.5 SCSI Parity Errors and Interrupts 2-29

2.6 HVD Signals 2-36

2.7 Parallel ROM Support 2-57

2.8 Mode A Serial EEPROM Data Format 2-59

2.9 Power States 2-60

3.1 LSI53C896 Internal Pull-ups and Pull-downs 3-4

xii Contents

3.2 System Signals 3-5

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3.3 Address and Data Signals 3-6

3.4 Interface Control Signals 3-7

3.5 Arbitration Signals 3-8

3.6 Error Reporting Signals 3-9

3.7 Interrupt Signals 3-10

3.8 SCSI Function A GPIO Signals 3-11

3.9 SCSI Function B GPIO Signals 3-12

3.10 SCSI Bus Interface Signals 3-13

3.11 SCSI Function A Signals 3-14

3.12 SCSI Function A_SCTRL Signals 3-15

3.13 SCSI Function B Signals 3-16

3.14 SCSI Function B_SCRTL Signals 3-18

3.15 Flash ROM and Memory Interface Signals 3-19

3.16 Test Interface Signals 3-20

3.17 Power and Ground Signals 3-21

3.18 Decode of MAD[3:1] Pins 3-23

4.1 PCI Configuration Register Map 4-2

4.2 SCSI Register Map 4-20

4.3 Examples of Synchronous Transfer Periods and
Rates for SCSI-1 4-34

4.4 Example Transfer Periods and Rates for Fast SCSI-2,
Ultra, and Ultra2 4-35

4.5 Maximum Synchronous Offset 4-36

4.6 SCSI Synchronous Data FIFO Word Count 4-46

5.1 Read/Write Instructions 5-25

6.1 Absolute Maximum Stress Ratings 6-2

6.2 Operating Conditions 6-2

6.3 LVD Driver SCSI Signals—SD[15:0], SDP[1:0], SREQ/,
SREQ2/, SACK/, SACK2/, SMSG/, SIO/, SCD/, SATN/,
SBSY/, SSEL/, SRST/ 6-3

6.4 LVD Receiver SCSI Signals—SD[15:0], SDP[1:0],
SREQ/, SREQ2/, SACK/, SACK2/, SMSG/, SIO/,
SCD/, SATN/, SBSY/, SSEL/, SRST/ 6-3

6.5 A and B DIFFSENS SCSI Signals 6-4

6.6 Input Capacitance 6-4

6.7 Bidirectional Signals—GPIO0_FETCH/,
GPIO1_MASTER/, GPIO2, GPIO3, GPIO4, MAD[7:0] 6-5

Contents xiii

6.8 Output Signals—MAS/[1:0], MCE/, MOE/_TESTOUT,

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MWE/, TDO 6-5

6.9 Bidirectional Signals—AD[63:0], C_BE[7:0]/, FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR, PAR64,
REQ64/, ACK64/ 6-6

6.10 Input Signals—CLK, GNT/, IDSEL, INT_DIR, RST/,
SCLK, TCK, TDI, TEST_HSC, TEST_RST/, TMS 6-6

6.11 Output Signals—INTA, INTB, ALT_INTA, ALT_INTB,
REQ/ 6-7

6.12 Output Signal—SERR/ 6-7

6.13 TolerANT Technology Electrical Characteristics for SE
SCSI Signals 6-8

6.14 External Clock 6-12

6.15 Reset Input 6-13

6.16 Interrupt Output 6-14

6.17 PCI Configuration Register Read 6-16

6.18 PCI Configuration Register Write 6-17

6.19 Operating Register/SCRIPTS RAM Read, 32-Bit 6-18

6.20 Operating Register/SCRIPTS RAM Read, 64-Bit 6-19

6.21 Operating Register/SCRIPTS RAM Write, 32-Bit 6-20

6.22 Operating Register/SCRIPTS RAM Write, 64-Bit 6-21

6.23 Nonburst Opcode Fetch, 32-Bit Address and Data 6-22

6.24 Burst Opcode Fetch, 32-Bit Address and Data 6-24

6.25 Back to Back Read, 32-Bit Address and Data 6-26

6.26 Back to Back Write, 32-Bit Address and Data 6-28

6.27 Burst Read, 32-Bit Address and Data 6-30

6.28 Burst Read, 64-Bit Address and Data 6-32

6.29 Burst Write, 32-Bit Address and Data 6-34

6.30 Burst Write, 64-Bit Address and Data 6-36

6.31 External Memory Read 6-39

6.32 External Memory Write 6-43

6.33 Normal/Fast Memory (≥ 128 Kbytes) Single Byte
Access Read Cycle 6-46

6.34 Normal/Fast Memory (≥ 128 Kbytes) Single Byte
Access Write Cycle 6-48

6.35 Slow Memory (≥ 128 Kbytes) Read Cycle 6-54

6.36 Slow Memory (≥ 128 Kbytes) Write Cycle 6-56

6.37 ≤ 64 Kbytes ROM Read Cycle 6-58

xiv Contents

6.38 ≤ 64 Kbytes ROM Write Cycle 6-59

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6.39 Initiator Asynchronous Send 6-60

6.40 Initiator Asynchronous Receive 6-61

6.41 Target Asynchronous Send 6-61

6.42 Target Asynchronous Receive 6-62

6.43 SCSI-1 Transfers (SE 5.0 Mbytes) 6-63

6.44 SCSI-1 Transfers (Differential 4.17 Mbytes) 6-63

6.45 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or

20.0 Mbytes (16-Bit Transfers) 40 MHz Clock 6-64

6.46 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or

20.0 Mbytes (16-Bit Transfers) 50 MHz Clock 6-64

6.47 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers)
or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz
Clock 6-65

6.48 Ultra SCSI HVD Transfers 20.0 Mbytes (8-Bit Transfers)
or 40.0 Mbytes (16-Bit Transfers) 80 MHz Clock 6-65

6.49 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or

80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock 6-66

6.50 Signal Names and BGA Position 6-68

6.51 Signal Names by BGA Position 6-69

A.1 LSI53C896 Register Map A-1

Contents xv

xvi Contents

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Chapter 1

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Introduction

This chapter provides a general overview of the LSI53C896 PCI to Dual
Channel Ultra2 SCSI Multifunction Controller. The chapter contains the
following sections:

• Section 1.1, “General Description”

• Section 1.2, “Benefits of Ultra2 SCSI”

• Section 1.3, “Benefits of L VDlink”

• Section 1.4, “TolerANT

• Section 1.5, “LSI53C896 Benefits Summary”

1.1 General Description

®

Technology”

The LSI53C896 brings Ultra2 SCSI performance to host adapter,
workstation, and general computer designs, making it easy to add a
high-performance SCSI bus to any PCI system. It supports Ultra2 SCSI
transfer rates and allows increased SCSI connectivity and cable length
with Low Voltage Differential (LVD) signaling for SCSI devices.

The LSI53C896 has a local memory bus for local storage of the device’s
BIOS ROM in flash memory or standard EPROMs. The LSI53C896
supports programming of local flash memory for updates to BIOS. The
chip is packaged in a 329 Ball Grid Array (BGA) package. System
diagrams showing the connections of the LSI53C896 with an external
ROM or flash memory are shown in Appendix B, “External Memory

Interface Diagram Examples. ”

LVDlink™ technology is the LSI Logic implementation of LVD. LVDlink
transceivers allow the LSI53C896 to perform either Single-Ended (SE) or
LVD transfers, and support external High Voltage Differential (HVD)
transceivers. The LSI53C896 integrates a high-performance SCSI core,
a 64-bit PCI bus master DMA core, and the LSI Logic SCSI SCRIPTS™

LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller 1-1

processor to meet the flexibility requirements of SCSI-3 and Ultra2 SCSI

*

standards. It is designed to implement multithreaded I/O algorithms with
a minimum of processor intervention, solving the protocol overhead
problems of previous intelligent and nonintelligent adapter designs.

Figure 1.1 illustrates a typical LSI53C896 system and Figure 1.2

illustrates a typical LSI53C896 board application.

Figure 1.1 Typical LSI53C896 System Application

PCI Bus

Interface

Controller

Processor Bus

Central

Processing

Unit

(CPU)

Typical PCI Computer

System Architecture

LSI53C896 PCI

to Wide Ultra2 SCSI

Function A

and

LSI53C896 PCI

to Wide Ultra2 SCSI

Function B

One PCI Bus Load

PCI Graphic Accelerator

PCI Fast Ethernet

Memory

Controller

Memory

SCSI Bus

SCSI Bus

Fixed Disk, Optical Disk,

Printer, Tape, and Other

Peripherals

Fixed Disk, Optical Disk,

Printer, Tape, and Other

Peripherals

1-2 Introduction

Figure 1.2 Typical LSI53C896 Board Application

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SCSI Data,

Function A

68 Pin

Wide SCSI

Connector

Function B

68 Pin

Wide SCSI

Connector

Parity, and

Control Signals

LSI53C896

64-Bit PCI

SCSI Data,

Parity, and

Control Signals

PCI Address, Data, Parity and Control Signals

Dual Channel SCSI

to

Controller

PCI Interface

1.1.1 New Features in the LSI53C896

The LSI53C896 is functionally similar to the LSI53C876 PCI to Dual
Channel SCSI Multifunction Controller, with added support for Ultra2
SCSI. Some software enhancements, and the use of LVD, are needed to
enable the chip to transfer data at Ultra2 SCSI transfer rates.

Memory

Address/Data

Bus

A_GPIO/[1:0]

B_GPIO/[1:0]

Memory Control

Block

Flash EEPROM

Serial EEPROM

Function A

Serial EEPROM

Function B

• 64-bit PCI Interface.

• Able to handle SCSI phase mismatches in SCRIPTS without

interrupting the CPU.

• Two wide Ultra2 SCSI channels in a single package.

• Separate 8 Kbyte internal SCRIPTS RAMs.

• JTAG boundary scanning.

• RAID ready alternative interrupt signaling.

• PC99 Power Management - including automatic download of

Subsystem Vendor ID and Subsystem ID, and PCI power
management levels D0, D1, D2, and D3.

General Description 1-3

• Improved PCI Caching design - improves PCI bus efficiency.

*

• Load/Store data transferred to or from SCRIPTS RAM internal to

chip.

• Hardware control of SCSI activity LED.

• Optional 944 byte DMA FIFO supports large block transfers at Ultra2

SCSI speeds. The default FIFO size of 112 bytes is also supported.

• 32-bit ISTAT registers (Interrupt Status Zero (ISTAT0), Interrupt Status

One (ISTAT1), Mailbox Zero (MBOX0), and Mailbox One (MBOX1)).

1.2 Benefits of Ultra2 SCSI

Ultra2 SCSI is an extension of the SPI-2 draft standard that allows faster
synchronous SCSI transfer rates and defines a new physical layer, LVD
SCSI, that provides an incremental evolution from SCSI-2 and Ultra
SCSI. When enabled, Ultra2 SCSI performs 40 mega transfers per
second, which results in approximately double the synchronous transfer
rates of Ultra SCSI. The LSI53C896 can perform 16-bit, Ultra2 SCSI
synchronous transfers as fast as 80 Mbytes/s on each channel for a total
bandwidth of 160 Mbytes/s. This advantage is most noticeable in heavily
loaded systems, or large block size applications such as video
on-demand and image processing.

An advantage of Ultra2 SCSI is that it significantly improves SCSI
bandwidth while preserving existing hardware and software investments.
The primary software changes required are to enable the chip to perform
synchronous negotiations for Ultra2 SCSI rates, and to enable the clock
quadrupler. Ultra2 SCSI uses the same connectors as Ultra SCSI, but
can operate with longer cables and more devices on the bus. Chapter 2,

“Functional Description,” contains more information on migrating an Ultra

SCSI design to an Ultra2 SCSI design.

1.3 Benefits of LVDlink

The LSI53C896 supports LVD for SCSI, a signaling technology that
increases the reliability of SCSI data transfers over longer distances than
are supported by SE SCSI. The low current output of LVD allows the I/O
transceivers to be integrated directly onto the chip. LVD provides the

1-4 Introduction

reliability of HVD SCSI without the added cost of external differential

*

transceivers. Ultra2 SCSI with LVD allows a longer SCSI cable and more
devices on the bus, with the same cables defined in the SCSI-3 Parallel
Interface standard for Fast-20 (Ultra SCSI). LVD provides a long-term
migration path to even faster SCSI transfer rates without compromising
signal integrity, cable length, or connectivity.

For backward compatibility to existing SE devices, the LSI53C896
features universal LVDlink transceivers that can support LVD SCSI, SE,
and HVD modes. The LVDlink technology also supports HVD signaling
in legacy systems, when external transceivers are connected to the
LSI53C896. This allows the LSI53C896 to be used in both legacy and
Ultra2 SCSI applications.

1.4 TolerANT®Technology

The LSI53C896 features TolerANT technology, which includes active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation causes the SCSI Request, Acknowledge,
Data, and Parity signals to be actively driven HIGH rather than passively
pulled up by terminators. Active negation is enabled by setting bit 7 in
the SCSI T est Three (STEST3) register.

TolerANT receiver technology improves data integrity in unreliable
cabling environments, where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions, without the long signal delay associated with
RC-type input filters. This improved driver and receiver technology helps
eliminate double clocking of data, the single biggest reliability issue with
SCSI operations. TolerANT input signal filtering is a built-in feature of the
LSI53C896 and all LSI Logic fast SCSI, Ultra SCSI, and Ultra2 SCSI
devices.

The benefits of TolerANT technology include increased immunity to noise
when the signal is going HIGH, better performance due to balanced duty
cycles, and improvedfast SCSI transfer rates.Inaddition,TolerANT SCSI
devices do not cause glitches on the SCSI bus at power-up or
power-down, so other devices on the bus are also protected from data
corruption. When it is used with the LVDlink transceivers, TolerANT
technology provides excellent signal quality and data reliability in real

TolerANT®Technology 1-5

world cabling environments. TolerANT technology is compatible with both

*

the Alternative One and Alternative Two termination schemes proposed
by the American National Standards Institute.

1.5 LSI53C896 Benefits Summary

This section provides an overview of the LSI53C896 features and
benefits. It contains information on SCSI Performance, PCI Performance,

Integration, Ease of Use, Flexibility, Reliability, and Testability.

1.5.1 SCSI Performance

• Has integrated LVDlink universal transceivers which:

– Support SE, LVD, and HVD signals (with external transceivers).
– Allow greater device connectivity and longer cable length.
– LVDlink transceivers save the cost of external differential

transceivers.

– Supports a long-term performance migration path.

• With a 944 byte FIFO, the chip can efficiently burst up to 512 bytes

across the PCI bus.

• Two separate SCSI channels on one chip.

• Performs wide, Ultra2 SCSI synchronous transfers as fast as

80 Mbytes/s on each SCSI channel for a total of 160 Mbytes/s.

• Can handle phase mismatches in SCRIPTS without interrupting the

system processor.

• On-chip SCSI clock quadrupler allows the chip to achieve Ultra2

SCSI transfer rates with an input frequency of 40 MHz.

• Includes 8 Kbytes of internal RAM for SCRIPTS instruction storage

for each SCSI channel.

• 31 levels of SCSI synchronous offset.

• Supports variable block size and scatter/gather data transfers.

• Performs sustained memory-to-memory DMA transfers to

approximately 100 Mbytes/s.

• Minimizes SCSI I/O start latency.

1-6 Introduction

• Performs complex bus sequences without interrupts, including

*

restoring data pointers.

• Reduces ISR overhead through a unique interrupt status reporting

method.

• Load/Store SCRIPTS instructions increase performance of data

transfers to and from the chip registers without using PCI cycles.

• SCRIPTS support of 64-bit addressing.

• Supports target disconnect and later reconnect with no interrupt to

the system processor.

• Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast

I/O context switching.

• Expanded Register Move instruction supports additional arithmetic

capability.

1.5.2 PCI Performance

• Complies with the PCI 2.1 specification.

• 64-bit or 32-bit 33 MHz PCI interface.

– Dual Address Cycle (DAC) can be generated for all SCRIPTS.
– True PCI Multifunction Device - presents one electrical load to

the PCI Bus.

• Bursts 2/4, 4/8, 8/16, 16/32, 32/64, or 64/128 Qword/Dword transfers

across the PCI bus.

• Supports 64-bit or 32-bit word data bursts with variable burst lengths.

• Prefetches up to 8 Dwords of SCRIPTS instructions.

• Bursts SCRIPTS opcode fetches across the PCI bus.

• Performs zero wait-state bus master data bursts up to 264 Mbytes/s

(@ 33 MHz).

• Supports PCI Cache Line Size register.

• Supports PCI Write and Invalidate, Read Line, and Read Multiple

commands.

• Complies with PCI Bus Power Management Specification

Revision 1.1.

LSI53C896 Benefits Summary 1-7

1.5.3 Integration

*

• Dual channel Ultra2 SCSI PCI Multifunction controller.

• Integrated LVD transceivers.

• Full 64-bit or 32-bit PCI DMA bus master.

• Can be used as a third-party PCI bus DMA controller by using

• Integrated SCRIPTS processor.

1.5.4 Ease of Use

• Up to one megabyte of add-in memory support for BIOS and

• Direct PCI to SCSI connection.

• Reduced SCSI development effort.

• Compiler-compatible with existing LSI53C7XX and LSI53C8XX

• Direct connection to PCI and SCSI SE, LVD and HVD (needs

• Development tools and sample SCSI SCRIPTS available.

Memory-to-Memory Move instructions.

SCRIPTS storage.

family SCRIPTS.

external transceivers).

• Maskable and pollable interrupts.

• Wide SCSI, A or P cable, and up to 15 devices per SCSI channel

supported.

• Three programmable SCSI timers: Select/Reselect,

Handshake-to-Handshake, and General Purpose. The time-out
period is programmable from 100 µs to greater than 25.6 seconds.

• Software for PC-based operating system support.

• Support for relative jumps.

• SCSI Selected As ID bits for responding with multiple IDs.

1.5.5 Flexibility

• Universal LVD transceivers are backward compatible with SE or HVD

devices.

• High level programming interface (SCSI SCRIPTS).

1-8 Introduction

1.5.6 Reliability

*

• Programs local and bus flash memory.

• Selectable 112 or 944 byte DMA FIFO for backward compatibility.

• Tailored SCSI sequences execute from main system RAM or internal

SCRIPTS RAM.

• Flexible programming interface to tune I/O performance or to adapt

to unique SCSI devices.

• Support for changes in the logical I/O interface definition.

• Low level access to all registers and all SCSI bus signals.

• Fetch, Master, and Memory Access control pins.

• Separate SCSI and system clocks.

• SCSI clock quadrupler bits enable Ultra2 SCSI transfer rates with a

40 MHz SCSI clock input.

• Selectable IRQ pin disable bit.

• Ability to route system clock to SCSI clock.

• Compatible with 3.3 V and 5 V PCI.

• 2 kV ESD protection on SCSI signals.

• Protection against bus reflections due to impedance mismatches.

• Controlled bus assertion times (reduces RFI, improves reliability,and

eases FCC certification).

• Latch-up protection greater than 150 mA.

• Voltage feed-through protection (minimum leakage current through

SCSI pads).

• More than 25% of pins are power and ground.

• Power and ground isolation of I/O pads and internal chip logic.

• TolerANT technology provides:

– Active negation of SCSI Data, Parity, Request, and Acknowledge

signals for improved fast SCSI transfer rates.

– Input signal filtering on SCSI receivers improves data integrity,

even in noisy cabling environments.

LSI53C896 Benefits Summary 1-9

1.5.7 Testability

*

• All SCSI signals accessible through programmed I/O.

• SCSI loopback diagnostics.

• SCSI bus signal continuity checking.

• Support for single step mode operation.

• JTAG boundary scan.

1-10 Introduction

Chapter 2

*

Functional Description

Chapter 2 is divided into the following sections:

• Section 2.1, “PCI Functional Description”

• Section 2.2, “SCSI Functional Description”

• Section 2.3, “Parallel ROM Interface”

• Section 2.4, “Serial EEPROM Interface”

• Section 2.5, “Power Management”

The LSI53C896 is composed of the following modules:

• 64-bit PCI Interface.

• Two independent PCI-to-Wide Ultra2 SCSI Controllers.

• ROM/Flash Memory Controller.

• Serial EEPROM Controller.

Figure 2.1 illustrates the relationship between these modules.

LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller 2-1

Figure 2.1 LSI53C896 Block Diagram

*

64-Bit PCI Interface, PCI Configuration Registers (2 sets)

PCI Bus

Wide Ultra2 SCSI Controller

8 Kbyte

SCRIPTS RAM

944 Byte

DMA FIFO

SCSI FIFO and SCSI Control Block

JTAG

JTAG

Bus

8 Dword SCRIPTS

Prefetch Buffer

Registers

Processor

SCSI SCRIPTS

Universal TolerANT

Drivers and Receivers

SCSI Function A

Wide Ultra2

SCSI Bus

Operating

Local

Memory

ROM/Flash

Memory

Bus

ROM/Flash Memory Control

Bus

2-Wire Serial

EEPROM Bus

(Function A)

SCRIPTS RAM

and Autoconfiguration

Serial EEPROM Controller

Wide Ultra2 SCSI Controller

8 Kbyte

Registers

Operating

SCSI FIFO and SCSI Control Block

2-Wire Serial

EEPROM Bus

(Function B)

8 Dword SCRIPTS

Prefetch Buffer

Processor

SCSI SCRIPTS

Universal TolerANT

Drivers and Receivers

SCSI Function B

Wide Ultra2

SCSI Bus

944 Byte

DMA FIFO

2.1 PCI Functional Description

The LSI53C896 implements two PCI-to-Wide Ultra2 SCSI controllers in
a single package. This configuration presents only one load to the PCI
bus and uses one REQ/ - GNT/ pair to arbitrate for PCI bus mastership.
However, separate interrupt signals are generated for SCSI Function A
and SCSI Function B.

2-2 Functional Description

2.1.1 PCI Addressing

*

There are three physical PCI-defined address spaces:

• PCI Configuration Space.

• I/O Space for operating registers.

• Memory Space for operating registers.

2.1.1.1 Configuration Space

The host processor uses this configuration space to initialize the
LSI53C896. Two independent sets of configuration space registers are
defined, one set for each SCSI function. The Configuration registers are
accessible only by system BIOS during PCI configuration cycles. Each
configuration space is a contiguous 256 X 8-bit set of addresses.
Decoding C_BE[3:0]/ determines if a PCI cycle is intended to access the
configuration register space. The IDSEL bus signal is a “chip select” that
allows access to the configuration register space only. A configuration
read/write cycle without IDSEL is ignored. The eight lower order address
bits (AD[7:0]) are used to select a specific 8-bit register. Since the
LSI53C896 is a PCI multifunction device, bits AD[10:8] decode either
SCSI Function A Configuration register (AD[10:8] = 0b000) or SCSI
Function B Configuration register (AD[10:8] = 0b001).

At initialization time, each PCI device is assigned a base address (in the
case of the LSI53C896, the upper 24 bits of the address are selected)
for memory accesses and I/O accesses. On every access, the
LSI53C896 compares its assigned base addresses with the value on the
Address/Data bus during the PCI address phase. If there is a match of
the upper 24 bits, the access is for the LSI53C896 and the low-order
eight bits define the register to be accessed. A decode of C_BE[3:0]/
determines which registers and what type of access is to be performed.

2.1.1.2 I/O Space

The PCI specification defines I/O space as a contiguous 32-bit I/O
address that is shared by all system resources, including the LSI53C896.

Base Address Register Zero (I/O) determines which 256-byte I/O area

this device occupies.

PCI Functional Description 2-3

2.1.1.3 Memory Space

*

The PCI specification defines memory space as a contiguous 64-bit
memory address that is shared by all system resources, including the
LSI53C896. Base Address Register One (MEMORY) determines which
1 Kbyte memory area this device occupies. Each SCSI function uses a
8 Kbyte SCRIPTS RAM memory space.Base Address Register Two

(SCRIPTS RAM) determines the 8 Kbyte memory area the SCRIPTS

RAM occupies.

2.1.2 PCI Bus Commands and Functions Supported

Bus commands indicate to the target the type of transaction the master
is requesting. Bus commands are encoded on the C_BE[3:0]/ lines
during the address phase. PCI bus commands and encoding types
appear in Table 2.1.

2-4 Functional Description

Table 2.1 PCI Bus Commands and Encoding Types for the LSI53C896

*

C_BE[3:0]/ Command Type Supported as Master Supported as Slave

0000 Interrupt Acknowledge No No
0001 Special Cycle No No
0010 I/O Read Yes Yes
0011 I/O Write Yes Yes
0100 Reserved N/A N/A
0101 Reserved N/A N/A
0110 Memory Read Yes Yes
0111 Memory Write Yes Yes
1000 Reserved N/A N/A
1001 Reserved N/A N/A
1010 Configuration Read No Yes
1011 Configuration Write No Yes
1100 Memory Read Multiple Yes

1

Yes (defaults to 0110)
1101 DAC Yes Yes
1110 Memory Read Line Yes
1111 Memory Write and Invalidate Yes

1. See the DMA Mode (DMODE) register.

2. See the Chip Test Three (CTEST3) register.

1

2

Yes (defaults to 0110)

Yes (defaults to 0111)

2.1.2.1 Interrupt Acknowledge Command

The LSI53C896 does not respond to this command as a slave and it
never generates this command as a master.

2.1.2.2 Special Cycle Command

The LSI53C896 does not respond to this command as a slave and it
never generates this command as a master.

PCI Functional Description 2-5

2.1.2.3 I/O Read Command

*

The I/O Read command reads data from an agent mapped in the I/O
address space. When decoding I/O cycles, the LSI53C896 decodes the
lower 32 address bits and ignores the upper 32 address bits.

2.1.2.4 I/O Write Command

The I/O Write command writes data to an agent mapped in the I/O
address space. When decoding I/O cycles, the LSI53C896 decodes the
lower 32 address bits and ignores the upper 32 address bits.

2.1.2.5 Reserved Command

The LSI53C896 does not respond to this command as a slave and it
never generates this command as a master.

2.1.2.6 Memory Read Command

The Memory Read command reads data from an agent mapped in the
Memory Address Space. The target is free to do an anticipatory read for
this command only if it can guarantee that such a read has no side
effects.

2.1.2.7 Memory Write Command

The Memory Write command writes data to an agent mapped in the
Memory Address Space. When the target returns “ready”, it assumes
responsibility for the coherency (which includes ordering) of the subject
data.

2.1.2.8 Configuration Read Command

The Configuration Read command reads the configuration space of each
agent. An agent is selected during a configuration access when its
IDSEL signal is asserted and AD[1:0] are 0b00. During the address
phase of a configuration cycle AD[7:2] addresses one of the 64 Dword
registers (where byte enables address the bytes within each Dword) in
the configuration space of each device. AD[63:11] are logical don’t cares
to the selected agent. AD[10:8] indicate which device of a multifunction
agent is being addressed.

2-6 Functional Description

2.1.2.9 Configuration Write Command

*

The Configuration Write command transfers data to the configuration
space of each agent. An agent is selected when its IDSEL signal is
asserted and AD[1:0] are 0b00. During the address phase of a
configuration cycle, the AD[7:2] lines address the 64 Dword registers
(where byte enables address the bytes within each Dword) in the
configuration space of each device. AD[63:11] are logical don’t cares to
the selected agent. AD[10:8] indicate which device of a multifunction
agent is addressed.

2.1.2.10 Memory Read Multiple Command

This command is identical to the Memory Read command except that it
additionally indicates that the master may intend to fetch more than one
cache line before disconnecting. The LSI53C896 supports PCI Memory
Read Multiple functionality and issues Memory Read Multiple commands
on the PCI bus when the Read Multiple mode is enabled. This mode is
enabled by setting bit 2 (ERMP) of the DMA Mode (DMODE) register. If
cache mode is enabled, a Memory Read Multiple command is issued on
all read cycles, except opcode fetches, when the following conditions are
met:

• The CLSE bit (Cache Line Size Enable, bit 7, DMA Control (DCNTL)

register) and the ERMP bit (Enable Read Multiple, bit 2, DMA Mode

(DMODE) register) are set.

• The Cache Line Size register for each function contains a legal burst

size value (2, 4, 8, 16, 32, or 64) and that value is less than or equal
to the DMODE burst size.

• The transfer will cross a cache line boundary.

When these conditions are met, the chip issues a Memory Read Multiple
command instead of a Memory Read during all PCI read cycles.

PCI Functional Description 2-7

Burst Size Selection – The Read Multiple command reads in multiple

*

cache lines of data in a single bus ownership. The number of cache lines
to read is a multiple of the cache line size specified in Revision 2.1 of
the PCI specification. The logic selects the largest multiple of the cache
line size based on the amount of data to transfer, with the maximum
allowableburstsize determined from the DMA Mode (DMODE) burst size
bits, and the Chip Test Five (CTEST5), bit 2.

2.1.2.11 DAC Command

The LSI53C896 performs DACs when 64-bit addressing is required. See
PCI specification 2.1. If any of the selector registers contain a nonzero
value, a DAC will be generated.

2.1.2.12 Memory Read Line Command

This command is identical to the Memory Read command, except that it
additionally indicates that the master intends to fetch a complete cache
line. This command is intended for use with bulksequentialdatatransfers
where the memory system and the requesting master might gain some
performance advantage by reading to a cache line boundary rather than
a single memory cycle. The Read Line function in the LSI53C896 takes
advantage of the PCI 2.1 specification regarding issuing of this
command.

If the cache mode is disabled, Read Line commands will not be issued.
If the cache mode is enabled, a Read Line command is issued on all

read cycles, except nonprefetch opcode fetches, when the following
conditions are met:

• The CLSE (Cache Line Size Enable, bit 7, of the DMA Control

(DCNTL) register) and ERL (Enable Read Line, bit 3, of the DMA
Mode (DMODE) register) bits are set.

• The Cache Line Size register for each function must contain a legal

burst size value in Dwords (2, 4, 8, 16, 32, 64, or 128) and that value
is less than or equal to the DMODE burst size.

• The transfer will cross a Dword boundary but not a cache line

boundary.

2-8 Functional Description

When these conditions are met, the chip issues a Read Line command

*

instead of a Memory Read during all PCI read cycles. Otherwise, it
issues a normal Memory Read command.

Read Multiple with Read Line Enabled – When both the Read
Multiple and Read Line modes are enabled, the Read Line command is
not issued if the above conditions are met. Instead, a Read Multiple
command is issued, even though the conditions for Read Line are met.

If the Read Multiple mode is enabled and the Read Line mode is
disabled, Read Multiple commands are issued if the Read Multiple
conditions are met.

2.1.2.13 Memory Write and Invalidate Command

The Memory Write and Invalidate command is identical to the Memory
Write command, except that it additionally guarantees a minimum
transfer of one complete cache line. That is, the master intends to write
all bytes within the addressed cache line in a single PCI transaction
unless interrupted by the target. This command requires implementation
of the PCI Cache Line Size register at address 0x0C in PCI configuration
space. The LSI53C896 enables Memory Write and Invalidate cycles
when bit 0 (WRIE) in the Chip Test Three (CTEST3) register and bit 4
(WIE) in the PCI Command register are set. When the following
conditions are met, Memory Write and Invalidate commands are issued:

• The CLSE bit (Cache Line Size Enable, bit 7, of the DMA Control

(DCNTL) register), WRIE bit (Write and Invalidate Enable, bit 0, of

the Chip Test Three (CTEST3) register), and PCI configuration

Command register, bit 4 are set.

• The Cache Line Size register for each function contains a legal burst

size value in Dwords (2, 4, 8, 16, 32, 64, or 128) and that value is
less than or equal to the DMA Mode (DMODE) burst size.

• The chip has enough bytes in the DMA FIFO to complete at least

one full cache line burst.

• The chip is aligned to a cache line boundary.

When these conditions are met, the LSI53C896 issues a Write and
Invalidate command instead of a Memory Write command during all PCI
write cycles.

PCI Functional Description 2-9

Multiple Cache Line Transfers – The Memory Write and Invalidate

*

command can write multiple cache lines of data in a single bus
ownership. The chip issues a burst transfer as soon as it reaches a
cache line boundary. The size of the transfer is not automatically the
cache line size, but rather a multiple of the cache line size specified in
Revision 2.1 of the PCI specification. The logic selects the largest
multiple of the cache line size based on the amount of data to transfer,
with the maximum allowable burst size determined from the DMA Mode

(DMODE) burst size bits, and Chip Test Five (CTEST5), bit 2. If multiple

cache line size transfers are not desired, set the DMODE burst size to
exactly the cache line size and the chip only issues single cache line
transfers.

After each data transfer, the chip re-evaluates the burst size based on
the amount of remaining data to transfer and again selects the highest
possible multiple of the cache line size, and no larger than the DMA

Mode (DMODE) burst size. The most likely scenario of this scheme is

that the chip selects the DMODE burst size after alignment, and issues
bursts of this size. The burst size is, in effect, throttled down toward the
end of a long Memory Move or Block Move transfer until only the cache
line size burst size is left. The chip finishes the transfer with this burst
size.

Latency – In accordance with the PCI specification, the latency timer is
ignored when issuing a Memory Write and Invalidate command such that
when a latency time-out occurs, the LSI53C896 continues to transfer up
to a cache line boundary. At that point, the chip relinquishes the bus, and
finishes the transfer at a later time using another bus ownership. If the
chip is transferring multiple cache lines it continues to transfer until the
next cache boundary is reached.

PCI Target Retry – During a Memory Write and Invalidate transfer, if the
target device issues a retry (STOP with no TRDY/, indicating that no data
was transferred), the chip relinquishes the bus and immediately tries to
finish the transfer on another bus ownership. The chip issues another
Memory Write and Invalidate command on the next ownership, in
accordance with the PCI specification.

PCI Target Disconnect – During a Memory Write and Invalidate
transfer, if the target device issues a disconnect the LSI53C896
relinquishes the bus and immediately tries to finish the transfer on

2-10 Functional Description

another bus ownership. The chip does not issue another Memory Write

*

and Invalidate command on the next ownership unless the address is
aligned.

2.1.3 Internal Arbiter

The PCI to SCSI controller uses a single REQ/ - GNT/ signal pair to
arbitrate for access to the PCI bus. An internal arbiter circuit allows the
different bus mastering functions resident in the chip to arbitrate among
themselves for the privilege of arbitrating for PCI bus access. There are
two independent bus mastering functions inside the LSI53C896, one for
each of the SCSI functions.

The internal arbiter uses a round robin arbitration scheme to decide
which internal bus mastering function may arbitrate for access to the PCI
bus. This ensures that no function is starved for access to the PCI bus.

2.1.4 PCI Cache Mode

The LSI53C896 supports the PCI specification for an 8-bit Cache Line

Size register located in the PCI configuration space. The Cache Line
Size register provides the ability to sense and react to nonaligned

addresses corresponding to cache line boundaries. In conjunction with
the Cache Line Size register, the PCI commands Memory Read Line,
Memory Read Multiple, Memory Write and Invalidate are each software
enabled or disabled to allow the user full flexibility in using these
commands.

2.1.4.1 Enabling Cache Mode

For the cache logic to be enabled to issue PCI cache commands
(Memory Read Line, Memory Read Multiple, and Memory Write and
Invalidate) on any given PCI master operation the following conditions
must be met:

• The Cache Line Size Enable bit in the DMA Control (DCNTL) register

must be set.

• The PCI Cache Line Size register must contain a valid binary cache

size, i.e. 2, 4, 8, 16, 32, 64, or 128 Dwords. Only these values are
considered valid cache sizes.

PCI Functional Description 2-11

• The programmed burst size (in Dwords) must be equal to or greater

*

than the cache line size register. The DMA Mode (DMODE) register
bits [7:6] and the Chip Test Five (CTEST5) register bit 2 are the burst
length bits.

• The part must be doing a PCI Master transfer. The following PCI

Master transactions do not utilize the PCI cache logic and thus no
PCI cache commands will be issued during these types of cycles: a
nonprefetch SCRIPTS fetch, a Load/Store data transfer, a data flush
operation. All other types of PCI Master transactions will utilize the
PCI cache logic.

The above four conditions must be met for the cache logic to control the
type of PCI cache command that is issued, along with any alignment that
may be necessary during write operations. If these conditions are not
met for any given PCI Master transaction, a Memory Read or Memory
Write will be issued and no cache write alignment will be done.

2.1.4.2 Issuing Cache Commands

In order to issue each type of PCI cache command, the corresponding
enable bit must be set (2 bits in the case of Memory Write and
Invalidate).

• To issue Memory Read Line commands, set the Memory Read Line

enable bit in the DMA Mode (DMODE) register.

• To issue Memory Read Multiple commands, set the Read Multiple

enable bit in the DMA Mode (DMODE) register.

• To issue Memory Write and Invalidate commands, set the Write and

Invalidate enables in both the Chip Test Three (CTEST3) and the
PCI configuration Command registers.

If the corresponding cache command that is to be issued is not enabled
then the cache logic will fall back to the next command enabled, i.e., if
Memory Read Multiple is not enabled and Memory Read Lines are, read
lines will be issued in place of read multiples. If no cache commands are
enabled, cache write alignment will still occur but no cache commands
will be issued, only memory reads and memory writes will be issued.

2-12 Functional Description

2.1.4.3 Memory Read Caching

*

Which type of Memory Read command gets issued depends on the
starting location of the transfer and the number of bytes to be transferred.
During reads, no cache alignment is done (this is not required nor
optimal per PCI 2.1 specification) and reads will always be either a
programmed burst length in size, as set in the DMA Mode (DMODE) and

Chip Test Three (CTEST3) registers. In the case of a transfer which is

smaller than the burst length, all bytes for that transfer will be read in one
PCI burst transaction. If the transfer will cross a Dword boundary
(A[1:0] = 0b00) a Memory Read Line command is issued. When the
transfer will cross a cache boundary (depends on the cache line size
programmed into the PCI configuration register), a Memory Read
Multiple command is issued. If a transfer will not cross a Dword or cache
boundary or if cache mode is not enabled a Memory Read command is
issued.

2.1.4.4 Memory Write Caching

Writes will be aligned in a single burst transfer to get to a cache
boundary. At that point, Memory Write and Invalidate commands will be
issued and will continue at the burst length programmed into the DMA

Mode (DMODE) register. Memory Write and Invalidate commands are

issued as long as the remaining byte count is greater than the Memory
Write and Invalidate threshold. When the byte count goes below this
threshold, a single Memory Write burst will be issued to complete the
transfer. The general pattern for PCI writes will is:

• A single Memory Write to align to a cache boundary.

• Multiple Memory Write and Invalidates.

• A single data residual Memory Write to complete the transfer.

Table 2.2 describes PCI cache mode alignment.

PCI Functional Description 2-13

Table 2.2 PCI Cache Mode Alignment

*

Host Memory

A 0x00

B 0x04

0x08
C 0x0C
D 0x10

0x14

0x18

0x1C
E 0x20

0x24

0x28

0x2C

F 0x30

0x34

0x38

0x3C

G 0x40

0x44

0x48

0x4C
H 0x50

0x54

0x58

0x5C

0x60

2-14 Functional Description

2.1.4.5 Examples:

*

The examples in this section employ the following abbreviations:
MR = Memory Read, MRL = Memory Read Line, MRM = Memory Read
Multiple, MW = Memory Write, MWI = Memory Write and Invalidate.

Read Example 1 –

Burst = 4 Dwords, Cache Line Size = 4 Dwords:

AtoB: MRL (6 bytes)
AtoC: MRL (13 bytes)
AtoD: MRL (15 bytes)

CtoD: MRM (5 bytes)
CtoE: MRM (15 bytes)

DtoF: MRL (15 bytes)

AtoH: MRL (15 bytes)

AtoG: MRL (15 bytes)

MR (2 bytes)

MRM (6 bytes)

MRL (16 bytes)
MR (1 byte)

MRL (16 bytes)
MRL (16 bytes)
MRL (16 bytes)
MRL (16 bytes)
MR (2 bytes)

MRL (16 bytes)
MRL (16 bytes)
MRL (16 bytes)
MR (3 bytes)

PCI Functional Description 2-15

Read Example 2 –

*

Burst = 8 Dwords, Cache Line Size = 4 Dwords:

AtoB: MRL (6 bytes)
AtoC: MRL (13 bytes)
AtoD: MRM (17 bytes)
CtoD: MRM (5 bytes)
CtoE: MRM (21 bytes)
DtoF: MRM (31 bytes)

AtoH: MRM (31 bytes)

AtoG: MRM (31 bytes)

MR (1 byte)

MRM (32 bytes)
MRM (18 bytes)

MRM (32 bytes)
MR (3 bytes)

Read Example 3 –

Burst = 16 Dwords, Cache Line Size = 8 Dwords:

AtoB: MRL (6 bytes)
AtoC: MRL (13 bytes)
AtoD: MRL (17 bytes)
CtoD: MRL (5 bytes)
CtoE: MRM (21 bytes)
DtoF: MRM (32 bytes)
AtoH: MRM (63 bytes)

MRL (16 bytes)
MRM (2 bytes)

AtoG: MRM (63 bytes)

2-16 Functional Description

MR (3 bytes)

Write Example 1 –

*

Burst = 4 Dwords, Cache Line Size = 4 Dwords:

AtoB: MW (6 bytes)
AtoC: MW (13 bytes)
AtoD: MW (17 bytes)
CtoD: MW (5 bytes)
CtoE: MW (3 bytes)

DtoF: MW (15 bytes)

AtoH: MW (15 bytes)

AtoG: MW (15 bytes)

MWI (16 bytes)
MW (2 bytes)

MWI (16 bytes)
MW (1 byte)

MWI (16 bytes)
MWI (16 bytes)
MWI (16 bytes)
MWI (16 bytes)
MW (2 bytes)

MWI (16 bytes)
MWI (16 bytes)
MWI (16 bytes)
MW (3 bytes)

PCI Functional Description 2-17

Write Example 2 –

*

Burst = 8 Dwords, Cache Line Size = 4 Dwords:

AtoB: MW (6 bytes)
AtoC: MW (13 bytes)
AtoD: MW (17 bytes)
CtoD: MW (5 bytes)
CtoE: MW (3 bytes)

DtoF: MW (15 bytes)

AtoH: MW (15 bytes)

AtoG: MW (15 bytes)

MWI (16 bytes)
MW (2 bytes)

MWI (16 bytes)
MW (1 byte)

MWI (32 bytes)
MWI (32 bytes)
MW (2 bytes)

MWI (32 bytes)
MWI (16 bytes)
MW (3 bytes)

2-18 Functional Description

Write Example 3 –

*

Burst = 16 Dwords, Cache Line Size = 8 Dwords:

AtoB: MW (6 bytes)
AtoC: MW (13 bytes)
AtoD: MW (17 bytes)
CtoD: MW (5 bytes)
CtoE: MW (21 bytes)
DtoF: MW (32 bytes)
AtoH: MW (15 bytes)

AtoG: MW (15 bytes)

MWI (64 bytes)
MW (2 bytes)

MWI (32 bytes)
MW (18 bytes)

2.1.4.6 Memory-to-Memory Moves

Memory-to-Memory Moves also support PCI cache commands, as
described above, with one limitation: Memory Write and Invalidate on
Memory-to-Memory Move writes are only supported if the source and
destination address are quad word aligned. If the source and destination
are not quad word aligned, that is, Source address[2:0] == Destination
Address[2:0], write aligning is not performed and no Memory Write and
Invalidate commands are issued. The LSI53C896 is little endian only.

2.2 SCSI Functional Description

The LSI53C896 provides two Ultra2 SCSI controllers on a single chip.
Each Ultra2 SCSI controller provides a SCSI function that supports an
8-bit or 16-bit bus. Each controller supports Wide Ultra2 SCSI
synchronous transfer rates up to 80 Mbytes/s on a LVD SCSI bus. SCSI
functions can be programmed with SCSI SCRIPTS, making it easy to
“fine tune” the system for specific mass storage devices or Ultra2 SCSI
requirements.

SCSI Functional Description 2-19

The LSI53C896 offers low level register access or a high-level control

*

interface. Like first generation SCSI devices, the LSI53C896 is accessed
as a register-oriented device. The ability to sample and/or assert any
signal on the SCSI bus is used in error recovery and diagnostic
procedures. In support of SCSI loopback diagnostics, each SCSI function
may perform a self-selection and operate as both an initiator and a
target.

The LSI53C896 is controlled by the integrated SCRIPTS processor
through a high-level logical interface. Commands controlling the SCSI
functions are fetched out of the main host memory or local memory.
These commands instruct the SCSI functions to Select, Reselect,
Disconnect, Wait for a Disconnect, Transfer Information, Change Bus
Phases and, in general, implement all aspects of the SCSI protocol. The
SCRIPTS processor is a special high-speed processor optimized for
SCSI protocol.

2.2.1 SCRIPTS Processor

The SCSI SCRIPTS processor allows both DMA and SCSI commands
to be fetched from host memory or internal SCRIPTS RAM. Algorithms
written in SCSI SCRIPTS control the actions of the SCSI and DMA
cores. The SCRIPTS processor executes complex SCSI bus sequences
independently of the host CPU.

Algorithms may be designed to tune SCSI bus performance, to adjust to
new bus devicetypes(suchasscanners,communicationgateways, etc.),
or to incorporate changes in the SCSI-2 or SCSI-3 logical bus definitions
without sacrificing I/O performance. SCSI SCRIPTS are hardware
independent, so they can be used interchangeably on any host or CPU
system bus. SCSI SCRIPTS also handle conditions such as Phase
Mismatch.

2.2.1.1 Phase Mismatch Handling in SCRIPTS

The LSI53C896 can handle phase mismatches due to drive disconnects
without needing to interrupt the processor. The primary goal of this logic
is to completely eliminate the need for CPU intervention during an I/O
disconnect/reselect sequence.

2-20 Functional Description

Storing the appropriate information to later restart the I/O can be done

*

through SCRIPTS, eliminating the need for processor intervention during
an I/O disconnect/reselect sequence. Calculations are performed such
that the appropriate information is available to SCRIPTS so that an I/O
state can be properly stored for restart later.

The Phase Mismatch Jump logic powers up disabled and must be
enabled by setting the Phase Mismatch Jump Enable bit (ENPMJ, bit 7
in the Chip Control 0 (CCNTL0) register).

Utilizing the information supplied in the Phase Mismatch Jump Address

1 (PMJAD1) and Phase Mismatch Jump Address 2 (PMJAD2) registers,

described in Chapter 4, “Registers,” allows all overhead involved in a
disconnect/reselect sequence to be handled with a modest amount of
SCRIPTS instructions.

2.2.2 Internal SCRIPTS RAM

The LSI53C896 has 8 Kbytes (2048 x 32 bits) of internal, general
purpose RAM for each SCSI function. The RAM is designed for
SCRIPTS program storage, but is not limited to this type of information.
When the chip fetchesSCRIPTSinstructions or Table Indirect information
from the internal RAM, these fetches remain internal to the chip and do
not use the PCI bus. Other types of access to the RAM by the chip,
except Load/Store, use the PCI bus as if they were external accesses.
The SCRIPTS RAM powers up enabled by default.

The RAM can be relocated by the PCI system BIOS anywhere in the
64-bit address space. Base Address Register Two (SCRIPTS RAM) in
the PCI configuration space contains the base address of the internal
RAM. To simplify loading of the SCRIPTS instructions, the base address
of the RAM appears in the Scratch Register B (SCRATCHB) register
when bit 3 of the Chip Test Two (CTEST2) register is set. The upper
32 bits of a 64-bit base address will be in the SCRIPTS Fetch Selector

(SFS) register. The RAM is byte accessible from the PCI bus and is

visible to any bus mastering device on the bus. External accesses to the
RAM (by the CPU) follow the same timing sequence as a standard slave
register access, except that the required target wait-states drop from
5to3.

SCSI Functional Description 2-21

A complete set of development tools is available for writing custom

*

drivers with SCSI SCRIPTS. For more information on the SCSI SCRIPTS
instructions supported by the LSI53C896, see Chapter 5, “SCSI

SCRIPTS Instruction Set.”

2.2.3 64-Bit Addressing in SCRIPTS

The LSI53C896 has a 64-bit PCI interface which provides 64-bit address
and data capability in the initiator mode. The chip can also respond to
64-bit addressing in the target mode.

DACs can be generated for all SCRIPTS operations. There are six
selector registers which hold the upper Dword of a 64-bit address. All but
one of these is static and requires manual loading using a CPU access,
a Load/Store instruction, or a memory move instruction. One of the
selector registers is dynamic and is used during 64-bit direct block moves
only. All selectors will default to zero, meaning the LSI53C896 will
power-up in a state where only Single Address Cycles (SACs) will be
generated. When any of the selector registers are written to a nonzero
value, DACs will be generated.

Direct, table indirect and indirect block moves, Memory-to-Memory
Moves, Load/Stores and jumps are all instructions with 64-bit address
capability.

Crossing the 4 Gbyte boundary on any one SCRIPTS operation is not
permitted and software needs to take care that any given SCRIPTS
operation will not cross the 4 Gbyte boundary.

2.2.4 Hardware Control of SCSI Activity LED

The LSI53C896 has the ability to control a LED through the GPIO_0 pin
to indicate that it is connected to the SCSI bus. Formerly this function
was done by a software driver.

When bit 5 (LED_CNTL) in the General Purpose Pin Control (GPCNTL)
register is set and bit 6 (Fetch Enable) in the GPCNTL register is cleared
and the LSI53C896 is not performing an EEPROM autodownload, then
bit 3 (CON) in the Interrupt Status Zero (ISTAT0) register will be
presented at the GPIO_0 pin.

2-22 Functional Description

The CON (Connected) bit in Interrupt Status Zero (ISTAT0) will be set

*

anytime the LSI53C896 is connected to the SCSI bus either as an
initiator or a target. This will happen after the LSI53C896 has
successfully completed a selection or when it has successfully
responded to a selection or reselection. It will also be set when the
LSI53C896 wins arbitration in low level mode.

2.2.5 Designing an Ultra2 SCSI System

Since Ultra2 SCSI is based on existing SCSI standards, it can use
existing driver programs as long as the software is able to negotiate for
Ultra2 SCSI synchronous transfer rates. Additional software
modifications may be needed to take advantage of the new features in
the LSI53C896.

In the area of hardware, LVD SCSI is required to achieve Ultra2 SCSI
transfer rates and to support the longer cable and additional devices on
the bus. All devices on the bus must have LVD SCSI capabilities to
guarantee Ultra2 SCSI transfer rates. Foradditional information on Ultra2
SCSI, refer to the SPI-2 working document which is available from the
SCSI BBS referenced at the beginning of this manual. Chapter 6,

“Specifications,” contains Ultra2 SCSI timing information. In addition to

the guidelines in the draft standard, make the following software and
hardware adjustments to accommodate Ultra2 SCSI transfers:

• Set the Ultra Enable bit to enable Ultra2 SCSI transfers.

• Set the TolerANT Enable bit, bit 7 in the SCSI Test Three (STEST3)

register, whenever the Ultra Enable bit is set.

• Do not extend the SREQ/SACK filtering period with the SCSI Test

Two (STEST2) register bit 1. When the Ultra Enable bit is set, the

filtering period will be fixed at 8 ns for Ultra2 SCSI or 15 ns for Ultra
SCSI, regardless of the value of the SREQ/SACK filtering bit.

• Use the SCSI clock quadrupler.

2.2.5.1 Using the SCSI Clock Quadrupler

The LSI53C896 can quadruple the frequency of a 40 MHz SCSI clock,
allowing the system to perform Ultra2 SCSI transfers. This option is user
selectable with bit settings in the SCSI Test One (STEST1), SCSI Test

SCSI Functional Description 2-23

Three (STEST3), and SCSI Control Three (SCNTL3) registers. At

*

power-on or reset, the quadrupler is disabled and powered down. Follow
these steps to use the clock quadrupler:

1. Set the SCLK Quadrupler Enable bit (SCSI Test One (STEST1)
register, bit 3).

2. Poll bit 5 of the SCSI Test Four (STEST4) register. The LSI53C896
sets this bit as soon as it locks in the 160 MHz frequency. The
frequency lockin takes approximately 100 microseconds.

3. Halt the SCSI clock by setting the Halt SCSI Clock bit (SCSI Test

Three (STEST3) register, bit 5).

4. Set the clock conversion factor using the SCF and CCF fields in the

SCSI Control Three (SCNTL3) register.

5. Set the SCLK Quadrupler Select bit (SCSI Test One (STEST1), bit 2).

6. Clear the Halt SCSI Clock bit.

2.2.6 Prefetching SCRIPTS Instructions

When enabled by setting the Prefetch Enable bit (bit 5) in the DMA

Control (DCNTL) register, the prefetch logic in the LSI53C896 fetches

8 Dwords of instruction. The prefetch logic automatically determines the
maximum burst size that it can perform, based on the burst length as
determined by the values in the DMA Mode (DMODE) register. If the unit
cannot perform bursts of at least four Dwords, it disables itself. While the
chip is prefetching SCRIPTS instructions, it will use PCI cache
commands Memory Read Line, and Memory Read Multiple, if PCI
caching is enabled.

Note: This feature is only useful when fetching SCRIPTS

instructions from main memory. Due to the short access
time of SCRIPTS RAM, prefetching is not necessary when
fetching instructions from this memory.

The LSI53C896 may flush the contents of the prefetch unit under certain
conditions to ensure that the chip always operates from the most current
version of the SCRIPTS instruction. When one of these conditions
applies, the contents of the prefetch unit are automatically flushed.

• On every Memory Move instruction. The Memory Move instruction is

often used to place modified code directly into memory. To make
sure that the chip executes all recent modifications, the prefetch unit

2-24 Functional Description

flushes its contents and loads the modified code every time an

*

instruction is issued. To avoid inadvertently flushing the prefetch unit
contents, use the No Flush option for all Memory Move operations
that do not modify code within the next 8 Dwords. For more
information on this instruction refer to Chapter 5, “SCSI SCRIPTS

Instruction Set.”

• On every Store instruction. The Store instruction may also be used

to place modified code directly into memory. To avoid inadvertently
flushing the prefetch unit contents use the No Flush option for all
Store operations that do not modify code within the next 8 Dwords.

• On every write to the DMA SCRIPTS Pointer (DSP) register.

• On all Transfer Control instructions when the transfer conditions are

met. This is necessary because the next instruction to execute is not
the sequential next instruction in the prefetch unit.

• When the Prefetch Flush bit (DMA Control (DCNTL) register, bit 6)

is set. The unit flushes whenever this bit is set. The bit is
self-clearing.

2.2.7 Opcode Fetch Burst Capability

Setting the Burst Opcode Fetch Enable bit (bit 1) in the DMA Mode

(DMODE) register (0x38) causes the LSI53C896 to burst in the first two

Dwords of all instruction fetches. If the instruction is a Memory-to­Memory Move, the third Dword is accessed in a separate ownership. If
the instruction is an Indirect Type, the additional Dword is accessed in a
subsequent bus ownership. If the instruction is a table indirect Block
Move, the chip uses two accesses to obtain the four Dwords required, in
two bursts of two Dwords each.

Note: This feature is only useful if Prefetching is disabled.

This feature is only useful if fetching SCRIPTS instructions
from main memory. Due to the short access time of
SCRIPTS RAM, burst opcode fetching is not necessary
when fetching instructions from this memory.

SCSI Functional Description 2-25

2.2.8 Load/Store Instructions

*

The LSI53C896 supports the Load/Store instruction type, which
simplifies the movement of data between memory and the internal chip
registers. It also enables the chip to transfer bytes to addresses relative
to the Data Structure Address (DSA) register. Load/Store data transfers
to or from the SCRIPTS RAM will remain internal to the chip and will not
generate PCI bus cycles. While a Load/Store to or from SCRIPTS RAM
is occurring, any external PCI slave cycles that occur will be retried on
the PCI bus. This feature can be disabled by setting the DILS bit in the

Chip Control 0 (CCNTL0) register. For more information on the

Load/Store instructions refer to Chapter 5, “SCSI SCRIPTS Instruction

Set.”

2.2.9 JTAG Boundary Scan Testing

The LSI53C896 includes support for JTAG boundary scan testing in
accordance with the IEEE 1149.1 specification with one exception, which
is explained in this section. This device accepts all required boundary
scan instructions including the optional CLAMP, HIGH-Z, and IDCODE
instructions.

The LSI53C896 uses an 8-bit instruction register to support all boundary
scan instructions. The data registers included in the device are the
Boundary Data register, the IDCODE register, and the Bypass register.
This device can handle a 10 MHz TCK frequency for TDO and TDI.

Due to design constraints, the RST/ pin (system reset) always 3-states
the SCSI pins when it is asserted. Boundary scan logic does not control
this action, and this is not compliant with the specification. There are two
solutions that resolve this issue:

1. Use the RST/ pin as a boundary scan compliance pin. When the pin
is deasserted, the device is boundary scan compliant and when
asserted, the device is noncompliant. To maintain compliance the
RST/ pin must be driven HIGH.

2. When RST/ is asserted during boundary scan testing the expected
output on the SCSI pins must be the HIGH-Z condition, and not what
is contained in the boundary scan data registers for the SCSI pin
output cells.

2-26 Functional Description

2.2.10 SCSI Loopback Mode

*

The LSI53C896 loopback mode allows testing of both initiator and target
functions and, in effect, lets the chip communicate with itself. When the
Loopback Enable bit is set in the SCSI Test Two (STEST2) register, bit 4,
the LSI53C896 allows control of all SCSI signals whether the chip is
operating in the initiator or target mode. For more information on this
mode of operation refer to the LSI Logic SCSI SCRIPTS Processors
Programming Guide.

2.2.11 Parity Options

The LSI53C896 implements a flexible parity scheme that allows control
of the parity sense, allows parity checking to be turned on or off, and has
the ability to deliberately send a byte with bad parity over the SCSI bus
to test parity error recovery procedures. Table 2.3 defines the bits that
are involved in parity control and observation. Table 2.4 describes the
parity control function of the Enable Parity Checking and Assert SCSI
Even Parity bits in the SCSI Control One (SCNTL1) register, bit 2.

Table 2.5 describes the options available when a parity error occurs.
Figure 2.2 shows where parity checking is done in the LSI53C896.

SCSI Functional Description 2-27

Table 2.3 Bits Used for Parity Control and Generation

*

Bit Name Location Description

Assert SATN/ on Parity
Errors

Enable Parity
Checking

Assert Even SCSI Parity SCSI Control

Disable Halt on SATN/
or a Parity Error (Target
Mode Only)

Enable Parity Error
Interrupt

Parity Error SCSI Interrupt

Status of SCSI
Parity Signal

SCSI SDP1 Signal SCSI Status Two

SCSI Control
Zero (SCNTL0),

Bit 1

SCSI Control
Zero (SCNTL0),

Bit 3

One (SCNTL1),

Bit 2

SCSI Control
One (SCNTL1),

Bit 5

SCSI Interrupt
Enable Zero
(SIEN0), Bit 0

Status Zero
(SIST0), Bit 0

SCSI Status Zero
(SSTAT0), Bit 0

(SSTAT2), Bit 0

Causes the LSI53C896 to automatically assert SATN/
when it detects a SCSI parity error while operating as
an initiator.

Enables the LSI53C896 to check for parity errors. The
LSI53C896 checks for odd parity.

Determines the SCSI parity sense generated by the
LSI53C896 to the SCSI bus.

Causes the LSI53C896 not to halt operations when a
parity error is detected in target mode.

Determines whether the LSI53C896 generates an
interrupt when it detects a SCSI parity error.

This status bit is set whenever the LSI53C896 detects
a parity error on the SCSI bus.

This status bit representsthe active HIGH current state
of the SCSI SDP0 parity signal.

This bit represents the active HIGH current state of the
SCSI SDP1 parity signal.

Latched SCSI Parity SCSI Status Two

Master Parity Error
Enable

Master Data Parity Error DMA Status

Master Data Parity Error
Interrupt Enable

2-28 Functional Description

(SSTAT2), Bit 3
SCSI Status One
(SSTAT1), Bit 3

Chip Test Four
(CTEST4), Bit 3

(DSTAT), Bit 6

DMA Interrupt
Enable (DIEN),

Bit 6

These bits reflect the SCSI odd parity signal
corresponding to the data latched into the SCSI Input

Data Latch (SIDL) register.

Enables parity checking during PCI master data
phases.

Set when the LSI53C896, as a PCI master, detects a
target device signaling a parity error during a data
phase.

By clearing this bit, a Master Data Parity Error does not
cause assertion of INTA/ (or INTB/), but the status bit
is set in the DMA Status (DSTAT) register.

Table 2.4 SCSI Parity Control

*

EPC

1

ASEP

2

Description

0 0 Does not check for parity errors. Parity is generated when sending SCSI data.

Asserts odd parity when sending SCSI data.

0 1 Does not check for parity errors. Parity is generated when sending SCSI data.

Asserts even parity when sending SCSI data.

1 0 Checks for odd parity on SCSI data received. Parity is generated when

sending SCSI data. Asserts odd parity when sending SCSI data.

1 1 Checks for odd parity on SCSI data received. Parity is generated when

sending SCSI data. Asserts even parity when sending SCSI data.

1. EPC = Enable Parity Checking (bit 3 SCSI Control Zero (SCNTL0)).

2. ASEP = Assert SCSI Even Parity (bit 2 SCSI Control One (SCNTL1)).

Table 2.5 SCSI Parity Errors and Interrupts

1

DHP

0 0 Halts when a parity error occurs in the target or initiator mode and does NOT

0 1 Halts when a parity error occurs in the target mode and generates an interrupt

PAR

2

Description

generate an interrupt.

in the target or initiator mode.

1 0 Does not halt in target mode when a parity error occurs until the end of the

transfer. An interrupt is not generated.

1 1 Does not halt in target mode when a parity error occurs until the end of the

transfer. An interrupt is generated.

1. DHP = Disable Halt on SATN/ or Parity Error (bit 5 SCSI Control One (SCNTL1)).

2. PAR = Parity Error (bit 0 SCSI Interrupt Enable One (SIEN1)).

SCSI Functional Description 2-29

Figure 2.2 Parity Checking/Generation

*

Asynchronous

SCSI Send

PCI Interface**

X

DMA FIFO*

(64 Bits x 118)

SODL Register*

S

SCSI Interface**

X - Check parity
G - Generate 32-bit even PCI parity
S - Generate 8-bit odd SCSI parity

Asynchronous

SCSI Receive

PCI Interface**

DMA FIFO*

(64 Bits x 118)

SIDL Register*

SCSI Interface**

2.2.12 DMA FIFO

The DMA FIFO is 8 bytes wide by 118 transfers deep. The DMA FIFO is
illustrated in Figure 2.3. The default DMA FIFO size is 112 bytes to
assure compatibility with older products in the LSI53C8XX family.

The DMA FIFO size may be set to 944 bytes by setting the DMA FIFO
Size bit, bit 5, in the Chip Test Five (CTEST5) register.

Synchronous

SCSI Send

PCI Interface**

G

(64 Bits x 118)

SODL Register*

X

SODR Register*

SCSI Interface**

X

DMA FIFO*

S

Synchronous

SCSI Receive

PCI Interface**

G

DMA FIFO*

(64 Bits x 118)

X

SCSI FIFO*

(8 or 16 Bits x 31)

X

SCSI Interface**

* = No parity protection

** = Parity protected

2-30 Functional Description

Figure 2.3 DMA FIFO Sections

*

8 Bytes Wide

.

.

118

Transfers

Deep

.

8 Bits

Byte Lane 7

2.2.12.1 Data Paths

8 Bits

Byte Lane 6

8 Bits

Byte Lane 5

8 Bits

Byte Lane 4

8 Bits

Byte Lane 3

8 Bits

Byte Lane 2

8 Bits

Byte Lane 1

8 Bits

Byte Lane 0

The LSI53C896 supports 64-bit memory and automatically supports
misaligned DMA transfers. A 944-byte FIFO allows the LSI53C896 to
support 2, 4, 8, 16, 32, 64, or 128 Dword bursts across the PCI bus
interface.

The data path through the LSI53C896 is dependent on whether data is
being moved into or out of the chip, and whether SCSI data is being
transferred asynchronously or synchronously.

Figure 2.4 shows how data is moved to/from the SCSI bus in each of the

different modes.

.

.

.

SCSI Functional Description 2-31

Figure 2.4 LSI53C896 Host Interface SCSI Data Paths

*

Asynchronous

SCSI Send

PCI Interface

DMA FIFO

(8 Bytes x 118)

SODL Register

SCSI Interface

Asynchronous

SCSI Receive

PCI Interface

DMA FIFO

(8 Bytes x 118)

SIDL Register

SCSI Interface

Synchronous

SCSI Send

PCI Interface

DMA FIFO

(8 Bytes x 118)

SWIDE Register

SODL Register

SODR Register

SCSI Interface

Synchronous

SCSI Receive

PCI Interface

DMA FIFO

(8 Bytes x 118)

SWIDE Register

SCSI FIFO

(1 or 2 Bytes x 31)

SCSI Interface

The following items determine if any bytes remain in the data path when
the chip halts an operation:

Asynchronous SCSI Send –

Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Chip Test

Five (CTEST5) register cleared), look at the DMA FIFO
(DFIFO) and DMA Byte Counter (DBC) registers and calculate

if there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the DBC register from
the 7-bit value of the DFIFO register. AND the result with 0x7F
for a byte count between zero and 112.

If the DMA FIFO size is set to 944 bytes (bit 5 of the Chip Test

Five (CTEST5) register is set), subtract the 10 least significant

bits of the DMA Byte Counter (DBC) register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the Chip Test Five (CTEST5) register and bits [7:0]
of the DMA FIFO (DFIFO) register. AND the result with 0x3FF
for a byte count between zero and 944.

Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) and SCSI Status

Two (SSTAT2) registers to determine if any bytes are left in the
SCSI Output Data Latch (SODL) register. If bit 5 is set in the

2-32 Functional Description

SSTAT0 or SSTAT2 register, then the least significant byte or

*

the most significant byte in the SODL register is full. Checking
this bit also reveals bytes left in the SODL register from a
Chained Move operation with an odd byte count.

Synchronous SCSI Send –

Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Chip Test

Five (CTEST5) register cleared), look at the DMA FIFO
(DFIFO) and DMA Byte Counter (DBC) registers and calculate

if there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the DBC register from
the 7-bit value of the DFIFO register. AND the result with 0x7F
for a byte count between zero and 112.

If the DMA FIFO size is set to 944 bytes (bit 5 of the Chip Test

Five (CTEST5) register is set), subtract the 10 least significant

bits of the DMA Byte Counter (DBC) register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the Chip Test Five (CTEST5) register and bits [7:0]
of the DMA FIFO (DFIFO) register. AND the result with 0x3FF
for a byte count between zero and 944.

Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) and SCSI Status

Two (SSTAT2) registers to determine if any bytes are left in the

SODL register. If bit 5 is set in the SSTAT0 or SSTAT2 register,
then the least significant byte or the most significant byte in the

SCSI Output Data Latch (SODL) register is full. Checking this

bit also reveals bytes left in the SODL register from a Chained
Move operation with an odd byte count.

Step 3. Read bit 6 in the SCSI Status Zero (SSTAT0) and SCSI Status

Two (SSTAT2) registers to determine if any bytes are left in the

SODR register (a hidden buffer register which is not
accessible). If bit 6 is set in the SSTAT0 or SSTAT2 register,
then the least significant byte or the most significant byte in the
SODR register is full.

Asynchronous SCSI Receive –

Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Chip Test

Five (CTEST5) register cleared), look at the DFIFO and DMA
Byte Counter (DBC) registers and calculate if there are bytes

SCSI Functional Description 2-33

left in the DMA FIFO. To make this calculation, subtract the

*

seven least significant bits of the DBC register from the 7-bit
value of the DMA FIFO (DFIFO) register. AND the result with
0x7F for a byte count between zero and 112.

If the DMA FIFO size is set to 944 bytes (bit 5 of the Chip Test

Five (CTEST5) register is set), subtract the 10 least significant

bits of the DMA Byte Counter (DBC) register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the CTEST5 register and bits [7:0] of the DMA FIFO

(DFIFO) register. AND the result with 0x3FF for a byte count

between zero and 944.

Step 2. Read bit 7 in the SCSI Status Zero (SSTAT0) and SCSI Status

Two (SSTAT2) registers to determine if any bytes are left in the
SCSI Input Data Latch (SIDL) register. If bit 7 is set in the

SSTAT0 or SSTAT2 registers, then the least significant byte or
the most significant byte is full.

Step 3. If any wide transfers have been performed using the Chained

Move instruction, read the Wide SCSI Receive bit (SCSI

Control Two (SCNTL2), bit 0) to determine whether a byte is left

in the SCSI Wide Residue (SWIDE) register.

Synchronous SCSI Receive –

Step 1. If the DMA FIFO size is set to 112 bytes, subtract the seven

least significant bits of the DMA Byte Counter (DBC) register
from the 7-bit value of the DMA FIFO (DFIFO) register. AND
the result with 0x7F for a byte count between zero and 112.

If the DMA FIFO size is set to 944 bytes (bit 5 of the Chip Test

Five (CTEST5) register is set), subtract the 10 least significant

bits of the DMA Byte Counter (DBC) register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the CTEST5 register and bits [7:0] of the DMA FIFO

(DFIFO) register. AND the result with 0x3FF for a byte count

between zero and 944.

Step 2. Read the SCSI Status One (SSTAT1) register and examine bits

[7:4], the binary representation of the number of valid bytes in
the SCSI FIFO, to determine if any bytes are left in the SCSI
FIFO.

2-34 Functional Description

Step 3. If any wide transfers have been performed using the Chained

*

Move instruction, read the Wide SCSI Receive bit (SCSI

Control Two (SCNTL2), bit 0) to determine whether a byte is left

in the SCSI Wide Residue (SWIDE) register.

2.2.13 SCSI Bus Interface

The LSI53C896 performs SE and LVD transfers, and supports traditional
HVD operation when the chip is connected to external HVD transceivers.

To support LVD SCSI, all SCSI data and control signals have both
negative and positive signal lines. The negative signals perform the SCSI
data and control function. In the SE mode they become virtual ground
drivers. In the HVD mode, the positive signals provide directional control
to the external transceivers. TolerANT technology provides signal filtering
at the inputs of SREQ/ and SACK/ to increase immunity to signal
reflections.

2.2.13.1 LVDlink Technology

To support greater device connectivity and a longer SCSI cable, the
LSI53C896 features LVDlink technology, the LSI Logic implementation of
LVD SCSI. LVDlink transceivers provide the inherent reliability of
differential SCSI, and a long-term migration path of faster SCSI transfer
rates.

LVDlink technology is based on current drive. Its low output current
reduces the power needed to drive the SCSI bus, so that the I/O drivers
can be integrated directly onto the chip. This reduces the cost and
complexity compared to traditional HVD designs. LVDlink lowers the
amplitude of noise reflections and allows higher transmission
frequencies.

The LSI Logic LVDlink transceivers operate in LVD or SE modes. They
allow the chip to detect a HVD signal when the chip is connected to
external HVD transceivers. The LSI53C896 automatically detects which
type of signal is connected, based on the voltage detected by the
DIFFSENS pin. Bits 7 and 6 of the SCSI Test Four (STEST4) register
contain the encoded value for the type of signal that is detected (LVD,
SE, or HVD). Please see the SCSI Test Four (STEST4) register
description for encoding and other bit information.

SCSI Functional Description 2-35

2.2.13.2 HVD Mode

*

To maintain backward compatibility with legacy systems, the LSI53C896
can operate in the HVD mode (when the chip is connected to external
differential transceivers). In the HVD mode, the SD[15:0]+, SDP[1:0]+,
SREQ+, SACK+, SRST+, SBSY+, and SSEL+ signals control the
direction of external differential pair transceivers. The LSI53C896 is
placed in the HVD mode by setting the DIF bit, bit 5, of the SCSI Test

Two (STEST2) register (0x4E). Setting this bit 3-states the SBSY−,

SSEL−, and SRST− pads so they can be used as pure input pins. In
addition to the standard SCSI lines, the signals shown in Table 2.6 are
used by the LSI53C896 during HVD operation.

Table 2.6 HVD Signals

Signal Function

SBSY+, SSEL+,
SRST+

SD[15:0]+,
SDP[1:0]+

SACK+ Active HIGH signal used to control the direction of the differential drivers for

SREQ+ Active HIGH signal used to control the direction of the differential drivers for

DIFFSENS Input to the LSI53C896 used to detect the voltage level of a SCSI signal to

Active HIGH signals used to enable the differential drivers as outputs for
SCSI signals SBSY−, SSEL−, and SRST−, respectively.

Active HIGH signals used to control the direction of the differential drivers for
SCSI data and parity lines, respectively.

the initiator group signals SATN− and SACK−.

target group signals SMSG−, SC_D−, SI_O− and SREQ−.

determine whether it is a SE, LVD, or HVD signal. The encoded result is
displayed in SCSI Test Four (STEST4) bits 7 and 6.

In the example differential wiring diagram in Figure 2.5, the LSI53C896 is
connected to TI SN75976 differential transceivers for Ultra SCSI operation.
The recommended value of the pull-up resistor on the SREQ

−,SACK−,

SMSG−, SC_D−, SI_O−,SATN−, SD[7:0]−, and SDP0− lines is 680 Ω
when the Active Negation portion of LSI Logic TolerANT technology is not
enabled. When TolerANT technology is enabled, the recommended
resistor value on the SREQ−,SACK−, SD[7:0]−, and SDP0− signals is

1.5 kΩ. The electrical characteristics of these pins change when TolerANT

technology is enabled, permitting a higher resistor value.

2-36 Functional Description

Figure 2.5 8-Bit HVD Wiring Diagram for Ultra SCSI

*

LSI53C8XX

SEL+
BSY+
RST+

SEL−
BSY−
RST−

REQ−

ACK−

MSG−

ATN−

REQ+
ACK+

SD[8:15]+

SDP1+

SD[8:15]−

SDP1−

SDP0+

SD7+
SD6+
SD5+
SD4+
SD3+
SD2+
SD1+
SD0+

SDP0−

SD7−
SD6−
SD5−
SD4−
SD3−
SD2−
SD1−
SD0−

DIFFSENS

C/D−

I/O−

Float
Float

VDD

1.5 K

VDD

DIFFSENS

1.5 K

VDD

VDD

1.5 K

1.5 K

1.5 K

VDD

1.5 K

1.5 K

1.5 K

1.5 K

SEL­BSY­RST-

1.5 K

SD0−
SD1−
SD2−
SD3−
SD4−
SD5−
SD6−
SD7−
SDP0−

VDD

1.5 K

SEL+
BSY+
RST+

REQ/

ACK−
MSG−

C_D−
I_O−

ATN-

DIFFSENS

SD0+
SD1+
SD2+
SD3+
SD4+
SD5+
SD6+
SD7+
SDP0+

DIFFSENS

Schottky

Diode

SN75976A2

CDE0
CDE1
CDE2
BSR
CRE

1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE

SN75976A2

CDE0
CDE1
CDE2
BSR
CRE

1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE

DIFFSENS (pin 21)

(42)

−SEL

1B+
1B−
2B+
2B−
3B+
3B−
4B+
4B−
5B+
5B−
6B+
6B−
7B+
7B−
8B+
8B−
9B+
9B−

1B+
1B−
2B+
2B−
3B+
3B−
4B+
4B−
5B+
5B−
6B+
6B−
7B+
7B−
8B+
8B−
9B+
9B−

+SEL

−BSY
+BSY

−RST
+RST

−REQ
+REQ

−ACK
+ACK

−MSG
+MSG

−C/D

+C/D

−I/O
+I/O

−ATN

+ATN

−DB0
+DB0

−DB1
+DB1

−DB2
+DB2

−DB3
+DB3

−DB4
+DB4

−DB5
+DB5

−DB6
+DB6

−DB7
+DB7

−DBP

+DBP

(41)
(34)
(33)
(38)
(37)
(46)

(45)
(36)
(35)
(40)
(39)
(44)
(43)
(48)
(47)
(30)
(29)

(4)
(3)

(6)
(5)
(8)
(7)

(10)

(9)
(12)
(11)
(14)
(13)
(16)
(15)
(18)
(17)
(20)
(19)

SCSI
Bus

SCSI Functional Description 2-37

To interface the LSI53C896 to the SN75976A, connect the positive pins

*

in the SCSI LVD pair of the LSI53C896 directly to the transceiver enables
(DE/RE/). These signals control the direction of the channels on the
SN75976A.

The SCSI bidirectional control and data pins (SD[7:0]

−, SDP0−, SREQ−,

SACK−,SMSG−, SI_O−, SC_D−, and SATN−) of the LSI53C896 connect
to the bidirectional data pins (nA) of the SN75976A with a pull-up
resistor. The pull-up value should be no lower than the transceiver I

OL

can tolerate, but not so high as to cause RC timing problems. The three
remaining pins, SSEL

−, SBSY− and SRST−, are connected to the

SN75976A with a pull-down resistor. The pull-down resistors are required
when the pins (nA) of the SN75976A are configured as inputs. When the
data pins are inputs, the resistors provide a bias voltage to both the
LSI53C896 pins (SSEL

−, SBSY−, and SRST−) and the SN75976A data

pins. Because the SSEL−, SBSY−, and SRST− pins on the LSI53C896
are inputs only, this configuration allows for the SSEL−, SBSY−, and
SRST− SCSI signals to be asserted on the SCSI bus.

The differential pairs on the SCSI bus are reversed when connected to
the SN75976A due to the active low nature of the SCSI bus.

8-Bit/16-Bit SCSI and the HVD Interface – In an 8-bit SCSI bus, the
SD[15:8] pins on the LSI53C896 should be pulled up with a 1.5 kΩ
resistor or terminated like the rest of the SCSI bus lines. This is very
important, as errors may occur during reselection if these lines are left
floating.

2.2.13.3 SCSI Termination

The terminator networks provide the biasing needed to pull signals to an
inactive voltage level, and to match the impedance seen at the end of
the cable with the characteristic impedance of the cable. Terminators
must be installed at the extreme ends of the SCSI chain, and only at the
ends. No system should ever have more or less than two terminators
installed and active. SCSI host adapters should provide a means of
accommodating terminators. There should be a means of disabling the
termination.

SE cables can use a 220 Ω pull-up resistor to the terminator power
supply (Term Power) line and a 330 Ω pull-down resistor to ground.
Because of the high-performance nature of the LSI53C896, regulated (or

2-38 Functional Description

active) termination is recommended. Figure 2.6 shows a Unitrode active

*

terminator. TolerANT technology active negation can be used with either
termination network.

For information on terminators that support LVD, refer to the SPI-2 draft
standard.

Note: If the LSI53C896 is to be used in a design with only an

8-bit SCSI bus, all 16 data lines must be terminated.

Figure 2.6 Regulated Termination for Ultra2 SCSI

UCC5630

−

SD0+
SD0−
SD1+
SD1−
SD2+
SD2−

SD3+
SD3−
SD4+
SD4−

4
5
6
7
11
12
13
14
15
16

Line1+
Line1−
Line2+
Line2−
Line3+
Line3−
Line4+
Line4−
Line5+
Line5−

Line9−
Line9+

Line8−
Line8+

Line7−
Line7+

Line6−
Line6+

SE

LVD

HVD

32
31
30
29
25
24
23
22

33
34

35

SDP0
SDP0+

SD7

−

SD7+
SD6

−

SD6+

−

SD5
SD5+

To LED
Drivers

DIFFSENS

17

DISCNCT

DIFF B

DIFFSENS connects to the SCSI bus DIFFSENS line to detect what
type of devices (SE, LVD, or HVD) are connected to the SCSI bus.
DISCNCT shuts down the terminator when it is not at the end of the
bus. The disconnect pin low enables the terminator.
*Use additional UCC5630 terminators to terminate the SCSI control
signals and wide SCSI data byte as needed.

20

22 K

21

0.1 µF

SCSI Functional Description 2-39

2.2.14 Select/Reselect During Selection/Reselection

*

In multithreaded SCSI I/O environments, it is not uncommon to be
selected or reselected while trying to perform selection/reselection. This
situation may occur when a SCSI controller (operating in the initiator
mode) tries to select a target and is reselected by another. The Select
SCRIPTS instruction has an alternate address to which the SCRIPTS will
jump when this situation occurs. The analogous situation for target
devices is being selected while trying to perform a reselection.

Once a change in operating mode occurs, the initiator SCRIPTS should
start with a Set Initiator instruction or the target SCRIPTS should start
with a Set Target instruction. The Selection and Reselection Enable bits
(SCSI Chip ID (SCID) bits 5 and 6, respectively) should both be asserted
so that the LSI53C896 may respond as an initiator or as a target. If only
selection is enabled, the LSI53C896 cannot be reselected as an initiator.
There are also status and interrupt bits in the SCSI Interrupt Status Zero

(SIST0) and SCSI Interrupt Enable Zero (SIEN0) registers, respectively,

indicating that the LSI53C896 has been selected (bit 5) and reselected
(bit 4).

2.2.15 Synchronous Operation

The LSI53C896 can transfer synchronous SCSI data in both the initiator
and target modes. The SCSI Transfer (SXFER) register controls both the
synchronous offset and the transfer period. It may be loaded by the CPU
before SCRIPTS execution begins, from within SCRIPTS using a Table
Indirect I/O instruction, or with a Read-Modify-Write instruction.

The LSI53C896 can receive data from the SCSI bus at a synchronous
transfer period as short as 25 ns, regardless of the transfer period used
to send data. The LSI53C896 can receive data at one-fourth of the
divided SCLK frequency. Depending on the SCLK frequency, the
negotiated transfer period, and the synchronous clock divider, the
LSI53C896 can send synchronous data at intervals as short as 25 ns for
Ultra2 SCSI, 50 ns for Ultra SCSI, 100 ns for fast SCSI and 200 ns for
SCSI-1.

2-40 Functional Description

2.2.15.1 Determining the Data Transfer Rate

*

Synchronous data transfer rates are controlled by bits in two different
registers of the LSI53C896. Following is a brief description of the bits.

Figure 2.7 illustrates the clock division factors used in each register, and

the role of the register bits in determining the transfer rate.

Figure 2.7 Determining the Synchronous Transfer Rate

SCF2 SCF1 SCF0 SCF

Divisor
0011
0 1 0 1.5
0112
1003
0003
1014
1106
1118

SCF

Divider

SCLK

CCF2 CCF1 CCF0 Divisor QCLK (MHz)

0 0 1 1 50.1–66.00
0 1 0 1.5 16.67–25.00
0 1 1 2 25.1–37.50
1 0 0 3 37.51–50.00
0 0 0 3 50.01–66.00
1 0 1 4 75.01–80.00
1 1 0 6 120
1 1 1 8 160

Clock

Quadrupler

QCLK

CCF

Divider

TP2 TP1 TP0 XFERP

Divisor
0004
0015
0106
0117
1008
1019
11010
11111

This point

must not

exceed

160 MHz

Example:
QCLK (Quadrupled SCSI Clock) = 160 MHz
SCF = 1 (/1), XFERP = 0 (/4), CCF = 7 (/8)

Synchronous send rate = (QCLK/SCF)/XFERP =
(160/1) /4 = 40 Mbytes/s

Synchronous receive rate = (QCLK/SCF) /4 =
(160/1) /4 = 40 Mbytes/s

Divide by 4

Synchronous

Divider

Asynchronous

SCSI Logic

Receive

Clock

Send Clock

(to SCSI Bus)

2.2.15.2 SCSI Control Three (SCNTL3) Register, Bits [6:4] (SCF[2:0])

The SCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the synchronous SCSI control logic.
The output from this divider controls the rate at which data can be
received. This rate must not exceed 160 MHz. The receive rate of

SCSI Functional Description 2-41

synchronous SCSI data is one-fourth of the SCF divider output. For

*

example, if SCLK is 160 MHz and the SCF value is set to divide by one,
then the maximum rate at which data can be received is 40 MHz
(160/(1*4) = 40).

2.2.15.3 SCSI Control Three (SCNTL3) Register, Bits [2:0] (CCF[2:0])

The CCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the asynchronous SCSI core logic.
This divider must be set according to the input clock frequency in the
table.

2.2.15.4 SCSI Transfer (SXFER) Register, Bits [7:5] (TP[2:0])

The TP[2:0] divider bits determine the SCSI synchronous transfer period
when sending synchronous SCSI data in either the initiator or target
mode. This value further divides the output from the SCF divider.

2.2.15.5 Ultra2 SCSI Synchronous Data Transfers

Ultra2 SCSI is an extension of the current Ultra SCSI synchronous
transfer specifications. It allows synchronous transfer periods to be
negotiated down as low as 25 ns, which is half the 50 ns period allowed
under Ultra SCSI. This will allow a maximum transfer rate of 80 Mbytes/s
on a 16-bit, LVD SCSI bus. The LSI53C896 has a SCSI clock quadrupler
that must be enabled for the chip to perform Ultra2 SCSI transfers with
a 40 MHz oscillator. In addition, the following bit values affect the chip’s
ability to support Ultra2 SCSI synchronous transfer rates:

• Clock Conversion Factor bits, SCSI Control Three (SCNTL3) register

bits [2:0] and Synchronous Clock Conversion Factor bits, SCNTL3
register bits [6:4]. These fields support a value of 111 (binary),
allowing the 160 MHz SCLK frequency to be divided down by 8 for
the asynchronous logic.

• Ultra2 SCSI Enable bit, SCSI Control Three (SCNTL3) register bit 7.

Setting this bit enables Ultra2 SCSI synchronous transfers in
systems that use the internal SCSI clock quadrupler.

• TolerANT Enable bit, SCSI TestThree (STEST3) register bit 7. Active

negation must be enabled for the LSI53C896 to perform Ultra2 SCSI
transfers.

2-42 Functional Description

Note: The clock quadrupler requires a 40 MHz external clock.

*

LSI Logic software assumes that the LSI53C896 is
connected to a 40 MHz external clock, which is quadrupled
to achieve Ultra2 SCSI transfer rates.

2.2.16 Interrupt Handling

The SCRIPTS processors in the LSI53C896 perform most functions
independently of the host microprocessor. However, certain interrupt
situations must be handled by the external microprocessor. This section
explains all aspects of interrupts as they apply to the LSI53C896.

2.2.16.1 Polling and Hardware Interrupts

The external microprocessor is informed of an interrupt condition by
polling or hardware interrupts. Polling means that the microprocessor
must continually loop and read a register until it detects a bit that is set
indicating an interrupt. This method is the fastest, but it wastes CPU time
that could be used for other system tasks. The preferred method of
detecting interrupts in most systems is hardware interrupts. In this case,
the LSI53C896 asserts the Interrupt Request (INTA/ or INTB/) line that
interrupts the microprocessor, causing the microprocessor to execute an
interrupt service routine. A hybrid approach would use hardware
interrupts for long waits, and use polling for short waits.

SCSI Function A is routed to PCI Interrupt INTA/. SCSI Function B is
normally routed to INTB/, but can be routed to INTA/ if a pull-up is
connected to MAD[4]. See Section 3.7, “MAD Bus Programming,” for
additional information.

2.2.16.2 Registers

The registers in the LSI53C896 that are used for detecting or defining
interrupts are ISTAT, SCSI Interrupt Status Zero (SIST0), SCSI Interrupt

Status One (SIST1), SCSI Interrupt Enable Zero (SIEN0), SCSI Interrupt
Enable One (SIEN1), DMA Control (DCNTL), and DMA Interrupt Enable
(DIEN).

ISTAT – The ISTAT register includes the Interrupt Status Zero (ISTAT0),

Interrupt Status One (ISTAT1), Mailbox Zero (MBOX0), and Mailbox One
(MBOX1) registers. It is the only register that can be accessed as a slave

SCSI Functional Description 2-43

during the SCRIPTS operation. Therefore, it is the register that is polled

*

when polled interrupts are used. It is also the first register that should be
read after the INTA/ (or INTB/) pin is asserted in association with a
hardware interrupt. The INTF (Interrupt-on-the-Fly) bit should be the first
interrupt serviced. It must be written to one to be cleared. This interrupt
must be cleared before servicing any other interrupts.

See Register 0x14, Interrupt Status Zero (ISTAT0), Bit 5 signal process
in Chapter 4, “Registers,” for additional information.

The host (C Code) or the SCRIPTS code could potentially try to access
the mailbox bits at the same time.

If the SIP bit in the Interrupt Status Zero (ISTAT0) register is set, then a
SCSI-type interrupt has occurred and the SCSI Interrupt Status Zero

(SIST0) and SCSI Interrupt Status One (SIST1) registers should be read.

If the DIP bit in the Interrupt Status Zero (ISTAT0) register is set, then a
DMA-type interrupt has occurred and the DMA Status (DSTAT) register
should be read.

SCSI-type and DMA-type interrupts may occur simultaneously, so in
some cases both SIP and DIP may be set.

SIST0 and SIST1 – The SCSI Interrupt Status Zero (SIST0) and SCSI

Interrupt Status One (SIST1) registers contain SCSI-type interrupt bits.

Reading these registers determines which condition or conditions caused
the SCSI-type interrupt, and clears that SCSI interrupt condition.

If the LSI53C896 is receiving data from the SCSI bus and a fatal interrupt
condition occurs, the chip attempts to send the contents of the DMA
FIFO to memory before generating the interrupt.

If the LSI53C896 is sending data to the SCSI bus and a fatal SCSI
interrupt condition occurs, data could be left in the DMA FIFO. Because
of this the DMA FIFO Empty (DFE) bit in DMA Status (DSTAT) should be
checked.

If this bit is cleared, set the CLF (Clear DMA FIFO) and CSF (Clear SCSI
FIFO) bits before continuing. The CLF bit is bit 2 in Chip Test Three

(CTEST3). The CSF bit is bit 1 in SCSI Test Three (STEST3).

2-44 Functional Description

DSTAT – The DMA Status (DSTAT) register contains the DMA-type

*

interrupt bits. Reading this register determines which condition or
conditions caused the DMA-type interrupt, and clears that DMA interrupt
condition. Bit 7 in DSTAT, DFE, is purely a status bit; it will not generate
an interrupt under any circumstances and will not be cleared when read.
DMA interrupts flush neither the DMA nor SCSI FIFOs before generating
the interrupt, so the DFE bit in the DSTAT register should be checked
after any DMA interrupt.

If the DFE bit is cleared, then the FIFOs must be cleared by setting the
CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits, or flushed by
setting the FLF (Flush DMA FIFO) bit.

SIEN0 and SIEN1 – The SCSI Interrupt Enable Zero (SIEN0) and SCSI

Interrupt Enable One (SIEN1) registers are the interrupt enable registers

for the SCSI interrupts in SCSI Interrupt Status Zero (SIST0) and SCSI

Interrupt Status One (SIST1).

DIEN – The DMA Interrupt Enable (DIEN) register is the interrupt enable
register for DMA interrupts in DMA Status (DSTAT).

DMA Control (DCNTL) – When bit 1 in this register is set, the INTA/ (or

INTB/) pin is not asserted when an interrupt condition occurs. The
interrupt is not lost or ignored, but is merely masked at the pin. Clearing
this bit when an interrupt is pending immediately causes the INTA/ (or
INTB/) pin to assert. As with any register other than ISTAT, this register
cannot be accessed except by a SCRIPTS instruction during SCRIPTS
execution.

2.2.16.3 Fatal vs. Nonfatal Interrupts

A fatal interrupt, as the name implies, always causes the SCRIPTS to
stop running. All nonfatal interrupts become fatal when they are enabled
by setting the appropriate interrupt enable bit. Interrupt masking is
discussed in Section 2.2.16.4, “Masking.” All DMA interrupts (indicated
by the DIP bit in Interrupt Status Zero (ISTAT0) and one or more bits in

DMA Status (DSTAT) being set) are fatal.

Some SCSI interrupts (indicated by the SIP bit in the Interrupt Status

Zero (ISTAT0) and one or more bits in SCSI Interrupt Status Zero
(SIST0) or SCSI Interrupt Status One (SIST1) being set) are nonfatal.

SCSI Functional Description 2-45

2.2.16.4 Masking

*

When the LSI53C896 is operating in the Initiator mode, only the Function
Complete (CMP), Selected (SEL), Reselected (RSL), General Purpose
Timer Expired (GEN), and Handshake-to-Handshake Timer Expired
(HTH) interrupts are nonfatal.

When operating in the Target mode, CMP, SEL, RSL, Target mode:
SATN/ active (M/A), GEN, and HTH are nonfatal. Refer to the description
for the Disable Halt on a Parity Error or SATN/ active (Target Mode Only)
(DHP) bit in the SCSI Control One (SCNTL1) register to configure the
chip’s behavior when the SATN/ interrupt is enabled during Target mode
operation. The Interrupt-on-the-Fly interrupt is also nonfatal, since
SCRIPTS can continue when it occurs.

The reason for nonfatal interrupts is to prevent the SCRIPTS from
stopping when an interrupt occurs that does not require service from the
CPU. This prevents an interrupt when arbitration is complete (CMP set),
when the LSI53C896 is selected or reselected (SEL or RSL set), when
the initiator asserts ATN (target mode: SATN/ active), or when the
General Purpose or Handshake-to-Handshake timers expire. These
interrupts are not needed for events that occur during high-level
SCRIPTS operation.

Masking an interrupt means disabling or ignoring that interrupt. Interrupts
can be masked by clearing bits in the SCSI Interrupt Enable Zero

(SIEN0) and SCSI Interrupt Enable One (SIEN1) (for SCSI interrupts)

registers or DMA Interrupt Enable (DIEN) (for DMA interrupts) register.
How the chip responds to masked interrupts depends on: whether polling
or hardware interrupts are being used; whether the interrupt is fatal or
nonfatal; and whether the chip is operating in the Initiator or Target mode.

If a nonfatal interrupt is masked and that condition occurs, the SCRIPTS
do not stop, the appropriate bit in the SCSI Interrupt Status Zero (SIST0)
or SCSI Interrupt Status One (SIST1) is still set, the SIP bit in the

Interrupt Status Zero (ISTAT0) is not set, and the INTA/ (or INTB/) pin is

not asserted.

2-46 Functional Description

If a fatal interrupt is masked and that condition occurs, then the SCRIPTS

*

still stop, the appropriate bit in the DMA Status (DSTAT), SCSI Interrupt

Status Zero (SIST0),orSCSI Interrupt Status One (SIST1) register is

set, and the SIP or DIP bit in the Interrupt Status Zero (ISTAT0) register
is set, but the INTA/ (or INTB/) pin is not asserted.

Interrupts can be disabled by setting the SYNC_IRQD bit in the Interrupt

Status One (ISTAT1) register. If an interrupt is already asserted and

SYNC_IRQD is then set, the interrupt will remain until serviced. Further
interrupts will be blocked.

When the LSI53C896 is initialized, enable all fatal interrupts if hardware
interrupts are being used. If a fatal interrupt is disabled and that interrupt
condition occurs, the SCRIPTS halts and the system never knows it
unless it times out and checks the Interrupt Status Zero (ISTAT0),

Interrupt Status One (ISTAT1), Mailbox Zero (MBOX0), and Mailbox One
(MBOX1) registers after a certain period of inactivity.

If ISTAT is being polled instead of using hardware interrupts, then
masking a fatal interrupt makes no difference since the SIP and DIP bits
in the Interrupt Status Zero (ISTAT0) inform the system of interrupts, not
the INTA/ (or INTB/) pin.

Masking an interrupt after INTA/ (or INTB/) is asserted does not cause
deassertion of INTA/ (or INTB/).

2.2.16.5 Stacked Interrupts

The LSI53C896 will stack interrupts, if they occur, one after the other. If
the SIP or DIP bits in the Interrupt Status Zero (ISTAT0) register are set
(first level), then there is already at least one pending interrupt, and any
future interrupts are stacked in extra registers behind the SCSI Interrupt

Status Zero (SIST0), SCSI Interrupt Status One (SIST1), and DMA
Status (DSTAT) registers (second level). When two interrupts have

occurred and the two levels of the stack are full, any further interrupts
set additional bits in the extra registers behind SIST0, SIST1, and DSTAT.
When the first level of interrupts are cleared, all the interrupts that came
in afterward move into SIST0, SIST1, and DSTAT. After the first interrupt
is cleared by reading the appropriate register, the INTA/ (or INTB/) pin is
deasserted for a minimum of three CLKs; the stacked interrupts move
into SIST0, SIST1, or DSTAT; and the INTA/ (or INTB/) pin is asserted
once again.

SCSI Functional Description 2-47

Since a masked nonfatal interrupt does not set the SIP or DIP bits,

*

interrupt stacking does not occur. A masked, nonfatal interrupt still posts
the interrupt in SCSI Interrupt Status Zero (SIST0), but does not assert
the INTA/ (or INTB/) pin. Since no interrupt is generated, future interrupts
move into SIST0 or SCSI Interrupt Status One (SIST1) instead of being
stacked behind another interrupt. When another condition occurs that
generates an interrupt, the bit corresponding to the earlier masked
nonfatal interrupt is still set.

A related situation to interrupt stacking is when two interrupts occur
simultaneously. Since stacking does not occur until the SIP or DIP bits
are set, there is a small timing window in which multiple interrupts can
occur but are not stacked. These could be multiple SCSI interrupts (SIP
set), multiple DMA interrupts (DIP set), or multiple SCSI and multiple
DMA interrupts (both SIP and DIP set).

As previously mentioned, DMA interrupts do not attempt to flush the
FIFOs before generating the interrupt. It is important to set either the
Clear DMA FIFO (CLF) and Clear SCSI FIFO (CSF) bits if a DMA
interrupt occurs and the DMA FIFO Empty (DFE) bit is not set. This is
because any future SCSI interrupts are not posted until the DMA FIFO
is cleared of data. These ‘locked out’ SCSI interrupts are posted as soon
as the DMA FIFO is empty.

2.2.16.6 Halting in an Orderly Fashion

When an interrupt occurs, the LSI53C896 attempts to halt in an orderly
fashion.

• If the interrupt occurs in the middle of an instruction fetch, the fetch

is completed, except in the case of a Bus Fault. Execution does not
begin, but the DSP points to the next instruction since it is updated
when the current instruction is fetched.

• If the DMA direction is a write to memory and a SCSI interrupt

occurs, the LSI53C896 attempts to flush the DMA FIFO to memory
before halting. Under any other circumstances only the current cycle
is completed before halting, so the DFE bit in DMA Status (DSTAT)
should be checked to see if any data remains in the DMA FIFO.

• SCSI SREQ/SACK handshakes that have begun are completed

before halting.

2-48 Functional Description

• The LSI53C896 attempts to clean up any outstanding synchronous

*

offset before halting.

• In the case of Transfer Control Instructions, once instruction

execution begins it continues to completion before halting.

• If the instruction is a JUMP/CALL WHEN/IF <phase>, the DMA

SCRIPTS Pointer (DSP) is updated to the transfer address before

halting.

• All other instructions may halt before completion.

2.2.16.7 Sample Interrupt Service Routine

The following is a sample of an interrupt service routine for the
LSI53C896. It can be repeated if polling is used, or should be called
when the INTA/ (or INTB/) pin is asserted if hardware interrupts are used.

1. Read Interrupt Status Zero (ISTAT0).

2. If the INTF bit is set, it must be written to a one to clear this status.

3. If only the SIP bit is set, read SCSI Interrupt Status Zero (SIST0) and

SCSI Interrupt Status One (SIST1) to clear the SCSI interrupt

condition and get the SCSI interrupt status. The bits in the SIST0
and SIST1 tell which SCSI interrupts occurred and determine what
action is required to service the interrupts.

4. If only the DIP bit is set, read DMA Status (DSTAT) to clear the
interrupt condition and get the DMA interrupt status. The bits in
DSTAT tell which DMA interrupts occurred and determine what action
is required to service the interrupts.

5. If both the SIP and DIP bits are set, read SCSI Interrupt Status Zero

(SIST0), SCSI Interrupt Status One (SIST1), and DMA Status
(DSTAT) to clear the SCSI and DMA interrupt condition and get the

interrupt status. If using 8-bit reads of the SIST0, SIST1, and DSTAT
registers to clear interrupts, insert a 12 clock delay between the
consecutive reads to ensure that the interrupts clear properly. Both
the SCSI and DMA interrupt conditions should be handled before
leaving the Interrupt Service Routine. It is recommended that the
DMA interrupt is serviced before the SCSI interrupt, because a
serious DMA interrupt condition could influence how the SCSI
interrupt is acted upon.

SCSI Functional Description 2-49

6. When using polled interrupts go back to step 1 before leaving the

*

interrupt service routine in case any stacked interrupts moved in
when the first interrupt was cleared. When using hardware interrupts,
the INTA/ (or INTB/) pin is asserted again if there are any stacked
interrupts. This should cause the system to re-enter the interrupt
service routine.

2.2.17 Interrupt Routing

This section documents the recommended approach to RAID ready
interrupt routing for the LSI53C896. In order to be compatible with AMI
RAID upgrade products and the LSI53C896, the following requirements
must be met:

• When a RAID upgrade card is installed in the upgrade slot, interrupts

from the mainboard SCSI controller(s) assigned to the RAID upgrade
card must be routed to INTC/ and INTD/ of the upgrade slot and
isolated from the mainboard interrupt controller. The system
processor must not see interrupts from the SCSI controllers that are
to be serviced by the RAID upgrade card. An upgrade slot is one that
is connected to the interrupt routing logic for mainboard SCSI
device(s). When a PCI RAID upgrade board is installed into the
system, it would be plugged into this slot if it is to control mainboard
SCSI device(s).

• The TDI pin of the upgrade slot must be connected to the INT_DIR/

pin of the LSI53C896.

• When a RAID upgrade card is not installed, interrupts from a SCSI

core must not be presented to the system’s interrupt controller using
multiple interrupt inputs.

Figure 2.8 shows an example configuration. In this example the

LSI53C896 Dual Channel Ultra2 SCSI Controller contains the interrupt
routing logic.

The LSI53C896 supports four different interrupt routing modes.
Additional information for these modes may be found in register 0x4D,

SCSI Test One (STEST1) description in Chapter 4, “Registers.” Each

SCSI core within the chip may be configured independently. The interrupt
routing mode is selected using bits [1:0] in the STEST1 register within
each core. Mode 0 is the default mode and is compatible with AMI RAID
upgrade products.

2-50 Functional Description

If the implementation shown in Figure 2.8 is used, INTC/ and INTD/ of

*

the PCI RAID upgrade slot cannot be used when a non-RAID upgrade
card is installed in the slot. If this restriction is not acceptable, additional
buffer logic must be implemented on the mainboard. As long as the
interrupt routing requirements stated above are satisfied, a mainboard
designer could implement this design with external logic.

Figure 2.8 Interrupt Routing Hardware Using the LSI53C896

+ 5 V

INT_DIR

LSI53C896

SCSI Core

I

SCSI Core

II

10 K

2.7 K

ALT_INTA/

INTA/

ALT_INTB/

INTB/

+ 5 V

2.7 K

PCI RAID UPGRADE SLOT

A4

+ 5 V

INTB/

INTD/

B7
B8

A6
A7

MB SCSI INTA/
MB SCSI INTB/

TDI
INTA/

INTC/

PCI RAID
Upgrade
Slot INTA/

PCI RAID
Upgrade
Slot INTB/

These interrupt lines are
connected to the other PCI
slot interrupt lines as
determined by the
mainboard interrupt
routing scheme.

There can only be one entity controlling a mainboard SCSI core or
conflicts will occur. Typically a SCSI core will be controlled by the SCSI
BIOS and an operating system driver. When a SCSI core is allocated to
a RAID adapter, however, a mechanism must be implemented to prevent
the SCSI BIOS and operating system driver from trying to access the
SCSI core. The mainboard designer has several options to choose from
for doing this.

The first option is to have the SCSI core load its PCI Subsystem ID using
a serial EPROM on power-up. If bit 15 in this ID is set, the LSI Logic
BIOS and operating system drivers will ignore the chip. This makes it
possible to control the assignment of the mainboard SCSI cores using a
configuration utility.

SCSI Functional Description 2-51

The second option is to provide mainboard and system BIOS support for

*

NVS. The SCSI core may then be enabled or disabled using the SCSI
BIOS configuration utility. Not all versions of the LSI Logic drivers support
this capability.

The third option is to have the system BIOS not report the existence of
the SCSI controller chips when the SCSI BIOS and operating systems
make PCI BIOS calls. This approach requires modifications to the
system BIOS and assumes the operating system uses PCI BIOS calls
when searching for PCI devices.

2.2.18 Chained Block Moves

Since the LSI53C896 has the capability to transfer 16-bit wide SCSI
data, a unique situation occurs when dealing with odd bytes. The
Chained Move (CHMOV) SCRIPTS instruction along with the Wide SCSI
Send (WSS) and Wide SCSI Receive (WSR) bits in the SCSI Control

Two (SCNTL2) register are used to facilitate these situations. The

Chained Block Move instruction is illustrated in Figure 2.9.

2-52 Functional Description

Figure 2.9 Block Move and Chained Block Move Instructions

*

Host Memory SCSI Bus

0x03 0x02 0x01 0x00

0x07 0x06 0x05 0x04

0x0B 0x0A 0x09 0x08

0x0F 0x0E 0x0D 0x0C

0x13 0x12 0x11 0x10

32 Bits 16 Bits

00

04

08

0C

10

0x04 0x03

0x06 0x05

0x09 0x07

0x0B 0x0A

0x0D 0x0C

CHMOV 5, 3 when Data_Out
Moves five bytes from address 0x03 in the host memory to the SCSI bus.

Bytes 0x03, 0x04, 0x05, and 0x06 are moved and byte 0x07 remains in
the low-order byte of the SCSI Output Data Latch (SODL) register and
is combined with the first byte of the following MOVE instruction.

Move 5, 9 when Data_Out
Moves five bytes from address 0x09 in the host memory to the SCSI bus.

2.2.18.1 Wide SCSI Send Bit

The WSS bit is set whenever the SCSI controller is sending data
(Data-Out for the initiator or Data-In for the target) and the controller
detects a partial transfer at the end of a chained Block Move SCRIPTS
instruction (this flag is not set if a normal Block Move instruction is used).
Under this condition, the SCSI controller does not send the low-order
byte of the last partial memory transfer across the SCSI bus. Instead, the
low-order byte is temporarily stored in the lower byte of the SCSI Output

Data Latch (SODL) register and the WSS flag is set. The hardware uses

the WSS flag to determine what behavior must occur at the start of the
next data send transfer. When the WSS flag is set at the start of the next

SCSI Functional Description 2-53

transfer, the first byte (the high-order byte) of the next data send transfer

*

is “married” with the stored low-order byte in the SODL register; and the
two bytes are sent out across the bus, regardless of the type of Block
Move instruction (normal or chained). The flag is automatically cleared
when the “married” word is sent. The flag is alternately cleared through
SCRIPTS or by the microprocessor. Also, the microprocessor or
SCRIPTS can use this bit for error detection and recovery purposes.

2.2.18.2 Wide SCSI Receive Bit

The WSR bit is set whenever the SCSI controller is receiving data
(Data-In for the initiator or Data-Out for the target) and the controller
detects a partial transfer at the end of a block move or chained block
move SCRIPTS instruction. When WSR is set, the high-order byte of the
last SCSI bus transfer is not transferred to memory. Instead, the byte is
temporarily stored in the SCSI Wide Residue (SWIDE) register. The
hardware uses the WSR bit to determine what behavior must occur at
the start of the next data receive transfer. The bit is automatically cleared
at the start of the next data receive transfer. The bit can alternatively be
cleared by the microprocessor or through SCRIPTS. Also, the
microprocessor or SCRIPTS can use this bit for error detection and
recovery purposes.

2.2.18.3 SWIDE Register

This register is used to store data for partial byte data transfers. For
receive data, the SCSI Wide Residue (SWIDE) register holds the
high-order byte of a partial SCSI transfer which has not yet been
transferred to memory. This stored data may be a residue byte (and
therefore ignored) or it may be valid data that is transferred to memory
at the beginning of the next Block Move instruction.

2.2.18.4 SODL Register

For send data, the low-order byte of the SCSI Output Data Latch (SODL)
register holds the low-order byte of a partial memory transfer which has
not yet been transferred across the SCSI bus. This stored data is usually
“married” with the first byte of the next data send transfer, and both bytes
are sent across the SCSI bus at the start of the next data send block
move command.

2-54 Functional Description

2.2.18.5 Chained Block Move SCRIPTS Instruction

*

A chained Block Move SCRIPTS instruction is primarily used to transfer
consecutive data send or data receive blocks. Using the chained Block
Move instruction facilitates partial receive transfers and allows correct
partial send behavior without additional opcode overhead. Behavior of
the chained Block Move instruction varies slightly for sending and
receiving data.

For receive data (Data-In for the initiator or Data-Out for the target), a
chained Block Move instruction indicates that if a partial transfer occurred
at the end of the instruction, the WSR flag is set. The high-order byte of
the last SCSI transfer is stored in the SCSI Wide Residue (SWIDE)
register rather than transferred to memory. The contents of the SWIDE
register should be the first byte transferred to memory at the start of the
chained Block Move data stream. Since the byte count always represents
data transfers to/from memory (as opposed to the SCSI bus), the byte
transferred out of the SCSI Wide Residue (SWIDE) register is one of the
bytes in the byte count. If the WSR bit is cleared when a receive data
chained Block Move instruction is executed, the data transfer occurs
similar to that of the regular Block Move instruction. Whether the WSR
bit is set or cleared, when a normal block move instruction is executed,
the contents of the SWIDE register are ignored and the transfer takes
place normally. For “N” consecutive wide data receive Block Move
instructions, the 2nd through the Nth Block Move instructions should be
chained block moves.

For send data (Data-Out for the initiator or Data-In for the target), a
chained Block Move instruction indicates that if a partial transfer
terminates the chained block move instruction, the last low-order byte
(the partial memory transfer) should be stored in the lower byte of the

SCSI Output Data Latch (SODL) register and not sent across the SCSI

bus. Without the chained Block Move instruction, the last low-order byte
would be sent across the SCSI bus. The starting byte count represents
data bytes transferred from memory but not to the SCSI bus when a
partial transfer exists. For example, if the instruction is an Initiator
chained Block Move Data Out of five bytes (and WSS is not previously
set), five bytes are transferred out of memory to the SCSI controller, four
bytes are transferred from the SCSI controller across the SCSI bus, and
one byte is temporarily stored in the lower byte of the SODL register
waiting to be married with the first byte of the next Block Move
instruction. Regardless of whether a chained Block Move or normal Block

SCSI Functional Description 2-55

Move instruction is used, if the WSS bit is set at the start of a data send

*

command, the first byte of the data send command is assumed to be the
high-order byte and is “married” with the low-order byte stored in the
lower byte of the SODL register before the two bytes are sent across the
SCSI bus. For “N” consecutive wide data send Block Move commands,
the first through the (N
Block Moves.

2.3 Parallel ROM Interface

The LSI53C896 supports up to one megabyte of external memory in
binary increments from 16 Kbytes to allow the use of expansion ROM for
add-in PCI cards. Both functions of the device share the ROM interface.
This interface is designed for low speed operations such as downloading
instruction code from ROM. It is not intended for dynamic activities such
as executing instructions.

System requirements include the LSI53C896, two or three external
8-bit address holding registers (HCT273 or HCT374), and the
appropriate memory device. The 4.7 kΩ pull-up resistors on the MAD bus
require HC or HCT external components to be used. If in-system Flash
ROM updates are required, a 7406 (high voltage open collector inverter),
a MTD4P05, and several passive components are also needed. The
memory size and speed is determined by pull-up resistors on the
8-bit bidirectional memory bus at power-up. The LSI53C896 senses this
bus shortly after the release of the Reset signal and configures the

Expansion ROM Base Address register and the memory cycle state

machines for the appropriate conditions.

th

− 1) Block Move instructions should be Chained

The external memory interface works with a variety of ROM sizes and
speeds. An example set of interface drawings is in Appendix B, “External

Memory Interface Diagram Examples.”

The LSI53C896 supports a variety of sizes and speeds of expansion
ROM, using pull-down resistors on the MAD[3:0] pins. The encoding of
pins MAD[3:1] allows the user to define how much external memory is

2-56 Functional Description

available to the LSI53C896. Table 2.7 shows the memory space

*

associated with the possible values of MAD[3:1]. The MAD[3:1] pins are
fully described in Chapter 3, “Signal Descriptions.”

Table 2.7 Parallel ROM Support

MAD[3:1] Available Memory Space

000 16 Kbytes
001 32 Kbytes
010 64 Kbytes
011 128 Kbytes
100 256 Kbytes
101 512 Kbytes
110 1024 Kbytes
111 no external memory present

To use one of the configurations mentioned above in a host adapter
board design, put 4.7 kΩ pull-up resistors on the MAD pins
corresponding to the available memory space. For example, to connect
to a 64 Kbytes external ROM, use a pull-up on MAD[2]. If the external
memory interface is not used, MAD[3:1] should be pulled HIGH.

Note: There are internal pull-downs on all of the MAD bus

signals.

The LSI53C896 allows the system to determine the size of the available
external memory using the Expansion ROM Base Address register in the
PCI configuration space. For more information on how this works, refer
to the PCI specification or the Expansion ROM Base Address register
description in Chapter 4, “Registers.”

MAD[0] is the slow ROM pin. When pulled up, it enables two extra clock
cycles of data access time to allow use of slower memory devices. The
external memory interface also supports updates to flash memory.

Parallel ROM Interface 2-57

2.4 Serial EEPROM Interface

*

The LSI53C896 implements an interface that allows attachment of a
serial EEPROM device to the GPIO0 and GPIO1 pins for each SCSI
function. There are two modes of operation relating to the serial
EEPROM and the Subsystem ID and Subsystem Vendor ID registers for
each SCSI function. These modes are programmable through the
MAD[7] pin which is sampled at power-up or hard reset.

2.4.1 Default Download Mode

In this mode, MAD[7] is pulled down internally, GPIO0 is the serial data
signal (SDA) and GPIO1 is the serial clock signal (SCL). Certain data in
the serial EEPROM is automatically loaded into chip registers at
power-up or hard reset.

The format of the serial EEPROM data is defined in Table 2.8. If the
download is enabled and an EEPROM is not present, or the checksum
fails, the Subsystem ID and Subsystem Vendor ID registers read back all
zeros. At power-up or hard reset, only five bytes are loaded into the chip
from locations 0xFB through 0xFF.

The Subsystem ID and Subsystem Vendor ID registers are read only, in
accordance with the PCI specification, with a default value of all zeros if
the download fails.

2-58 Functional Description

Table 2.8 Mode A Serial EEPROM Data Format

*

Byte Name Description

0xFB SVID(0) Subsystem Vendor ID, LSB. This byte is loaded into the least significant

0xFC SVID(1) Subsystem Vendor ID, MSB. This byte is loaded into the most significant

0xFD SID(0) Subsystem ID, LSB. This byte is loaded into the least significant byte of

0xFE SID(1) Subsystem ID, MSB. This byte is loaded into the most significant byte

0xFF CKSUM Checksum. This 8-bit checksum is formed by adding, bytewise, each

0x100–EOM UD User Data.

byte of the Subsystem Vendor ID register in the appropriate PCI
configuration space at chip power-up or hard reset.

byte of the Subsystem Vendor ID register in the appropriate PCI
configuration space at chip power-up or hard reset.

the Subsystem ID register in the appropriate PCI configuration space at
chip power-up or hard reset.

of the Subsystem ID register in the appropriate PCI configuration space
at chip power-up or hard reset.

byte contained in locations 0x00–0x03 to the seed value 0x55, and then
taking the 2s complement of the result.

2.4.2 No Download Mode

When MAD[7] is pulled up through an external resistor, the automatic
download is disabled and no data is automatically loaded into chip
registers at power-up or hard reset. The Subsystem ID and Subsystem

Vendor ID registers are read only, per the PCI specification, with a default

value of 0x1000 and 0x1000 respectively.

2.5 Power Management

The LSI53C896 complies with the PCI Bus Power Management Interface
Specification, Revision 1.1. The PCI Function Power States D0, D1, D2,
and D3 are defined in that specification.

D0 is the maximum powered state, and D3 is the minimum powered
state. Power state D3 is further categorized as D3hot or D3cold. A
function that is powered off is said to be in the D3cold power state.

Power Management 2-59

The LSI53C896 power states shown in Table 2.9 are independently

*

controlled through two power state bits that are located in the PCI
Configuration Space Power Management Control/Status (PMCSR)
register 0x44–0x45.

Table 2.9 Power States

Configuration
Register 0x44

Bits [1:0] Power State Function

00 D0 Maximum Power
01 D1 Disables SCSI clock
10 D2 Coma Mode
11 D3 Minimum Power

Although the PCI Bus Power Management Interface Specification does
not allow power state transitions D2 to D1, D3 to D2, or D3 to D1, the
LSI53C896 hardware places no restriction on transitions between power
states.

The PCI Function Power States D0, D1, D2, and D3 are described below
in conjunction with each SCSI function. Power state actions are separate
for each function.

As the device transitions from one power level to a lower one, the
attributes that occur from the higher power state level are carried over
into the lower power state level. For example, D1 disables the SCSI CLK.
Therefore, D2 will include this attribute as well as the attributes defined
in the Power State D2 section. The PCI Function Power States - D0, D1,
D2, and D3 are described below in conjunction with each SCSI function.
Power state actions are separate for each function.

2.5.1 Power State D0

Power state D0 is the maximum power state and is the power-up default
state for each function. The LSI53C896 is fully functional in this state.

2-60 Functional Description

2.5.2 Power State D1

*

Power state D1 is a lower power state than D0. A function in this state
places the LSI53C896 core in the snooze mode and disables the SCSI
CLK. In the snooze mode, a SCSI reset does not generate an IRQ/
signal.

2.5.3 Power State D2

Power state D2 is a lower power state than D1. A function in this state
places the LSI53C896 core in the coma mode. The following PCI
Configuration Space Command register enable bits are suppressed:

• I/O Space Enable

• Memory Space Enable

• Bus Mastering Enable

• SERR/Enable

• Enable Parity Error Response

Thus, the function's memory and I/O spaces cannot be accessed, and
the function cannot be a PCI bus master. Furthermore, SCSI and DMA
interrupts are disabled when the function is in power state D2. If the
function is changed from power state D2 to power state D1 or D0, the
previous values of the PCI Command register are restored. Also, any
pending interrupts before the function entered power state D2 are
asserted.

2.5.4 Power State D3

Power state D3 is the minimum power state, which includes settings
called D3hot and D3cold. D3hot allows the device to transition to D0
using software. The LSI53C896 is considered to be in power state
D3cold when power is removed from the device. D3cold can transition to
D0 by applying VCCand resetting the device.

Power state D3 is a lower power level than power state D2. A function in
this state places the LSI53C896 core in the coma mode. Furthermore,
the function's soft reset is continually asserted while in power state D3,
which clears all pending interrupts and 3-states the SCSI bus. In
addition, the function's PCI Command register is cleared. If both of the
LSI53C896 functions are placed in power state D3, the Clock Quadrupler
is disabled, which results in additional power savings.

Power Management 2-61

2-62 Functional Description

*

Chapter 3

*

Signal Descriptions

This chapter presents the LSI53C896 pin configuration and signal
definitions using tables and illustrations. Figure 3.1 is the functional
signal grouping. The signal descriptions begin with Table 3.2. The signal
descriptions are organized into functional groups:

• Section 3.1, “Internal Pull-ups on LSI53C896 Signals”

• Section 3.2, “PCI Bus Interface Signals”

• Section 3.3, “SCSI Bus Interface Signals”

• Section 3.4, “Flash ROM and Memory Interface Signals”

• Section 3.5, “Test Interface Signals”

• Section 3.6, “Power and Ground Signals”

• Section 3.7, “MAD Bus Programming”

The PCI Interface signals are divided into the following functional groups:

System Signals, Address and Data Signals, Interface Control Signals,
Arbitration Signals, Error Reporting Signals, Interrupt Signals, SCSI
Function A GPIO Signals, and SCSI Function B GPIO Signals.

The SCSI Bus Interface signals are divided into SCSI Function A

Signals, and SCSI Function B Signals groups.

A slash (/) at the end of a signal name indicates that the active state
occurs when the signal is at a LOW voltage. When the slash is absent,
the signal is active at a HIGH voltage.

LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller 3-1

Figure 3.1 LSI53C896 Functional Signal Grouping

*

PCI

Bus

Interface

System

Address

and

Data

Interface

Control

Arbitration

Error

Reporting

Interrupt

SCSI

Function

GPIO

SCSI

Function

GPIO

ROM

Flash

and

Memory

Interface

CLK
RST/

AD[63:0]
C_BE[7:0]
PAR
PAR64

ACK64/
REQ64/
FRAME/
TRDY/
IRDY/
STOP/
DEVSEL/
IDSEL

REQ/
GNT/

PERR/
SERR/

INTA/
INTB/
ALT_INTA/
ALT_INTB/
INT_DIR

A_GPIO0_FETCH/
A_GPIO1_MASTER/

A

B

A_GPIO2
A_GPIO3
A_GPIO4

B_GPIO0_FETCH/
B_GPIO1_MASTER/
B_GPIO2
B_GPIO3
B_GPIO4

MWE/
MCE/
MOE/_TESTOUT
MAS0/
MAS1/
MAD[7:0]

LSI53C896

A_SCTRL/

B_SCTRL/

SCLK

A_SD[15:0]/

A_SDP[1:0]/

A_DIFFSENS

A_SC_D/

A_SI_O/

A_SMSG/

A_SREQ/

A_SREQ2/

A_SACK/

A_SACK2/

A_SBSY/

A_SATN/

A_SRST/

A_SSEL/

B_SD[15:0]/

B_SDP[1:0]/

B_DIFFSENS

B_SC_D/

B_SI_O/

B_SMSG/

B_SREQ/

B_SREQ2/

B_SACK/

B_SACK2/

B_SBSY/

B_SATN/

B_SRST/

B_SSEL/

TEST_HSC

TEST_RST/

MOE/_TESTOUT

TCK

TMS

TDI

TDO

SCSI
Function
A

SCSI
Bus
Interface

SCSI
Function
B

Test
Interface

3-2 Signal Descriptions

There are five signal type definitions:

*

I Input, a standard input-only signal.
O Output, a standard output driver (typically a Totem Pole Output).
I/O Input and output (bidirectional).
T/S 3-state, a bidirectional, 3-state input/output signal.
S/T/S Sustained 3-state, an active LOW 3-state signal owned and driven by

one and only one agent at a time.

3-3

3.1 Internal Pull-ups on LSI53C896 Signals

*

Several LSI53C896 signals use internal pull-ups and pull-downs.

Table 3.1 describes the conditions that enable these pull-ups and

pull-downs.

Table 3.1 LSI53C896 Internal Pull-ups and Pull-downs

Pin Name

INTA/, INTB/, ALT_INTA/,
ALT_INTB/

INT_DIR, TCK, TDI,
TEST_RST/, TMS

AD[63:32], C_BE[7:4], PAR64 25 µA Pulled up internally if not used.
GPIO[4:0] −25 µA Pulled down internally when configured as inputs.
MAD[7:0] −25 µA Pulled down internally.
TDO, TEST_HSC −25 µA Pulled down internally.

1. When bit 3 of DMA Control (DCNTL) is set, the pad becomes a totem pole output pad and will
drive both HIGH and LOW.

Pull-up
current Conditions for Pull-up

25 µA Pull-up enabled when the “AND-tree” mode is

enabled by driving TEST_RST/ LOW or when the
IRQ mode bit (bit 3 of DCNTL, 0X3B) is cleared.

25 µA Pulled up internally.

1

3-4 Signal Descriptions

3.2 PCI Bus Interface Signals

*

The PCI Bus Interface Signals section contains tables describing the
signals for the following signal groups: System Signals, Address and

Data Signals, Interface Control Signals, Arbitration Signals, Error
Reporting Signals, Interrupt Signals, SCSI Function A GPIO Signals, and
SCSI Function B GPIO Signals.

3.2.1 System Signals

Table 3.2 describes the signals for the System Signals group.

Table 3.2 System Signals

Name Bump Type Strength Description

CLK H3 I N/A Clock provides timing for all transactions on the PCI bus and

RST/ G1 I N/A Reset forces the PCI sequencer of each device to a known

is an input to every PCI device. All other PCI signals are
sampled on the rising edge of CLK, and other timing
parameters are defined with respect to this edge. Clock can
optionally serve as the SCSI core clock, but this may effect fast
SCSI-2 (or faster) transfer rates.

state. All T/S and S/T/S signals are forced to a high impedance
state, and all internal logic is reset. The RST/ input is
synchronized internally to the rising edge of CLK. The CLK
input must be active while RST/ is active to properly reset the
device.

PCI Bus Interface Signals 3-5

3.2.2 Address and Data Signals

*

Table 3.3 describes the signals for the Address and Data Signals group.

Table 3.3 Address and Data Signals

Name Bump Type Strength Description

AD[63:0] Y5, AB5, AC5, AA6,

Y6, AB6, AC6, AA7,
AB7, AC7, AA8, Y8,
AB8, AC8, AA9, Y9,
AB9, AC9, AA10,
Y11, AB10, AC10,
AA11, AC11, AB11,
AC12, AA12, AB12,
AB13, AC13, AA13,
AC14, H1, J3, J4,
J2, J1, K3, L4, K2,
L1, L2, M1, M3, M2,
N2, N1, N3, T4, T3,
U1-U3, V1, V2, V4,
W1, W2, W4, W3,
Y1, Y2, AA1, Y3.

C_BE[7:0]/ AA4, AC3, AB4,

AC4, K1, P1, T2, V3.

T/S 16 mA

PCI

T/S 16 mA

PCI

Physical Dword Address and Data are
multiplexed on the same PCI pins. A bus
transaction consists of an address phase
followed by one or more data phases.
During the first clock of a transaction,
AD[63:0] contain a 64-bit physical byte
address. If the command is a DAC,
implying a 64-bit address, AD[31:0] will
contain the upper 32 bits of the address
during the second clock of the
transaction. During subsequent clocks,
AD[63:0] contain data. PCI supports both
read and write bursts. AD[7:0] define the
least significant byte, and AD[63:56]
define the most significant byte.

Bus Command and Byte Enables are
multiplexed on the same PCI pins.
During the address phase of a
transaction, C_BE[3:0]/ define the bus
command. If the transaction is a DAC,
C_BE[3:0]/ contain the DAC command
and C_BE[7:4]/ define the bus command.
C_BE[3:0]/ define the bus command
during the second clock of the
transaction. During the data phase,
C_BE[7:0]/ are used as byte enables.
The byte enables determine which byte
lanes carry meaningful data. C_BE[0]/
applies to byte 0, and C_BE[7]/ to byte 7.

PAR T1 T/S 16 mA

PCI

3-6 Signal Descriptions

Parity is the even parity bit that protects
the AD[31:0] and C_BE[3:0]/ lines.
During the address phase, both the
address and command bits are covered.
During data phase, both data and byte
enables are covered.

Table 3.3 Address and Data Signals (Cont.)

*

Name Bump Type Strength Description

PAR64 AA5 T/S 16 mA

PCI

3.2.3 Interface Control Signals

Table 3.4 describes the signals for the Interface Control Signals group.

Table 3.4 Interface Control Signals

Name Bump Type Strength Description

ACK64/ AB1 S/T/S 16 mA

PCI

REQ64/ AA2 S/T/S 16 mA

PCI

FRAME/ P2 S/T/S 16 mA

PCI

TRDY/ P3 S/T/S 16 mA

PCI

Acknowledge 64-bit transfer is driven by the current bus
target to indicate its ability to transfer 64-bit data.

Request 64-bit transfer is driven by the current bus master
to indicate a request to transfer 64-bit data.

Cycle Frame is driven by the current master to indicate the
beginning and duration of an access. FRAME/ is asserted
to indicate that a bus transaction is beginning. While
FRAME/ is deasserted, either the transaction is in the final
data phase or the bus is idle.

Target Ready indicates the target agent’s (selected
device’s) ability to complete the current data phase of the
transaction. TRDY/ is used with IRDY/. A data phase is
completed on any clock when used with IRDY/. A data
phase is completed on any clock when both TRDY/ and
IRDY/ are sampled asserted. During a read, TRDY/
indicates that valid data is present on AD[31:0]. During a
write, it indicates that the target is prepared to accept data.
Wait cycles are inserted until both IRDY/ and TRDY/ are
asserted together.

Parity64 is the even parity bit that
protects the AD[63:32] and C_BE[7:4]/
lines. During address phase, both the
address and command bits are covered.
During data phase, both data and byte
enables are covered.

IRDY/ N4 S/T/S 16 mA

PCI

PCI Bus Interface Signals 3-7

Initiator Ready indicates the initiating agent’s (bus
master’s) ability to complete the current data phase of the
transaction. IRDY/ is used with TRDY/. A data phase is
completed on any clock when both IRDY/ and TRDY/ are
sampled asserted. During a write, IRDY/ indicates that valid
data is present on AD[31:0]. During a read, it indicates that
the master is prepared to accept data. Wait cycles are
inserted until both IRDY/ and TRDY/ are asserted together.

Table 3.4 Interface Control Signals (Cont.)

*

Name Bump Type Strength Description

STOP/ R2 S/T/S 16 mA

PCI

DEVSEL/ R1 S/T/S 16 mA

PCI

IDSEL L3 I N/A Initialization Device Select is used as a chip select in

Stop indicates that the selected target is requesting the
master to stop the current transaction.

Device Select indicates that the driving device has
decoded its address as the target of the current access. As
an input, it indicates to a master whether any device on the
bus has been selected.

place of the upper 24 address lines during configuration
read and write transactions.

3.2.4 Arbitration Signals

Table 3.5 describes the signals for the Arbitration Signals group.

Table 3.5 Arbitration Signals

Name Bump Type Strength Description

REQ/ H2 O 16 mA

PCI

GNT/ H4 I N/A Grant indicates to the agent that access to the PCI bus has

Request indicates to the system arbiter that this agent
desires use of the PCI bus. This is a point-to-point signal.
Both SCSI functions share the REQ/ signal.

been granted. This is a point-to-point signal. Both SCSI
functions share the GNT/ signal.

3-8 Signal Descriptions

3.2.5 Error Reporting Signals

*

Table 3.6 describes the signals for the Error Reporting Signals group.

Table 3.6 Error Reporting Signals

Name Bump Type Strength Description

PERR/ R4 S/T/S 16 mA

PCI

SERR/ R3 O 16 mA

PCI

Parity Error may be pulsed active by an agent that detects
a data parity error. PERR/ can be used by any agent to
signal data corruption. However, on detection of a PERR/
pulse, the central resource may generate a nonmaskable
interrupt to the host CPU, which often implies the system is
unable to continue operation once error processing is
complete.

System Error is an open drain output used to report
address parity errors as well as critical errors other than
parity.

PCI Bus Interface Signals 3-9

3.2.6 Interrupt Signals

*

Table 3.7 describes the Interrupt Signals group.

Table 3.7 Interrupt Signals

1

Name

Bump Type Strength Description

INTA/ F4 O 16 mA

PCI

INTB/ F2 O 16 mA

PCI

ALT_INTA/ F1 O 16 mA

PCI

ALT_INTB/ G3 O 16 mA

PCI

INT_DIR G2 I N/A Interrupt Direction. This input signal indicates whether

1. See Register 0x4D, SCSI Test One (STEST1) in Chapter 4, “Registers,” for additional information
on these signals.

Interrupt Function A. This signal, when asserted LOW,
indicates an interrupting condition in SCSI Function A and
that service is required from the host CPU. The output drive
of this pin is open drain. If the SCSI Function B interrupt is
rerouted at power-up using the INTA/ enable sense resistor
(pull-up on MAD[4]), this signal indicates that an interrupting
condition has occurred in either the SCSI Function A or
SCSI Function B. This interrupt pin is disabled if INT_DIR is
driven LOW.

Interrupt Function B. This signal, when asserted LOW,
indicates an interrupting condition has occurred in the SCSI
Function B and that service is required from the host CPU.
The output drive of this pin is open drain. This interrupt can
be rerouted to INTA/ at power-up using the INTA/ enable
sense resistor (pull-up on MAD[4]). This causes the
LSI53C896 to program the SCSI Function B PCI Interrupt
Pin register (0x3D) to 0x01. This interrupt pin is disabled if
INT_DIR is driven LOW.

Alt Interrupt Function A. When asserted LOW, it indicates
an interrupting condition has occurred in SCSI Function A.
The output drive of this pin is open drain. If the SCSI
Function B interrupt was rerouted at power-up using the
INTA/ enable sense resistor (pull-up on MAD[4]), this signal
indicates that an interrupting condition has occurred in
either the SCSI Function A or SCSI Function B.

Alt Interrupt Function B. When asserted LOW, indicates
an interrupting condition has occurred in SCSI Function B.
The output drive of this pin is open drain. This interrupt can
be rerouted to INTA/ at power-up using the INTA/ enable
sense resistor (pull-up on MAD[4]). This will cause the
LSI53C896 to program the Function B PCI Interrupt Pin
register (0x3D) to 0x01.

internally generated interrupts will be presented on INTA/
and INTB/. If INT_DIR is HIGH, internal interrupts will be
generated on both the INTx/ pins and the ALT_INTx pin. If
INT_DIR is LOW, the internal interrupts will be generated
only on the ALT_INTx/ pin. This pin has a static pull-up.

3-10 Signal Descriptions

3.2.7 SCSI Function A GPIO Signals

*

Table 3.8 describes the signals for the SCSI Function A GPIO group.

Table 3.8 SCSI Function A GPIO Signals

Name Bump Type Strength Description

A_GPIO0_
FETCH/

A_GPIO1_
MASTER/

A_GPIO2 AA16 I/O 8 mA SCSI Function A General Purpose I/O pin 2. This pin

A_GPIO3 AC17 I/O 8 mA SCSI Function A General Purpose I/O pin 3. This pin

A_GPIO4 AB17 I/O 8 mA SCSI Function A General Purpose I/O pin 4. This pin

AB16 I/O 8 mA SCSI Function A General Purpose I/O pin 0. This pin

is programmable at power-up through the MAD[7] pin to
serve as the data signal for the serial EEPROM interface.
When GPIO_0 is not in the process of downloading
EEPROM data it can be used to drive a SCSI Activity
LED if bit 5 in the General Purpose Pin Control

(GPCNTL) register is set. Or, it can be used to indicate

that the next bus request will be an opcode fetch if bit 6
in the GPCNTL register is set.

Y16 I/O 8 mA SCSI Function A General Purpose I/O pin 1. This pin

is programmable at power-up through the MAD[7] pin to
serve as the clock signal for the serial EEPROM interface.
When General Purpose Pin Control (GPCNTL) bit 7 is
set, this pin drives LOW when the LSI53C896 is bus
master.

powers up as an input.

powers up as an input.

powers up as an output.

PCI Bus Interface Signals 3-11

3.2.8 SCSI Function B GPIO Signals

*

Table 3.9 describes the signals for the SCSI Function B GPIO group.

Table 3.9 SCSI Function B GPIO Signals

Name Bump Type Strength Description

B_GPIO0_
FETCH/

B_GPIO1_
MASTER/

B_GPIO2 AB15 I/O 8 mA SCSI Function B General Purpose I/O pin 2. This pin

B_GPIO3 AA15 I/O 8 mA SCSI Function B General Purpose I/O pin 3. This pin

B_GPIO4 AC16 I/O 8 mA SCSI Function B General Purpose I/O pin 4. This pin

AA14 I/O 8 mA SCSI Function B General Purpose I/O pin 0. This pin

is programmable at power-up through the MAD[7] pin
to serve as the data signal for the serial EEPROM
interface. When GPIO_0 is not in the process of
downloading EEPROM data it can be used to drive a
SCSI Activity LED if bit 5 in the General Purpose Pin

Control (GPCNTL) register is set. Or, it can be used to

indicate that the next bus request will be an opcode
fetch if bit 6 in the GPCNTL register is set.

AC15 I/O 8 mA SCSI Function B General Purpose I/O pin 1. This pin

is programmable at power-up through the MAD[7] pin
to serve as the clock signal for the serial EEPROM
interface. When General Purpose Pin Control

(GPCNTL) bit 7 is set, this pin is driven LOW when the

LSI53C896 is bus master.

powers up as an input.

powers up as an input.

powers up as an output.

3-12 Signal Descriptions