LSI53C1030 PCI-X to
Dual Channel Ultra320
SCSI Multifunction
Controller
June 2003
Version 2.1
®
DB14-000156-04
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
Document DB14-000156-04, Version 2.1 (June 2003)
This document describes LSI Logic Corporation’s LSI53C1030 PCI-X to
Dual Channel Ultra320 SCSI Multifunction Controller and will remain the official
reference source for all revisions/releases of this product until rescinded by an
update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or thi rd parties.
LSI Logic, the LSI Logic logo design, Fusion-MPT, Integrated Mirroring, LVDlink,
SDMS, SureLINK, and TolerANT are trademarks or registered trademarks of LSI
Logic Corporation. ARM and Multi-ICE are registered trademarks of ARM Ltd.,
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AP
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This book is the pri mary reference and techni cal manual for the
LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Mul tifunction
Controller. It contains a functional de scription for the LSI53C 1030 and
the physical and ele ctrical specifications f or the LSI53C1030.
This document ass umes that you have som e familiarity with
microprocessors and related support d evices. The people who benefit
from this book are:
Organization
•Engineers and manag ers who are evaluating t he LSI53C1030 for
use in a system
•Engineers who are d esigning the LSI53C1030 into a system
This document ha s the following chapters and appendixes:
•Chapter 1, Introduction, provides an ove rview of the LSI53C1030
features and capabil ities.
•Chapter 2, Functional Description, provide s a detailed functional
description of the LSI53 C1030 operation. This c hapter describes
how the LSI53C1030 im plements the PCI, PCI-X , and SCSI bus
specifications.
•Chapter 3, Signal Description, provides a deta iled signal
description for the LSI53C 1030.
•Chapter 4, PCI Host Register Description, provides a bit level
description of the host register set of the LSI53C 1030.
LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controlleriii
2575 N. E. Katherine
Hillsboro, OR 97214
(800) 433-5177; (503) 693-6232 (International) ; FAX (503) 693-834 4
Conventions Used in This Manual
The first time a wor d or phrase is def ined in this manual , it is italicized.
The word assert means to drive a signal true or active. The word
deassert means to dr iv e a sig nal fal se or ina ct ive. S ign al s th at ar e a ctiv e
LOW end with a “/.”
Hexadecimal numb ers are indicated b y the prefix “0x” —for ex ample,
0x32CF. Binary numbers are indic ated by the prefix “0 b” —for example,
0b0011.0010.1100.1111.
Revision History
RevisionDateRemarks
Version 2.16/2003Updated the external memory timing diagrams.
Version 2.04/2002Added register summary appendix.
Preliminary
Version 1.0
Advance
Version 0.1
12/2001 Updated the description of Fusion-MPT architecture in Chapter 1.
2/2001Initial release of document.
Updated the default Subsystem ID value.
Updated the ZCR behavior description.
Updated the Multi-ICE test interface description.
Updated the electrical characteristics.
Updated the Index.
Updated External Memory Interface descriptions in Chapter 2.
Added Test Interface description to Chapter 2.
Added Zero Channel RAID interface description to Chapters 2 and 3.
Updated the MAD Power-On Sense pin description in Chapter 3.
Updated signal descriptions and lists to include the ZCR-related pins.
Updated ele ctrical an d environmen tal charact eristics in Chapter 5.
Removed figures relating to SE SCSI electrical and timing characteristics
from Chapter 5.
Removed SCSI timing information from Chapter 5 and referred readers to
the SCSI specification.
Removed PSBRAM interface and all related information.
This chapter provides a general overview of the LSI53C1030 PCI-X to
Dual Channel Ultra320 S CSI Multifunction Controller. This chapter
contains the follow ing sections:
•Se ction 1.1, “General Desc ription”
•Se ction 1.2, “Benefits o f the Fusion-MPT Architecture”
•Se ction 1.3, “Benefits o f PCI-X”
•Se ction 1.4, “Benefits o f Ultra320 SCSI”
•Se ction 1.5, “Benefits of S ureLINK (Ultra320 SCSI Do main
Validation)”
•Se ction 1.6, “Benefits o f LVDlink Technology”
•Se ction 1.7, “Benefits o f Tole rANT® Technology”
•Se ction 1.8, “Summary of LSI5 3C1030 Features”
1.1 General Description
The LSI53C1030 PCI- X to Dual Channel Ultra320 S CSI Multifunction
Controller brings Ult ra320 SCSI performance to host adapter,
workstation, and ser ver designs, making it e asy to add a
high-performance SCS I bus to any PCI or PCI- X system. The
LSI53C1030 supports b oth the PCI Local Bus Specification, Revisio n
2.2, and the PCI-X Adden dum to the PCI Local Bus Specification,
Revision 1.0a.
1. In some instances, this manual references PCI-X explicit ly. References to the PCI
bus may be inclusive of bo th the PCI specification and P CI-X addendum, or they
may refer only t o the PCI bus depending o n the operating mode of th e device.
1
LSI53C1030 PCI-X to Du al Channel Ultra320 SCS I Multifunction Controller1-1
The LSI53C1030 is pi n compatible with the LSI53C 1010R PCI to Dual
Channel Ultra160 SC SI Multifunction Controll er to provide an easy and
safe migration path to Ultra 320 SC SI. The LSI5 3C1030 sup ports up to a
64-bit, 133 MHz PCI-X bu s. The Ultra320 SCSI f eatures for the
LSI53C1030 include : double transition (DT ) clocking, packetize d
protocol, paced tra nsfers, quick arbitrate and select (QAS), s kew
compensation, inte rsymbol interference (ISI) compens ation, cyclic
redundancy check (C RC), and domain validation te chnology. These
features comply with the American National S tandard Institute (AN SI)
T10 SCSI Parallel Interface-4 (SPI-4) dr aft specification.
DT clocking enables the LSI53C1030 to achieve data transfer rates of
up to 320 megabytes per s econd (Mbytes/s) on each SCSI channel , for
a total bandwidth of 640 M bytes/s on both SCSI ch annels. Packetized
protocol increases d ata trans fer capabi lities with SCS I informat ion uni ts.
QAS minimizes SCSI bus latency by allowing the bus to directly ente r
the arbitration/selec tion bus phase after a SCSI disconn ect and skip the
bus free phase. Skew compensation permit s the LSI53C1030 to adjus t
for cable and bus sk ew on a per-device basis . Paced transfers enab le
high speed data transfers during DT data phases by using the REQ/ACK
transition as a free running data clock. Pre compensation enables the
LSI53C1030 to adj ust the signal drive stre ngth to compensate fo r the
charge present on the cable. CRC improves the SCSI data transmission
integrity through en hanced detection of communication error s.
SureLINK™ Domain Validation detects the S CSI bus configuration a nd
adjusts the SCSI tr ansfer rate to optim ize bus interop erability and SC SI
data transfer rates . Sur eLINK Domain Validation provides thr ee le vels of
domain validatio n, assuring robust sy stem operation.
The LSI53C1030 suppor ts a local memory bus, wh ich supports a
standard serial EEPRO M and allows local storage of the BIOS in Flash
ROM memory. The LSI53C1030 supports pro gramming of local Flash
ROM memory for BIOS updates. Figure 1.1 shows a typical LSI53C1030
board application connected to external R OM memory.
The LSI53C1030 integr ates two high-performan ce SCSI Ultra320 cores
and a 64-bit, 133 MHz P CI-X bus master DMA core . The LSI53C1030
employs three ARM96 6E-S processors to meet th e data transfer
flexibility requiremen ts of the Ultra320 SCSI, PCI, and PCI-X
®
specifications. S eparate ARM
processors su pport each SCSI chann el
and the PCI/PCI-X in terface.
These processors im plement the LSI Logic F usion-MPT™ architectu re,
a multithreaded I/O al gorithm that supports d ata transfers between the
host system and SCS I de vices w ith minim al host p roce ssor i nterventi on.
Fusion-MPT technology prov ides an efficie nt archi tecture that s olves the
protocol overhead pr oblems of previous intell igent and nonintelligent
adapter designs.
LVDlink™ technolo gy is the LSI Logic impl ementation of Low Voltage
Differential (LVD) SCSI. LVDlink transceiver s allow the LSI53C1030 to
perform either Single -Ended (SE) or LVD transfers. Figure 1.2 illustrates
a typical LSI53C1030 s ystem application.
The LSI53C1030 suppor ts the LSI Logic Integrated Mirroring
technology, which provides physical mirroring of the boot volume through
LSI53C1030 firmware. Th is feature provides extr a reliability for the
system’s boot volume withou t burdening the host CPU. Keepi ng a
second disk as a mi rror requires the LSI Logi c Fusion-MPT firmware,
which performs writes to both the boot drive a nd the mir rored driv e. The
runtime mirroring of the boot drive is transparen t to the BIOS, drivers,
and operating syste m.
The IM firmware requi res a configuration mecha nism, which enables
configuration of the m irroring attributes durin g initial setup or
reconfiguration afte r hardware failures or cha nges in the system
environment. Use the LSI Logic BIOS Configuration Utility or the IM DOS
Configuration Utility to configure the IM firmware attributes. Using the LSI
Logic BIOS and dri vers adds support of p hysical device recogn ition for
the purpose of Domain Validation and Ultra320 SCSI expander
configuration. Host b ased status software moni tors the state of the
mirrored drives an d reports error condit ions as they arise.
1.2 Benefits of the Fusion-MPT Architecture
The Fusion-MPT architectu re provides an open architectur e that is ideal
for SCSI, Fibre Channel , and other emerging interfa ces. The I/O
interface is inter changable at the system a nd application level;
embedded software uses th e same device interfac e for SCSI and Fibre
Channel implementation s just as application software uses the same
storage managemen t interfaces for SCSI and F ibre Channel
implementations. LS I Logic provi des Fusion-MPT devi ce drivers that ar e
binary compatible b etween Fibre Channel and Ultra320 SCSI int erfaces.
The Fusion-MPT arch itecture improves overall system performance by
requiring only a th in device driver, which off loads t he intensive wor k of
managing SCSI I/Os from the system processor to the LSI53C1030.
Developed from the proven LSI Logi c SDMS ™ s ol ution, th e F usio n- MPT
architecture deliver s unmatched perform ance of up to 100,000 Ul tra320
SCSI I/Os per seco nd with minimal system o verhead or device
maintenance. The use of thin, easy to devel op, common OS device
drivers accelerates time to market by reducing device driver development
and certificatio n times.
The Fusion-MPT architectu re provides an interrupt coalescing feature.
Interrupt coalescing allows an I/O controller to send multiple reply
messages in a sing le interrupt to the host pr ocessor. Sending multiple
reply messages pe r interrupt reduces c ontext switching of th e host
processor and maxi mizes the host proc essor efficiency, which results in
a significant imp rovement of system per formance. To use the interrupt
coalescing feature , the host processor mu st be able to accept an d
manage multiple r eplies per interrupt.
The Fusion-MPT architec ture als o provides bui lt-in devic e driver sta bility
since the device dr iver need not change for each revision of the
LSI53C1030 silicon or firmware. Th is architecture is a reliable, constant
interface between the hos t device driv er and the LSI 53C1030. Changes
within the LSI53C1030 are transparent to the ho st device driver,
operating system, and user. The Fusion-MPT architecture also saves the
user significant dev elopment and maintenanc e effort since it is not
necessary to alter or redevelop the devi ce driver when a r evision of the
LSI53C1030 device or firmware occurs.
1.3 Benefits of PCI-X
PCI-X doubles the max imum clock frequenc y of the conventional PCI
bus. The PCI-X Adde ndum to the PCI Local Bus S pecification,
Revision 1.0a, defi nes enhancements to th e proven PCI Local Bus
Specification, Revis ion 2.2. PCI-X provid es more efficient data transf ers
by enabling registe red input s and outpu ts, impro ves buffer man agement
by including transaction in for ma tio n with each data transfer, and reduces
bus overhead by restricting the use of wait states and disconnects. PCI-X
also reduces host processor overhead by providing a wide range of error
recovery implem entations.
The LSI53C1030 suppor ts up to a 133 MHz, 64- bit PCI-X bus and is
backward compatible with p revious versions of the PCI /PCI-X
specification. The LSI5 3C1030 is a true multifunction PCI-X dev ice and
presents a single e lectrical load to the PCI bu s. The LSI53C1030 uses
a single REQ/-GNT/ p air to arbitrate for PCI bus mastership. Separate
interrupt signals for P CI Function [0] and PCI Function [1] allow
independent control o f the two PCI functions.
Per the PCI-X addendu m, the LSI53C1030 includes transaction
information with al l PCI-X transactions to e nable more efficient buffer
management schemes. E ach PCI-X transaction c ontains a transaction
sequence identif ier (Tag), the identity of th e initiator, and the number of
bytes in the sequence . The LSI53C1030 clocks PCI-X data directly into
and out of registers, whi ch creates a more efficient data pa th. The
LSI53C1030 increases bus efficiency since it does not insert wa it states
after the initial data p hase when acting as a PC I-X target and never
inserts wait states when acting as a PCI-X in itiator.
1.4 Benefits of Ultra320 SCSI
Ultra320 SCSI is a n e xte ns io n o f th e S PI -4 draft specification tha t al lo ws
faster synchronous S CSI data transf er rates than Ul tra160 SCSI. When
enabled, Ultra320 SCS I performs 160 megatransfer s per second
resulting in a pproximate ly doub le the s ynchronou s data t ransfer rates of
Ultra160 SCSI. The LSI53 C1030 performs 16-bi t, Ultra320 SCSI
synchronous data tran sfers as fast as 320 Mbytes/s on each SCS I
channel. This advantage is most noticea ble in hea vi ly l oade d s y ste ms or
large block size applications, su ch as video on-dema nd and image
processing.
Ultra320 SCSI doubles both the data and clock freq uencies from
Ultra160 SCSI. Due to the increased data and cloc k speeds, Ultra320
SCSI introduces sk ew compensation and i ntersymbol interferen ce (ISI)
compensation. These new features simplify system design by resolving
timing issues at the chip level. Skew co mpensation adjust s for timing
differences between data an d clock signals caused by cabling, board
traces, etc. ISI compensa tion enhances the first pulse after a chan ge in
state to ensure dat a integrity.
Ultra320 SCSI include s CRC, which offers higher levels of data r el iabil ity
by ensuring complete integrity of transferred data. CRC is a 32-bit
scheme, referred to as CRC-32. CRC g uarantees detection of all single
or double bit errors, as well as any combination of bit errors within a
single 32-bit rang e.
1.5 Benefits of SureLINK (Ultra320 SCSI Domain Validation)
SureLINK Domain Validation software ensu res robus t SCS I interc onnec t
management and lo w risk Ultra320 S CSI implementa tions by extendi ng
the domain validatio n gui de lines doc um ente d in t he SPI- 4 s pec if ic ations .
Domain validation verifie s that th e sys tem is capab le of tr ansferr ing dat a
at Ultra320 SCSI sp eeds, allowing the LSI53C10 30 to renegotiate to a
lower data transfer s peed a nd bus width i f nece ssary. SureLINK Domain
Validation is the softwar e cont rol for th e domain vali dation m anagea bility
enhancements in the LSI53C1030. SureLINK Domain Validation software
provides domain v alidation management at boot time as well as duri ng
system operatio n.
SureLINK Domain Validation ensures robust system operation by
providing 3 levels of integrity check ing on a per-device b asis: Basic
(Level 1) with inquiry c ommand, Enhanced (Leve l 2) with read/write
buffer and Margined (L evel 3) with margining of drive strength an d slew
rates.
Benefits of SureLINK (Ultra320 SCSI Domain Validation)1-7
The LSI53C1030 suppor ts Low Voltage Differential (LVD) through
LVDlink technolo gy. This signalling techno logy inc reas es the r eliab ility o f
SCSI data transfers over longer distances th an are supported by SE
(Single Ended) SCSI. Th e low current output of LVD allows the I/O
transceivers to be i ntegrated directly onto the chip. To allow the use of
the LSI53C1030 in both legacy and Ultra320 SCS I applications, this
device features unive rsal LVDlink transceiver s that support LVD SCSI
and SE SCSI.
1.7 Benefits of TolerANT® Technology
The LSI53C1030 feature s Toler ANT technology, which provides active
negation on the SCSI d rivers and input signal filtering on the SCSI
receivers. Active negation causes the S CSI Request, Acknowle dge,
Data, and Parity signals to be ac tively driven high rather tha n passively
pulled up by termina tors.
To lerANT receiver tech nology improves data inte grity in unreliable
cabling environme nts where other devices wo uld be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions , without the long signal delay associated with
RC-type input filters. Thi s improv ed dri ver and r eceiver techno logy he lps
ensure correct clocking of data. TolerANT input signal filtering is a built-in
feature of the LSI53C1 030 and all LSI Logic Fa st SCSI, Ultra SCSI,
Ultra2 SCSI, Ultra160 SCSI, and Ultra320 SCSI dev ices.
TolerANT technology in creases noise immunity, balances duty cyc les,
and improves SCSI tran sfer rates. In addition, Toler ANT SCSI devices
do not cause glitches on the SCSI bus at power-up o r power-down,
which protects other devices on the bus from data corruption. When used
with the LVDlink transceivers, TolerANT technology provides excell ent
signal quality a nd data reliability in r eal world cabling env ironments.
To lerANT technology is comp atible with both the Alternati ve One and
Alternative Two termination schemes proposed by the American National
Standards Institute.
This section provi des a summary of the LSI53C1 030 features and
benefits. It contains information on SCSI Performance, PCI Performance,
Integration, Flexibility, Reliability, and Testability.
1.8.1 SCSI Performance
The LSI53C1030 con tains the following SCSI per formance features:
•Su pports Ultra320 SCSI
–Paced transfers using a free runnin g clock
–320 Mbyte/s data transfer rate on eac h SCSI channel
–Mandatory packetized protocol
–Quick arbitrate and select (QAS )
–Skew compensation with bus training
–Transmitter precompen sation to overcome IS I effects for SCSI
data signals
–Retained training information (RTI)
•O ffers a performance optimized architecture
–Three ARM966E-S processors provid e high performance with
•Has a 133 MHz, 64-bit PCI/P CI-X interface that:
–Operates at 33 MHz or 66 MHz PCI
–Operates at up to 133 MHz PCI-X
–Supports 32-bit or 64-bit data
–Supports 32-bit or 64-bit addressi ng through Dual Address
–Provides a theoretical 1066 Mbytes/s zero wait state transfer rate
–Complies with the PCI Local Bus Sp ecification, Revisi on 2.2
–Complies with the PCI-X Addendum to the PCI Local Bus
–Complies with PCI Power Management In terface Specificatio n,
–Complies with PC2001 System Design Guide
Cycles (DAC)
Specification, Re vision 1.0a
Revision 1.1
•O ffers unmatched performa nce through the Fus ion-MPT architect ure
•Pr ovi des h i gh throu ghput and low CPU utilizati on to off load the ho st
processor
•Pr esents a single ele ctrical load to the PCI B us (True PCI
Multifunction Device)
•U ses SCSI Interrupt Steering Logic (SISL) to provide alternate
interrupt routing fo r RAID applications
•R educes Interrupt Servi ce Routine (ISR) overhead with interrupt
coalescing
•Su pports 32-bit or 64-bit data b ursts with variable burst len gths
•Su pports the PCI Cache Line S ize register
•Su pports the PCI Mem ory Write and Invalid ate, Memory Read L ine,
and Memory Read Multi ple commands
•Supports the PCI-X Memory Read Dword, Split Completion, Memory
Read Block, and Memor y Write Block commands
•Su pports up to 8 PCI-X ou tstanding split transa ctions
These features make th e LSI53C1030 easy to in tegrate:
•Is backward compat ible with prev ious revisi ons o f the P CI and S CSI
specifications
•Is pin compatible wit h the LSI53C1010R PCI to Dual Cha nnel
Ultra160 SCSI Multi function Controller
•Provides a low-risk mig ration path to Ultra320 SCS I from the
LSI53C1010R
•Is a dual channel Ultr a3 20 S CS I to PCI/ PCI- X mul ti functi on c on tr oller
•Supports a 32-bit or 6 4-bit PCI/PCI-X DMA bus m aster
•Reduces time to mark et with the Fusion-MPT architecture
–Single driver binary for SCSI and F ibre Channel products
–Thin, easy to develop drivers
–Reduced integration and certification effort
•Provides integra ted LVDlink transceivers
1.8.4 Flexibility
These features inc rease the flexibility of t he LSI53C1030:
•U niversal LVD transceivers are backward compati ble with SE
devices
•Provides a flexible programming interface to tune I/O performance or
to adapt to unique SCS I devices
•Su pports MSI or pin-based ( INTx/ or ALT_INTx/) interrupt signalling
•C an respond with multipl e SCSI IDs
•I s compatible with 3.3 V and 5.0 V PCI signall ing
–Drives and receives 3.3 V PCI signals
–Receives 5.0 V PCI if the PCI5VB IAS pin connects to 5 V, but
This chapter provid es a subsytem level overvi ew of the LSI53C1030, a
discussion of the Fus ion-MPT architecture, and a fu nctional description
of the LSI53C1030 inte rfaces. This chapter conta ins the following
sections:
•Section 2.1, “Block Diagram Description”
•Section 2.2, “Fusi on-MPT Architecture Ove rview”
•Section 2.3, “PCI Fu nctional Description”
•Section 2.4, “Ultra 320 SCSI Functional De scription”
•Section 2.5, “Exter nal Memory Interface”
•Section 2.6, “Seri al EEPROM Interface”
•Section 2.7, “Zero Cha nnel RAID”
•Section 2.8, “Multi- ICE Tes t Interface”
The LSI53C1030 is a hi gh performance, intellig ent PCI-X to Dual
Channel Ultra320 SCSI M ultifunction Contr oller. The LSI53C1030
supports the PCI Lo cal Bus Specific ation, Revision 2.2, the PCI-X Addendum to the PCI Lo cal Bus Specifica tion, Revision 1.0a, an d the
proposed SCSI Parallel Interface-4 (SPI-4) draft standard.
The LSI53C1030 employ s the LSI Logic Fusion- MPT architecture to
ensure robust system performance, to support bi nary compatibility o f
host software between the LSI Logic SC SI and Fibre Channe l products,
and to significantly reduce software developm ent time. Refer to the
Fusion-MPT Device Mana gement User ’s Guide for more information on
the Fusion-MPT archite cture.
LSI53C1030 PCI-X to Du al Channel Ultra320 SCS I Multifunction Controller2-1
The LSI53C1030 consi sts of three major modu les: a host interface
module and two indepe ndent Ultra320 SCSI ch annel modules. The
modules consist of the following component s:
•Host Interface Module
–Up to a 64-bit, 133 MHz PCI/PCI-X Interfa ce
–System Interface
–I/O Processor (IOP)
–DMA Arbiter and Router
–Shared RAM
–External Memory Interface
◊Fla sh ROM Memory Controller
◊NVSRAM
–Timer and Configuratio n Control
◊Devic e Configuration Controll er
◊Se rial EEPROM Interface Co ntroller
◊GPIO Interface
◊Chip Timer