LSI53C1030 PCI-X to
Dual Channel Ultra320
SCSI Multifunction
Controller
June 2003
Version 2.1
®
DB14-000156-04
Page 2
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
Document DB14-000156-04, Version 2.1 (June 2003)
This document describes LSI Logic Corporation’s LSI53C1030 PCI-X to
Dual Channel Ultra320 SCSI Multifunction Controller and will remain the official
reference source for all revisions/releases of this product until rescinded by an
update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or thi rd parties.
LSI Logic, the LSI Logic logo design, Fusion-MPT, Integrated Mirroring, LVDlink,
SDMS, SureLINK, and TolerANT are trademarks or registered trademarks of LSI
Logic Corporation. ARM and Multi-ICE are registered trademarks of ARM Ltd.,
used under license. Windows is a registered trademarks of Microsoft
Corporation. NetWare is a registered trademarks of Novell Corporation. Linux is
a registered trademark of Linus Torvalds. Solaris is a trademark of Sun
Microsystems, Inc. SCO Openserver is a trademark of Caldera International, Inc.
UnixWare is a trademark of The Open Group. All other brand and product names
may be trademarks of their respective companies
AP
To receive product literature, visit us at http://www.lsilogic.com.
For a current list of our distributors, sales offices, and design resource
centers, v iew our web p age located at
http://www.lsilogic.com/contacts/index.html
This book is the pri mary reference and techni cal manual for the
LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Mul tifunction
Controller. It contains a functional de scription for the LSI53C 1030 and
the physical and ele ctrical specifications f or the LSI53C1030.
This document ass umes that you have som e familiarity with
microprocessors and related support d evices. The people who benefit
from this book are:
Organization
•Engineers and manag ers who are evaluating t he LSI53C1030 for
use in a system
•Engineers who are d esigning the LSI53C1030 into a system
This document ha s the following chapters and appendixes:
•Chapter 1, Introduction, provides an ove rview of the LSI53C1030
features and capabil ities.
•Chapter 2, Functional Description, provide s a detailed functional
description of the LSI53 C1030 operation. This c hapter describes
how the LSI53C1030 im plements the PCI, PCI-X , and SCSI bus
specifications.
•Chapter 3, Signal Description, provides a deta iled signal
description for the LSI53C 1030.
•Chapter 4, PCI Host Register Description, provides a bit level
description of the host register set of the LSI53C 1030.
LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controlleriii
2575 N. E. Katherine
Hillsboro, OR 97214
(800) 433-5177; (503) 693-6232 (International) ; FAX (503) 693-834 4
Conventions Used in This Manual
The first time a wor d or phrase is def ined in this manual , it is italicized.
The word assert means to drive a signal true or active. The word
deassert means to dr iv e a sig nal fal se or ina ct ive. S ign al s th at ar e a ctiv e
LOW end with a “/.”
Hexadecimal numb ers are indicated b y the prefix “0x” —for ex ample,
0x32CF. Binary numbers are indic ated by the prefix “0 b” —for example,
0b0011.0010.1100.1111.
Revision History
RevisionDateRemarks
Version 2.16/2003Updated the external memory timing diagrams.
Version 2.04/2002Added register summary appendix.
Preliminary
Version 1.0
Advance
Version 0.1
12/2001 Updated the description of Fusion-MPT architecture in Chapter 1.
2/2001Initial release of document.
Updated the default Subsystem ID value.
Updated the ZCR behavior description.
Updated the Multi-ICE test interface description.
Updated the electrical characteristics.
Updated the Index.
Updated External Memory Interface descriptions in Chapter 2.
Added Test Interface description to Chapter 2.
Added Zero Channel RAID interface description to Chapters 2 and 3.
Updated the MAD Power-On Sense pin description in Chapter 3.
Updated signal descriptions and lists to include the ZCR-related pins.
Updated ele ctrical an d environmen tal charact eristics in Chapter 5.
Removed figures relating to SE SCSI electrical and timing characteristics
from Chapter 5.
Removed SCSI timing information from Chapter 5 and referred readers to
the SCSI specification.
Removed PSBRAM interface and all related information.
This chapter provides a general overview of the LSI53C1030 PCI-X to
Dual Channel Ultra320 S CSI Multifunction Controller. This chapter
contains the follow ing sections:
•Se ction 1.1, “General Desc ription”
•Se ction 1.2, “Benefits o f the Fusion-MPT Architecture”
•Se ction 1.3, “Benefits o f PCI-X”
•Se ction 1.4, “Benefits o f Ultra320 SCSI”
•Se ction 1.5, “Benefits of S ureLINK (Ultra320 SCSI Do main
Validation)”
•Se ction 1.6, “Benefits o f LVDlink Technology”
•Se ction 1.7, “Benefits o f Tole rANT® Technology”
•Se ction 1.8, “Summary of LSI5 3C1030 Features”
1.1 General Description
The LSI53C1030 PCI- X to Dual Channel Ultra320 S CSI Multifunction
Controller brings Ult ra320 SCSI performance to host adapter,
workstation, and ser ver designs, making it e asy to add a
high-performance SCS I bus to any PCI or PCI- X system. The
LSI53C1030 supports b oth the PCI Local Bus Specification, Revisio n
2.2, and the PCI-X Adden dum to the PCI Local Bus Specification,
Revision 1.0a.
1. In some instances, this manual references PCI-X explicit ly. References to the PCI
bus may be inclusive of bo th the PCI specification and P CI-X addendum, or they
may refer only t o the PCI bus depending o n the operating mode of th e device.
1
LSI53C1030 PCI-X to Du al Channel Ultra320 SCS I Multifunction Controller1-1
The LSI53C1030 is pi n compatible with the LSI53C 1010R PCI to Dual
Channel Ultra160 SC SI Multifunction Controll er to provide an easy and
safe migration path to Ultra 320 SC SI. The LSI5 3C1030 sup ports up to a
64-bit, 133 MHz PCI-X bu s. The Ultra320 SCSI f eatures for the
LSI53C1030 include : double transition (DT ) clocking, packetize d
protocol, paced tra nsfers, quick arbitrate and select (QAS), s kew
compensation, inte rsymbol interference (ISI) compens ation, cyclic
redundancy check (C RC), and domain validation te chnology. These
features comply with the American National S tandard Institute (AN SI)
T10 SCSI Parallel Interface-4 (SPI-4) dr aft specification.
DT clocking enables the LSI53C1030 to achieve data transfer rates of
up to 320 megabytes per s econd (Mbytes/s) on each SCSI channel , for
a total bandwidth of 640 M bytes/s on both SCSI ch annels. Packetized
protocol increases d ata trans fer capabi lities with SCS I informat ion uni ts.
QAS minimizes SCSI bus latency by allowing the bus to directly ente r
the arbitration/selec tion bus phase after a SCSI disconn ect and skip the
bus free phase. Skew compensation permit s the LSI53C1030 to adjus t
for cable and bus sk ew on a per-device basis . Paced transfers enab le
high speed data transfers during DT data phases by using the REQ/ACK
transition as a free running data clock. Pre compensation enables the
LSI53C1030 to adj ust the signal drive stre ngth to compensate fo r the
charge present on the cable. CRC improves the SCSI data transmission
integrity through en hanced detection of communication error s.
SureLINK™ Domain Validation detects the S CSI bus configuration a nd
adjusts the SCSI tr ansfer rate to optim ize bus interop erability and SC SI
data transfer rates . Sur eLINK Domain Validation provides thr ee le vels of
domain validatio n, assuring robust sy stem operation.
The LSI53C1030 suppor ts a local memory bus, wh ich supports a
standard serial EEPRO M and allows local storage of the BIOS in Flash
ROM memory. The LSI53C1030 supports pro gramming of local Flash
ROM memory for BIOS updates. Figure 1.1 shows a typical LSI53C1030
board application connected to external R OM memory.
The LSI53C1030 integr ates two high-performan ce SCSI Ultra320 cores
and a 64-bit, 133 MHz P CI-X bus master DMA core . The LSI53C1030
employs three ARM96 6E-S processors to meet th e data transfer
flexibility requiremen ts of the Ultra320 SCSI, PCI, and PCI-X
®
specifications. S eparate ARM
processors su pport each SCSI chann el
and the PCI/PCI-X in terface.
These processors im plement the LSI Logic F usion-MPT™ architectu re,
a multithreaded I/O al gorithm that supports d ata transfers between the
host system and SCS I de vices w ith minim al host p roce ssor i nterventi on.
Fusion-MPT technology prov ides an efficie nt archi tecture that s olves the
protocol overhead pr oblems of previous intell igent and nonintelligent
adapter designs.
LVDlink™ technolo gy is the LSI Logic impl ementation of Low Voltage
Differential (LVD) SCSI. LVDlink transceiver s allow the LSI53C1030 to
perform either Single -Ended (SE) or LVD transfers. Figure 1.2 illustrates
a typical LSI53C1030 s ystem application.
The LSI53C1030 suppor ts the LSI Logic Integrated Mirroring
technology, which provides physical mirroring of the boot volume through
LSI53C1030 firmware. Th is feature provides extr a reliability for the
system’s boot volume withou t burdening the host CPU. Keepi ng a
second disk as a mi rror requires the LSI Logi c Fusion-MPT firmware,
which performs writes to both the boot drive a nd the mir rored driv e. The
runtime mirroring of the boot drive is transparen t to the BIOS, drivers,
and operating syste m.
The IM firmware requi res a configuration mecha nism, which enables
configuration of the m irroring attributes durin g initial setup or
reconfiguration afte r hardware failures or cha nges in the system
environment. Use the LSI Logic BIOS Configuration Utility or the IM DOS
Configuration Utility to configure the IM firmware attributes. Using the LSI
Logic BIOS and dri vers adds support of p hysical device recogn ition for
the purpose of Domain Validation and Ultra320 SCSI expander
configuration. Host b ased status software moni tors the state of the
mirrored drives an d reports error condit ions as they arise.
1.2 Benefits of the Fusion-MPT Architecture
The Fusion-MPT architectu re provides an open architectur e that is ideal
for SCSI, Fibre Channel , and other emerging interfa ces. The I/O
interface is inter changable at the system a nd application level;
embedded software uses th e same device interfac e for SCSI and Fibre
Channel implementation s just as application software uses the same
storage managemen t interfaces for SCSI and F ibre Channel
implementations. LS I Logic provi des Fusion-MPT devi ce drivers that ar e
binary compatible b etween Fibre Channel and Ultra320 SCSI int erfaces.
The Fusion-MPT arch itecture improves overall system performance by
requiring only a th in device driver, which off loads t he intensive wor k of
managing SCSI I/Os from the system processor to the LSI53C1030.
Developed from the proven LSI Logi c SDMS ™ s ol ution, th e F usio n- MPT
architecture deliver s unmatched perform ance of up to 100,000 Ul tra320
SCSI I/Os per seco nd with minimal system o verhead or device
maintenance. The use of thin, easy to devel op, common OS device
drivers accelerates time to market by reducing device driver development
and certificatio n times.
The Fusion-MPT architectu re provides an interrupt coalescing feature.
Interrupt coalescing allows an I/O controller to send multiple reply
messages in a sing le interrupt to the host pr ocessor. Sending multiple
reply messages pe r interrupt reduces c ontext switching of th e host
processor and maxi mizes the host proc essor efficiency, which results in
a significant imp rovement of system per formance. To use the interrupt
coalescing feature , the host processor mu st be able to accept an d
manage multiple r eplies per interrupt.
The Fusion-MPT architec ture als o provides bui lt-in devic e driver sta bility
since the device dr iver need not change for each revision of the
LSI53C1030 silicon or firmware. Th is architecture is a reliable, constant
interface between the hos t device driv er and the LSI 53C1030. Changes
within the LSI53C1030 are transparent to the ho st device driver,
operating system, and user. The Fusion-MPT architecture also saves the
user significant dev elopment and maintenanc e effort since it is not
necessary to alter or redevelop the devi ce driver when a r evision of the
LSI53C1030 device or firmware occurs.
1.3 Benefits of PCI-X
PCI-X doubles the max imum clock frequenc y of the conventional PCI
bus. The PCI-X Adde ndum to the PCI Local Bus S pecification,
Revision 1.0a, defi nes enhancements to th e proven PCI Local Bus
Specification, Revis ion 2.2. PCI-X provid es more efficient data transf ers
by enabling registe red input s and outpu ts, impro ves buffer man agement
by including transaction in for ma tio n with each data transfer, and reduces
bus overhead by restricting the use of wait states and disconnects. PCI-X
also reduces host processor overhead by providing a wide range of error
recovery implem entations.
The LSI53C1030 suppor ts up to a 133 MHz, 64- bit PCI-X bus and is
backward compatible with p revious versions of the PCI /PCI-X
specification. The LSI5 3C1030 is a true multifunction PCI-X dev ice and
presents a single e lectrical load to the PCI bu s. The LSI53C1030 uses
a single REQ/-GNT/ p air to arbitrate for PCI bus mastership. Separate
interrupt signals for P CI Function [0] and PCI Function [1] allow
independent control o f the two PCI functions.
Per the PCI-X addendu m, the LSI53C1030 includes transaction
information with al l PCI-X transactions to e nable more efficient buffer
management schemes. E ach PCI-X transaction c ontains a transaction
sequence identif ier (Tag), the identity of th e initiator, and the number of
bytes in the sequence . The LSI53C1030 clocks PCI-X data directly into
and out of registers, whi ch creates a more efficient data pa th. The
LSI53C1030 increases bus efficiency since it does not insert wa it states
after the initial data p hase when acting as a PC I-X target and never
inserts wait states when acting as a PCI-X in itiator.
1.4 Benefits of Ultra320 SCSI
Ultra320 SCSI is a n e xte ns io n o f th e S PI -4 draft specification tha t al lo ws
faster synchronous S CSI data transf er rates than Ul tra160 SCSI. When
enabled, Ultra320 SCS I performs 160 megatransfer s per second
resulting in a pproximate ly doub le the s ynchronou s data t ransfer rates of
Ultra160 SCSI. The LSI53 C1030 performs 16-bi t, Ultra320 SCSI
synchronous data tran sfers as fast as 320 Mbytes/s on each SCS I
channel. This advantage is most noticea ble in hea vi ly l oade d s y ste ms or
large block size applications, su ch as video on-dema nd and image
processing.
Ultra320 SCSI doubles both the data and clock freq uencies from
Ultra160 SCSI. Due to the increased data and cloc k speeds, Ultra320
SCSI introduces sk ew compensation and i ntersymbol interferen ce (ISI)
compensation. These new features simplify system design by resolving
timing issues at the chip level. Skew co mpensation adjust s for timing
differences between data an d clock signals caused by cabling, board
traces, etc. ISI compensa tion enhances the first pulse after a chan ge in
state to ensure dat a integrity.
Ultra320 SCSI include s CRC, which offers higher levels of data r el iabil ity
by ensuring complete integrity of transferred data. CRC is a 32-bit
scheme, referred to as CRC-32. CRC g uarantees detection of all single
or double bit errors, as well as any combination of bit errors within a
single 32-bit rang e.
1.5 Benefits of SureLINK (Ultra320 SCSI Domain Validation)
SureLINK Domain Validation software ensu res robus t SCS I interc onnec t
management and lo w risk Ultra320 S CSI implementa tions by extendi ng
the domain validatio n gui de lines doc um ente d in t he SPI- 4 s pec if ic ations .
Domain validation verifie s that th e sys tem is capab le of tr ansferr ing dat a
at Ultra320 SCSI sp eeds, allowing the LSI53C10 30 to renegotiate to a
lower data transfer s peed a nd bus width i f nece ssary. SureLINK Domain
Validation is the softwar e cont rol for th e domain vali dation m anagea bility
enhancements in the LSI53C1030. SureLINK Domain Validation software
provides domain v alidation management at boot time as well as duri ng
system operatio n.
SureLINK Domain Validation ensures robust system operation by
providing 3 levels of integrity check ing on a per-device b asis: Basic
(Level 1) with inquiry c ommand, Enhanced (Leve l 2) with read/write
buffer and Margined (L evel 3) with margining of drive strength an d slew
rates.
Benefits of SureLINK (Ultra320 SCSI Domain Validation)1-7
The LSI53C1030 suppor ts Low Voltage Differential (LVD) through
LVDlink technolo gy. This signalling techno logy inc reas es the r eliab ility o f
SCSI data transfers over longer distances th an are supported by SE
(Single Ended) SCSI. Th e low current output of LVD allows the I/O
transceivers to be i ntegrated directly onto the chip. To allow the use of
the LSI53C1030 in both legacy and Ultra320 SCS I applications, this
device features unive rsal LVDlink transceiver s that support LVD SCSI
and SE SCSI.
1.7 Benefits of TolerANT® Technology
The LSI53C1030 feature s Toler ANT technology, which provides active
negation on the SCSI d rivers and input signal filtering on the SCSI
receivers. Active negation causes the S CSI Request, Acknowle dge,
Data, and Parity signals to be ac tively driven high rather tha n passively
pulled up by termina tors.
To lerANT receiver tech nology improves data inte grity in unreliable
cabling environme nts where other devices wo uld be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions , without the long signal delay associated with
RC-type input filters. Thi s improv ed dri ver and r eceiver techno logy he lps
ensure correct clocking of data. TolerANT input signal filtering is a built-in
feature of the LSI53C1 030 and all LSI Logic Fa st SCSI, Ultra SCSI,
Ultra2 SCSI, Ultra160 SCSI, and Ultra320 SCSI dev ices.
TolerANT technology in creases noise immunity, balances duty cyc les,
and improves SCSI tran sfer rates. In addition, Toler ANT SCSI devices
do not cause glitches on the SCSI bus at power-up o r power-down,
which protects other devices on the bus from data corruption. When used
with the LVDlink transceivers, TolerANT technology provides excell ent
signal quality a nd data reliability in r eal world cabling env ironments.
To lerANT technology is comp atible with both the Alternati ve One and
Alternative Two termination schemes proposed by the American National
Standards Institute.
This section provi des a summary of the LSI53C1 030 features and
benefits. It contains information on SCSI Performance, PCI Performance,
Integration, Flexibility, Reliability, and Testability.
1.8.1 SCSI Performance
The LSI53C1030 con tains the following SCSI per formance features:
•Su pports Ultra320 SCSI
–Paced transfers using a free runnin g clock
–320 Mbyte/s data transfer rate on eac h SCSI channel
–Mandatory packetized protocol
–Quick arbitrate and select (QAS )
–Skew compensation with bus training
–Transmitter precompen sation to overcome IS I effects for SCSI
data signals
–Retained training information (RTI)
•O ffers a performance optimized architecture
–Three ARM966E-S processors provid e high performance with
•Has a 133 MHz, 64-bit PCI/P CI-X interface that:
–Operates at 33 MHz or 66 MHz PCI
–Operates at up to 133 MHz PCI-X
–Supports 32-bit or 64-bit data
–Supports 32-bit or 64-bit addressi ng through Dual Address
–Provides a theoretical 1066 Mbytes/s zero wait state transfer rate
–Complies with the PCI Local Bus Sp ecification, Revisi on 2.2
–Complies with the PCI-X Addendum to the PCI Local Bus
–Complies with PCI Power Management In terface Specificatio n,
–Complies with PC2001 System Design Guide
Cycles (DAC)
Specification, Re vision 1.0a
Revision 1.1
•O ffers unmatched performa nce through the Fus ion-MPT architect ure
•Pr ovi des h i gh throu ghput and low CPU utilizati on to off load the ho st
processor
•Pr esents a single ele ctrical load to the PCI B us (True PCI
Multifunction Device)
•U ses SCSI Interrupt Steering Logic (SISL) to provide alternate
interrupt routing fo r RAID applications
•R educes Interrupt Servi ce Routine (ISR) overhead with interrupt
coalescing
•Su pports 32-bit or 64-bit data b ursts with variable burst len gths
•Su pports the PCI Cache Line S ize register
•Su pports the PCI Mem ory Write and Invalid ate, Memory Read L ine,
and Memory Read Multi ple commands
•Supports the PCI-X Memory Read Dword, Split Completion, Memory
Read Block, and Memor y Write Block commands
•Su pports up to 8 PCI-X ou tstanding split transa ctions
These features make th e LSI53C1030 easy to in tegrate:
•Is backward compat ible with prev ious revisi ons o f the P CI and S CSI
specifications
•Is pin compatible wit h the LSI53C1010R PCI to Dual Cha nnel
Ultra160 SCSI Multi function Controller
•Provides a low-risk mig ration path to Ultra320 SCS I from the
LSI53C1010R
•Is a dual channel Ultr a3 20 S CS I to PCI/ PCI- X mul ti functi on c on tr oller
•Supports a 32-bit or 6 4-bit PCI/PCI-X DMA bus m aster
•Reduces time to mark et with the Fusion-MPT architecture
–Single driver binary for SCSI and F ibre Channel products
–Thin, easy to develop drivers
–Reduced integration and certification effort
•Provides integra ted LVDlink transceivers
1.8.4 Flexibility
These features inc rease the flexibility of t he LSI53C1030:
•U niversal LVD transceivers are backward compati ble with SE
devices
•Provides a flexible programming interface to tune I/O performance or
to adapt to unique SCS I devices
•Su pports MSI or pin-based ( INTx/ or ALT_INTx/) interrupt signalling
•C an respond with multipl e SCSI IDs
•I s compatible with 3.3 V and 5.0 V PCI signall ing
–Drives and receives 3.3 V PCI signals
–Receives 5.0 V PCI if the PCI5VB IAS pin connects to 5 V, but
This chapter provid es a subsytem level overvi ew of the LSI53C1030, a
discussion of the Fus ion-MPT architecture, and a fu nctional description
of the LSI53C1030 inte rfaces. This chapter conta ins the following
sections:
•Section 2.1, “Block Diagram Description”
•Section 2.2, “Fusi on-MPT Architecture Ove rview”
•Section 2.3, “PCI Fu nctional Description”
•Section 2.4, “Ultra 320 SCSI Functional De scription”
•Section 2.5, “Exter nal Memory Interface”
•Section 2.6, “Seri al EEPROM Interface”
•Section 2.7, “Zero Cha nnel RAID”
•Section 2.8, “Multi- ICE Tes t Interface”
The LSI53C1030 is a hi gh performance, intellig ent PCI-X to Dual
Channel Ultra320 SCSI M ultifunction Contr oller. The LSI53C1030
supports the PCI Lo cal Bus Specific ation, Revision 2.2, the PCI-X Addendum to the PCI Lo cal Bus Specifica tion, Revision 1.0a, an d the
proposed SCSI Parallel Interface-4 (SPI-4) draft standard.
The LSI53C1030 employ s the LSI Logic Fusion- MPT architecture to
ensure robust system performance, to support bi nary compatibility o f
host software between the LSI Logic SC SI and Fibre Channe l products,
and to significantly reduce software developm ent time. Refer to the
Fusion-MPT Device Mana gement User ’s Guide for more information on
the Fusion-MPT archite cture.
LSI53C1030 PCI-X to Du al Channel Ultra320 SCS I Multifunction Controller2-1
The LSI53C1030 consi sts of three major modu les: a host interface
module and two indepe ndent Ultra320 SCSI ch annel modules. The
modules consist of the following component s:
•Host Interface Module
–Up to a 64-bit, 133 MHz PCI/PCI-X Interfa ce
–System Interface
–I/O Processor (IOP)
–DMA Arbiter and Router
–Shared RAM
–External Memory Interface
◊Fla sh ROM Memory Controller
◊NVSRAM
–Timer and Configuratio n Control
◊Devic e Configuration Controll er
◊Se rial EEPROM Interface Co ntroller
◊GPIO Interface
◊Chip Timer
The host interface modu le provides an interface between the host dr iver
and the two SCSI channels . The host interface module c ontrols system
DMA transfers and the ho st side of the LSI Logic Fus ion-MPT
architecture. It als o supports th e external m emory, serial EEPROM, and
General Purpose I /O (GPIO) i nterface s. This s ection prov ides a de tailed
explanation of the h ost interface submodule s.
The LSI53C1030 provi des a P CI- X inte rf ace th at supports up to a 64-bit,
133 MHz PCI-X bus. The i nterface is compatible wi th all previous
implementations o f the PCI specificatio n. For more informatio n on the
PCI interface, refer to Section 2.3, “PCI Functional Descr iption.”
2.1.1.2 System Interfa ce
The system interface efficiently passes messages between the
LSI53C1030 and other I/O agents using a high performance, packetized,
mailbox architectur e. The system interface c oalesces PCI interrupts to
minimize traffic on the PC I bus and maximize syste m performance.
All host accesses to the IOP, exter nal memory, and timer and
configuration subsys tems pas s t hroug h the s yst em int erf ace and use the
primary bus. The hos t system initia tes data transaction s on the primary
bus with the syste m interface registers . PCI Memory Spac e [0] and the
PCI I/O Base Addr ess registers ident ify the location of the s ystem
interface register s et. Chapter 4, "PCI Host Regi ster Description",
provides a bit level d escription of the syst em interface register s et.
2.1.1.3 I/O Processor ( IOP)
The LSI53C1030 I/O pr ocessor (IOP) is a 32- bit ARM966E-S RISC
processor. The IOP controls the system inter face and uses the LSI Logic
Fusion-MPT architecture to manage the host side of non-DM A access es
to the Ultra320 SCSI bus . The context manager uses the Fusion-MPT
architecture to co ntrol the SCSI side of data transfers. The IOP and
Context Manager compl etely manage all SCSI I/Os without host
intervention. Refer to Section 2.2, “Fusion-MPT Architec ture Overview,”
for more informatio n on the Fusion-MPT arch itecture
2.1.1.4 DMA Arbiter and Router
The descriptor based DMA Arbiter and Router s ubsystem manages the
transfer of memory blocks between local memory and the host system.
The DMA channel i ncludes PCI bus mast er interface logic, the in ternal
bus interface logic, and a 256-byte system DMA FIFO.
The host interface module physically contains the 96 Kbyte shared RAM.
However, both the host interface m odu le and the SCSI channel mod ule s
access the shared RAM. The shared RAM holds a portion of the IOP and
context manager firmwar e, as well as the request me ssage queue and
reply message queue . All non-DMA data transf ers that use the request
and reply message q ueues pass through the shared RAM.
2.1.1.6 External Memory Controller
The external memor y control subsystem provides a direct inter face
between the primary bus and the external memory subsystem. MA D[7 :0]
and MADP[0] comprise th e external memory bus. The LSI53C1030
supports the Flas h ROM and NVSRAM interfac es through the external
memory controller. The Flash ROM is opti onal if the LSI53C103 0 is not
the boot device and a s uitable driver exists to initialize the device. T he
LSI53C1030 uses the NVS RAM for IM technology. For a detailed
description of this bloc k r efer to Section 2.5, “External Memory Interface.”
During power up or reset th e LSI53C1030 uses the MAD[1 5:0] and
MADP[1:0] signals as Power-On Sense pins, wh ich configure the
LSI53C1030 through t heir pull-up or pull-down s ettings. Refer to
Section 3.10, “Power-On Sense Pins Description,” for a description of the
Power-On Sense pin c onfiguration options .
2.1.1.7 Timer, GPIO, and Configuration
This subsystem p rovides a free running ti mer to allow event time
stamping and also controls the general pu rpose I/O (GPIO), LED, and
serial EEPROM inter faces. T he LSI53 C103 0 uses th e free running timer
to aid in tracking and managing S CSI I/Os. The LS I53C1030 generat es
the free running timer’s microsecond time base by dividing the SCSI
reference clock by 40.
The LSI53C1030 provi des eight GPIO pi ns (GPIO[7:0]). The se pins are
under the control of the LSI53C1 030 and defa ult to th e input m ode upo n
PCI reset. The LSI53C 1030 also provides three LED pins: A_LED/,
B_LED/, and HB_LED/. E ith er firmware or hardware control A_L ED/ a nd
B_LED/. The LSI53C1030 firmware controls HB_LE D/ (heartbeat LED),
which indicates that the IOP is operational.
A 2-wire serial interface provides a connection t o a nonvolatile exter nal
serial EEPROM. T he serial EEPROM s tores PCI configuration
parameters for the L SI53C1030. Refer to Section 2.6, “Serial EEPROM
Interface,” for more i nformation concerning the s erial EEPROM.
2.1.2 SCSI Channel Module Description
The LSI53C1030 provides two independent Ultra320 SCSI bus channels.
Separate Ultra320 SCSI cores, datapath engines, and context managers
support each SCSI ch annel. Refer to Sectio n 2.4, “Ultra320 SCSI
Functional Description,” for an operational description of the LSI53C1030
SCSI bus channels .
2.1.2.1 Ultra320 SCSI Core s
The Ultra320 SCSI co res control thei r individual SCSI b us interface.
2.1.2.2 Datapath Engines
The datapath engine s manage the SCSI side of DM A transactions
between their indivi dual SCSI bus and the host system.
2.1.2.3 Context Managers
The context manager s are ARM966E-S proc essors. Each context
manager controls the SCSI channel side of the LSI53C1030 Fusion-MPT
architecture for their individual SCSI bu s. The context managers control
the outbound queues, tar get mo de I/O mapping, disconnect and reselec t
sequences, scatter /gather lists, and status r eports.
2.2 Fusion-MPT Architecture Overview
The Fusion-MPT architec ture provides two I/O methods for the host
system to communi cate with the IOP: the s ystem interface do orbell and
the message queues.
The system interface d oorbell is a simp le message pass ing mechanism
that allows the PCI ho st system and IOP to ex change single 32-bit
Dword messages. When the host system writes to the d oorbell, the
LSI53C1030 hardware gene rates a maskabl e interrupt to th e IOP, which
can then read th e doorbell v alue and ta ke the approp riate action. When
the IOP writes a value t o the doorbell, the LSI53C10 30 hardware
generates a maska ble i nterr upt to the host system. The h ost s yst em can
then read the doorbell value and take the app ropriate action.
There are two 32-bit m essage queu es: the requ est mess age queue and
the reply message q ueue. The host uses the requ est queue to request
an action by the LSI53C1030, and the LSI53C1030 uses the reply queue
to return status inform ation to the host. The reques t message queue
consists of only th e request post FIFO. The repl y message queue
consists of both the reply po st F IFO an d the re p ly fr ee FIF O. The s ha red
RAM contains the m essage queues.
Communication using the message queues occu rs through request
messages and reply message s. Requ es t mes sage f rame des c ripto rs are
pointers to the request m essage frames and are pas sed through the
request post FIFO. T he request message fr ame data structure is u p to
128 bytes in length and incl udes a mess age header and a pay load. The
header uniquely ide ntifies the message. The payload contains
information that is specific to the request. R eply message frame
descriptors have one of two formats and are p assed through the reply
post FIFO. When indicating the succes sful comp letion of a SCSI I/O, the
IOP writes the reply message frame descriptor using th e Context Reply
format, which is a mess age context. If a SCSI I/O do es not complete
successfully, the IOP uses the Address Reply for mat. In this case, the
IOP pops a reply messa ge frame from the reply fr ee FIFO, generates a
reply message desc ribing the error, writes the reply mess age to system
memory, and writes the address of the reply message frame to the repl y
post FIFO. The host can then read the reply mes sage and take the
appropriate action.
The doorbell mecha nism provides both a high -priority communication
path that interrupts th e host system device d river and an alternative
communication pa th to the message queues. S ince data transport
through the system door bell occurs a single Dword at a time, use the
LSI53C1030 messag e queues for normal operati on and data transport.
2.3 PCI Functional Description
The host PCI interfac e complies with the PCI Lo cal Bus Specificatio n,
Revision 2.2, and the PC I-X Addendum to the PCI Local Bus
Specification, Revision 1.0a. The LSI53C1030 supports up to a 133 MHz,
64-bit PCI-X bus. The LSI53C1030 provides su pport for 64-bit
addressing with Dual Address Cycle (DAC).
The LSI53C1030 is a true multifunction PCI-X dev ice and presents a
single electrical l oad to the PCI bus. The LSI5 3C1030 uses a single
REQ/-GNT/ pair to arbitr ate for PCI bus mastership. Separate interrupt
signals for PCI Func tion [0] and PCI Function [1 ] allow independent
control of the two P CI functions.
2.3.1 PCI Addressing
The three physical a ddress spaces the PCI spe cification defines a re:
•PCI Configuratio n Space
•PCI I/O Space for operat ing registers
•PCI Memory Space for operating registers
The following secti ons describe the PCI add ress spaces.
2.3.1.1 PCI Configurat ion Space
The LSI53C1030 defines an independent set of PCI Configuration Space
registers for each PCI function. Each configuration space is a contiguous
256 x 8-bit set of a ddresses. The syst em BIOS initialize s the
configuration reg isters using PCI configuration cycles. Th e LSI53C1030
decodes C_BE[3:0]/ to d etermine if a PCI cycle intends to access the
configuration regist er space. The IDS EL signal beh aves as a chip sele ct
signal that enables ac cess to the configurati on register space on ly. The
LSI53C1030 ignores c onfiguration read/write cycles when IDSEL is not
asserted.
Since the LSI53C1030 i s a multifunction PCI devic e, bits AD[10:8]
decode either the PCI Fu nction [0] Configuration S pace (AD[10:8] =
0b000) or the PCI Functio n [1] Configu ration S pace (AD[10:8 ] = 0b001).
The LSI53C1030 does not r espond to any other en codings of AD[10:8 ].
Bits AD[7:2] selec t one of the sixty-four Dword registers in the device’s
PCI Configuration S pace. Bits AD[1:0] determ ine if the configuration
command is a Type 0 Configuration Com mand (AD[1:0] = 0b00) or a
Type 1 Configuration Command (AD[1:0] = 0b01). Since the LSI53C1030
is not a PCI Bridge device, a ll PCI Config uration Comma nds desig nated
for the LSI53C1030 mu st be Type 0. C_BE[3:0]/ address the indivi dual
bytes within each Dword and d etermine the type of access to perform.
2.3.1.2 PCI I/O Space
The PCI specificat ion defines I/O Space as a contiguous 32-bit I/O
address that all system re sour ces shar e, inc luding the LSI53 C1030. T he
I/O Base Address register determines the 256-byte PCI I/O area that the
PCI device occupie s.
2.3.1.3 PCI Memory Space
The LSI53C1030 contai ns two PCI memory spaces: PCI M emory
Space [0] and PCI Mem ory Space [1]. PCI Memory Sp ace [0] supports
normal memory accesses, while PCI Memory Space [1] supports
diagnostic memory accesses. The LSI53C 1030 requires 64 Kbyte s of
memory space.
The PCI specificat ion defines memory space as a contiguous 64-bit
memory address tha t all system resources share. The Memory [0] Lo w
and Memory [0] High regis ters determine whic h 64 Kbyte memory ar ea
PCI Memory Space [0] occup ies. The Memory [1] Low and Memory [1]
High registers determin e which 64 Kbyte memory area PCI Memory
Space [1] occupie s.
2.3.2 PCI Commands and Functions
Bus commands indic ate to the target the type of transa ction the master
is requesting. The master encodes the bus commands on the C_BE[3:0]/
lines during the add ress phase. The PCI bus c ommand encodings
appear in Table 2.1.
The LSI53C1030 ignores this com mand a s a sl ave and n ever generat es
it as a master.
2.3.2.3 I/O Read Command
The I/O Read command reads data from an agent ma pped in the I/O
address space. Wh en decoding I/O commands , the LSI53C1030
decodes the lower 32 a ddress bits and ignores the upper 32 address
bits. The LSI53C1030 s upports this command when operating in either
the PCI or PCI-X bus m ode.
2.3.2.4 I/O Write Command
The I/O Write command writes data to an agent mapped in the I/O
address space. Wh en decoding I/O commands , the LSI53C1030
decodes the lower 32 a ddress bits and ignores the upper 32 address
bits. The LSI53C1030 s upports this command when operating in either
the PCI or PCI-X bus m ode.
2.3.2.5 Memory Read Command
The LSI53C1030 uses the Memory Read command to read data from an
agent mapped in the memor y addres s space . The targe t can per form an
anticipatory read if such a read produces no side effects. The
LSI53C1030 supports t his command when oper ating in the PCI bus
mode.
2.3.2.6 Memory Read Dword Command
The Memory Read Dword command reads up to a single Dword of data
from an agent mapped in the memory address sp ace and can only be
initiated as a 32-bi t transaction. The target can p erform an anticipatory
read if such a read pro duces no side effects. The LSI53C103 0 supports
this command when oper ating in the PCI-X bus m ode.
2.3.2.7 Memory Write Command
The Memory Write command wr ites data to an agent mapped in the
memory address s pace. The target assumes responsibility for d ata
coherency when it r eturns “ready.” The LSI53C1030 supports t his
command when opera ting in either the PCI or PCI- X bus mode.
2.3.2.8 Alias to Memory Read Block Command
This command is res erved for future implemen tations of the PCI
specification. Th e LSI53C1030 never gene rates this command as a
master. When a slave, the LSI53C1030 supports this command using the
Memory Read Block command.
2.3.2.9 Alias to Memory Write Block Command
This command is res erved for future implemen tations of the PCI
specification. Th e LSI53C1030 never gene rates this command as a
master. When a slave, the LSI53C1030 supports this command using the
Memory Write Block com mand.
2.3.2.10 Configuration Read Command
The Configuration Rea d command reads the configu ration space of a
device. The LSI53C1030 never generates this command as a master, but
does respond to it as a slave. A device on th e PCI bus selects the
LSI53C1030 by asser ting its IDSEL signal whe n AD[1:0] equal 0b00.
During the address p hase of a configu ration cycle , AD[7:2] add ress one
of the 64 Dword registe rs in the configuration sp ace of each device.
C_BE[3:0]/ address the indi vidual bytes within eac h Dword register and
determine the type of access to perform. Bits AD[10:8] address either the
PCI Function [0] Config uration Space (AD[10:8] = 0 b000) or the PCI
Function [1] Configuration Space (AD[10:8] = 0b001). The LSI53C10 30
treats AD[63:11] as logical don’t cares.
2.3.2.11 Configuration Write Command
The Configuration Write co mmand writes the configura tion space of a
device. The LSI53C1030 never generates this command as a master, but
does respond to it as a slave. A device on th e PCI bus selects the
LSI53C1030 by asserting its IDSEL signal when bits AD[1:0] equal 0b00.
During the address pha se of a configura tion cycle, bit s AD[7:2] address
one of the 64 Dword regis ters in the conf igurat ion spa ce of each devic e.
C_BE[3:0]/ address the indi vidual bytes within eac h Dword register and
determine the type of ac ce ss to per form . Bits AD[10:8] decode either th e
PCI Function [0] Config uration Space (AD[10:8] = 0 b000) or the PCI
Function [1] Configuration Space (AD[10:8] = 0b001). The LSI53C10 30
treats AD[63:11] as logical don’t cares.
2.3.2.12 Memory Read Mul tiple Command
The Memory Read Multip le command is identical to the Memory Read
command, except it additionally indicates that the master intends to fetch
multiple cache lines before disconnecting. The LSI53C1030 supports PCI
Memory Read Multiple functi ona li ty wh en ope rating in the PCI mode and
determines when to is sue a M emory Read M ultiple comma nd instead o f
a Memory Read command.
Burst Size Selection – The Read Multiple co mmand reads multiple
cache lines of dat a duri ng a si ngle b us owne rship. Th e num ber of cach e
lines the LSI53C103 0 reads is a multipl e of the cache line si ze, which
Revision 2.2 of the PCI spe cification provide s. The LSI53C103 0 selects
the largest multiple of th e cache line size based on the amount of data
to transfer.
2.3.2.13 Split Completion Command
Split transactions i n PCI-X replace the dela yed transactions in
conventional PCI. The LSI53C1030 supports up to eight outstanding split
transactions when oper ating in the PCI-X mode. A sp lit transaction
consists of at lea st two se parate b us transac tions: a s plit reques t, which
the requester initiates , and one or more split com pletion commands,
which the completer i nitiates. Revision 1.0a of the PCI-X addendum
permits split transactio n com pleti on for th e Memo ry Read Block , Alias to
Memory Read Block, Memory Read Dword, Interrup t Acknowledge,
I/O Read, I/O Write, Configu ration Read, and Configu ration Write
commands. When oper ating in the PCI-X mode, the LSI53C1030
supports the Split Co mpletion command for all of these commands
except the Interrupt Acknowledge command, whi ch the LSI53C1030
neither responds to nor generates.
2.3.2.14 Dual Address Cycles (DAC) Command
The LSI53C1030 performs Dual Address Cycles (DAC), per the PCI
Local Bus Specifi cation, Revision 2.2. T he LSI53C1030 supports thi s
command when opera ting in either the PCI or PCI- X bus mode.
This command is iden tical to the Memory Read c ommand except it
additionally ind icates that the mast er intends to fetch a com plete cache
line. The LSI53C1030 supports this command when operating in the PCI
mode.
2.3.2.16 Memory Read Bloc k Command
The LSI53C1030 uses this command to read fro m memory. The
LSI53C1030 supports thi s command when op erating in the PCI- X mode.
2.3.2.17 Memory Write and Invalidate Command
The Memory Write and Inva lidate command is id entical to the Memory
Write command, except i t additio nally g uarantees a minimum transfer o f
one complete cache line. The master uses this command when it intends
to write all bytes wit hin the addressed ca che line in a single PCI
transaction unless i nterrupted by the target. Th is command requires
implementation of th e PCI Cache Line Size register. The LSI53C1030
determines when to i ssue a Write and I nvalidate com mand instead o f a
Memory Write command and suppor ts this command whe n operating in
the PCI bus mode.
Alignment – The LSI53C10 30 uses the calculated line size value to
determine if the cu rrent address aligns to the cache line size . If the
address does not al ign, the LSI53C1030 bursts data using a noncache
command. If the startin g address aligns, the L SI53C1030 issues a
Memory Write and Inval idate comm and using the c ache line siz e as the
burst size.
Multiple Cache Line Transfers – The Me mory Write and Invalidate
command can write multiple cache line s of data in a single bu s
ownership. The LSI53C10 30 issues a burst transfe r as soon as it
reaches a cache li ne boundary. The PCI Local Bus specificati on states
that the transfer size m ust be a multiple of the cache line size. T he
LSI53C1030 selects the largest multip le of the cache li ne size base d on
the transfer size. When the DMA buffer contains less data than the value
Cache Line Size register specifies, th e LSI53C1030 issues a Me mory
Write command on the ne xt cache boundary to co mplete the data
transfer.
The LSI53C1030 uses this command to burst dat a to memory. The
LSI53C1030 supports t his command when oper ating in the PCI-X bus
mode.
2.3.3 PCI Arbitration
The LSI53C1030 contains in dep ende nt bu s ma stering functions for each
of the SCSI function s and for the s ystem interfac e. T he syste m inte rface
bus mastering func tion manages DMA operati ons as well as the reque st
and reply message f rames. The SCSI channe l bus mastering func tions
manage data transfe rs across the SCSI channel s.
The LSI53C1030 uses a single REQ/-GNT/ signal pai r to arbitrate for
access to the PCI bus. To ensure fair access to the PCI bus, the intern al
arbiter uses a round robin arbitration scheme to decide which of the three
internal bus mastering fun ctions can arbitrate for access to the PCI bus.
2.3.4 PCI Cache Mode
The LSI53C1030 supports an 8-bi t Cache Line S ize reg ister. The Cache
Line Size register p rovides the ability to sen se and react to nonalign ed
addresses corres ponding to cache line boun daries. The LSI53C1030
determines when to is sue a PCI cache comma nd (Memory Read Line,
Memory Read Multiple , and Memory Write and Inval idate), or PCI
noncache comm and (Memory Read or Mem ory Write command).
2.3.5 PCI Interrupts
The LSI53C1030 signa ls an interrupt to the host processor e ither using
PCI interrupt pins, I NTx/ and ALT_INTx/, or using Message Signall ed
Interrupts (MSI). If usin g the PCI interrupt pin s, the Interrupt Request
Routing Mode bits in the Host Interrupt Mask register configure the
routing of each inter rupt to either the INTx/ and/o r the ALT_INTx/ pin.
The Interrupt Pin regi ster configures the routing of each PCI function’s
interrupt signals t o either the interrup t A pins (INTA/, ALT_INTA/) or the
interrupt B pins (INTB/ or ALT_INTB/).
If using MSI, the LSI53C1 030 does not signal inter rupts on INTx/ or
ALT_INTx/. Note that enabling MSI to mask PC I interrupts is a violation
of the PCI specificati on. Each PCI function of the LSI53C1030
implements its ow n MSI register set. The LSI53 C1030 supports one
requested message a nd dis ables MS I after the chip pow ers-up or res ets.
The Host Interrupt Ma sk register also prevents th e assertion of a PCI
interrupt to the host processor by selectively masking reply interrupts and
system doorbell in terrupts. This reg ister masks both pin -based and MSIbased interrupts.
2.3.6 Power Management
The LSI53C1030 compl ies with the PCI Power Managem ent Interface
Specification, Revision 1.1, and the PC2001 System Design Gui de. The
LSI53C01030 support s the D0, D1, D2, D3
D0 is the maximum power s tate, and D3 is the minimum power state.
Power State D3 is furt her categorized as D3
function off places it in the D3
Bits [1:0] of the Powe r Management Control/Status register
independently contr ol the power state of each P CI device on the
LSI53C1030. Table 2.2 provides the power state bit settin gs.
Power State.
cold
, and D3
hot
or D3
hot
power states.
cold
. Powering a
cold
Table 2.2Power States
Power Management Control and
Status Register, Bits [1:0]Power StateFunction
0b00D0Maximum Po wer
0b01D1Snooze Mode
0b10D2Coma Mode
0b11D3Minimum Power
The following sectio ns describe the PC I Function Power St ates D0, D1,
D2, and D3. As the device tr ansitions from one power l evel to a lower
one, the attributes that occur in the higher power state level carry into
the lower power sta te level. For example, Po wer State D2 includes the
attributes for Power State D1, as well as the attrib utes defi ned for Power
State D2. The follow ing se ct ion s d es cri be th e P C I Fun cti on powe r st a tes
in conjunction with each SCSI function. Power state actions are separate
for each SCSI function.
Power State D0 is the maximum power sta te and is the powe r-up defau lt
state for each functi on. The LSI53C1030 is f ully functional in this st ate.
2.3.6.2 Power State D 1
Per the PCI Power Manag eme nt Inte rfac e Sp eci fi ca tio n, Po wer Sta te D 1
must have an equal or lower power level than Power State D0. A function
in Power State D1 pl aces the SCSI core in the s nooze mode. In the
snooze mode, a SCS I reset does not generate an IRQ/ signal.
2.3.6.3 Power State D 2
Per the PCI Power Manag eme nt Inte rfac e Sp eci fi ca tio n, Po wer Sta te D 2
must have an equal or lower power level than Power State D1. A function
in this state places the SCSI core in the coma mo de. Placing the PCI
Function in Power State D2 disab les the SCSI and DMA interrupts , and
suppresses the follow ing PCI Configuratio n Space Command regis ter
enable bits:
•I/O Space Enable
•Memory Space En able
•Bus Mastering E nable
•SERR/Enable
•Enable Parity Erro r Response
Therefore, the function ’s memory and I/O spaces cannot be acces sed,
and the PCI function can not be a PCI bus master.
If the PCI function is chang ed from Power State D2 to Powe r State D1
or D0, the PCI function res tores the previous values of the PCI
Command register and as serts any interrupts tha t were pending before
the function entered Power State D2.
2.3.6.4 Power State D 3
Per the PCI Power Manag eme nt Inte rfac e Sp eci fi ca tio n, Po wer Sta te D 3
must have an equal or lower power level than P ower State D2. Power
State D3 is the minim um power state an d includes t he D3
settings. D3
and D3
hot
allows the device to tr ansition to D0 using softwar e.
by applying VCC and r esetting the device.
Placing a function i n Power State D3 puts the LS I53C1030 core in the
coma mode, clears the function’s PCI Command register, and continually
asserts the function’s soft reset. A sserting soft reset clears all pending
interrupts and 3-state s the SCSI bus.
2.4 Ultra320 SCSI Functional Description
The LSI53C1030 provi des two indepen dent Ultra320 SCS I channels on
a single chip. Ea ch channel supports wi de SCSI synchronous tr ansfer
rates up to 320 Mbytes / s a cros s an S E o r LVD SCSI bus. The integrate d
L VDlink transceivers support both LVD and SE signals and do not require
external transceive rs. The LSI53C1030 c ontroller supports th e Ultra320
SCSI, Ultra160 SCSI, Ultra2 SCSI, Ultra SCSI, and Fast SCSI interfaces.
2.4.1 Ultra320 SCSI Features
can transition to D0
cold
This section describes how the LSI53C 1030 implements the features in
the SPI-4 draft spec ification.
2.4.1.1 Parallel Prot ocol Request (PPR)
A SCSI extended mess age negotiates the PPR parame ters. The PPR
parameters include th e (1) transfer period, (2) ma ximum REQ/ACK
offset, (3) QAS, (4) margin control settings (MCS), (5) transfer width,
(6) IU_Request, (7) write flow, (8) read streaming, (9) RTI,
(10) precompensa tion enable, (11) information unit transfers, and the
(12) DT data phases be tween an initiator and a target .
2.4.1.2 Double Transition (DT) Clocking
Ultra160 SCSI and Ultra32 0 SCSI implement DT clock ing to provide
speeds up to 80 mega transfers per second (meg atransfers/s) for
Ultra160 SCSI, and up to 160 meg atransfe rs/s for Ultra3 20 SCSI. Whe n
implementing DT clocking, a SCSI device samples data on both the
asserting and dea sserting edge of REQ/A CK. DT clocking is onl y valid
using an LVD SCSI bus.
2.4.1.3 Intersymbol Int erference (ISI) Compens ation
ISI Compensation u ses paced transfers a nd preco mpensati on to enab le
high data transfer ra tes. Ultra32 0 SCSI da ta transfers require t he use of
ISI Compensation.
Paced Transfers – The initiator an d target must establish a paced
transfer agreement that specifies the REQ/ACK o ffset and the transfer
period before using this feature. Devices can only perform paced
transfers during Ultra 320 SCSI DT data p hases. In pace d transfers, the
device sourcing t he data drives the REQ/A CK signal as a free run ning
clock. The tran sition of the REQ /ACK signal, ei ther the assert ion or the
negation, clocks da ta across the bus. For suc cessful completion of a
paced transfer, the number of ACK tra nsitions m ust eq ual the number of
REQ transitions and bo th the REQ and ACK lines mus t be negated.
The P1 line indicate s valid data in 4-byte qu antities by using its pha se.
The transmitting d evice indicates th e start of valid data state by hold ing
the state of the P1 line for the first two data transf er periods. Beginning
on the third data trans fer period, the transmitting d evice continues the
valid data state by toggling the state of the P1 line every two da ta
transfer periods for as long as the d ata is valid. The transmitting device
must toggle the P1 lin e coincident with the REQ /ACK assertion. The
method provides a mi nimum data valid period of two transfer periods.
To pau se the d ata tra ns fer, the transmitting dev ic e rev er ses the phas e o f
P1 by withholding the n ext transition of P1 at th e start of the first two
invalid data transfer periods. Beginning with the third invalid data transfer
period, the transmitti ng device to ggles the P 1 line ever y two inva lid data
transfer periods unti l it sends val id data. The tra nsmitting dev ice returns
to the valid data stat e by reversing the phase of the P1 line . The invalid
data state must experi ence at least o ne P1 transi tion befor e returning to
the valid data state. This metho d pr ov ide s a mini mum data i nv ali d peri od
of four transfer periods .
Figure 2.2 provides a waveform diagram of pac ed data transfers and
The LSI53C1030 uses the PPR negoti ation that the SPI-4 draft stan dard
describes to establi sh a paced transfer agreem ent for each initiatortarget pair.
Precompensation – When transmitting in the Ultra320 SCS I mode, the
LSI53C1030 uses precom pensation to adjust the strength of the REQ,
ACK, parity, and data signals. When a signal transitions to HIGH or LOW,
the LSI53C1030 boosts the signal drive strength for the first data transfer
period, and then lo wers the signal drive stren gth on the second data
transfer period if the s ignal remains i n the same state. The LSI53 C1030
maintains the lower signal drive strength until the signal again transiti on s
HIGH or LOW. Figure 2.3 illustrates the dr ivers performance wi th
precompensation ena bled and disabled.
Packetized transf ers are also referr ed to as information un it transfers.
They reduce overhea d on the SCS I bus by merging sev eral of the S CSI
bus phases. Packetized transfers can only occur in DT Data phases. The
initiator and target m ust establish either a DT sy nchronous transfer
agreement or a paced tr ansfer agreeme nt before perfor ming packetize d
transfers.
The number of bytes in an inform ation unit transfer is always a mul tiple
of four. If the number of bytes to tr ansfer in the i nformation unit i s not a
multiple of four, the LSI53C1030 transmi ts pad bytes to bring the b yte
count to a multiple of four.
2.4.1.5 Quick Arbitration and Selection (QAS)
When using packetize d tr ans fers , QAS al lo ws devices to arbitrate for the
bus immediately after th e message phase. QAS re duces the bus
overhead and max imizes bu s bandwi dth by sk ipping the bus fr ee phas e
that normally follows a SCSI connection.
To perform QAS, the target sends a QAS request message to the initiator
during the message phase of the bus . QAS capable dev ices snoop the
SCSI bus for the QAS r equest message. If a QAS request message is
seen, devices can imm ediately move to the arbi tration phase without
going to the bus fre e phase. The LSI53C1030 em ploys a fairness
algorithm to ensu re that all devices have equal bus access .
2.4.1.6 Skew Compensa tion
The LSI53C1030 provide s a method to account for a nd control system
skew between the cl ock and data signals. S kew compensation is only
available when the dev ice operates in the Ultra3 20 SCSI mode. The
initiator-target pa ir uses the training sequ ences in the SPI-4 draft
standard to determine the skew compensation. Depen ding on the state
of the RTI bit in the PPR negotiation, the LSI53C1030 can either execute
this training pattern during each con nection, or can e xecute the training
pattern, store the adjustment parameters, and recall them on subsequent
connections with the g iven device. The targ et determines when to
execute the training patt ern.
2.4.1.7 Cyclic Redundancy Check (CRC)
Ultra320 SCSI and Ultra160 SCSI devices employ CRC as an error
detection code during the DT Data phases. These devic es transfer four
CRC bytes during the DT Da ta phases t o ensure relia ble data tra nsfers.
2.4.1.8 SureLINK Domain Validation
SureLINK Domain Validation establishes t he integrity of a SCSI bus
connection between an initiator and a target. Under the SureLINK
Domain Validation procedure, a host que ries a device to determin e its
ability to communic ate at the negotiated data t ransfer rate.
SureLINK Domain Validation provides 3 le vels of integrity check ing:
Basic (Level 1) with inquiry command, E nhanced (Level 2) with
read/write buffer, and Margined (Level 3) with d rive strength margining
and slew rate control . The basic check co nsists of an inquir y command
to detect gross proble ms. The enhanced check sends a known data
pattern using the rea d and write buffer commands to d etect additional
problems. The margin ed check verifies that the physical parameters
have a reasonable oper ating margin. Use SureLINK Domain Validation
only during the diagn ostic system checks and no t during norma l system
operation. If transmi ssion errors occur dur ing any of these chec ks, the
system can reduc e the tr ansmis sion ra te on a per-t arget bas is t o ensu re
robust system operation.
2.4.2 SCSI Bus Interface
This section desc ribes the SCSI bus mode s that the LSI53C1030
supports and the SCSI bus termination method s necessa ry to ope rate a
high speed SCSI bus.
2.4.2.1 SCSI Bus Modes
The LSI53C1030 suppor ts SE and LVD transfers. To increase device
connectivity and S CSI cable length, the LSI53C1030 features LVDlink
technology, which is the LSI Logic implementation of LVD SCSI. LVDlink
transceivers provid e the inherent reliab ility of differential SCSI and a
long-term migration p ath for faster SCSI trans fer rates.
The A_DIFFSENS or B_DI FFSENS signals detect the d ifferent input
voltages for HVD, LVD, and SE. The LSI53C1030 drivers are tol erant of
HVD signal strengths , but do not support the H VD bus mode. The
LSI53C1030 SCSI d evice 3-states its SCSI d rivers when it detec ts an
HVD signal level.
2.4.2.2 SCSI Termination
The terminator netwo rks pull signals to an i nactive voltage level a nd
match the impedance se en at the end of the cable to the characterist ic
impedance of the ca ble. Install terminator s at the extreme ends o f the
SCSI chain, and on ly at the end s; all S CSI buses m ust hav e ex actly two
terminators.
Note:
If using the LSI53C1030 in a design with an 8-bit SCSI bus,
designers must termi nate all 16 data lines.
The LSI53C1030 provide s Flash ROM, NVSRAM, and s erial EEPROM
interfaces. The Flash ROM interface stores the SCSI BIOS and firmware
image. The Flash ROM is optional if the LSI53C10 30 is not the boot
device and a suitabl e driver exists to init ialize the LSI53C1030.
Integrated Mirroring (IM) technology require s an NVSRAM. The
nonvolatile externa l serial EEPROM s tores configurat ion parameters for
the LSI53C1030.
2.5.1 Flash ROM Interface
The Flash ROM interface multi plexes the 8-bit address and data buses
on the MAD[7:0] pins. The inter face latches the address in to three 8-bit
latches to support u p to 1 Mbyte of address space. The interface
supports byte, word, and Dword accesses. The LSI 53C1030 Dword
aligns Dword reads, word alig ns word r eads, an d byte alig ns byte re ads.
The remaining bits fr om word and byte reads are meaningless.
The MAD[2:1] Power-On sens e pin configuratio ns define the size of the
Flash ROM address space. Table 2.3 provides the pin encoding for these
pins. By default, inte rnal logic pulls these pi ns down to indicate that no
Flash ROM is present.
Table 2.3Flash ROM Size Programming
MAD[2:1] OptionsFlash ROM Size
0b00No Flash ROM present (Default)
0b01Up to 1024 Kbytes
0b10
0b11
1. Choose t his settin g for a 128 Kb yte or 512 K byte Flash R OM.
The LSI53C1030 define s o nl y t he m iddle ( MA [15:8 ]) an d l ower ( MA [7:0 ])
address ranges if the Flash ROM addressab le space is 64 Kb ytes or
less. The LSI53C1030 defines the upper (MA[21:16]), middle (MA[15:8]),
and lower (MA[7:0]) address ranges if the Flash ROM addressable space
is 128 Kbytes or more. Figure 2.4 provides an exampl e of a Flash ROM
configuration.
Figure 2.4Flash ROM Block Diagram
FLSHALE[1]/
FLSHALE[0]/
FLSHALE[1]/
FLSHALE[0]/
MAD[7:0]
FLSHCE/
MOE/
BWE[0]/
Upper Address
CK
D
Middle Address
CK
D
Lower Address
CK
D
Q
Q
Q
A[21:16]
A[15:8]
A[7:0]
Flash ROM (512 K x 8)
D[7:0]
CE/
OE/
WE/
The LSI53C1030 imp lements a Flash signa ture recognition mecha nism
to determine if the Fl ash contains a valid i mage. The Flash can be
present and not co ntain a valid image either before its initial
programming or during bo ard testing. The first access t o the Flash is a
16-byte burst read beg inning at Flash address 0x 000000. The
LSI53C1030 compares the values read to the Flash signature values that
Ta ble 2.4 provides. If the sig nature values match, the LSI53C1030
performs the instr uction located at Flas h address 0x000000. If the
signature values do no t match, the LSI53C103 0 records an error and
ignores the Flash ins truction. The Flash si gnature does not includ e the
first three bytes of Flash memor y as thes e bytes c ontain a branch offset
instruction.
Write journaling for IM requires an NVSRAM. The LSI53C1030 FusionMPT firmware is capable of ma intainin g a second di sk as a mirr or of the
boot drive. To do so, the LSI Logic Fusion-MPT firmware writes to both
the boot drive and the m irror drive. The mirror ing of the boot drive is
transparent to the BIOS , drivers, and operating sy stem. Figure 2.5
provides a block diagram illustrating how to conne ct the NVSRAM. This
design employs the CP LD to la tch the address instead of using s e parate
address latches.
When using an NVSRAM , pull the MAD[3] Power-O n Sense pin HIGH
during board boot-up. Th is configures the exte rnal memory interface as
an NVSRAM interfac e. During o peration, RA MCE/ selec ts the NVSR AM
when MAD[3] is pulled HI GH.
The nonvolatile external serial EEPROM stores c onfiguration fields for
the LSI53C1030. T he serial EEPROM contains fields f or the S ubsystem
ID(s), Subsystem Vendor ID(s), and the size o f the PCI Diagnostic
Memory Space. The LSI53C1030 must establis h each of these
parameters prior to rea ding system BIOS and l oading the PCI
Configuration Space registers. The power-on option settings enabl e the
download of PCI configur ation data from the serial EE PROM. For more
information on the setti ng of the power-on opt ions, refer to Se ction 3. 10,
“Power-On Sense Pi ns Description.”
CPLD
CY37032
MAS[1:0]
MAD[7:0]
MAD[14:0]
A[14:0]
D[7:0]
CE/
OE/
WE/
3.3 V
NVSRAM (32 K x 8)
A 2-wire serial inte rface provid es the connecti on to the seri al EEPROM.
During initializat ion, the firmware checks i f a serial EEPROM exis ts.
Firmware uses the ch ecksum byte to determine if the configur ation held
in the serial EEPRO M is vali d. If the c heck sum f ails the firmwa re ch ecks
for a valid NVData signa ture. If a valid NVData signatu re is found the
firmware individu ally checksums each per sistent configuration pa ge to
find the invalid pa ge or pages. Table 2.5 provides the structure of the
configuration re cord in the serial EEPROM.
Table 2.5PCI Configuration Record in Serial EEPROM
EEPROM AddressConfiguration Data
0x00PCI Function [0] Subsystem ID, bits [7:0]
0x01PCI Function [0] Subsystem ID, bits [15:8]
0x02PCI Function [0] Subsystem Vendor ID, bits [7:0]
0x03PCI Function [0] Subsystem Vendor ID, bits [15:8]
0x04PCI Diagnostic Memory Size
0x05Reserved
0x06PCI Function [1] Subsystem ID, bits [7:0]
0x07PCI Function [1] Subsystem ID, bits [15:8]
0x08PCI Function [1] Subsystem Vendor ID, bits [7:0]
0x09PCI Function [1] Subsystem Vendor ID, bits [15:8]
0x0AChecksum
2.7 Zero Channel RAID
Zero channel RAID (ZCR) ca pabilities enable the LS I53C1030 to
respond to acces s es from a P C I RAID c ont ro ller c ard or c hi p that i s able
to generate ZCR cycles . The LSI53C1030’s ZCR functiona lity is
controlled through the ZCR_EN/ and the IOPD_ GNT/ signals. Both of
these signals ha ve internal pull-ups and are active LOW.
The ZCR_EN/ signal enables ZCR s upport on the LSI53C1030. Pulli ng
ZCR_EN/ HIGH disables ZCR s upport on the LSI53C1030 an d causes
the LSI53C1030 to b ehave as a normal PCI-X to Ultra3 20 SCSI
controller. When ZCR is disabled, the I OPD_GNT/ signal has no e ffect
on the LSI53C1030 operation.
Pulling ZCR_EN/ LOW enables ZCR operation. Wh en ZCR is enabled,
the LSI53C1030 respond s to PCI configuratio n cycles when the
IOPD_GNT/ and IDSEL si gnal are asserted. Conn ect the IOPD_GNT/
pin on the LSI53C1030 to the PCI GNT/ signal of the e xternal I/O
processor. This allows the I/O process or to perform PCI configur ation
cycles to the LSI53C1030 when the I/O processor is granted the PCI
bus. This configurati on also prevents the s ystem processor from
accessing the LSI53 C1030 PCI configura tion registers.
LSI53C1030 based designs do not use the M6 6EN pin to determine the
PCI bus speed.
Figure 2.6 illustra tes how to connect the LSI53C 1030 to enable ZCR.
This figure also con tains information for c onnecting the LSI53C101 0R
based designs to a ZCR design and migrating from LSI53C1010R based
designs to LSI53C1030 based designs. Notice that the LSI53C1030 does
not require the 2:1 mux.
Figure 2.6ZCR Cir cuit Diagram for LSI53C1030 and LSI53C1010R
ZCR PCI
Slot
Int A/ (A6)
Int B/ (B7)
Int C/ (A7)
Int D/ (B8)
Vdd
Vdd
Vdd
Vdd
0.1 k
Vdd
Ω
0.1 k
Ω
4.7 k
Ω
4.7 k
Ω
4.7 k
Ω
TDI (A4)
GNT/ (A17)
TMS (A3)
IDSEL (A26)
AD21 (B29)
Host System
Int A/
Int B/
Int C/
Int D/
AD21
AD19
Note: To maintain proper interrupt mappin g, select the addres s line for use as IDSEL on the
LSI53C1010R/LSI5 3C1030 to be +2 add ress lines above IDS EL on ZCR slot.
This section describe s the LSI Logic requi rements for the M ulti-ICE test
interface. LSI Logic recommends that all tes t signals be routed to a
header on the board.
The Multi-ICE test inte rface header is a 20-pin head er for Multi-ICE
debugging through t he ICE JTAG port. This header is essential for
debugging both the fi rmware and the design func tionality and must be
included in boa rd design s. The conne ctor is a 20-pin h eader that mates
with the IDC sockets mo unted on a ribbon cable. Table 2.6 details the
pinout of the 20 pin heade r.
This chapter descri bes the input and o utput signals of the LSI53C1030.
The chapter consists of the following sections:
•Section 3.1, “Signal Organization”
•Section 3.2, “PCI Bus Interface Signals”
•Section 3.3, “PCI-Rel ated Signals”
•Section 3.4, “SCSI Int erface Signals”
•Section 3.5, “Mem ory Interface”
•Section 3.6, “Zero Cha nnel RAID Interface”
•Section 3.7, “Test Interface”
•Section 3.8, “GPIO and LED Signals”
•Section 3.9, “Power and Ground Pins”
•Section 3.10, “Pow er-On Sense Pins Descr iption”
•Section 3.11, “Internal Pull-ups and Pull-downs”
A slash (/) at the end of a signal i ndicates that th e signal is activ e LOW.
When the slash is ab sent, the signal is acti ve HIGH. NC designates a
No Connect signal.
LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller 3-1
There are five si gnal types:
IInput, a standard in put-only signal
OOutput, a standard outp ut driver (typically a Tote m Pole output)
I/OInput and outpu t (bidirectional)
PPower
GGround
Figure 3.1 contains th e functional signal gro upings of the LSI53C1030 .
Figure 5.12 on page 5-22 provides a diag ram of the LSI53C1030
456 Ball Grid Array (BGA). Table 5.20 and Table 5.21 on page 5-24 and
page 5-26 provide pi nout listings for the LSI53 C1030.
This section desc ribes the PCI interface. T he PCI interface con sists of
the System, Address and Data, Interface Contro l, Arbitration, Error
Reporting, and Interr upt signal groups.
3.2.1 PCI System Signals
Table 3.1 describe s the PCI System sign als group.
Table 3.1PCI System Signals
Signal NameBGA PositionTypeStrength Description
CLKAC22IN/ARefer to the PCI Local Bus Specification,
Ver si on 2. 2 , and the PCI-X Addendum to the
PCI Local B us S pe ci fic at i o n, Versio n 1.0 a , f or
this signal description.
RST/AB10IN/ARefer to the PCI Local Bus Specification,
Ver si on 2. 2 , and the PCI-X Addendum to the
PCI Local B us S pe ci fic at i o n, Versio n 1.0 a , fo r
PVT2, PVT1AF4, AE5IN/APVT2 and PVT1 provide biasing for PCI
Active LOW Alternate Interrupt A indicates
that PCI Function [0] is requesting service
from its host device driver. ALT_INTA/ is an
open drain signal. The interrupt request
routing mode bits, bits [9:8] in the PCI Host
Interrupt Mask register, control the routing of
interrupt signals to INTA/ and/or ALT_INTA/.
Active LOW Alternate Interrupt B indicates
that PCI Function [1] is requesting service
from its host device driver. ALT_INTB/ is an
open drain signal. The interrupt request
routing mode bits, bits [9:8] in the PCI Host
Interrupt Mask register, control the routing of
interrupt signals to INTB/ and/or ALT_INTB/.
signals. Connect a 49.9 Ω, 1% resistor
between PVT2 and PVT1.
The SCSI Interfac e signals section describes the signals for the SCSI
Channel [0] and SCSI Ch annel [1] interfaces. Table 3.8 describes the
SCSI bus clock si gnal that is common to b oth SCSI Channel [0] and
SCSI Channel [1].
In the LVD mode, the negative and positiv e signals form the di fferential
pair. In the SE mode, the negative signals represent the signal pin an d
the positive signal s are a virtual groun d. The LSI53C1030 does not
support the HVD mode . If HVD signalling is present , the SCSI channel
3-states its driv ers.
Table 3.8SCSI Bus Clock Signal
Signal NameBGA PositionTypeStrength Description
SCLKF3IN/ASCS I C l oc k provides the 80 MHz reference
clock source f or the ARM966 E-S
processors and all SCSI-related timings.
3.4.1 SCSI Channel [0] Signals
Ta ble 3.9 describes the SCSI Channel [0] Interface sign als.
carries the memory and address signals
for the Flash ROM and NVSRAM
interfaces on MAD[7:0]. These pins also
provide the Power-On Sense options that
configur e operating pa rameters du ring
chip powe r up or res et.
MADP[1:0]C22, B24I/O8 mAThe Memory Address and Data Parity
signals provide parity checking for
MAD[15:0]. By default, the LSI53C1030
uses even parity. The user can enable odd
parity through the Fusion-MPT
architecture. These pins also provide the
Power-On Sense options that configure
operating parameters during chip power
up or reset.
MOE/G26O4 mAThe LSI53C1030 asserts active LOW
Memory Output Enable to indicate that
the selected NVSRAM or Flash ROM
device can drive data. This signal is
typically an asynchronous input to
NVSRAM and/or Flash ROM devices.
BWE[1:0]/E24, H23O8 mAThe LSI53C1030 asserts active LOW
Memory Byte Write Enables to allow
single byte writes to th e NVSR AM. BWE0/
enables writes on MAD[7:0].
RAMCE/D20O8 mAWhen MAD[3] is pulled HIGH, the
LSI53C1030 asserts active LOW
synchronous RAM Chip Enable to select
the NVSRAM.
FLSHCE/G25O8 mAThe LSI53C1030 asserts active LOW
Flash Chip Enable to enable data
transfers with a single 8-bit device.
FLSHALE[1:0]/ J24, K22O8 mAThe Flash ROM and NVSRAM interfaces
use active LOW Flash Address Latch Enable. For the Flash ROM, these si gnals
provide clocks for addres s latc hes. For the
NVSRAM, these signals provide the
memory address strobe.
SCANENN22IN/ASCANEN is for use only by LSI Logic.
SCANMODEE7IN/ASCANMODE is for use on ly by LSI Lo gic.
IDDTNY4IN/AIDDTN is for use only by LSI Logic.
CLKMODE_0AA22IN/ACLKMODE_0 is for use on ly by LSI Lo gic.
CLKMODE_1AC2IN/ACLKMODE_1 is for use on ly by LSI Lo gic.
DIS_PCI_FSN/A24IN/APulling DIS_PCI_FSN/ LOW disa bles the PCI
FSN. Pulling this pin HIGH allows the chip to
enable the PCI FSN when operating in PCI-X
mode, or to disable the PCI FSN when
operating in PCI mode. The LSI53C1030
controls the PCI FSN.
DIS_SCSI_FSN/ AC4IN/ADIS_SCSI_FSN/ is for use only by LSI Logic.
TESTACLKAB6IN/ATESTACLK is for use only by LSI Lo gic.
TESTHCLKAE2IN/ATESTHCLK is for use only by LSI Logic.
TNC5IN/ATN is f or use only by LSI Logi c.
TESTCLKEND7IN/ATESTCLKEN is for use only by LSI Logic.
the PCI bus
drivers/receivers, SCSI bus
drivers/re ceivers, loca l
memory interface
drivers/receivers, and other
I/O pins.
GN/AVSS_IO provides ground for
the PCI bus
drivers/receivers, SCSI bus
drivers/re ceivers, loca l
memory interface
drivers/receivers, and other
I/O pins.
circuit power for the PLL
circuit.
circuit ground for the PLL
circuit.
PN/AVDDC provides po wer for
the core lo gic.
GN/AVSSC provides ground for
the core lo gic.
PCI5VBIASM23, W25, Y22, AB22, AC10, AD9,
AD18, AE6, AF12
NCAC9–N/ANo Connect.
1. To reduce signal noise that can affect FSN functionality, place a ferrite bead in series with the VDDA
and VSSA pins. LSI Logic recommends a bead with a rating of 150 Ω at 100 MHz.
In addition to provid ing the address/data b us for the external memory
interface, MAD[15:0] and MADP[1:0] provide eigh teen Power-On S ense
pins that configure g lobal operating conditions within the LSI53C1030.
The MAD[15:0] and MADP[1:0] pins have internal pull-down current sinks
and sense a logical 0 if no pull-up resist or is present on the pin . To
program a particular option, allow the internal pull-down to pull the pi n
LOW or connect a 4.7 k
to pull the pin HIGH. T he LSI53C1030 samples these pins during PCI
reset and holds th eir values upon the remov al of PCI reset. Table 3.20
provides the MAD Powe r-On Sense pin con figuration o ptions. LSI Logic
expects most config urations to employ the de fault settings. Provide
pull-up options f or all MAD pins.
Table 3.20MAD Power-On Sense Pin Options
MAD Pin FunctionPulled-Down (Default)Pulled-Up
MADP[1]Reserved
Ω resistor between the appr opriate pin an d VDD
MADP[0] PCI-X ModeEnables the PCI-X Mode.Disables the PCI-X Mode.
MAD[15]133 MHz PCI-XEnables 133 MHz PCI-X Mode.Disables 133 MHz PCI-X Mode.
MAD[14]64-bit PCI Configures a 64-bit PCI Bus.Configures a 32-bit PCI Bus.
MAD[13]66 MHz PCI Enables the 66 MHz PCI Mode.Disables the 66 MHz PCI Mode.
MAD[12]Reserved
MAD[11]ID Control [1]Has no effect.Sets bit [15] of the PCI Function [1]
MAD[10]ID Control [0]Has no effect.Sets bit [15] of the PCI Function [0]
MAD[9:8]Reserved
MAD[7]Serial EEPROM
Download
Enable
MAD[6]IOP Boot Enable Enables the IOP boot process.Disables the IOP boot process.
MAD[5:4] PCI/SCSI
Configuration
Enables the download of the PCI
configuration information from
the serial EEPROM.
Configures the LSI53C1030 according to Table 3.21.
Subsystem ID register to 0b1.
Subsystem ID register to 0b1.
Disables the download of the PCI
configuration information from the
serial EEPROM.
MAD[3]NVSRAM Select Has no effect.Configures the LSI53C1030 to
MAD[2:1] Flash ROM Size Configures the Flash ROM size according to Table 3.22.
MAD[0]Reserved
support an NVSRAM.
•MADP[1], Reserved.
•MADP[0], PCI-X Mode – By default, internal logic pulls this pin LOW
to enable the PCI-X m ode on the LSI 53C1 030. Pulling this pin HI GH
disables the PCI-X mode on the LSI53C1030 . Pull this pin HIGH
when the host board does no t support the PCI-X mode . The setting
of this pin must c oincide wi th the settin g of the P CI_CAP pin on the
host board. When the PCI-X mode is disabled, the P CI-X extended
capabilities regi ster structure is not v isible in PCI Configuration
Space.
•MAD[15], 133 MHz PCI-X – By default, i nternal logic pulls th is pin
LOW to enable 133 MHz PCI-X operation and to set th e 133 MHz
Capable bit in the PCI-X Status register. Pulling this pin HIGH
disables 133 MH z PCI-X ope ratio n and clear s the 133 M Hz Capabl e
bit in the PCI-X St atus register.
•MAD[14], 64-bit PCI – By default, internal logic pulls this pin LOW
to enable 64-bit PCI ope ration an d to set the 6 4-bit Enabl e bit in th e
PCI-X Status register. Pulling this pin HIGH configur es the PCI
connection as a 32-b it co nnecti on an d cle ars the 64-b it En able b it in
the PCI-X Status register.
•MAD[13], 66 MHz PCI – By default, internal logic pulls this pin LOW
to enable 66 MHz PCI opera tion on the LSI53C1030 and to set the
66 MHz Capable bit in th e PCI Status register. Pulling this pin HIGH
disables 66 MHz PCI ope ration and clears the 66 MHz Capa ble bit
in the PCI Status re gister.
•MAD[12], Reserved.
•MAD[11], ID Control [1] – By default, internal logic p ulls this pin
LOW. Pulling this signal LOW either allows the serial EEPRO M to
program bit 15 of the PCI F unction [1] Subsystem ID register or
allows this bit to default to 0 b0. Pull ing this p in HIGH sets thi s bit to
0b1.
•MAD[10], ID Control [0] – By default, inte rnal logic pulls this pi n
LOW. Pulling this signal LOW either allows the serial EEPRO M to
program bit 15 of the PCI F unction [0] Subsystem ID register or
allows this bit to default to 0b0. Pull ing this pin HIGH sets this bit to
0b1.
•MAD[9:8], Reserved.
•MAD[7], Serial EEPROM Download Enable – By default, internal
logic pulls this pi n LOW to enab le the do wnload of PCI c onfigu ratio n
information from the se rial EEPROM. Pulling this pin HIGH disables
the download of the PCI configuration information from the serial
EEPROM. Disa bling the download of PCI configuration information
defaults the Subsystem Vendor ID register to 0x1000 and defaults
Subsystem ID register for the respective PCI F unction to either
0x1000 if MAD[11:10] are pulled LOW or to 0x8000 if MAD[11:10] are
pulled HIGH.
•MAD[6], IOP Boot Enable – By default, interna l logic pulls this pin
LOW. In the default mode, the IOP star ts the boot process and
downloads firmware fro m the Flash ROM. Pulling this pin HIGH
causes the IOP to await a firmwar e download from the host system.
•MAD[5:4], PCI Single/Multifunction and SCSI Single/Dual
Channel Configuration – These pins work in conju nctio n with each
other to configure the LSI53C1030 as a single fu nction PCI-X to
single channel S CSI controller or a mu ltifunction PCI-X to dual
channel SCSI cont roller. By default, hardware internally p ulls
MAD[5:4] down to configu re the LSI53C1 030 as mu ltifuncti on PCI-X
to dual channel SCSI cont roller. The user may pull MAD[5:4] HIGH
to configure the LSI53 C1030 as a single func tion PCI-X to single
channel SCSI cont roller. This configur ation enabl es PCI Functio n [0]
and SCSI Channel [0], d isables PCI Function [1] and S CSI
Channel [1], and programs the PCI Function [0] Header Type register
to indicate a single func tion PCI device. L SI Logic does not s upport
multifunction PCI-X to s ingle channel S CSI or single functi on PCI-X
to dual channel SCSI c onfigurations. Table 3.21 provi des the
MAD[5:4] pin encoding d efinitions.
Table 3.21PCI-X Function to SCSI Channel Configurations
MAD[5:4] Options LSI53C1030 Configuration
0b00Multifunction PCI-X to Dual Channel SCSI Controller
0b01Reserved
0b10Reserved
0b11Single Function PCI-X to Single Channel SCSI Controller
•MAD[3], NVSRAM Select – By defaul t, internal logic pulls this pin
LOW, which has no effect on the LSI53C1030. Pulling this pin HIGH
configures the externa l memory interface as an NVSRAM interface.
•MAD[2:1], ROM Size – These pins program the size of the Flash
ROM memory. Refer to Table 3.22 for the pin encoding. By default,
internal logic pull s these pins LOW to indic ate that a Flash ROM is
not present in the sy stem.
Table 3.22Flash ROM Size Programming
MAD[2:1] OptionsFlash ROM Size
0b00Flash ROM not present (Default)
0b01Up to 1024 Kbytes
0b10
Reserved
0b11
1. Choose t his settin g for a 128 Kb yte or 512 K byte Flash R OM.
This chapter describes the PCI host register space. This chapter consists
of the following secti ons:
•Section 4.1, “PCI C onfiguration Space Regis ter Description”
•Section 4.2, “PCI I/O Space and Memory Spac e Register
Description”
The register map at the beginni ng of each register description pr ovides
the default bit settings for the register. Shading indicates a reserved bit
or register. Do not access the res erved address areas.
There are two PCI function s on the LSI5 3C1030. Each P CI funct ion has
its own independent interrupt pin and its own PCI Address space. The
PCI System Address s pace consists of three r egions: Configuration
Space, Memory Spac e, and I/O Space. PCI Con figuration Space
supports the iden tification, configurati on, initialization an d error
management function s for the LSI53C1030 PCI devices.
PCI Memory Space [0] and Memory Space [1] form th e PCI Memory
Space. PCI Memory S pace [0] provides normal s ystem accesses to
memory and PCI Memory Space [1] provides diagnostic memory
accesses. PCI I/O Sp ace provides normal sys tem access to memory.
4.1 PCI Configuration Space Register Description
This section provi des bit level descripti ons of the PCI Configuration
Space registers. Tabl e 4.1 defines the PCI Configuration Space registers.
A separate set of PCI Configu ration Space registers exis ts for each PCI
function.
The LSI53C1030 enable s, orders, and locates the PCI extended
capability regist er structures (Power Ma nagement, Messaged S ignalled
LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller 4-1
Interrupts, and PCI-X) to optimize dev ice perfo rmance. T he LSI53C1 030
does not hard code the loca tio n and order of the PCI ex ten ded capa bi li ty
structures. T he address and location of the PCI extended capa bility
structures are subj ect to change. To access a PCI extend ed capability
structure, follow the po inters held in the Capabil ity Pointer registers a nd
identify the extended c apability structure with the Capability ID regi ster
for the given structur e.
Table 4.1LSI53C1030 P CI Configuration Space Ad dress Map
3116 150 OffsetPage
Device IDVendor ID0x004-3
StatusCommand0x044-3
Class CodeRevision ID0x084-7
ReservedHeader TypeLatency TimerCache Line Size0x0C4-7
This 16-bit registe r identifies the manufactur er of the
device. The Vendor ID is 0x1000.
Register: 0x02–0x03
Device ID
Read Only
150
Device ID
0000000000110000
Device ID [15:0]
This 16-bit registe r identifies the partic ular device. The
default Device ID for th e LSI53C1030 is 0x0030.
Register: 0x04–0x05
Command
Read/Write
159876543210
Command
0000000000000000
The Command register provides coarse control over the PCI function’s
ability to generate a nd respond to PCI cycle s. Writing a zero to this
register logically di sconnects the LSI53C1030 PCI function from the PCI
bus for all access es except configuration accesses.
Setting this bit enabl es the LSI53C1030 to activ ate the
SERR/ driver. Clearing this bit disables the SERR/ dri ver.
Reserved7
This bit is reserved.
Enable Parity Error Response6
Setting this bit enabl es the LSI53C1030 PCI func tion to
detect parity errors on the PCI bus and report thes e
errors to the system. Cle aring this bit causes the
LSI53C1030 PCI function to set the Detected Parity Error
bit, bit 15 in the PCI Status register, but not assert PERR/
when the PCI function detects a parit y error. This bit only
affects parity checking. Th e PCI function always gene rates parity for the PCI bus.
Reserved5
This bit is reserved.
Write and Invalidate Enable 4
Setting this bit enables the PCI func ti on to ge ner at e write
and invalidate commands on the PCI bus when operating
in the conventiona l PCI mode.
Reserved3
This bit is reserved.
Enable Bus Mastering2
Setting this bit allows the PCI function to behave as a PCI
bus master. Clearing this bit disables the PCI function
from generating PCI bu s master accesses.
Enable Memory Sp ace1
This bit controls the ab ility of the PCI func tion to re spond
to Memory Space acces ses. Setting this bit al lows the
LSI53C1030 to resp ond to Memory Space accesse s at
the address range s pecified by the Memory [0] L ow,
Memory [0] High, Me mory [1] Low, Memory [1] High, and
Expansion ROM Base Address registers. Clearing this bit
disables the PCI fu nction’s response to PCI Me mory
Space accesse s.
Enable I/O Space 0
This bit controls the LSI53C1030 PCI function’s response
to I/O Space accesses. S etting this bit enables the PCI
function to respond to I/O Space accesses at the address
range the PCI Configu ration Space I/O Bas e Address
register specifies. C learing this bi t disables the PC I function’s response to I/O Space accesses.
Register: 0x06–0x07
Status
Read/Write
15141312111098765430
Status
0000
Reads to this regist er behave normally. To cl ear a bit location tha t is
currently set, wr ite the bit to on e (1). For exam ple, to clear bit 1 5 when
it is set, without affecting any other bits, write 0x800 0 to the register.
001000110000
Detected Parity Error (from Slave)15
This bit is set per the PCI Lo cal Bus Specifica tion, Revision 2.2, and PCI-X Addendum to the PCI Local B us
Specification, Re vision 1.0a.
Signalled System Er ror14
The LSI53C1030 PCI func tion sets this bit when asser ting the SERR/ signa l.
Received Master Abort (from Master)13
A master device s ets this bit when a Master Ab ort command terminates its transaction (except fo r Special
Cycle).
Received Target Abort (from Master)12
A master device s ets this bit when a Target Abort command terminates its transaction.
Reserved11
This bit is reserved.
DEVSEL/ Timing[10:9]
These two read o nly bits encode the timing of DE VSEL/
and indicate the sl owest time that a devic e asserts
DEVSEL/ for any bu s command except Conf iguration
Read and Configuration Wri te. The LSI53C1030 only
supports medium DEVSEL/ timing. The possi ble timing
values are:
0b00Fast
0b01Medium
0b10Slow
0b11Reserved
Data Parity Error Reported 8
This bit is set per the PCI Lo cal Bus Specifica tion, Revision 2.2, and PCI-X Addendum to the PCI Local B us
Specification, Re vision 1.0a. Refer to b it 0 of the PCI-X
Command register for more information.
Reserved[7:6]
This field is reserved.
66 MHz Capable5
The MAD[13] Power-On Sense pin controls this b it.
Allowing the internal pull-down to pull MAD[13] LOW sets
this bit and indicate s to the host system that the
LSI53C1030 PCI functi on is capable of operati ng at
66 MHz. Pulling MA D[13] HIGH clears this bit a nd indicates to the host syst em that the LSI53C1030 PC I function is not configured to operate at 66 MHz. Refer to
Section 3.10, “Pow er-On Sense Pins Descr iption,” for
more informat ion.
New Capabilities 4
The LSI53C1030 PCI func tion sets this read only b it to
indicate a list o f PCI extended capabiliti es such as PCI
Power Management, MSI, and PCI-X support.
This register indicates the current revision level of the
device.
Register: 0x09–0x0B
Class Code
Read Only
230
Class Code
000000010000000000000000
Class Code [23:0]
This 24-bit registe r identifies the generic fu nction of the
device. The upper byt e of this register is a base c lass
code, the middle byte is a subclass code, and the lower
byte identifies a s pecific r egister- level pro gramming i nterface. The value of this register is 0x010000, which identifies a SCSI contr oller.
Register: 0x0C
Cache Line Size
Read/Write
7320
Cache Line Size
00000
Cache Line Size[7:3]
This register specif ies the sys tem cac he line size in uni ts
of 32-bit words. In the conventional PCI mode, the
LSI53C1030 PCI functi on uses thi s register to determin e
whether to use Write and Invalidate or Write comman ds
for performing write cy cles. Programming this register to
a number other than a nonzero power of two disables the
the use of the PCI perfor mance commands to exec ute
data transfers. The P CI function ignores thi s register
when operating in the P CI-X mode.
Reserved[2:0]
This field is reserved.
Register: 0x0D
Latency Timer
Read/Write
7430
Latency Timer
0X00
Latency Timer [7:4]
The Latency Timer register spe cifies, in units of PCI bus
clocks, the value of th e Latency Timer for this PCI bus
master. If the LSI53C1030 initializes in the PCI mode, the
default value of this reg ister is 0x00. If the LSI 53C1030
initializes in the PCI-X mod e, t he default value of this register is 0x40.
0000
Reserved[3:0]
This field is reserved.
Register: 0x0E
Header Type
Read Only
70
X0000000
Header Type [7:0]
This 8-bit register i dentifies the layout of by tes 0x10
through 0x3F in config uration spac e and also indi cates if
the device is a single function or multifunction PCI device.
If the LSI53C1030 is con figured as a multifuncti on PCI
device, bit 7 is set. I f the LSI53C1030 is configur ed as a
single function PC I device, bit 7 is cleare d.
The I/O Base Addre ss register maps the opera ting register set in to I/O
Space. The LSI53C1030 requires 256 bytes of I/O Space for this base
address register. Hardware sets bit 0 to 0b1. Bit 1 is reserved and returns
0b0 on all reads.
The Memory [0] Low register and the Memory [0] High register map SCSI
operating registers into Memory Space [0 ]. This register contains t he
lower 32 bits of the Me mory Space [0] base addr ess. Hardware
programs bits [9:0] to 0b 0000000100, which indica tes that the Memory
Space [0] base add ress is 64 bits wide and that the memo ry data is no t
prefetchable. The LS I53C1030 requires 1024 b ytes of memory space.
Memory [0] Low [31:0]
This field contains t he Memory [0] Low address .
Register: 0x18–0x1B
Memory [0] High
Read/Write
310
Memory [0] High
00000000000000000000000000000000
The Memory [0] High register and the Memory [0] Low register map SC SI
operating registers into Memory Space [0 ]. This register contains t he
upper 32 bits of the Memory Spac e [0] base address. The LSI53C10 30
requires 1024 bytes o f memory space.
The Me mory [1] L ow register and th e Memory [1] High register map the
RAM into Memory Spac e [1]. This regist er contains the lower 32 bits of
the Memory Space [1] b ase address. Hardware progr ams bits [12:0] to
0b0000000000100, which indicates that the Memo ry Space [1] base
address is 64 bits wid e and that the memory data i s not prefetchable.
The LSI53C1030 require s 64 Kbytes of memory for Memory Space [1].
Memory [1] Low [31:0]
This field contains t he Memory [1] Low address .
Register: 0x20–0x23
Memory [1] High
Read/Write
310
Memory [1] High
00000000000000000000000000000000
The Me mory [1] High register and the Memory [1] Low registe r map the
RAM into Memory Space [1]. This register conta ins the upper 32 bits of
the Memory Space [1] b ase address. The LSI53C10 30 requires
64 Kbytes of memory for Memory Space [1].
This 16-bit regi ster uniquely identifie s the vendor that
manufactures the add- in board or subsystem wher e the
LSI53C1030 resides. This register provides a mechanism
for an add-in card vendor to distingui sh their cards from
another vendor ’s cards, even if the car ds use the same
PCI controller (and have the same Vendor ID and
Device ID).
The external se rial E EPRO M ca n hol d a v endor -speci fic,
16-bit value for thi s register, which the board designer
must obtain from th e PCI Special Interest G roup
(PCI-SIG). By default, a n internal pull-down on t he
MAD[7] Power-On Sen se pin enables the serial
EEPROM interface so that the LSI53C1030 can loa d this
register from the serial E EPROM at power-up. If the
download from the EEPROM fai ls, this register contains
0x0000.
If the board designer disabl es the EEPROM in terface by
pulling the MAD[7] P ower-On Sense pin HIGH, th is register returns a valu e of 0x1000. Refer to S ection 3.10,
“Power-On Sense Pins Desc ription ,” page 3-21, for more
information.
Register: 0x2E–0x2F
Subsystem ID
Read Only
150
Subsystem ID
xxxxxxxxxxxxxxxx
Subsystem ID [15:0]
This 16-bit register uniquely identifies the add-in board or
subsystem where thi s PCI device resides. Thi s register
provides a mechani sm for an add-in ca rd vendor to distinguish their cards fr om one another even if the c ards
use the same PCI cont roller (and h ave the s ame Vendor
ID and Device ID). The board designer can st ore a vendor specific, 16 -bit value in an ext ernal serial EEPR OM.
The ID Control Powe r-On Sense pins (MAD[11] for PCI
Function [1]; MAD[10] for PCI Function [0]) and the serial
EEPROM enable Pow er-On Sense pin (MAD[7] ) control
the value of this r egister. These pins have internal pull
downs. Allowing MAD [7] to r em ai n inte rn all y pu lle d d own
enables the serial EEPROM interface and p ermits the
LSI53C1030 to load this register from the serial EEPROM
at power up. Pulling M AD[7] HIGH disables the se rial
EEPROM interface. Allowing the ID Control pins to
remain internally pul led LOW has no effect on this register. Pulling the ID Control pins HIGH sets bit [15 ] of this
register for the gi ven PCI f unction. Pulling the ID Con trol
pins HIGH takes precedenc e over all other settings for
bit [15].
Table 4.2 lists the c onfi gu ration options for the Power -On
Sense pins and s ettings for this register. If the serial
EEPROM interface i s disabled and the ID Contr ol pins
are internally pulled LOW, this register contai ns 0x1000.
If the serial EEPROM i nterface is disabled and th e ID
Control pins are pulled HIGH, this register contains
0x8000. If a downlo ad fro m the se rial EE PR OM fails and
the ID Control pins are internally pulled LOW , this register
contains 0x0000. If a downlo ad from the ser ial EEPROM
fails and the ID Control pins are pulled HIGH, this register
contains 0x8000. Refer to Section 3.10, “Power-On
Sense Pins Descript ion,”, for additional in formation.
Table 4.2Subsystem ID Register Download Conditions and Values
MAD[7] StateMAD[11] or MAD[10] LOWMAD[11] or MAD[10] HIGH
MAD[7] LOW
MAD[7] HIGH
1. The Subsystem ID register returns 0x0000 if the serial EEPROM download fails.
2. The Subsystem ID register returns 0x8000 if the serial EEPROM download fails.
Subsystem ID = 0xXXXX
Bits [15:0] are downlo aded.
Subsystem ID register = 0x1000.Subsystem ID = 0x8000.
1
(Default)
Subsystem ID = 0b1XXXXXXXXXXXXXXX
Bits [14:0] are downloaded with Bit [15] set.
Register: 0x30–0x33
Expansion ROM Base Address
Read/Write
3111 101 0
Expansion ROM Base Address
000000000000000000000
This four-byte register contains the base address and size information for
the expansion ROM.
Expansion ROM Base Address[31:11]
These bits correspond to the upper 21 bits of the expansion ROM base add ress. The host system d etects the
size of the external memory by first writing 0xFFFFFFFF
to this register and the n reading the registe r back. The
LSI53C1030 responds with zeros in all don ’t care locations. The least significant one (1) that remains represents the binary versio n of the exter n al me mor y size . Fo r
example, to indicate an external memory size of 3 2
Kbytes, this regist er returns ones in the up per 17 bits
when written with 0xFFFFFFFF and read back.
Reserved[10:1]
This field is reserved.
Expansion ROM Enable0
This bit controls if the device accepts accesses to its
expansion ROM. Setting this bit enables address d ecoding. Depending on the system configuration, the device
can optionally use a n expansion ROM. Note that to
access the e xpansion ROM , the user must also set bit 1
in the PCI Command r egister.
Register: 0x34
Capabilities Pointer
Read Only
70
Capabilities Pointer
XXXXXXXX
Capabilities Pointer[7:0]
This register indica tes the location of the fir st extended
capabilities regi ster in PCI Configuratio n Space. The
value of this register var ies according to system confi guration.
This register communic ates interrupt li ne routing information. Power-On-Self-Test (POST) software writes the routing information i nto this register as it configures the
system. This regist er indicates the sys tem interrupt controller input to which this PCI func tion’s interrupt pin connects. System architectu re determines the value s in this
register.
Register: 0x3D
Interrupt Pin
Read Only
70
00000001
00000010
Interrupt Pin[7:0]
The encoding of this read only r egister i s unique to each
function on the LSI53C10 30. It indicates which int errupt
pin the function uses. The value for Function [0] is 0x01,