LSI LS7535-S, LS7535, LS7534, LS7534-S Datasheet

DIMMER LIGHT SWITCH

WITH UP AND DOWN CONTROLS

FEATURES:

• Phase-lock loop synchronization allows use as a
Wall Switch

• Brightness control of incandescent lamps with touch
plates (LS7534) or mechanical switches (LS7535)

• Dual Controls eliminate confusion

• Soft turn-on /turn-off

• Controls the "Duty Cycle" from 23% to 88%

(conduction angles for AC half-cycles between 41°
and 159°, respectively)

• Operates at 50Hz/60Hz line frequency

• Input for slow dimming

• +12V to +18V DC supply voltage (VSS - VDD)

• LS7534/LS7535 (DIP);

LS7534-S/LS7535-S SOIC - See Figure 1

DESCRIPTION:

LS7534/LS7535 are monolithic, MOS integrated cir­cuits that are designed for brightness control of in­candescent lamps. The outputs of these ICs control
the brightness of a lamp by controlling the firing an­gle of a triac connected in series with the lamp. All
internal timings are synchronized with the line fre­quency by means of a built-in phase-lock loop cir­cuit. The output occurs once every half-cycle of the
line frequency. Within the half-cycle, the output can
be positioned anywhere between 159° conduction
angle for maximum brightness and 41° conduction
angle for minimum brightness in relation to the AC
line frequency. The positioning of the output is con­trolled by applying the proper logic levels at the UP
and DOWN inputs.

These functions may be implemented with very few
interface components which is described in the ap­plication examples (See Fig. 5A and 5B). For touch
plates, LS7534 is used (Fig. 5A). For mechanical
switches, LS7535 is used (Fig. 5B).

In the following Operating Description of the applica­tion examples, an Activation is Touch for LS7534
and Switch Closure for LS7535.

Short Activation (34ms to 325ms)
UP - When the lamp is off, if a short activation is applied to

the UP input, the lamp brightness is ramped up to full-on or
to a previous brightness stored in the memory. The ramp­up time from off to full-on is 2.8 sec. The ramp-up time from

off to any other brightness is proportionally shorter. When
the lamp is on at any brightness, a short activation applied
to the UP input has no effect.
DOWN - If a short activation is applied to the DOWN input,
the lamp brightness is ramped down to off. The ramp-down
time from full-on to off is 5.6 seconds. The ramp-down time
from any other brightness is proportionally shorter. When
the lamp is off, a short activation applied to the DOWN input
has no effect.

Long Activation (Greater than 334ms)
UP - If a long activation is applied to the UP input, the lamp

brightness ramps up from the pre-activation brightness as
long as the activation is maintained or until the full bright­ness is reached. At full brightness any continued long ac­tivation has no further effect.
DOWN - If a long activation is applied to the DOWN input,
the lamp brightness is ramped down as long as the long ac­tivation is maintained or until the minimum brightness is
reached. At minimum brightness, any continued long ac­tivation has no further effect. When the lamp is off, a long
activation applied to the DOWN input has no effect.

CONNECTION DIAGRAM - TOP VIEW

LSI

1

2

3

4

8

7

6

5

LS7534

FIGURE 1

TRIG

VDD(-V )

DOWN

UP

VSS (+V)

DOZE

CAP

SYNC

August 1996

7534/35-080796-1

LSI/CSI

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 [phone] FAX [phone]

U

L

®

A3800

LS7534
LS7535

UP/DOWN SIGNAL DURATION

SHORT LONG

INPUT 34ms to 325 ms More than 334ms

UP

DOWN

PRE-ACTIVATION

BRIGHTNESS

Off

Max.

Intermediate

Off

Max.

Intermediate

POST-ACTIVATION

BRIGHTNESS

Memory **

(See Note 1)

No Change
No Change

No Change

Off *
Off *

PRE-ACTIVATION

BRIGHTNESS

Off

Max.

Intermediate

Off

Max.

Intermediate

POST-ACTIVATION

BRIGHTNESS

Increases from Min.

No change

Increases from pre-

touch brightness

No change

Decreases from Max.

Decreases from pre-

touch brightness

* 5.6 second ramp-down from max. to off. Ramp-down time from any other brightness is proportionally shorter.

** 2.8 second ramp-up from off to max.
NOTE 1: "Memory" refers to the brightness stored in the memory. The brightness is stored in memory when the
lamp is turned off by a short activation. First time after power-up, a short activation produces max. brightness.

INPUT/OUTPUT DESCRIPTION:

VSS (Pin 1)

Supply voltage positive terminal.

DOZE (Pin 2)

A clock applied to this input causes the brightness to de­crease in equal increments with each negative transition
of the clock. Eventually, when the lamp becomes off, this
input has no further effect. The lamp can be turned on
again by activating the UP input. For the transition from
maximum brightness to off, a total of 83 clock pulses are
needed at the DOZE input.
When either the UP or the DOWN input is active, the
DOZE input is disabled.

CAP (Pin 3)

The CAP input is for external component connection for
the PLL filter capacitor. A capacitor of 0.047µF ± 20%
should be used at this input.

SYNC (Pin 4).

The AC line frequency (50Hz/60Hz), when applied to this
input, synchronizes all internal timings through a phase
lock loop. The signal for this input may be obtained from
the line voltage by employing the circuit arrangement
shown in the application examples.

UP (Pin 5).

This input controls the turn-on and the conduction angle, ø ,
of the TRIG output. A description of this is provided in the
DESCRIPTION and TABLE 1. For LS7534, a logic low level
is the active level whereas for LS7535 a logic high level is
the active level. LS7535 has an internal pull-down resistor
of about 500K Ohms on this input.

DOWN (Pin 6).

This input controls the turn-off and the conduction angle, ø,
of the TRIG output. A description of this is provided in the
DESCRIPTION and TABLE 1. For LS7534, a logic low level
is the active level, whereas for LS7535 a logic high level is
the active level. LS7535 has an internal pull-down resistor
of about 500K Ohms on this input.

VDD (Pin 7).

Supply voltage negative terminal.
TRIG (Pin 8).

The TRIG output provides a low level pulse occurring every
half-cycle of the SYNC signal. The conduction angle, ø, of

the TRIG output can be varied within the range of 41o to
159o by means of either the UP or the DOWN input.

TABLE 1

7534/35-080796-2

ABSOLUTE MAXIMUM RATINGS:

PARAMETER SYMBOL VALUE UNIT

DC supply voltage VSS - VDD +20 V
Any input voltage VIN VSS - 20 toVSS + 0.5 V
Operating temperature TA 0 to +80 °C
Storage temperature TSTG -65 to +150 °C

DC ELECTRICAL CHARACTERISTICS:

(TA = 25°C, all voltages referenced to VDD)

PARAMETER SYMBOL MIN TYP MAX UNIT CONDITIONS

Supply voltage VSS +12 - +18 V ­Supply current ISS - 1.2 1.7 mA VSS = +15V,

Output off

Input Voltages:

DOZE LO VIZL 0 - VSS - 6 V -

DOZE HI VIZH VSS - 2 - VSS V ­SYNC LO VIRL 0 - VSS - 9.5 V ­SYNC HI VIRH VSS - 5.5 - VSS V ­UP, DOWN LO VIOL 0 - VSS - 8 V ­UP, DOWN HI VIOH VSS - 2 - VSS V -

Input Current:

SYNC, UP, DOWN HI IIH - - 110 uA With Series 1.5MΩ

Resistor to

115 VAC Line
SYNC, UP, DOWN LO IIL - - 100 nA ­DOZE HI IIH - - 100 nA -

DOZE LO IIL - - 100 nA -

TRIG HI VOH - VSS - V ­TRIG LO VOL - VSS - 8 - V VSS = +15V
TRIG Sink Current IOS 50 - - mA VSS = +15V,

VOL = VSS - 4V

TRANSIENT CHARACTERISTICS (See Fig. 2 and 3)
(All timings are based on fs = 60Hz, unless otherwise specified.)

PARAMETER SYMBOL MIN TYP MAX UNIT

SYNC frequency fs 40 - 70 Hz
UP, DOWN duration (SHORT) Ts1 34 - 325 ms
UP, DOWN duration (LONG) Ts2 334 - infinite ms

ø ramp time, off to max TUS - 2.8 - sec
(UP,SHORT)
ø ramp time, min to max TUL - 3.6 - sec
(UP,LONG)
ø ramp time, max to min TDS - 5.6 - sec
(DOWN,SHORT)
ø ramp time, max to min TDL - 3.6 - sec
(DOWN,LONG)
TRIG pulse width TW - 33 - µs
TRIG conduction angle (See Note) ø 41 - 159 degrees
DOZE frequency fD 0 - 500 Hz

NOTE: The phase delay caused by the typical RC network used between SYNC input and the AC line (See Fig. 5A and
Fig. 5B) reduces the effective ø values by 8°.

7534/35-080796-3

FIGURE 3. OUTPUT CONDUCTION ANGLE, ø, vs UP/DOWN INPUTS

Note 1. UP/DOWN input polarity shown is for LS7534. For LS7535, the polarity is reversed.
Note 2. Points A, D, E and K correspond to minimum brightness, where ø = 41°.

Points B, C, G and H correspond to maximum brightness, where ø = 159°.
Points denoted by M correspond to an arbitrary intermediate brightness.
Note 3. Points F, J and L correspond to ø = 64°. The ramp-up or ramp-down rate of ø changes at these points
(upon long activation only) indicated by the discontinuity of the slopes. The interval E to F or J to K,
in terms of time and angle, are 934ms and 23°, respectively.

OUT

ø

SYNC

TW TW

200
150

100

50

0

DOWN

UP

(Degrees)

0 4 8 12 16 0 4 8 12 0 4 8 12 16 20 24

A

B

C

D

E

F

H

K

G

J

M
L

M

TDL

334ms

334ms

TS2

TS2

TS1

TS2

TS1

TS1

TS1

TUS

TDS

TUL

334ms

ø

SECONDS

FIGURE 2. OUTPUT CONDUCTION ANGLE, ø

7534/35-080596-4

TRIG

OUTPUT
DRIVER

DIGITAL
COM­PARATOR

BRIGHTNESS
MEMORY

Ø

POINTER

PHASE
LOCK
LOOP

CONTROL
LOGIC

BUF

BUF

BUF

BUF

SYNC

CAP

DOZE

DOWN

UP

(+V)

(-V)

FIGURE 4

LS7534/LS7535 BLOCK DIAGRAM

4

3

2

6

5

1

7

8

VSS

VDD

APPLICATION EXAMPLES:

Typical dimmer light switch circuit schematics are shown in Fig. 5A (LS7534) and
Fig. 5B (LS7535). The brightness of the lamp is set by touching the UP and DOWN
touch plates in Fig. 5A and closure of the UP and DOWN switches in Fig. 5B. The
functions of different components are as follows:

• Z, D1, R1, C2 and C5 produce the 15V DC supply for the chip.

• R2 and C4 filter and current limit the AC signal for the SYNC input.

• C3 is the filter capacitor for the internal PLL.

• C1 and L are RFI filters.

• In Fig. 5A, R3 and R4 set the touch sensitivity of the UP and DOWN inputs.

• In Fig. 5B, R3 limits the current between Vss and the UP and DOWN inputs upon
closure of a switch.

• The resistor and diode connected between the chip output and the triac gate
provides current limiting and isolation for the chip. The resistor is R5 in Fig. 5A
and R4 in Fig. 5B.

• In Fig. 5B, PCB layout may cause triac switching transients to be coupled to the UP
or Down input which can have the effect of having a Long switch closure “lock-up”
at a certain phase angle output. In this case, capacitors C6 and C7 must be added
as shown.

The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.

7534/35-080796-5

P

115VAC

OR

220VAC

N

LOAD

C1

T

L

C2

R1

R2

A

B

R5

R3

C5

D1

1

2 3

4

8 7

6

5

R3

C3

C4

TRIG VDD DOWN UP

VSS DOZE CAP SYNC

+

SEE NOTE 2

LS7534

DOZE
CIRCUIT
FIG. 6A

VSS

DZ

UP

VDD

R4

R4

R4 R4

DOWN
TOUCH
PLATE

UP
TOUCH
PLATE

DOWN

SEE NOTE 1

FIGURE 5A. TYPICAL LS7534 DIMMER LIGHT SWITCH

G

MT2

MT1

Z

D2

-

115VAC

C1 = 0.15µF, 200V R4 = 2.7MΩ, 1/4W

C2 = See C2 Value Table R5 = See R5 Value Table
C3 = 0.047µF, 25V D1, D2 = IN4148
C4 = 470pF, 25V Z = 15V, 1W (Zener)
C5 = 47µF, 25V T = Q4004L4 Triac (Typical)
R1 = 270Ω, 1W L = 100µH (RFI Filter)
R2 = 1.5MΩ, 1/4W
R3 = 1MΩ to 5MΩ, 1/4W (Select for sensitivity)

(1) For Connection A. Use 1/4 W for Connection B.
C2 VALUE TABLE R5 VALUE TABLE

C2 = 0.33µF, 200V, Connection A R5 = 100Ω, 1/4W, 25mA Triac Gate

7534/35-041597-6

NOTES: 1) When DOZE circuit is used, break Pin 1 to Pin 2 connection.

2) Use Connection A when Neutral is not available. Use Connection B when Neutral is available.

(1)

220VAC

C1 = 0.15µF, 400V R4 = 4.7MΩ, 1/4W

C2 = See C2 Value Table R5 = See R5 Value Table
C3 = 0.047µF, 25V D1 , D2 = IN4148
C4 = 470pF, 25V Z = 15V, 1W (Zener)
C5 = 47µF, 25V T = Q5004L4 Triac (Typical)
R1 = 1kΩ, 2W L = 200µH (RFI Filter)
R2 = 1.5MΩ, 1/4W
R3 = 1MΩ to 5MΩ, 1/4W (Select for sensitivity)

(2) For Connection A. Use 1/4W for Connection B.
C2 VALUE TABLE R5 VALUE TABLE

C2 = 0.22µF, 400V, Connection A R5 = 100Ω, 1/4W, 25mA Triac Gate
C2 = 0.10µF, 400V, Connection B R5 = 50Ω, 1/4W, 50mA Triac Gate

(2)

115VAC

C1 = 0.15µF, 200V R2 = 1.5MΩ, 1/4W

C2 = See C2 Value Table R3 = 27kΩ, 1/4W
C3 = 0.047µF, 25V R4 = See R4 Value Table
C4 = 470pF, 25V D1, D2 = IN4148
C5 = 47µF, 25V Z = 15V, 1W (Zener)
C6,C7 = 0.001µF, 25V T = Q4004L4 Triac (Typical)
R1 = 270Ω, 1W L = 100µH (RFI Filter)

(1) For Connection A. Use 1/4W for Connection B.

C2 VALUE TABLE R4 VALUE TABLE

C2 = 0.33µF, 200V, Connection A R4 = 100Ω, 1/4W, 25mA Triac Gate
C2 = 0.22µF, 200V, Connection B R4 = 50Ω, 1/4W, 50mA Triac Gate

P

115VAC

OR

220VAC

N

LOAD

C1

MT1

L

Z

C2

R1

R2

A

B

R4

C5

D1

1 2 3 4

8 7 6 5

C3 C4

TRIG V DD DOWN UP

VSS DOZE CAP SYNC

+

SEE NOTE 2

LS7535

DOZE
CIRCUIT
FIG. 6B

VSS

DZ

UP

VDD

DOWN

SEE NOTE 1

FIGURE 5B. TYPICAL LS7535 DIMMER LIGHT SWITCH

G

UP

R3

T

MT2

DOWN

D2

-

SEE NOTE 3

C6

C7.

NOTES: 1) When DOZE circuit is used, break Pin 1 to Pin 2 connection.

2) Use Connection A when Neutral is not available. Use Connection B when Neutral is available .

3) C6 and C7 may be required in some PCB layouts to eliminate coupling from triac circuitry.

(1)

(2)

220VAC

C1 = 0.15µF, 400V R2 = 1.5MΩ, 1/4W

C2 = See C2 Value Table R3 = 27kΩ, 1/4W
C3 = 0.047µF, 25V R4 = See R4 Value Table
C4 = 470pF, 25V D1,D2 = IN4148
C5 = 47µF, 25V Z = 15V, 1W (Zener)
C6,C7 = 0.001µF, 25V T = Q5004L4 Triac (Typical)

R1 = 1kΩ, 2W L = 200µH (RFI Filter)

(2) For Connection A. Use 1/4 W for Connection B.

C2 VALUE TABLE R4 VALUE TABLE

C2 = 0.22µF, 400V, Connection A R4 = 100Ω, 1/4W, 25mA Triac Gate
C2 = 0.10µF, 400V, Connection B R4 = 50Ω, 1/4W, 50mA Triac Gate

7534/35-041597-7

VSS

UP
DN

DZ

VDD

FIGURE 6A. DOZE CIRCUIT FOR LS7534

Sense

DOZE
SWITCH

4093

4093

4093

10µF

330K

4093

MP58098

+

-

3.3M

330K

3.3M

NOTE: All Resistors 1/4W, all Capacitors 25V

VSS

VDD

DOZE
SWITCH

4093

4093

FIGURE 6B. DOZE CIRCUIT FOR LS7535

4093

4093

+

-

DZ

Sense

3.3M

UP

DN

IN914

IN914

3.3M

3.3M

10µF

NOTE: All Resistors 1/4 W, all Capacitors 25V.

DOZE CIRCUIT: (Figures 6A and 6B)

The Doze circuits shown generate a slow clock (0.04Hz) at
the DZ terminal. If the UP/DOWN inputs (Figures 5A and
5B) are not activated, the Sense node of the Doze circuit
sits at a logic high level. A momentary pressing of the
Doze switch sets the SR flip-flop, enabling the oscillator.
Every negative transition of the clock (DZ terminal) causes
the lamp brightness to be reduced by equal increments, un­til eventurally the lamp is shut- off.

When the lamp is off, the oscillator has no further effect on
the dimmer circuit. When the lamp is turned on again by
activating the UP input, the SR flip-flop is reset and the DZ
clock is turned off.

When the Doze circuit is used, the connection between
DOZE input (Pin 2) and Vss (Pin 1), as shown in Figures
5A and 5B, should be removed.

FIGURE 7. OPERATING DESCRIPTION OF A FULL-FEATURE LS7535 WALL SWITCH

See Application Note
AN 705 for the Schematic

DUAL CONTROL CONTINUOUS

DIMMER WITH UNIQUE
DELAYED OFF FEATURE

INITIAL CONDITION ACTION RESULT

Off SHORT PRESS On “Softly” turns On to memory intensity (1)
Off LONG PRESS On Varies from min. intensity towards max. intensity (2)
On LONG PRESS On Varies towards max. intensity (2)
On LONG PRESS Off Varies towards min. intensity (3)

On SHORT PRESS Off “Softly” turns Off

On PRESS Auto-Dim Begins auto-dimming to off (4)
Auto-Dimming SHORT PRESS On “Softly” returns to memory intensity (5)
Auto-Dimming LONG PRESS On Varies towards max. intensity (2)
Auto-Dimming SHORT PRESS Off “Softly “ turns off
Auto-Dimming LONG PRESS Off Varies towards min. intensity (3)
Auto-Dimming PRESS Auto-Dim No change
Auto-Dimming None Auto-dims to Off

(1) Last intensity achieved before turn off is stored as memory intensty.
(2) On (Dim Up) varies intensity towards maximum and stops there.
(3) Off (Dim Down) varies intensity towards minimum and stops there.
(4) Auto-dimming period controlled by RC components and intensity level when Auto-Dim is activated.
(5) Last intensity achieved before Auto-Dim started is stored as memory intensity.

7534/35-080796-8

ON

DIM UP

OFF

DIM DOWN

AUTO DIM