LSI LS7362-TS, LS7362-S, LS7362 Datasheet

BRUSHLESS DC MOTOR COMMUTATOR/CONTROLLER

FEATURES:

• Speed Control by Pulse Width Modulation (PWM)
of low-side drivers only.

• Open or closed loop motor speed control.

• +5 to +28 Volt operation (Vss - VDD).

• Externally selectable input to output code for 60°,
120°, 240°, or 300° electrical sensor spacing.

• Three or four phase operation.

• Analog Speed control.

• Forward/Reverse control.

• Output Enable control.

• Positive Static Braking.

• Overcurrent Sensing.

• Six outputs drive switching bridge directly.

DESCRIPTION:

The LS7362 is a monolithic, ion implanted MOS circuit de­signed to generate the signals necessary to control a three
phase or four phase brushless DC motor. It is the basic
building block of a brushless DC motor controller. The cir­cuit responds to changes at the SENSE inputs, originating
at the motor position sensors, to provide electronic com­mutation of the motor windings. Pulse width modulation
(PWM) of low-side drivers for motor speed control is ac­complished through either the ENABLE input or through
the V TRIP input (Analog Speed control) in conjunction with
the OSCILLATOR input. Overcurrent circuitry is provided
to protect the windings, associated drivers and power sup­ply. The LS7362 circuitry causes the external output driv­ers to switch off immediately upon sensing the overcurrent
condition, and on again only when the overcurrent condi­tion disappears and the positive edge of either the EN­ABLE input or the sawtooth OSCILLATOR occurs. This lim­its the overcurrent sense cycling to the chopping rate of the
ENABLE input or the sawtooth OSCILLATOR. A positive
braking feature is provided to effect rapid deceleration. The
LS7362 is designed for driving Bipolar and Field Effect
Transistors. Because only low-side drivers are pulse width
modulated, the LS7362 is ideally suited in situations where
the integrated circuit interfaces with level converters to
drive high voltage brushless DC motors. By pulse width
modulating the low-side drivers only, the switch losses in
the level conversion circuitry for the high-side drivers is
minimized. Figure 1 indicates how the level conversion is
accomplished.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

LSI

CS1

OUT 1

OUT 2

OUT 3

OUT 4

COMMON

OUT 5

OUT 6

BRAKE

ENABLE

CS2

FORWARD/REVERSE

VDD (-V)

S3

S2

S1

OSCILLATOR

V TRIP

OVERCURRENT SENSE

VSS (+V)

LS7362

CONNECTION DIAGRAM - TOP VIEW

STANDARD 20 PIN PLASTIC DIP

The COMMON, Pin 5, is tied to the positive supply rail
and LS7362 Outputs 1, 2, and 3 are used to drive level
converters Q101, Q102 and Q103 respectively. Only the
motor top side drivers consisting of Q107, Q108 and
Q109 which are connected to the motor power supply,
VM, will be subject to the high speed switching currents
that flow through the motor. The level converters are
turned on and off at the slower commutation rate.

INPUT/OUTPUT DESCRIPTION:
COMMUTATION SELECTS (Pins 1, 20)

These inputs are used to select the proper sequence of
outputs based on the electrical separation of the motor
position sensors. With both inputs low (logic zero), the
sequence is adjusted for 60° electrical separation, with
CS2 high and CS1 low 120° separation sequence is se­lected, with CS1 high and CS2 low 240° separation se­quence is selected and with CS1 and CS2 high the 300°
separation sequence is selected. Note that in all cases
the external output drivers are disabled for invalid
SENSE input codes. Internal pull down resistors are pro­vided at Pins 1 and 20 causing a logic zero when these
pins are left open.

September 1999

7362-041100-1

LSI/CSI

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 [phone] FAX [phone]

LS7362

• LS7362 (DIP); LS7362-S (SOIC);
LS7362-TS (TSSOP) - See Connection Diagram

U

L

®

A3800

FORWARD/REVERSE (Pin 19)

This pin acts to modify the input to output sequence such
that when brought from high to low or low to high the direc­tion of rotation will reverse. An internal pull up resistor is
provided at Pin 19 causing a logic one when left open.

SENSE INPUTS (Pins 15, 16, 17)

These inputs provide control of the output commutation
sequence as shown in Table III. S1, S2, S3 originate in
the position sensors of the motor and must sequence in
cycle code order. Hall switch "pull-up" resistors are pro­vided at Pins 15, 16 and 17. The positive supply of the
Hall devices should be common to the chip Vss.

BRAKE (Pin 9)

A high level applied to this input unconditionally turns off
outputs 1, 2 and 3 and turns on outputs 4,5 and 6 (See
Figure 1). Transistors Q101, Q102 and Q103 cut off caus­ing Q107, Q108 and Q109 to cut off and transistors Q104,
Q105 and Q106 turn on, shorting the windings together,
The BRAKE has priority over all other inputs. An internal
pull down resistor is provided at Pin 9 causing no braking
when left open. (Center- tapped motor configuration re­quires a power supply disconnect transistor controlled by
the BRAKE signal - See Figure 3.)

ENABLE (Pin 10)

A high level on this input permits the output to sequence
as in Table III, while a low disables all external output driv­ers. An internal "pull up" resistor is provided at Pin 10,
enabling when left open. Positive edges at this input will
reset the overcurrent flip-flop.

OVERCURRENT SENSE (Pin 12)

This input provides the user a way of protecting the motor
winding, drivers and power supply from an overload
condition. The user provides a fractional ohm resistor
between the negative supply and the common emitters of
the NPN drivers. This point is connected to one end of a
potentiometer (e.g. 100K ohms), the other end of which is
connected to the positive supply. The wiper pickoff is
adjusted so that all outputs are disabled for currents great­er than the limit. The action of the input is to disable all
external output drivers. When BRAKE exists, OVER­CURRENT SENSE will be overridden. The overcurrent
circuitry latches the overcurrent condition. The latch may
be reset by the positive edge of either the sawtooth OS­CILLATOR or the ENABLE input. When using the EN­ABLE input as a chopped input, the OSCILLATOR pin
should be held at VSS. When the ENABLE input is held
high, the OSCILLATOR must be used to reset the over­current latch.

V TRIP (Pin 13)

This pin is used in conjunction with the sawtooth oscillator
provided on the circuit. When the voltage level applied to
V TRIP is more negative than the waveform at the OS­CILLATOR pin, the low-side drivers will be enabled. When
V TRIP is more positive than the sawtooth OSCILLATOR
waveform the low-side drivers are disabled.

The sawtooth waveform at the OSCILLATOR pin typically var­ies from .4 Vss to Vss-2 Volts (assuming VDD is at ground po­tential). The purpose of the V TRIP input in conjunction with the
OSCILLATOR is to provide variable speed adjustment for the
motor by means of PWM of the low-side drivers.

OSCILLATOR (Pin 14)

A reisistor and capacitor connected to this pin (See Fig. 6) pro­vide the timing components for a sawtooth OSCILLATOR. The
signal generated is used in conjunction with V TRIP to provide
PWM for variable speed applications and to reset the over­current condition.

OUTPUTS 1, 2, 3 (Pins 2, 3, 4)

These open drain outputs are enabled as shown in Table III and
provide base current when the COMMON (Pin 5) is tied to Vss.
These outputs provide commutation only for the high-side driv­ers. They are not pulse width modulated to control speed.

OUTPUT 4, 5, 6 (PINS 6, 7, 8)

These open drain outputs are enabled as in Table III and
provide base current to NPN transistors when the COMMON is
tied to Vss. They provide commutation and are pulse width
modulated to provide speed control.

COMMON (Pin 5)

The COMMON is connected to Vss for driving low-side drivers
and high-side level converters.

Vss (Pin 11) Supply voltage positive terminal.
VDD (Pin 18) Supply voltage negative terminal.

TYPICAL CIRCUIT OPERATION:

Figure 1 indicates an application using bipolar power tran­sistors. The oscillator is used for motor speed control as ex­plained under VTRIP. Only low-side drive transistors are pulse
width modulated during speed control. The outputs turn on
in pairs (See Table III). For example, two separate paths are
turned on when Q8 and Q4 are on. One path is from the pos­itive supply through Q8, R1 and the base emitter junction of
Q101. The second is from the positive supply through Q4, R14,
the base emitter junction of Q105 and the fractional ohm re­sistor to ground. The current in the first path is determined by
the power supply voltage, the impedance of Q8, the value of
R1 and the voltage drop across the base-emitter junction of
Q101 (0.7 Volts for a single transistor or 1.4 Volts for a Darling­ton Transistor). The current in the second path is determined
by the power supply voltage, the impedance of Q4, the value of
R14 and the voltage drop across the base-emitter junction of
Q105. Table I provides the recommended value for R1; R2,
R3, R13, R14, and R15 are the same value.
Figure 2 indicates an application where Power FETS are used.
The nominal power supply for the LS7362 in this configuration
is 15 Volts so that the low side N channel Power FET drivers
will have 15 Volts of gate drive. Resistors R13, R14 and R15
serve to discharge the gate capacitance during FET turn-off.
The high-side P-channel FET drivers use 15 Volt Zener diodes
Z1, Z2 and Z3 to limit the gate drive. Resistors R8, R10 and
R12 are the gate capacitance discharge resistors. Table II in­dicates the minimum value of R13 (=R14=R15) needed as a
function of output drive voltage for the low-side drivers.

7362-110292-2