Datasheet LS7166-TS24, LS7166-S, LS7166 Datasheet (LSI)

24-BIT QUADRATURE COUNTER

FEATURES:

• Programmable modes are: Up/Down,
Binary, BCD, 24 Hour Clock, Divide-by-N,
x1 or x2 or x4 Quadrature and Single Cycle.

• DC to 20 MHz Count Frequency.

• 8-Bit I/O Bus for Microprocessor
Communication and Control.

• 24-Bit comparator for pre-set count
comparison.

• Readable status register.

• Input/Output TTL and CMOS compatible.

• 5 Volt operation (Vdd - Vss).

• LS7166 (DIP); LS7166-S (SOIC);

LS7166-TS24 (24-Pin TSSOP)* - See Fig. 1

GENERAL DESCRIPTION:

The LS7166 is a CMOS, 24-bit counter that
can be programmed to operate in several dif­ferent modes. The operating mode is set up
by writing control words into internal control
registers (see Figure 8). There are three 6-bit
and one 2-bit control registers for setting up
the circuit functional characteristics. In addi­tion to the control registers, there is a 5-bit out­put status register (OSR) that indicates the cur­rent counter status. The IC communicates with
external circuits through an 8-bit three state I/O
bus. Control and data words are written into
the LS7166 through the bus. In addition to the
I/O bus, there are a number of discrete inputs
and outputs to facilitate instantaneous hard­ware based control functions and in­stantaneous status indication.

REGISTER DESCRIPTION:

Internal hardware registers are accessible
through the I/O bus (D0 - D7) for READ or
WRITE when CS = 0. The C/D input selects
between the control registers (C/D = 1) and the
data registers (C/D = 0) during a READ or
WRITE operation. (See Table 1)

The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.

(Write Input) WR

(Chip Select Input) CS
(Load Counter/Load Latch) LCTR/LLTC
(A, B Gate/Reset Counter)ABGT/RCTR

VDD (+5V)
(Count Input) A
(Count Input) B

D0
D1
D2

VSS (GND)
RD (Read Input)
C/D (Control/ Data Input)
BW (Borrow Output)
CY (Carry Output)
D7
D6
D5
D4
D3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

LSI

LS7166

December 2002

FIGURE 1

7166-120902-1

LSI/CSI

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 [phone] FAX [phone]

LS7166

U

L

®

A3800

20-Pin Package PIN ASSIGNMENT - Top View

*(Contact factory for 24-Pin TSSOP Package Pinout)

OSR (Output Status Register). Indicates CNTR status: Accessed by: READ when C/D = 1, CS = 0.

Bit # 7 6 5 4 3 2 1 0
U U U 0/1 0/1 0/1 0/1 0/1

BWT. Borrow Toggle Flip-Flop. Toggles everytime CNTR underflows
generating a borrow.
CYT. Carry Toggle Flip-Flop. Toggles everytime CNTR overflows
generating a carry.
COMPT. Compare Toggle Flip-Flop. Toggles everytime CNTR equals PR
SIGN. Sign bit. Reset ( = 0) when CNTR underflows
Set ( = 1) when CNTR overflows
UP/DOWN. Count direction indicatior in quadrature mode.
Reset ( = 0) when counting down
Set ( = 1) when counting up
(Forced to 1 in non-quadrature mode)

OL(Output latch). The OL is the output port for the CNTR. The 24 bit CNTR Value at any instant can be accessed

by performing a CNTR to OL transfer and then reading the OL in 3 READ cycle sequence of Byte 0 (OL0), Byte 1 (OL1)
and Byte 2 (OL2). The address pointer for OL0/OL1/OL2 is automatically incremented with each READ cycle.

Accessed by: READ when C/D = 0, CS = 0.
Bit # 7 0 7 0 7 0

OL2 OL1 OL0

(BYTE 2) (BYTE 1) (BYTE 0)
Standard Sequence for Loading and Reading OL:

3 MCR ; Reset OL address pointer and Transfer CNTR to OL
READ OL ; Read Byte 0 and increment address
READ OL ; Read Byte 1 and increment address
READ OL ; Read Byte 2 and increment address

TABLE 1 - Register Addressing Modes

D7 D6 C/D RD WR CS COMMENT
X X X X X 1 Disable Chip for READ/WRITE
0 0 1 1 0 Write to Master Control Register (MCR)

0 1 1 1 0 Write to input control register (ICR)
1 0 1 1 0 Write to output/counter control register (OCCR)
1 1 1 1 0 Write to quadrature register (QR)

X X 0 1 0 Write to preset register (PR) and increment register
address counter.

X X 0 1 0 Read output latch (OL) and increment register
address counter

X X 1 1 0 Read output status register (OSR).

X = Don't Care

U = Undefined

7166-062394-3

PR (Preset register). The PR is the input port for the CNTR. The CNTR is loaded with a 24 bit data via the PR. The
data is first written into the PR in 3 WRITE cycle sequence of Byte 0 (PR0), Byte 1 (PR1) and Byte 2 (PR2).
The address pointer for PR0/PR1/PR2 is automatically incremented with each write cycle.
Accessed by: WRITE when C/D = 0, CS = 0.

Bit # 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0
PR2 PR1 PR0

(BYTE 2) (BYTE 1) (BYTE 0)
Standard Sequence for Loading PR and Reading CNTR:

1 MCR ; Reset PR address pointer
WRITE PR ; Load Byte 0 and into PR0 increment address
WRITE PR ; Load Byte 1 and into PR1 increment address
WRITE PR ; Load Byte 2 and into PR3 increment address

8 MCR ; Transfer PR to CNTR

MCR (Master Control Register). Performs register reset and load operations. Writing a "non-zero” word to MCR does
not require a follow-up write of an “all-zero” word to terminate a designated operation.
Accessed by: WRITE when C/D = 1, CS = 0.

Bit # 7 6 5 4 3 2 1 0
0 0

1: Reset PR/OL address pointer
1: Transfer CNTR to OL (24 bits)
1: Reset CNTR, BWT and CYT. Set SIGN bit.
(CNTR=0, BWT=0, CYT=0, SIGN=1)
1: Transfer PR to CNTR (24 bits)
1: Reset COMPT (COMPT = 0)
1: Master reset. Reset CNTR, ICR, OCCR, QR, BWT, CYT, OL
COMPT, and PR/OL address pointer. Set PR (PR=FFFFFF) and SIGN.
0: Select MCR
0:
NOTE: Control functions may be combined.

ICR (Input Control Register). Initializes counter input operating modes.
Accessed by: WRITE when C/D = 1, CS = 0.
Bit # 7 6 5 4 3 2 1 0

0 1
0: Input A = Up count input, Input B = Down count input
1: Input A = Count input, Input B = Count direction input (overridden in
quadrature mode) where B = 0 selects up count mode and B =1
selects Down count mode.
(NOTE: During counting operation B may switch only when A = 1.)
0: NOP
1: Increment CNTR once (A/B = 1, if enabled)
0: NOP
1: Decrement CNTR once (A/B = 1, if enabled)
0: Disable inputs A/B
1: Enable inputs A/B
0: Initialize Pin 4 as CNTR Reset input (Pin 4 = RCTR)
1: Initialize Pin 4 as Enable/Disable gate for A/B inputs (Pin 4 = ABGT)
0: Initialize Pin 3 as CNTR load input (Pin 3 = LCTR)
1: Initialize Pin 3 as OL load input (Pin 3 = LLTC)
1: Select ICR
0:

NOTE: Control functions may be combined.

7166-062394-2

OCCR (Output Control Register) Initializes CNTR and output operating modes.
Accessed by : WRITE when C/D = 1, CS = 0.

Bit # 7 6 5 4 3 2 1 0
1 0

0: Binary count mode (Overridden by D3 = 1).
1: BCD count mode (Overridden by D3 = 1)
0: Normal count mode
1: Non-Recycle count mode. (CNTR enabled with a Load or Reset
CNTR and disabled with generation of Carry or Borrow.
In this mode no external CY or BW is generated. Instead
CYT or BWT should be used as cycle completion indicator.)
0: Normal count mode

1: Divide by N count mode (CNTR is reloaded with PR data upon
Carry or Borrow).
0: Binary or BCD count mode (see D0)
1: 24 Hour Clock mode with Byte 0 = Sec, Byte 1 = Min and Byte 2 = Hr.
(Overrides BCD/Binary Modes)

0

Pin 16 = CY, Pin 17 = BW. (Active Low)

0
1

Pin 16 = CYT, Pin 17 = BWT

0
0

Pin 16 = CY, Pin 17 = BW. (Active high)

1
1

Pin 16 = COMP, Pin 17 = COMPT

1
0

Select OCCR

1

QR (Quadrature Register). Selects quadrature count mode (See Fig. 7)
Accessed by: WRITE when C/D = 1, CS = 0.

Bit # 7 6 5 4 3 2 1 0
1 1 X X X X
0

Disable quadrature mode

0
1

Enable x1 quadrature mode

0
0

Enable x2 quadrature mode

1
1

Enable x4 quadrature mode

1
1

Select QR

1

7166-062394-4

X = Don’t Care

I/O DESCRIPTION:
(See REGISTER DESCRIPTION for I/O Prgramming.)

Data-Bus (D0-D7) (Pin 8-Pin 15). The 8-line data bus is a

three-state I/O bus for interfacing with the system bus.
CS (Chip Select Input) (Pin 2). A logical "0" at this input en­ables the chip for Read and Write.
RD (Read Input) (Pin 19). A logical "0" at this input enables the
OSR and the OL to be read on the data bus.
WR (Write Input) (Pin 1) A logical "0" at this input enables the
data bus to be written into the control and data registers.
C/D (Control/Data Input) (Pin 18). A logical "1" at this input en­ables a control word to be written into one of the four control
registers or the OSR to be read on the I/O bus. A logical "0" en­ables a data word to be written into the PR, or the OL to be read
on the I/O bus.
A (Pin 6). Input A is a programmable count input capable of
functioning in three different modes, such as up count input,
down count input and quadrature input.
B (Pin 7). Input B is also a programmable count input that can
be programmed to function either as down count input, or count
direction control gate for input A, or quadrature input. When B is
programmed as count direction control gate, B = 0 enables A as
the Up Count input and B = 1 enables A as the Down Count in­put. When programmed as the direction input, B can switch
state only when A is high.

ABGT/RCTR (PIN 4). This input can be programmed to func­tion as either inputs A and B enable gate or as external counter
reset input. A logical "0" is the active level on this input.

DC Electrical Characteristics. (All voltages referenced to VSS.
TA = 0˚ to 70˚C, VDD = 4.5V to 5.5V, fc = 0, unless otherwise specified)

Parameter Symbol Min. Value Max.Value Unit Remarks
Supply Voltage VDD 4.5 5.5 Volts ­Supply Current IDD - 350 µA Outputs open
Input Low Voltage VIL 0 0.8 Volts ­Input High Voltage VIH 2.0 VDD Volts ­Output Low Voltage VOL - 0.4 Volts 4mA Sink
Output High Voltage VOH 2.5 - Volts 200µA Source
Input Current - - 15 nA Leakage

Current
Output Source Current ISRC 200 - µA VOH = 2.5V
Output Sink Current ISINK 4 - mA VOL = 0.4V
Data Bus Off-State
Leakage Current - - 15 nA -

Absolute Maximum Ratings:

Parameter Symbol Values Unit

Voltage at any input VIN VSS - 0.3 to VDD + 0 .3 Volts
Operating Temperature TA 0 to +70

o

C

Storage Temperature TSTG -65 to +150

o

C

Supply Voltage VDD - VSS +7.0 Volts

In non-quadrature mode, if Pin 4 is programmed as A and B en­able gate input, it may switch state only when A is high (if A is
clock and B is direction) or when both A and B are high (if A
and B are clocks. In quadrature mode, if Pin 4 is programmed
as A and B enable gate, it may switch state only when either A
or B switches.

LCTR/LLTC (PIN 3). This input can be programmed to func­tion as the external load command input for either the CNTR or
the OL. When programmed as counter load input, the counter
is loaded with the data contained in the PR. When pro­grammed as the OL load input, the OL is loaded with data con­tained in the CNTR. A logical "0" is the active level on this in­put.
CY (Pin 16). This output can be programmed to serve as one
of the following:

A. CY. Complemented Carry out (active "0").
B. CY. True Carry out (active "1").
C. CYT. Carry Toggle flip-flop out.

D. COMP. Comparator out (active "0")
BW (Pin 17). This output can be programmed to serve as one
of the following:

A. BW. Complemented Borrow out (active "0").

B. BW. True Borrow out (active "1").

C. BWT. Borrow Toggle flip-flop out.

D. COMPT. Comparator Toggle output.

VDD (Pin 5). Supply voltage positive terminal.
VSS (Pin 20). Supply voltage negative terminal.

7166-111299-5

­TRANSIENT CHARACTERISTICS (See Timing Diagrams in Fig. 2 thru Fig. 7,
VDD = 4.5V to 5.5V, TA = 0˚ to 70˚C, unless otherwise specified)

Parameter Symbol Min.Value Max.Value Unit
Clock A/B "Low” TCL 20 No Limit ns
Clock A/B "High" TCH 30 No Limit ns
Clock A/B Frequency fc 0 20 MHz
(See NOTE 1)
Clock UP/DN Reversal TUDD 100 - ns
Delay
LCTR Positive edge to TLC 100 - ns
the next A/B positive or
negative edge delay
Clock A/B to TCBL - 65 ns
CY/BW/COMP "low"
propagation delay
Clock A/B to TCBH - 85 ns
CY/BW/COMP "high"
propagation delay
LCTR and LLTC pulse TLCW 60 - ns
width
Clock A/B to CYT, BWT TTFH - 100 ns
and COMPT "high"
propagation delay
Clock A/B to CYT, BWT TTFL - 100 ns
and COMPT "low"
progagation delay
WR pulse width TWW 60 - ns
RD to data out delay TR - 110 ns
(CL = 20pF)
CS, RD Terminate to TRT - 30 ns
Data-Bus Tri-State

Data-Bus set-up TDS 15 - ns (see Note 3)
time for WR
Data-Bus hold time for WR TDH 30 - ns (see Note 3)
C/D, CS set-up time for RD TCRS 0 - ns
C/D, CS hold time for RD TCRH 0 - ns
C/D set-up time for WR TCWS 15 - ns (see Note 3)
C/D hold time for WR TCWH 30 - ns (see Note 3)
CS set-up time for WR TSWS 15 - ns (see Note 3)
CS holdtime for WR TSWH 0 - ns (see Note 3)

Quadrature Mode:

Clock A/B Validation delay TCQV - 160 ns
(See NOTE 2)
A and B phase delay TPH 208 - ns
Clock A/B frequency fCQ - 1.2 MHz
CY, BW, COMP pulse width TCBW 75 180 ns

NOTE 1: A) In Divide by N mode, the maximum clock frequency is 10 MHz.
B) The maximum frequency for valid CY, BW, CYT, BWT, COMP, COMPT is 10 MHz.

NOTE 2: In quadrature mode A/B inputs are filtered and required to be stable
for at least TCQV length to be valid.

NOTE 3: All WR specifications are critical for proper operation of LS7166

7166-120902-6

FIGURE 2 . LOAD COUNTER, UP CLOCK, DOWN CLOCK, COMPARE OUT, CARRY, BORROW

NOTE 1: The counter in this example is assumed to be operating in the binary mode.
NOTE 2: No COMP output is generated here, although PR = CNTR. COMP output is disabled with a counter load command and

enabled with the rising edge of the next clock, thus eliminating invalid COMP outputs whenever the CNTR is loaded from the PR.
NOTE 3: When UP Clock is active, the DN Clock should be held "HIGH" and vice versa.

CNTR=FFFFFD

(PR=CNTR)

CNTR=FFFFFE

CNTR=FFFFFF CNTR=000000 CNTR=000000

CNTR=FFFFFE

CNTR=0000001

CNTR=FFFFFD

(PR=CNTR)

CNTR=FFFFFF

NOTE 2

UP CLK (A)

DN CLK (B)

Q0
(Internal)

Q1
(Internal)

COMP

CY

BW

LTCR

TLCW

TCL

TUDD

TCH

TCL

TCH

Q2-Q23

(Internal)

TLC

UP CLK
OR DN CLK

CY

CYT

BW

BWT

COMP

COMPT

FIGURE 3. CLOCK TO CY/BW OUTPUT PROPAGATION DELAYS

TCBL

TCBH

TTFH

TCBL

TCBH

TTFH

TTFH

TTFL

TTFL

TCBL

TCBH

TTFL

SIGN

(INTERNAL)

7166-030192-7

C/D

WR

CS, C/D

RD

TCRS TCRH

DATA BUS

TRD

VALID OUTPUT

TWW

TCWS TCWH

DATA BUS

FIGURE 4. READ/WRITE CYCLES

VALID DATA

TDS

TDH

TSWS

TSWH

CS,

T

RT

Q1
(INTERNAL)

Q2-Q23
(INTERNAL)

DN CLK

LCTR

CNTR LD

(INTERNAL)

BW

Q0
(INTERNAL)

CNTR=3 =2 =1 =0 =3 =2 =1 =0 =3

FIGURE 5. DIVIDE BY N MODE

NOTE: EXAMPLE OF DIVIDE BY 4 IN DOWN COUNT MODE

CNTR DISABLED

CNTR ENABLED

CNTR DISABLED

CNTR LOAD
(LCTR or MCR BASED)

CY or BW

FIGURE 6 . CYCLE ONCE MODE

UP CLK OR
DN CLK

7166-030494-8

TPH TPH

A

B

UPCLK (X1)

(Internal)

DNCLK (X1)

(Internal)

UPCLK (X2)

(Internal)

DNCLK (X2)

(Internal)

UPCLK (X4)

(Internal)

DNCLK (X4)

(Internal)

FORWARD

REVERSE

UP/DN(OSR Bit 4)

CY

BW

FIGURE 7.

QUADRATURE MODE INTERNAL CLOCKS

TCBW

TCBW

TCQV

TCQV

7166-030392-9

3

4

7

PR/OL
ADDRESS

INPUT
BUFFER
AND
DECODE
LOGIC

(DATA-BUS) 8-15

I/O

BUFFER

D0 - D7

18

1

19

2

D0, D6,D7

D0 - D7

D0 - D7

D0 - D7

D0 -D7

5

20

(+5V) VDD

(GND) VSS

INTERNAL DATA BUS

D0 -D4

QR

OCCR

ICR

MCR

PR0

B0 - B7

PR1

B8 - B15

PR2

DN CLOCK

UP CLOCK

D0 - D7

PR/OL ADDRESS

B16 - B23

CNTR

B0 - B23

N1=N2

N1

N2

STATUS
LOGIC

OL0

OL1

OL2

Q0 -Q23

CONTROL
LOGIC

OSR

FIGURE 8.

LS7166 BLOCK DIAGRAM

6

(LOAD CTR/LOAD LATCH) LCTR/LLTC

(AB GATE/LOAD LATCH) ABGT/RCTR

(COUNT INPUT) B

(COUNT INPUT) A

(CONTROL /DATA INPUT) C/D

(WRITE INPUT) WR

(READ INPUT) RD

(CHIP SELECT INPUT) CS

16

17

CY (CARRY OUT)

BW (BORROW OUT)

COMPARATOR

7166-03392-10

DECODE

DECODE

DECODE

8080

WR

DBIN

DATA BUS

A0

CS

7166

C/D

WR

RD

ADDRESS BUS

DATA

I/O DECODE

STB

A0

D0 - D7

CS

C/D
RD

WR

RD

WR

CS

C/D

D0 - D7

CLK

S0 -S2

WR

RD

S0 - S2

ALE

ADDRESS

+V

D

CK

Q

S

S74

R

7166

7166

8086/8088

8086/8088

(Minimum
Mode)

(Maximum
Mode)

ADDRESS

8282

IORC

IOWC

ALE

8288

DATA

ADRS/DATA

STB

A0

LS7166 INTERFACE EXAMPLES

8282

D0 - D7

ADRS/
DATA

7166-03392-11

DECODE

DATA BUS

ADDRESS BUS

IORQ

RD

WR

A0

C/D

CS

D0 - D7

RD

WR

7166

7166

7166

Z80

Z8000

68000
68008
68010

AS

ST0-ST3

R/W

DS

WR

RD

CS

C/D

D0 - D7

DECODE

LS373

I/O DECODE

CK

ADRS/
DATA

A0

DATA

ADDRESS

DATA BUS

A0

DECODE

D

Q

CK

S74

WR

RD

CS

C/D

D0 - D7

AS

R/W

LDS/UDS

DTACK

CLK

LS373

CK

ADDRESS

LS7166 INTERFACE EXAMPLES

D

Q

D Q

DQ

CK

S74

S

D

CK

S74

Q

R

R

R

+V

S

+V

S

CLOCK

7166-03392-12