LSI LS7062, LS7060 Datasheet

LSI/CSI

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 [phone] FAX [phone]

LS7060/7062

U

L

®

A3800

32 BIT/DUAL 16 BIT BINARY UP COUNTER

WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS

FEATURES:

• DC to 15 MHz Count Frequency

• Byte Multiplexer

• DC to 1 MHz Scan Frequency

• +4.75V to +5.25V Operation (VDD-VSS)

• Three-State Data Outputs, Bus and TTL Compatible

• Inputs TTL and CMOS Compatible

• Unique Cascade Feature Allows Multiplexing of
Successive Bytes of Data in Sequence in Multiple
Counter Systems

• Low Power Dissipation

• LS7060, LS7062 (DIP); LS7060-S, LS7062-S (SOIC)

See Figures 1 and 2
DESCRIPTION:

The LS7060/LS7062 is a monolithic, ion implanted MOS Silicon
Gate, 32 bit/dual 16 bit up counter. The IC includes latches, multi­plexer, eight three-state binary data output drivers and output
cascading logic.

DESCRIPTION OF OPERATION:

PIN ASSIGNMENT - TOP VIEW

COUNT

ALT COUNT

B3 OUT

B2 OUT

B1 OUT

B0 OUT

RESET

CASCADE EN OUT

VSS (-V)

July 1998

1

2

3

4

5

6

7

8

9

LSI

LS7060

FIGURE 1

VDD (+V)

18

B4 OUT

17

16

B5 OUT

B6 OUT

15

B7 OUT

14

TEST COUNT

13

SCAN RESET/LOAD

12

ENABLE

11

SCAN

10

32 (16) BIT BINARY UP COUNTER - LS7060 (LS7062)

The 32(16) bit static ripple through counter increments on the
negative edge of the input count pulse. Maximum ripple time is
4µs (2µs) - transition count of 32(16) ones to 32(16) zeros.
Guaranteed count frequency is DC to 15MHz.
See Figure 9A(9B) for Block Diagram.

COUNT, ALT COUNT (LS7060)
Input count pulses to the 32 bit counter may be applied through
either of these two inputs. The ALT COUNT input circuitry con­tains a Schmitt trigger network which allows proper counting with
"infinitely" long clock edges. A high applied to either of these two
inputs inhibits counting.

COUNT A, ALT COUNT A (LS7062)
Input count pulses to the first 16 bit counter may be applied
through either of these two inputs. The ALT COUNT A input cir­cuitry contains a Schmitt trigger network which allows proper
counting with “infinitely” long clock edges. A high applied to either
of these two inputs inhibits counting.

RESET

All 32 counter bits are reset to zero when RESET is brought low
for a minimum of 1µs. RESET must be high for a minimum of
300ns before next valid count can be recorded.

TEST COUNT (LS7060)
Count pulses may be applied to the last 16 bits of the binary
counter through this input, as long as Bit 16 of the counter is a
low. The counter advances on the negative transition of these
pulses. This input is intended to be used for test purposes.

7060/62-071698-1

PIN ASSIGNMENT - TOP VIEW

COUNT A

ALT COUNT A

B3 OUT

B2 OUT

B1 OUT

B0 OUT

RESET

CASCADE EN OUT

VSS (-)

1

2

3

4

5

6

7

8

9

LSI

LS7062

FIGURE 2

VDD (+V)

18

B4 OUT

17

16

B5 OUT

15

B6 OUT

14

B7 OUT

COUNT B

13

SCAN RESET/LOAD

12

ENABLE

11

SCAN

10

COUNT B (LS7062)

Count pulses may be applied to the last 16 bits of the binary
counter through this input. The counter advances on the neg­ative transition of these pulses.

LATCHES - LS7060 (LS7062)
32 bits of latch are provided for storage of counter data. All latch­es are loaded when the LOAD input is brought low for a mini­mum of 1µs and kept low until a minimum of 4µs (2µs) has
elapsed from previous negative edge of count pulse (ripple time).
Storage of valid data occurs when LOAD is brought high for a
minimum of 250ns before next negative edge of count pulse or
RESET.

SCAN COUNTER AND DECODER

7060/62-071698-2

The scan counter is reset to the least significant byte position
(State 1) when SCAN RESET input is brought low for a mini­mum of 1µs. The scan counter is enabled for counting as long
as the ENABLE input is held low. The counter advances to the
next significant byte position on each negative transition of the
SCAN pulse. When the scan counter advances to State 5 it dis­ables the Output Drivers and stops in that state until
SCAN RESET is again brought low.

SCAN

When the scan counter is enabled, each negative transition of
this input advances the scan counter to its next state. When
SCAN is low the Data Outputs are disabled. When SCAN is
brought high the Data Outputs are enabled and present the
latched counter data corresponding to the present state of the
scan counter. Therefore, in microprocessor applications, the
Data Output Bus may be utilized for other activities while new
data is propagating to the outputs. This positive SCAN pulse
can be viewed as a "Place the next byte on my bus" instruction
from the microprocessor. Minimum positive and negative pulse
widths of 500ns for the SCAN signal are required for scan
counter operation.

SCAN RESET/LOAD

When this input is brought low for a minimum of 1µs, the scan
counter is reset to State 1, the least significant byte position,
and the latches are simultaneously loaded with new count
information.

ENABLE

When this input is high, the scan counter and the Data Outputs are
disabled. When ENABLE is low, the scan counter and Data Out­puts are enabled for normal operation. Transition of this input
should only be made while the SCAN input is in a low state in order
to prevent false clocking of the scan counter.

CASCADE ENABLE

This output is normally high. It transitions low and stays low when
the scan counter advances to State 5. In a multiple counter system
this output is connected to the ENABLE input of the next counter in
the cascade string. The SCAN input and SCAN RESET/LOAD in­put are carried to all the counters in the "Cascade". Counter 1 then
presents its bytes of data to the Output Bus on each positive transi­tion of the SCAN pulse as previously discussed. When State 5 of
Counter 1 is achieved, Counter 2 presents its data to the Output
Bus. This sequence continues until all counters in the cascade
have been addressed. See Figure 5 for an illustration of a 3 device
cascade design. This output is TTL and CMOS compatible.

THREE-STATE DATA OUTPUT DRIVERS

The eight Data Output Drivers are disabled when either ENABLE
input is high, the scan counter is in State 5, or the SCAN input is
low. The Output Drivers are TTL and Bus compatible.

The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.

ABSOLUTE MAXIMUM RATINGS:
PARAMETER SYMBOL VALUE UNIT

StorageTemperature TSTG -55 to +150 °C
Operating Temperature TA 0 to +70 °C
Voltage (any pin to VSS) VIN +10 to -0.3 V

DC ELECTRICAL CHARACTERISTICS:

(VDD = +5V ± 5%, VSS = 0V, TA = 0˚C to + 70˚C unless otherwise noted.)

PARAMETER SYMBOL Min MAX UNIT CONDITIONS

Power Supply Current IDD - 15 mA At Maximum Operating Frequency

VDD = Max, Outputs No Load
Input High Voltage VIH +3.5 VDD V ­Input Low Voltage VIL 0 +0.6 V -

Output High Voltage

CASCADE ENABLE VOH VDD-0.2 - V IO = 0, VDD = Min

+2.4 - V IO = -100µA, VDD = Min

B0 - B7 +2.4 - V IO = -260µA, VDD = Min

Output Low Voltage +2.0 - V IO = 750µA, VDD = Min

CASCADE ENABLE VOL - +0.2 V IO = 0, VDD = Min

+0.4 V IO = 1.6mA, VDD = Min
B0 - B7 +0.4 V IO = 1.6mA, VDD = Min
Output Source Current Isource 3.0 - mA VO = +1.2V, VDD = Min
B0 - B7 Outputs 4.8 - mA VO = +0.8V, VDD = Min

7.3 - mA VO = +0.4V, VDD = Min
Output Sink Current Isink 5.7 - mA VO = +1.2V, VDD = Min
B0 - B7 Outputs 4.0 - mA VO = +0.8V, VDD = Min

2.2 - mA VO = +0.4V, VDD = Min
Output Leakage Current IOL - 1 µA VO = +.4V to +2.4V,VDD = Min
B0 - B7 (Off State)
Input Capacitance CIN - 6 pF TA = 25˚C, f = 1MHz
Output Capacitance COUT - 12 pF TA = 25˚C, f = 1MHz
Input Leakage Current ILI - 1 µA VDD = Max
ENABLE, RESET, SCAN

INPUT CURRENT

*SCAN RESET/LOAD IIH - -2.5 µA VDD = Max, VIH = +3.5

IIL - -5 µA VDD = Max, VIL = 0

**All Count inputs IIH - 5 µA VDD = Max, VIH = +3.5

IIL - 1 µA VDD = Max, VIL = 0

*Input has internal pull-up resistor to VDD
** Inputs have internal pull-down resistor to VSS

7060/62-071398-3

DYNAMIC ELECTRICAL CHARACTERISTICS:

(VDD = +5V ± 5%, VSS = 0V, TA = 0˚C to +70˚C unless otherwise noted.)

PARAMETER SYMBOL MIN MAX UNIT CONDITIONS

Count Frequency fc DC 15 MHz -

(All Count inputs)
Count Pulse Width tCPW 30 - ns Measured at 50% point,
(All Count Inputs) Max tr, tf = 10ns

Count Rise & Fall time tr, tf - 30 µs ­(Pins 1, 13)

Count Ripple Time tCR - 4 µs Transition from 32 ones to 32 zeros

(Pins 1, 2 - LS7062) from negative edge of count pulse
Count Ripple Time tCR - 2 µs Transition of 16 bits from

(Pin 13 - LS7060) all ones to all zeros from negative edge
(Pins 1,2,13 - LS7062) of count pulse

Reset Pulse Width tRPW 500 - ns Measured at 50% point

(All Counter Stages Max tr, tf = 200ns

Fully Reset)
RESET Removal Time tRR - 250 ns Measured from RESET signal at VIH

(Reset Removed From

All Counter Stages)

SCAN Frequency fSC - 1 MHz

SCAN Pulse Wildth tSCPW 500 - ns Measured at 50% point

Max tr, tf = 100ns
SCAN RESET/LOAD tRSCPW 1 - µs Measured at 50% point
Pulse Width Max tr, tf = 200ns
(All latches loaded and
Scan Counter Reset to
Least Significant Byte)

SCAN RESET/LOAD tRSCR - 250 ns Measured from SCAN RESET/

Removal Time LOAD at VIH
(Reset Removed from
Scan Counter; Load
Command Removed
From Latches)

Output Disable tDOD - 200 ns Transition to Output High
Delay Time Impedance State Measured
(B0 - B7) From Scan at VIL or

ENABLE at VIH
Output ENABLE tDOE - 200 ns Transition to Valid On State
Delay Time Measured from Scan at VIH
(B0 - B7) and ENABLE at VIL; Delay to

Valid Data Levels for COL =10pF

and one TTL Load or Valid Data

Currents for High Capacitance Loads
Output Delay Time tDCE - 300 ns Negative Transition from Scan at VIL
CASCADE ENABLE and ST5 of Scan Counter or Positive

Transition From SCAN RESET/LOAD at

VIL to Valid Data Levels for COL = 10pF

and one TTL Load