LSI LS6501LP Datasheet

LSI/CSI

LS6501LP

U

A3800

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 [phone] FAX [phone]

L

®

PIR MOTION DETECTOR

FEATURES:

• Low Quiescent Current

• Direct Interface with PIR Sensor

• Two-Stage Differential Amplifier

• Amplifier Gain and Bandwidth externally controlled

• Window Comparator and Digital Filter limit Noise

• Triac or Relay Output Drive

• Programmable Output Duration Timer

• Ambient Light Level Inhibit input

• Selectable Dead Time

• Single or Dual Pulse Detection

• Timing derived from RC Oscillator or 50Hz/60Hz AC

• Regulated 5V Output for PIR Sensor

• Motion Detection LED Indicator

• Triac can drive Incandescent or Fluorescent Lamps

• LS6501LP (DIP), LS6501LP-S (SOIC-NB)
LS6501LP-SW (SOIC-WB) - See Figure 1

APPLICATIONS:

• Automatic Light Control

• Intrusion Alarm
DESCRIPTION: (See Figure 2)

The LS6501LP is a monolithic, CMOS Silicon Gate in­tegrated circuit, designed for detecting motion from a PIR
Sensor and initiating appropriate responses. The detailed
description of the functional blocks is as follows:

DIFFERENTIAL AMPLIFIER

Each stage of the two stage Differential Amplifier can be set
to have its own amplification and bandwidth. The two inputs
to the first stage allow for single ended or differential con­nection to PIR Sensors. This stage can be biased anywhere
in its dynamic range. The second stage is internally biased
so that the Window Comparator’s lower and higher thresh­olds can be fixed relative to this bias.

WINDOW COMPARATOR

The Window Comparator provides noise filtering by enabling
only those signals equal to or greater than a fixed threshold
at the output of the Differential Amplifier to appear at the
output of the Window Comparator.

COMPARATOR DIGITAL FILTER

The output of the Window Comparator is filtered so that
motion must be present for a certain duration before it can
be recognized and appear as pulses at the Digital Filter
output.

6501LP-071201-1

July 2001

PIN ASSIGNMENT - TOP VIEW

DIFF. AMP. 1 OUTPUT

DIFF. AMP. 2 INPUT (-)

DIFF. AMP. 2 OUTPUT

OSCILLATOR INPUT

AC INPUT

VSS

TRIAC/RELAY OUTPUT

VDD

LSI

1

2

3

LS6501LP

4

5

6

7

8

FIGURE 1

16

DIFF. AMP 1 INPUT (-)

15

DIFF. AMP 1 INPUT (+)

14

5V REGULATOR OUTPUT

13

TIMER CONTROL INPUT

12

DEAD TIME SELECT INPUT

11

INHIBIT INPUT
PULSE MODE

10

SELECT INPUT

9

LED OUTPUT

OUTPUT DURATION TIMER

The voltage level at the TIMER CONTROL input can
select 16 different timeouts for this Timer (See Table 1).
The selection can be made by varying the setting of a
potentiometer. The Timer is retriggerable and controls
the ON duration of the TRIAC/RELAY output. The trigger
for the Timer is generated from pulses appearing at the
Digital Filter output.

SINGLE PULSE/DUAL PULSE MODES

A Single Pulse or Dual Pulse (two pulses occurring within
a specified time period) at the Digital Filter output can be
selected as the trigger for the Output Duration Timer.
This selection is made by the logic level at the PULSE
MODE SELECT input. Logic 0 = Single Pulse Mode,
logic 1 = Dual Pulse Mode.

LED OUTPUT

This is an open drain output which is turned on by pulses
generated by a retriggerable one-shot. The one-shot is
triggered by the leading edge of pulses appearing at the
Digital Filter output. When turned on, this output can sink
current from a series Resistor-LED network returned to a
positive voltage (VDD to 12.5V maximum). This results in
the LED lighting whenever motion is detected.

INHIBIT

The Output Duration Timer can be inhibited from trig­gering by the voltage level at the INHIBIT input. When this
voltage level exceeds the Inhibit Threshold, the Timer will
be prevented from triggering if it is OFF. If the Timer is
ON, the INHIBIT input is blocked from affecting the Timer.
There is approximately 10% hysteresis between the In­hibit and Enable thresholds at the INHIBIT input. The LED
output is not affected by the INHIBIT input. An adjustable
Ambient Light Level Inhibit can be implemented by con­necting a Light Determining Resistor (LDR) network to the
INHIBIT input (See Figures 3 and 4).

DEAD TIME

False turn-ons are prevented from occurring by es­tablishing a Dead Time between the end of the timeout of
the Output Duration Timer and the retriggering of that
Timer. The state of the DEAD TIME SELECT input de­termines the Dead Time duration (See Table 2).

OSCILLATOR

For battery operation, an external RC is connected to the
OSCILLATOR input to produce a 50Hz or 60Hz clock. A
30Hz clock can be used to extend timing durations (See
Tables 1 and 2).

DC POWER SUPPLY

VDD-Vss is 8V±1V. Typical quiescent current is 250µA
(TRIAC/RELAY, LED and REGULATOR outputs not loaded).

DC REGULATOR

The LS6501LP includes a Regulator which provides a
nominal +5V to the Differential Amplifier and Window
Comparator and is available as an output to supply the
PIR Sensor.

TRIAC/RELAY OUTPUT

This open drain output turns ON when the Output Dura­tion Timer is triggered. The output drives a Triac when
the OSCILLATOR input is tied to ground and 50/60Hz is
applied to the AC input (See Figure 3). The output drives
a Relay when the AC input is tied to ground and an RC
network is connected to the OSCILLATOR input (See
Figure 4).

TRIAC DRIVE (See Figure 3)
With the Output Duration Timer ON and a 2.7V P-P
60Hz signal applied to the AC input, the output produces
a negative-going pulse in each half-cycle delayed a
nominal 1.2ms from the zero crossing. There is no more
than 150µs difference between the zero-crossing delay
of each pulse.

RELAY DRIVE (See Figure 4)
The output can sink current continously with the Output
Duration Timer ON and the OSCILLATOR input active.
This output can sink current from a relay coil returned to
a positive voltage (VDD to 12.5V maximum).

TABLE 1

OUTPUT DURATION TIMER AS A FUNCTION OF TIMER CONTROL INPUT VOLTAGE

(f = Frequency at AC input or OSCILLATOR input)

INPUT VOLTAGE f = 30Hz f = 50Hz f = 60Hz UNIT

0 30 18 15
1/16 VDD 60 36 30
2/16 VDD 90 54 45
3/16 VDD 120 72 60
4/16 VDD 4 2.4 2
5/16 VDD 6 3.6 3
6/16 VDD 8 4.8 4
7/16 VDD 10 6 5
8/16 VDD 12 7.2 6
9/16 VDD 14 8.4 7

10/16 VDD 16 9.6 8
11/16 VDD 18 10.8 9
12/16 VDD 20 12 10
13/16 VDD 24 14.4 12
14/16 VDD 28 16.8 14
15/16 VDD 30 18 15

sec
sec
sec
sec
min
min
min
min
min
min
min
min
min
min
min
min

TABLE 2

DEAD TIME DURATION AS A FUNCTION OF THE STATE OF DEAD TIME SELECT INPUT

(f = Frequency at AC input or OSCILLATOR input)
INPUT STATE f = 30Hz f = 50Hz f = 60Hz UNIT

0 2 1.2 1

OPEN 8 4.8 4

1 16 9.6 8

sec
sec
sec

6501LP070601-2

ABSOLUTE MAXIMUM RATINGS:

PARAMETER SYMBOL VALUE UNIT

DC supply voltage VDD - VSS +10 V
Any input voltage VIN VSS - 0.3 to VDD + 0.3 V
Operating temperature TA -40 to +85 °C
Storage temperature TSTG -65 to +150 °C

ELECTRICAL CHARACTERISTICS:

( All voltages referenced to VSS, TA = -40˚C to +55˚C, 7V≤ VDD ≤9V, unless otherwise specified.)

PARAMETER SYMBOL MIN TYP MAX UNIT CONDITIONS

SUPPLY CURRENT:

VDD = 8V IDD - 250 350 µA TRIAC/RELAY,
VDD = 7V - 9V IDD - 300 420 µA LED and REGULATOR

outputs not loaded

REGULATOR:

Voltage VR 4.5 - 6 V -

Current IR - - 200 µA -

DIFFERENTIAL AMPLIFIERS:

Open Loop Gain, Each Stage G 70 - - dB -

Common Mode Rejection Ratio CMRR 60 - - dB -
Power Supply Rejection Ratio PSRR 60 - - dB -

Output Drive Current ID - - 25 µA -

Input Sensitivity VS 70 - - µV TA = 25˚C, with Amplifier
(Minimum Detectable Voltage Bandpass configuration
to first amplifier when both as shown in Figure 3
amplifiers are cascaded for

a net gain of 7,500)
Input Dynamic Range - 0 - 2.5 V -

Diff. Amp 2 Internal VIR - .4VR - V -

Reference

COMPARATOR:

Lower Reference VTHL - VIR - .5V - V -
Higher Reference VTHH - VIR + .5V - V -

DIGITAL FILTER:

Input Pulse Width TPW 66.3 - - ms 60Hz operation

(for recognition) TPW 79.6 - - ms 50Hz operation

INHIBIT INPUT:

Inhibit Threshold VTHI - ≥ .5VDD - V -

Enable Threshold VTHE - ≤ .45VDD - V -

OSCILLATOR:

Resistor RO - 2.2 - MΩ 60Hz Oscillator
Capacitor CO - .01 - µF Frequency

Resistor RO - 4.3 - MΩ 30Hz Oscillator
Capacitor CO - .01 - µF Frequency

6501LP-070601-3