LSI L64105 MPEG-2 Technical Manual

®

L64105 MPEG-2
A udio/Video Decoder

Technical Manual

Preliminary

查询L64105供应商 捷多邦，专业PCB打样工厂，24小时加急出货

ii

This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.

Document DB14-000041-00, First Edition (July 1998)
This document describes revision A of LSI Logic Corporation’s L64105 MPEG-2
Audio/Video Decoder and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.

To receive product literature, call us at 1.800.574.4286 (U.S. and Canada);
+32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, and Europe)
and ask for Department JDS; or visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.

In particular, supply of the LSI Logic IC L64105 does not convey a license or
imply a right under certain patents and/or other industrial or intellectual property
rights claimed by IRT, CCETT and Philips, to use this IC in any ready-to-use
electronic product. The purchaser is hereby notified that Philips, CCETT and IRT
are of the opinion that a generally available patent license for such use is
required from them. No warranty or indemnity of any sort is provided by LSI Logic
regarding patent infringement.

Copyright © 1997, 1998 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT

The LSI Logic logo design and G10 are registered trademarks of LSI Logic
Corporation. All other brand and product names may be trademarks of their
respective companies.

Contents iii

Contents

Preface

Chapter 1 Introduction

1.1 An L64105 Application 1-1

1.2 L64105 Overview 1-2

1.2.1 Memory Utilization 1-5

1.2.2 Error Concealment 1-5

1.3 Features 1-6

Chapter 2 I/O Signal Descriptions

2.1 Signals Organization 2-1

2.2 Host Interface 2-3

2.3 Channel Interface 2-5

2.4 Memory Interface 2-7

2.5 Video Interface 2-8

2.6 Audio Interface 2-9

2.7 Miscellaneous and Test Interfaces 2-11

Chapter 3 Register Summary

3.1 Summary by Register 3-1

3.2 Alphabetical Listing 3-30

Chapter 4 Register Descriptions

4.1 Host Interface Registers 4-2

4.2 Video Decoder Registers 4-17

4.3 Memory Interface Registers 4-38

4.4 Microcontroller Registers 4-48

iv Contents

4.5 Video Interface Registers 4-58

4.6 Audio Decoder Registers 4-72

4.7 RAM Test Registers 4-91

Chapter 5 Host Interface

5.1 Overview 5-1

5.2 Interface Signals 5-2

5.3 Register Access and Functions 5-5

5.3.1 General Functions 5-5

5.3.2 SCR Registers 5-6

5.3.3 Interrupt Registers 5-9

5.4 SDRAM Access 5-10

5.4.1 Host Reads/Writes 5-10

5.4.2 Host DMA SDRAM Transfers 5-14

5.4.3 SDRAM Block Move 5-18

Chapter 6 Channel Interface

6.1 Overview 6-1

6.2 Interface Signals Operation 6-3

6.2.1 Asynchronous Mode 6-4

6.2.2 Synchronous VALIDn Inputs 6-5

6.2.3 Synchronous A/VREQn Outputs 6-7

6.2.4 Channel Bypass Mode 6-8

6.2.5 Channel Pause 6-8

6.3 Preparser 6-9

6.3.1 Host Selection of Streams and Headers 6-9

6.3.2 Elementary Streams 6-12

6.3.3 PES Packet Structure 6-14

6.3.4 Preparsing an MPEG-1 System Stream 6-16

6.3.5 Preparsing a Program Stream 6-18

6.3.6 Error Handling in Program Streams 6-21

6.3.7 Preparsing A/V PES Packets from a
Transport Stream 6-24

6.3.8 Error Handling in A/V PES Mode 6-25

6.4 Channel Buffer Controller 6-27

6.4.1 Buffer Reset 6-28

Contents v

6.4.2 Detecting Potential Underflow Conditions
in the Video Channel 6-29

6.5 Summary 6-30

Chapter 7 Memory Interface

7.1 Overview 7-1

7.2 SDRAM Configurations 7-2

7.3 SDRAM Timing and Modes 7-3

7.4 SDRAM Refresh and Arbitration 7-5

7.5 Memory Channel Buffer Allocation 7-6

7.6 Memory Frame Store Allocation 7-9

7.6.1 Luma Store 7-9

7.6.2 Chroma Store 7-9

7.6.3 Normal Mode 7-10

7.6.4 Reduced Memory Mode (RMM) 7-11

7.7 Summary 7-12

Chapter 8 Video Decoder Module

8.1 Overview 8-1

8.2 Postparser Operation 8-4

8.2.1 Sequence Header 8-4

8.2.2 Sequence Extension 8-6

8.2.3 Sequence Display Extension 8-7

8.2.4 Group of Pictures Header 8-8

8.2.5 Picture Header 8-9

8.2.6 Picture Coding Extension 8-11

8.2.7 Quant Matrix Extension 8-13

8.2.8 Host Access of Q Table Entries 8-14

8.2.9 Picture Display Extension 8-15

8.2.10 Copyright Extension 8-17

8.2.11 User Data 8-18

8.2.12 Picture Data 8-18

8.2.13 Unsupported Syntax 8-18

8.2.14 Auxiliary Data FIFO Operation 8-19

8.2.15 User Data FIFO Operation 8-21

vi Contents

8.3 Video Decoder Pacing 8-24

8.3.1 Channel Start/Reset and Status Bits 8-25

8.3.2 Video Decoder Start/Stop 8-26

8.4 Frame Store Modes 8-30

8.4.1 Normal (3-Frame Store) Mode 8-30

8.4.2 Reduced Memory Mode 8-32

8.4.3 Two-Frame Store Mode 8-34

8.4.4 Decode and Display Frame Store Status
Indicators 8-34

8.5 Trick Modes 8-35

8.5.1 Skip Frame 8-35

8.5.2 Repeat Frame 8-38

8.5.3 Channel Buffer Underflow Panic Repeat 8-40

8.5.4 Rip Forward Mode 8-40

8.5.5 Force Broken Link 8-43

8.5.6 Search for Next GOP/Seq Command 8-43

8.5.7 Reconstruction Force Rate Control 8-43

8.5.8 Sequence End Processing 8-46

8.6 Error Handling and Concealment 8-48

8.6.1 Error Conditions Detected 8-49

8.6.2 Recovery Mechanisms 8-49

Chapter 9 Video Interface

9.1 Overview 9-2

9.2 Television Standard Select 9-4

9.3 Display Areas 9-5

9.3.1 Vertical Timing 9-7

9.3.2 Horizontal Timing 9-10

9.4 Video Background Modes 9-12

9.5 Still Image Display 9-13

9.6 Display Modes and Vertical Filtering 9-16

9.7 Reduced Memory Mode 9-19

9.8 Horizontal Postprocessing Filters 9-20

9.9 On-Screen Display 9-23

9.9.1 OSD Modes 9-24

9.9.2 Internal OSD 9-24

9.9.3 External OSD 9-31

Contents vii

9.10 Pan and Scan Operation 9-32

9.10.1 Host Controlled Pan and Scan 9-33

9.10.2 Bitstream Controlled Pan and Scan 9-35

9.10.3 Vertical Pan and Scan 9-35

9.11 Display Freeze 9-36

9.12 Pulldown Operation 9-38

9.13 Video Output Format and Timing 9-39

9.14 Display Controller Interrupts 9-40

Chapter 10 Audio Decoder Module

10.1 Features 10-1

10.2 Audio Decoder Overview 10-2

10.3 Decoding Flow Control 10-6

10.3.1 Audio Decoder Play Mode 10-6

10.3.2 Audio Decoder Start/Stop 10-7

10.3.3 Audio Formatter Play Mode 10-8

10.3.4 Audio Formatter Start/Stop 10-8

10.3.5 Autostart 10-9

10.4 MPEG Audio Decoder 10-10

10.4.1 MPEG Audio Syntax 10-10

10.4.2 MPEG Audio Decoding 10-12

10.5 Linear PCM Audio Decoder 10-14

10.5.1 Packet Header Syntax 10-14

10.5.2 Synchronization 10-16

10.5.3 Other Host Controls and Status 10-18

10.5.4 Sample Decimation for S/P DIF 10-18

10.6 MPEG Formatter 10-19

10.6.1 Number of IEC958 Frames when Formatting
MPEG Data 10-21

10.6.2 Pd Field 10-21

10.6.3 Pause Burst 10-22

10.6.4 Synchronization 10-24

10.6.5 Error Conditions 10-24

10.7 PCM FIFO Mode 10-26

10.8 DAC Interface 10-27

viii Contents

10.9 S/P DIF Interface 10-29

10.9.1 Biphase Mark Coding 10-30

10.9.2 IEC958 Syntax 10-30

10.9.3 IEC958 Channel Status 10-32

10.10 Clock Divider 10-32

Chapter 11 Specifications

11.1 Electrical Requirements 11-1

11.2 AC Timing 11-4

11.3 Pinouts and Packaging 11-18

Appendix A Video/Audio Compression and Decompression Concepts

A.1 Video Compression and Decompression Concepts A-1

A.1.1 Video Encoding A-2
A.1.2 Bitstream Syntax A-5
A.1.3 Video Decoding A-7

A.2 Audio Compression and Decompression Concepts A-7

A.2.1 MPEG Audio Encoding A-8
A.2.2 Audio Decoding A-11

Appendix B Glossary of Terms and Abbreviations

Index

Customer Feedback

Figures

1.1 A Typical L64105 Application 1-2

1.2 L64105 Decoder Block Diagram 1-3

2.1 L64105 I/O Signals 2-2

2.2 PLLVDD Decoupling Circuit 2-11

4.1 Register 0 (0x000) 4-2

4.2 Register 1 (0x001) 4-3

4.3 Register 2 (0x002) 4-5

4.4 Register 3 (0x003) 4-7

Contents ix

4.5 Register 4 (0x004) 4-8

4.6 Register 5 (0x005) 4-9

4.7 Register 6 (0x006) 4-10

4.8 Register 7 (0x007) 4-11

4.9 Registers 9–12 (0x009–0x00C) SCR Value [31:0] 4-13

4.10 Registers 13–16 (0x00D–0x010) SCR
Compare/Capture [31:0] 4-13

4.11 Register 17 (0x011) 4-14

4.12 Register 18 (0x012) 4-15

4.13 Register 19 (0x013) 4-15

4.14 Registers 20–23 (0x014–0x017)
SCR Compare Audio [31:0] 4-16

4.15 Register 28 (0x01C) Video Channel Bypass Data [7:0] 4-16

4.16 Register 29 (0x01D) Audio Channel Bypass Data [7:0] 4-17

4.17 Register 64 (0x040) 4-17

4.18 Register 65 (0x41) 4-18

4.19 Register 66 (0x042) User Data FIFO Output [7:0] 4-19

4.20 Register 67 (0x043) Aux Data FIFO Output [7:0] 4-19

4.21 Register 68 (0x044) 4-20

4.22 Register 69 (0x045) 4-21

4.23 Registers 72 and 73 (0x048 and 0x049)
Video ES Channel Buffer Start Address [13:0] 4-22

4.24 Registers 74 and 75 (0x04A and 0x04B)
Video ES Channel Buffer End Address [13:0] 4-23

4.25 Registers 76 and 77 (0x04C and 0x04D)
Audio ES Channel Buffer Start Address [13:0] 4-23

4.26 Registers 78 and 79 (0x04E and 0x04F)
Audio ES Channel Buffer End Address [13:0] 4-24

4.27 Registers 80 and 81 (0x050 and 0x051)
Video PES Header Channel Buffer Start Address [13:0] 4-24

4.28 Registers 82 and 83 (0x052 and 0x053)
Video PES Header Channel Buffer End Address [13:0] 4-24

4.29 Registers 88 and 89 (0x058 and 0x059)
Audio PES Header/System Channel Buffer
Start Address [13:0] 4-25

4.30 Registers 90 and 91 (0x05A and 0x05B) Audio
PES Header/System Channel Buffer End Address [13:0] 4-25

4.31 Registers 96–98 (0x060–0x062)
Video ES Channel Buffer Write Address [19:0] 4-26

x Contents

4.32 Registers 99–101 (0x063–0x065) Audio
ES Channel Buffer Write Address [19:0] 4-26

4.33 Registers 102–104 (0x066–0x068) Video
PES Header Channel Buffer Write Address [19:0] 4-27

4.34 Registers 108–110 (0x06C–0x06E) Video
ES Channel Buffer Read Address [19:0] 4-27

4.35 Registers 108–110 (0x06C–0x06E) Video
ES Channel Buffer Compare DTS Address [18:0] 4-28

4.36 Registers 111–113 (0x06F–0x071) Audio
ES Channel Buffer Read Address [19:0] 4-28

4.37 Registers 111–113 (0x06F–0x071) Audio
ES Channel Buffer Compare DTS Address [18:0] 4-29

4.38 Registers 114–116 (0x072–0x074) Audio
PES Header/System Channel Buffer Write Address [19:0] 4-29

4.39 Registers 120–122 (0x078–0x07A)
S/P DIF Channel Buffer Read Address [19:0] 4-30

4.40 Register 124 (0x07C) 4-30

4.41 Registers 128–130 (0x080–0x082)
Picture Start Code Read Address [19:0] 4-31

4.42 Registers 131–133 (0x083–0x085)
Audio Sync Code Read Address [19:0] 4-31

4.43 Registers 134–136 (0x086–0x088)
Video ES Channel Buffer Numitems [18:0] 4-32

4.44 Registers 134–136 (0x086–0x088)
Video Numitems/Pics in Channel Compare Panic [18:0] 4-32

4.45 Registers 137–139 (0x089–0x08B)
Audio ES Channel Buffer Numitems [18:0] 4-33

4.46 Registers 140–142 (0x08C–0x08E)
S/P DIF Channel Buffer Numitems [18:0] 4-33

4.47 Register 143 (0x08F) 4-34

4.48 Register 144 (0x090) 4-35

4.49 Register 145 (0x091) 4-35

4.50 Register 147 (0x093) 4-36

4.51 Register 149 (0x094) 4-37

4.52 Registers 150 and 151 (0x096 and 0x097)
Pictures in Video ES Channel Buffer Counter [15:0] 4-38

4.53 Register 192 (0x0C0) 4-38

4.54 Register 193 (0x0C1) 4-39

4.55 Register 194 (0x0C2) Host SDRAM Read Data [7:0] 4-41

Contents xi

4.56 Register 195 (0x0C3) Host SDRAM Write Data [7:0] 4-41

4.57 Registers 196–198 (0x0C4–0x0C6)
Host SDRAM Target Address [18:0] 4-42

4.58 Registers 199–201 (0x0C7–0x0C9)
Host SDRAM Source Address [18:0] 4-42

4.59 Registers 202 and 203 (0x0CA and 0x0CB)
Block Transfer Count [15:0] 4-43

4.60 Register 204 (0x0CC) 4-43

4.61 Register 205 (0x0CD) 4-44

4.62 Register 206 (0x0CE) 4-45

4.63 Registers 207–212 (0x0CF–0x0D4) 4-45

4.64 Registers 213–215 (0xD5–0x0D7)
DMA SDRAM Target Address [18:0] 4-46

4.65 Registers 216–218 (0xD8–0x0DA)
DMA SDRAM Source Address [18:0] 4-46

4.66 Register 219 (0x0DB) DMA SDRAM Read Data [7:0] 4-47

4.67 Register 220 (0x0DC) DMA SDRAM Write Data [7:0] 4-47

4.68 Register 221 (0x0DD) 4-47

4.69 Registers 222 and 223 (0x0DE and 0x0DF)
VCO Test Low Freq [15:8] 4-47

4.70 Registers 224 and 225 (0x0E0 and 0x0E1)
Anchor Luma Frame Store 1 Base Address [15:0] 4-48

4.71 Registers 226 and 227 (0x0E2 and 0x0E3)
Anchor Chroma Frame Store 1 Base Address [15:0] 4-48

4.72 Registers 228 and 229 (0x0E4 and 0x0E5)
Anchor Luma Frame Store 2 Base Address [15:0] 4-48

4.73 Registers 230 and 231 (0x0E6 and 0x0E7)
Anchor Chroma Frame Store 2 Base Address [15:0] 4-49

4.74 Registers 232 and 233 (0x0E8 and 0x0E9)
B Luma Frame Store Base Address [15:0] 4-49

4.75 Registers 234 and 235 (0x0EA and 0x0EB)
B Chroma Frame Store Base Address [15:0] 4-49

4.76 Register 236 (0x0EC) 4-50

4.77 Register 237 (0x0ED) 4-51

4.78 Register 238 (0x0EE) 4-52

4.79 Register 239 (0x0EF) 4-54

4.80 Register 240 (0x0F0) 4-56

4.81 Register 241 (0x0F1) 4-56

4.82 Register 242 (0x0F2) Q Table Entry [7:0] 4-57

xii Contents

4.83 Register 243 and 244 (0x0F3 and 0x0F4)
Microcontroller PC [11:0] 4-57

4.84 Register 245 (0x0F5) Revision Number [7:0] 4-57

4.85 Register 246 (0x0F6) 4-57

4.86 Register 248 (0x0F8) Reduced Memory
Mode (RMM) Bit 4-58

4.87 Register 265 (0x109) 4-58

4.88 Registers 266–268 (0x10A and 0x10C)
Programmable Background Y/Cb/Cr [7:0] 4-60

4.89 Register 269 (0x10D) OSD Palette Write [7:0] 4-60

4.90 Registers 270–273 (0x10E–0x111)
OSD Odd/Even Field Pointers [15:0] 4-61

4.91 Register 274 (0x112) 4-61

4.92 Register 275 (0x113) 4-62

4.93 Register 276 (0x114) 4-63

4.94 Register 277 (0x115) Horizontal Filter Scale [7:0] 4-64

4.95 Register 278 (0x116) 4-65

4.96 Register 279 (0x117) 4-65

4.97 Register 280 (0x118) Horizontal Pan and Scan
Luma/Chroma Word Offset [7:0] 4-66

4.98 Register 281 (0x119) Vertical Pan and Scan
Line Offset [7:0] 4-66

4.99 Register 282 (0x11A) 4-66

4.100 Register 283 (0x11B) 4-67

4.101 Register 284 (0x11C) 4-67

4.102 Registers 285–288 (0x11D–0x120) Display Override
Luma/Chroma Frame Store Start Addresses [15:0] 4-68

4.103 Register 289 (0x121) 4-68

4.104 Register 290 (0x122) 4-69

4.105 Registers 297–299 (0x129–0x12B) Main
Start/End Rows [10:0] 4-70

4.106 Registers 300–302 (0x12C–0x12E) Main
Start/End Columns [10:0] 4-70

4.107 Register 303 (0x12F) 4-70

4.108 Register 304 (0x130) Vcode Even [7:0] 4-71

4.109 Register 305 (0x131) Fcode [7:0] 4-71

4.110 Registers 306–308 (0x132–0x134)
SAV/EAV Start Columns [10:0] 4-72

Contents xiii

4.111 Register 309 (0x135) 4-72

4.112 Register 336 (0x150) 4-72

4.113 Register 337 (0x151) 4-74

4.114 Register 338 (0x152) 4-76

4.115 Register 351 (0x15F) 4-77

4.116 Register 352 (0x160) 4-77

4.117 Register 353 (0x161) 4-77

4.118 Register 354 (0x162) 4-78

4.119 Register 355 (0x163) 4-79

4.120 Register 356 (0x164) 4-80

4.121 Register 357 (0x165) 4-81

4.122 Register 358 (0x166) 4-82

4.123 Register 359 (0x167) PCM FIFO Data In [7:0] 4-83

4.124 Register 360 (0x168) Linear PCM - dynscalehigh [7:0] 4-83

4.125 Register 361 (0x169) Linear PCM - dynscalelow [7:0] 4-83

4.126 Register 362 (0x16A) PCM Scale [7:0] 4-84

4.127 Register 363 (0x16B) 4-84

4.128 Register 364 (0x16C) 4-85

4.129 Register 365 (0x16D) 4-87

4.130 Register 366 (0x16E) 4-88

4.131 Register 367 (0x16F) Host Category [7:0] 4-89

4.132 Register 368 (0x170) 4-90

4.133 Registers 369 and 370 (0x171 and 0x172)
Host Pd Value [15:0] 4-91

4.134 Registers 384 and 385 (0x180 and 0x181)
Memory Test Address [11:0] 4-91

4.135 Register 386 (0x182) 4-91

4.136 Registers 387–392 (0x183–0x188) Memory
Test Pass/Fail Status Bits 4-93

5.1 Host Interface Block Diagram 5-2

5.2 Motorola Mode Write Timing 5-3

5.3 Motorola Mode Read Timing 5-4

5.4 Intel Mode Write Timing 5-5

5.5 Intel Mode Read Timing 5-5

5.6 Operation of the SCR Counter 5-7

5.7 Interrupt Structure 5-9

5.8 Host Read/Write Flowchart 5-13

5.9 DMA SDRAM Read/Write Flowchart 5-17

xiv Contents

5.10 Block Move Flowchart 5-19

6.1 Channel Interface Block Diagram 6-3

6.2 Asynchronous Channel Interface Timing 6-4

6.3 xVALIDn Input Synchronization Circuits 6-6

6.4 Synchronous Valid Signals Timing 6-6

6.5 L64105 A/VREQn Circuits 6-7

6.6 Elementary Stream Buffering 6-13

6.7 PES Packet Structure 6-15

6.8 Preparsing an MPEG-1 System Stream 6-16

6.9 System PES Channel Buffer Map for MPEG-1 Streams 6-17

6.10 System Channel Buffer Map for Program Streams 6-19

6.11 Audio ES Channel Buffer Map for Linear PCM Audio 6-20

6.12 Audio ES Channel Buffer Map for MPEG Audio 6-21

6.13 Video ES Channel Buffer Map 6-21

6.14 Parsing an Audio/Video PES Transport Stream 6-24

6.15 MPEG-1/MPEG-2 Channel Interface Operation 6-30

6.16 A/V PES Mode Channel Interface Operation 6-31

7.1 Memory Interface Block Diagram 7-2

7.2 SDRAM Timing Requirements for Reads 7-4

7.3 SDRAM Timing Requirements for Writes 7-5

7.4 SDRAM Timing Requirements for Refresh 7-5

7.5 Luma Frame Store Organization 7-9

7.6 Chroma Frame Store Organization 7-10

8.1 Video Decoder Block Diagram 8-3

8.2 Time Line for Frame Picture 8-28

8.3 Time Line for Field Picture 8-29

8.4 Frame Store Organization in Normal Mode 8-31

8.5 Single Skip with and without Display Freeze 8-37

8.6 Frame Repeat Modes 8-39

8.7 Setting Up Rip Forward/Display Override Command 8-42

8.8 Automatic Rate Control 8-45

8.9 Using Force Rate Control in Rip Forward Mode 8-46

8.10 Example of Sequence End Processing 8-47

9.1 Video Interface Block Diagram 9-3

9.2 Display Areas Example 9-6

9.3 Vertical Timing Vcodes and Fcodes for NTSC 9-8

9.4 Vertical Timing Vcodes and Fcodes for PAL 9-9

9.5 Sync Input Timing 9-10

Contents xv

9.6 Horizontal Input Timing 9-11

9.7 Horizontal Timing for 8-Bit Digital Transmission for NTSC 9-12

9.8 Luma and Chroma Frame Store Format 9-14

9.9 Frequency Response A 9-21

9.10 Impulse Response A 9-21

9.11 Frequency Response B 9-22

9.12 Impulse Response B 9-22

9.13 OSD Area Data Organization 9-25

9.14 OSD Header Control Fields 9-26

9.15 OSD Header Color Fields 9-27

9.16 OSD Storage Formats 9-29

9.17 Horizontal Pan and Scan Calculation 9-35

9.18 Freeze Operation Timing 9-37

9.19 Pulldown Operation Timing 9-39

9.20 Video and Control Output Timing 9-40

10.1 L64105 Audio Decoder Block Diagram 10-4

10.2 MPEG Audio Bitstream Syntax 10-11

10.3 MPEG Audio Decoding Flow 10-13

10.4 Linear PCM Packet Syntax 10-14

10.5 Linear PCM Audio Sample Syntax 10-16

10.6 Linear PCM Output Ports 10-19

10.7 Syntax of the MPEG Data in IEC958 Format 10-20

10.8 Length of Burst Payload 10-21

10.9 Inserting Pause Bursts in the MPEG Formatter Output 10-23

10.10 DAC Output Mode: PCM Sample Precision = 16 Bit 10-27

10.11 DAC Output Mode: PCM Sample Precision = 20 Bit 10-28

10.12 DAC Output Mode: PCM Sample Precision = 24 Bit 10-28

10.13 IEC958 Biphase Mark Representation 10-30

10.14 IEC958 Syntax 10-31

10.15 IEC958 Channel Status 10-32

11.1 AC Test Load and Waveform for Standard Outputs 11-4

11.2 AC Test Load and Waveform for 3-State Outputs 11-5

11.3 SDRAM Read Cycle 11-7

11.4 SDRAM Write Cycle 11-8

11.5 Host Write Timing (Motorola Mode) 11-10

11.6 Host Read Timing (Motorola Mode) 11-11

11.7 Host Write Timing (Intel Mode) 11-13

11.8 Host Read Timing (Intel Mode) 11-13

xvi Contents

11.9 Asynchronous Channel Write Timing 11-14

11.10 Synchronous AVALIDn/VVALIDn Signals Timing 11-15

11.11 Reset Timing 11-15

11.12 Video Interface Timing 11-16

11.13 Serial PCM Data Out Timing 11-17

11.14 A_ACLK Timing 11-17

11.15 PREQn Timing 11-18

11.16 160-Pin Package Pinout 11-25

11.17 160-Pin PQFP (PZ) Mechanical Drawing (Sheet 1 of 2) 11-26

A.1 MPEG Macroblock Structure A-3
A.2 Typical Sequence of Pictures in Display Order A-6
A.3 Typical Sequence of Pictures in Bitstream Order A-6
A.4 Audio Encoding Process (Simplified) A-8
A.5 ISO System Stream A-9
A.6 MPEG Audio Packet Structure A-9

Tables

3.1 L64105 Register Groupings 3-1

3.2 Host Interface Registers 3-2

3.3 Video Decoder Registers 3-7

3.4 Memory Interface Registers 3-14

3.5 Microcontroller Registers 3-17

3.6 Video Interface Registers 3-20

3.7 Audio Decoder Registers 3-24

3.8 RAM Test Registers 3-27

4.1 Display Mode Selection Table 4-64

4.2 MPEG Bitrate Index Table 4-73

4.3 Audio Decoder Modes 4-81

4.4 ACLK Divider Select [3:0] Code Definitions 4-86

5.1 Host Interface Signals 5-2

5.2 SCR Compare/Capture Mode Bits 5-6

5.3 DMA Mode Bits 5-14

6.1 Levels of Hierarchy in MPEG-1 and MPEG-2
System Syntax 6-2

6.2 Video Stream Select Enable Bits 6-9

6.3 Audio Stream Select Enable Bits 6-10

6.4 Pack Header Enable Bits 6-11

Contents xvii

6.5 System Header Enable Bits 6-11

6.6 Video PES Header Enable Bits 6-12

6.7 Audio PES Header Enable Bits 6-12

6.8 Buffer Start and End Address Registers for ES Mode 6-13

6.9 Buffer Write and Read Pointer Registers in ES Mode 6-14

6.10 Number of Items in Buffers in ES Mode 6-14

6.11 SDRAM Addresses - Audio PES Header/System
Channel Buffer 6-18

6.12 Video PES Header Channel Buffer Registers 6-25

6.13 Compare DTS Register Bits and Fields 6-28

6.14 Video Channel Underflow Control Registers 6-29

7.1 NEC’s 16 Mbit Synchronous DRAM (Burst Length = 2) 7-4

7.2 Example NTSC SDRAM Allocation 7-6

7.3 Channel Buffer Architectures 7-8

7.4 Example NTSC SDRAM Allocation with Frame Store
(720 x 480) 7-12

8.1 Sequence Header Processing 8-4

8.2 Sequence Extension Processing 8-6

8.3 Sequence Display Extension Processing 8-7

8.4 Group Of Pictures Header Processing 8-8

8.5 Picture Header Processing 8-9

8.6 Picture Coding Extension Processing 8-11

8.7 Quant Matrix Extension Processing 8-13

8.8 Picture Display Extension Processing 8-15

8.9 Number of Frame Center Offsets 8-16

8.10 Copyright Extension Processing 8-17

8.11 All User Data Processing 8-18

8.12 Aux Data FIFO Registers 8-19

8.13 Aux Data FIFO Status 8-20

8.14 Auxiliary Data Layer ID Assignments 8-21

8.15 User Data FIFO Registers 8-22

8.16 User Data FIFO Status 8-22

8.17 User Data Layer ID Assignments 8-24

8.18 Frame Store Base Address Registers 8-32

8.19 Current Decode/Display Frame Bits Coding 8-34

8.20 Video Skip Frame Modes 8-35

9.1 Television Standard Select Field 9-4

9.2 Television Standard Select Default Values 9-5

xviii Contents

9.3 Force Video Background Selections 9-12

9.4 Override Display Registers 9-14

9.5 Display Mode Selection Table 9-17

9.6 Raster Mapper Increment Value by Source Resolution 9-23

9.7 OSD Modes 9-24

9.8 High Color Modes 9-26

9.9 Host Controlled Pan and Scan Registers 9-33

9.10 Freeze Modes 9-36

10.1 Audio Decoder Modes 10-3

10.2 Audio Autostart Registers 10-9

10.3 Valid Linear PCM Stream Permutations 10-15

10.4 MPEG Formatter Data Burst Preamble Syntax 10-20

10.5 IEC958 Frame Sizes Supported in MPEG
Audio Formatter 10-21

10.6 Pd Selection 10-22

10.7 MPEG Formatter Pause Burst Syntax 10-23

10.8 MPEG Audio Formatter Error Handling 10-25

10.9 PCM FIFO Mode Registers 10-26

10.10 IEC958 Subframe Preambles 10-31

10.11 ACLK Divider Select [3:0] Code Definitions 10-34

11.1 Absolute Maximum Ratings 11-2

11.2 Recommended Operating Conditions 11-2

11.3 Capacitance 11-2

11.4 DC Characteristics 11-3

11.5 SDRAM Interface AC Timing 11-6

11.6 Host Interface AC Timing (Motorola Mode) 11-9

11.7 Host Interface AC Timing (Intel Mode) 11-12

11.8 Asynchronous Channel Write AC Timing 11-14

11.9 Synchronous AVALIDn/VVALIDn Signals AC Timing 11-14

11.10 Video Interface AC Timing 11-16

11.11 Audio Interface AC Timing 11-17

11.12 Alphabetical Pin Summary 11-18

A.1 MPEG Compressed Bitstream Syntax A-5

Preface xix

Preface

This book is the primary reference and Technical Manual for the L64105
MPEG-2 Audio/Video Decoder. It contains functional descriptions, I/O
signal and register descriptions, and includes complete physical and
electrical specifications for the L64105.

Audience

This document assumes that you have some familiarity with ISO/IEC
13818,

Generic Coding of Moving Pictures and Associated Audio

(MPEG-2), microprocessors, and related support devices. The people
who benefit from this book are:

♦ Engineersand managers who are evaluating the L64105 for possible

use in a system

♦ Engineers who are designing the L64105 into a system

Organization

This document has the following chapters and appendixes:

♦ Chapter1, Introduction includes an overview of the L64105

Decoder and lists its features.

♦ Chapter2, I/O Signal Descriptions describes the input/output

signals of the L64105.

♦ Chapter3, Register Summary summarizes all of the registers of the

L64105 in tabular form with page references to their descriptions in
Chapter 4.

♦ Chapter4, Register Descriptions identifies and describes all of the

register bits and fields of the L64105 accessible from the host
processor.

xx Preface

♦ Chapter5, Host Interface describes the host interface to the L64105

and to external SDRAM connected to the L64105.

♦ Chapter6, Channel Interface describes the processing of the

audio/video bitstream as it comes into the L64105 and the various
methods which the L64105 uses to handle and recover from input
stream errors.

♦ Chapter7, Memory Interface describes the SDRAM configurations

required by the L64105 and its interface to those memories.

♦ Chapter8, Video Decoder Module describes how the video

decoder portion of the L64105 supports MPEG-2 Main Profile and
Main Level decoding and MPEG-1 Simple Profile and Main Level
decoding.

♦ Chapter9, Video Interface describes how video is displayed from

decoded frame stores. Also describes the features and operation of
the Display Controller and how to program it for proper operation.
Includes an overview of the vertical and horizontal post-processing
filters.

♦ Chapter10, Audio Decoder Module describes how the L64105

processes Linear PCM and MPEG (MUSICAM) input audio streams.

♦ Chapter11, Specifications includes the electrical requirements for,

AC timing characteristics of, and a pin summary for the L64105. Also
contains the pin listing and package outline drawing for the 160-pin
PQFP.

♦ AppendixA, Video/Audio Compression and Decompression

Concepts

♦ AppendixB, Glossary of Terms and Abbreviations

Related Publications

L64108 MPEG-2 Transport with Embedded MIPS CPU (CW4001) and
Control Chip Technical Manual

, LSI Logic Corporation, DB14-000039-00.

ISO/IEC 13818,

Generic Coding of Moving Pictures and Associated

Audio

(MPEG-2), International Standard.ISO/IEC Copyright Office, Case

Postal 56, CH1211 Genève 20, Switzerland.
ISO/IEC 11172 (1993),

Information Technology—Coding of Moving

Picture and Associated Audio for Digital Storage Media at up to about

Preface xxi

1.5 Mbit/s

(MPEG-1), International Standard.ISO/IEC Copyright Office,

Case Postal 56, CH1211 Genève 20, Switzerland.

ITU-R BT.601-5 (10/95), Studio Encoding Parameters of Digital
Television for Standard 4:3 and Wide-screen 16:9 Aspect Ratios

,

http://www.itu.ch/publications/itu-r/iturbt.htm.

ITU-R BT.656-3(10/95), Interface for Digital Component Video Signals in
525-line and 625-line Television Systems Operating at the 4:2:2 Level of
Recommendation ITU-R BT.601 (Part A)

,

http://www.itu.ch/publications/itu-r/iturbt.htm.

Conventions Used in This Manual

Unless otherwise specified,

MPEG

refers to the MPEG-2 standard.

MSB

indicates the most-significant bit or byte.

LSB

indicates the least­significant bit or byte. If bit or byte is not obvious in the context, the term
is spelled out.

The first time a word or phrase is defined in this manual, it is

italicized.

The word set means to change a bit to the logic 1 state. The word clear
means to change a bit to the logic 0 state.

The word

assert

means to drive a signal true or active. The word

deassert

means to drive a signal false or inactive. Signals that are active

LOW end in an “n.”
Hexadecimal numbers are indicated by the prefix “0x” before the

number—for example, 0x32CF. Binary numbers are indicated by the
prefix “0b” before the number—for example, 0b0011.0010.1100.1111.

xxii Preface

1-1

Chapter 1
Introduction

This chapter provides general overview information on the L64105
MPEG-2 Audio/Video Decoder chip. The chapter contains the following
sections:

♦ Section 1.1, “An L64105 Application,” page 1-1
♦ Section 1.2, “L64105 Overview,” page 1-2
♦ Section 1.3, “Features,” page 1-6

1.1 An L64105 Application

Figure 1.1 illustrates the L64105 in a typical set top box application. The

L64105 is specifically designed for use in digital audio and video
MPEG-2 decoding systems based on the MPEG-2 algorithm. The device
may be considered a “black box” that receives coded audio and video
data and produces decoded audio and video data streams. LSI Logic has
optimized the L64105 input/output interfaces for low-cost integration into
embedded applications.

The L64105 is a member of a family of pin and software compatible,
advanced, MPEG-2 A/V decoders. The L64020 DVD Audio/Video
Decoder adds DVD and Dolby Digital audio decoding features.

1-2 Introduction

Figure 1.1 A Typical L64105 Application

The L64105 accepts an 8-bit, parallel channel input from a transport
demultiplexer and, with interaction of a host microcontroller,
decompresses and decodes the channel information into separate, serial
video and audio streams. The L64105 handles NTSC and PAL formats
and provides a Sony/Philips Digital Interface (S/P DIF) formatted output
stream.

1.2 L64105 Overview

Figure 1.2 shows a block diagram of the L64105. Its major blocks include

the:

♦ Host Interface
♦ Channel Interface
♦ Memory Interface
♦ Video Decoder
♦ Video Interface
♦ Audio Decoder

The Host Interface includes 512, 8-bit registers (some not used), read
and write FIFOs, and byte enable logic. The host and L64105
communicate with each other exclusively through the registers. An
external interrupt signal from the L64105 alerts the host about internal
events, such as picture start code detection. Separate I/O signals are
used for handshaking. The L64105 can interface with either an Intel or
Motorola type processor by tying an external pin high or low.

L64105

NTSC/PAL

Encoder

Audio
DACs

16 Mbit
SDRAM

Baseband

Video

Stereo

Audio

Decoder

MPEG-2

A/V

L64X08

Integrated

X-PORT

CPU

L647X4

QPSK

Demod

L64768

QAM

Demod

Or

4 Mbit
DRAM

Satellite in

Cable in

Optional
16 Mbit SDRAM

L64X08 EBUS

S/P DIF

L64105 Overview 1-3

Figure 1.2 L64105 Decoder Block Diagram

The read and write FIFOs are used to give the host access to the
external SDRAM. The read/write paths are still through registers. The
interface supports direct read/write, DMA transfers using an external
DMA controller, and block moves within SDRAM. The byte enable logic
converts host byte writes to 8-byte words for the write FIFO and 64-bit
internal bus and vice versa. The byte enable logic also performs byte
switching for little endian hosts.

The Channel Interface accepts byte-wide MPEG streams and a clock.
The interface synchronizes to and preparses the incoming stream by
stripping system headers and storing them in a dedicated buffer area in
SDRAM. The interface also separates the audio and video streams and
stores them in dedicated buffer areas in SDRAM. A buffer controller
maintains the read and write pointers for the dedicated buffers.

The Memory Interface includes byte enable logic and an address
converter. The recommended SDRAM is 16 bits wide, so the byte enable
logic performs the conversion between the SDRAM bus and the 8-byte
wide internal bus of the L64105. The host and internal microcontroller of

Host

Microcontroller

DCK (£ 9 MHz)

L64105 Decoder

Interface

Video

Decoder

Video

Interface

SDRAM Buffers and

Frame Stores

Audio

Video to

I/O
Control

NTSC/PAL
Encoder

Audio
Clocks

to DAC
Oversampling

S/P DIF
Out

Status

Control

Decoder

CH_DATA[7:0]

Data

Address

Buses

Memory

Interface

Channel
Interface

and

and

and

Clock In

SYSCLK
(27 MHz)

64-bit

Address Bus

Data Bus

1-4 Introduction

the L64105 address SDRAM as if it were 8-byte wide RAM. The address
converter changes these addresses to chip selects, bank selects, and
column and row addresses for the SDRAM.

The Video Decoder reads the MPEG video elementary stream from the
SDRAM buffer, performs postparsing on it, decompresses it, decodes it,
and stores it back in SDRAM. The postparser strips off all header
information and stores it in internal memory for use in the decoding
process. The postparser also strips auxiliary and user data from the
stream and stores it in FIFOs that can be read through registers by the
host. The decompressed and decoded video is stored back in SDRAM
in frame form.

The Video Interface reads the video frames from frame stores in
SDRAM, synchronizes them to the vertical and horizontal sync signals
from the NTSC/PAL Encoder, and mixes in On-Screen Display (OSD)
information. The interface performs letterboxing, 3:2 pulldown, and pan
and scan. It also handles trick modes such as pause, slow play, fast
forward, etc.

The Audio Decoder contains an MPEG (Musicam) Decoder, Linear PCM
Decoder, MPEG Formatter, Audio DAC Interface, and an S/P DIF
(IEC958) Interface. The decoders decompress and decode the audio
stream. The decoder outputs can be steered to the DAC or S/P DIF
Interface. The formatter converts the encoded and compressed streams
to S/P DIF format for the S/P DIF Interface. The host controls the mode
of the Audio Decoder; that is, it determines which decoder runs and
where its output goes, and which formatter runs. The host can also place
the Audio Decoder in the bypass mode and connect inputs from another
device directly to the L64105 audio outputs.

The microcontroller is shown on the block diagram since it controls most
of the processes of the L64105.

L64105 Overview 1-5

The L64105 is an MPEG-2 Main Level, Main Profile decoder. It handles
image sizes up to 720 x 480 pixels with a frame rate of 30 fps for NTSC
and up to 720 x 576 pixels at 25 fps for PAL. It can also decode MPEG-1
sequences. The coded data channel may have a sustained bit rate of up
to 20 Mbits/second. As the resolution decreases, the amount and
bandwidth of SDRAM memory required for frame stores also decreases.

1.2.1 Memory Utilization

The L64105 supports direct connection to commercial SDRAM for use
as frame stores, channel buffers, and overlay memory. The L64105 uses
frame stores for frame reconstruction and display, separate video and
audio channel buffers for rate matching, and zero or more regions for
graphical overlay. This storage is combined into a single contiguous
memory space accessed over a 16-bit wide bus. In most cases this will
be one 1 M x 16-bit SDRAM, for a total memory space of 2 Mbytes. The
interface between the L64105 and SDRAM requires no external
components. The L64105 pinout allows the connection to SDRAM to be
made on a single PCB layer. During normal operation, the L64105
exclusively controls the SDRAM frame stores. However, it is possible to
access the SDRAM through the host port on the L64105 for test
verification and for access to the overlay stores and channel information.

1.2.2 Error Concealment

The L64105 detects data in the bitstream that does not meet MPEG-2
syntax or grammar rules and can flag the data for exception processing.
Hardware error handling is limited to error masking and the application
of concealment vectors in video. Audio error concealment is limited to
muting on errors and searching for error-free frames. The L64105 flags
gross errors in the bitstream due to channel buffer overrun or underrun
or to nonconformance in the bitstream. The L64105 flags the errors so
that they may be masked in the video or the audio output. The host
microcontroller may be programmed to execute mechanisms to recover
from gross errors.

1-6 Introduction

1.3 Features

Video Decoder –

♦ Fully compliant to Main Profile at Main Level of the MPEG-2 video

standard, ISO 13818-2.

♦ Decodes an MPEG-2 bitstream, including MPEG-2 Program stream,

with private stream support.

♦ Decodesan MPEG-1 bitstream as defined in ISO IS 11172, including

the MPEG-1 system layer.

♦ Operates at image sizes up to ITU-R BT.601 resolution (720 x

480 pixels @ 30 fps for NTSC and 720 x 576 @ 25 fps for PAL).

♦ Up to 20 Mbps sustained input channel data rate for program

streams and A/V PES streams from a transport demultiplexer.

♦ 8-bit parallel dedicated input channel interface.
♦ 8-bit luma/chroma output.
♦ Complete on-chip channel buffer controller and display buffer

controls.

♦ Error concealment maintains display of images during channel

errors.

Video Interface –

♦ Integrates a flexible 256-color, On-Screen Display (OSD) controller.
♦ Allows connection to an external OSD generator.
♦ Programmable display management.
♦ Slave video timing operation.
♦ Integrates postprocessing filters for image resizing (horizontal and

vertical).

♦ Integrates vertical filter for letterbox format display.
♦ Implements 3:2 pulldown.
♦ Supports pan and scan with 1/8-pixel accuracy.
♦ Supports 4:2:0 to 4:2:2 sampling filters.

Features 1-7

Audio Decoder –

♦ Processes MPEG audio with support for Linear PCM data.
♦ Decodes dual-channel MPEG audio, Layer I and II ISO 13818-2,

supporting bit rates of 8 Kbps to 448 Kbps and sampling rates of 16,

22.05, 24, 32, 44.1, and 48 kHz.

♦ Supports Linear PCM streams with sample rates of 48 kHz and

96 kHz at 24-bit resolution.

♦ IEC958 output interface for audio data bitstreams.
♦ Mute on error for concealment.
♦ Provides an audio “Bypass” mode for interface to a CD audio

decoder.

System –

♦ Programmable preparser accepts PES, ES, and PS streams.
♦ Direct connection to commodity SDRAM.
♦ Input/output interfaces are optimized for glueless integration into

consumer video systems.

♦ Operates from a single 27-MHz clock with an additional audio

sample clock input.

♦ Total external memory required for audio and video decoding is

16-Mbit SDRAM for ITU-R BT.601-5 resolution.

♦ Interfaces to Intel and Motorola (and compatible) 8-bit

microcontrollers for initialization, testing, and status monitoring.

♦ Direct interface to off-the-shelf NTSC/PAL video encoders.
♦ Direct interface to off-the-shelf audio stereo DACs.
♦ Available in a 160-pin, PQFP pack.
♦ Low power 3.3-Volt process.
♦ TTL-compatible I/O pins.

1-8 Introduction

2-1

Chapter 2
I/O Signal Descriptions

This chapter describes the input/output signals of the L64105. The
chapter contains the following sections:

♦ Section 2.1, “Signals Organization,” page 2-1
♦ Section 2.2, “Host Interface,” page 2-3
♦ Section 2.3, “Channel Interface,” page 2-5
♦ Section 2.4, “Memory Interface,” page 2-7
♦ Section 2.5, “Video Interface,” page 2-8
♦ Section 2.6, “Audio Interface,” page 2-9
♦ Section 2.7, “Miscellaneous and Test Interfaces,” page 2-11

2.1 Signals Organization

The L64105 has six major interfaces:

♦ Host (8-bit microcontroller interface)
♦ Channel (8-bit synchronous or asynchronous bitstream data

channel)

♦ Memory (16-bit synchronous SDRAM interface)
♦ Video (8-bit multiplexed digital video output)
♦ Audio (serial digital audio output)
♦ Test

Figure 2.1 shows the signals, their grouping, and their I/O direction. A

lower case “n” at the end of a signal name indicates that it is an active
LOW signal.

2-2 I/O Signal Descriptions

Figure 2.1 L64105 I/O Signals

Host

Channel

Memory

Video

Audio

A[8:0]

D[7:0]

CH_DATA[7:0]

AREQn

VREQ

AVALIDn
VVALIDn

ERRORn

DCK

L64105

BUSMODE

ASn

CSn

DSn/WRITEn

READ/READn

DTACKn/RDYn

WAITn

INTRn

DREQn

Interface

Interface

PD[7:0]
CREF

BLANK
OSD_ACTIVE

EXT_OSD[3:0]
HS
VS

ASDATA
BCLK
LRCLK

A_ACLK

PREQn

AUDIO_SYNCn
ACLK_32
ACLK_441
ACLK_48
SPDIF_IN
SPDIF_OUT

Interface

Interface

Interface

SCSn

SCS1n

SDQM

SBA[11:0]

SCASn
SRASn

SBD[15:0]

SWEn

SCLK

PLLVDD
PLLVSS
RESETn
SYSCLK
TM[1:0]
ZTEST

SCAN_TE

Miscellaneous and
Test Interface

CD_ASDATA
CD_BCLK
CD_LRCLK
CD_ACLK

Host Interface 2-3

2.2 Host Interface

BUSMODE Host Controller Select Pin Input

This pin must be tied to VSS if the host CPU is an Intel
processor or to VDD if it is a Motorola processor. The
Intel processor uses two separate pins, READn and
WRITEn, for read and write transfers. The Motorola
processor uses a single read/write signal, READ.

CSn Chip Select Input

This active-LOW signal indicates an attempt by an
external host CPU to access the L64105 either for a read
or a write bus cycle. CSn must be asserted for the entire
read/write cycle and may held LOW for more than one
bus transaction.

A[8:0] Address Input

Nine-bit address input selects one of 512 internal
registers. The address value on these lines is latched on
the falling edge of READn in a read cycle and on the
falling edge of WRITEn in a write cycle in Intel mode.
Motorola mode uses a separate address strobe, ASn.

ASn Address Strobe Input

Active-LOW address strobe input. This signal is used in
Motorola mode to latch the address.

D[7:0] Host Data Bus Bidirectional

The host uses the D[7:0] bidirectional data bus to
program the L64105 and access status and bitstream
information during operation. During a read bus cycle,
D[7:0] carries valid information from an internal L64105
register. DTACKn/RDYn or WAITn indicate when the data
on the bus is valid. In write cycles, the data is latched by
the L64105 on the rising edge of DSn/WRITEn.

DSn/WRITEn Data Strobe/Write Indicator Input

DSn - Motorola Mode
DSn indicates when the host strobes the data in or out of
the L64105. Read transactions start when DSn, CSn, and
ASn are all LOW. During a write cycle, the L64105
latches the data on the bus on the rising edge of DSn.

2-4 I/O Signal Descriptions

WRITEn - Intel Mode
The external host asserts WRITEn to start a write cycle.
READn must be HIGH during a write cycle, and CSn
must be LOW during a write cycle. The address is
registered on the falling edge of WRITEn. The data is
latched by the L64105 on the rising edge of WRITEn.

READ/READn Read/Write Strobe - Read Indicator Input

READ - Motorola Mode
The Motorola host asserts READ HIGH for a read cycle
and deasserts it for a write cycle. CSn must be asserted
to select the L64105.

READn - Intel Mode
The Intel host asserts READn and holds WRITEn
deasserted to perform a read cycle. The address is
registered on the falling edge of READn. CSn must be
asserted to select the L64105.

DTACKn/RDYn

Data Acknowledge/Data Ready 3-State Output

DTACKn - Motorola Mode
The L64105 asserts this signal to indicate to the external
host that the current bus transaction (read or write) can
be completed. DTACKnis 3-stated if CSn is not asserted.
The bus cycle is terminated if the L64105 deasserts
DTACKn before the cycle is completed.

RDYn - Intel Mode
The L64105 asserts this signal to indicate to the external
host that the current bus transaction (read or write) can
be completed. RDYn is 3-stated if CSn is not asserted.
The bus cycle is terminated if the L64105 deasserts
RDYn before the cycle is completed.

WAITn Wait 3-State Output

This signal may be used instead of DTACKn/RDYn by
hosts that require an inverted sense. The L64105 asserts
WAITn to indicate that its Host Interface is busy with a
read or write bus cycle and it deasserts it when the
current cycle is completed. WAITn is 3-stated when CSn
is not active.

INTRn Interrupt OD Output

INTRn is an active-LOW, open-drain, output signal. The
L64105 asserts this signal to alert the host that an

Channel Interface 2-5

unmasked interrupt condition has occurred in the chip.
The host must read registers 0 through 4 to determine
the cause of the interrupt, take the appropriate action,
and set the Clear Interrupt Pin bit in Register 6
(page 4-10) to deassert INTRn.

DREQn DMA Transfer Request Output

The L64105 asserts this signal when it is ready to receive
a new byte of data from or transmit a new byte of data to
an external DMA controller. The state of DREQn reflects
the condition of internal read and write FIFOs. For DMA
write cycles, DREQn is deasserted when the write FIFO
is not near full (more than one space left) and deasserted
when the FIFO is near full (one space left). For read
cycles, DREQn is asserted when the read FIFO is not
near empty (more than one space filled) and deasserted
when the FIFO is near empty (one space filled). The
maximum transfer rate over this interface is 20 Mbps in
worst case conditions. The peak data rate may increase
above this depending on system SDRAM usage.

PREQn PCM FIFO Request Output

The L64105 asserts this signal when it is ready to receive
a new byte of data in the PCM FIFO, i.e., when the FIFO
is not near full (less than 25 bytes unread). The PCM
FIFO allows the host to send Linear PCM audio samples
to the Audio Decoder in the L64105. PREQn can be used
as a request signal to an external DMA controller.

2.3 Channel Interface

AREQn Audio Transfer Request Output

The L64105 asserts AREQn when it is ready to receive
a new byte of coded audio data in A/V PES stream mode
(from a transport stream demultiplexer) or a new byte of
any data in program stream modes. The decoder is ready
when the channel input FIFO is not near full.

VREQn Video Transfer Request Output

The L64105 asserts VREQn when it is ready to receive
a new byte of coded audio data in A/V PES stream mode
(from a transport stream demultiplexer). The decoder is
ready when the channel input FIFO is not near full.
VREQn is not used in program stream modes.

2-6 I/O Signal Descriptions

CH_DATA[7:0] Channel Data Bus Input

The CH_DATA bus is used to transfer 8-bit, parallel
bitstreams into the L64105. The maximum transfer rate
over this interface is 20 Mbps in worst case conditions.
The peak data rate may increase above this rate
depending on system SDRAM usage.

AVALIDn Audio Data Valid Input

The channel device asserts this signal in response to
AREQn when the data byte it placed on the CH_DATA
bus is valid. The L64105 transfers the byte in when
AVALIDn is deasserted. This signal can be used with the
DCK input for synchronous transfers.

VVALIDn Video Data Valid Input

The channel device asserts this signal in response to
VREQn when the data byte it placed on the CH_DATA
bus is valid. The L64105 transfers the byte in when
VREQn is deasserted. This signal can be used with the
DCK input for synchronous transfers. This signal is used
only in the A/V PES stream mode when the channel input
is a program from a transport stream demultiplexer. Use
the AVALIDn signal for all data bytes in program stream
modes.

ERRORn Bitstream Error Input

ERRORn is asserted by the channel device to signal
uncorrectable errors in the bitstream and is used by the
L64105 to invoke error handling routines. It is latched by
the L64105 on the rising edge of AVALIDn or VVALIDn.

DCK Channel Clock Input

The DCK is a free-running clock from the external
channel device. It must have a period ≥ 3 x that of
SYSCLK (27 MHz). DCK, together with the AVALIDn and
VVALIDn signals, is used to write data synchronously to
the L64105 channel input.

Memory Interface 2-7

2.4 Memory Interface

Important: The length of all connections between the L64105 and

SDRAM on a PCB layout must be kept as short as
possible, must be matched in length and pin load, and the
pin load should be less than 50 pF.

SCSn SDRAM Chip Select Output

The host asserts this signal to select the low address
SDRAM chip, the first 2 Mbytes of memory. The
recommended SDRAM size for the L64105 is:

SCS1n Second SDRAM Chip Select Output

The host asserts this signal to select the high address
SDRAM chip in systems that have more than
2 Mbytes of memory. The high address SDRAM chip
must have the same page size as the low address
SDRAM chip but does not have to have the same number
of pages.

SDQM SDRAM Control Pin Output

SDQM is an active HIGH output signal for the SDRAM
data control mask.

SBA[11:0] SDRAM Address Bus Output

The row/column multiplexed address bus for SDRAM
memory. The L64105’s microcontroller and the host
address SDRAM as if it were RAM. The Memory
Interface converts these addresses to SDRAM format.

SCASn SDRAM Column Address Select Output

The Memory Interface asserts this signal when the
SDRAM column address is on SBA[11:0].

SRASn SDRAM Row Address Select Output

The Memory Interface asserts this signal when the
SDRAM row address is on SBA[11:0].

SBD[15:0] SDRAM Data Bus Bidirectional

This 16-bit bidirectional data bus is directly connected to
1M x 16 SDRAM(s) for buffering channel data and
reconstructed pictures.

2048 512 16 bits××

2-8 I/O Signal Descriptions

SWEn SDRAM Write Enable Output

The Memory Interface asserts SWEn for SDRAM write
cycles and holds it deasserted for SDRAM read cycles.

SCLK SDRAM 81-MHz Clock Output

The 27-MHz SYSCLK input is multiplied by three using
the on-chip PLL to generate the 81-MHz SCLK.

Important: SCLK should be connected through a 33-Ω terminating

resistor mounted as close as possible to the SCLK pin of
the L64105.

2.5 Video Interface

PD[7:0] Pixel Data Output Bus Output

The PD[7:0] bus carries the pixel data for the
reconstructed pictures. The pixel data is formatted in
ITU_R BT.601 Y, Cb, Cr chromaticity.

CREF Chroma Reference Output

The Video Interface asserts CREF when the Cb
component of Chroma is on PD[7:0] and deasserts it at
all other times.

BLANK Blank Output

BLANK is a composite blank output from the L64105
display controller. Its polarity is user-defined.

OSD_ACTIVE

On-Screen Display Output

The Memory Interface asserts this signal to indicate that
the on-chip OSD pixel on PD[7:0] is nontransparent. This
signal indicates which pixels have mixed OSD.

EXT_OSD[3:0]

Palette Selection Bus Input

The host controls an external device (such as a character
generator) to write half-bytes across this bus to select
colors from a 16-color look-up table in the L64105 to be
used for external OSD.

Audio Interface 2-9

HS Horizontal Sync Input

HS is the horizontal sync signal from the PAL/NTSC
Encoder. HS is used to reset the horizontal counters in
the display controller. HS should be synchronous to
SYSCLK.

VS Vertical Sync/Odd-Even Field Indicator Input

VS is the vertical sync signal from the PAL/NTSC
Encoder. It can be programmed to be either a
conventional vertical sync input or an even/odd field
indicator. In the even/odd field indicator mode, the
internal display controller counters reset each time VS
changes state (at the beginning of each field). The
polarity of the field is controlled by the timing of VS
relative to HS. VS should be synchronous to SYSCLK.

2.6 Audio Interface

CD_ASDATA CD Mode Audio Data Input

Unencoded serial audio data from a CD or other storage
device. Connected directly to the ASDATA output when
the host selects the CD Bypass mode.

CD_BCLK CD Mode DAC Bit Clock Input

Bit clock from CD player. Connected directly to the BCLK
output when the host selects the CD Bypass mode.

CD_LRCLK CD Mode DAC Left/Right Clock Input

Left/right sample clock from CD player. Connected
directly to the LRCLK output when the host selects the
CD Bypass mode.

CD_ACLK CD Mode DAC Clock Input

DAC clock from CD player. Connected directly to the
A_ACLK output when the host selects the CD Bypass
mode.

ASDATA Audio Serial Data Output

Serial audio data from the L64105’s Audio Decoder in
nonbypass modes. The data can be MPEG or Linear
PCM audio. Serial audio data from the CD_ASDATAinput
in CD Bypass mode.

2-10 I/O Signal Descriptions

BCLK DAC Bit Clock Output

Serial data bit clock used by the L64105’s DAC Interface
to serialize the decoded audio data and by the external
DAC to clock it in on the rising edge. BCLK is derived
from one of the ACLK_ inputs under host control in
normal modes and is the CD_BCLK input in CD Bypass
mode.

LRCLK DAC Left/Right Sample Clock Output

Used to indicate which samples belong to the left and
right stereo channels. In default mode, LRCLK is
asserted when the right channel sample is on the
ASDATA pin and deasserted when the left channel
sample is on the ASDATA pin. The host can set the Invert
LRCLK bit in Register 363 (page 4-84) to invert the sense
of the clock (HIGH for left channel, LOW for right).

A_ACLK DAC Clock Output

This clock is buffered from the selected input ACLK_ (see
the following ACLK_ description). In CD-bypass mode,
this clock comes directly from the CD_ACLK input pin.

AUDIO_SYNCn

Audio Sync Strobe Output

Provides an indication of Audio Decoder synchronization
to the bitstream. Used in transport systems requiring
hardware sync controls. This is an active LOW pulse at
the time of the audio frame decode start.

ACLK_32, ACLK_441, ACLK_48

Audio Reference Clocks Input

Host selectable audio reference clocks from which clocks
for the external DAC, internal DAC Interface, and internal
S/P DIF Interface are derived.

ACLK_32 = 32 kHz * N,
ACLK_441 = 44.1 kHz * N, and
ACLK_48 = 48 kHz * N

where N = 768, 512, 384, or 256.
At least one of the three ACLK_ inputs must be supplied

and it must be integrally divisible into the required sample
rate clocks. See the ACLK Select bits in Register 363
(page 4-84) and the ACLK Divider Select bits in Register
364 (page 4-85).

Miscellaneous and Test Interfaces 2-11

SPDIF_IN External S/P DIF Input

This input is directly connected to the SPDIF_OUT pin
when the host selects the S/P DIF Bypass mode.

SPDIF_OUT S/P DIF Output Output

IEC958 formatted output of the L64105’s S/P DIF
Interface in normal modes and SPDIF_IN in S/P DIF
Bypass mode.

2.7 Miscellaneous and Test Interfaces

PLLVDD PLL Power Supply Input

This pin provides power (3.3 V) to the on-chip PLL for
deriving the 81-MHz SDRAM clock. This power supply
pin

must

be isolated from the digital power plane with the
filter shown in Figure 2.2 and only connected at the
voltage regulator.

Figure 2.2 PLLVDD Decoupling Circuit

PLLVSS PLL Ground Input

This pin provides ground to the on-chip PLL for deriving
the 81-MHz SDRAM clock. This supply pin

must

be
isolated from the digital ground plane, and only
connected at the voltage regulator. It should be
decoupled from the PLLVDD pin.

RESETn Reset Input

When RESETn is asserted, the L64105 resets its internal
microcontroller, FIFO controllers, state machines, and
registers. The minimum RESETn pulse width is 8 cycles
of SYSCLK (8/27 MHz = 300 ns). SYSCLK and the
selected ACLK (ACLK_32, ACLK_441, or ACLK_48)
must be running during reset.

VDD

Ferrite Bead

PLLVSS PLLVSS

1 µF10µF

PLLVDD

2-12 I/O Signal Descriptions

SYSCLK Device Clock Input

Device clock has a nominal frequency of 27 MHz. Picture
reconstruction and video timing are referenced with
respect to this clock. SYSCLK also drives the PLL to
generate the 81-MHz clock for the SDRAM interface.

TM[1:0] Test Mode Input

These inputs are used by LSI Logic during manufacturing
test. They are not exercised in a customer system. They
should both be tied to VSS in the system.

ZTEST Test Mode Input

Test mode pin. This should be tied to VDD in the system
for normal operation. Forcing this signal LOW 3-states all
outputs allowing for simple PCB bed-of-nails testing.

SCAN_TE Test Mode Input

Test mode pin. This should be tied to VSS in the system
for normal operation.

3-1

Chapter 3
Register Summary

Communication with the L64105 Decoder is through 512, 8-bit registers.
The registers are named by their decimal address, 0 to 511. They are
organized into the eight groups listed in Table3.1. The registers, fields,
and bits in each group are further detailed in Table 3.2 through Table 3.8.

To find a register, field, or bit, use Table 3.1 to find the starting page of
the summary table for the group. Then use the summary table to find the
page in Chapter 4 on which the register is described.

If you know the name of a field or bit, use the alphabetic index starting
on page 3-31 to find the page number on which it is described.

3.1 Summary by Register

Table 3.1 L64105 Register Groupings

Register
Number Register Group

Table

Number

Page

Reference

0–63 Host Interface Registers 3.2 3-2
64–191 Video Decoder Registers 3.3 3-7
192–223 Memory Interface Registers 3.4 3-14
224–255 Microcontroller Registers 3.5 3-17
256–335 Video Interface Registers 3.6 3-20
336–383 Audio Decoder Registers 3.7 3-24
384–415 RAM Test Registers 3.8 3-27

3-2 Register Summary

Table 3.2 Host Interface Registers

Addr

(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

000R

1

0 Decode Status Interrupt 4-2

W 0 Decode Status Mask

1R10 Aux/User Data FIFO Ready Interrupt 4-2

W 0 Aux/User Data FIFO Ready Mask

2R10 First Slice Start Code Detect Interrupt 4-3

W 0 First Slice Start Code Detect Mask

3R10 Sequence End Code Detect Interrupt 4-3

W 0 Sequence End Code Detect Mask

4R10 SDRAM Transfer Done Interrupt 4-3

W 0 SDRAM Transfer Done Mask
5 1 Reserved
6 R 0 Audio Sync Recovery Interrupt 4-3

W 0 Audio Sync Recovery Mask
7 R 0 New Field Interrupt 4-3

W 0 New Field Mask

110R10 Audio Sync Code Detect Interrupt 4-3

W 0 Audio Sync Code Detect Mask
1R10 Picture Start Code Detect Interrupt 4-4

W 0 Picture Start Code Detect Mask
2R10 SCR Compare Audio Interrupt 4-4

W 0 SCR Compare Audio Mask
3 1 Reserved
4R10 Begin Active Video Interrupt 4-4

W 0 Begin Active Video Mask

(Sheet 1 of 5)

Summary by Register 3-3

115R10 Begin Vertical Blank Interrupt 4-5

W 0 Begin Vertical Blank Mask
6R10 SCR Overflow Interrupt 4-5

W 0 SCR Overflow Mask
7R10 SCR Compare Interrupt 4-5

W 0 SCR Compare Mask

220R10 Pack Data Ready Interrupt 4-5

W 0 Pack Data Ready Mask
1R10 Audio PES Data Ready Interrupt 4-6

W 0 Audio PES Data Ready Mask
2R10 Video PES Data Ready Interrupt 4-6

W 0 Video PES Data Ready Mask
3 1 Reserved
4R10 Seq End Code in Video Channel Interrupt 4-6

W 0 Seq End Code in Video Channel Mask
5 1 Reserved
6R10 DTS Audio Event Interrupt 4-6

W 0 DTS Audio Event Mask
7R10 DTS Video Event Interrupt 4-6

W 0 DTS Video Event Mask

330R10 Audio ES Channel Buffer Overflow Interrupt 4-7

W 0 Audio ES Channel Buffer Overflow Mask
1R10 Video ES Channel Buffer Overflow Interrupt 4-7

W 0 Video ES Channel Buffer Overflow Mask

Table 3.2 Host Interface Registers (Cont.)

Addr

(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 2 of 5)

3-4 Register Summary

3 3 2:3 1X Reserved

4R10 Audio ES Channel Buffer Underflow Interrupt 4-7

W 0 Audio ES Channel Buffer Underflow Mask
5R10 Video ES Channel Buffer Underflow Interrupt 4-7

W 0 Video ES Channel Buffer Underflow Mask

7:6 – Reserved

440R10 VLC or Run Length Error Interrupt 4-8

W 0 VLC or Run Length Error Mask
1R10 Context Error Interrupt 4-8

W 0 Context Error Mask
2R10 Audio CRC or Illegal Bit Error Interrupt 4-8

W 0 Audio CRC or Illegal Bit Error Mask
3R10 Audio Sync Error Interrupt 4-8

W 0 Audio Sync Error Mask

5:4 1 Reserved

6R10 Packet Error Interrupt 4-9

W 0 Packet Error Interrupt Mask
7R10 S/P DIF Channel Buffer Underflow Interrupt 4-9

W 0 S/P DIF Channel Buffer Underflow Mask

5 5 0 R/W 0 Invert Channel Clock 4-9

1 R/W 0 Channel Request Mode
2 R/W 0 Channel Pause 4-10
3 R/W 0 Channel Bypass Enable
4 R – AREQ Status

Table 3.2 Host Interface Registers (Cont.)

Addr

(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 3 of 5)

Summary by Register 3-5

5 5 5 R – VREQ Status 4-10

7:6 – Reserved

6 6 0 W 0 Clear Interrupt Pin (INTRn) 4-10

7:1 00 Reserved

7 7 0 R 0 Channel Status 4-11

W 0 Channel Start/Reset
1 – Reserved

3:2 R/W 0 Stream Select [1:0] 4-12

4 R/W 0 SCR Pause
5 W 0 Software Reset

7:6 0 Reserved
8 8 7:0 – Reserved
9 9 7:0 R/W 00 SCR Value [7:0] 4-13

10 0A 7:0 R/W 00 SCR Value [15:8]
11 0B 7:0 R/W 00 SCR Value [23:16]
12 0C 7:0 R/W 00 SCR Value [31:24]
13 0D 7:0 R/W FF SCR Compare/Capture [7:0] 4-13
14 0E 7:0 R/W FF SCR Compare/Capture [15:8]
15 0F 7:0 R/W FF SCR Compare/Capture [23:16]
16 10 7:0 R/W FF SCR Compare/Capture [31:24]
17 11 1:0 R/W 0 SCR Compare/Capture Mode [1:0] 4-14

2 R/W 0 Capture on Picture Start Code
3 R/W 0 Capture on Audio Sync Code
4 R/W 0 Capture on Beginning of Active Video

Table 3.2 Host Interface Registers (Cont.)

Addr

(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 4 of 5)

3-6 Register Summary

17 11 5 R/W 0 Capture on Pack Data Ready 4-14

6 R/W 0 Capture on Audio PES Ready 4-15
7 R/W 0 Capture on Video PES Ready

18 12 2:0 0 Reserved

3 R/W 0 Capture on DTS Video 4-15
4 R/W 0 Capture on DTS Audio

7:5 – Reserved

19 13 0 R/W 0 Audio Start on Compare 4-15

1 R/W 0 Video Start on Compare 4-16

7:2 0 Reserved

20 14 7:0 R/W FF SCR Compare Audio [7:0] 4-16
21 15 7:0 R/W FF SCR Compare Audio [15:8]
22 16 7:0 R/W FF SCR Compare Audio [23:16]
23 17 7:0 R/W FF SCR Compare Audio [31:24]

24–27 18–1B – Reserved

28 1C 7:0 W – Video Channel Bypass Data [7:0] 4-16
29 1D 7:0 W – Audio Channel Bypass Data [7:0] 4-17

30–63 1E–3F – Reserved

1. Cleared after read.

Table 3.2 Host Interface Registers (Cont.)

Addr

(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 5 of 5)

Summary by Register 3-7

Table 3.3 Video Decoder Registers

Addr
(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

64 40 0 W 0 Reset Aux Data FIFO 4-17

1:0 R 0 Aux Data FIFO Status [1:0]

4:2 R – Aux Data Layer ID [2:0] 4-18

7:5 0 Reserved

65 41 0 W 0 Reset User Data FIFO 4-18

1:0 R 0 User Data FIFO Status [1:0]

3:2 R – User Data Layer ID [2:0] 4-19

7:4 0 Reserved

66 42 7:0 R – User Data FIFO Output [7:0] 4-19
67 43 7:0 R – Aux Data FIFO Output [7:0]
68 44 0 W 0 Reset Channel Buffer on Error 4-20

1 W 0 Reset Audio PES Header/System Channel Buffer
2 W 0 Reset Video PES Header Channel Buffer

4:3 0 Reserved

5 W 0 Reset Video ES Channel Buffer 4-20
6 W 0 Reset Audio ES Channel Buffer
7 0 Reserved

69 45 0 R/W 0 Enable Video Read Compare DTS 4-21

2:1 R/W 0 Enable Audio Read Compare DTS [1:0]

4:3 R/W 0 Video Numitems/Pics Panic Mode Select [1:0] 4-22

7:5 0 Reserved

(Sheet 1 of 7)

3-8 Register Summary

70, 71 46, 47 7:0 Reserved

72 48 7:0 R/W – Video ES Channel Buffer Start Address [7:0]

1

4-22

73 49 5:0 R/W – Video ES Channel Buffer Start Address [13:8]

1

7:6 0 Reserved

74 4A 7:0 R/W – Video ES Channel Buffer End Address [7:0]

1

4-23

75 4B 5:0 R/W – Video ES Channel Buffer End Address [13:8]

1

7:6 0 Reserved

76 4C 7:0 R/W – Audio ES Channel Buffer Start Address [7:0]

1

4-23

77 4D 5:0 R/W – Audio ES Channel Buffer Start Address [13:8]

1

7:6 0 Reserved

78 4E 7:0 R/W – Audio ES Channel Buffer End Address [7:0]

1

4-24

79 4F 5:0 R/W – Audio ES Channel Buffer End Address [13:8]

1

7:6 0 Reserved

80 50 7:0 R/W – Video PES Header Channel Buffer Start Address

[7:0]

1

4-24

81 51 5:0 R/W – Video PES Header Channel Buffer Start Address

[13:8]

1

7:6 0 Reserved

82 52 7:0 R/W – Video PES Header Channel Buffer End Address

[7:0]

1

4-24

83 53 5:0 R/W – Video PES Header Channel Buffer End Address

[13:8]

1

7:6 0 Reserved

84–87 54–57 7:0 – Reserved

Table 3.3 Video Decoder Registers (Cont.)

Addr
(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 2 of 7)

Summary by Register 3-9

88 58 7:0 R/W – Audio PES Header/System Channel Buffer Start

Address [7:0]

1

4-25

89 59 5:0 R/W – Audio PES Header/System Channel Buffer Start

Address [13:8]

1

7:6 0 Reserved

90 5A 7:0 R/W – Audio PES Header/System Channel Buffer End

Address [7:0]

1

4-25

91 5B 5:0 R/W – Audio PES Header/System Channel Buffer End

Address [13:8]

1

7:6 0 Reserved

92–95 5C–5F 7:0 – Reserved

96 60 7:0 R – Video ES Channel Buffer Write Address [7:0]

2

4-26

97 61 7:0 R – Video ES Channel Buffer Write Address [15:8]

2

98 62 3:0 R – Video ES Channel Buffer Write Address [19:16]

2

7:4 0 Reserved

99 63 7:0 R – Audio ES Channel Buffer Write Address [7:0]

2

4-26

100 64 7:0 R – Audio ES Channel Buffer Write Address [15:8]

2

101 65 3:0 R – Audio ES Channel Buffer Write Address [19:16]

2

7:4 0 Reserved

102 66 7:0 R – Video PES Header Channel Buffer Write Address

[7:0]

2

4-27

103 67 7:0 R – Video PES Header Channel Buffer Write Address

[15:8]

2

104 68 3:0 R – Video PES Header Channel Buffer Write Address

[19:16]

2

7:4 0 Reserved

Table 3.3 Video Decoder Registers (Cont.)

Addr
(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 3 of 7)

3-10 Register Summary

105–

107

69–6B 7:0 – Reserved

108 6C 7:0 R – Video ES Channel Buffer Read Address [7:0]

2

4-27

W – Video ES Channel Buffer Compare DTS Address

[7:0]

4-28

109 6D 7:0 R – Video ES Channel Buffer Read Address [15:8]

2

4-27

W – Video ES Channel Buffer Compare DTS Address

[15:8]

4-28

110 6E 3:0 R – Video ES Channel Buffer Read Address [19:16])

2

4-27

2:0 W – Video ES Channel Buffer Compare DTS Address

[18:16]

4-28

7:4 0 Reserved

111 6F 7:0 R – Audio ES Channel Buffer Read Address [7:0]

2

4-28

W – Audio ES Channel Buffer Compare DTS Address

[7:0]

4-29

112 70 7:0 R – Audio ES Channel Buffer Read Address [15:8]

2

4-28

W – Audio ES Channel Buffer Compare DTS Address

[15:8]

4-29

113 71 3:0 R – Audio ES Channel Buffer Read Address [19:16]

2

4-28

2:0 W – Audio ES Channel Buffer Compare DTS Address

[18:16]

4-29

7:4 0 Reserved

114 72 7:0 R – Audio PES Header/System Channel Buffer Write

Address [7:0]

3

4-29

115 73 7:0 R – Audio PES Header/System Channel Buffer Write

Address [15:8]

3

Table 3.3 Video Decoder Registers (Cont.)

Addr
(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 4 of 7)

Summary by Register 3-11

116 74 3:0 R – Audio PES Header/System Channel Buffer Write

Address [19:16]

3

4-29

7:4 0 Reserved

117–

119

75–77 7:0 – Reserved

120 78 7:0 R – S/P DIF Channel Buffer Read Address [7:0]

3

4-30

121 79 7:0 R – S/P DIF Channel Buffer Read Address [15:8]

3

122 7A 3:0 R – S/P DIF Channel Buffer Read Address [19:16]

3

7:4 0 Reserved

123 7B 7:0 Reserved
124 7C 4:0 W 00 MPEG Audio Extension Stream ID [4:0] 4-30

7:5 Reserved

125–

127

7D–7F 7:0 – Reserved

128 80 7:0 R – Picture Start Code Read Address [7:0]

3

4-31

129 81 7:0 R – Picture Start Code Read Address [15:8]

3

130 82 3:0 R – Picture Start Code Read Address [19:16]

3

7:4 0 Reserved

131 83 7:0 R – Audio Sync Code Read Address [7:0]

3

4-31

132 84 7:0 R – Audio Sync Code Read Address [15:8]

3

133 85 3:0 R – Audio Sync Code Read Address [19:16]

3

7:4 0 Reserved

134 86 7:0 R 00 Video ES Channel Buffer Numitems [7:0]

2

4-32

W – Video Numitems/Pics in Channel Compare Panic

[7:0]

2

Table 3.3 Video Decoder Registers (Cont.)

Addr
(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 5 of 7)

3-12 Register Summary

135 87 7:0 R 00 Video ES Channel Buffer Numitems [15:8]

2

4-32

W – Video Numitems/Pics in Channel Compare Panic

[15:8]

2

136 88 2:0 R 00 Video ES Channel Buffer Numitems [18:162] 4-32

W – Video Numitems/Pics in Channel Compare Panic

[18:16]

2

7:3 00 Reserved

137 89 7:0 R 00 Audio ES Channel Buffer Numitems [7:0]

2

4-33

138 8A 7:0 R 00 Audio ES Channel Buffer Numitems [15:8]

2

139 8B 2:0 R 00 Audio ES Channel Buffer Numitems [18:16]

2

7:3 00 Reserved

140 8C 7:0 R 00 S/P DIF Channel Buffer Numitems [7:0]

2

4-33

141 8D 7:0 R 00 S/P DIF Channel Buffer Numitems [15:8]

2

142 8E 2:0 R 00 S/P DIF Channel Buffer Numitems [18:16]

2

7:3 00 Reserved

143 8F 4:0 W 00 Audio Stream ID [4:0] 4-34

7:5 W 0 Audio Stream Select Enable [2:0]

144 90 0 W 0 Transport Private Stream Audio 4-35

7:1 00 Reserved

145 91 3:0 W 0 Video Stream ID [3:0] 4-35

5:4 W 0 Video Stream Select Enable [1:0]

7:6 R/W 0 Video PES Header Enable [1:0] 4-36

146 92 7:0 0 Reserved

Table 3.3 Video Decoder Registers (Cont.)

Addr
(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 6 of 7)

Summary by Register 3-13

147 93 1:0 R/W 0 Audio PES Header Enable [1:0] 4-36

3:2 R/W 0 System Header Enable [1:0]

5:4 R/W 0 Pack Header Enable [1:0] 4-37

7:6 0 Reserved

148 94 7:0 0 Reserved
149 95 0 R 0 Audio Packet Error Status

4

4-37

1 R 0 Video Packet Error Status

4

7:2 00 Reserved

150 96 7:0 R – Pictures in Video ES Channel Buffer Counter

[7:0]

4-38

151 97 7:0 R – Pictures in Video ES Channel Buffer Counter

[15:8]

152–

191

98–

BF

– Reserved

1. The channel must be stopped to access these registers. Addresses SDRAM at 256-byte boundaries.

2. SDRAM addresses at 8-byte boundaries. A 1 in the most significant bit indicates that the circular
buffer has executed a “wraparound.” Bytes must be read in a least, next, and most significant order.

3. SDRAM addresses at 8-byte boundaries. Bytes must be read in a least, next, and most significant
order.

4. Cleared after read.

Table 3.3 Video Decoder Registers (Cont.)

Addr
(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 7 of 7)

3-14 Register Summary

Table 3.4 Memory Interface Registers

Addr

(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value

(Hex) Status/Command/Data

Page

Ref.

192 C0 0 R 1 Host Read FIFO Empty 4-38

1 R 0 Host Read FIFO Full
2 R 1 Host Write FIFO Empty
3 R 0 Host Write FIFO Full
4 R 1 DMA Read FIFO Empty
5 R 0 DMA Read FIFO Full
6 R 1 DMA Write FIFO Empty
7 R 0 DMA Write FIFO Full

193 C1 0 0 Reserved

2:1 R/W 0 DMA Mode [1:0] (idle, DMA, R/W, block move) 4-39

3 R/W 0 Host SDRAM Transfer Byte Ordering 4-40

5:4 R/W 0 Refresh Extend [1:0]

6 R/W 0 DMA SDRAM Transfer Byte Ordering 4-41

7 0 Reserved
194 C2 7:0 R 0 Host SDRAM Read Data [7:0] 4-41
195 C3 7:0 W 0 Host SDRAM Write Data [7:0]
196 C4 7:0 R/W 0 Host SDRAM Target Address [7:0] 4-42
197 C5 7:0 R/W 0 Host SDRAM Target Address [15:8]
198 C6 2:0 R/W 0 Host SDRAM Target Address [18:16]

7:3 00 Reserved
199 C7 7:0 R/W 00 Host SDRAM Source Address [7:0] 4-42
200 C8 7:0 R/W 00 Host SDRAM Source Address [15:8]

(Sheet 1 of 3)

Summary by Register 3-15

201 C9 2:0 R/W 0 Host SDRAM Source Address [18:16] 4-42

7:3 00 Reserved
202 CA 7:0 R/W FF Block Transfer Count [7:0] 4-43
203 CB 7:0 R/W FF Block Transfer Count [15:8]
204 CC 0 R/W 0 PLL Test 4-43

2:1 0 Reserved

3 R 0 Clk Out of Sync 4-43
5:4 R/W 1 Control for Programmable Delay Path 1
7:6 R/W 1 Control for Programmable Delay Path 2 4-44

205 CD 0 R 0 Phase Locked Status 4-44

2:1 R 0 Internal Lock Counter State
5:3 R 0 Internal DRAM State
7:6 0 Reserved

206 CE 1:0 R – Internal Phase State (3 cycles before) 4-45

3:2 R – Internal Phase State (2 cycles before)
5:4 R – Internal Phase State (1 cycle before)
7:6 R 0 Internal Phase State (current cycle)

207 CF 7:0 R/W 80 Phase Detect Test High Freq [7:0] 4-45
208 D0 7:0 R/W 00 Phase Detect Test High Freq [15:8]
209 D1 7:0 R/W 00 Phase Detect Test Low Freq [7:0]
210 D2 7:0 R/W 01 Phase Detect Test Low Freq [15:8]
211 D3 7:0 R/W A2 VCO Test High Freq [7:0]
212 D4 7:0 R/W 00 VCO Test High Freq [15:8]

Table 3.4 Memory Interface Registers (Cont.)

Addr

(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value

(Hex) Status/Command/Data

Page

Ref.

(Sheet 2 of 3)

3-16 Register Summary

213 D5 7:0 R/W 00 DMA SDRAM Target Address [7:0] 4-46
214 D6 7:0 R/W 00 DMA SDRAM Target Address [15:8]
215 D7 2:0 R/W 00 DMA SDRAM Target Address [18:16]

7:3 00 Reserved

216 D8 7:0 R/W 00 DMA SDRAM Source Address [7:0] 4-46
217 D9 7:0 R/W 00 DMA SDRAM Source Address [15:8]
218 DA 2:0 R/W 00 DMA SDRAM Source Address [18:16]

7:3 00 Reserved

219 DB 7:0 R – DMA SDRAM Read Data [7:0] 4-47
220 DC 7:0 W 00 DMA SDRAM Write Data [7:0]
221 DD 0 R – PLL Phase Detect High Freq Test Pass

1 R – PLL Phase Detect Low Freq Test Pass

2 R – PLL VCO High Freq Test Pass

3 R – PLL VCO Low Freq Test Pass
7:4 0 Reserved

222 DE 7:0 R/W B4 VCO Test Low Freq [7:0] 4-47
223 DF 7:0 R/W 00 VCO Test Low Freq [15:8]

Table 3.4 Memory Interface Registers (Cont.)

Addr

(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value

(Hex) Status/Command/Data

Page

Ref.

(Sheet 3 of 3)

Summary by Register 3-17

Table 3.5 Microcontroller Registers

Addr

(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

224 E0 7:0 R/W – Anchor Luma Frame Store 1 Base Address [7:0]

1

4-48

225 E1 7:0 R/W – Anchor Luma Frame Store 1 Base Address [15:8]

1

226 E2 7:0 R/W – Anchor Chroma Frame Store 1 Base Address [7:0]

1

4-48

227 E3 7:0 R/W – Anchor Chroma Frame Store 1 Base Address [15:8]

1

228 E4 7:0 R/W – Anchor Luma Frame Store 2 Base Address [7:0]

1

4-48

229 E5 7:0 R/W – Anchor Luma Frame Store 2 Base Address [15:8]

1

230 E6 7:0 R/W – Anchor Chroma Frame Store 2 Base Address [7:0]

1

4-49

231 E7 7:0 R/W – Anchor Chroma Frame Store 2 Base Address [15:8]

1

232 E8 7:0 R/W – B Luma Frame Store Base Address [7:0]

1

4-49

233 E9 7:0 R/W – B Luma Frame Store Base Address [15:8]

1

234 EA 7:0 R/W – B Chroma Frame Store Base Address [7:0]

1

4-49

235 EB 7:0 R/W – B Chroma Frame Store Base Address [15:8]

1

236 EC 1:0 R 0 Video Skip Frame Status [1:0] 4-50

W 0 Video Skip Frame Mode [1:0]

2 R 0 Video Continuous Skip Status

W 0 Video Continuous Skip Mode 4-51

7:3 00 Reserved

237 ED 0 R 0 Video Repeat Frame Status 4-51

W 0 Video Repeat Frame Enable

1 R 0 Video Continuous Repeat Frame Status

W 0 Video Continuous Repeat Frame Mode 4-52

7:2 00 Reserved

(Sheet 1 of 3)

3-18 Register Summary

238 EE 0 R 0 Rip Forward Mode Status 4-52

W 0 Rip Forward Mode Enable

1 R 0 Rip Forward Display Single Step Status 4-53

W 0 Rip Forward Display Single Step Command
3:2 R – Current Display Frame [1:0]
5:4 R – Current Decode Frame [1:0]
7:6 0 Reserved

239 EF 0 0 Reserved

1 R/W 0 Host Force Broken Link Mode 4-54
2 R/W 0 Panic Prediction Enable
3 R/W 0 GOP User Data Only 4-55
4 R/W 0 Concealment Copy Option
5 R/W 0 Force Rate Control
6 R/W 0 Ignore Sequence End
7 0 Reserved

240 F0 0 R 0 Host Next GOP/Seq Status 4-56

0 W 0 Host Search Next GOP/Seq Command

7:1 00 Reserved

241 F1 0 R – Q Table Ready 4-56

1 R/W – Intra Q Table

7:2 R/W – Q Table Address [5:0]

242 F2 7:0 R – Q Table Entry [7:0] 4-57

Table 3.5 Microcontroller Registers (Cont.)

Addr

(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 2 of 3)

Summary by Register 3-19

243 F3 7:0 R – Microcontroller PC [7:0] 4-57
244 F4 3:0 R – Microcontroller PC [11:8]

7:4 0 Reserved

245 F5 7:0 R – Revision Number [7:0] 4-57
246 F6 0 W 0 Decode Start/Stop Command 4-57

7:1 00 Reserved

247 F7 7:0 – Reserved
248 F8 0 R/W 0 Reduced Memory Mode (RMM) 4-58

7:1 00 Reserved

249–

255

F9–

FF

– Reserved

1. SDRAM addresses at 64-byte boundaries.

Table 3.5 Microcontroller Registers (Cont.)

Addr

(Dec)

Addr
(Hex) Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 3 of 3)

3-20 Register Summary

Table 3.6 Video Interface Registers

Addr

Dec

Addr

Hex Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

256–

264

100–

108

Reserved

265 109 1:0 R/W 0 OSD Mode [1:0] 4-58

2 0 Reserved
3 R – OSD Palette Counter Zero Flag 4-59

W 0 Clear OSD Palette Counter
5:4 R/W 0 Display Override Mode [1:0]
7:6 R/W 0 Force Video Background [1:0] 4-59

266 10A 7:0 R/W 23 Programmable Background Y[7:0] 4-60
267 10B 7:0 R/W D4 Programmable Background Cb[7:0]
268 10C 7:0 R/W 72 Programmable Background Cr[7:0]
269 10D 7:0 W – OSD Palette Write [7:0] 4-60
270 10E 7:0 R/W – OSD Odd Field Pointer [7:0]

1

4-61

271 10F 7:0 R/W – OSD Odd Field Pointer [15:8]

1

272 110 7:0 R/W – OSD Even Field Pointer [7:0]

1

273 111 7:0 R/W – OSD Even Field Pointer [15:8]

1

274 112 3:0 R/W 0 OSD Mix Weight [3:0] 4-61

4 R/W 0 OSD Chroma Filter Enable
5 – Reserved
6 R/W 0 Horizontal Decimation Filter Enable 4-61
7 0 Reserved

275 113 1:0 R/W 0 Freeze Mode [1:0] 4-62

2 R/W 1 3:2 Pulldown from Bitstream
3 R/W 0 Host Repeat First Field

(Sheet 1 of 4)

Summary by Register 3-21

275 113 4 R/W 1 Host Top Field First 4-62

5 R – First Field
6 R – Odd/Not Even Field 4-63
7 R – Top/Not Bottom Field

276 114 0 R – Last Field 4-63

1 R/W 0 Horizontal Filter Enable
2 R/W – Horizontal Filter Select

6:3 R/W – Display Mode [3:0] 4-64

7 R/W 0 Field Sync Enable
277 115 7:0 R/W – Horizontal Filter Scale [7:0] 4-64
278 116 6:0 R/W – Main Reads per Line [6:0] 4-65

7 0 Reserved
279 117 2:0 R/W – Pan and Scan 1/8 Pixel Offset [2:0] 4-65

5:3 R/W – Pan and Scan Byte Offset [2:0]

6 R/W 1 Pan and Scan from Bitstream

7 R/W 0 Automatic Field Inversion Correction
280 118 7:0 R/W – Horizontal Pan and Scan Luma/Chroma Word

Offset [7:0]

4-66

281 119 7:0 R/W – Vertical Pan and Scan Line Offset [7:0]
282 11A 2:0 R/W 1 Vline Count Init [2:0]

7:3 00 Reserved

283 11B 6:0 R/W – Override Picture Width [6:0] 4-67

7 0 Reserved

Table 3.6 Video Interface Registers (Cont.)

Addr

Dec

Addr

Hex Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 2 of 4)

3-22 Register Summary

284 11C 0 R/W 0 ITU-R BT.656 Mode 4-67

1 R/W 0 Sync Active Low

2 0 Reserved

4:3 R/W 2 Pixel State Reset Value [1:0] 4-67

5 R/W 0 CrCb 2s Complement 4-68

6 R/W 0 VSYNC Input Type

7 0 Reserved
285 11D 7:0 R/W – Display Override Luma FrameStore Start Address

[7:0]

1

4-68

286 11E 7:0 R/W – Display Override Luma Frame Store Start Address

[15:8]

1

287 11F 7:0 R/W – Display Override Chroma Frame Store Start

Address [7:0]

1

288 120 7:0 R/W – Display Override Chroma Frame Store Start

Address [15:8]

1

289 121 0 0 Reserved

6:1 R/W 2C Number of Segments in RMM [5:0] 4-69

7 0 Reserved
290 122 1:0 W 0 Television Standard Select [1:0] 4-69

7:2 00 Reserved

291–

296

123–

128

Reserved

297 129 7:0 R/W – Main Start Row [7:0] 4-70
298 12A 7:0 R/W – Main End Row [7:0]
299 12B 2:0 R/W – Main Start Row [10:8]

3 – Reserved

Table 3.6 Video Interface Registers (Cont.)

Addr

Dec

Addr

Hex Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 3 of 4)

Summary by Register 3-23

299 12B 6:4 R/W – Main End Row [10:8] 4-70

7 0 Reserved
300 12C 7:0 R/W – Main Start Column [7:0] 4-70
301 12D 7:0 R/W – Main End Column [7:0]
302 12E 2:0 R/W – Main Start Column [10:8]

3 – Reserved

6:4 R/W – Main End Column [10:8] 4-70

7 0 Reserved
303 12F 4:0 R/W – Vcode Zero [4:0] 4-70

5 R/W – Vcode Even [8] 4-71

6 R/W – Vcode Even Plus 1

7 R/W – Fcode [8]
304 130 7:0 R/W – Vcode Even [7:0] 4-71
305 131 7:0 R/W – Fcode [7:0]
306 132 7:0 R/W – SAV Start Column [7:0] 4-72
307 133 7:0 R/W – EAV Start Column [7:0]
308 134 2:0 R/W – SAV Start Column [10:8]

3 0 Reserved

6:4 R/W – EAV Start Column [10:8] 4-72

7 0 Reserved
309 135 0 R/W 0 Display Start Command 4-72

7:1 00 Reserved

310–

335

136–

14F

– Reserved

Table 3.6 Video Interface Registers (Cont.)

Addr

Dec

Addr

Hex Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 4 of 4)

3-24 Register Summary

Table 3.7 Audio Decoder Registers

Addr

Dec

Addr

Hex Bit(s) R/W

Default

Value

(Hex) Status/Command/Data

Page

Ref.

336 150 3:0 R – MPEG - bitrate_index [3:0] 4-72

4 R – MPEG - protection_bit 4-73

6:5 R – MPEG - layer_code [1:0] 4-74

7 R – MPEG - ID

337 151 0 R – MPEG - copyright 4-74

2:1 R – MPEG - mode_extension [1:0]
4:3 R – MPEG - mode [1:0] 4-75

5 R – MPEG - private_bit 4-76

7:6 R – MPEG - sampling_freq [1:0]

338 152 4:0 0 Reserved

6:5 R – MPEG - emphasis [1:0] 4-76

7 R – MPEG - original/copy

339—

350

153—

15E

7:0 – Reserved

351 15F 2:0 R – PCM - num_of_audio_ch [2:0] 4-77

7:3 R – PCM - audio_frm_num [4:0]

352 160 0 0 Reserved

1 R – PCM - mute_bit 4-77
3:2 R – PCM - emphasis [1:0]
5:4 R – PCM - quantization [1:0]
7:6 R – PCM - Fs [1:0]

353 161 4:0 – Reserved

5 R – PCM FIFO Empty 4-77

(Sheet 1 of 4)

Summary by Register 3-25

353 161 6 R – PCM FIFO Near Full 4-78

7 R – PCM FIFO Full

354 162 1:0 R – Audio Decoder Play Mode Status [1:0]

2 R – Audio Decoder Soft Mute Status

3 R – Audio Decoder Reconstruct Error

4 R – MPEG Multichannel Extension Sync Word Missing 4-79
7:5 0 Reserved

355 163 4:0 00 Reserved

6:5 R/W 0 Audio Decoder Play Mode [1:0] 4-79

7 R/W 0 Audio Decoder Start/Stop 4-80

356 164 4:0 00 Reserved

6:5 R/W 0 Audio Formatter Play Mode [1:0] 4-80

7 R/W 0 Audio Formatter Start/Stop

357 165 4:0 00 Reserved

7:5 R/W 0 Audio Decoder Mode Select [2:0] 4-81

358 166 1:0 0 Reserved

3:2 R/W 0 Audio Dual-Mono Mode [1:0] 4-82
5:4 0 Reserved

6 R/W 0 User Mute Bit 4-82

7 R/W 1 Mute on Error

359 167 7:0 W – PCM FIFO Data In [7:0] 4-83
360 168 7:0 R/W FF Linear PCM - dynscalehigh [7:0]
361 169 7:0 R/W FF Linear PCM - dynscalelow [7:0]

Table 3.7 Audio Decoder Registers (Cont.)

Addr

Dec

Addr

Hex Bit(s) R/W

Default

Value

(Hex) Status/Command/Data

Page

Ref.

(Sheet 2 of 4)

3-26 Register Summary

362 16A 7:0 R/W FF PCM Scale [7:0] 4-84
363 16B 1:0 R/W 1 ACLK Select [1:0]

2 R/W 0 Invert LRCLK
5:3 0 Reserved

6 R/W 0 User 4-85

7 R/W 1 Valid

364 16C 3:0 R/W 0 ACLK Divider Select [3:0] 4-85

4 R/W 0 LPCM - Dynamic Range On 4-87
7:5 0 Reserved

365 16D 1:0 0 Reserved

4:2 R/W 0 IEC - Host Emphasis [2:0] 4-87

5 R/W 0 IEC - Overwrite Emphasis

6 R/W 0 IEC - Host Copyright

7 R/W 0 IEC - Overwrite Copyright 4-88

366 16E 0 R/W 0 Overwrite Category 4-88

2:1 R/W 0 Host Overwrite Quantization [1:0]

3 R/W 0 Overwrite Quantization Enable 4-89

4 R/W 0 MPEG Formatter Only
6:5 R/W 0 Formatter Skip Frame Size [1:0]

7 0 Reserved

367 16F 7:0 R/W 00 Host Category [7:0] 4-89
368 170 0 0 Reserved

1 R – Pd Data Valid 4-90

Table 3.7 Audio Decoder Registers (Cont.)

Addr

Dec

Addr

Hex Bit(s) R/W

Default

Value

(Hex) Status/Command/Data

Page

Ref.

(Sheet 3 of 4)

Summary by Register 3-27

368 170 2 0 Reserved

4:3 R/W 0 Pd Selection [1:0] 4-90
7:5 R/W 0 Host Pc Info [2:0]

369 171 7:0 R/W 00 Host Pd Value [15:8] 4-91
370 172 7:0 R/W 00 Host Pd Value [7:0]

371–

383

173–

17F

– Reserved for diagnostic use

Table 3.8 RAM Test Registers

Addr

Dec

Addr

Hex Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

384 180 7:0 R/W 00 Memory Test Address [7:0] 4-91
385 181 3:0 R/W 00 Memory Test Address [11:8]

7:4 0 Reserved

386 182 1:0 W 0 Operational Mode for RAM Test [1:0] 4-91

2 R 0 Report End of Test 4-92

W 0 Initiate Memory Test

4:3 W 0 Data Pattern to be Applied to RAM [1:0]

5 R/W 0 Memory Test Output Select

7:6 0 Reserved

(Sheet 1 of 4)

Table 3.7 Audio Decoder Registers (Cont.)

Addr

Dec

Addr

Hex Bit(s) R/W

Default

Value

(Hex) Status/Command/Data

Page

Ref.

(Sheet 4 of 4)

3-28 Register Summary

387 183 0 R 1 MemTest01 Pass/Fail Status

1

4-93

1 R 1 MemTest02 Pass/Fail Status

1

387 183 2 R 1 MemTest03 Pass/Fail Status

1

4-93

3 R 1 MemTest04 Pass/Fail Status

1

4 R 1 MemTest05 Pass/Fail Status

5 R 1 MemTest06 Pass/Fail Status

1

6 R 1 MemTest07 Pass/Fail Status

1

7 R 1 MemTest08 Pass/Fail Status

1

388 184 0 R 1 MemTest09 Pass/Fail Status

1

4-93

1 R 1 MemTest10 Pass/Fail Status

1

2 R 1 MemTest11 Pass/Fail Status

1

3 R 1 MemTest12 Pass/Fail Status

1

4 R 1 MemTest13 Pass/Fail Status

1

5 R 1 MemTest14 Pass/Fail Status

1

6 R 1 MemTest15 Pass/Fail Status

1

7 R 1 MemTest16 Pass/Fail Status

1

Table 3.8 RAM Test Registers (Cont.)

Addr

Dec

Addr

Hex Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 2 of 4)

Summary by Register 3-29

389 185 0 R 1 MemTest17 Pass/Fail Status

1

4-93

1 R 1 MemTest18 Pass/Fail Status

1

2 R 1 MemTest19 Pass/Fail Status

1

3 R 1 MemTest20 Pass/Fail Status

1

4 R 1 MemTest21 Pass/Fail Status

1

5 R 1 MemTest22 Pass/Fail Status

1

6 R 1 MemTest23 Pass/Fail Status

1

7 R 1 MemTest24 Pass/Fail Status

1

390 186 0 R 1 MemTest25 Pass/Fail Status

1

4-93

1 R 1 MemTest26 Pass/Fail Status

1

2 R 1 MemTest27 Pass/Fail Status

1

3 R 1 MemTest28 Pass/Fail Status

1

4 R 1 MemTest29 Pass/Fail Status

1

5 R 1 MemTest30 Pass/Fail Status

1

6 R 1 MemTest31 Pass/Fail Status

1

7 R 1 MemTest32 Pass/Fail Status

1

391 187 0 R 1 MemTest33 Pass/Fail Status

1

4-93

1 R 1 MemTest34 Pass/Fail Status

1

2 R 1 MemTest35 Pass/Fail Status

1

3 R 1 MemTest36 Pass/Fail Status

1

7:4 0 Reserved

Table 3.8 RAM Test Registers (Cont.)

Addr

Dec

Addr

Hex Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 3 of 4)

3-30 Register Summary

392 188 0 R 1 MemTest37 Pass/Fail Status

1

4-93

1 R 1 MemTest38 Pass/Fail Status

1

2 R 1 MemTest39 Pass/Fail Status

1

6:3 0 Reserved

7 R 1 Overall MemTest Pass/Fail Status

1

4-93

393–

511

189–

1FF

7:0 – Reserved

1. Reset after read.

Table 3.8 RAM Test Registers (Cont.)

Addr

Dec

Addr

Hex Bit(s) R/W

Default

Value
(Hex) Status/Command/Data

Page

Ref.

(Sheet 4 of 4)

Alphabetical Listing of Register Bits and Fields 3-31

3.2 Alphabetical Listing of Register Bits and Fields

Numerics

3:2 Pull Down From Bitstream bit 4-62

A

ACLK Divider Select [3:0] 4-85
ACLK Select [1:0] 4-84
Anchor Chroma Frame Store 1 Base Address [15:0] 4-48
Anchor Chroma Frame Store 2 Base Address [15:0] 4-49
Anchor Luma Frame Store 1 Base Address [15:0] 4-48
Anchor Luma Frame Store 2 Base Address [15:0] 4-48
AREQ Status bit 4-10
Audio Channel Bypass Data [7:0] 4-17
Audio CRC or Illegal Bit Error Interrupt bit 4-8
Audio Decoder Play Mode [1:0] 4-79
Audio Decoder Play Mode Status [1:0] 4-78
Audio Decoder Reconstruct Error bit 4-78
Audio Decoder Soft Mute Status bit 4-78
Audio Decoder Start/Stop bit 4-80
Audio Dual-Mono Mode [1:0] 4-82
Audio ES Channel Buffer Compare DTS Address [19:0] 4-29
Audio ES Channel Buffer End Address [13:0] 4-24
Audio ES Channel Buffer Numitems [18:0] 4-33
Audio ES Channel Buffer Overflow Interrupt bit 4-7
Audio ES Channel Buffer Read Address [19:0] 4-28
Audio ES Channel Buffer Start Address [13:0] 4-23
Audio ES Channel Buffer Underflow Interrupt bit 4-7
Audio ES Channel Buffer Write Address [19:0] 4-26
Audio Formatter Play Mode [1:0] 4-80
Audio Formatter Start/Stop bit 4-80
Audio Module Mode Select [2:0] 4-81
Audio Packet Error Status bit 4-37
Audio PES Data Ready Interrupt bit 4-6
Audio PES Header Enable [1:0] 4-36
Audio PES Header/System Channel Buffer End Address [13:0] 4-25
Audio PES Header/System Channel Buffer Start Address [13:0] 4-25
Audio PES Header/System Channel Buffer Write Address [19:0] 4-29
Audio Start on Compare bit 4-15
Audio Stream ID [4:0] 4-34
Audio Stream Select Enable [2:0] 4-34
Audio Sync Code Detect Interrupt bit 4-3

3-32 Register Summary

Audio Sync Code Read Address [19:0] 4-31
Audio Sync Error Interrupt bit 4-8
Audio Sync Recovery Interrupt bit 4-3
Automatic Field Inversion Correction bit 4-65
Aux Data FIFO Output [7:0] 4-19
Aux Data FIFO Status [1:0] 4-17
Aux Data Layer ID [2:0] 4-18
Aux/User Data FIFO Ready Interrupt bit 4-2

B

B Chroma Frame Store Base Address [15:0] 4-49
B Luma Frame Store Base Address [15:0] 4-49
Begin Active Video Interrupt bit 4-4
Begin Vertical Blank Interrupt bit 4-5
Block Transfer Count [15:0] 4-43

C

Capture on Audio PES Ready bit 4-15
Capture on Audio Sync Code bit 4-14
Capture on Beginning of Active Video bit 4-14
Capture on DTS Audio bit 4-15
Capture on DTS Video bit 4-15
Capture on PACK Data Ready bit 4-14
Capture on Picture Start Code bit 4-14
Capture on Video PES Ready bit 4-15
Channel Bypass Enable bit 4-10
Channel Pause bit 4-10
Channel Request Mode bit 4-9
Channel Start/Reset bit 4-11
Channel Status bit 4-11
Clear Interrupt Pin bit 4-10
Clear OSD Palette Counter bit 4-59
Clk Out of Sync bit 4-43
Concealment Copy Option bit 4-55
Context Error Interrupt bit 4-8
Control for Programmable Delay Path 1 [1:0] 4-43
Control for Programmable Delay Path 2 [1:0] 4-44
CrCb 2’s Complement bit 4-68
Current Decode Frame [1:0] 4-53
Current Display Frame [1:0] 4-53

Alphabetical Listing of Register Bits and Fields 3-33

D

Data Pattern to be Applied to RAM [1:0] 4-92
Decode Start/Stop Command bit 4-57
Decode Status Interrupt bit 4-2
Display Mode [3:0] 4-63
Display Override Luma/Chroma Frame Store Start
Addresses [15:0] 4-68
Display Override Mode [1:0] 4-59
Display Start Command bit 4-72
DMA Mode [1:0] 4-39
DMA Read FIFO Empty bit 4-38
DMA Read FIFO Full bit 4-38
DMA SDRAM Read Data [7:0] 4-47
DMA SDRAM Source Address [18:0] 4-46
DMA SDRAM Target Address [18:0] 4-46
DMA SDRAM Write Data [7:0] 4-47
DMA SDRAM Transfer Byte Ordering bit 4-41
DMA Write FIFO Empty bit 4-38
DMA Write FIFO Full bit 4-38
DTS Audio Event Interrupt bit 4-6
DTS Video Event Interrupt bit 4-6

E

Enable Audio Read Compare DTS [1:0] 4-21
Enable Video Read Compare DTS bit 4-21

F

Fcode [7:0] 4-71
Fcode [8] 4-71
Field Sync Enable bit 4-64
First Field bit 4-62
First Slice Start Code Detect Interrupt bit 4-3
Force Rate Control bit 4-55
Force Video Background [1:0] 4-59
Formatter Skip Frame Size [1:0] 4-89
Freeze Mode [1:0] 4-62

G

GOP User Data Only bit 4-55

H

Horizontal Decimation Filter Enable bit 4-61
Horizontal Filter Enable bit 4-63

3-34 Register Summary

Horizontal Filter Scale [7:0] 4-64
Horizontal Filter Select bit 4-63
Horizontal Pan and Scan Luma/Chroma Word Offset [7:0] 4-66
Host Category [7:0] 4-89
Host SDRAM Transfer Byte Ordering bit 4-40
Host Force Broken Link Mode bit 4-54
Host Next GOP/Seq Status bit 4-56
Host Overwrite Quantization [1:0] 4-88
Host Pc Info [2:0] 4-90
Host Pd Value [15:0] 4-91
Host Read FIFO Empty bit 4-38
Host Read FIFO Full bit 4-38
Host Repeat First Field bit 4-62
Host SDRAM Read Data [7:0] 4-41
Host SDRAM Source Address [18:0] 4-42
Host SDRAM Target Address [18:0] 4-42
Host SDRAM Write Data [7:0] 4-41
Host Search Next GOP/Seq Command bit 4-56
Host Top Field First bit 4-62
Host Write FIFO Empty bit 4-38
Host Write FIFO Full bit 4-38

I

IEC - Host Copyright bit 4-87
IEC - Host Emphasis [2:0] 4-87
IEC - Overwrite Copyright bit 4-88
IEC - Overwrite Emphasis bit 4-87
Ignore Sequence End bit 4-55
Initiate Memory Test bit 4-92
Internal Lock Counter State [1:0] 4-44
Internal Phase State (1 cycle before) [1:0] 4-45
Internal Phase State (2 cycles before) [1:0] 4-45
Internal Phase State (3 cycles before) [1:0] 4-45
Internal Phase State (current cycle) [1:0] 4-45
Internal SDRAM State [2:0] 4-44
Intra Q Table bit 4-56
Invert Channel Clock bit 4-9
Invert LRCLK bit 4-84
ITU-R BT.656 Mode bit 4-67

Alphabetical Listing of Register Bits and Fields 3-35

L

Last Field bit 4-63
Linear PCM - dynscalehigh [7:0] 4-83
Linear PCM - dynscalelow [7:0] 4-83
LPCM - Dynamic Range On bit 4-87

M

Main Reads Per Line [6:0] 4-65
MAIN Start/End Columns [10:0] 4-70
MAIN Start/End Rows [10:0] 4-70
Memory Test Address [11:0] 4-91
Memory Test Output Select bit 4-92
Memory Test Pass/Fail Status Bits 4-93
Microcontroller PC [11:0] 4-57
MPEG - bitrate_index [3:0] 4-72
MPEG - copyright bit 4-74
MPEG - emphasis [1:0] 4-76
MPEG - ID bit 4-74
MPEG - layer code [1:0] 4-74
MPEG - mode [1:0] 4-75
MPEG - mode_extension [1:0] 4-74
MPEG - original/copy bit 4-76
MPEG - private_bit 4-76
MPEG - protection_bit 4-73
MPEG - sampling_frequency [1:0] 4-76
MPEG Audio Extension Stream ID [4:0] 4-30
MPEG Formatter Only bit 4-89
MPEG Multichannel Extension Sync Word Missing bit 4-79
Mute on Error bit 4-82

N

New Field Interrupt bit 4-3
Number of Segments in RMM [5:0] 4-69

O

Odd/Not Even Field bit 4-63
Operational Mode for Ram Test [1:0] 4-91
OSD Chroma Filter Enable bit 4-61
OSD Mix Weight [3:0] 4-61
OSD Mode [1:0] 4-58
OSD Odd/Even Field Pointers [15:0] 4-61
OSD Palette Counter Zero Flag 4-59
OSD Palette Write [7:0] 4-60

3-36 Register Summary

Override Picture Width [6:0] 4-67
Overwrite Category bit 4-88
Overwrite Quantization Enable bit 4-89

P

Pack Data Ready Interrupt bit 4-5
Pack Header Enable [1:0] 4-37
Packet Error Interrupt bit 4-9
Pan and Scan 1/8 Pixel Offset [2:0] 4-65
Pan and Scan Byte Offset [2:0] 4-65
Pan and Scan From Bitstream bit 4-65
Panic Prediction Enable bit 4-54
PCM - audio_frm_num [4:0] 4-77
PCM - emphasis [1:0] 4-77
PCM - Fs [1:0] 4-77
PCM - mute_bit 4-77
PCM - num_of_audio_ch [2:0] 4-77
PCM - quantization [1:0] 4-77
PCM FIFO Empty bit 4-77
PCM FIFO Full bit 4-78
PCM FIFO Near Full bit 4-78
PCM Scale [7:0] 4-84
PCM FIFO Data In [7:0] 4-83
Pd Data Valid bit 4-90
Pd Selection bit 4-90
Phase Detect Test High Freq [15:0] 4-45
Phase Detect Test Low Freq [15:0] 4-45
Phase Locked Status bit 4-44
Picture Start Code Detect Interrupt bit 4-4
Picture Start Code Read Address [19:0] 4-31
Pictures in Video ES Channel Buffer Counter [15:0] 4-38
Pixel State Reset Value [1:0] 4-67
PLL Phase Detect High Frequency Test Pass bit 4-47
PLL Phase Detect Low Frequency Test Pass bit 4-47
PLL Test bit 4-43
PLL VCO High Frequency Test Pass bit 4-47
PLL VCO Low Frequency Test Pass bit 4-47
Programmable Background Y/Cb/Cr [7:0] 4-60

Q

Q Table Address [5:0] 4-56
Q Table Entry [7:0] 4-57
Q Table Ready bit 4-56

Alphabetical Listing of Register Bits and Fields 3-37

R

Reduced Memory Mode (RMM) bit 4-58
Refresh Extend [1:0] 4-40
Report End of Test bit 4-92
Reset Audio ES Channel Buffer bit 4-20
Reset Audio PES Header/System Channel Buffer bit 4-20
Reset Aux Data FIFO bit 4-17
Reset Channel Buffers on Error bit 4-20
Reset User Data FIFO bit 4-18
Reset Video ES Channel Buffer bit 4-20
Reset Video PES Header Channel Buffer bit 4-20
Revision Number [7:0] 4-57
Rip Forward Display Single Step Command bit 4-53
Rip Forward Display Single Step Status bit 4-53
Rip Forward Mode Enable bit 4-52
Rip Forward Mode Status bit 4-52

S

S/P DIF (IEC958) Channel Buffer Read Address [19:0] 4-30
S/P DIF Channel Buffer Numitems [18:0] 4-33
S/P DIF Channel Buffer Underflow Interrupt bit 4-9
SAV/EAV Start Columns [10:0] 4-72
SCR Compare Audio [31:0] 4-16
SCR Compare Audio Interrupt bit 4-4
SCR Compare Interrupt bit 4-5
SCR Compare/Capture [31:0] 4-13
SCR Compare/Capture Mode [1:0] 4-14
SCR Overflow Interrupt bit 4-5
SCR Pause bit 4-12
SCR Value [31:0] 4-13
SDRAM Transfer Done Interrupt bit 4-3
Seq End Code in Video Channel Interrupt bit 4-6
Sequence End Code Detect Interrupt bit 4-3
Software Reset bit 4-12
Stream Select [1:0] 4-12
Sync Active Low bit 4-67
System Header Enable [1:0] 4-36

T

Television Standard Select [1:0] 4-69
Top/Not Bottom Field bit 4-63
Transport Private Stream Audio bit 4-35

3-38 Register Summary

U

User bit 4-85
User Data FIFO Output [7:0] 4-19
User Data FIFO Status [1:0] 4-18
User Data Layer ID [1:0] 4-19
User Mute Bit 4-82

V

Valid bit 4-85
VCO Test High Freq [15:0] 4-45
VCO Test Low Freq [15:8] 4-47
Vcode Even [7:0] 4-71
Vcode Even [8] 4-71
Vcode Even Plus 1 bit 4-71
Vcode Zero [4:0] 4-70
Vertical Pan and Scan Line Offset [7:0] 4-66
Video Channel Bypass Data [7:0] 4-16
Video Continuous Repeat Frame Mode bit 4-52
Video Continuous Repeat Frame Status bit 4-51
Video Continuous Skip Mode bit 4-51
Video Continuous Skip Status bit 4-50
Video ES Channel Buffer Compare DTS Address [19:0] 4-28
Video ES Channel Buffer End Address [13:0] 4-23
Video ES Channel Buffer Numitems [18:0] 4-32
Video ES Channel Buffer Overflow Interrupt bit 4-7
Video ES Channel Buffer Read Address [19:0] 4-27
Video ES Channel Buffer Start Address [13:0] 4-22
Video ES Channel Buffer Underflow Interrupt bit 4-7
Video ES Channel Buffer Write Address [19:0] 4-26
Video Numitems/Pics in Channel Compare Panic [18:0] 4-32
Video Numitems/Pics Panic Mode Select [1:0] 4-22
Video Packet Error Status 4-37
Video PES Data Ready Interrupt bit 4-6
Video PES Header Channel Buffer End Address [13:0] 4-24
Video PES Header Channel Buffer Start Address [13:0] 4-24
Video PES Header Channel Buffer Write Address [19:0] 4-27
Video PES Headers Enable [1:0] 4-36
Video Repeat Frame Enable 4-51
Video Repeat Frame Status 4-51
Video Skip Frame Mode [1:0] 4-50
Video Skip Frame Status [1:0] 4-50
Video Start on Compare bit 4-16
Video Stream ID [3:0] 4-35

Alphabetical Listing of Register Bits and Fields 3-39

Video Stream Select Enable [1:0] 4-35
VLC or Run Length Error Interrupt bit 4-8
Vline Count Init [2:0] 4-66
VREQ Status bit 4-10
VSYNC Input Type bit 4-68

3-40 Register Summary

4-1

Chapter 4
Register Descriptions

This chapter describes the bit and field assignments of all of the registers
in the L64105. The chapter contains the following sections:

♦ Section 4.1, “Host Interface Registers,” page 4-2
♦ Section 4.2, “Video Decoder Registers,” page 4-17
♦ Section 4.3, “Memory Interface Registers,” page 4-38
♦ Section 4.4, “Microcontroller Registers,” page 4-48
♦ Section 4.5, “Video Interface Registers,” page 4-58
♦ Section 4.6, “Audio Decoder Registers,” page 4-72
♦ Section 4.7, “RAM Test Registers,” page 4-91

To locate a specific register, field, or bit, use the register summary in

Chapter 3.

If you know the name of a field or bit, use the alphabetic index starting
on page 3-31 to find the page number on which it is described.

4-2 Register Descriptions

4.1 Host Interface Registers

Figure 4.1 Register 0 (0x000)

Decode Status Interrupt 0

This bit is set when the video decode status changes
from stopped to running (0 to 1) and cleared when the
status changes from running to stopped (1 to 0). Either
status change causes assertion of the INTRn interrupt
signal to the host if not masked. The 0 to 1 transition
occurs on a picture start code boundary after channel
start. It is linked in timing to the last field of the display
system. The decode status is updated internally and may
change when one of the following events is recognized by
the internal microcontroller:

1. A write to the Decode Start/Stop Command register
(page 4-57) by the host.

2. When the Video Start on Compare register (page 4-16)
is set by the host and a compare occurs. In this case, the
status goes from stopped to running.

Reading this register does NOT change the Decode
Status bit.

INTRn is not asserted if the host sets the mask bit.

Aux/User Data FIFO Ready Interrupt 1

When set, indicates there is new data in the Aux or User
Data FIFO ready to be read. A NOT ready (0) to ready
(1) change causes assertion of the INTRn signal if not
masked. The status of the Aux Data FIFO (page 4-17)
and User Data FIFO (page 4-18) can be read to
determine which has valid data. The bit is cleared on
reading. Even though data remains in the FIFOs, no
further interrupts are generated.

INTRn is not asserted if the host sets the mask bit.

76543210

Read

New Field

Interrupt

Audio Sync

Recovery

Interrupt

Reserved

SDRAM
Transfer

Done

Interrupt

Sequence
End Code

Detect

Interrupt

First Slice

Start Code

Detect

Interrupt

Aux/User

Data FIFO

Ready

Interrupt

Decode

Status

Interrupt

Write

New Field

Mask

Audio Sync

Recovery

Mask

Reserved

SDRAM
Transfer

Done Mask

Sequence
End Code

Detect Mask

First Slice

Start Code

Detect Mask

Aux/User

Data FIFO

Ready Mask

Decode

Status Mask

Host Interface Registers 4-3

First Slice Start Code Detect Interrupt 2

This bit is set when the decoder detects the first slice
start code after the picture layer. INTRn is asserted
unless the host sets the mask bit.

Sequence End Code Detect Interrupt 3

This bit is set when the decoder detects a sequence end
code. INTRn is asserted unless the host sets the mask
bit.

SDRAM Transfer Done Interrupt 4

This bit is set when an SDRAM block move is completed.
INTRn is asserted unless the host sets the mask bit.

Reserved 5

Set this bit when writing to Register 0.

Audio Sync Recovery Interrupt 6

The audio sync recovery bit is set when sync is re­established after any errors, i.e., when three good frames
are detected after synchronization was lost.

This bit is cleared when read. INTRn is also asserted
unless the host sets the mask bit.

New Field Interrupt 7

This bit is set after a short delay after the termination of
the Vertical Sync pulse from the PAL/NTSC Encoder.
INTRn is also asserted unless the host sets the mask bit.

Figure 4.2 Register 1 (0x001)

Audio Sync Code Detect Interrupt 0

This bit is set when the Audio Decoder detects a valid
audio sync code. The interrupt is intended to be used for
synchronization of presentation units. This is achieved by
sampling the System Clock Reference (SCR) using the
capture register function of the SCR. Also at this time, the

76543210

Read

SCR

Compare

Interrupt

SCR

Overflow

Interrupt

Begin

Vertical

Blank

Interrupt

Begin Active

Video

Interrupt

Reserved

SCR

Compare

Audio

Interrupt

Picture Start
Code Detect

Interrupt

Audio Sync

Code Detect

Interrupt

Write

SCR

Compare

Mask

SCR

Overflow

Mask

Begin

Vertical

Blank Mask

Begin Active

Video Mask

Reserved

SCR

Compare

Audio Mask

Picture Start
Code Detect

Mask

Audio Sync

Code Detect

Mask

4-4 Register Descriptions

decoder samples the channel read pointers and
maintains the audio sync code read address and the
picture start code address. These addresses are the
current read pointers which are generally 48 addresses
higher than the picture start code and 8 addresses higher
than the audio sync code (due to the size of the top of
channel FIFOs). These can be related to the channel
buffer address stored at the time of the Packetized
Elementary Stream (PES) packet header when the
packet entered the system to allow correlating the packet
to the particular picture or audio frame contained in that
packet.

This bit is cleared when read. INTRn is also asserted
unless the host sets the mask bit.

Picture Start Code Detect Interrupt 1

This bit is set when the decoder detects a picture start
code in the bitstream. The bit is cleared when read.
INTRn is also asserted unless the host sets the mask bit.

SCR Compare Audio Interrupt 2

This bit is set when the System Clock Reference (SCR)
Compare Audio value in Registers 20, 21, 22, and 23
(page 4-16) matches the current SCR value. The SCR
Compare Audio value is different from the main SCR
Compare value.

This bit is cleared when read. INTRn is also asserted
unless the host sets the mask bit.

Reserved 3

Set this bit when writing to Register 1.

Begin Active Video Interrupt 4

The Video Interface module sets this bit and asserts
INTRn (if not masked) at the beginning of active video.
This time is defined by the vertical blanking code (Vcode)
in the Start of Active Video/End of Active Video
(SAV/EAV) timing codes programmed into the Video
Interface.

This bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.

Host Interface Registers 4-5

Begin Vertical Blank Interrupt 5

The Video Interface module sets this bit and asserts
INTRn (if not masked) at the beginning of the vertical
blanking interval. This time is defined by the Vcode in the
Start of Active Video/End of Active Video (SAV/EAV)
timing codes programmed into the Video Interface.

This bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.

SCR Overflow Interrupt 6

This bit is set and when the System Clock Reference
(SCR) counter (page 4-13) overflows. This bit is cleared
when read. INTRn is also asserted unless the host sets
the mask bit.

SCR Compare Interrupt 7

This bit is set when the System Clock Reference (SCR)
Compare mode is enabled and a match between the
value stored in the SCR Compare/Capture registers
(page 4-13) and the current value of the SCR occurs.

This bit is cleared when read. INTRn is also asserted
unless the host sets the mask bit.

Figure 4.3 Register 2 (0x002)

Pack Data Ready Interrupt 0

This bit is set and INTRn is asserted (if not masked) by
the preparser when it detects the start of a pack. The
interrupt alerts the host that the pack header, system
header, and first packet pointer are in the channel buffer.
This bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.

76543210

Read

DTS Video

Event

Interrupt

DTS Audio

Event

Interrupt

Reserved

Seq End

Code in

Video
Channel
Interrupt

Reserved

Video PES

Data Ready

Interrupt

Audio PES

Data Ready

Interrupt

Pack Data

Ready

Interrupt

Write

DTS Video

Event Mask

DTS Audio

Event Mask

Reserved

Seq End

Code in

Video
Channel

Mask

Reserved

Video PES

Data Ready

Mask

Audio PES

Data Ready

Mask

Pack Data

Ready

Mask

4-6 Register Descriptions

Audio PES Data Ready Interrupt 1

This bit is set and INTRn is asserted (if not masked) by
the preparser when it detects an audio PES packet. This
bit is cleared when read. INTRn is not asserted if the host
sets the mask bit.

Video PES Data Ready Interrupt 2

This bit is set and INTRn is asserted (if not masked) by
the preparser when it detects a video PES packet. This
bit is cleared when read. INTRn is not asserted if the host
sets the mask bit.

Reserved 3

Set this bit when writing to this register.

Seq End Code in Video Channel Interrupt 4

This bit is set and INTRn is asserted (if not masked) by
the preparser when it detects a sequence end code in the
video channel. This bit is cleared when read. INTRn is
not asserted if the host sets the mask bit.

Reserved 5

Set this bit when writing to this register.

DTS Audio Interrupt 6

When the chip is in the Audio Read Compare mode
(Register 69, bits 1 and 2, page 4-21), the channel buffer
controller generates a single cycle pulse when the read
pointer in the channel buffer matches a preset value
(Registers 111, 112, and 113, page 4-28). At the pulse,
an internal state machine waits for an audio sync code,
sets this bit, and then generates an interrupt by asserting
the INTRn output signal. The interrupt is used for
audio/video synchronization.

This bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.

DTS Video Event Interrupt 7

When the chip is in the Video Read Compare mode
(Register 69, bit 0, page 4-21), the channel buffer
controller generates a single cycle pulse when the read
pointer in the channel buffer matches to a preset value
(Registers 108, 109, and 110, page 4-28). At the pulse,
an internal state machine waits for a picture start code,
sets this bit, and then generates an interrupt by asserting

Host Interface Registers 4-7

the INTRn output signal. The interrupt is used for
audio/video synchronization.

This bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.

Figure 4.4 Register 3 (0x003)

Audio ES Channel Buffer Overflow Interrupt 0

This bit is set and INTRn is asserted (if not masked)
when the Audio ES channel buffer in SDRAM overflows.
The bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.

Video ES Channel Buffer Overflow Interrupt 1

This bit is set and INTRn is asserted (if not masked)
when the Video ES channel buffer in SDRAM overflows.
The bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.

Reserved [2:3]

Set these bits when writing to this register.

Audio ES Channel Buffer Underflow Interrupt 4

This bit is set and INTRn is asserted (if not masked)
when the Audio ES channel buffer in SDRAM underflows
(becomes empty). The bit is cleared when read. INTRn is
not asserted if the host sets the mask bit.

Video ES Channel Buffer Underflow Interrupt 5

This bit is set and INTRn is asserted (if not masked)
when the Video ES channel buffer in SDRAM underflows
(becomes empty). The bit is cleared when read. INTRn is
not asserted if the host sets the mask bit.

Reserved [7:6]

Set these bits when writing to this register.

76543210

Read Reserved

Video ES

Channel

Buffer

Underflow

Interrupt

Audio ES

Channel

Buffer

Underflow

Interrupt

Reserved

Video ES

Channel

Buffer
Overflow
Interrupt

Audio ES

Channel

Buffer

Overflow

Interrupt

Write Reserved

Video ES

Channel

Buffer

Underflow

Mask

Audio ES

Channel

Buffer

Underflow

Mask

Reserved

Video ES

Channel

Buffer
Overflow

Mask

Audio ES

Channel

Buffer

Overflow

Mask

4-8 Register Descriptions

Figure 4.5 Register 4 (0x004)

VLC or Run Length Error Interrupt 0

This bit is set and INTRn is asserted (if not masked)
when an illegal variable length code (VLC) is detected in
the bitstream, for example:

1. when a start code is found in an unexpected location
in the bitstream, or

2. when there is an error in the run-length parameters
supplied to the IDCT unit.

The bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.

Context Error Interrupt 1

This bit is set and INTRn is asserted (if not masked)
when the Video Decoder detects a parameter in the
bitstream that is not consistent with the context, e.g., an
illegal value. The bit is cleared when read. INTRn is not
asserted if the host sets the mask bit.

Audio CRC or Illegal Bit Error Interrupt 2

This bit is set and INTRn is asserted (if not masked) by
the Audio Decoder when it detects a CRC or illegal bit
error.The bit is cleared when read. INTRn is not asserted
if the host sets the mask bit.

Audio Sync Error Interrupt 3

This bit is set and INTRn is asserted (if not masked)
when an audio sync code is not in the expected location
in the bitstream. The bit is cleared when read. INTRn is
not asserted if the host sets the mask bit.

76543210

Read

S/P DIF

Channel

Buffer

Underflow

Interrupt

Packet

Error

Interrupt

Reserved

Audio Sync

Error

Interrupt

Audio CRC

or Illegal Bit

Error

Interrupt

Context

Error

Interrupt

VLC or Run

Length

Error

Interrupt

Write

S/P DIF

Channel

Buffer

Underflow

Mask

Packet

Error

Interrupt

Mask

Reserved

Audio Sync
Error Mask

Audio CRC

or Illegal Bit

Error Mask

Context

Error Mask

VLC or Run

Length

Error Mask

Host Interface Registers 4-9

Reserved [5:4]

Set these bits when writing to this register.

Packet Error Interrupt 6

This bit is set and INTRn is asserted (if not masked)
when the preparser detects an error while processing
packet data. When this interrupt occurs, the host should
read the Packet Error Status register (page 4-37)to
determine in which packet the error occurred.

The Packet Error Interrupt bit is cleared when read.
INTRn is not asserted if the host sets the mask bit.

S/P DIF Channel Buffer Underflow Interrupt 7

This bit is set and INTRn is asserted (if not masked)
when the S/P DIF read pointer in the Audio ES channel
buffer catches up to the write pointer (all buffer data read
to the S/P DIF Formatter).

The bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.

Figure 4.6 Register 5 (0x005)

Invert Channel Clock R/W 0

When this bit is set, the internal DCK is inverted from the
external DCK clock. By default, the host interface accepts
the DCK and ACLK signals and ORs them together to
generate the internal VALID signal. This assumes that
channel data is available immediately after the rising
edge of DCK. For systems in which the data is available
immediately after the falling edge of DCK, this bit needs
to be set so that the internal VALID signal can be
generated on the falling edge of DCK. Asynchronous
systems can tie DCK to ground.

Channel Request Mode R/W 1

By default, the L64105 expects an external device to
sample the REQn (AREQn and VREQn) signals
synchronously with the system clock of the L64105. If the
external device requires the REQn signals to be

76543210

Reserved

VREQ
Status

AREQ
Status

Channel

Bypass

Enable

Channel

Pause

Channel
Request

Mode

Invert

Channel

Clock

4-10 Register Descriptions

synchronous with the external device clock (DCK), then
the Channel Request Mode bit needs to be set. In this
mode, the channel internal request is sampled twice, first
by the rising edge of internal DCK and then by the falling
edge of internal DCK, before being sent out as a REQn
signal.

Channel Pause R/W 2

Setting this bit prevents the channel request signals
(AREQn and VREQn) from being asserted so channel
data is not transferred into the L64105. The external host
must clear this bit to reassert the REQn signals.

Channel Bypass Enable R/W 3

Setting this bit allows the host to write data directly to the
channel, bypassing the parallel channel input port. Video
ES or Audio ES channel data can be written into
Registers 28 or 29 respectively (page 4-16) when in this
mode. At reset, this register defaults to 0, i.e., no bypass.

AREQ Status R 4

This bit is set when the AREQn signal in the chip is
asserted. This bit position is read only.

VREQ Status R 5

This bit is set when the VREQn signal in the chip is
asserted. This bit position is read only.

Reserved [7:6]

Figure 4.7 Register 6 (0x006)

Clear Interrupt Pin W 0

This bit is used to clear the interrupt signal, INTRn, of
previous pending interrupts. In normal operation, events
in the L64105 can cause INTRn to be asserted if the
event mask is cleared. The bits in the interrupt registers
(Registers 0 through 4) are cleared when read by the
host. However, INTRn remains asserted until all the
interrupt registers are read (all bits cleared) and the Clear
Interrupt Pin bit is set.

7 10

Reserved

Clear

Interrupt Pin

Host Interface Registers 4-11

This separate control is provided for systems with priority
interrupts since this will allow the driver software to exit
the interrupt handler before completion and service
higher priority interrupts. While INTRn is still asserted,
the interrupt handler returns to the interrupt routine for
the L64105 when it is again the highest priority interrupt.

Reserved [7:1]

Figure 4.8 Register 7 (0x007)

Channel Status R 0

This bit indicates the status of the channel at any time.
At reset or power-up, this bit is cleared to indicate that the
channel is stopped. When the Channel Start command is
issued (host writes a 1 to this bit position), the L64105
microcontroller updates this bit to a 1 indicating that the
channel start command has been acknowledged and the
channel has started. When a Channel Reset command is
issued (host writes a 0 to this bit position) the L64105
microcontroller updates this bit to a 0 indicating
acknowledgment of the Channel Reset command and
that the channel is currently stopped.

Channel Start/Reset W 0

Setting this bit starts the channel. Clearing it stops the
channel.

Reserved 1

The default value of this bit is 1 and should NOT be
overwritten with 0.

76543210

Reserved

Software

Reset

SCR Pause Stream Select [1:0] Reserved

Channel

Status

R

Channel

Start/Reset

W

4-12 Register Descriptions

Stream Select [1:0] R/W [3:2]

The host must program these bits to set up the L64105
for the format of the input bitstream as shown in the
following table.

A 0b11 in these bits causes the L64105 to skip packet
searching and byte count matching. Video data is taken
in at the first start code. Subsequent start codes
re-establish the byte alignment. Audio data is not byte
aligned in the channel buffer.

For 0b00 through 0b10, the L64105 parses from the
packet layer and resynchronizes the preparser to the
packet layer start codes on any packet layer errors.

SCR Pause R/W 4

When set, this bit prevents the SCR Counter (Figure 4.9)
from incrementing. However, the SCR Counter can still
be written to by the host (override). When this bit is
cleared, the SCR Counter operates in normal mode, i.e.,
it increments with the system clock. At power-on and
reset, this bit is initialized to 0.

Software Reset W 5

When set by the host, this bit causes the L64105 to reset
(reinitialize). The effect is the same as asserting the hard
reset signal of the chip, RESETn. This reset function
generates a 10-clock cycle reset pulse that resets all
internal modules. All host register values are reinitialized
and need to be reconfigured by the host for proper
operation.

Reserved [7:6]

The default value of these bits is 0b11 and should NOT
be overwritten with 0b00.

Register 8 (0x008) Reserved [7:0]

Stream
Select [1:0] Bitstream Format

0b00 A/V PES Packets
0b01 MPEG-1 System or MPEG-2

Program Stream
0b10 (Not defined)
0b11 A/V Elementary Streams

Host Interface Registers 4-13

Figure 4.9 Registers 9–12 (0x009–0x00C) SCR Value [31:0]

These registers contain the current value of the System Clock Reference
(SCR) Counter. The host must read Register 9, the LSB, first. This
captures the upper 24 bits and writes them into Registers 10, 11, and

12. The host must set the SCR Pause bit in Register 8 before writing to
these registers.

Figure 4.10 Registers 13–16 (0x00D–0x010) SCR Compare/Capture [31:0]

At reset, these registers are initialized to 0xFFFF.FFFF. They can be
configured in two ways. If the SCR Compare/Capture Mode in Register
17 is set to 0b10, the host can write in any value to generate an interrupt
when the SCR Counter reaches that value.

If the SCR Compare/Capture Mode is set to 0b01, the L64105 captures
the SCR Counter value at an event specified by the host and writes the
SCR value to these registers. The capture can be triggered when any
one of the bits in Registers 17 or 18 is set and the corresponding event
occurs.

7 0

Reg. 9

LSB

SCR Value [7:0]

R/W

Reg. 10

SCR Value [15:8]

R/W

Reg. 11

SCR Value [23:16]

R/W

Reg. 12

MSB

SCR Value [31:24]

R/W

7 0

Reg. 13

LSB

SCR Compare/Capture [7:0]

R/W

Reg. 14

SCR Compare/Capture [15:8]

R/W

Reg. 15

SCR Compare/Capture [23:16]

R/W

Reg. 16

MSB

SCR Compare/Capture [31:24]

R/W

4-14 Register Descriptions

Figure 4.11 Register 17 (0x011)

SCR Compare/Capture Mode [1:0] R/W 1:0

The value of these two bits sets the operating mode of
Registers 13, 14, 15, and 16 as shown in the following
table.

Capture on Picture Start Code R/W 2

When this bit is set and the L64105 is in the Capture
Mode, the SCR Counter value is captured and written to
Registers 13 through 16 when the preparser detects the
Picture Start Code.

Capture on Audio Sync Code R/W 3

When this bit is set and the L64105 is in the Capture
Mode, the SCR Counter value is captured and written to
Registers 13 through 16 when the preparser detects the
Audio Sync Code.

Capture on Beginning of Active Video (BAV) R/W 4

When this bit is set and the L64105 is in the Capture
Mode, the SCR Counter value is captured and written to
Registers 13 through 16 when the preparser detects the
Beginning of Active Video.

Capture on Pack Data Ready R/W 5

When this bit is set and the L64105 is in the Capture
Mode, the SCR Counter value is captured and written to
Registers 13 through 16 when the preparser detects
Pack Data Ready.

76543210

Capture on
Video PES

Ready

Capture on

Audio PES

Ready

Capture on

Pack Data

Ready

Capture on

BAV

Capture on
Audio Sync

Code

Capture on

Picture Start

Code

SCR Compare/Capture

Mode

Mode Bits Mode

0b00 No compare and capture.

SCR overflow works.
0b01 Capture
0b10 Compare
0b11 Reserved

Host Interface Registers 4-15

Capture on Audio PES Ready R/W 6

When this bit is set and the L64105 is in the Capture
Mode, the SCR Counter value is captured and written to
Registers 13 through 16 when the preparser detects
Audio PES Ready.

Capture on Video PES Ready R/W 7

When this bit is set and the L64105 is in the Capture
Mode, the SCR Counter value is captured and written to
Registers 13 through 16 when the preparser detects
Video PES Ready.

Figure 4.12 Register 18 (0x012)

Reserved [2:0]

Clear these bits when writing to this register.

Capture on DTS Video R/W 3

When this bit is set and the L64105 is in the Capture
Mode, the SCR Counter value is captured and written to
Registers 13 through 16 when the preparser detects
Decode Time Stamp (DTS) Video.

Capture on DTS Audio R/W 4

When this bit is set and the L64105 is in the Capture
Mode, the SCR Counter value is captured and written to
Registers 13 through 16 when the preparser detects DTS
Audio.

Reserved [7:5]

Clear these bits when writing to this register.

Figure 4.13 Register 19 (0x013)

Audio Start on Compare R/W 0

When the L64105 is in the Compare Mode, setting this
bit generates a single-cycle, autostart pulse for starting
the Audio Decoder when the current value of the SCR
Counter is equal to the value in the SCR Compare Audio

7 5432 0

Reserved

Capture on
DTS Audio

Capture on
DTS Video

Reserved

7 210

Reserved

Video Start

on Compare

Audio Start

on Compare

4-16 Register Descriptions

register. This autostart pulse also clears the Audio Start
on Compare bit. The Audio Decoder must be in Pause
Mode for the autostart signal to be effective.

Video Start on Compare R/W 1

When the L64105 is in the Compare Mode, setting this
bit generates a single-cycle, autostart pulse to start the
Video Decoder when current value of the SCR Counter
is equal to the value in the SCR Compare register. This
bit is cleared after the autostart signal is generated.

Reserved [7:2]

Figure 4.14 Registers 20–23 (0x014–0x017) SCR Compare Audio [31:0]

When the Audio Start on Compare bit in Register 19 (Figure 4.13) is set,
the SCR Compare/Capture mode is Compare, and the SCR Counter
reaches the value in these registers, an autostart pulse is generated to
start the Audio Decoder.

The compare also sets the SCR Compare Audio Interrupt bit (bit 2 in
Register 1, page 4-4) and asserts the INTRn signal to the host if not
masked. The Audio Start on Compare bit is cleared when the compare
event occurs.

Registers 24–27 (0x018–0x01B) Reserved [7:0]

Figure 4.15 Register 28 (0x01C) Video Channel Bypass Data [7:0]

7 0

Reg. 20

LSB

SCR Compare Audio [7:0]

R/W

Reg. 21

SCR Compare Audio [15:8]

R/W

Reg. 22

SCR Compare Audio [23:16]

R/W

Reg. 23

MSB

SCR Compare Audio [31:24]

R/W

7 0

Video Channel Bypass Data [7:0]

W

Video Decoder Registers 4-17

Setting the Channel Bypass Enable bit (bit 3 in Register 5 - page 4-10)
allows the host to write data directly to the video channel through this
register, bypassing the parallel channel input port.

Figure 4.16 Register 29 (0x01D) Audio Channel Bypass Data [7:0]

Setting the Channel Bypass Enable bit (bit 3 in Register 5 - page 4-10)
allows the host to write data directly to the audio channel through this
register, bypassing the parallel channel input port.

Registers 30–63 Reserved [7:0]

4.2 Video Decoder Registers

Figure 4.17 Register 64 (0x040)

Aux Data FIFO Status [1:0] R [1:0]

The states of these bit indicate the status of the Aux Data
FIFO as shown in the following table. Once “overrun”
(0b11) occurs, the status stays at overrun until the
register is read.

Reset Aux Data FIFO W 0

Writinga1tothis bit resets the Aux Data FIFO to empty.
Any data in the FIFO at this time is lost.

7 0

Audio Channel Bypass Data [7:0]

W

7 54 210

Reserved Aux Data Layer ID [2:0]

Aux Data FIFO Status [1:0]

R

Read Only

Reset Aux
Data FIFO

W

Bits Status

0b00 Empty
0b01 Data ready
0b10 Full
0b11 Overrun

4-18 Register Descriptions

Aux Data Layer ID [2:0] R [4:2]

The Aux Data Layer ID indicates the layer origin of the
physical parameter of the current Aux Data FIFO output.
Reading the ID does NOT change the FIFO status.
Reading the current byte in the Auxiliary Data FIFO
Output register (page 4-19) may change the Aux Data
Layer ID. The host should always read this layer ID
register before reading the FIFO output register. The IDs
for the layers are defined in the following table.

Reserved [7:5]

Figure 4.18 Register 65 (0x41)

User Data FIFO Status [1:0] R [1:0]

The following table shows the user data FIFO status
codes and their meanings. Once “overrun” (11) occurs it
stays at overrun until the status is read.

Reset User Data FIFO W 0

Writinga1tothis bit position resets the User Data FIFO
to empty. Any data currently in the FIFO is lost.

Bits Layer

0b100 Packet
0b000 Sequence
0b001 Group of pictures
0b010 Picture
0b111 Extension layer

(picture or sequence)

743210

Reserved User Data Layer ID [1:0]

User Data FIFO Status [1:0]

R

Read Only

Reset User

Data FIFO

W

Bits Status

0b00 Empty
0b01 Data ready
0b10 Full
0b11 Overrun