LSI L64005 Technical Manual

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L64005

Enhanced MPEG-2

Audio/Video Decoder

Technical Manual

Final Edition May 1998

This document contains proprietary information of LSI Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an ofﬁcer of LSI Corporation.

Document DB14-000045-00, Final Revision F (May, 1998) This document describes revisions D through F of LSI Logic Corporation’s L64005 MPEG-2 Audio/Video Decoder and will remain the ofﬁcial reference source for all revisions/releases of this product until rescinded by an update.

To receive product literature, call us at 1.800.574.4286 (U.S. and Canada); +32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, and Europe) and ask for Department JDS; or visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.

In particular, supply of the LSI Logic IC L64005 does not convey a license or imply a right under certain patents and/or other industrial or intellectual proper ty rights claimed by IRT, CCETT and Philips, to use this IC in any ready-to-use electronic product. The purchaser is herby notiﬁed that Philips, CCETT and IRT are of the opinion that a generally available patent license for such use is required from them. No warranty or indemnity of any sort is provided by LSI Logic regarding patent infringement.

LSI Logic logo design is a registered trademark of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies.

Preface

This book is the primary reference and technical manual for the L64005 MPEG-2 Audio/Video Decoder. It contains a complete functional description and includes complete physical and electrical speciﬁcations for the L64005.

Audience This document assumes that you have some familiarity with microproces-

sors and related support devices. The people who beneﬁt from this book are:

♦ Engineers and managers who are evaluating the processor for pos-

sible use in a system

♦ Engineers who are designing the processor into a system

Organization This document has the following chapters:

♦ Chapter 1 Introduction, describes the system interface and the

architecture of the L64005 MPEG-2 Audio/Video Decoder.

♦ Chapter 2 Registers, discusses the L64005 internal registers. It also

provides a description of the internal memory mapping and how the registers are accessed from the system interface. This chapter is intended primarily for system programmers who are developing software drivers.

♦ Chapter 3 Signals, provides detailed information on the L64005 sig-

nals. The signal descriptions are useful for hardware designers who are interfacing the L64005 with other devices.

♦ Chapter 4 Video Data Flow, This chapter describes the MPEG bit-

stream construction, parsing and error handling as well as the operation of the channel buffer.

L64005 MPEG-2 Audio/Video Decoder Technical Manual iii

♦ Chapter 5 External Memory Interface, describes the frame mem-

ory interface.

♦ Chapter 6 Video Interface and On-Screen Display, describes the

L64005 video interface and video timing characteristics.

♦ Chapter 7 Audio Decoder, describes the details of the integrated

two channel Musicam (MPEG) audio decoder.

♦ Chapter 8 System Stream Decoding and Synchronization,

describes the resources that the L64005 provides for parsing an MPEG system stream.

♦ Chapter 9 Speciﬁcations, speciﬁes the L64005 electrical and

mechanical characteristics.

♦ Appendix A Interfacing the L64005 to 5-V Signals, describes how

to interface LSI Logic’s 3.3-V L64005 MPEG-2 Audio/Video Decoder to 5-V signals.

♦ Customer Feedback.

Related Publications

Conventions Used in This Manual

ISO/IEC 13818,

Audio

(MPEG-2), Draft International Standard.ISO/IEC Copyright Ofﬁce,

Case Postal 56, CH1211 Genève 20, Switzerland. ISO/IEC 11172 (1993),

Generic Coding of Moving Pictures and Associated

Information Technology—Coding of Moving Pic-

ture and Associated Audio for Digital Storage Media at up to about

1.5 Mbit/s L64002 MPEG-2 Audio/Video Decoder Technical Manual

Corp.

L64007 MPEG-2 Transport Demultiplexer

Unless otherwise speciﬁed,

MSB

signiﬁcant bit or byte.The ﬁrst time a word or phrase is deﬁned in this manual, it is

The following signal naming conventions are used throughout this manual:

(MPEG-1).

, LSI Logic Corp.

MPEG

refers to the MPEG-2 standard.

indicates the most-signiﬁcant bit or byte.

italicized.

, LSI Logic

LSB

indicates the least-

iv Preface

♦ A level-signiﬁcant signal that is true or valid when the signal is LOW

always has an overbar ( ) over its name.

♦ An edge-signiﬁcant signal that initiates actions on a HIGH-to-LOW

transition always has an overbar ( ) over its name.

Revision History

The word

deassert

assert

means to drive a signal true or active. The word

means to drive a signal false or inactive.

Hexadecimal numbers are indicated by the preﬁx “0x” before the number—for example, 0x32CF. Binary numbers are indicated by a subscripted “2” following the number—for example, 0011.0010.1100.11112.

This section lists the changes in this document from initial release to the current version.

Version Release Date Comments

L64005.ADV.0 March 4, 1996 Initial release L64005.ADV.1 August 23, 1996 Major modiﬁcations to most chapters.

L64005.Final May 11, 1998 Minor changes to most chapters.

Changed register map, pinout, and signal descriptions. Added Section

6.3, “Reduced Memory Mode, ” Section

3.6, “PLL Interface,” and Section 5.5, “Channel Buffer Architecture”.

Added corrections from document review and relevant items from L64005 Rev. E and F ECNs.

Notice for L64002 Users

This section is for customers using the L64002, and who want to upgrade to the L64005. The following is a brief description of the pertinent changes, with emphasis on pinout and necessary software changes.

Please note: LSI Logic recommends building new boards to ensure L64005 to L64002 compatibility. A simple 0 Ω resistor jumper (for pin 69) allows switching between the loop ﬁlter and the CAS signal.

Pinout Changes If the L64005 is used with fast page mode DRAM, then a few changes

are needed. For further information, please refer to Chapter 9: Speciﬁcations.

L64005 MPEG-2 Audio/Video Decoder Technical Manual v

♦ Pin 64 is CAS for the L64005, not BA9 (BA9 has been removed). ♦ For Rev. E and F devices Pin 69 is now not connected (NC) and no

external loop ﬁlter is required. The ﬁlter may be left in place on any board that already has it designed in. For the L64005 Rev. D, Pin 69 is LP2. Regardless of the DRAM mode used, an external loop ﬁlter must be included in the design (requires one resistor and two capacitors for an off-chip loop ﬁlter).

♦ The DRAM interface now supports both regular and synchronous

DRAM modes. See Section 5.3.2, “Synchronous DRAM Mode,” for more information on the SDRAM interface.

♦ New AC timing speciﬁcations and drawings have been added to Sec-

tion 9.1

♦ Pin 68 is Analog VDD (AVDD), and pin 70 is Analog GND (AGND).

These pins must be isolated from other VDD and VSS pins.

♦ Please note that the L64005 has an on-chip PLL, so the 27-MHz

input clock must have low jitter (<300ps).

♦ The duty cycle for SYSCLK has been speciﬁed slightly differently.

Please refer to Chapter 9, Speciﬁcations, for details.

Software Changes

A few changes must be made to L64005 supporting software.

♦ Bit 0in Group 7, Register 27 must be set for reduced memory mode

(1=RMM, 0=Normal).

♦ If reduced memory mode is used, Group 7, Register 27, Bits [7:2]

must be set to determine the number of 8-line segments used for a B-frame decode.

♦ Bits [4:3] of Group 7, Register 1 are no longer used for PMCT (1CAS

enable) or 512-page size select. In the L64005, bits [4:3] are used to select the DRAM mode. Refer to Chapter 2 for more details.

♦ In the L64005 32-bit mode is not supported. Bit 5 of Group 7, Reg-

ister 1 is now reserved.

♦ Bit 6 of Group 7, Register 26 controls line doubling for the interlaced

display mode.

♦ In the L64005, bits [7:0] in Group 7, Register 28 contains the hori-

zontal word origin of the luma and the chroma.

vi Preface

♦ Additional ﬁeld status bits have been added to the register map. Odd

Field First and Last Active Field have been added to Group 6, Register 31, Bits [3:2]. Refer to Section 2.8.18, “Group 6 Display Mode 1” for more details.

L64005 MPEG-2 Audio/Video Decoder Technical Manual vii

viii Preface

Chapter 1 Introduction

1.1 Video Compression and Decompression Concepts 1-1

1.1.1 Video Encoding 1-2

1.1.2 Bitstream Syntax 1-5

1.1.3 Video Decoding 1-7

1.2 Audio Compression and Decompression Concepts 1-8

1.2.1 MPEG Audio Encoding 1-8

1.2.2 Audio Decoding 1-11

1.3 Standards Compliance 1-11

1.3.1 MPEG-1 1-12

1.3.2 MPEG-2 1-12

1.4 Ter ms and Concepts 1-12

1.5 System Overview 1-17

1.5.1 Video Decoding 1-17

1.5.2 Audio Decoding 1-17

1.5.3 Post Processing 1-18

1.5.4 On-Screen Display 1-18

1.5.5 PES Decoding 1-18

1.5.6 Video Output 1-19

1.5.7 Audio Output 1-19

1.5.8 User Interface 1-19

1.5.9 Memory Utilization 1-19

1.5.10 Error Concealment 1-20

1.5.11 Mechanical and Electrical 1-20

1.6 L64005 Overview 1-20

1.6.1 MPEG-2 Video Decoder 1-20

1.6.2 System Layer Decoding 1-21

1.6.3 Video Output Features 1-21

1.6.4 On-Screen Display 1-24

1.6.5 Audio Decoder 1-24

L64005 MPEG-2 Audio/Video Decoder Technical Manual ix

1.6.6 System Controller Interface 1-25

1.6.7 Channel Interface 1-27

1.6.8 Bitstream Syntax and Grammar 1-27

1.7 Features 1-28

Chapter 2 Registers

2.1 L64005 Register Overview 2-1

2.1.1 Writing a Single Register 2-14

2.1.2 Reading or Writing Multiple Registers

2.2 Group 0 Address Indirection Register 2-15

2.3 Group 1 Status 0 Register 2-16

2.4 Group 2 Status 1 Register 2-18

2.5 Group 3 Interrupt Register 0 2-19

2.6 Group 4 Interrupt Register 1 2-21

2.7 Group 5 Control Register 2-22

2.8 Group 6 Secondary Control Registers 2-23

2.8.1 Group 6 User Data FIFO 2-23

2.8.2 Group 6 Error Status Register 2-24

2.8.3 Group 6 Forward Anchor Luma

2.8.4 Group 6 Forward Anchor Chroma

2.8.5 Group 6 Backward Anchor Luma

2.8.6 Group 6 Backward Anchor Chroma

2.8.7 Group 6 Display Luma Base Address 2-27

2.8.8 Group 6 Display Chroma Base Address 2-27

2.8.9 Group 6 VBI1 Luma Base Address 2-28

2.8.10 Group 6 VBI1 Chroma Base Address 2-28

2.8.11 Group 6 VBI2 Luma Base Address 2-29

2.8.12 Group 6 VBI2 Chroma Base Address 2-29

2.8.13 Group 6 VBI Size 2-30

2.8.14 Group 6 OSD Control Register 2-30

2.8.15 Group 6 OSD Field 1 Pointer 2-31

2.8.16 Group 6 OSD Field 2 Pointer 2-32

2.8.17 Group 6 Display Mode 0 2-32

in a Group 2-15

Base Address 2-25

Base Address 2-26

Base Address 2-27

x Contents

2.8.18 Group 6 Display Mode 1 2-33

2.8.19 Group 6 Raster Mapper Increment 2-34

2.8.20 Group 6 Display Controller Status 2-35

2.8.21 Group 6 Video PES Buffer Start Address 2-36

2.8.22 Group 6 Video PES Buffer End Address 2-37

2.8.23 Group 6 Audio PES Buffer Start Address 2-37

2.8.24 Group 6 Audio PES Buffer End Address 2-38

2.8.25 Group 6 Video Channel Buffer Start Address 2-38

2.8.26 Group 6 Video Channel Buffer End Address 2-39

2.8.27 Group 6 Audio Channel Buffer Start Address 2-39

2.8.28 Group 6 Audio Channel Buffer End Address 2-40

2.8.29 Group 6 Audio Mode Control 2-40

2.8.30 Group 6 Audio Oscillator Frequency Control 2-41

2.8.31 Group 6 Audio Parameter 0 2-42

2.8.32 Group 6 Audio Parameter 1 2-44

2.8.33 Group 6 Audio Trick Modes 2-45

2.8.34 Group 6 Reserved Registers 2-47

2.9 Group 7 Secondary Control Registers 2-47

2.9.1 Group 7 Auxiliary Data FIFO 2-47

2.9.2 Group 7 DRAM Control 2-51

2.9.3 Group 7 DRAM Address 2-52

2.9.4 Group 7 DRAM Data 2-53

2.9.5 Group 7 Horizontal Sync Width 2-54

2.9.6 Group 7 Equalization Pulse Width 2-54

2.9.7 Group 7 Serration Pulse Width 2-54

2.9.8 Group 7 Horizontal Blank Pulse Width 2-55

2.9.9 Group 7 Active Image Done 2-55

2.9.10 Group 7 Half Line Time 2-55

2.9.11 Group 7 Upper Bits 2-55

2.9.12 Group 7 Pre-Blank/Equalization 2-56

2.9.13 Group 7 Post-Blank/Equalization 2-56

2.9.14 Group 7 Main/Serration Lines 2-57

2.9.15 Group 7 Scan Half Lines 2-57

2.9.16 Group 7 Main Reads Per Line 2-57

2.9.17 Group 7 Display Width 2-58

2.9.18 Group 7 Pan and Scan Control 2-58

2.9.19 Group 7 Reduced Memory Mode Control 2-59

2.9.20 Group 7 Reserved Registers 2-60

L64005 MPEG-2 Audio/Video Decoder Technical Manual xi

Chapter 3 Signals

3.1 User Interface 3-2

3.2 Channel Interface 3-4

3.3 Memory Interface 3-7

3.4 Video Interface 3-9

3.5 Audio Interface 3-10

3.6 PLL Interface 3-11

2.9.21 Group 7 Video Output Mode Control 2-60

2.9.22 Group 7 Channel Buffer Read Address 2-61

2.9.23 Group 7 Picture Start Code Read Address 2-62

2.9.24 Group 7 Audio Sync Code Read Address 2-62

2.9.25 Group 7 Reserved Registers 2-62

2.9.26 Group 7 DRAM Source Address Registers 2-63

2.9.27 Group 7 DRAM Transfer Count Registers 2-63

2.9.28 Group 7 DRAM Transfer Mode Register 2-63

2.9.29 Group 7 Revision ID Register 2-64

2.9.30 Group 7 Video Tr ick Modes 2-64

2.9.31 Group 7 System Clock Reference (SCR) Value 2-66

2.9.32 Group 7 SCR Compare Value 2-66

2.9.33 Group 7 Reserved Registers 2-66

3.2.1 Parallel Channel Writes 3-6

3.2.2 Serial Channel Writes 3-6

3.3.1 Regular DRAM Signals 3-7

3.3.2 Synchronous DRAM Signals 3-8

Chapter 4 Video Data Flow

4.1 Overview 4-1

4.2 Channel Data Parsers 4-1

4.2.1 Pre-Parser Operation 4-3

4.2.2 Post-Parser Operation 4-6

4.3 Channel Buffer Operation 4-10

4.3.1 Channel Buffer Hardware 4-10

4.3.2 User Data Buffer 4-11

4.3.3 Auxiliary Data Buffer 4-12

4.4 Elementary Stream Decoding 4-13

xii Contents

Chapter 5 External Memory Interface

5.1 Overview 5-1

5.2 Memory Architecture 5-1

5.3 Memory Interface 5-2

5.3.1 Regular DRAM Mode 5-2

5.3.2 Synchronous DRAM Mode 5-3

5.3.3 DRAM Transfer Modes 5-4

5.3.4 Read/Write 5-12

5.3.5 Refresh Cycles 5-16

5.4 Memory Map 5-17

5.4.1 Luma Frame Organization 5-19

5.4.2 Chroma Frame Organization 5-19

5.4.3 Random Read/Write to Frame Store 5-19

5.5 Channel Buffer Architecture 5-19

5.5.1 Video PES Buffer 5-21

5.5.2 Audio PES Buffer 5-22

5.5.3 Video Channel Buffer 5-22

5.5.4 Audio Channel Buffer 5-22

Chapter 6 Video Interface and On-Screen Display

6.1 Video Output Format 6-1

6.1.1 Post-Processing 480- and 576-Line Images 6-2

6.1.2 Post-Processing 240- and 288-Line Images 6-4

6.1.3 Selecting the Post-Processing Mode 6-5

6.2 Video Resolution 6-6

6.3 Reduced Memory Mode 6-7

6.4 Horizontal Post-Processing Filter 6-8

6.4.1 Filter Speciﬁcation 6-8

6.4.2 Setting the Filter Raster Mapper Increment 6-10

6.4.3 Setting the Start Phase of the Filter 6-11

6.4.4 Filter Inhibit 6-11

6.4.5 Video Data and OSD 6-11

6.5 Display Control Parameters 6-11

6.5.1 Video Raster Timing (Master Mode 6-12

6.5.2 VCode Delay 6-17

6.5.3 Slave Mode 6-17

L64005 MPEG-2 Audio/Video Decoder Technical Manual xiii

6.5.4 Adaptive Modiﬁcation of Video Raster for Copy Protection 6-18

6.6 Pan and Scan Operation 6-18

6.7 Display Trick Modes 6-19

6.7.1 Trick Mode Decoding 6-19

6.8 3:2 Pull-Down 6-22

6.9 On-Screen Display 6-23

6.9.1 Color Palette 6-23

6.9.2 Operation of the OSD Controller 6-24

6.9.3 OSD Control Registers 6-25

6.9.4 Alpha Blending 6-31

6.9.5 High Color Operation 6-31

6.9.6 Bitmap Storage 6-31

6.9.7 Use of the OSDA Field 6-31

6.9.8 Alignment of the Bitmap 6-32

6.9.9 OSD Control 6-32

6.9.10 Limitations in the OSD Controller 6-32

6.9.11 OSD Compatibility Mode 6-33

6.9.12 Accessing the Overlay Bitmaps 6-34

6.10 Interrupts from the Display Controller 6-34

Chapter 7 Audio Decoder

7.1 Audio Decoder Overview 7-1

7.2 Decoder Programming 7-1

7.2.1 Reading the Audio Parameters 7-1

7.2.2 Starting, Stopping and Controlling the Rate of the Decoder 7-2

7.2.3 Setting the DAC Interface Mode 7-3

7.2.4 Setting the Output Sample Rate 7-3

7.2.5 Determining the Presentation Time 7-6

7.2.6 Ancillary Channel Data 7-6

7.2.7 Error Detection 7-6

7.2.8 Output Control 7-8

Chapter 8 System Stream Decoding and Synchronization

8.1 System Parser Basics 8-1

xiv Contents

8.1.1 Parsing a Program Stream 8-2

8.1.2 Parsing a Transport Stream 8-4

8.2 Reading the System Header Data 8-5

8.2.1 System Parser Control Bits 8-5

8.3 Synchronization Basics 8-7

8.4 L64005 Synchronization Resources 8-10

8.4.1 L64005 Video Skip and Repeat Frame 8-13

8.4.2 Video Decoding and Presentation Schedule 8-15

8.4.3 Audio Decoder Rate Control 8-16

8.5 Audio/Video Synchronization Technique 8-17

8.5.1 Clock Recovery 8-19

8.5.2 Creating Audio and Video PTS list 8-20

8.5.3 Picture Header Interrupt and AUX

8.5.4 Ver tical Sync Interrupt 8-26

8.5.5 Audio Sync Interrupt 8-26

8.6 Real System Considerations 8-28

Chapter 9 Speciﬁcations

9.1 AC Timing 9-2

9.2 Electrical Requirements 9-14

9.3 Pin Summary 9-15

9.4 Packaging 9-18

FIFO Interrupt 8-23

Appendix A Interfacing the L64005 to 5-V Signals

A.2 JEDEC LVTTL Interface Standards A-1 A.3 L64005 5V-Compatible I/Os A-2

9.4.1 5V-Compatible Input Buffers A-3

9.4.3 Passive Resistor Loads and 5-V Compatible Outputs A-5

9.4.5 Open Drain Outputs A-7

A.4 Mixed Voltage System Design Considerations A-8 A.5 Engineering Practice for Mixed Voltage Systems A-8

9.4.6 Precautions During Power Sequencing A-8

9.4.7 Precautions to Avoid Bus Contention A-9

9.4.8 Precautions During Power Failure A-9

L64005 MPEG-2 Audio/Video Decoder Technical Manual xv

Appendix B Customer Feedback

List of Figures

1.1 MPEG Macroblock Structure 1-3

1.2 Typical Sequence of Frames in Display Order 1-6

1.3 Typical Sequence of Frames in Bitstream Order 1-6

1.4 Audio Encoding Process (Simpliﬁed) 1-9

1.5 ISO System Stream 1-9

1.6 MPEG Audio Packet Structure 1-10

1.7 System Block Diagram 1-18

2.1 Address Indirection Register 2-15

2.2 Status 0 Register 2-16

2.3 Status 1 Register 2-18

2.4 Group 3 Interrupt Register 0 2-20

2.5 Group 4 Interrupt Register 1 2-21

2.6 Group 5 Control Register 2-22

2.7 LAF and ODFF Bit Fields 2-36

2.8 DRAM Control Register 2-51

2.9 Active Image Done Register 2-55

2.10 Scan Half Lines Register 2-57

3.1 L64005 Logic Symbol 3-2

3.2 Parallel Channel Input Timing 3-6

3.3 Serial Channel Input Timing 3-7

3.4 Master Mode 3-10

3.5 External Loop Filter 3-12

4.1 Summary of the Bitstream Parsing Operations 4-2

4.2 Conceptual System Synchronization 4-3

4.3 Synchronization at the System Level 4-4

4.4 Successful and Unsuccessful Frame Skips 4-14

5.1 Regular DRAM Interface 5-3

5.2 Synchronous DRAM Interface 5-4

5.3 The Single Word Write Routine 5-6

5.4 Multiple Word Write Routine 5-7

5.5 Single Word Read Routine 5-8

5.6 Multiple Word Read Routine 5-9

5.7 Regular DRAM Read and Write Timing 5-12

xvi Contents

5.8 Synchronous DRAM Read and Write Timing 5-15

5.9 Regular DRAM Refresh Timing 5-16

5.10 Synchronous DRAM Refresh Timing 5-17

5.11 Memor y Map of L64005 5-18

5.12 Channel Buffer Organization in L64005 5-21

6.1 Composite Sync and Composite Blank 6-2

6.2 Effect of Ver tical Resolution and Blanking 6-6

6.3 Frequency and Phase Response A 6-9

6.4 Impulse Response A 6-9

6.5 Frequency and Phase Response B 6-9

6.6 Impulse Response B 6-10

6.7 Video Timing Chain Nomenclature 6-12

6.8 Horizontal Sync Timing 6-13

6.9 Display Parameters 6-14

6.10 Freeze Frame for One Frame Time 6-20

6.11 Freeze Frame for One Field Time 6-21

6.12 Pull-Down Field Order 6-22

6.13 Pointers to Overlay Display Lists 6-24

6.14 OSD File Organization 6-26

6.15 Region Attribute Bits 6-27

6.16 Color Fields 6-28

6.17 Color Attribute Bits 6-29

6.18 Color Extension Bits 6-29

8.1 MPEG-2 Transpor t Encoder 8-7

8.2 Audio and Video Sync train 8-8

8.3 Local Counter and Comparator Logic 8-11

8.4 Interrupt at each Vertical Sync 8-11

8.5 Audio and Video Decode Interrupts 8-12

8.6 System Header Interrupt 8-13

8.7 Video Skip 8-14

8.8 Video Repeat 8-14

8.9 Buffer Organization In L64005 Memory 8-21

8.10 PES Header Structure 8-22

8.11 List of Pending PUs for Video and Audio 8-23

8.12 PTS Association with Presentation Unit 8-24

8.13 Picture Type Routine 8-25

8.14 Audio PTS Association 8-27

8.15 Audio Sync Algorithm 8-28

L64005 MPEG-2 Audio/Video Decoder Technical Manual xvii

9.1 AC Test Load and Waveform for Standard Outputs 9-3

9.2 AC Test Load and Waveform for 3-State Outputs 9-3

9.3 DRAM Write Cycle 9-7

9.4 DRAM Read Cycle 9-8

9.5 Sync DRAM Write Cycle 9-9

9.6 Sync DRAM Read Cycle 9-10

9.7 Parallel Channel Write Timing 9-11

9.8 Host Write Timing 9-11

9.9 Host Read Timing 9-12

9.10 Serial Data Input 9-12

9.11 Reset 9-13

9.12 Video Timing 9-13

9.13 Serial PCM Data Out Timing 9-13

9.14 L64005 Pinout Diagram for Regular DRAM 160-Pin PQFP 9-21

9.15 L64005 Pinout Diagram for Synchronous DRAM 160-Pin PQFP 9-22

9.16 160-Pin Copper Lead Frame PQFP Mechanical Drawing 9-23

A.17 5V Interface Conﬁgurations A-3 A.18 5V-Compatible Output Buffer, Open Drain A-7

List of Tables

1.1 MPEG Compressed Bitstream Syntax 1-5

2.1 Register Groups and Function 2-2

2.2 L64005 Register Map 2-2

2.3 User Data FIFO 0 2-23

2.4 VLD Parameters 2-48

5.1 Mapping of Physical Address Bus to BA[8:0] 5-3

5.2 Mapping of Physical Address Bus to SBA[11:0] 5-4

5.3 Word Accesses vs. 81MHz Clock Cycles

5.4 Word Accesses Vs. 81MHz Clock Cycle

5.5 Channel Buffer Architecture 5-20

6.1 Post-processing modes 6-3

6.2 Chroma Line Repeat: Coefﬁcients for Odd

xviii Contents

in Regular DRAM Mode 5-13

in SDRAM Mode 5-14

and Even Fields 6-3

6.3 Luma Processing: Coefﬁcients for Even and Odd Fields 6-4

6.4 Chroma Processing: Coefﬁcients for Even and Odd Fields 6-5

6.5 Memory Mode Speciﬁcations 6-8

6.6 Raster Mapper Increment by Source Resolution 6-11

6.7 Horizontal Timing of NTSC TV Systems 6-15

6.8 Horizontal Timing of PAL TV Systems 6-16

6.9 Vertical Timing of Common TV Systems 6-17

6.10 Pull-Down Mode Bits 6-23

6.11 Conversion from 4:4:4 to 4:2:2 6-32

7.1 Typical Values for NCO at 27 MHz fd 7-5

7.2 Location of Maskable Interrupts 7-7

8.1 Levels of Hierarchy in MPEG-1 and MPEG-2 System Syntax 8-2

8.2 DRAM Map of an MPEG-2 Packet Header Structure in the Elementary Stream with Write Pointer 8-6

8.3 Audio and Video DTSs and PTSs 8-10

8.4 Decode to Display Delay 8-15

8.5 Audio Input Clock is 256 fs 8-17

8.6 Audio Input Clock is 384 fs 8-17

9.1 AC Test Conditions 9-2

9.2 AC Timing Values 9-4

9.3 Absolute Maximum Ratings 9-14

9.4 Recommended Operating Conditions 9-14

9.5 Capacitance 9-14

9.6 DC Characteristics 9-15

9.7 Pin Description Summary 9-16

9.8 L64005 Ordering Information 9-18

9.9 Alphabetical Pin List by Signal Name for Regular DRAM 160-Pin PQFP 9-19

9.10 Alphabetical Pin List by Signal Name for Synchronous DRAM 160-Pin PQFP 9-20

A.11 DC Logic Levels A-2 A.12 DC Characteristics A-4 A.13 ibuf (3.3V Input), LVTTL AC Characteristics A-4 A.14 ibuff, LVTTL Input Buffer, Non-inverting,

5V-Compatible A-4

L64005 MPEG-2 Audio/Video Decoder Technical Manual xix

A.15 DC Characteristics without Resistor Load A-6 A.16 3-State Output Buffer, 5 V-Compatible

AC Characteristics A-7

xx Contents

Chapter 1 Introduction

This chapter describes the system interface and the architecture of the L64005 MPEG-2 Audio/Video Decoder, and contains the following sections:

♦ Section 1.1, “Video Compression and Decompression Concepts” ♦ Section 1.2, “Audio Compression and Decompression Concepts” ♦ Section 1.3, “Standards Compliance” ♦ Section 1.4, “Ter ms and Concepts” ♦ Section 1.5, “System Overview” ♦ Section 1.6, “L64005 Overview” ♦ Section 1.7, “Features”

Sections 1.1 through 1.4 explain in general terms the requirements of the Moving Picture Expert’s Group MPEG-2 International Standard (IS) 13818 as applied to video compression and decompression. These sections provide a good foundation for the L64005-speciﬁc discussion that follows in Sections 1.5 through 1.7.

1.1 Video Compression and Decompression Concepts

The MPEG standard deﬁnes a format for compressed digital video. Encoders designed to work within the conﬁnes of the standard compress video information, and decoders decompress it.

The MPEG algorithms for video compression and decompression are ﬂexible, but generally ﬁt the following criteria:

♦ Data rates are about 1 to 1.5 Mbit/s for MPEG-1 and up to 15 Mbit/s

for MPEG-2. The L64005 MPEG-2 decoder’s channel interface is capable of supporting a 20 Mbit/s serial data rate or a 40 Mbit/s parallel data rate.

L64005 MPEG-2 Audio/Video Decoder Technical Manual 1-1

♦ Resolutions are about 352 pixels horizontally up to about 288 lines

vertically for MPEG-1 and 720 x 576 for MPEG-2 (main proﬁle/main level). The L64005 is capab le of resolutions up to 720 x 576 f or either MPEG-1 or MPEG-2.

♦ Display frame rates range from 24 to 30 frames per second.

1.1.1 Video Encoding

For a video signal to be compressed, it must be sampled, digitized, and converted to luminance and color difference signals (Y, Cr, Cb). The MPEG standard stipulates that the luminance component (Y) be sampled with respect to the color difference signals (Cr and Cb) by a ratio of 4:1. That is, for every four samples of Y, there is to be one sub-sample each of Cr and Cb, because the human eye is much more sensitive to luminance (brightness) components than to color components. Video sampling takes place in both the vertical and horizontal directions. Once video is sampled, it is reformatted, if necessary, into a non-interlaced signal. An interlaced signal contains only part of the picture content (every other horizontal line, for example) for each complete display scan.

The encoder must also choose which picture type to use. A picture corresponds to a single frame of motion video, or to a movie frame. There are three picture types:

♦ Intracoded pictures (

other pictures.

♦ Predictive-coded pictures (

compensated prediction from the past I or P reference pictures.

♦ Bidirectionally predictive-coded pictures (

motion compensation from a previous and a future I or P-picture.

I-pictures

P-pictures

) are coded without reference to any

) are coded using motion-

B-pictures

) are coded using

A typical coding scheme contains a mixture of I, P, and B-pictures. Typically, an I-picture may occur every half a second, to give reasonably fast random access, with two B-pictures inserted between each pair of I- or P-pictures.

Once the picture types have been deﬁned, the encoder must estimate motion vectors for each of a 16-pixel by 16-line section of luminance component and two spatially corresponding 8-pixel by 8-line sections, one for each chrominance component.

1-2 Introduction

macroblock

in the picture. A macroblock consists

Motion vectors give the displacement from the stored previous picture. P-pictures use motion compensation to exploit temporal redundancy in the video. Motion within the pictures means that the pix els in the previous picture will be in a different position from the pixels in the current block, and the displacement is given by motion vectors encoded in the MPEG bitstream. Motion vectors deﬁne the motion of a macroblock, which is the motion of a 16 x 16 block of luminance pixels and the associated chrominance components.

When an encoder provides B-pictures, it must reorder the picture sequence so that the decoder operates properly. Because B-pictures use motion compensation based on previously sent I- or P- pictures, they can only be decoded after the referenced pictures have been sent.

As mentioned earlier, a macroblock is a 16 x 16 region of video, corresponding to 16 horizontal pixels and 16 vertical display lines. When sampling a block, the video encoder captures the luminance component of every pixel in the horizontal direction, and the luminance component of every line in the vertical direction. However, the encoder similarly captures only every other Cb and Cr chrominance component. The result is a 16 x 16 block of luminance components and two 8 x 8 blocks each of Cr and Cb components. Each macroblock then consists of a total of six 8 x 8 blocks (four 8 x 8 luminance blocks, one 8 x 8 Cr block, and one 8 x 8 Cb block), as illustrated in Figure 1.1.

Figure 1.1 MPEG Macroblock Structure

YCrCb

It is important to note that the spatial picture area covered by the four 8 x 8 blocks of luminance is the same area covered by each of the 8 x 8 chrominance blocks. Because half as many chrominance samples are needed to cover the same area, they ﬁt into an 8 x 8 block instead of a 16 x 16 block.

For a given macroblock, the encoder must choose a coding mode. The coding mode depends on the picture type, the effectiveness of motion

L64005 MPEG-2 Audio/Video Decoder Technical Manual 1-3

compensation in the particular region of the picture, and the nature of the signal within the block. In addition, for MPEG-2 the encoder must choose to code the macroblock as either a ﬁeld or frame. After it selects the coding method, the encoder performs a motion-compensated prediction of the block contents based on past and/or future reference pictures. The encoder then produces an error signal by subtracting the prediction from the actual data in the current macroblock. The error signal is separated into 8 x 8 blocks (four luminance blocks and two chrominance blocks) and a discrete cosine transform (DCT) is performed on each 8 x 8 block.

The DCT operation converts an 8 x 8 block of pixel values to an 8 x 8 matrix of horizontal and vertical spatial frequency coefﬁcients. An 8 x 8 block of pixel values can be reconstructed by performing the inverse discrete cosine transform (IDCT) on the spatial frequency coefﬁcients. In general, most of the energy is concentrated in the low frequency coefﬁcients, which are located in the upper left corner of the transformed matrix. A quantization step achieves compression — where an index identiﬁes the quantization intervals. Because the encoder identiﬁes the interval and not the exact value within the interval, the pixel values of the block reconstructed by the IDCT have reduced accuracy.

The DCT coefﬁcient in the upper left location (0, 0) of the block represents the zero horizontal and zero vertical frequencies and is known as the

DC coefﬁcient.

The DC coefﬁcient is proportional to the average pixel value of the 8 x 8 block, and additional compression is provided through predictive coding because the difference in the average value of neighboring 8 x 8 blocks tends to be relatively small. The other coefﬁcients represent one or more nonzero horizontal or nonzero vertical spatial frequencies, and are called

AC coefﬁcients.

The quantization level of the coefﬁcients corresponding to the higher spatial frequencies favors the creation of an AC coefﬁcient of zero by choosing a quantization step size such that the human visual system is unlikely to perceive the loss of the particular spatial frequency, unless the coefﬁcient value lies above the particular quantization level. The statistical encoding of the expected runs of consecutive zero-valued coefﬁcients of higher-order coefﬁcients accounts for some coding gain.

To cluster nonzero coefﬁcients early in the series and to encode as many zero coefﬁcients as possible following the last nonzero coefﬁcient in the ordering, the coefﬁcient sequence is speciﬁed to be a zigzag ordering.

Zigzag ordering

1-4 Introduction

concentrates the highest spatial frequencies at the end

of the series. The MPEG-2 standard includes additional block scanning orders.

1.1.2 Bitstream Syntax

After block scanning has been performed, the encoder performs

length coding

on the AC coefﬁcients. This process reduces each 8 x 8

run-

block of DCT coefﬁcients to a number of events represented by a nonzero coefﬁcient and the number of preceding zero coefﬁcients. Because many coefﬁcients are likely to be zero after quantization, run-length coding increases the overall compression ratio.

The encoder then performs

variable-length coding

(VLC) on the resulting data. VLC is a reversible procedure for coding that assigns shorter codewords to frequent events and longer codewords to less frequent events, thereby achieving video compression. Huffman encoding is a particularly well-known form of VLC that reduces the number of bits necessary to represent a data set without losing any information.

The ﬁnal compressed video data is now ready for transmission to either a local storage device from which a video decoder may later retrieve and decompress the data, or to a remote video decoder via cable or direct satellite broadcast, for example.

The MPEG standard speciﬁes the syntax for a compressed bitstream. The video syntax contains six layers, each of which supports either a signal processing or a system function. The layers and their functions are described in Table 1.1.

Table 1.1 MPEG Compressed Bitstream Syntax

Syntax Layers Function

Sequence Layer Random Access Unit: Context Group of Pictures Layer Random Access Unit: Video Picture Layer Primary Coding Unit Slice Layer Resynchronization Unit Macroblock Layer Motion Compensation Unit Block Layer DCT Unit

The MPEG syntax layers correspond to a hierarchical structure. A

sequence

a header and some number of

is the top layer of the video coding hierarchy and consists of

groups-of-pictures (GOPs).

The sequence header initializes the state of the decoder, which allows the decoder to decode any sequence without being affected by past decoding history.

L64005 MPEG-2 Audio/Video Decoder Technical Manual 1-5

Figure 1.2 Typical Sequence of Frames in Display Order

A GOP is a random access point; that is, it is the smallest coding unit that can be independently decoded within a sequence, and consists of a header and some number of pictures. The GOP header contains time and editing information.

The three types of pictures as explained earlier are:

♦ I-pictures ♦ P-pictures ♦ B-pictures

Note that because of the picture dependencies, the bitstream order (the order in which pictures are transmitted, stored, or retrieved), is not the display order, but rather the order in which the decoder requires the pictures for decoding the bitstream. For example, a typical sequence of pictures, in display order, might be as shown in Figure 1.2.

I B B P B B P B B P B B I B B P B B P

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

In contrast, the bitstream order corresponding to the given display order would be as shown in Figure 1.3.

Figure 1.3 Typical Sequence of Frames in Bitstream Order

I P B B P B B P B B I B B P B B P B B

0 3 1 2 6 4 5 9 7 8 12 10 11 15 13 14 18 16 17

Because the B-pictures depend on the subsequent I- or P-picture in display order, the I- or P-picture must be transmitted and decoded before the dependent B-pictures.

Pictures consist of a header and one or more contains time, picture type, and coding information.

A slice provides some immunity to data errors. Should the bitstream become unreadable within a picture, the decoder should be able to

1-6 Introduction

slices.

The picture header

recover by waiting for the next slice, without having to drop an entire picture.

Slices consist of a header and one or more

macroblocks.

The slice

header contains position and quantizer scale information. A macroblock is the basic unit for motion compensation and quantizer

scale changes. In MPEG-2 the block can be either ﬁeld or frame coded. Each macroblock consists of a header and six component 8 x 8 blocks:

four blocks of luminance, one block of Cb chrominance, and one block of Cr chrominance. The macroblock header contains quantizer scale and motion compensation information.

A macroblock contains a 16-pixel by 16-line section of luminance component and the spatially corresponding 8-pixel by 8-line section of each chrominance component. A skipped macroblock is one f or which no DCT information is encoded.

Blocks

are the basic coding unit, and the DCT is applied at this block level. Each block contains 64 component pixels arranged in an 8 x 8 order. Note that pixel values are not individually coded, but are components of the coded block.

Note that the picture area covered by the four blocks of luminance is the same as the area covered by each of the chrominance blocks. Each luminance pixel corresponds to one picture pixel, but because the chrominance information is subsampled with a 2:1 ratio both horizontally and vertically (4:1 total), each chrominance pixel corresponds to four picture pixels.

1.1.3 Video Decoding

Video decoding is the reverse of video encoding and is intended to reconstruct a moving picture sequence from a compressed, encoded bitstream. Decoding is simpler than encoding because there is no motion estimation performed and there are far fewer options.

The data in the bitstream is decoded according to the syntax deﬁned in the MPEG-2 standard. The decoder must ﬁrst identify the beginning of a coded picture and identify the type of picture, then decode each individual macroblock within a particular picture. Motion vectors and macrobloc k types (each of the picture types I, P, and B have their own macroblock types) present in the bitstream, are used to construct a prediction of the

L64005 MPEG-2 Audio/Video Decoder Technical Manual 1-7

current macroblock based on past and future reference pictures that the encoder has already stored. Coefﬁcient data is then inverse quantized and operated on by an inverse DCT process that changes data from the frequency domain to the time and space domain.

After the decoder processes all of the macroblocks, the picture reconstruction is complete. If the picture just reconstructed is a reference picture (I-picture or P-picture), it replaces the oldest stored reference picture and is used as the new reference for subsequent pictures. The pictures may need to be reordered before they are displayed, in accordance with the display order instead of the coding order. After the pictures are reordered, they may be displayed on an appropriate output device.

1.2 Audio Compression and Decompression Concepts

1.2.1 MPEG Audio Encoding

Given an

audio stream

elementary stream

of data (for audio data, this is called an

), an MPEG encoder ﬁrst digitally compresses and codes the data. The MPEG algorithm offers a choice of levels of complexity and performance for this process.

To prepare a stream of compressed audio data for transmission, it is formatted into correction data, and optional user-deﬁned frames are then sent in

System Stream

audio frames

. Each audio frame contains audio data, error-

packets

ancillary data

grouped within

packs

. The audio

in an ISO MPEG

The packs in system streams may contain a mix of audio packets and video packets f or one or more channels . Packs ma y contain packets from separate elementary streams. Thus, MPEG can easily support multiple

channels

of program material, and a decoder given access to a system

stream may access large numbers of channels.

MPEG audio encoding is intended to efﬁciently represent a digitized audio stream by removing redundant information. Because different applications have different performance goals, MPEG uses different encoding techniques. These techniques, called

Layers

, provide a different trade-off between compression and signal quality. The MPEG algorithm uses the two following processes for removing redundant audio information:

♦ Coding and quantization ♦ Psychoacoustic modelling

1-8 Introduction

Figure 1.4 Audio Encoding Process (Simpliﬁed)

Coding and quantization are techniques that are applied to data that has been mapped into the frequency domain and ﬁltered into subbands.

Psychoacoustic modeling is a technique that determines the best allocation of data within the available data channel bandwidth based on human perception.

The general structure of an MPEG audio encoder is shown in Figure 1.4.

Digitized

Audio

Input

Frequency Filter Bank (Mapping)

Psychoacoustic

Model

Bit Allocation

Processor

(Among Subbands,

Coding, Quantizing)

Bitstream Formatter

Once audio data has been coded, it may be stored or transmitted digitally. MPEG provides a framework for use of packet-oriented transmission of compressed data. In particular, ISO CD 11172 deﬁnes formats for digital data streams for both video and audio. The ISO System Stream format is designed to accommodate both audio packets and video packets within the same frame work for transmission. The data may be physically delivered in parallel form or serial form. The System Stream is composed of a sequence of packs, as shown in Figure 1.5.

Figure 1.5 ISO System Stream

Pack Pack

. . .

Pack

Layer

Header

Contains: Pack Start Code (32 bits),

System Clock Reference (128 bits)

System

Header

Packet

An MPEG pack is composed of a

packet

, a sequence of

Packet

(ﬁrst) (last)(variable #)

More Packets

Contains:

Various data, including system stream ID

pack layer header

packets

, and ends with an ISO 11172

Packet ISO

Contains: Audio stream data (in audio frames)

11172

End Code

, a

system header

end code.

The pack layer header contains a pack start code used for synchroniza-

L64005 MPEG-2 Audio/Video Decoder Technical Manual 1-9

tion purposes, and a system clock value. The system header packet contains a variety of housekeeping data and in particular contains a system stream ID used to differentiate multiple system streams. A sequence of one or more packets contains either encoded audio or encoded video stream data. The ISO 11172 end code is the ﬁnal element in an MPEG pack. For detailed deﬁnition of pack headers, refer to the ISO CD 11172-1 system stream descriptions.

Any one MPEG packet carries either audio or video data, but not both simultaneously. An MPEG Audio Packet contains an audio packet header and one or more Audio Frames. Figure 1.6 shows the packet structure.

Figure 1.6 MPEG Audio Packet Structure

Audio Packet

Audio

Packet

Header

Contains:

Packet Start Code Packet Length Presentation Time Stamps

Audio

Frame

(ﬁrst) (last)

(quantity varies)

. . .

Audio Frames

Contains: Audio Frame Header

Audio Frame CRC Audio Data Ancillary/User Data

Audio

Frame

Audio Packet

1.2.1.1 Audio Packet Header

An audio packet header contains the following:

♦ Packet Start Code

Identiﬁes this as an audio packet. The Packet Start Code also contains a ﬁve-bit audio stream identiﬁer that may be read by the user to identify the audio channel.

♦ Packet Length

Indicates the number of bytes remaining in the audio packet.

♦ Presentation Time Stamps (PTS)

. . .

The PTS indicates when audio data should be presented.

1.2.1.2 Audio Frame

An Audio Frame contains a slice of the audio data stream together with some supplementary data. Audio frames have the following elements:

1-10 Introduction

+ 242 hidden pages

LSI L64005 Technical Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Preface

Audience This document assumes that you have some familiarity with microproces-

Organization This document has the following chapters:

Related Publications

Conventions Used in This Manual

Revision History

Notice for L64002 Users

Pinout Changes If the L64005 is used with fast page mode DRAM, then a few changes

Software Changes

Contents

Appendix A Interfacing the L64005 to 5-V Signals

Appendix B Customer Feedback

List of Figures

List of Tables

1.1 Video Compression and Decompression Concepts

1.1.1 Video Encoding

1.1.2 Bitstream Syntax

1.1.3 Video Decoding

1.2 Audio Compression and Decompression Concepts

1.2.1 MPEG Audio Encoding

1.2.1.1 Audio Packet Header

1.2.1.2 Audio Frame