LSI L64005 Technical Manual

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L64005

Enhanced MPEG-2

Audio/Video Decoder

Technical Manual

Final Edition May 1998

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This document contains proprietary information of LSI Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an ofﬁcer of LSI Corporation.

Document DB14-000045-00, Final Revision F (May, 1998) This document describes revisions D through F of LSI Logic Corporation’s L64005 MPEG-2 Audio/Video Decoder and will remain the ofﬁcial reference source for all revisions/releases of this product until rescinded by an update.

To receive product literature, call us at 1.800.574.4286 (U.S. and Canada); +32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, and Europe) and ask for Department JDS; or visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.

In particular, supply of the LSI Logic IC L64005 does not convey a license or imply a right under certain patents and/or other industrial or intellectual proper ty rights claimed by IRT, CCETT and Philips, to use this IC in any ready-to-use electronic product. The purchaser is herby notiﬁed that Philips, CCETT and IRT are of the opinion that a generally available patent license for such use is required from them. No warranty or indemnity of any sort is provided by LSI Logic regarding patent infringement.

LSI Logic logo design is a registered trademark of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies.

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Preface

This book is the primary reference and technical manual for the L64005 MPEG-2 Audio/Video Decoder. It contains a complete functional description and includes complete physical and electrical speciﬁcations for the L64005.

Audience This document assumes that you have some familiarity with microproces-

sors and related support devices. The people who beneﬁt from this book are:

♦ Engineers and managers who are evaluating the processor for pos-

sible use in a system

♦ Engineers who are designing the processor into a system

Organization This document has the following chapters:

♦ Chapter 1 Introduction, describes the system interface and the

architecture of the L64005 MPEG-2 Audio/Video Decoder.

♦ Chapter 2 Registers, discusses the L64005 internal registers. It also

provides a description of the internal memory mapping and how the registers are accessed from the system interface. This chapter is intended primarily for system programmers who are developing software drivers.

♦ Chapter 3 Signals, provides detailed information on the L64005 sig-

nals. The signal descriptions are useful for hardware designers who are interfacing the L64005 with other devices.

♦ Chapter 4 Video Data Flow, This chapter describes the MPEG bit-

stream construction, parsing and error handling as well as the operation of the channel buffer.

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♦ Chapter 5 External Memory Interface, describes the frame mem-

ory interface.

♦ Chapter 6 Video Interface and On-Screen Display, describes the

L64005 video interface and video timing characteristics.

♦ Chapter 7 Audio Decoder, describes the details of the integrated

two channel Musicam (MPEG) audio decoder.

♦ Chapter 8 System Stream Decoding and Synchronization,

describes the resources that the L64005 provides for parsing an MPEG system stream.

♦ Chapter 9 Speciﬁcations, speciﬁes the L64005 electrical and

mechanical characteristics.

♦ Appendix A Interfacing the L64005 to 5-V Signals, describes how

to interface LSI Logic’s 3.3-V L64005 MPEG-2 Audio/Video Decoder to 5-V signals.

♦ Customer Feedback.

Related Publications

Conventions Used in This Manual

ISO/IEC 13818,

Audio

(MPEG-2), Draft International Standard.ISO/IEC Copyright Ofﬁce,

Case Postal 56, CH1211 Genève 20, Switzerland. ISO/IEC 11172 (1993),

Generic Coding of Moving Pictures and Associated

Information Technology—Coding of Moving Pic-

ture and Associated Audio for Digital Storage Media at up to about

1.5 Mbit/s L64002 MPEG-2 Audio/Video Decoder Technical Manual

Corp.

L64007 MPEG-2 Transport Demultiplexer

Unless otherwise speciﬁed,

MSB

signiﬁcant bit or byte.The ﬁrst time a word or phrase is deﬁned in this manual, it is

The following signal naming conventions are used throughout this manual:

(MPEG-1).

, LSI Logic Corp.

MPEG

refers to the MPEG-2 standard.

indicates the most-signiﬁcant bit or byte.

italicized.

, LSI Logic

LSB

indicates the least-

iv Preface

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♦ A level-signiﬁcant signal that is true or valid when the signal is LOW

always has an overbar ( ) over its name.

♦ An edge-signiﬁcant signal that initiates actions on a HIGH-to-LOW

transition always has an overbar ( ) over its name.

Revision History

The word

deassert

assert

means to drive a signal true or active. The word

means to drive a signal false or inactive.

Hexadecimal numbers are indicated by the preﬁx “0x” before the number—for example, 0x32CF. Binary numbers are indicated by a subscripted “2” following the number—for example, 0011.0010.1100.11112.

This section lists the changes in this document from initial release to the current version.

Version Release Date Comments

L64005.ADV.0 March 4, 1996 Initial release L64005.ADV.1 August 23, 1996 Major modiﬁcations to most chapters.

L64005.Final May 11, 1998 Minor changes to most chapters.

Changed register map, pinout, and signal descriptions. Added Section

6.3, “Reduced Memory Mode, ” Section

3.6, “PLL Interface,” and Section 5.5, “Channel Buffer Architecture”.

Added corrections from document review and relevant items from L64005 Rev. E and F ECNs.

Notice for L64002 Users

This section is for customers using the L64002, and who want to upgrade to the L64005. The following is a brief description of the pertinent changes, with emphasis on pinout and necessary software changes.

Please note: LSI Logic recommends building new boards to ensure L64005 to L64002 compatibility. A simple 0 Ω resistor jumper (for pin 69) allows switching between the loop ﬁlter and the CAS signal.

Pinout Changes If the L64005 is used with fast page mode DRAM, then a few changes

are needed. For further information, please refer to Chapter 9: Speciﬁcations.

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♦ Pin 64 is CAS for the L64005, not BA9 (BA9 has been removed). ♦ For Rev. E and F devices Pin 69 is now not connected (NC) and no

external loop ﬁlter is required. The ﬁlter may be left in place on any board that already has it designed in. For the L64005 Rev. D, Pin 69 is LP2. Regardless of the DRAM mode used, an external loop ﬁlter must be included in the design (requires one resistor and two capacitors for an off-chip loop ﬁlter).

♦ The DRAM interface now supports both regular and synchronous

DRAM modes. See Section 5.3.2, “Synchronous DRAM Mode,” for more information on the SDRAM interface.

♦ New AC timing speciﬁcations and drawings have been added to Sec-

tion 9.1

♦ Pin 68 is Analog VDD (AVDD), and pin 70 is Analog GND (AGND).

These pins must be isolated from other VDD and VSS pins.

♦ Please note that the L64005 has an on-chip PLL, so the 27-MHz

input clock must have low jitter (<300ps).

♦ The duty cycle for SYSCLK has been speciﬁed slightly differently.

Please refer to Chapter 9, Speciﬁcations, for details.

Software Changes

A few changes must be made to L64005 supporting software.

♦ Bit 0in Group 7, Register 27 must be set for reduced memory mode

(1=RMM, 0=Normal).

♦ If reduced memory mode is used, Group 7, Register 27, Bits [7:2]

must be set to determine the number of 8-line segments used for a B-frame decode.

♦ Bits [4:3] of Group 7, Register 1 are no longer used for PMCT (1CAS

enable) or 512-page size select. In the L64005, bits [4:3] are used to select the DRAM mode. Refer to Chapter 2 for more details.

♦ In the L64005 32-bit mode is not supported. Bit 5 of Group 7, Reg-

ister 1 is now reserved.

♦ Bit 6 of Group 7, Register 26 controls line doubling for the interlaced

display mode.

♦ In the L64005, bits [7:0] in Group 7, Register 28 contains the hori-

zontal word origin of the luma and the chroma.

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♦ Additional ﬁeld status bits have been added to the register map. Odd

Field First and Last Active Field have been added to Group 6, Register 31, Bits [3:2]. Refer to Section 2.8.18, “Group 6 Display Mode 1” for more details.

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Chapter 1 Introduction

1.1 Video Compression and Decompression Concepts 1-1

1.1.1 Video Encoding 1-2

1.1.2 Bitstream Syntax 1-5

1.1.3 Video Decoding 1-7

1.2 Audio Compression and Decompression Concepts 1-8

1.2.1 MPEG Audio Encoding 1-8

1.2.2 Audio Decoding 1-11

1.3 Standards Compliance 1-11

1.3.1 MPEG-1 1-12

1.3.2 MPEG-2 1-12

1.4 Ter ms and Concepts 1-12

1.5 System Overview 1-17

1.5.1 Video Decoding 1-17

1.5.2 Audio Decoding 1-17

1.5.3 Post Processing 1-18

1.5.4 On-Screen Display 1-18

1.5.5 PES Decoding 1-18

1.5.6 Video Output 1-19

1.5.7 Audio Output 1-19

1.5.8 User Interface 1-19

1.5.9 Memory Utilization 1-19

1.5.10 Error Concealment 1-20

1.5.11 Mechanical and Electrical 1-20

1.6 L64005 Overview 1-20

1.6.1 MPEG-2 Video Decoder 1-20

1.6.2 System Layer Decoding 1-21

1.6.3 Video Output Features 1-21

1.6.4 On-Screen Display 1-24

1.6.5 Audio Decoder 1-24

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1.6.6 System Controller Interface 1-25

1.6.7 Channel Interface 1-27

1.6.8 Bitstream Syntax and Grammar 1-27

1.7 Features 1-28

Chapter 2 Registers

2.1 L64005 Register Overview 2-1

2.1.1 Writing a Single Register 2-14

2.1.2 Reading or Writing Multiple Registers

2.2 Group 0 Address Indirection Register 2-15

2.3 Group 1 Status 0 Register 2-16

2.4 Group 2 Status 1 Register 2-18

2.5 Group 3 Interrupt Register 0 2-19

2.6 Group 4 Interrupt Register 1 2-21

2.7 Group 5 Control Register 2-22

2.8 Group 6 Secondary Control Registers 2-23

2.8.1 Group 6 User Data FIFO 2-23

2.8.2 Group 6 Error Status Register 2-24

2.8.3 Group 6 Forward Anchor Luma

2.8.4 Group 6 Forward Anchor Chroma

2.8.5 Group 6 Backward Anchor Luma

2.8.6 Group 6 Backward Anchor Chroma

2.8.7 Group 6 Display Luma Base Address 2-27

2.8.8 Group 6 Display Chroma Base Address 2-27

2.8.9 Group 6 VBI1 Luma Base Address 2-28

2.8.10 Group 6 VBI1 Chroma Base Address 2-28

2.8.11 Group 6 VBI2 Luma Base Address 2-29

2.8.12 Group 6 VBI2 Chroma Base Address 2-29

2.8.13 Group 6 VBI Size 2-30

2.8.14 Group 6 OSD Control Register 2-30

2.8.15 Group 6 OSD Field 1 Pointer 2-31

2.8.16 Group 6 OSD Field 2 Pointer 2-32

2.8.17 Group 6 Display Mode 0 2-32

in a Group 2-15

Base Address 2-25

Base Address 2-26

Base Address 2-27

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2.8.18 Group 6 Display Mode 1 2-33

2.8.19 Group 6 Raster Mapper Increment 2-34

2.8.20 Group 6 Display Controller Status 2-35

2.8.21 Group 6 Video PES Buffer Start Address 2-36

2.8.22 Group 6 Video PES Buffer End Address 2-37

2.8.23 Group 6 Audio PES Buffer Start Address 2-37

2.8.24 Group 6 Audio PES Buffer End Address 2-38

2.8.25 Group 6 Video Channel Buffer Start Address 2-38

2.8.26 Group 6 Video Channel Buffer End Address 2-39

2.8.27 Group 6 Audio Channel Buffer Start Address 2-39

2.8.28 Group 6 Audio Channel Buffer End Address 2-40

2.8.29 Group 6 Audio Mode Control 2-40

2.8.30 Group 6 Audio Oscillator Frequency Control 2-41

2.8.31 Group 6 Audio Parameter 0 2-42

2.8.32 Group 6 Audio Parameter 1 2-44

2.8.33 Group 6 Audio Trick Modes 2-45

2.8.34 Group 6 Reserved Registers 2-47

2.9 Group 7 Secondary Control Registers 2-47

2.9.1 Group 7 Auxiliary Data FIFO 2-47

2.9.2 Group 7 DRAM Control 2-51

2.9.3 Group 7 DRAM Address 2-52

2.9.4 Group 7 DRAM Data 2-53

2.9.5 Group 7 Horizontal Sync Width 2-54

2.9.6 Group 7 Equalization Pulse Width 2-54

2.9.7 Group 7 Serration Pulse Width 2-54

2.9.8 Group 7 Horizontal Blank Pulse Width 2-55

2.9.9 Group 7 Active Image Done 2-55

2.9.10 Group 7 Half Line Time 2-55

2.9.11 Group 7 Upper Bits 2-55

2.9.12 Group 7 Pre-Blank/Equalization 2-56

2.9.13 Group 7 Post-Blank/Equalization 2-56

2.9.14 Group 7 Main/Serration Lines 2-57

2.9.15 Group 7 Scan Half Lines 2-57

2.9.16 Group 7 Main Reads Per Line 2-57

2.9.17 Group 7 Display Width 2-58

2.9.18 Group 7 Pan and Scan Control 2-58

2.9.19 Group 7 Reduced Memory Mode Control 2-59

2.9.20 Group 7 Reserved Registers 2-60

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Chapter 3 Signals

3.1 User Interface 3-2

3.2 Channel Interface 3-4

3.3 Memory Interface 3-7

3.4 Video Interface 3-9

3.5 Audio Interface 3-10

3.6 PLL Interface 3-11

2.9.21 Group 7 Video Output Mode Control 2-60

2.9.22 Group 7 Channel Buffer Read Address 2-61

2.9.23 Group 7 Picture Start Code Read Address 2-62

2.9.24 Group 7 Audio Sync Code Read Address 2-62

2.9.25 Group 7 Reserved Registers 2-62

2.9.26 Group 7 DRAM Source Address Registers 2-63

2.9.27 Group 7 DRAM Transfer Count Registers 2-63

2.9.28 Group 7 DRAM Transfer Mode Register 2-63

2.9.29 Group 7 Revision ID Register 2-64

2.9.30 Group 7 Video Tr ick Modes 2-64

2.9.31 Group 7 System Clock Reference (SCR) Value 2-66

2.9.32 Group 7 SCR Compare Value 2-66

2.9.33 Group 7 Reserved Registers 2-66

3.2.1 Parallel Channel Writes 3-6

3.2.2 Serial Channel Writes 3-6

3.3.1 Regular DRAM Signals 3-7

3.3.2 Synchronous DRAM Signals 3-8

Chapter 4 Video Data Flow

4.1 Overview 4-1

4.2 Channel Data Parsers 4-1

4.2.1 Pre-Parser Operation 4-3

4.2.2 Post-Parser Operation 4-6

4.3 Channel Buffer Operation 4-10

4.3.1 Channel Buffer Hardware 4-10

4.3.2 User Data Buffer 4-11

4.3.3 Auxiliary Data Buffer 4-12

4.4 Elementary Stream Decoding 4-13

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Chapter 5 External Memory Interface

5.1 Overview 5-1

5.2 Memory Architecture 5-1

5.3 Memory Interface 5-2

5.3.1 Regular DRAM Mode 5-2

5.3.2 Synchronous DRAM Mode 5-3

5.3.3 DRAM Transfer Modes 5-4

5.3.4 Read/Write 5-12

5.3.5 Refresh Cycles 5-16

5.4 Memory Map 5-17

5.4.1 Luma Frame Organization 5-19

5.4.2 Chroma Frame Organization 5-19

5.4.3 Random Read/Write to Frame Store 5-19

5.5 Channel Buffer Architecture 5-19

5.5.1 Video PES Buffer 5-21

5.5.2 Audio PES Buffer 5-22

5.5.3 Video Channel Buffer 5-22

5.5.4 Audio Channel Buffer 5-22

Chapter 6 Video Interface and On-Screen Display

6.1 Video Output Format 6-1

6.1.1 Post-Processing 480- and 576-Line Images 6-2

6.1.2 Post-Processing 240- and 288-Line Images 6-4

6.1.3 Selecting the Post-Processing Mode 6-5

6.2 Video Resolution 6-6

6.3 Reduced Memory Mode 6-7

6.4 Horizontal Post-Processing Filter 6-8

6.4.1 Filter Speciﬁcation 6-8

6.4.2 Setting the Filter Raster Mapper Increment 6-10

6.4.3 Setting the Start Phase of the Filter 6-11

6.4.4 Filter Inhibit 6-11

6.4.5 Video Data and OSD 6-11

6.5 Display Control Parameters 6-11

6.5.1 Video Raster Timing (Master Mode 6-12

6.5.2 VCode Delay 6-17

6.5.3 Slave Mode 6-17

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6.5.4 Adaptive Modiﬁcation of Video Raster for Copy Protection 6-18

6.6 Pan and Scan Operation 6-18

6.7 Display Trick Modes 6-19

6.7.1 Trick Mode Decoding 6-19

6.8 3:2 Pull-Down 6-22

6.9 On-Screen Display 6-23

6.9.1 Color Palette 6-23

6.9.2 Operation of the OSD Controller 6-24

6.9.3 OSD Control Registers 6-25

6.9.4 Alpha Blending 6-31

6.9.5 High Color Operation 6-31

6.9.6 Bitmap Storage 6-31

6.9.7 Use of the OSDA Field 6-31

6.9.8 Alignment of the Bitmap 6-32

6.9.9 OSD Control 6-32

6.9.10 Limitations in the OSD Controller 6-32

6.9.11 OSD Compatibility Mode 6-33

6.9.12 Accessing the Overlay Bitmaps 6-34

6.10 Interrupts from the Display Controller 6-34

Chapter 7 Audio Decoder

7.1 Audio Decoder Overview 7-1

7.2 Decoder Programming 7-1

7.2.1 Reading the Audio Parameters 7-1

7.2.2 Starting, Stopping and Controlling the Rate of the Decoder 7-2

7.2.3 Setting the DAC Interface Mode 7-3

7.2.4 Setting the Output Sample Rate 7-3

7.2.5 Determining the Presentation Time 7-6

7.2.6 Ancillary Channel Data 7-6

7.2.7 Error Detection 7-6

7.2.8 Output Control 7-8

Chapter 8 System Stream Decoding and Synchronization

8.1 System Parser Basics 8-1

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8.1.1 Parsing a Program Stream 8-2

8.1.2 Parsing a Transport Stream 8-4

8.2 Reading the System Header Data 8-5

8.2.1 System Parser Control Bits 8-5

8.3 Synchronization Basics 8-7

8.4 L64005 Synchronization Resources 8-10

8.4.1 L64005 Video Skip and Repeat Frame 8-13

8.4.2 Video Decoding and Presentation Schedule 8-15

8.4.3 Audio Decoder Rate Control 8-16

8.5 Audio/Video Synchronization Technique 8-17

8.5.1 Clock Recovery 8-19

8.5.2 Creating Audio and Video PTS list 8-20

8.5.3 Picture Header Interrupt and AUX

8.5.4 Ver tical Sync Interrupt 8-26

8.5.5 Audio Sync Interrupt 8-26

8.6 Real System Considerations 8-28

Chapter 9 Speciﬁcations

9.1 AC Timing 9-2

9.2 Electrical Requirements 9-14

9.3 Pin Summary 9-15

9.4 Packaging 9-18

FIFO Interrupt 8-23

Appendix A Interfacing the L64005 to 5-V Signals

A.2 JEDEC LVTTL Interface Standards A-1 A.3 L64005 5V-Compatible I/Os A-2

9.4.1 5V-Compatible Input Buffers A-3

9.4.3 Passive Resistor Loads and 5-V Compatible Outputs A-5

9.4.5 Open Drain Outputs A-7

A.4 Mixed Voltage System Design Considerations A-8 A.5 Engineering Practice for Mixed Voltage Systems A-8

9.4.6 Precautions During Power Sequencing A-8

9.4.7 Precautions to Avoid Bus Contention A-9

9.4.8 Precautions During Power Failure A-9

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Appendix B Customer Feedback

List of Figures

1.1 MPEG Macroblock Structure 1-3

1.2 Typical Sequence of Frames in Display Order 1-6

1.3 Typical Sequence of Frames in Bitstream Order 1-6

1.4 Audio Encoding Process (Simpliﬁed) 1-9

1.5 ISO System Stream 1-9

1.6 MPEG Audio Packet Structure 1-10

1.7 System Block Diagram 1-18

2.1 Address Indirection Register 2-15

2.2 Status 0 Register 2-16

2.3 Status 1 Register 2-18

2.4 Group 3 Interrupt Register 0 2-20

2.5 Group 4 Interrupt Register 1 2-21

2.6 Group 5 Control Register 2-22

2.7 LAF and ODFF Bit Fields 2-36

2.8 DRAM Control Register 2-51

2.9 Active Image Done Register 2-55

2.10 Scan Half Lines Register 2-57

3.1 L64005 Logic Symbol 3-2

3.2 Parallel Channel Input Timing 3-6

3.3 Serial Channel Input Timing 3-7

3.4 Master Mode 3-10

3.5 External Loop Filter 3-12

4.1 Summary of the Bitstream Parsing Operations 4-2

4.2 Conceptual System Synchronization 4-3

4.3 Synchronization at the System Level 4-4

4.4 Successful and Unsuccessful Frame Skips 4-14

5.1 Regular DRAM Interface 5-3

5.2 Synchronous DRAM Interface 5-4

5.3 The Single Word Write Routine 5-6

5.4 Multiple Word Write Routine 5-7

5.5 Single Word Read Routine 5-8

5.6 Multiple Word Read Routine 5-9

5.7 Regular DRAM Read and Write Timing 5-12

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5.8 Synchronous DRAM Read and Write Timing 5-15

5.9 Regular DRAM Refresh Timing 5-16

5.10 Synchronous DRAM Refresh Timing 5-17

5.11 Memor y Map of L64005 5-18

5.12 Channel Buffer Organization in L64005 5-21

6.1 Composite Sync and Composite Blank 6-2

6.2 Effect of Ver tical Resolution and Blanking 6-6

6.3 Frequency and Phase Response A 6-9

6.4 Impulse Response A 6-9

6.5 Frequency and Phase Response B 6-9

6.6 Impulse Response B 6-10

6.7 Video Timing Chain Nomenclature 6-12

6.8 Horizontal Sync Timing 6-13

6.9 Display Parameters 6-14

6.10 Freeze Frame for One Frame Time 6-20

6.11 Freeze Frame for One Field Time 6-21

6.12 Pull-Down Field Order 6-22

6.13 Pointers to Overlay Display Lists 6-24

6.14 OSD File Organization 6-26

6.15 Region Attribute Bits 6-27

6.16 Color Fields 6-28

6.17 Color Attribute Bits 6-29

6.18 Color Extension Bits 6-29

8.1 MPEG-2 Transpor t Encoder 8-7

8.2 Audio and Video Sync train 8-8

8.3 Local Counter and Comparator Logic 8-11

8.4 Interrupt at each Vertical Sync 8-11

8.5 Audio and Video Decode Interrupts 8-12

8.6 System Header Interrupt 8-13

8.7 Video Skip 8-14

8.8 Video Repeat 8-14

8.9 Buffer Organization In L64005 Memory 8-21

8.10 PES Header Structure 8-22

8.11 List of Pending PUs for Video and Audio 8-23

8.12 PTS Association with Presentation Unit 8-24

8.13 Picture Type Routine 8-25

8.14 Audio PTS Association 8-27

8.15 Audio Sync Algorithm 8-28

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9.1 AC Test Load and Waveform for Standard Outputs 9-3

9.2 AC Test Load and Waveform for 3-State Outputs 9-3

9.3 DRAM Write Cycle 9-7

9.4 DRAM Read Cycle 9-8

9.5 Sync DRAM Write Cycle 9-9

9.6 Sync DRAM Read Cycle 9-10

9.7 Parallel Channel Write Timing 9-11

9.8 Host Write Timing 9-11

9.9 Host Read Timing 9-12

9.10 Serial Data Input 9-12

9.11 Reset 9-13

9.12 Video Timing 9-13

9.13 Serial PCM Data Out Timing 9-13

9.14 L64005 Pinout Diagram for Regular DRAM 160-Pin PQFP 9-21

9.15 L64005 Pinout Diagram for Synchronous DRAM 160-Pin PQFP 9-22

9.16 160-Pin Copper Lead Frame PQFP Mechanical Drawing 9-23

A.17 5V Interface Conﬁgurations A-3 A.18 5V-Compatible Output Buffer, Open Drain A-7

List of Tables

1.1 MPEG Compressed Bitstream Syntax 1-5

2.1 Register Groups and Function 2-2

2.2 L64005 Register Map 2-2

2.3 User Data FIFO 0 2-23

2.4 VLD Parameters 2-48

5.1 Mapping of Physical Address Bus to BA[8:0] 5-3

5.2 Mapping of Physical Address Bus to SBA[11:0] 5-4

5.3 Word Accesses vs. 81MHz Clock Cycles

5.4 Word Accesses Vs. 81MHz Clock Cycle

5.5 Channel Buffer Architecture 5-20

6.1 Post-processing modes 6-3

6.2 Chroma Line Repeat: Coefﬁcients for Odd

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in Regular DRAM Mode 5-13

in SDRAM Mode 5-14

and Even Fields 6-3

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6.3 Luma Processing: Coefﬁcients for Even and Odd Fields 6-4

6.4 Chroma Processing: Coefﬁcients for Even and Odd Fields 6-5

6.5 Memory Mode Speciﬁcations 6-8

6.6 Raster Mapper Increment by Source Resolution 6-11

6.7 Horizontal Timing of NTSC TV Systems 6-15

6.8 Horizontal Timing of PAL TV Systems 6-16

6.9 Vertical Timing of Common TV Systems 6-17

6.10 Pull-Down Mode Bits 6-23

6.11 Conversion from 4:4:4 to 4:2:2 6-32

7.1 Typical Values for NCO at 27 MHz fd 7-5

7.2 Location of Maskable Interrupts 7-7

8.1 Levels of Hierarchy in MPEG-1 and MPEG-2 System Syntax 8-2

8.2 DRAM Map of an MPEG-2 Packet Header Structure in the Elementary Stream with Write Pointer 8-6

8.3 Audio and Video DTSs and PTSs 8-10

8.4 Decode to Display Delay 8-15

8.5 Audio Input Clock is 256 fs 8-17

8.6 Audio Input Clock is 384 fs 8-17

9.1 AC Test Conditions 9-2

9.2 AC Timing Values 9-4

9.3 Absolute Maximum Ratings 9-14

9.4 Recommended Operating Conditions 9-14

9.5 Capacitance 9-14

9.6 DC Characteristics 9-15

9.7 Pin Description Summary 9-16

9.8 L64005 Ordering Information 9-18

9.9 Alphabetical Pin List by Signal Name for Regular DRAM 160-Pin PQFP 9-19

9.10 Alphabetical Pin List by Signal Name for Synchronous DRAM 160-Pin PQFP 9-20

A.11 DC Logic Levels A-2 A.12 DC Characteristics A-4 A.13 ibuf (3.3V Input), LVTTL AC Characteristics A-4 A.14 ibuff, LVTTL Input Buffer, Non-inverting,

5V-Compatible A-4

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A.15 DC Characteristics without Resistor Load A-6 A.16 3-State Output Buffer, 5 V-Compatible

AC Characteristics A-7

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Chapter 1 Introduction

This chapter describes the system interface and the architecture of the L64005 MPEG-2 Audio/Video Decoder, and contains the following sections:

♦ Section 1.1, “Video Compression and Decompression Concepts” ♦ Section 1.2, “Audio Compression and Decompression Concepts” ♦ Section 1.3, “Standards Compliance” ♦ Section 1.4, “Ter ms and Concepts” ♦ Section 1.5, “System Overview” ♦ Section 1.6, “L64005 Overview” ♦ Section 1.7, “Features”

Sections 1.1 through 1.4 explain in general terms the requirements of the Moving Picture Expert’s Group MPEG-2 International Standard (IS) 13818 as applied to video compression and decompression. These sections provide a good foundation for the L64005-speciﬁc discussion that follows in Sections 1.5 through 1.7.

1.1 Video Compression and Decompression Concepts

The MPEG standard deﬁnes a format for compressed digital video. Encoders designed to work within the conﬁnes of the standard compress video information, and decoders decompress it.

The MPEG algorithms for video compression and decompression are ﬂexible, but generally ﬁt the following criteria:

♦ Data rates are about 1 to 1.5 Mbit/s for MPEG-1 and up to 15 Mbit/s

for MPEG-2. The L64005 MPEG-2 decoder’s channel interface is capable of supporting a 20 Mbit/s serial data rate or a 40 Mbit/s parallel data rate.

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♦ Resolutions are about 352 pixels horizontally up to about 288 lines

vertically for MPEG-1 and 720 x 576 for MPEG-2 (main proﬁle/main level). The L64005 is capab le of resolutions up to 720 x 576 f or either MPEG-1 or MPEG-2.

♦ Display frame rates range from 24 to 30 frames per second.

1.1.1 Video Encoding

For a video signal to be compressed, it must be sampled, digitized, and converted to luminance and color difference signals (Y, Cr, Cb). The MPEG standard stipulates that the luminance component (Y) be sampled with respect to the color difference signals (Cr and Cb) by a ratio of 4:1. That is, for every four samples of Y, there is to be one sub-sample each of Cr and Cb, because the human eye is much more sensitive to luminance (brightness) components than to color components. Video sampling takes place in both the vertical and horizontal directions. Once video is sampled, it is reformatted, if necessary, into a non-interlaced signal. An interlaced signal contains only part of the picture content (every other horizontal line, for example) for each complete display scan.

The encoder must also choose which picture type to use. A picture corresponds to a single frame of motion video, or to a movie frame. There are three picture types:

♦ Intracoded pictures (

other pictures.

♦ Predictive-coded pictures (

compensated prediction from the past I or P reference pictures.

♦ Bidirectionally predictive-coded pictures (

motion compensation from a previous and a future I or P-picture.

I-pictures

P-pictures

) are coded without reference to any

) are coded using motion-

B-pictures

) are coded using

A typical coding scheme contains a mixture of I, P, and B-pictures. Typically, an I-picture may occur every half a second, to give reasonably fast random access, with two B-pictures inserted between each pair of I- or P-pictures.

Once the picture types have been deﬁned, the encoder must estimate motion vectors for each of a 16-pixel by 16-line section of luminance component and two spatially corresponding 8-pixel by 8-line sections, one for each chrominance component.

1-2 Introduction

macroblock

in the picture. A macroblock consists

Page 23

Motion vectors give the displacement from the stored previous picture. P-pictures use motion compensation to exploit temporal redundancy in the video. Motion within the pictures means that the pix els in the previous picture will be in a different position from the pixels in the current block, and the displacement is given by motion vectors encoded in the MPEG bitstream. Motion vectors deﬁne the motion of a macroblock, which is the motion of a 16 x 16 block of luminance pixels and the associated chrominance components.

When an encoder provides B-pictures, it must reorder the picture sequence so that the decoder operates properly. Because B-pictures use motion compensation based on previously sent I- or P- pictures, they can only be decoded after the referenced pictures have been sent.

As mentioned earlier, a macroblock is a 16 x 16 region of video, corresponding to 16 horizontal pixels and 16 vertical display lines. When sampling a block, the video encoder captures the luminance component of every pixel in the horizontal direction, and the luminance component of every line in the vertical direction. However, the encoder similarly captures only every other Cb and Cr chrominance component. The result is a 16 x 16 block of luminance components and two 8 x 8 blocks each of Cr and Cb components. Each macroblock then consists of a total of six 8 x 8 blocks (four 8 x 8 luminance blocks, one 8 x 8 Cr block, and one 8 x 8 Cb block), as illustrated in Figure 1.1.

Figure 1.1 MPEG Macroblock Structure

YCrCb

It is important to note that the spatial picture area covered by the four 8 x 8 blocks of luminance is the same area covered by each of the 8 x 8 chrominance blocks. Because half as many chrominance samples are needed to cover the same area, they ﬁt into an 8 x 8 block instead of a 16 x 16 block.

For a given macroblock, the encoder must choose a coding mode. The coding mode depends on the picture type, the effectiveness of motion

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compensation in the particular region of the picture, and the nature of the signal within the block. In addition, for MPEG-2 the encoder must choose to code the macroblock as either a ﬁeld or frame. After it selects the coding method, the encoder performs a motion-compensated prediction of the block contents based on past and/or future reference pictures. The encoder then produces an error signal by subtracting the prediction from the actual data in the current macroblock. The error signal is separated into 8 x 8 blocks (four luminance blocks and two chrominance blocks) and a discrete cosine transform (DCT) is performed on each 8 x 8 block.

The DCT operation converts an 8 x 8 block of pixel values to an 8 x 8 matrix of horizontal and vertical spatial frequency coefﬁcients. An 8 x 8 block of pixel values can be reconstructed by performing the inverse discrete cosine transform (IDCT) on the spatial frequency coefﬁcients. In general, most of the energy is concentrated in the low frequency coefﬁcients, which are located in the upper left corner of the transformed matrix. A quantization step achieves compression — where an index identiﬁes the quantization intervals. Because the encoder identiﬁes the interval and not the exact value within the interval, the pixel values of the block reconstructed by the IDCT have reduced accuracy.

The DCT coefﬁcient in the upper left location (0, 0) of the block represents the zero horizontal and zero vertical frequencies and is known as the

DC coefﬁcient.

The DC coefﬁcient is proportional to the average pixel value of the 8 x 8 block, and additional compression is provided through predictive coding because the difference in the average value of neighboring 8 x 8 blocks tends to be relatively small. The other coefﬁcients represent one or more nonzero horizontal or nonzero vertical spatial frequencies, and are called

AC coefﬁcients.

The quantization level of the coefﬁcients corresponding to the higher spatial frequencies favors the creation of an AC coefﬁcient of zero by choosing a quantization step size such that the human visual system is unlikely to perceive the loss of the particular spatial frequency, unless the coefﬁcient value lies above the particular quantization level. The statistical encoding of the expected runs of consecutive zero-valued coefﬁcients of higher-order coefﬁcients accounts for some coding gain.

To cluster nonzero coefﬁcients early in the series and to encode as many zero coefﬁcients as possible following the last nonzero coefﬁcient in the ordering, the coefﬁcient sequence is speciﬁed to be a zigzag ordering.

Zigzag ordering

1-4 Introduction

concentrates the highest spatial frequencies at the end

Page 25

of the series. The MPEG-2 standard includes additional block scanning orders.

1.1.2 Bitstream Syntax

After block scanning has been performed, the encoder performs

length coding

on the AC coefﬁcients. This process reduces each 8 x 8

run-

block of DCT coefﬁcients to a number of events represented by a nonzero coefﬁcient and the number of preceding zero coefﬁcients. Because many coefﬁcients are likely to be zero after quantization, run-length coding increases the overall compression ratio.

The encoder then performs

variable-length coding

(VLC) on the resulting data. VLC is a reversible procedure for coding that assigns shorter codewords to frequent events and longer codewords to less frequent events, thereby achieving video compression. Huffman encoding is a particularly well-known form of VLC that reduces the number of bits necessary to represent a data set without losing any information.

The ﬁnal compressed video data is now ready for transmission to either a local storage device from which a video decoder may later retrieve and decompress the data, or to a remote video decoder via cable or direct satellite broadcast, for example.

The MPEG standard speciﬁes the syntax for a compressed bitstream. The video syntax contains six layers, each of which supports either a signal processing or a system function. The layers and their functions are described in Table 1.1.

Table 1.1 MPEG Compressed Bitstream Syntax

Syntax Layers Function

Sequence Layer Random Access Unit: Context Group of Pictures Layer Random Access Unit: Video Picture Layer Primary Coding Unit Slice Layer Resynchronization Unit Macroblock Layer Motion Compensation Unit Block Layer DCT Unit

The MPEG syntax layers correspond to a hierarchical structure. A

sequence

a header and some number of

is the top layer of the video coding hierarchy and consists of

groups-of-pictures (GOPs).

The sequence header initializes the state of the decoder, which allows the decoder to decode any sequence without being affected by past decoding history.

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Figure 1.2 Typical Sequence of Frames in Display Order

A GOP is a random access point; that is, it is the smallest coding unit that can be independently decoded within a sequence, and consists of a header and some number of pictures. The GOP header contains time and editing information.

The three types of pictures as explained earlier are:

♦ I-pictures ♦ P-pictures ♦ B-pictures

Note that because of the picture dependencies, the bitstream order (the order in which pictures are transmitted, stored, or retrieved), is not the display order, but rather the order in which the decoder requires the pictures for decoding the bitstream. For example, a typical sequence of pictures, in display order, might be as shown in Figure 1.2.

I B B P B B P B B P B B I B B P B B P

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

In contrast, the bitstream order corresponding to the given display order would be as shown in Figure 1.3.

Figure 1.3 Typical Sequence of Frames in Bitstream Order

I P B B P B B P B B I B B P B B P B B

0 3 1 2 6 4 5 9 7 8 12 10 11 15 13 14 18 16 17

Because the B-pictures depend on the subsequent I- or P-picture in display order, the I- or P-picture must be transmitted and decoded before the dependent B-pictures.

Pictures consist of a header and one or more contains time, picture type, and coding information.

A slice provides some immunity to data errors. Should the bitstream become unreadable within a picture, the decoder should be able to

1-6 Introduction

slices.

The picture header

Page 27

recover by waiting for the next slice, without having to drop an entire picture.

Slices consist of a header and one or more

macroblocks.

The slice

header contains position and quantizer scale information. A macroblock is the basic unit for motion compensation and quantizer

scale changes. In MPEG-2 the block can be either ﬁeld or frame coded. Each macroblock consists of a header and six component 8 x 8 blocks:

four blocks of luminance, one block of Cb chrominance, and one block of Cr chrominance. The macroblock header contains quantizer scale and motion compensation information.

A macroblock contains a 16-pixel by 16-line section of luminance component and the spatially corresponding 8-pixel by 8-line section of each chrominance component. A skipped macroblock is one f or which no DCT information is encoded.

Blocks

are the basic coding unit, and the DCT is applied at this block level. Each block contains 64 component pixels arranged in an 8 x 8 order. Note that pixel values are not individually coded, but are components of the coded block.

Note that the picture area covered by the four blocks of luminance is the same as the area covered by each of the chrominance blocks. Each luminance pixel corresponds to one picture pixel, but because the chrominance information is subsampled with a 2:1 ratio both horizontally and vertically (4:1 total), each chrominance pixel corresponds to four picture pixels.

1.1.3 Video Decoding

Video decoding is the reverse of video encoding and is intended to reconstruct a moving picture sequence from a compressed, encoded bitstream. Decoding is simpler than encoding because there is no motion estimation performed and there are far fewer options.

The data in the bitstream is decoded according to the syntax deﬁned in the MPEG-2 standard. The decoder must ﬁrst identify the beginning of a coded picture and identify the type of picture, then decode each individual macroblock within a particular picture. Motion vectors and macrobloc k types (each of the picture types I, P, and B have their own macroblock types) present in the bitstream, are used to construct a prediction of the

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current macroblock based on past and future reference pictures that the encoder has already stored. Coefﬁcient data is then inverse quantized and operated on by an inverse DCT process that changes data from the frequency domain to the time and space domain.

After the decoder processes all of the macroblocks, the picture reconstruction is complete. If the picture just reconstructed is a reference picture (I-picture or P-picture), it replaces the oldest stored reference picture and is used as the new reference for subsequent pictures. The pictures may need to be reordered before they are displayed, in accordance with the display order instead of the coding order. After the pictures are reordered, they may be displayed on an appropriate output device.

1.2 Audio Compression and Decompression Concepts

1.2.1 MPEG Audio Encoding

Given an

audio stream

elementary stream

of data (for audio data, this is called an

), an MPEG encoder ﬁrst digitally compresses and codes the data. The MPEG algorithm offers a choice of levels of complexity and performance for this process.

To prepare a stream of compressed audio data for transmission, it is formatted into correction data, and optional user-deﬁned frames are then sent in

System Stream

audio frames

. Each audio frame contains audio data, error-

packets

ancillary data

grouped within

packs

. The audio

in an ISO MPEG

The packs in system streams may contain a mix of audio packets and video packets f or one or more channels . Packs ma y contain packets from separate elementary streams. Thus, MPEG can easily support multiple

channels

of program material, and a decoder given access to a system

stream may access large numbers of channels.

MPEG audio encoding is intended to efﬁciently represent a digitized audio stream by removing redundant information. Because different applications have different performance goals, MPEG uses different encoding techniques. These techniques, called

Layers

, provide a different trade-off between compression and signal quality. The MPEG algorithm uses the two following processes for removing redundant audio information:

♦ Coding and quantization ♦ Psychoacoustic modelling

1-8 Introduction

Page 29

Figure 1.4 Audio Encoding Process (Simpliﬁed)

Coding and quantization are techniques that are applied to data that has been mapped into the frequency domain and ﬁltered into subbands.

Psychoacoustic modeling is a technique that determines the best allocation of data within the available data channel bandwidth based on human perception.

The general structure of an MPEG audio encoder is shown in Figure 1.4.

Digitized

Audio

Input

Frequency Filter Bank (Mapping)

Psychoacoustic

Model

Bit Allocation

Processor

(Among Subbands,

Coding, Quantizing)

Bitstream Formatter

Once audio data has been coded, it may be stored or transmitted digitally. MPEG provides a framework for use of packet-oriented transmission of compressed data. In particular, ISO CD 11172 deﬁnes formats for digital data streams for both video and audio. The ISO System Stream format is designed to accommodate both audio packets and video packets within the same frame work for transmission. The data may be physically delivered in parallel form or serial form. The System Stream is composed of a sequence of packs, as shown in Figure 1.5.

Figure 1.5 ISO System Stream

Pack Pack

. . .

Pack

Layer

Header

Contains: Pack Start Code (32 bits),

System Clock Reference (128 bits)

System

Header

Packet

An MPEG pack is composed of a

packet

, a sequence of

Packet

(ﬁrst) (last)(variable #)

More Packets

Contains:

Various data, including system stream ID

pack layer header

packets

, and ends with an ISO 11172

Packet ISO

Contains: Audio stream data (in audio frames)

11172

End Code

, a

system header

end code.

The pack layer header contains a pack start code used for synchroniza-

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tion purposes, and a system clock value. The system header packet contains a variety of housekeeping data and in particular contains a system stream ID used to differentiate multiple system streams. A sequence of one or more packets contains either encoded audio or encoded video stream data. The ISO 11172 end code is the ﬁnal element in an MPEG pack. For detailed deﬁnition of pack headers, refer to the ISO CD 11172-1 system stream descriptions.

Any one MPEG packet carries either audio or video data, but not both simultaneously. An MPEG Audio Packet contains an audio packet header and one or more Audio Frames. Figure 1.6 shows the packet structure.

Figure 1.6 MPEG Audio Packet Structure

Audio Packet

Audio

Packet

Header

Contains:

Packet Start Code Packet Length Presentation Time Stamps

Audio

Frame

(ﬁrst) (last)

(quantity varies)

. . .

Audio Frames

Contains: Audio Frame Header

Audio Frame CRC Audio Data Ancillary/User Data

Audio

Frame

Audio Packet

1.2.1.1 Audio Packet Header

An audio packet header contains the following:

♦ Packet Start Code

Identiﬁes this as an audio packet. The Packet Start Code also contains a ﬁve-bit audio stream identiﬁer that may be read by the user to identify the audio channel.

♦ Packet Length

Indicates the number of bytes remaining in the audio packet.

♦ Presentation Time Stamps (PTS)

. . .

The PTS indicates when audio data should be presented.

1.2.1.2 Audio Frame

An Audio Frame contains a slice of the audio data stream together with some supplementary data. Audio frames have the following elements:

1-10 Introduction

Page 31

♦ Audio Frame Header

Data in the audio frame header set the parameters that describe the format and mode of the audio data.

♦ Audio Frame Cyclic Redundancy Code (CRC)

This ﬁeld contains a 16-bit checksum, which can be used to detect errors in the audio frame header.

♦ Audio Data

The L64005 uses the audio data to reconstruct the sampled audio data. Its format is beyond the scope of this document. The data structures for Layer I dual channel/stereo, intensity stereo, and for the more complex Lay er II audio data ﬁelds are described in Sections

2.4.1.5 and 2.4.1.6 of the ISO CD 11172-3.

♦ Ancillary Data

The ﬁnal ﬁeld in an audio frame contains user-deﬁned data (ancillary data).

1.2.2 Audio Decoding

1.3 Standards Compliance

Audio decoding is the reverse of audio encoding and is intended to reconstruct the compressed audio data. MPEG audio decoding involves:

♦ identifying and removing a channel’s audio frames from the audio

packets in the System Stream

♦ managing the temporary storage of frames ♦ applying appropriate algorithms for decoding the audio frames ♦ merging decoded audio frames back into continuous audio ♦ limiting the effect of transmission errors

The L64005 conforms to the following international standards:

♦ MPEG-1. ISO/IEC 11172 (1993)

Moving Picture and Associated Audio for Digital Storage Media at up to about 1.5 Mbit/s

♦ MPEG-2. ISO/IEC 13818

Associated Audio,

Generic Coding of Moving Pictures and

International Standard.

Information Technology—Coding of

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1.3.1 MPEG-1

The MPEG-1 International Standard (ISO/IEC IS 11172-2, -3) deﬁnes both audio and video services and is targeted at compressing audio and video services for storage on CD-ROM. Typically MPEG-1 video streams will be Standard Image Format (SIF) resolution, which is 240 x 352 pixels at 30 frames per second (NTSC). The total data stream is compressed to 1.864 Mbits/s. The video and audio portions (11172-2 and 11172-3) of MPEG-1 have been adopted as ISO International Standards, whereas the conformance portion (11172-4) is still an ISO Draft International Standard.

1.3.2 MPEG-2

1.4 Terms and Concepts

The MPEG-2 International Standard (ISO/IEC IS 13818) more effectively addresses the needs of the TV industry. The most signiﬁcant need is to decompress a video stream of up to 720 x 480 resolution at 30 frames per second (NTSC), with a compressed data rate above 10 Mbits/s. A signiﬁcant limitation of MPEG-1 is that the video is encoded in a progressive (non-interlaced) format, whereas TV source material is in an interlaced format in which each frame is comprised of two interlaced ﬁelds. MPEG-2 allows the encoder to switch between ﬁeld or frame prediction and coding at the macroblock level, depending on which produces the best overall coding gain.

The MPEG algorithm is asymmetric, meaning in this case that the encoding is more complex than the decoding. More expensive encoders than decoders ﬁts the scale of economy for these applications that require many decoders to a few encoders.

The L64005 is fully complaint with the MPEG-2 standard main proﬁle, main level.1 As such it can also decode an MPEG-1 video sequence.

The following section lists and deﬁnes terms and concepts that are helpful throughout this document.

3:2 Pulldown. 3:2 pulldown is used for conversion from ﬁlm to video. Film material digitized at 24 pictures per second forms an excellent source for the MPEG video bitstream. Sometimes source material available for compression consists of ﬁlm material that has been converted to video at some other rate. The encoder can detect the rate difference and

1. The MPEG-2 standard deﬁnes “proﬁles” and “levels” as a means of specifying subsets of the syntax and semantics of the standard. Refer to the ISO/IEC 13818 standard for details.

1-12 Introduction

Page 33

recode at the original ﬁlm rate. For example, ﬁlm material at 24 pictures per second may have been digitized and converted to a 30 frame-persecond system by the technique of 3:2 pull-down. In this mode, digitized pictures are shown alternately for three and for two television ﬁeld times. A television ﬁeld time is 60 ﬁelds per second.

In order for video at 30 frames per second to be shown at the television ﬁeld rate, each frame is simply shown for two television ﬁeld times. However, to display 24 frame-per-second video at the television frame rate, 3:2 pull-down is necessary. A single frame of 24 frame per second video is repeated three times at the television ﬁeld rate, followed by the next frame repeated two times. This pattern of three and then two repeated frames continues. The net result is that a total of two frames of 24 frameper-second video is displayed over a period of ﬁve television ﬁeld times, or 5/60ths (1/12th) of a second. This result is exactly the same amount of time occupied by two frames of 24 frame per second video

124⁄ 2× 112⁄=()

. Therefore 3:2 pull-down allows video digitized at 24 frames per second to be displayed at the television ﬁeld rate with no jerkiness or loss of synchronization.

ADPCM. Adaptive Differential Pulse Code Modulation. A type of DPCM in which the algorithm dynamically adjusts to the content of the data being encoded.

B-Channel. ISDN communications channel carrying 64 Kbit/s. CCIR. Consultative Committee for International Radio. CCIR601. Recommendation for digital video (4:2:2, 720 samples per

line). Also recommends chromaticity for YCrCb color space. CCITT. International Telegraph and Telephone Consultative Committee.

Renamed ITU-TSS.

CD-ROM. Compact Disk Read-Only Memory. CD-ROM XA. CD-ROM extended architecture (speciﬁes ADPCM

qualities). CMYK. Cyan, Magenta, Yellow, Black. These colors are used in the print-

ing industry. Chrominance. The color information portion of a signal (UV por tion of

YUV). See YUV.

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Codec. Coder/decoder. Composite Signal. Single signal that encodes the luminance and

chrominance signals. Component Signal. Signal which contains either the luminance or the

chrominance component. DCT. Discrete Cosine Transform. A DCT converts data from the time

(spatial) into the frequency domain.

DIS. Draft International Standard. DPCM. Differential Pulse Code Modulation. This type of modulation

transmits only the differences between two values.

DVI. Digital Video Interactive. Entropy Coding. An efﬁcient coding method that encodes frequent

events with fewer bits than it does with infrequent events.

FDCT. Forward DCT, the usual form of DCT. Field. A ﬁeld is the complete set of the even or the odd scan lines. In

television, a single frame consists of two ﬁelds containing the odd and even scan lines, respectively.

fps. Frames per second. Frame. In motion video, a single image. Frames can be presented at 25

frames per second (PAL standard) or at 30 frames per second (NTSC standard).

Genlocking. Synchronizing signals to an external video source. HDTV. High Deﬁnition TV (for example, 1125 or 1250 lines). Huffman Coding. A static set of minimum redundancy, integral-length bit

strings. Huffman coding is a type of entropy coding that uses predetermined variable-length codewords.

IDCT. Inverse DCT. An IDCT converts data from the frequency domain into the time (spatial) domain.

IEC. International Electrotechnical Commission.

1-14 Introduction

Page 35

Interframe Compression/Decompression. These techniques, including MPEG, encode the differences between successive fr ames . This process suits motion video that does

not

require frame-by-frame editing.

Intraframe Compression/Decompression. These techniques, including JPEG, encode each frame independently. This process suits motion video that does require frame-by-frame editing.

Interlaced Scan. Displays odd lines in a frame, then displays even lines. Inverse Quantization. Scaling up of previously quantized data into

larger-range numbers.

IS. International Standard. ISDN. Integrated Services Digital Network. ISO. International Standards Organization. ITU-TSS. International Telecommunications Union, Telecommunication

Standardization Sector (known as CCITT before March 1, 1994). The ITU-TSS is responsible for making technical recommendations about telephone and data (including fax) communications systems. Every four years they hold plenary sessions where they adopt new standards; there was one in 1992.

JPEG. Joint Photographic Experts Group. JPEG also refers to a multipart standard (ISO/IEC IS 10918) that the group has ﬁnalized for still-frame images.

Lossless (noiseless) Compression. Technique that ensures or iginal data is completely recoverable.

Lossy (noisy) Compression. Technique that does

not

ensure original

data is completely recoverable. Luminance. Brightness of an image (Y por tion of a YUV signal). See

YUV. MPEG. Moving Picture Experts Group. Also the name of a multipart stan-

dard the group is currently developing for full-motion, color video. Motion Compensation. Image compression that takes into consider-

ation partial image shifts that are due to motion.

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Motion Estimation. The prediction of pixel or block movements between frames.

NTSC. National Television System Committee. NTSC also refers to the TV standard in the United States and Japan.

PAL. Phase Alternating Line. PAL also refers to the TV standard in much of Europe.

PCM. Pulse Code Modulation. Used in CD audio. PEL. Picture element or pixel. PES. Packetized Elementary Stream. Progressive Scan. Same as non-interlaced. Each line of a frame is dis-

played sequentially. Quantization. A process of scaling down data represented by many bits

into a lower-precision value requiring fewer bits. RGB. Red, Green, Blue. RGB is the color system used in the computer

industry. The display signal is composed of separately controllable red, blue, and green signals, as opposed to composite video in which the luminance and chrominance video signals are combined prior to output.

Run-Length Coding. Run-Length coding replaces sequences of bits with a run-level pair that indicates the number of z eroes in a row followed by a coefﬁcient.

Spatial Redundancy. Compressible repetition of patterns in a 2-d image.

SECAM. Sequentiel Couleur avec Memoire. SECAM is the TV standard in France and much of the former Soviet Union.

SMPTE. Society of Motion Picture and Television Engineers. SMPTE Time Code. Standard (hr:min:sec:frame) method to record and

identify video frames. T-1 Channel. A T-1 channel transmits and receives digital data at 1.44

Mbits per second.

1-16 Introduction

Page 37

Temporal Redundancy. Compressible repetition in motion video between frames.

Transform Coding. Maps statistically dependent pixels to independent coefﬁcients.

Variable-Length Coding. Encoding that creates codewords of variable numbers of bits. See

Huffman coding

VBI. Vertical blanking interval. YUV. Color space used in PAL. Y is luminance; U and V are the 1.3-MHz

color difference (U =Y–R and V = Y – B) chrominance components. Zigzag Scanning. This method reorders data by reading it in diagonal

order from upper left (0, 0) to lower right prior to run-length coding.

1.5 System Overview

1.5.1 Video Decoding

1.5.2 Audio Decoding

The L64005 is speciﬁcally designed for use in digital audio and video decoding systems based on the MPEG-2 algorithm (herein referred to as MPEG). The device may be considered a “black box” that receiv es coded audio and video data and produces a decoded audio and video data stream. LSI Logic has optimized L64005 input/output interfaces for lowcost integration into an embedded application. The L64005 core logic is based on the proven L64002 MPEG-2 Video Decoder. The system block diagram in Figure 1.7 shows how an audio/video decoding system uses the L64005.

The L64005 operates optimally at image sizes up to 720 x 480 pixels, with a frame rate of 30 fps (720 x 576 @ 25 fps for PAL). This is sometimes referred to as “main level, main proﬁle” of MPEG-2. As such it can also decode MPEG-1 sequences. The coded data channel may have a bit rate of up to 20 Mbit/s for serial, and 40 Mbit/s for parallel. The L64005 supports image resolutions up to 720 x 480 in dimension multiples of 16 pixels. As the resolution decreases, the amount and bandwidth of DRAM memory required for frame stores also decreases.

The L64005 also integrates an MPEG audio decoder (MUSICAM). The audio decoder is capable of decoding two channels of MPEG audio Layer 1 or Layer 2 over the full range of compliant bit rates and sample rates. The audio decoder uses the same external memory as the video

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decoder for its channel buffers, eliminating the need for the extra DRAM found in non-integrated audio solutions.

1.5.3 Post Processing

Figure 1.7 System Block Diagram

The L64005 uses on-chip interpolation ﬁlters to interpolate images with resolutions below 720 x 480 to full size. This allows programming produced at different resolutions to be decoded and displayed on televisions with standard NTSC or PAL timing. As well, these ﬁlters enable the decoder to interface with digital or analog NTSC or PAL modulators operating at standard frequencies (typically 27 MHz). Using these ﬁlters, the decoder also supports pan and scan of the MPEG image to 1/8 pixel accuracy.

Baseband

Video

Stereo

Audio

ROM/

EEPROM

Video Coder/

DACs

CD Audio DACs

Microcontroller

L64005 MPEG-2

A/V Decoder

2 MByte

DRAM

or SDRAM

Demodulator/

ECC/

Decrypt/

Transport

Baseband Channel

1.5.4 On-Screen Display

The L64005 also integrates an on-screen display controller capable of overlaying an image up to 720 x 480 pixels (720 x 576 for PAL) at up to 4 bits/pixel on top of an MPEG video sequence while it is being decoded. Up to 16 colors can be selected per scan line. Each scan line may have its own set of colors. Bitmaps for on-screen display may be assembled off-screen then made visible instantaneously. Hardware panning and scrolling of the overlay data is supported. The overlay planes remain ﬁxed in size regardless of the resolution of the MPEG sequence. This means that scaling of the MPEG sequence to full-frame display does not affect the size or ﬁdelity of text on the overlay plane.

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1.5.5 PES Decoding

The L64005 is capable of decoding either separate video and audio streams, or a program stream (PES) containing both audio and video streams.

1.5.6 Video Output

1.5.7 Audio Output

1.5.8 User Interface

The L64005 provides a digitized video output for subsequent display. This data is in the CCIR 601 (Y, Cb, Cr) color space. The video output operates with a luminance sample rate that is always exactly half the device clock—nominally 13.5 MHz from a 27-MHz clock. The L64005 provides video synchronization signals in master mode, or can accept external synchronization signals in slave mode.

The audio decoder produces a serial PCM, or I2S output that is compatible with most commercial audio DACs. Since the audio and video decoders operate off the same clock, synchronization is greatly simpliﬁed. The audio decoder includes circuitry to maintain the correct audio output sample rate regardless of the input clock rate.

A user port allows you to program system options and monitor the operation of the device. Errors ﬂagged by the L64005 and user data present in this channel may be read through this port. However, the device will not maintain unread user data indeﬁnitely. Once the L64005 FIFO is full, no more data is written to the FIFO and subsequent data will be lost. The system controller must read data transmitted in the user data records of the MPEG bitstream, even if that data is subsequently used to control some aspect of the video display subsystem. To avoid losing data, the controller must read this data, then write it to L64005 internal state registers, if necessary. The user port is also used to write data into the video overlay memory.

1.5.9 Memory Utilization

The L64005 supports direct connection to regular or synchronous DRAMs for use as frame stores, channel buffers, and overlay memory. The L64005 uses frame stores for intermediate frame reconstruction and display, separate video and audio channel buffers for rate matching, and zero or more regions for graphical overlay. This storage is combined into a single contiguous memory space accessed over a 64-bit wide bus. In most cases this will be four 256k x 16 regular DRAMs, or a single 1M x 16 SDRAM, for a total memory space of 2 MByte. The interface between the L64005 and external memory requires no external compo-

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nents. During normal operation, the L64005 exclusively controls the external memory frame stores. However, it is possible to access the external memory through the user por t on the L64005 for test, veriﬁcation, and access to the overlay stores.

1.5.10 Error Concealment

1.5.11 Mechanical and Electrical

1.6 L64005 Overview

The L64005 handles coded channel data that is assumed to be an MPEG-2 compliant bitstream with excellent error performance. The L64005 detects data in the bitstream that does not meet MPEG-2 syntax or grammar rules and can ﬂag the data for exception processing. Hardware error handling is limited to error masking and the application of concealment vectors, or redisplay of the previous frame. The L64005 ﬂags gross errors in the bitstream that occur because of channel buffer overrun, channel buffer underrun, or non-conformance in the bitstream. The L64005 ﬂags the errors so that they may be masked in the display or on the audio output. An external programmable microcontroller may execute mechanisms to recover from gross errors.

The L64005 is available in a 160-pin plastic quad ﬂat package (PQFP). LSI Logic manufactures the L64005 with its 0.5 micron, 3.3-V CMOS process (Revisions D and prior), and with its 0.35 micron, 3.3-V CMOS process (Revision E and later).

The following subsections provide an overview of the L64005. Included in the following subsections are descriptions of the video decoder, the on-screen display controller, the audio decoder, and the channel interface. System layer decoding, bitstream syntax and grammar, and the video output features of the L64005 are also described.

1.6.1 MPEG-2 Video Decoder

The L64005 is a main level, main proﬁle MPEG-2 decoder. It is fully compatible to the MPEG-2 standard, including support for adaptive ﬁeld/frame motion compensation, dual prime motion compensation, concealment motion vectors, alternate block scan, 3:2 pulldo wn and pan and scan modes to 1/8 pixel accuracy. The MPEG decoder is based on the proven L64002 core with these enhancements:

♦ Improved DRAM interface provides the option to use one 1Mx16 syn-

chronous DRAM chips, or four 256Kx16 regular DRAM chips.

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♦ Reduced Memory Mode, capable of decoding and displaying a full

resolution PAL with 16-color OSD with only 2 MBytes of external DRAM.

♦ Addition of on-chip PLL provides higher bandwidth that triples the

DRAM interface clock frequency from 27 MHz to 81 MHz.

1.6.2 System Layer Decoding

The L64005 performs MPEG-2 system layer decoding of the Pack and PES layer. The primary purpose of Pack and PES decoding is to support the extraction of the video and audio timestamps, which are then used for synchronization purposes. The system layer is parsed bit serially before the data is written to the channel buffers.

The L64005 parses MPEG-2 Pack Layer and video and audio PES packets only. Other types of PES packets are discarded. The video and audio streams are separated into header and payload streams and written to independent buffers in the DRAM. There are therefore four buffers: video payload, video PES header, audio payload and audio PES header. The video and audio payload buffers are the video and audio channel buffers. The PES header buffers queue pending header information until decode time. The external microprocessor may read the contents of the PES header buffers at any time. The external processor can synchronize audio and video by reading the presentation timestamps from the PES header buffers, adjusting them for system dependent delays, and then writing the adjusted values back to the L64005. The adjusted values are compared with a local copy of the system clock reference at the presentation time of the respective audio and video presentation units. The error between the actual presentation time and the desired presentation time can then be determined. Depending on the sign and magnitude of the error, the audio and video decoders may then be independently instructed to skip or repeat a frame. This process continues until the decoders are synchronized to the system clock reference.

1.6.3 Video Output Features

Other parameters carried in the PES headers may be read on demand and limited to the length of the PES header buffers—which is programmable.

The decoder outputs video through an 8-bit interface clocked at the device clock. It is expected that in a given implementation, the L64005 will be operated at the nominal clock frequency of 27 MHz. This clock provides both the computational timebase as well as the video timing ref-

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erence. Internal post-processing ﬁlters interpolate decompressed images with a horizontal size of less than 720 pixels so that they ﬁll a complete scan line at the operational clock frequency.

1.6.3.1 8-Bit CCIR 601 Interface

The CCIR 601 interface allows data to be time-division multiplexed onto a single 8-bit interface—which supports easy connection to SMPTE RP-125 type connectors. Eight-bit CCIR 601 is the preferred interface for professional quality video equipment. It is also compatible with the Philips SAA7188 DENC chip and similar devices from Raytheon (TRW) and Brooktree that can digitally modulate the signal to NTSC or PAL.

1.6.3.2 Post-Processing Filters

Decompressed images with fewer than 720 horizontal pixels, or selected sections of images (such as the visible portion in pan and scan mode), may be interpolated to occupy a full scan line using on-chip poly phase interpolation ﬁlters. The ﬁlters are 64-tap oversampling ﬁlters and provide up to eight output samples for every two input samples. The ﬁlter coefﬁcients are ﬁxed as a windowed sync function. Sub-pixel accuracy of the interpolator is 1/256th of a pixel. These ﬁlters are also used during subpixel pan and scan to position the reconstructed output image to within 1/8 of a pixel.

1.6.3.3 Interlaced/Chroma Field Repeat or Chroma Line Repeat Video Output

The L64005 can output video to an interlace-scanned video monitor or television. The video timing circuitry must output the correct pulse train for both odd and even ﬁelds, as well as the transition between ﬁelds. The number of active scan lines in a typical ﬁeld is 240, though the actual value is programmable.

In the interlaced/chroma line repeat output mode, the decoder outputs each chroma line twice on neighboring lines in each ﬁeld.

1.6.3.4 Progressive/Field Repeat Video Output

The progressive/ﬁeld repeat video output mode is used in low resolution modes when there are typically 240 lines in a luma frame. The luma data is displayed twice, once in each ﬁeld time. The chroma data is displayed

1-22 Introduction

Page 43

four times; each line is repeated on neighboring lines, and the ﬁeld is displayed twice.

The L64005 may be programmed to repeat a ﬁeld. The full picture can be displayed during each ﬁeld of an interlaced video display system. This feature is only available when not using Reduced Memory Mode, however.

1.6.3.5 Field Pulldown

3:2 pulldown may be optionally performed during display. The ﬁeld on which 3:2 pulldown starts may be programmed. Also, the 3:2 pattern ma y be modiﬁed at any time. The proﬁle of the 3:2 pulldown is communicated in the MPEG-2 video stream. The L64005 extracts this data directly from the stream and applies it to the appropriate ﬁeld. 3:2 pulldown may only be performed if the device is not operating in reduced memory mode.

The L64005 may also be programmed to freeze any given ﬁeld or frame whilst operating in normal mode. In reduced memory mode it is not possible to freeze on a B frame.

1.6.3.6 16:9 Operation

A source image with a 16:9 aspect ratio is compacted into a 4:3 ratio before image coding and transmission. It is necessary to display a 4:3 aspect ratio window onto this image by interpolating a segment of each scan line prior to display. The on-chip inter polation ﬁlters perform this function. A pan-and-scan feature is also included, with the appropriate parameters communicated within the user data or the MPEG-2 stream.

1.6.3.7 Time Base Correction

Variations in system time base can produce long-term dr ift between the channel bitstream rate and the video rate. The decoder skips or repeats the display of certain frames to achieve time base correction. The L64005 decodes repeated frames once but displays them more than once. Skipped frames are not decoded or displayed; they are skipped over in the channel buffer. If B-frames are present in the stream, then they can be selected for repeating or skipping. If only I and P frames are in the stream then the next P frame is repeated or skipped. If only I frames are in the stream then, any I frame may be repeated or skipped. Note that this correction mechanism may produce undesirable effects if it is performed too often. Ideally, the decoder clock should be locked to

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the encoder clock so that local time base correction is unnecessary. However, with 10 ppm accuracy in the encoder and 50 ppm accuracy in the decoder, the decoder and encoder may drift by as much as one frame every 9 minutes, so some form of correction is clearly desirable.

1.6.3.8 Vertical Blanking Interval

Data stored in the frame stores can be output during the vertical blanking interval. This data does not constitute part of the MPEG image, but it can be downloaded by the user, and can be used for optional features such as VITS and closed caption.

1.6.4 On-Screen Display

1.6.5 Audio Decoder

The L64005 integrates a ﬂexible on-screen display controller that allows the overlay of text and graphics on top of the decoded video. The overlay is digitally mixed with the decoded video immediately before it is output on the video port. The overlay data is always displayed at the same size regardless of the resolution or mode of the video data. Pan and scan of the video data does not affect the position of the overlay data. Two basic modes supported for the overlay data are:

♦ Up to 720 x 576 pixels at 2 bits/pixel ♦ Up to 720 x 576 pixels at 4 bits/pixel

A color expansion feature and color palette allow for ﬂexibility in color selection. In addition, various sub-formats can be supported, including 240 line operation which presents a full sized ﬂicker-free image.

The L64005 integrates an MPEG audio decoder, capable of decoding two audio channels at bit rates of up to 448 kbps. The decoder operates at MPEG Layer 1 or Layer 2 only.

1.6.5.1 Input Buffering

The L64005 provides for an audio channel buffer (rate buffer) as part of the attached DRAM store. This offers considerab le sa vings o v er separ ate audio decoders which need an additional DRAM for channel buffering when operating in conjunction with a video decoder. The audio channel buffer is maintained separately from the video channel buffer.

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1.6.5.2 Audio Output

Audio output is over a three-wire serial PCM stream. The signals are: BCLK, a serial bit clock; ASDATA, a serial PCM data output; and LRCLK, the left/right channel indication. In addition, the emphasis output is optionally available.

1.6.5.3 Audio Decode Rate Control

The L64005 decodes audio data at a rate proportional to the audio sample frequency. The sample frequency is either derived internally from the 27-MHz SYSCLK reference, or externally from the oversampling clock reference input, ACLK. When using the internal reference clock, BCLK is derived from the 27-MHz reference using an numerically controlled oscillator (NCO) which acts as a N/M clock divider circuit. Note that in this case, care must be taken to avoid non-integer results in order maintain a phase constant BCLK frequency. If not, the phase is jittered about the desired frequency and although this will work for in-expensive broadband DAC’s, it’s generally not acceptable for the more commonly used oversampling DAC’s. If an external reference is selected, care must be taken to ensure that the reference is locked to the actual audio sample rate in the encoder. This can be done with a VCO or VCXO with a control voltage derived from the audio presentation time stamp, or otherwise locked to the encoder. Some oversampling DAC’s have very good on board sample frequency generation circuitry. Failing to adhere to these precautions will result in eventual underﬂow or overﬂow in the audio channel buffer unless other buffer management precautions are taken.

1.6.5.4 Support for Low Sampling Frequencies

The L64005 also supports Layer 1 and Layer 2 decoding at sample rates of 24 kHz, 22.05 kHz and 16 kHz as deﬁned in ISO/IEC 13818-3, an extension to the MPEG audio deﬁnition. The new deﬁnitions for the sampling frequency ﬁeld, bitrate index ﬁeld, and bit allocation are selected when the frame header ID bit is zero.

1.6.5.5 Signiﬁcant Differences from the L64002

See “Notice for L64002 Users,” in the Preface for more detail.

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1.6.6 System Controller Interface

An external system controller (microcontroller) is responsible for test, initialization, and real-time control of the L64005. The interface between the system controller and the L64005 is 8 bits wide and fully asynchronous.

1.6.6.1 Device Initialization

The system controller deﬁnes the operational mode of the L64005 decoder. L64005 operational modes are controlled through a number of internal state registers, which may be read or written over the interface. Device initialization parameters include frame size, sync pulse widths, active image size and position, frame mode, horizontal re-sizing, and channel buffer size. The programmability of these parameters greatly increases the ﬂexibility of the L64005 for systems with different resolutions and display system characteristics.

1.6.6.2 Operational Monitoring

The behavior of the L64005 video decoder can be monitored over the system controller interface. Parameters include channel buffer fullness, detected bitstream errors, and status of video sync signals. The L64005 internally arbitrates access to the frame stores is arbitrated in the L64005. Frame store accesses from the system controller have a lower priority than any other access in the system.

1.6.6.3 Interrupts

The L64005 has multiple interrupt sources, which include synchronization events, detectable errors, channel status, and display status. Interrupts are signalled to the system controller over a single interrupt pin, and are selectively maskable through the controller port. Pending interrupts may be read from an internal register. Interrupts make the program in the system controller more efﬁcient because the interface does not need to be polled.

1.6.6.4 Test

Frame memories can be tested by randomly reading and writing them through the interface. An internal address indirection register controls the addressing of these accesses. The L64005 arbitrates between these accesses and those of other subsystems internally.

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1.6.6.5 Channel Data Writes

Channel data can be written directly through the system controller interface instead of through the serial channel interface. Direct writing supports the parallel interfaces that are found in computer systems, particularly CD-ROM players. An internal control bit selects the serial/parallel mode. It is the user’s responsibility to ensure that writes to the parallel channel interface do not exceed the channel rate. State bits are provided that allow the user to poll the busy status of the audio and video channel. Output pins are also provided that reﬂects this status. These pins are used where a hardware handshake is needed.

1.6.7 Channel Interface

1.6.8 Bitstream Syntax and Grammar

Coded bitstream data is typically written serially into the L64005. On each rising edge of a serial channel clock, the decoder reads a single bit and an associated data-valid signal. The peak sustained rate on the serial interface is a function of the device clock. At the nominal frequency of 27 MHz, this rate is 20 Mbits/second. The instantaneous burst rate on the serial channel is faster and a function of device characterization. The burst rate limits the packet length and packet separation in a variable channel rate system.

Synchronization circuitry in the channel interface allows the device clock and the channel clock to run at different rates. The coded MPEG data does not need to be byte aligned in the stream.

The L64005 operates on MPEG-2 bitstream syntax. The device can decode either an MPEG-2 or MPEG-1 video sequence layer. If presented with an MPEG-1 System Layer bitstream, the L64005 parses out and decodes the Packet Layer and the Video Sequence Layer inside—which may be either an MPEG-1 or MPEG-2 stream.

1.6.8.1 User Data

User data in the channel is buffered on-chip and may be read by the system controller. The on-chip user data FIFO is intended to buffer data until the system controller can service an interrupt and read the data. If the data is not read, the FIFO overﬂows and all user data in the FIFO is invalidated until the user data FIFO is reset. It is the responsibility of the system controller to act on user data when appropriate.

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1.6.8.2 Program Change

If the coded data in the channel is changed to a new program source, the system controller must inform the bitstream parser to stop decoding and search for a new intra-frame resynchronization point. The L64005 then freezes on the last complete anchor frame until a new sequence is acquired. Program acquisition time is a function of the encoder sequence header length. B frames with a broken link are decoded unless the system controller forces resynchronization. The system controller restarts the L64005 when the channel buffer reaches an adequate threshold.

1.6.8.3 Virtual Program Channels

A seamless switch between virtual program channels may be achieved if the different channels within a channel group have a temporally aligned group of frame headers. Virtual channel switch is a function of the channel demultiplexer in the decoder. The L64005 handles virtual channel switching such as a regular P frame to I frame transition in the bitstream. Note that in a virtual channel scheme, no B frames can cross over the group of frames boundary; these would constitute a broken link in the new group— which would lead to a discontinuity in the video or depletion of the channel buffer. Constraining B frames in a virtual channel scheme is a function of the encoder. The system controller can freeze the display if the channel becomes depleted because of a channel switch.

1.6.8.4 Channel Panic Modes

The channel buffer has no explicit panic modes, because it is generally not deﬁned where buffer thresholds should be set. If the channel buffer underﬂows, the L64005 can optionally interrupt the external controller and then instigate a freeze frame. If the channel buffer overﬂows, the L64005 generates an interrupt. The typical recovery mechanism is identical to a channel switch; that is, the decoder freezes after the last good frame, the broken frame is discarded, and the decoder is set to resynchronize on a new group of frames. In a system with a properly matched encoder and decoder, panic modes are not necessary.

1.7

This section lists supported features and discusses their application.

Features

♦ Provides a highly integrated, studio quality MPEG-2 audio/video

decoder solution.

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♦ Decodes an MPEG-2 bit stream, including the MPEG-2 PES layer. ♦ Decodes an MPEG-1 bit stream as deﬁned in ISO IS 11172, includ-

ing the MPEG-1 system layer.

♦ Decodes dual channel MPEG audio, La yer 1 and 2 (MUSICAM), with

additional support for low sample rate coding and data rates from 8 to 448 kbps.

♦ Operates at image sizes up to CCIR 601 resolution 720 x 480 pixels

@ 30 fps for NTSC and 720 x 576 @ 25 fps for PAL.

♦ Supports master or slave video timing operation. ♦ Integrates post processing ﬁlters for image resizing. ♦ Integrates a ﬂexible on-screen display controller. ♦ Implements 3:2 pulldown and various wide screen modes, including

16:9 mode.

♦ Supports up to 20 Mbps serial, or 40 Mbit/s parallel, input channel

data rate.

♦ Supports 1-bit serial or 8-bit parallel input data formats through the

control of an external microcontroller.

♦ Provides 8-bit Y/C output data format in interlaced or progressive

scanned mode.

♦ Interfaces directly to LSI Logic's L64007, L64008, and L64108 trans-

port demultiplexers on the input and off-the-shelf NTSC/PAL encoders on the output.

♦ Provides a complete on-chip channel buffer and display buffer con-

trols.

♦ Includes programmable display management. ♦ Interfaces to an inexpensive 8-bit microcontroller for initialization,

testing and status monitoring.

♦ Supports downloadable quantization tables through bitstream. ♦ Provides programmable channel buffer and display buffer size. ♦ Connects directly to commodity DRAMs. ♦ 16 Mbits of DRAM, from four 4-Mbit regular DRAMs or one 16-Mbit

SDRAM, is required for CCIR601 resolution.

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♦ Maintains display of images during channel errors with error conceal-

ment.

♦ Provides selectable error concealment in audio decoder. ♦ Requires no external microcode or external logic. ♦ Optimizes input/output interfaces for glueless integration into con-

sumer video system to provide a cost effective solution.

♦ Operates from a single 27-MHz clock, with optional additional audio

sample clock input.

♦ Packaged in a 160-pin copper lead frame PQFP (plastic quad ﬂat

pack).

♦ Uses low power 3.3 V process. ♦ Includes TTL compatible I/O pins.

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Chapter 2 Registers

This chapter discusses the L64005 internal registers. It also provides a description of the internal memor y mapping and how the registers are accessed from the system interface. This chapter is intended primarily for system programmers who are developing software drivers.

This chapter contains the following sections:

♦ Section 2.1, “L64005 Register Overview” ♦ Section 2.2, “Group 0 Address Indirection Register” ♦ Section 2.3, “Group 1 Status 0 Register” ♦ Section 2.4, “Group 2 Status 1 Register” ♦ Section 2.5, “Group 3 Interrupt Register 0” ♦ Section 2.6, “Group 4 Interrupt Register 1”

2.1 L64005 Register Overview

♦ Section 2.7, “Group 5 Control Register” ♦ Section 2.8, “Group 6 Secondary Control Registers” ♦ Section 2.9, “Group 7 Secondary Control Registers”

The L64005 uses an address indirection scheme to access a large number of internal state registers using a small number of external address pins. A preset auto-incrementing address pointer may be used to index to any register in Group 6 or Group 7. Table 2.1 shows address groupings.

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Table 2.1 Register Groups and Function

Table 2.2 L64005 Register Map

Group Function

0 Address Indirection Register 1 Status 0 Register 2 Status 1 Register 3 Interrupt 0 Register 4 Interrupt 1 Register 5 General Register 6 Display Control and Audio Registers 7 DRAM and Display Control Registers

The registers are grouped according to function. A map of the registers is given in Table 2.2.

Group Index Bit(s) R/W Status/Command/Data

0 N/A 7 R Auto-decrement Status

W Auto-decrement Enable

6 R Auto-increment Status

W Auto-increment Enable

1 N/A 7 R Channel Status

(Sheet 1 of 13)

2-2 Registers

5:0 R Current Index

W Load New Index

W Channel Star t/Reset 6 R Video Req Channel Ready 5 R Audio Req Channel Ready

W Audio Stream Select Enable 4:0 W Audio Stream ID 4:2 R Aux Data Layer ID 1:0 R Aux Data FIFO Status

Page 53

Table 2.2 (Cont.) L64005 Register Map

Group Index Bit(s) R/W Status/Command/Data

2 N/A 7:6 Reserved

5 W Reset Channel and PES Buffer on Error 4 W Video Stream Select Enable 3:0 W Video Stream ID 3:2 R User Data Layer ID 1:0 R User Data FIFO Status

3 N/A 7 R DRAM Transfer Done

W DRAM Transfer Done Mask 6 R Pack Data Ready

W Pack Data Ready Mask 5 R SCRS Interrupt

W SCRS Interrupt Mask 4 R Picture Start Code Detect

W Picture Star t Code Detect Mask 3 R Audio Sync Code Detect

W Audio Sync Code Detect Mask 2 R Decode Error

W Decode Error Mask 1 R Data FIFO Ready

W Data FIFO Ready Mask 0 R Decode Status (Non-maskable Interrupt)

W Decode Star t/Stop

(Sheet 2 of 13)

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Table 2.2 (Cont.) L64005 Register Map

Group Index Bit(s) R/W Status/Command/Data

4 N/A 7 R Video PES Data Ready

W Video PES Data Ready Mask 6 R Audio PES Data Ready

W Audio PES Data Ready Mask 5 R Begin Vertical Blank

W Begin Vertical Blank Mask 4 R Begin Active Video

W Begin Active Video Mask 3 R Video Channel Buffer Underﬂow

W Video Channel Buffer Underﬂow Mask 2 R Audio Channel Buffer Underﬂow

W Audio Channel Buffer Underﬂow Mask 1 R Video Channel Buffer Overﬂow

W Video Channel Buffer Overﬂow Mask

5 N/A 7 R/W Refresh When Idle

6 0 7:0 R User Data FIFO Output (Sheet 3 of 13)

2-4 Registers

0 R Audio Channel Buffer Overﬂow

W Audio Channel Buffer Overﬂow Mask

6 R/W Enable Parallel Stream 5:4 R/W Stream Select 3 W Reset Video System Buffer 2 W Reset Audio System Buffer 1 W Reset Aux Data FIFO 0 W Reset User Data FIFO

Page 55

Table 2.2 (Cont.) L64005 Register Map

Group Index Bit(s) R/W Status/Command/Data

6 1 7 R System Clock Reference Match

6 R System Clock Reference Overﬂow 5 R Audio Reconstruction Error 4 R Audio Sync Error 3 R Audio CRC or Illegal Bit Error 2 R Video Reconstruction Error 1 R Context Error 0 R Variable Length Code or Run-Length Error

2 7:0 R/W For Anchor Luma Base Address (LSB) 3 6:0 R/W For Anchor Luma Base Address (MSB) 4 7:0 R/W For Anchor Chroma Base Address (LSB) 5 6:0 R/W For Anchor Chroma Base Address (MSB) 6 7:0 R/W Back Anchor Luma Base Address (LSB) 7 6:0 R/W Back Anchor Luma Base Address(MSB)

8 7:0 R/W Back Anchor Chroma Base Address (LSB) 9 6:0 R/W Back Anchor Chroma Base Address (MSB) 10 7:0 R/W Display Luma Base Address (LSB) 11 6:0 R/W Display Luma Base Address (MSB)

12 7:0 R/W Display Chroma Base Address (LSB) 13 6:0 R/W Display Chroma Base Address (MSB)

14 7:0 R/W VBI1 Luma Base Address (LSB) 15 6:0 R/W VBI1 Luma Base Address (MSB)

16 7:0 R/W VBI1 Chroma Base Address (LSB) 17 6:0 R/W VBI1 Chroma Base Address (MSB)

18 7:0 R/W VBI2 Luma Base Address (LSB)

(Sheet 4 of 13)

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Table 2.2 (Cont.) L64005 Register Map

Group Index Bit(s) R/W Status/Command/Data

6 19 6:0 R/W VBI2 Luma Base Address (MSB)

20 7:0 R/W VBI2 Chroma Base Address (LSB) 21 6:0 R/W VBI2 Chroma Base Address (MSB)

7 R/W VBI2 Select 6:5 R/W Reserved 4:0 R/W VBI Size (Number Of Luma Lines)

7 R/W Reser ved 6 R/W Reser ved 5:4 R/W OSD Active Count 3 R/W OSD Active Mode 2 R/W OSD Control Mode 1 R/W Video Black

0 R/W OSD Enable 24 7:0 R/W OSD Field 1 Pointer (LSB) 25 7:0 R/W OSD Field 1 Pointer (MSB)

(Sheet 5 of 13)

2-6 Registers

26 7:0 R/W OSD Field 2 Pointer (LSB) 27 7:0 R/W OSD Field 2 Pointer (MSB)

7:5 R/W Reserved

4 R/W Pull-down Repeat (..22.. or ..33..)

3 R/W 3:2 Pull-down Enable

2 R/W 3:2 Pull-down from Bit Stream

1 R/W Freeze Field (Trick Mode)

0 R/W Freeze Frame (Trick Mode)

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Table 2.2 (Cont.) L64005 Register Map

Group Index Bit(s) R/W Status/Command/Data

629

7 R/W Reconstr uction Error Indicator (Reserved)

6 R/W Memor y Segment Allocator Reset

(Reserved) 5 R/W Pan and Scan From Bitstream 4:2 R/W Display Post-Processing Mode 1 R/W Hor izontal Filter Select 0 R/W Hor izontal Filter Enable

7:0 R/W Raster Mapper Increment (Horizontal Filter

Scale)

31 7:4 R/W VCode Delay

3 R Odd Field First 2 R Last Active Field 1 R Bottom/Top Field Indicator 0 R Even/Odd Field Indicator

32 7:0 R/W Video PES Buffer Start Address (LSB) 33 4:0 R/W Video PES Buffer Start Address (MSB) 34 7:0 R/W Video PES Buffer End Address (LSB) 35 4:0 R/W Video PES Buffer End Address (MSB)

36 7:0 R/W Audio PES Buffer Start Address (LSB) 37 4:0 R/W Audio PES Buffer Start Address (MSB)

38 7:0 R/W Audio PES Buffer End Address (LSB) 39 4:0 R/W Audio PES Buffer End Address (MSB)

40 7:0 R/W Video Channel Buffer Start Address (LSB) 41 4:0 R/W Video Channel Buffer Start Address (MSB) 42 7:0 R/W Video Channel Buffer End Address (LSB) 43 4:0 R/W Video Channel Buffer End Address (MSB)

44 7:0 R/W Audio Channel Buffer Start Address (LSB) 45 4:0 R/W Audio Channel Buffer Start Address (MSB)

L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-7

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Table 2.2 (Cont.) L64005 Register Map

Group Index Bit(s) R/W Status/Command/Data

6 46 7:0 R/W Audio Channel Buffer End Address (LSB)

47 4:0 R/W Audio Channel Buffer End Address (MSB) 48 7 R/W Reserved

6 R/W Audio LRCLK Polarity 5:4 R/W Audio PCM Mode Select 3 R/W Audio I2S Output Mode 2 R/W Audio Soft Mute 1 R/W Mute On Audio Error 0 R/W Exter nal Audio Clock

49 7:0 R/W NCO Denominator Value (LSB) 50 7:0 R/W NCO Numerator Value (LSB) 51 7:6 R/W Reserved

5:4 R/W NCO Numerator Value (MSB) 3:0 R/W NCO Denominator Value (MSB)

(Sheet 7 of 13)

2-8 Registers

52 7:6 R Audio Emphasis

5 R Audio Original/Home 4 R Audio Copyright 3:2 R Audio Channel Mode 1:0 R Audio Sample Frequency

53 7 R Audio Rate ID

6 R Audio Private Data 5:4 R Audio Layer ID 3:0 R Audio Bit Rate

Page 59

Table 2.2 (Cont.) L64005 Register Map

Group Index Bit(s) R/W Status/Command/Data

6 54 7 Reser ved

6 R Audio Synchronized and Parameters Valid 5 R/W Audio Sync Byte Aligned 4:3 R/W Audio Dual/Mono Channel 2 R Audio Decode Status

W Audio Start/Stop (Resync)

1:0 R Audio Skip and Repeat Status

W Audio Skip and Repeat Mode 55 7:0 Reserved 56 7:0 Reserved 57 7:0 Reserved 58 7:0 Reserved 59 7:0 Reserved 60 7:0 Reserved 61 7:0 Reserved 62 7:0 Reserved 63 7:0 Reserved

(Sheet 8 of 13)

L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-9

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Table 2.2 (Cont.) L64005 Register Map

Group Index Bit(s) R/W Status/Command/Data

7 0 7:0 R Auxiliary Data FIFO

1 7:6 W Refresh Extend

5 Reser ved 4:3 R/W DRAM Interface Select 2 R DRAM Write Ready

W DRAM Write Strobe

1 R DRAM Read Ready

W DRAM Read Strobe

0 R DRAM Addr Auto-increment Status

W DRAM Addr Auto-increment Enable 2 7:0 R/W DRAM Address [7:0] 3 7:0 R/W DRAM Address [15:8] 4 7:2 Reserved (Must be set to zero on writes.)

1:0 R/W DRAM Address [17:16]

(Sheet 9 of 13)

2-10 Registers

5 7:0 R/W DRAM Data [7:0] 6 7:0 R/W DRAM Data [15:8] 7 7:0 R/W DRAM Data [23:16]

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Table 2.2 (Cont.) L64005 Register Map

Group Index Bit(s) R/W Status/Command/Data

7 8 7:0 R/W DRAM Data [31:24]

9 7:0 R/W DRAM Data [39:32] 10 7:0 R/W DRAM Data [47:40] 11 7:0 R/W DRAM Data [55:48] 12 7:0 R/W DRAM Data [63:56] 13 7:0 R/W Horizontal Sync Width 14 7:0 R/W Equalization Pulse Width 15 7:0 R/W Serration Pulse Width (LSB) 16 7:0 R/W Horizontal Blank Pulse Width (LSB) 17 7:0 R/W Active Image Done (LSB) 18 7:0 R/W Half Line Time (LSB) 19 7 Reserved

6:5 R/W Half Line Time (MSB) 4:3 R/W Active Image Done (MSB) 2 R/W Hor izontal Blank Pulse Width (MSB) 1:0 R/W Serration Pulse Width (MSB)

20 7:5 R/W Pre-equalization Lines

4:0 R/W Pre-blank Lines

21 7:5 R/W Post-equalization Lines

4:0 R/W Post-blank Lines

22 7:5 R/W Serration Lines

4:0 R/W Main Lines [7:3] 23 7:0 R/W Scan Halﬂines [8:1] 24 7 R/W Main Lines [8]

6:0 R/W Main Reads Per Line

(Sheet 10 of 13)

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Table 2.2 (Cont.) L64005 Register Map

Group Index Bit(s) R/W Status/Command/Data

7 25 7 R/W Scan Halﬂines [9]

6:0 R/W Display Width 26 7 Reserved

6 R/W Line Double

5:3 R/W Pan and Scan Byte Origin

2:0 R/W Pan and Scan 1/8 Pixel Origin 27 7:2 R/W Number of segments in RMM

1 R/W Reser ved

0 R/W Reduced Memor y Mode 28 7:0 R/W Horizontal word (8 byte) origin applies to

Luma and Chroma

29 7:0 Reserved 30 7:0 Reserved 31 7 R/W VS Input Type

6 R/W CrCb 2’s Complement

5 R/W Cr Component First

4 R/W Blank Active Low

3 R/W Sync Active Low

2 R/W Composite Sync Mode

1 R/W Display Master Mode

0 R/W CCIR 601 Mode 32 7:0 R Video System Write Address (LSB) 33 7:0 R Audio System Write Address (LSB)

34 7:0 R Video Channel Buffer Write Address (LSB) 35 7:0 R Audio Channel Buffer Write Address (LSB) 36 7:0 R Video Channel Buffer Read Address (LSB)

(Sheet 11 of 13)

2-12 Registers

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Table 2.2 (Cont.) L64005 Register Map

Group Index Bit(s) R/W Status/Command/Data

7 37 7:0 R Audio Channel Buffer Read Address (LSB)

38 7:0 R Index Registers 32-37 (NSB) 39 5:0 R Index Registers 32-37 (MSB) 40 7:0 R Picture Start Code Read Address (LSB) 41 7:0 R Picture Start Code Read Address (NSB) 42 7:6 Reserved

5:0 R Picture Start Code Read Address (MSB) 43 7:0 Reserved 44 7:0 R Audio Sync Code Read Address (LSB) 45 7:0 R Audio Sync Code Read Address (NSB) 46 7:6 Reserved

5:0 R Audio Sync Code Read Address (MSB) 47 7:0 Reserved 48 7:0 R/W DRAM Source Address (7:0)

49 7:0 R/W DRAM Source Address (15:8) 50 7:2 Reserved

1:0 R/W DRAM Source Address (17:16) 51 7:0 R/W DRAM Transfer Count (7:0) 52 7:0 R/W DRAM Transfer Count (15:8) 53 7:3 Reserved

2 W Flush DRAM FIFO

1:0 R/W DRAM Transfer Mode 54 7:0 R Revision ID

(Sheet 12 of 13)

L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-13

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Table 2.2 (Cont.) L64005 Register Map

Group Index Bit(s) R/W Status/Command/Data

7 55 7 R/W CMODE

6:5 R Display Frame Store 4:3 R Decode Frame Store 2 R Video Repeat Frame Status

W Video Repeat Frame Enable

1:0 R Video Skip Frame Status

W Video Skip Frame Control 56 7:0 R/W SCR Value (LSB) 57 7:0 R/W SCR Value (MSB) 58 7:0 R/W SCR Compare Value (LSB) 59 7:0 R/W SCR Compare Value (MSB) 60 7:0 R Reserved 61 7:0 R Reserved 62 7:0 R Reserved

(Sheet 13 of 13)

1. In 64-byte resolution, unused most signiﬁcant bits are reserved.

2. Sampled at vertical sync.

3. In 32-byte resolution.

4. In 256-byte resolution, unused most signiﬁcant bits are reserved.

5. 8-byte resolution

2.1.1 Writing a Single Register

2.1.1.1 Groups 0, 1, 2, 3, 4, 5

Register Groups 0 through 5 only have one register in each group. To read or write these registers, write the group number to the user interface address bits A[2:0]. Access to these groups does not auto-increment the address register.

2-14 Registers

63 7:0 R Reserved

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2.1.1.2 Groups 6, 7

Register Groups 6 and 7 have multiple registers in each group. To read or write each register, ﬁrst set the Group 0 Address Indirection Register to the register number within the group, then write the group number to the user interface address bits A[2:0]. After each access to these groups, the Address Indirection Register auto-increments if the auto-increment bit is set.

2.1.2 Reading or Writing Multiple Registers in a Group

2.2 Group 0 Address Indirection Register

Figure 2.1 Address Indirection Register

Register Groups 6 and 7 have more than one register in each group. Each register can be accessed sequentially. To perform a sequential access, ﬁrst initialize the address indirection register, then access the appropriate group multiple times. Each time the group is accessed, the address pointer is automatically incremented, allowing the user to step through all the registers in sequence from an arbitrary start point. Accessing addresses outside the range of addresses within the group is not deﬁned.

The Address Indirection Register is a read/write auto-incrementing register, used as an index to registers within other groups. Writing to the register sets its value. Reading the register returns its current value. The register may optionally be conﬁgured to operate in an auto-increment or auto-decrement mode.

7654 0

AD AI CI

AD Auto Decrement 7, R/W

Accessing any register in Groups 6 and 7 causes the CI to automatically decrement if the Auto Decrement bit is set. CI will not automatically decrement if the AD bit is not set.

AI Auto Increment 6, R/W

Accessing any register in Groups 6 and 7 causes the CI to automatically increment if the Auto Increment bit is set. CI will not automatically increment if the AI bit is not set.

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CI Current Index [5:0], R/W

CI is a six-bit writable auto-incrementing register ﬁeld used as an index to registers within other groups. Writing CI sets its value, while reading CI returns its current value.

2.3 Group 1 Status 0 Register

Figure 2.2 Status 0 Register

The Status 0 Register contains various control and status bits that are used in the decoder.

76 5 4 210

CS VR AR AUXID[2:0] ADFS Read

CS R ASEN AUDIOID[4:0] Write

The following paragraphs describe the function of bits [7:0] during a read only.

CS Channel Status 7, R

When set, CS indicates that the channel buffer is running and storing data.

VR Video Channel Ready 6, R

When set, VR duplicates the function of the VREQ signal to allow for polled transfers without using the VREQ signal handshake. Note that VR and VREQ both assert and deassert at the same time.

AR Audio Channel Ready 5, R

2-16 Registers

When set, AR duplicates the function of the AREQ signal to allow for polled transfers without using the AREQ signal handshake. Note that AR and AREQ both assert and deassert at the same time.

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AUXID[2:0] Aux Data Layer ID [4:2], R

AUID[2:0] indicates which MPEG layer produced the data found at the top of the Auxiliary Data FIFO. The table below shows the MPEG layer that corresponds to each value in AUXID[4:2].

AUXID[2:0] MPEG Layer

000 001 010 011 100 101 110 111

2 2 2 2 2 2 2 2

Sequence Layer Group of Pictures Layer Picture Layer (Not Deﬁned) (Not Deﬁned) (Not Deﬁned) (Not Deﬁned) Extension Layer

ADFS[1:0] Auxiliary Data FIFO Status [1:0], R

ADFS[1:0] indicates the status of the Auxiliary Data FIFO as shown in the table below.

ADFS[1:0] Auxiliary Data FIFO Status

00 01 10

2 2 2

Empty Data can be read Full (additional writes will

cause FIFO to overrun) Overrun

Note that once the FIFO has overrun, the status bits stay at 112 until the register is read. The L64005 will then mark the FIFO as full until a subsequent read clears the full condition or the FIFO is once again overrun.

The following paragraphs describe the function of bits [7:0] during a write only.

CS Channel Star t/Reset 7, W

Setting CS causes the L64005 to allow data into the channel buffers. Clearing CS causes the L64005 to reset the channel buffers and not allow data to enter the buffers.

R Reserved 6, W

This bit is reserved.

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ASEN Audio Stream Select Enable 5, W

Setting ASEN causes the decoder to check the ID of the audio stream before decoding it. Clearing ASEN causes the decoder to decode all audio streams.

AUDIOID[4:0] Audio ID [4:0], W

AUDIOID[4:0] is used to select the stream ID of the audio stream to be decoded when ASEN is set.

2.4 Group 2 Status 1 Register

Figure 2.3 Status 1 Register

The Status 1 Register contains various control and status bits used in the decoder.

76543210

R UDID UDFS Read

R RE VSS VIDEOID Write

The following paragraphs describe the function of bits [3:0] during a read only.

R Reserved [7:4], R

These bits are reserved.

UDID[1:0] User Data Layer ID [3:2], R

The value contained in UDID[1:0] indicates the MPEG Layer ID of the byte at the top of the User Data FIFO as shown in the following table. Refer to subsection entitled “User Data Buffer” in Chapter 4 for more information.

UDID[1:0] MPEG Layer ID

00 01 10 11

2 2 2 2

Video Sequence Group of Picture Picture Slice

UDFS[1:0] User Data FIFO Status [1:0], R

2-18 Registers

The value contained in UDFS[1:0] indicates the status of the user data FIFO as shown in the following table:

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UDFS[1:0] User Data FIFO Status

00 01 10

2 2 2

Empty Data is ready Full (additional writes will

cause FIFO to overrun) Overrun

The following paragraphs describe the function of bits [5:0] during a write only.

R Reserved [7:6], W

These bits are reserved.

RE Reset Channel and PES Buffer on Error 5, W

Setting RE causes the decoder to reset the channel buffers and the PES buffer if the system parser detects an error in the system stream. If RE is cleared, the decoder will not reset the buffers on error.

VSS Video Stream Select Enable 4, W

Setting VSS causes the decoder to check the ID of the video stream before decoding it. Clearing VSS causes the decoder to decode all video streams.

2.5 Group 3 Interrupt Register 0

VIDEOID Video Stream ID [3:0], W

VIDEOID is used to select the stream ID of the audio stream to be decoded when VSS is set.

The Group 3 Interrupt Register 0 contains a number of interrupt status bits and masks. Reading the register clears all pending interrupts in this register. Clearing these bits enables the corresponding interrupt; setting these bits disables the corresponding interrupts. An interrupt is only generated if there are no pending interrupts for that bit. After an interrupt is generated, each subsequent interrupt event related to that bit is ignored until the initial interrupt is cleared. All bits in this register are read/write.

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Figure 2.4 Group 3 Interrupt Register 0

7 6 5 43210

DRAMXFER PDR SCRS PSD ASD DER UFR DES

DRAMXFER DRAM Transfer Done 7, R/W

When DRAMXFER is set, it indicates that the DRAM block move or the DRAM DMA transfer is complete.

PDR Pack Data Ready 6, R/W

When PDR is set, it indicates that the system parser has stored a Pack Header in the system channel buffer.

SCRS System Clock Reference Status 5, R/W

When SCRS is set, it indicates that the on-chip System Clock Reference counter has wrapped around or the SCR counter matches the compare register. Read the Status Register in Group 6 to determine the status.

PSD Picture Start Code Detect 4, R/W

When PSD is set, it indicates that the video parser has detected a picture start code.

ASD Audio Sync Code Detect 3, R/W

When ASD is set, it indicates that the audio decoder has detected an audio sync code.

DER Decode Error 2, R/W

2-20 Registers

When DER is set, it indicates that the audio or video decoder has detected a decode error. The L64005 sets DER when any one of the error status bits in Group 6, Register 1 is set. The following table lists these bits and the corresponding error conditions.

Group 6, Error Status Bits Decode Error Condition

ARE Audio Reconstruction Error ASE Audio Sync Error ACE Audio CRC or Illegal Bit Error VRE Video Reconstruction Error CE Context Error (video) VLCE Variable Length Code or

Run-length Error (video)

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See Section 2.8.2, “Group 6 Error Status Register,” for more information.

DFR Data FIFO Ready 1, R/W

When DFR is set, it indicates that there is data in the user data FIFO or the auxiliary data FIFO. Read the user data FIFO status or the auxiliary data FIFO status to determine the state.

DES Decode Status 0, R/W

When DES is set, it indicates the video decoder is running. When DES is clear, it indicates that the decoder has stopped. Setting DES starts the decoder. Clearing DES stops the decoder.

2.6 Group 4 Interrupt Register 1

Figure 2.5 Group 4 Interrupt Register 1

The Group 4 Interrupt Register 1 contains a number of interrupt status bits and masks. Reading the register clears all pending interrupts in this register. Clearing these bits enables the corresponding interrupts; setting these bits disables the corresponding interrupts. All bits in this register are read/write.

7 6 5 43210

VPR APR BVB BAV VCU ACU VCO ACO

VPR Video PES Data Ready 7, R/W

When set, VPR indicates that the system parser has just written a PES header into the video system buffer.

APR Audio PES Data Ready 6, R/W

When set, APR indicates that the system parser has just written a PES header into the audio system buffer.

BVB Begin Vertical Blank 5, R/W

When set, BVB indicates that the vertical blanking interval has begun. If enabled, this interrupt occurs once per ﬁeld.

BAV Begin Active Video 4, R/W

When set, BAV indicates that the active video portion of a ﬁeld is being displayed. If enabled, this interrupt occurs once per ﬁeld.

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VCU Video Channel Buffer Underﬂow 3, R/W

When set, VCU indicates that the video channel buffer has underﬂowed. This is usually an error, and may result in failure of the decoder to reconstruct the video picture in time for it to be displayed.

ACU Audio Channel Buffer Underﬂow 2, R/W

When set, ACU indicates that the audio channel buffer has underﬂowed. This is usually an error, and may result in failure of the decoder to reconstruct the audio samples in time for them to be presented.

VCO Video Channel Buffer Overﬂow 1, R/W

When set, VCBO indicates that the video channel buffer has overﬂowed. This is an error, and it indicates that data is being lost.

ACO Audio Channel Buffer Overﬂow 0, R/W

When set, ACBO indicates that the audio channel buffer has overﬂowed. This is an error, and it indicates that data is being lost.

2.7 Group 5 Control Register

Figure 2.6 Group 5 Control Register

The Group 5 Control Register controls several miscellaneous modes of the system parser.

76543 210

RWI EPS SSEL[1:0] RVSB RASB RAF RUF

RWI Refresh When Idle 7, R/W

When set, RWI increases the number of refresh cycles performed in the DRAM. This bit is normally clear. Set RWI to refresh DRAM more often.

EPS Enable Parallel Stream 6, R/W

When set, EPS selects the parallel input as the source for the MPEG stream. When clear, EPS selects the serial input.

2-22 Registers

Page 73

SSEL[1:0] Stream Select [5:4], R/W

SSEL[1:0] sets the input bitstream format as shown in the following table.

SSEL[1:0] Bitstream Format

00 01 10 11

2 2 2 2

A/V PES packets MPEG-1 System or MPEG-2 Program stream Reserved A/V Elementary streams

RVSB Reset Video System Buffer 3, W

Set RVSB to reset the video system buffer pointers.

RASB Reset Audio System Buffer 2, W

Set RASB to reset the audio system buffer pointers.

RAF Reset Auxiliary Data FIFO 1, W

Set RAF to reset the Aux Data FIFO.

RUF Reset User Data FIFO 0, W

Set RUF to reset the User Data FIFO.

2.8 Group 6 Secondary Control Registers

2.8.1 Group 6 User Data FIFO

Table 2.3 User Data FIFO 0

These registers access secondary control functions inside the L64005. The register accessed within Group 6 is selected by writing its index into the Address Indirection Register (Group 0).

When read, the User Data FIFO Register returns the value on the top of the User Data FIFO and pops the FIFO. Reading the FIFO when empty yields an undeﬁned value. Failing to read the FIFO eventually results in loss of User Data from the 128-byte deep FIFO, but produces no other errors in the decoding process. This register is read only. Wr iting the register has no effect.

User Data FIFO 0 Register 0

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2.8.2 Group 6 Error Status Register

When read, the Error Status Register returns the error status of the decoder. This register is read only. Writing this register has no effect. Because of the limited amount of redundancy in the MPEG syntax, the actual error may be different from that ﬂagged.

7 6 54 3 210

SCRM SCRO ARE ASE ACE VRE CE VLCE Register 1

SCRM System Clock Reference Match 7, R

When set, SCRM indicates that the LSBs of the system clock reference in the match register is equal to the onchip SCR counter.

SCRO System Clock Reference Overﬂow 6, R

When set, SCRO indicates that the on-chip System Clock Reference counter has wrapped around. This interrupt can be used to extend the precision of this counter in software.

ARE Audio Reconstruction Error 5, R

If ARE is set, the audio decoder is unable to reconstruct the output samples in the time available before the intended presentation time. This usually indicates that the PCM output is incorrectly programmed. When the audio decoder sets ARE, it also sets the DER bit in Group 3. Please note that usually at decode start time a reconstruction error may occur.

ASE Audio Sync Error 4, R

ACE Audio CRC or Illegal Bit Error 3, R

2-24 Registers

When ASE is set, it indicates that the audio decoder has lost sync. When the audio decoder sets ASE, it also sets the DER bit in Group 3. Please note that this error may persist for one or more audio frame times.

If the CRC check in an audio frame header has failed and ACE is set, it indicates that there is an illegal syntax in the audio header, or that this coding mode is unsupported. When the audio decoder sets ACE, it also sets the DER bit in Group 3. Please note that although the CRC error may persist for one or more audio fr ame times, this bit will only be set once per audio frame. If it is read,

Page 75

it will be cleared and will not become set again until the next audio frame containing a CRC error.

VRE Video Reconstruction Error 2, R

If VRE is set, it indicates that the video decoder has been unable to reconstruct the image in the allocated time before its intended presentation time. This error can occur if the encoder produces bitstreams that do not properly meet the macroblock bit allocation constraint in MPEG-2. When the audio decoder sets VRE, it also sets the DER bit in Group 3.

CE Context Error 1, R

When set, CE indicates that the bitstream’s syntax is illegal in the current context. When the audio decoder sets CE, it also sets the DER bit in Group 3.

VLCE Variable Length Code or Run-Length Error 0, R

When set, VLCE indicates that the L64005 has found a variable length code that is illegal in the current context, or the combined run-length in a block exceeds 64. When the audio decoder sets VLCE, it also sets the DER bit in Group 3.

2.8.3 Group 6 Forward Anchor Luma Base Address

The Forward Anchor Luma Base Address Register supplies the base address of the Forward Anchor frame luminance component. The decoder uses this address to calculate offsets into the luma frame memory for picture reconstruction. The full address value stored in Registers 2 and 3 is in 64-byte resolution. These registers are read/write.

Forward Anchor Luma Base Address (LSB) Register 2

Forward Anchor Luma Base Address (MSB) Register 3

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2.8.4 Group 6 Forward Anchor Chroma Base Address

The Forward Anchor Chroma Base Address Register supplies the base address of the Forward Anchor frame chrominance component. The decoder uses this address to calculate offsets into the chroma frame memory for picture reconstruction. The full address value stored in Registers 4 and 5 is in 64-byte resolution. These registers are read/write.

2.8.5 Group 6 Backward Anchor Luma Base Address

Forward Anchor Chroma Base Address

(LSB)

Forward Anchor Chroma Base Address

(MSB)

The Backward Anchor Luma Base Address Register supplies the base address of the backward frame luminance component. The decoder uses this address to calculate offsets into the luma frame memory for picture reconstruction. The full address value stored in Registers 6 and 7 is in 64-byte resolution. These registers are read/write.

Backward Anchor Luma Base Address (LSB) Register 6

2-26 Registers

Backward Anchor Luma Base Address (MSB) Register 7

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2.8.6 Group 6 Backward Anchor Chroma Base Address

The Backward Anchor Chroma Base Address Register supplies the base address of the Backward Anchor frame chrominance component. The decoder uses this address to calculate offsets into the chroma frame memory for picture reconstruction.The full address value stored in Registers 8 and 9 is in 64-byte resolution. These registers are read/write.

Backward Anchor Chroma Base Address (LSB) Register 8

Backward Anchor Chroma Base Address (MSB) Register 9

2.8.7 Group 6 Display Luma Base Address

2.8.8 Group 6 Display Chroma Base Address

The Display Luma Base Address Register supplies the base address of an area used by both reconstruction and display processes for luma data. The full address value stored in Registers 10 and 11 is in 64-byte resolution. These registers are read/write.

Display Luma Base Address (LSB) Register 10

Display Luma Base Address (MSB) Register 11

The Display Chroma Base Address Register supplies the base address of an area used by both reconstruction and display processes for chroma data. The full address value stored in Registers 12 and 13 is in 64-byte resolution. These registers are read/write.

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Display Chroma Base Address (LSB) Register 12

Display Chroma Base Address (MSB) Register 13

2.8.9 Group 6 VBI1 Luma Base Address

2.8.10 Group 6 VBI1 Chroma Base Address

The VBI1 Luma Base Address Register supplies the base address of the luma data output during the vertical blanking interval if the VBI2 Select bit in Register 22 is clear. The full address value stored in Registers 14 and 15 is in 64-byte resolution. These registers are read/write.

VBI1 Luma Base Address (LSB) Register 14

VBI1 Luma Base Address (MSB) Register 15

The VBI1 Chroma Base Address Register supplies the base address of the chroma data output during the vertical blanking interval if the VBI2 Select bit in Register 22 is clear. The full address value stored in Registers 16 and 17 is in 64-byte resolution. These registers are read/write.

2-28 Registers

VBI1 Chroma Base Address (LSB) Register 16

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VBI1 Chroma Base Address (MSB) Register 17

2.8.11 Group 6 VBI2 Luma Base Address

2.8.12 Group 6 VBI2 Chroma Base Address

The VBI2 Luma Base Address Register supplies the base address of the luma data output during the vertical blanking interval if the VBI2 Select Bit in Register 22 is set. The full address value stored in Registers 18 and 19 is in 64-byte resolution. These registers are read/write.

VBI2 Luma Base Address (LSB) Register 18

VBI2 Luma Base Address (MSB) Register 19

The VBI2 Chroma Base Address Registers supply the base address of the chroma data output during the vertical blanking interval if the VBI2 Select Bit is set. The full address value stored in Registers 20 and 21 is in 64-byte resolution. These registers are read/write.

VBI2 Chroma Base Address (LSB) Register 20

VBI2 Chroma Base Address (MSB) Register 21

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2.8.13 Group 6 VBI Size

7654 0

VBI2 R VBISIZE[4:0] Register 22

VBI2 VBI2 Select 7, R/W

VBI2 selects the currently active VBI area. Setting VBI2 selects the data at VBI2. Clearing VBI2 selects the data at VBI1.

R Reserved 6, 5

These bits are reserved.

VBISIZE[4:0] VBI Size [4:0], R/W

VBISIZE[4:0] contains the number of luma lines. If VBISIZE[4:0] is zero, no VBI data is output. If VBISIZE[4:0] is set to one, decrease the number of pre-blank lines by one. VBISIZE[4:0] is typically one for closed caption.

2.8.14 Group 6

OSD Control Register

7654 3 2 1 0

R OSDAC[1:0] OSDAM OSDMD VBLK OSDE Register 23

R Reserved [7:6]

OSDAC[1:0] OSD Active Count [5:4], R/W

2-30 Registers

These bits are reserved.

These bits specify whether the OSD Active output occurs two cycles prior to the pixel, at the pixel, or one cycle after the pixel containing OSD mixed data. The count starts at zero, which corresponds to two cycles prior to pixel timing, or three, which corresponds to one cycle after pixel timing. OSDAM is used to control the multiplexing of OSD into another video source.

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OSDAM OSD Active Mode 3, R/W

When set, OSDAM conﬁgures the OSDA pin for input. When cleared, OSDAM conﬁgures the OSD A pin to be an output. The OSDA pin is used to control multiplexing OSD out to another video source.

OSDMD OSD Controller Mode 2, R/W

Clearing OSDMD causes the OSD controller to disable linked list operation. Setting OSDMD enables linked list operation. Refer to Section 6.9.11, “OSD Compatibility Mode,” on page 6-33 for a more detailed description of these modes.

VBLK Video Black 1, R/W

Setting VBLK sets the entire active video region to black. This does not affect VBI and OSD regions.

OSDE On-Screen Display Enable 0, R/W

Setting OSDE displays the on-screen display overlay image. When OSDE is clear, the on-screen display is not displayed.

2.8.15 Group 6 OSD Field 1 Pointer

The OSD Field 1 Pointer Register speciﬁes the base address of the OnScreen Display Overlay data for the ﬁrst ﬁeld. For a detailed description on the use of this ﬁeld refer to Section 6.9, “On-Screen Display.” The full address stored in these registers is in 32-byte resolution. These registers are read/write.

OSD Field 1 Address (LSB) Register 24

OSD Field 1 Address (MSB) Register 25

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2.8.16 Group 6 OSD Field 2 Pointer

The OSD Field 2 Pointer Register speciﬁes the base address of the OnScreen Display Overlay data for the second ﬁeld. The full address stored in these registers is in 32-byte resolution. These register are read/write. For a detailed description on the use of this ﬁeld refer to Section 6.9, “On-Screen Display.”

OSD Field 2 Address (LSB) Register 26

OSD Field 2 Address (MSB) Register 27

2.8.17 Group 6 Display Mode 0

7 543210

R PDR PDE PDB FFLD FFRM Register 28

R Reserved [7:5], R/W

These bits are reserved.

PDR Pulldown Repeat 4, R/W

Setting PDR causes the display controller to repeat the pulldown mode of the last frame (for example, 3333... or

2222...).

PDE Pulldown Enable 3, R/W

Setting PDE enables 3:2 pulldown. This control bit is only in effect when PDB is cleared. When PDE is set, every other frame pulls down three ﬁelds: 323232... This bit must be set while the display controller is displaying the last ﬁeld of the frame during which you want to begin the pulldown, and cleared while displaying the ﬁrst ﬁeld of the frame during which you want to end the pulldown.

2-32 Registers

Page 83

PDB Pulldown from Bitstream 2, R/W

Setting PDB causes the L64005 to decode pulldown control from the MPEG-2 syntax in the bitstream. Clearing PDB allows the user to control the pulldown.

FFLD Freeze Field 1, R/W

Setting FLD freezes the current ﬁeld being displayed. See Section 6.7, “Display Trick Modes,” for details. Note: this bit should remain set for an even number of ﬁeld times.

FFRM Freeze Frame 0, R/W

Setting FFRM freezes the current frame displayed. See Section 6.7, “Display Trick Modes,” for details. Note: This bit should be set during the time in which the odd ﬁeld of the frame to be frozen is being displayed, and remain set for an even number of ﬁeld times. The decoder is automatically stopped during the time when the frame is frozen.

2.8.18 Group 6 Display Mode 1

76543210

REI MSAR PSB DMODE[2:0] HFS HFE Register 29

REI Reconstruction Error Indicator (Reserved) 7, R/W

This bit is reserved. During internal testing this bit is set if a reconstructiuon error occurs while displaying a B Picture in Reduced Memory Mode. Refer to ECN Item 5.1.

MSAR Memory Segment Allocator Reset (Reserved) 6, R/W

This bit is reserved. During internal testing, if the B Picture memory allocation unit becomes corrupted, setting this bit would reset the allocator. Refer to ECN Item 5.1

PSB Pan and Scan from Bitstream 5, R/W

Setting PSB causes the L64005 to decode the pan and scan parameter from the bitstream. Clearing PSB allows the user to set the pan and scan offsets through host software control.

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DMODE[2:0] Display Post-Processing Mode [4:2], R/W

The value that the host microprocessor writes to DMODE[2:0] depends on characteristics of the source image. These bits cause the display controller to select the post-processing mode indicated in the following tab le . See Section 6.1, “Video Output Format,” for information about the post-processing modes.

DMODE[2:0] Mode

000 001 010 011 100 101 110 111

2 2 2 2 2 2 2 2

Progressive Line Repeat Progressive Filter Luma (Reserved) Progressive Filter Chroma (Reserved) (Reserved) Interlace Chroma Line Repeat Interlace Chroma Line Repeat and Filter

Chroma

HFS Horizontal Filter Select 1, R/W

HFS sets the frequency response of the output ﬁlter to one of two pre-programmed values. When HFS is set, frequency response A is selected, as shown in Figure 6.3 on page 6-9. When HFS is clear, frequency response B is selected as shown in Figure 6.5. See the subsection entitled “Filter Speciﬁcation” in Chapter 6, "Video Interface and On-Screen Display", for details.

HFE Horizontal Filter Enable 0, R/W

2.8.19 Group 6 Raster Mapper Increment (Horizontal

The raster mapper in the display controller uses the value that is stored in Register 30, the Raster Mapper Increment (Horizontal Filter Scale) Register, to step the interpolator for the output pixels. Refer to the subsection entitled “Setting the Filter Raster Mapper Increment” in Chapter 6. This register is read/write.

Filter Scale)

2-34 Registers

Setting HFE enables the horizontal interpolation ﬁlter.

Raster Mapper Increment Register Register 30

Page 85

2.8.20 Group 6 Display Controller Status

The bits in Register 31 indicate the current ﬁeld status of the display controller.

7 4 3 210

VCD ODFF LAF BTF EOF Register 31

VCD VCode Delay [7:4], R/W

This ﬁeld is used to program the number of line delays from the end of Main_Lines until the VCode is set to ‘1’. This ﬁeld is normally set to 0x0 such that the VCode turns on at the star t of Post_Blank_Lines. However, if a non-zero value is programmed into this ﬁeld, there will be a delay until the VCode shows up in the SAV and EAV word. This delay is equal to VCode_Delay + I lines where I=0 in even ﬁelds and I=1 in odd ﬁelds when VCode_Delay is not equal to zero.

ODFF Odd Field First 3, R

This bit indicates whether an odd ﬁeld is coded before an even ﬁeld in the MPEG video stream. The L64005 sets ODFF either when the ﬁrst ﬁeld of a single frame is an odd ﬁeld, or when the ﬁrst ﬁeld of a three ﬁeld pulldown sequence is an odd ﬁeld. Figure 2.7 shows an example of ODFF bit setting during normal operation. This bit is initially synchronized to top=odd=ﬁrst and reﬂects whether the display controller is in the ﬁrst or last ﬁeld of a frame. When performing a pulldown, the ﬁrst two ﬁelds are considered to be the ﬁrst ﬁeld.

LAF Last Active Field 2, R

This bit may be used to determine whether the last displayed ﬁeld of a picture was an odd or an even ﬁeld. The L64005 sets LAF while displaying either the last ﬁeld of a single frame, or the last ﬁeld of a three ﬁeld pulldown sequence. Figure 2.7 shows an example of LAF bit setting during normal operation.

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Figure 2.7 LAF and ODFF Bit Fields

OEOEOEOEOEOEOEOEO

New Field

(2 ﬁeld) (2 ﬁeld)

3:2 Pulldown

Last Active Field

Odd Field First

(3 ﬁeld) (3 ﬁeld)

MD96.230

BTF Bottom/Top Field Indicator 1, R

The L64005 sets BTF at the ﬁrst horizontal sync after a vertical sync when Bottom Field data is being displayed. The L64005 clears BTF at the ﬁrst horizontal sync after a vertical sync when Top Field data is being displayed. This bit is initially synchronized to EOF (top=odd) and remains synchronized until such time that a ﬁeld inversion occurs.

EOF Even/Odd Field Indicator 0, R

2.8.21 Group 6 Video PES Buffer Start Address

The Video PES Buffer Start Address Registers supply the start address of the Video PES data buffer. For a detailed description on the use of this ﬁeld refer to Chapter 8. The address value stored in Registers 32 and 33 is in 256-byte (thirty-two 8-byte DRAM words) resolution. This register provides the upper 13 bits of the video PES buffer start address. The implied lower address bits (not shown, but required to make a full 8byte DRAM word address) are set internally to 000002. These registers are read/write.

2-36 Registers

The L64005 sets EOF at the ﬁrst horizontal sync after a vertical sync during an even ﬁeld. The L64005 clears EOF at the ﬁrst horizontal sync after a vertical sync during an odd ﬁeld. The ﬁrst picture output by the display controller will begin on an odd ﬁeld.

Page 87

Video PES Buffer Start Address (LSB) Register 32

754 0

Reserved Video PES Buffer Start Address (MSB) Register 33

2.8.22 Group 6 Video PES Buffer End Address

2.8.23 Group 6 Audio PES Buffer Start Address

The Video PES Buffer End Address Registers supply the end address of the Video PES Data buffer. For a detailed description on the use of these registers refer to Chapter 8. The address value stored in Registers 34 and 35 is in 256-byte (thirty-two 8-byte DRAM words) resolution. The implied lower address bits (not shown, but required to make a full 8-byte DRAM word address) are set internally to 111112. These registers are read/write.

Video PES Buffer End Address (LSB) Register 34

754 0

Reserved Video PES Buffer End Address (MSB) Register 35

The Audio PES Buffer Start Address Registers supply the start address of the Audio PES data buffer. For a detailed description on the use of this ﬁeld refer to Chapter 8. The address value stored in Registers 36 and 37 is in 256-byte (thirty-two 8-byte DRAM words) resolution. This register provides the upper 13 bits of the audio PES buffer start address. The implied lower address bits (not shown, but required to make a full 8byte DRAM word address) are set internally to 000002. These registers are read/write.

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Audio PES Buffer Start Address (LSB) Register 36

754 0

Reserved Audio PES Buffer Start Address (MSB) Register 37

2.8.24 Group 6 Audio PES Buffer End Address

2.8.25 Group 6 Video Channel Buffer Start Address

The Audio PES Buffer End Address Registers supply the end address of the Audio PES Data buffer. For a detailed description on the use of these registers refer to Chapter 8. The address value stored in Registers 38 and 39 is in 256-byte (thirty-two 8-byte DRAM words) resolution. These registers provide the upper 13 bits of the audio PES buffer end address. The implied lower address bits (not shown, but required to make a full 8byte DRAM word address) are set internally to 111112. These registers are read/write.

Audio PES Buffer End Address (LSB) Register 38

754 0

RESERVED Audio PES Buffer End Address (MSB) Register 39

The Video Channel Buffer Start Address Registers supply the start address of the Video Channel buffer. For a detailed description on the use of this ﬁeld refer to Chapter 8. The address value stored in Registers 40 and 41 is in 256-byte (thirty-two 8-byte DRAM words) resolution. These registers provide the upper 13 bits of the video channel buffer start address. The implied lower address bits (not shown, but required to make a full 8-byte DRAM word address) are set internally to

000002.These registers are read/write.

2-38 Registers

Page 89

Video Channel Buffer Start Address (LSB) Register 40

74 0

RESERVED Video Channel Buffer Start Address (MSB) Register 41

2.8.26 Group 6 Video Channel Buffer End Address

2.8.27 Group 6 Audio Channel Buffer Start Address

The Video Channel Buffer End Address Registers supply the end address of the Video Channel buffer. For a detailed description on the use of this ﬁeld refer to Chapter 8. The address value stored in Registers 42 and 43 is in 256-byte (thirty-two 8-byte DRAM words) resolution. These registers provide the upper 13 bits of address. The implied lower address bits (not shown, but required to make a full 8-byte DRAM word address) are set internally to 111112. These registers are read/write.

Video Channel Buffer End Address (LSB) Register 42

754 0

RESERVED Video Channel Buffer End Address (MSB) Register 43

The Audio Channel Buffer Start Address Registers supply the start address of the Audio Channel buffer. For a detailed description on the use of this ﬁeld refer to Chapter 8. The address value stored in Registers 44 and 45 is in 256-byte (thirty-two 8-byte DRAM words) resolution. These registers provide the upper 13 bits of the audio channel buffer start address. The implied lower address bits (not shown, but required to make a full 8-byte DRAM word address) are set internally to 000002. These registers are read/write.

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Audio Channel Buffer Start Address (LSB) Register 44

RESERVED Audio Channel Buffer Start Address (MSB) Register 45

2.8.28 Group 6 Audio Channel Buffer End Address

2.8.29 Group 6 Audio Mode Control

The Audio Channel Buffer End Address Registers supply the end address of the Audio Channel buffer. For a detailed description on the use of this ﬁeld refer to Chapter 8. These registers provide the upper 13 bits of the audio channel buffer end address. The address value stored in Registers 46 and 47 is in 256-byte (thirty-two 8-byte words) resolution. The lower address bits (not shown, but required to make a full 8-byte DRAM word address) are set internally to 111112. These registers are read/write.

Audio Channel Buffer End Address (LSB) Register 46

754 0

RESERVED Audio Channel Buffer End Address (MSB) Register 47

The Audio Mode Control Register sets various operational modes of the audio decoder. This register is read/write.

76543 2 1 0

R LRP PCM[1:0] I2S ASM MUTE EXCLK Register 48

R Reserved 7, R/W

2-40 Registers

This bit is reserved.

Page 91

LRP Audio LRCLK Polarity 6, R/W

Setting LRCLK reverses the polarity of the LRCLK signal. When LRP is set, LRCLK is active HIGH. When LRP is cleared, LRCLK is active LOW.

PCM[1:0] Audio PCM Mode Select [5:4], R/W

Setting PCM[1:0] selects one of three output modes for the audio PCM output as shown in the following table.

PCM[1:0] BCLK Cycles

00 01 10 11

2 2 2 2

32 48 64 Reserved

I2S Audio I2S Output Mode 3, R/W

Setting I2S conﬁgures the PCM output in the I2S output mode. Clearing I2S conﬁgures the output in normal AES mode.

ASM Audio Soft Mute 2, R/W

Setting ASM mutes the output. Clearing ASM enables the audio output. A soft mute provides a gradual muting which may be used to avoid audible artifacts that would otherwise be heard during a muting operation.

2.8.30 Group 6 Audio Oscillator Frequency Control

MUTE Mute on Audio Error 1, R/W

Setting MUTE causes the audio output to mute when an error is detected. Clearing MUTE allows audio output if certain minor errors are detected.

EXCLK External Audio Clock Select 0, R/W

Setting EXCLK causes the L64005 to use an externally supplied audio clock (ACLK) for the derivation of the audio sample rate. Clearing EXCLK causes the L64005 to use SYSCLK (normally 27 MHz).

The Audio Oscillator Frequency Control Registers control the frequency of BCLK. Refer to the subsection entitled “Setting the Output Sample Rate” on page 7-3 for details. The sample rate is given by

Audio Clock

L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-41

--------

×=

. These registers are read/write.

Page 92

NMOSC (LSB) Register 49

NOSC (LSB) Register 50

76 5 4 3 0

R NOSC (MSB) NMOSC (MSB) Register 51

NMOSC NCO Denominator Value (n-m)Register 49, Bits [7:0]

These bits contain the value for the NCO denominator (n-m). This value should be stored as a negative two’s complement number. See Table 7.1 on page 7-5 for values of n-m at different sampling frequencies.

NOSC NCO Numerator Value (n) Register 50, Bits [7:0]

R Reserved Register 51, Bits [7:6]

2.8.31 Group 6 Audio

The Audio P arameter 0 Register returns values found in the audio stream that describe the format and mode of the audio data. This register is read only.

Parameter 0

2-42 Registers

A digital numerically controlled oscillator (NCO), which acts as a n/2m divider of the select clock, controls the output sample rate of the audio decoder. These bits contain the value for the NCO numerator (n). See Table 7.1 on page 7-5 for values of n at different sampling frequencies.

These bits are reserved.

Page 93

765 4 3 2 1 0

AE[1:0] OH CF ACMODE[1:0] ASF[1:0] Register 52

AE[1:0] Audio Emphasis [7:6], R

AE[1:0] indicates the type of emphasis that the L64005 uses.

AE[1:0] Type of Emphasis

00 01 10 11

2 2 2 2

No Emphasis 50/15 Microsecond Emphasis Reserved CCITT J.17

OH Audio Original/Home 5, R

When set, this bit indicates that the bitstream contains original data. When cleared, OH indicates that the bitstream is a copy.

CF Audio Copyright Flag 4, R

When set, CF indicates that the data represents copyrighted material.

ACMODE[1:0] Audio Channel Mode [3:2], R

ACMODE[1:0] indicates the audio channel mode as shown in the table below.

ACMODE[1:0] Channel Mode

00 01 10 11

2 2 2 2

Stereo Joint stereo Dual Channel Single Channel

ASF[1:0] Audio Sample Frequency [1:0], R

ASF [1:0] indicates the audio sample frequency as shown in the following table. The RATE bit from Register 53 indi-

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cates normal frequencies if it is set and lower frequencies if it is clear.

ASF[1:0] RATE Frequency

00 01 10 11 00 01 10 11

2 2 2 2 2 2 2 2

1 44.1 KHz 1 48 KHz 1 32 KHz 1 Reserved 0 22.05 KHz 0 24 KHz 0 16 KHz 0 Reserved

2.8.32 Group 6 Audio Parameter 1

Register 53 returns values found in the audio stream which describe the format and mode of the audio data. The register is read only.

76543210

RATE PRD LID[1:0] BRI[3:0] Register 53

RATE Audio Rate ID 7, R

RATE is the Audio Rate ID bit parsed from the frame header. If RATE = 1, it speciﬁes normal sample rates. If RATE = 0, it speciﬁes low sample rates. See the description for ASF[1:0] in Register 52.

PRD Audio Private Data 6, R

PRD is parsed from the audio header. When set, it indicates that the audio header contains private data.

LID[1:0] Audio Layer ID [5:4], R

LID[1:0] is parsed from the frame header. LID[1:0] indicates the MPEG coding layer.

LID[1:0] Layer

11 10 01 00

2 2 2 2

Layer 1 Layer 2 Layer 3 Reserved

2-44 Registers

Page 95

BRI[3:0] Audio Bit Rate Index [3:0]

BRI [3:0] indicate the selected bit rate All values shown in the following table are for RATE = 1.

BRI[3:0] Layer 1 Bit Rate Layer 2 Bit Rate

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Free Format 32 32 64 48 96 56 128 64 160 80 192 96 224 112 256 128 288 160 320 192 352 224 384 256 416 320 448 384 Reserved Reserved

Free Format

1. The L64005 does not support Free Format. The L64005 will not decode Free Format input.

2.8.33 Group 6 Audio Trick Modes

76 5 43 2 1 0 R ASPV ASBA ADMC[1:0] ADS ASRS[1:0] Register 54

R Reserved 7] ASPV Audio Synchronized and Parameters Valid 6, R

When set, ASPV indicates that the audio decoder has achieved synchronization to the bitstream and that the parameters presented in Group 6, Registers 52 and 53, are valid.

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ASBA Audio Sync Byte Aligned 5, R/W

This read/write bit, when set by host software, tells the audio parser that data presented to it may be assumed to be byte aligned. When cleared, the parser will make no such assumption, and the MPEG audio sync pattern will be searched for in a bit serial fashion. Note that this bit must only be set when using the device to decode PES bitstreams, program streams, and when using any parallel modes.

ADMC[1:0] Audio Dual/Mono Channel Select [4:3]

The ADMC[1:0] bits select from which channel, left or right, the dual mono data is output from the audio decoder. Note that this is only used when the L64005 receives dual mono audio bitstreams. The def ault at reset is 002 or stereo mode.

ADMC[1:0] Audio Dual Mono Output Mode

stereo: the left channel is output on left speaker, and the right channel is output on right speaker.

left: the left channel is output on both left and right speakers

right: the right channel is output on both left and right speakers

undeﬁned

ADS Audio Decode Status and Start/Stop 2, R/W

ASRS[1:0] Audio Skip and Repeat Status [1:0]

2-46 Registers

When set, ADS indicates that the audio decoder is currently running. Setting ADS starts the decoder, and clearing ADS stops the decoder. Stopping the decoder causes the audio decoder to lose sync with the audio bitstream.

When set, ASRS[1:0] commands the audio decoder to pause or play at normal, fast or slow rates, according to the following table.

ASRS[1:0] Skip and Repeat Audio Mode

00 01 10 11

2 2 2 2

Pause Normal Play 11/12 Play Time (Fast) 13/12 Play Time (Slow)

Page 97

When the 11/12 time or 13/12 time has been played for one frame, the audio decoder resets these bits to 01

(normal) to let the user know that the frame has been completed. In these modes, the audio decoder presents 11/12 of the normal data to the output PCM ﬁlter (fast) or 13/12 of the normal data to the output PCM ﬁlter (slow) within 1 normal frame decode. Reset these bits to 002 to enable pause mode. Note that in the pause mode, the audio decoder stops parsing the bitstream and maintains all current states, so that re-asserting normal play at a later time does not cause the audio decoder to lose sync with the bitstream.

2.8.34 Group 6 Reserved Registers

2.9 Group 7 Secondary Control Registers

2.9.1 Group 7 Auxiliary Data FIFO

Registers 55 through 63 are reserved for LSI Logic use and should not be read or written.

The Group 7 Secondary Control Registers access secondary control functions inside the L64005. These registers may be accessed indirectly through the Address Indirection Register. Most of the registers need to be set only once during initialization of the decoder.

When read, Register 0 returns the value on the top of the Auxiliary Data FIFO and pops the FIFO. Reading the FIFO when empty yields an undeﬁned value. Failing to read the FIFO will eventually result in loss of data from the FIFO, but will produce no other errors in the decoding process. Writing the register has no effect.

AUXFIFO Auxiliary Data FIFO [7:0], R

This eight-bit register is used to access auxiliary data in the coded data stream. The FIFO is 128 bytes deep for revisions C and later of the device. The FIFO is 80 bytes deep in revisions A and B.

Table 2.4 shows the available parameters, their arrival order, and their size. All values are right justiﬁed within their corresponding bytes in the FIFO.

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Table 2.4 VLD Parameters Layer Name Size

Video Sequence Horizontal Size (two bytes) 12 uimsbf

Vertical Size (two bytes) 12 uimsbf Pel Aspect Ratio (one byte) 4 uimsbf Picture Rate (one byte) 4 uimsbf Bit Rate (three bytes) 18 uimsbf VBV Buffer Size (two bytes) 10 uimsbf Constrained Parameter Flag, Load Intra Quan-

3 uimsbf tizer Matrix, Load Non Intra Quantizer Matrix (one byte)

Sequence Extension

Extension Identiﬁer (one byte) 4 uimsbf Proﬁle and Level (one byte) 8 uimsbf Progressive Sequence 1 bit Chroma Format, Horizontal Size Extension,

6 uimsbf Vertical Size Extension (one byte)

Bit Rate Extension (two bytes) 12 uimsbf VBV Buffer Size Extension (one byte) 8 uimsbf Low Delay, Frame Rate Extension (one byte) 8 uimsbf

Display Extension

Extension Identiﬁer (one byte) 4 uimsbf Video Format, Color Description (one byte) 4 uimsbf If (Dolor_Description) { Color Primaries (one byte) 8 uimsbf Transfer Characteristics (one byte) 8 uimsbf Matrix Coefﬁcients (one byte) 8 uimsbf } Horizontal Dimension (two bytes) 14 uimsbf Vertical Dimension (two bytes) 14 uimsbf

Group of Pictures Time Code (four bytes) 25 bits

Closed GOP (one byte) 1 bit Broken Link (one byte) 1 bit

Picture Temporal Reference (two bytes) 10 uimsbf

Picture Coding Type (one byte) 3 uimsbf VBV Delay (two bytes) 16 uimsbf

Quant Matrix Extension

Extension Identiﬁer (one byte) 4 uimsbf

(Sheet 1 of 3)

2-48 Registers

Page 99

Table 2.4 (Cont.) VLD Parameters Layer Name Size

Pan and Scan Extension

Extension Identiﬁer (one byte) 4 uimsbf Horizontal Offset [15:2] (two bytes) 14 simsbf Horizontal Offset [1:0] (one byte) 2 uimsbf Vertical Offset [15:4] (two bytes) 12 simsbf Vertical Offset [3:0] (one byte) 4 uimsbf if (Picture_Structure = “11” &&(Progressive_Sequence = 0 ||

Repeat_First_Field = 1)) { Horizontal Offset [15:2] (two bytes) 14 simsbf Horizontal Offset [1:0] (one byte) 2 uimsbf Vertical Offset [15:4] (two bytes) 12 simsbf Vertical Offset [3:0] (one byte) 4 uimsbf if (Progressive_Sequence = 0 && Repeat_First_Field = 1 ||

(Progressive_Sequence = 1 && Top_Field_First = 1)) { Horizontal Offset [15:2] (two bytes) 14 simsbf Horizontal Offset [1:0] (one byte) 2 uimsbf Vertical Offset [15:4] (two bytes) 12 simsbf Vertical Offset [3:0] (one byte) 4 uimsbf } }

Extension Identiﬁer (one byte) 4 uimsbf Copyright Flag (one byte) 1 bit Copyright Identiﬁer (one byte) 8 uimsbf Original/Copy (one byte) 1 bit Reserved (one byte) 7 uimsbf Copy Number 1 (three bytes) 20 uimsbf Copy Number 2 (three bytes) 22 uimsbf Copy Number 3 (three bytes) 22 uimsbf

(Sheet 2 of 3)

3,4

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Table 2.4 (Cont.) VLD Parameters Layer Name Size

Picture Coding Extension

Extension Identiﬁer (one byte) 4 uimsbf Forward Horizontal f Code (one byte) 4 uimsbf Forward Ver tical f Code (one byte) 4 uimsbf Backward Horizontal f Code (one byte) 4 uimsbf Backward Vertical f Code (one byte) 4 uimsbf Intra DC Precision (one byte) 2 uimsbf Picture Structure (one byte) 2 uimsbf Top Field First (one byte) 1 bit Frame Prediction Frame DCT (one byte) 1 bit Concealment Motion Vector (one byte) 1 bit Q Scale Type (one byte) 1 bit Intra VLC Format (one byte) 1 bit Alternate Scan (one byte) 1 bit Repeat First Field (one byte) 1 bit Chroma Post Processing Type (one byte) 1 bit Progressive Frame (one byte) 1 bit Composite Display (one byte) 1 bit if (Composite_Display = 1) { V-axis, Field Sequence, Sub-Carrier (one byte) 5 uimsbf Burst Amplitude (one byte) 7 uimsbf Sub-Carrier Phase (one byte) 8 uimsbf }

(Sheet 3 of 3)

1. uimsbf = Unsigned integer, most-signiﬁcant bit ﬁrst

2. MPEG-2 only; not present in MPEG-1 stream

3. simsbf = Signed integer, most-signiﬁcant bit ﬁrst

4. To extract horizontal or vertical offset, take the speciﬁed number of bits from the ﬁrst two bytes, concatenate this value with the speciﬁed number of bits from the last byte, and treat the ﬁnal 16-bits as a “simsbf”.

2-50 Registers