This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB15-000143-01, First Edition (July 2001)
This document describes Revision 1 and Revision 2 of the LSI Logic Corporation
EB402 Evaluation Board and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.
LSI Logic Corporation reserves the right to make changes to anyproductsherein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
The LSI Logic logo design and ZSP are trademarks or registered trademarks of
LSI Logic Corporation. Solaris is a trademark of Sun Microsystems, Inc. Windows
95, Windows 98, Windows 2000, and Windows NT are registered trademarks of
Microsoft Corporation. All other brand and product names may be trademarks of
their respective companies.
GL
To receive product literature, visit us at http://www.lsilogic.com. and
http://www.zsp.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
This document is the primary reference and user’s guide for Revision 1
and Revision 2 of the EB402 Evaluation Board. Unless otherwise noted,
references to the EB402 apply to Revision 1 and Revision 2 printed
circuit boards (PCBs). LSI Logic incorporated the following changes in
Revision 2 of the EB402 Evaluation Board:
•Added + 9 VDC power to SPORT0 and SPORT1 to increase serial
port versatility.
•Added Macraigor JTAG Interface (J5 reserved on Revision 1).
•Added Diode CR1 to PCB to accommodate Macraigor JTAG Interface.
The EB402 is the evaluation board for LSI402ZX Digital Signal
Processors (DSPs). In this manual, the EB402 Evaluation Board is
referred to as the EB402.
Audience
This document assumes that you are familiar with DSPs and related
support devices. The people who benefit from this book are:
•Engineers and managers who are evaluating the LSI402ZX DSP for
possible use in a system.
•Engineers who are designing the LSI402ZX DSP into a system.
Prefaceiii
Page 4
Organization
This document has the following chapters:
•Chapter 1, Introduction, provides an overview of the EB402 and
•Chapter 2, Installation, explains how to install EB402 hardware and
•Chapter 3, Hardware Overview, describes the LSI402ZX DSP signals,
•Chapter 4, Operation, explains the EB402 operating modes.
•Chapter 5, Board Layout and Jumper Settings, shows the physical
•Appendix A, Schematics, contains the schematics for the EB402
•Appendix B, Bill of Materials, lists the materials used in the EB402
Related Publications
describes its features.
verify its functionality with an RS-232-based or a JTAG-basedemulator.
the EB402 external interfaces, and the on-board memory configuration.
layout of the EB402, lists jumpers and their default settings, and
provides the pinouts for the PCB interface connectors.
and the BD-EBM-CODEC-1 Codec Daughterboard.
and the BD-EBM-CODEC-1 Codec Daughterboard.
The following documents provide supplemental information:
LSI402ZX Digital Signal Processor User’s Guide, LSI Logic Corporation,
Order No. R14021.B.
ZSP Digital Signal Processor Architecture Technical Manual, LSI Logic
Corporation, Order No. l14036.A.
EB402 Evaluation Board Getting Started, LSI Logic Corporation, Order
5.9J8, EEI Control Connector5-11
A.1EB402 Schematics (Sheet 1 of 6)A-2
A.2EB402 Schematics (Sheet 2 of 6)A-3
A.3EB402 Schematics (Sheet 3 of 6)A-4
A.4EB402 Schematics (Sheet 4 of 6)A-5
A.5EB402 Schematics (Sheet 5 of 6)A-6
A.6EB402 Schematics (Sheet 6 of 6)A-7
A.7BD-EBM-CODEC-1 Schematic Sheet 1 of 1A-8
Tables
3.1PLL Multiplier Selections3-4
3.2LSI402ZX External Interrupt Signal Use3-6
3.3PIO Signal Use3-8
3.4BD-EBM-CODEC-1 Audio Connectors3-16
3.5BD-EBM-CODEC-1 Jumper Settings and Descriptions3-18
Contentsix
Page 10
3.6Memory Chip Select3-24
5.1Evaluation Board Jumper Settings and Descriptions5-3
5.2Connector Summary5-5
B.1EB402 Bill of MaterialsB-1
B.2BD-EBM-CODEC Bill of MaterialsB-5
xContents
Page 11
Chapter 1
Introduction
The EB402 is the evaluation board for the LSI Logic Corporation
LSI402ZX Digital Signal Processor (DSP) device. The EB402 provides a
hardware platform for evaluating the device and a software platform for
developing, debugging, and demonstrating real-time applications for the
LSI402ZX DSP. The EB402 also provides a reference design for
hardware designers, and a flexible full-featured emulation platform for
DSP software designers.
This chapter includes the following sections:
•Section 1.1, “Product Features”
•Section 1.2, “Operating Modes”
•Section 1.3, “Block Diagram”
•Section 1.4, “Packing List”
•Section 1.5, “Related Components”
1.1Product Features
The EB402 provides the following features:
•RS-232 and JTAG interfaces for emulation, download, and debug.
•Full-speed execution of DSP programs.
•Full visibility and control of device memory and registers.
•Boot execution from nonvolatile flash memory for stand-alone test
and demonstration.
•On-board flash memory, SBSRAM, and SRAM for external
instruction and data memory.
EB402 Evaluation Board User’s Guide1-1
Page 12
•External Expansion Interface (EEI) for connecting additional external
memory and peripherals.
•Two serial port interfaces for flexible peripheral configurations.
•Codec Daughterboard(s) that supports up to eight channels of
real-time analog audio I/O.
•Host Processor Interface (HPI) for connecting the EB402 to a host
microprocessor.
1.2Operating Modes
The EB402 has three operating modes:
•JTAG-Based Emulation
•RS-232-Based Emulation
•Stand-Alone Mode
The development and debug capabilities of JTAG- and RS-232-based
emulators are similar. Both modes provide access to all on-chip
resources. The device emulation unit (DEU) works in conjunction with
code residing in the boot ROM to provide full-speed in-circuit emulation,
and to allow full visibility and control of the device’s memory and registers.
The major differences between JTAG- and RS-232-based emulation are
communication speed, RS-232 stack requirements, and hardware debug
capabilities. JTAG-based emulation offers access to hardware debug
capabilities that are not available with RS-232-based emulation. Refer to
the ZSP™ SDK Software Development Kit User’s Guide for more
information about hardware debug capabilities.
1.2.1 JTAG Mode
The EB402 supports JTAG controllers from these manufacturers:
•Corelis JTAG Controller
•Macraigor Raven Controller
Check the ZSP web site (http://www.zsp.com) for the latest information
about compatible JTAG controllers and software.
1-2Introduction
Page 13
1.2.1.1 Corelis JTAG Controller
JTAG-based emulation requires an IBM-compatible PC, a Corelis JTAG
controller (PCI or PCMCIA) installed on the PC, a JTAG cable connecting
the PC to the EB402, and the LSI Logic Corporation SDK Software
Development Kit. SDK provides a compiler, assembler, linker, debugger,
and other utilities required to create, simulate, debug and execute
LSI402ZX programs on the EB402.
1.2.1.2 Macraigor Raven JTAG Controller
JTAG-based emulation requires an IBM-compatible PC with a parallel
port, a JTAG cable between the parallel port and connector J5 on the
EB402, and the Green Hills Software ZSP development tools. These
software tools provide a compiler, assembler, linker, debugger, and other
utilities required to create, simulate, debug and execute LSI402ZX
programs on the EB402. The Macraigor Raven JTAG controller provides
a hardware reset from the user interface.
1.2.2 RS-232 Mode
RS-232 mode works with IBM-compatible PCs, and workstations running
Solaris 2.5 and later versions. Using either type of system requires an
RS-232 cable and the ZSP SDK Software Development Kit. An RS-232
cable is included with the EB402 package.
SDK provides GUI and command line interfaces for IBM-compatible PC
systems; a command line interface is provided for Solaris. Check the
ZSP web site (http://www.zsp.com) for the latest information about
compatible computers, operating systems, and development software.
RS-232-based emulation does not support modifying the %smode control
register. Consequently, the emulator can access internal memory, but not
external memory.
Note:SDK 2.1 and earlier versions do not support the LSI402ZX.
1.2.3 Stand-Alone Mode
In stand-alone mode, the EB402 executes code from on-board memory
without a host computer attached to the evaluation board. This mode can
demonstrate the Evaluation Board. For example, you can write a
Operating Modes1-3
Page 14
stand-alone application and run it on the EB402, or use the
demonstration code that is included in the flash ROM. The flash ROM is
preprogrammed with code that supports serial port debug and
illuminates LEDs that indicate a successful self-test.
1.3Block Diagram
A simplified block diagram of the EB402 is shown in Figure 1.1.
Figure 1.1EB402 Block Diagram
JTAG I/F
HP I/F
Serial Port
Daughter Card I/F
(Codec Installed)
Serial Port
Daughter Card I/F
INT4
UART
JTAG
HPI
INT2
Serial Port 0
PIO[1:0]
INT3
Serial Port 1
PIO[3:2]
INT4
Flash RAM
512 K x 16
LSI402ZX
HOLD/HOLDA
XBUS
SRAM
256 K x 16
CLKIN
PLL
RSTN
PIO[6:4]
INT[1:0]
Access Control
SB-SRAM
128 K x 32
Clock
Support
Reset
Logic
16-Bit
External Expansion I/F
LED
Display
RS-232C
1-4Introduction
Off-Board I/F
On-Board Memory
Logic
Page 15
1.4Packing List
The EB402 package includes the following components:
•EB402 PCB.
•BD-EBM-CODEC-1 Codec Daughterboard installed on EB402 PCB.
•Power Supply (input; 120 V or 240 V AC 50/60Hz; output: 9 V DC,
2.5 A) with separate AC power cable.
•RS-232 serial cable (9-pin) for RS-232-based emulation.
•This user’s guide, Document DB15-000143-01.
•EB402 Evaluation Board Getting Started.
Confirm that these items are included with your EB402. If any items are
missing, contact LSI Logic Corporation or your LSI Logic manufacturer’s
representative.
1.5Related Components
Although the following items are not part of the EB402 package, you may
need these items to use with the EB402.
•ZSP400 Software Development Kit (SDK), SW-ZSP400SDK.
LSI Logic USA distribution contacts: Arrow, Avnet, or Insight.
•Green Hills Software MULTI 2000 Integrated Development
Environment. E-mail contact: sales@ghs.com.
•Corelis PCI JTAG Emulator, BD-PCI1149. LSI Logic USA distribution
contacts: Arrow, Avnet, or Insight.
•Corelis PCMCIA JTAG Emulator, BD-PCMCIA1149. LSI Logic USA
distribution contacts: Arrow, Avnet, or Insight.
•Macraigor Systems RAVEN Parallel Port JTAG Interface. Contact:
http://www.macraigor.com.
Packing List1-5
Page 16
The following software components are available on the ZSP web site
(http://www.zsp.com):
•Example code
•Utility software
LSI Logic international distributors are listed in the back of this user’s guide.
1-6Introduction
Page 17
Chapter 2
Installation
This chapter explains how to install the EB402 and verify that it is
functioning correctly. It includes the following sections:
•Section 2.1, “Board Layout”
•Section 2.2, “Preparing to Install the Evaluation Board”
•Section 2.3, “Installing the Evaluation Board”
•Section 2.4, “Power-Up Sequence”
2.1Board Layout
Figure 2.1 is a simplified drawing of the EB402 PCB. It shows the
location of the components that are referenced in this section.
Prepare to install the EB402 by following this procedure:
1.Using appropriate antistatic measures to prevent electrostatic
discharge (ESD) damage, unpack the PCB and the other components.
2.Verify that you have received all the components. Refer to
Section 1.4, “PackingList” on page 1-5, for the contents of the EB402
package. Inspect the components to verify that none are damaged.
If any components are missing or damaged, contact LSI Logic
Corporation or your LSI Logic manufacturer’s representative.
2-2Installation
Page 19
3.Place the PCB on a flat, dry surface. Like most electronic devices,
the Evaluation Board should be kept away from strong heat and
electromagnetic interference sources, including electric heaters.
4.Familiarize yourself with the PCB. You need to identify and
manipulate connectors, controls, indicators, and jumpers during the
installation. Figure 2.1 shows the board’s components. Refer to
Chapter 5, Board Layout and Jumper Settings, for additional
information on this subject.
2.3Installing the Evaluation Board
Refer to the silk screen on the PCB for the location of components
referenced in this section. Refer to Table 5.1 on page 5-3 for additional
information about setting jumpers. To configure and install the EB402,
perform the following tasks:
1.Set the PCBs power switch, S3, to the OFF position.
2.Connect the input of the AC power supply to an AC power outlet. The
EB402 power supply is compatible with 120 V or 60 Hz and
240 V or 50 Hz sources.
3.Connect the power supply’s DC output to the EB402 power jack, J9.
4.Select either RS-232- or JTAG-based emulation. You may not use
both emulation modes simultaneously.
For RS-232-based emulation, use the RS-232 cable supplied with
the EB402 to connect the host PC’s RS-232 port to the DB-9
connector, J10, on the PCB.
For JTAG-based emulation, use a JTAG cable to connect the JTAG
interface on the host PC to the JTAG connector, J7 (Corelis) or
J5 (Macraigor), on the PCB.
Installing the Evaluation Board2-3
Page 20
5.Select the boot device. You may boot from either the on-board
external memory or the on-chip internal memory.
To boot from on-board external memory, install the IBOOT jumper,
JP3. Also, verify that the XBOOT jumper, JP18, is installed. The
position of JP18 determines whether flash memory or asynchronous
SRAM is the boot memory. To select SRAM, use a jumper to connect
pins 2–3 of JP18. To select flash memory, use a jumper to connect
pins 1–2 of JP18.
To boot from the LSI402ZX on-chip boot ROM, remove the jumper
at JP3.
6.Verify that the HALT jumper, JP4, is not installed. Installing JP4
causes the DSP to halt.
7.Verify that the GTN jumper, JP2, is not installed. Installing JP2
disables the LSI402ZX I/O drivers.
8.Select the reference clock. You can choose either the on-board
oscillator or an external clock source.
To select the on-board 10 MHz oscillator for the LSI402ZX reference
clock, use a jumper to connect pins 1–2 of JP1.
To select an external clock for the LSI402ZX reference clock, use a
jumper to connect pins 2–3 of JP1. Connect the external clock to
BNC connector J4.
9.Select the processor clock. You can select either the DSP PLL, or
CLKIN for the processor clock.
To select the output of the LSI402ZX PLL for the processor clock,
install the BYP jumper, JP12.
To bypass the PLL and select CLKIN for the processor clock,
remove JP12.
2-4Installation
Page 21
2.4Power-Up Sequence
1.Set the power switch, S3, to the ON position.
2.Verify that the two surface mounted LEDs illuminate. LED1 is
connected to the 3.3 V regulator, VR1. LED2 is connected to the
1.8 V regulator, VR2. Illumination only indicates that the regulators
are producing an output voltage, not necessarily the specified voltage.
3.Measure the output voltage of VR1 at TP8. The specified output
voltage is 3.3 V, +/- 5%. The voltage is normally within specification.
If necessary, adjust the voltage with 25-turn potentiometer R11.
4.Measure the output of voltage regulator VR2 at TP5. The specified
output voltage is 1.8 V, +/- 5%. The voltage is normally within
specification. If necessary, adjust the voltage with 25-turn
potentiometer R12.
5.Verify that the self-test diagnostic completes successfully.The EB402
runs a self-test diagnostic when it boots from its internal ROM. The
LSI402ZX illuminates LED3 when the test starts and extinguishes
LED3 when the self-test completes successfully. If LED3 remains
illuminated at the end of the self-test, the test failed. Refer to
LSI402ZX Digital Signal Processor User’s Guide and Section 4.1,
“Boot Modes,” page 4-1, for more information about self-test.
6.If the self-test fails, momentarily press the reset switch, S1, to reset
the board.
Power-Up Sequence2-5
Page 22
2-6Installation
Page 23
Chapter 3
Hardware Overview
This chapter is an overview of the EB402 hardware. It describes
LSI402ZX clock and control signals, programmable I/O signals, external
interfaces, the codec daughterboard, and memory.
Only a few LSI402ZX signals are described in this chapter. Each of these
signals has a jumper, switch, or external connection that a user must
manipulate to configure the Evaluation Board. These configuration options
are explained in the following sections. For a complete listing of EB402
jumper settings, refer to Table 5.1. For a comprehensive description of all
DSP signals, refer to LSI402ZX Digital Signal Processor User’s Guide.
The chapter includes the following sections:
•Section 3.1, “Clock and Control Signals”
•Section 3.2, “PIO[7:0] (Programmable I/Os)”
•Section 3.3, “External Interfaces”
•Section 3.4, “Memory and Memory-Mapped Peripherals”
Figure 3.1 is a block diagram of the EB402.
EB402 Evaluation Board User’s Guide3-1
Page 24
Figure 3.1Evaluation Board Block Diagram
Macraigor
J5
[7]
J3
2
SPORT0
BD-EBM-CODEC-1
2
SPORT1
J2
BD-EBM-CODEC-1
16
INT0
EEI
J8, J11
INT1
HOLD
HOLDA
PIO4,5,6
SYSRESETN
Connector
PIO0-6
Pull-Up/Pull-Down
Selection
PIO7
to CHIP
SELECT
CONFIG
18
32
12
16
Asynchronous
256 K x 16
JTAG
7
18
SRAM
Vcc
2
WR0N,
RDN
Corelis
Connector
JTAG
5
5
Buffer
5
JTAGCLKINRSTN
IBOOT
PIO7
PIO[6:0]
8
Serial Port 0
INT2
8
Serial Port 1
INT3
DBAB
32
17
5
Syncburst
SRAM
128 K x 32
J7
10 MHz
OSC
LSI402ZX
XBUS
[17:0][31:0]
WR0N,
WR1N,
RDN
MEMCLK,
ADSN
Control
16
Memory
512 K x 16
J4
EXT CLKIN
SYSRESETN
INT0
INT1
HPI
INT4
2
18
Flash
8 3
RDN,
WR0N
From EEI
16 Data, 4 Ctrl, 2 Flags
22
7.372 MHz
OSC
UART
3
WRN,
RDN,
PCS0N
16
LEDs
LD[16:1]
Power
Monitor
Power
Monitor
UART
4
PCS3N
RS-232
8
3.3 V
1.8 V
4
Address
Data
Control
DCS[3:0]N,
ICS[3:0]N
Switch
S1
J6
HPI Connector
RS-232
J10
Connector
Switch
S3
Power
J9
3-2Hardware Overview
VR1
VR2
Voltage Regulators
3.3 V
1.8 V
VDDIO33
PLLVDD
Chip Select
Configuration
Page 25
3.1Clock and Control Signals
This section describes LSI402ZX clock and control signals. Not all signals
are described. Refer to LSI402ZX Digital Signal Processor User’s Guide
for complete information about all LSI402ZX clock and control signals.
These clock and control signals are described in this section:
•CLKIN (Master Clock Input)
•CLKOUT (DSP Clock Output)
•PLLBYPASS (PLL Bypass)
•PLLSEL[3:0] (PLL Multiplier Select)
•RSTN (Device Reset)
•IBOOT (Memory Map Select)
•INT[4:0] (External Hardware Interrupts)
•NMI (Nonmaskable Interrupt)
•HALT (Halt Processor Clock)
3.1.1 CLKIN (Master Clock Input)
CLKIN is the Master Clock Input to the LSI402ZX. The setting of jumper
JP1 determines the clock’s source.
On-Board Oscillator – The EB402 provides an on-board 10 MHz
oscillator to clock the LSI402ZX. Connect pins 1–2 of JP1 to select the
on-board oscillator.
External Oscillator – The EB402 also allows an external oscillator to
clock the LSI402ZX. To use an external oscillator, connect pins 2–3 of
JP1, and connect an external oscillator to BNC connector J4.
3.1.2 CLKOUT (DSP Clock Output)
This signal is the DSP Clock output (buffered). The CLKOUT signal is
routed to BNC connector J1. The source of CLKOUT depends on the
level of the PLLBYPASS signal, which is controlled by jumper JP12.
Clock and Control Signals3-3
Page 26
3.1.3 PLLBYPASS (PLL Bypass)
When PLLBYPASS is LOW (JP12 installed), CLKIN is the PLL input, and
the PLL output is the DSP Clock. When PLLBYPASS is HIGH (JP12
removed), the PLL is bypassed, and CLKIN is the DSP Clock. During
normal operation, the level of PLLBYPASS must remain constant.
3.1.4 PLLSEL[3:0] (PLL Multiplier Select)
PLLSEL[3:0] are 4 binary-coded bits that determine the value of the PLL
multiplier. If the PLL is enabled, the product of the multiplier value and
the CLKIN frequency is the frequency of the processor clock.
Set the multiplier with the rotary hex encoder, S2. The encoder has 16
positions that correspond to multipliers of 10–25. Multiplier 25 is reserved
for test. The EB402 provides a 10 MHz clock to CLKIN. Therefore, using
the on-board oscillator, the range of operating frequencies is
100–240 MHz. Table 3.1 shows the PLL multiplier select options.
The PLL multiplier should only be changed when the EB402 is not
operating because changing the multiplier causes the PLL to lose lock.
Refer to LSI402ZX Digital Signal Processor User’s Guide for more
information about PLL multiplier selection.
Important:PLLSEL[3:0] = 0b1111 is reserved for test, so do not set
3.1.5 RSTN (Device Reset)
RSTN is the Device Reset input to the LSI402ZX. RSTN is driven by the
EB402 SYSRESETN signal. The output voltages of the EB402 power
supplies are monitored by circuits that generate a system reset signal if
a power supply voltage drops below its low-voltage threshold. The
open-drain outputs of both power monitors are connected, in a wired-OR
configuration, to a single 1 kΩ pull-up resistor. Figure 3.1 shows
these connections.
the PLLSEL switch to position F.
A MAX6337 power monitor is connected to the 1.8 V supply and
generates a reset signal if the output voltage drops below 1.6 V. The
power monitor holds SYSRESETN LOW for 100 ms. The reset input of
the power monitor is pulled-up internally and has no external connection.
A MAX6315 power monitor is connected to the 3.3 V supply to generate
a reset signal if the output voltage drops below 2.6 V. A normally-open
momentary push-button switch, S1, is connected to the Master Reset
(MRN) input of the power monitor. When activated, the switch causes the
power monitor to trigger a reset signal to the LSI402ZX. The power
monitor holds SYSRESETN LOW for 1.12 seconds.
SYSRESETN is inverted and routed to the EB402 on-board UART to
reset serial communications. For test purposes, SYSRESETN is
connected to J8, which is the control connector for the EEI.
Clock and Control Signals3-5
Page 28
3.1.6 IBOOT (Memory Map Select)
IBOOT is an input to the LSI402ZX. This signal selects the boot mode
for the LSI402ZX. To boot from the device’s internal memory, remove
jumper JP3. To boot from on-board external memory (Flash//SRAM),
install a jumper at JP3. For more information about selecting external
memory, refer to Section 3.4, “Memory and Memory-Mapped
INT[4:0] and NMI are external interrupt signals to the LSI402ZX. These
active-HIGH input signals are pulled LOW on the EB402. The EB402
uses these interrupts as shown in Table 3.2.
Table 3.2LSI402ZX External Interrupt Signal Use
InterruptOn-Board UseExternal Use
INT0Revision 2 PCB only,
connected to switch S4. Not
used on Revision 1 PCB.
INT1Not used.Available to user;
INT2Connected to SPORT0
Interface connector, J3.
(Not used by
EB-EBM-CODEC-1)
INT3Connected to SPORT1
Interface connector, J2.
(Not used by
BD-EBM-CODEC-1)
INT4INT4 is connected to the
UART’s interrupt output.
NMINot used.Not available to user.
Available to user;
connected to the control
connector, J8, of the EEI.
connected to the control
connector, J8, of the EEI.
Available to user;
connected to the control
connector, J8, of the EEI.
Available to user;
connected to the control
connector, J8, of the EEI.
Not available to user.
3-6Hardware Overview
Page 29
3.1.8 HALT (Halt Processor Clock)
HALT is an input to the LSI402ZX. When HALT is asserted, the
processor clock is disabled and halts the processor. This signal is pulled
LOW on the EB402. To halt the processor while it is running, install
jumper JP4.
RSTN or NMI must be used to wake a halted DSP. RSTN resets the
processor. NMI restarts the processor from where it has halted.
3.2PIO[7:0] (Programmable I/Os)
The LSI402ZX has 8 programmable input/output (PIO) signals. These
signals are used by the LSI402ZX internal boot ROM and the Evaluation
Board itself. Some programmable I/O signals are available to the user on
the EEI. Refer to LSI402ZX Digital Signal Processor User’s Guide for
additional information about the LSI402ZX PIO signals.
The EB402 uses the PIOs to control the codecs, control the EEI, and
select the HPI mode. The PIOs can also be used for testing the
Evaluation Board and the user’s programs. The PIO signals have
user-configured jumpers to select pull up/pull-down termination for these
signals. The jumpers and resistors are shown in Figure 3.1.
PIO[7:0] (Programmable I/Os)3-7
Page 30
PIO signal use is shown in Table 3.3.
Table 3.3PIO Signal Use
PIO Signal BOOT ROM UseEB402 UseExternal Use
PIO0Output goes LOW for a
short interval to signal
completion of self-test.
PIO1For HPI mode select. Input
HIGH selects Motorola
mode; input LOW selects
Intel mode.
PIO2Not used.Enables codec on
PIO3Not used.Resets codec on SPORT1.
PIO4Not used.Pull-up/pull-down jumper,
PIO5Not used.Pull-up/pull-down jumper,
PIO6Not used.Pull-up/pull-down jumper,
Enables codec on
SPORT0. Jumper JP11
selects pull-up/pull-down
termination.
Resets codec on SPORT0.
Jumper JP10 selects
pull-up/pull-down
termination.
Available as a general
purpose output pin at the
EEI Control Connector.
Available as a general
purpose output pin at the
EEI Control Connector.
Available as a general
purpose output pin at the
EEI Control Connector.
PIO7Not used.Not used.Not available.
3.2.1 Controlling the Codecs
You must reset the serial port audio codec daughterboards
(BD-EBM-CODEC-1), select their operating mode, and enable them
before using them. Use PIO[3:0] to reset and enable the codecs. One
codec is included with the EB402 package. It is configured and installed
on SPORT0.
3-8Hardware Overview
Page 31
Each PIO has a user configured jumper to select pull-up or pull-down
termination. The default configuration is pulled-up. When the PIOs are
configured as inputs, the jumpers can be used to continuously reset, or
enable, a codec for testing or debugging.
PIO0 enables the codec on Serial Port 0. Jumper JP11 selects pull-up
or pull-down termination. LED 3 is connected to PIO0 and illuminates
whenever PIO0 is LOW.
PIO1 resets the codec on Serial Port 0. Jumper JP10 selects pull-up or
pull-down termination.
PIO2 enables the codec on Serial Port 1. Jumper JP9 selects pull-up or
pull-down termination.
PIO3 resets the codec on Serial Port 1. Jumper JP8 selects pull-up or
pull-down termination.
3.2.2 Controlling the HPI Mode
When booting from the on-chip ROM, PIO1 controls the mode of the
LSI402ZX HPI. As the LSI402ZX comes out of reset, PIO1 selects Intel
or Motorola operating mode. If PIO1 is pulled-up (HIGH), HPI transfer
mode is set to Motorola mode. If PIO1 is pulled-down (LOW), HPI
transfer mode is set to Intel mode.
3.2.3 Controlling the External Expansion Interface (EEI)
PIO[6:4] control peripheral devices attached to the EEI. PIO[6:4] are
terminated by pull-up or pull-down resistors, which are connected to the
signal lines by user configured jumpers. The default configuration is
pulled-up.
3.2.4 Controlling Test and Debug Configurations
When PIO[6:0] are configured as inputs, the pull-up/pull-down resistors
can set input conditions for test programs, or control the program’s flow.
For example, a resistor can set an input HIGH when testing a software
loop that waits for a HIGH input before continuing the program.
PIO[7:0] (Programmable I/Os)3-9
Page 32
3.3External Interfaces
The section provides an overview of the EB402 external interfaces. In this
section, external interfaces are the physical interfaces users encounter
when operating the EB402. Refer to Section 5.2, “External Connectors,”
page 5-5, for additional information about external interfaces.
This section describes the following interfaces:
•JTAG Interface
•RS-232 Interface
•LSI402ZX Serial Port Interfaces
•Codec Interfaces
•Host Processor Interface (HPI
•External Expansion Interface (EEI)
•Discrete LED Display
3-10Hardware Overview
Page 33
3.3.1 JTAG Interfaces
The EB402 provides two JTAG interfaces to support emulators from
Corelis and Macraigor.
3.3.1.1 Corelis JTAG Interface
The Corelis JTAG connector, J7, provides a physical interface to the host
computer. The JTAG interface signals are buffered and connected to a
10-pin, low-profile header. Figure 3.2 shows the header and the signals
that connect to its pins.
Figure 3.2Corelis JTAG Connector
Header J7
1
TDI
1
1
3
TRSTn
2
GND
4
GND
5
TDO
1
TCK
7
1
9
TMS
Note: These signals are pulled up by a 1 kΩ resistor at the LSI402ZX.
The Corelis JTAG interface works with the SDK software tools and the
Corelis JTAG emulator (installed on the host computer) to provide
full-speed, in-circuit emulation.
3.3.1.2 Macraigor JTAG Interface
The Macraigor JTAG connector, J5, provides a physical interface to the
Macraigor JTA G controller installed on the host computer. The JTAG
interface signals are bufferedand connected to a 16-pin, low-profile header.
Figure 3.3 shows the header and the signals that connect to its pins.
10
6
GND
8
GND
GND
External Interfaces3-11
Page 34
Figure 3.3Macraigor JTAG Connector
XTDO
XTCK
SYSRESTN
XTDI
NC
TMS
NC
NC
1
3
5
7
9
11
13
15
2
GND
4
XTRSTN
6
VDD_SENSE
8
NC
10
NC
12
NC
14
NC
16
GND
The Macraigor JTAG interface works with the Green Hills Software
development tools and the Macraigor JTAG emulator that is attached to
the PC parallel port to provide full-speed in-circuit emulation.
3-12Hardware Overview
Page 35
3.3.2 RS-232 Interface
The EB402 has an RS-232 interface to provide a communication link
between the Evaluation Board and a host PC or workstation. The RS-232
interface uses a 9-pin female D-type connector, J10. The interface may
be used for emulation, or as a general-purpose serial interface.
When the host computer runs the debugger included with the SDK
software tools, the RS-232 interface can be used for in-circuit emulation
without any additional hardware.
The TL16C750 UART connects to the LSI402ZX as a memory-mapped
peripheral. The UART is enabled by PCS0N. On the evaluation board,
INT4 is dedicated to the RS-232 interface. The RS-232 interface and its
associated circuitry are shown in Figure 3.4.
Figure 3.4RS-232 Interface
Data Bus
ADDR[2:0]
INT4
RESET
RCLK
7.372 MHz
3
RCLK
BAUDOUTN
TL16C750C
UART
INTRPT
MR
XIN
Control Bus
8
SIN
SOUT
RTSN
CTSN
PCS0NRDNWR0N
Address Bus
R1OUT
T1IN
T3IN
R2OUT
T1OUT
MAX3233E
RS-232
T3OUT
GND/Vss
R1IN
R2IN
SHDNENN
SPDIN
SPDO
SPDTR
SPDSR
SPDCD
SPRTS
SPCTS
GND/Vss
J10
3
2
4
6
1
8
7
5
External Interfaces3-13
Page 36
3.3.3 BD-EBM-CODEC-1 Daughterboard
The LSI402ZX has two identical synchronous serial ports for receiving
and transmitting serial data. Each serial port is connected to a 20-pin
connector on the evaluation board; Serial Port 0 is connected to J3;
Serial Port 1 is connected to J2. The connectors provide a physical
interface for mounting daughterboards on the EB402. The standard
daughterboard is an audio codec module, BD-EBM-CODEC-1. One
BD-EBM-CODEC-1, configured and installed on SPORTO, is included
with the Evaluation Board. Figure 3.5 shows two BD-EBM-CODEC-1
modules connected to the LSI402ZX serial ports.
Figure 3.5Serial Port Interfaces to Codec Daughterboards
LSI402ZX
Serial
Port 0
Serial
Port 1
S0OBE
S0IBF
S0XFS
S0DO
S0XCLK
S0RCLK
S0RFS
S0DI
INT2
PIO0
PIO1
S1OBE
S1IBF
S1XFS
S1DO
S1XCLK
S1RCLK
S1RFS
S1DI
INT3
PIO2
PIO3
BD-EBM-CODEC-1
NC
NC
SDRFS
SDI
SCLK
SDXFS
SDO
NC
CODEC ENABLE
CODEC RESETN
NC
NC
SDRFS
SDI
SCLK
SDXFS
SDO
NC
CODEC ENABLE
CODEC RESETN
AD73322
AD73322
BD-EBM-CODEC-1
AD73322
AD73322
Cascade
Configuration
Cascade
Configuration
A1
A2
A3
A4
Audio
Jacks
A1
A2
A3
A4
Audio
Jacks
Note: NC pins are not connected.
3-14Hardware Overview
Page 37
Figure 3.6 shows the pin numbers and signal names for J3, which is the
20-pin serial port connector on the codec daughterboard.
Figure 3.6J3, BD-EBM-CODEC-1 Serial Port Connector
INT2
PIO0
PIO1
1
3
5
7
9
11
13
15
17
19
2
DVDD
4
SOD1
6
SORFS
8
SYSRESETN
10
SDRCLK
12
DGND
14
SOXFS
16
DGND
18
SDXCLK
20
DGND
DVDD
10 MHz*
+9 VDC*
SOD0
SDIBF
SDOBE
DGND
Note: * Revision 2 PCBs only; no connection on Revision 1 PCBs.
The codec receives audio frequency signals from an external system
through two audio jacks. The codec digitizes the signals and transmits
them to the LSI402ZX for processing. The module also receives processed
digital signals from the LSI402ZX, converts them to analog signals, and
transmits them to an external system through two other audio jacks.
Analog input signals from the audio jacks are sent to the 16-bit
analog-to-digital converters (ADCs) in the AD73322s, which are general
purpose dual-analog front-end devices. There are two of these devices
on each daughterboard, and each device has two ADCs. After the analog
signals are digitized, they are transmitted to the EB402 through the
AD73322’s serial ports.
The codec module receives processed digital signals from the EB402
through the AD73322 serial ports. The AD73322s perform a
digital-to-analog conversion (DAC) on the signals and transmit them to
an external system through two audio output jacks.
The codec analog outputs are limited to driving high-impedance loads.
They should only be used to drive amplified speakers that accept
line-level inputs. Do not connect passive, low-impedance (8 Ω) speakers
to these outputs. The analog inputs must also be line-level signals.
External Interfaces3-15
Page 38
Each BD-EBM-CODEC-1 module provides four 3.5 mm stereo audio
jacks for connecting external audio signals to the board. There are two
input-jacks and two output-jacks; one input-jack and one output-jack is
dedicated to each AD73322. Because each jack is a stereo connector,
the daughterboard supports a maximum of four inputs and four outputs.
The daughterboard ADCs must be configured in cascade mode to permit
the maximum number of I/Os. The codec module is configured with
removable jumpers. Cascade mode is the default configuration. The
BD-EBM-CODEC-1 board layout, shown in Figure 3.7, shows the
location of these jumpers.
Figure 3.7EBM CODEC-1 Board Layout
20
19
2
1
CHANNELS 1- 2
CHANNELS 3- 4
A1 INA3 OUTA2 INA1OUT
U3U2U1
EBM-CODEC-1
REV 0
J1
FS
J4
FS
J5
DO
1
J2
1
MCLK
DISABLE 3-2 2-1 ENABLE
1
External Interfaces3-17
Page 40
The codec module’s jumper settings are shown in Table 3.5.
Table 3.5BD-EBM-CODEC-1 Jumper Settings and Descriptions
No.LabelDescriptionPin 1Pin 2Pin 3
J1FSConnects frame sync
output to frame sync input
J2MCLKEnables the on-board
16.384 MHz clock
J4FSConfigures codec for
cascade mode
J5DOConfigures codec for
cascade mode
SORFSSOXFSN/AInstalled
DVDDOSC EN DGNDPins 1–2
C_B_OFSSORFSC_A_OFSPins 1–2
CODEC_B_DOSOD1CODEC_A_DO Pins 1–2
To connect input frame sync to output frame sync, install jumper J1. This
is the default configuration.
To enable the codec’s 16.384 MHz oscillator, install a jumper to connect
pins 1–2 of J2. This is the default configuration.
To cascade the AD73322s, you must install two jumpers: connect
pins 1–2 of J4; connect pins 1–2 of J5. This is the default configuration.
To operate the codec using a single AD73322, install two jumpers:
connect pins 2–3 pins of J4; connect pins 2–3 of J5.
3.3.4 Host Processor Interface (HPI)
Default
Position
The LSI402ZX HPI is an asynchronous 16-bit parallel port that allows an
external device to connect to the EB402. The HPI supports word
transfers for Motorola- and Intel-style memory interfaces. The LSI402ZX
internal boot ROM supports downloading code through the HPI, so an
external device connected to this interface can download code from a
host processor to the DSP. Refer to LSI402ZX Digital Signal ProcessorUser’s Guide for more information. The pinouts of the HPI connector, J6,
are shown in Figure 5.3 on page 5-7.
3-18Hardware Overview
Page 41
3.3.5 External Expansion Interface (EEI)
The EEI allows extending the LSI402ZX XBUS to an external system.
For example, the EEI allows the LSI402ZX to control off-board memory
and peripherals.
The XBUS control, address, and data signals are buffered and connected
to two external connectors; J8 has the control signals; J11 has the
address and data signals. These connectors provide a physical interface
for mounting a daughterboard that can provide additional external memory
or peripherals. The EEI uses the LSI402ZX HOLD/HOLDA protocol.
3.3.6 Discrete LED Display
After booting from the on-chip ROM, the LSI402ZX runs through an internal
diagnostic program and writes the self-test results into operand registers.
The results are also sent to the 74L VC574Aregisters, using PCS3N for the
write select. These registers drive 16 LEDs that display the results.
A write to anywhere in address space 0xFF00 to 0xFFFF will access the
LEDs because they are controlled by write select PCS3N. The LEDs are
numbered LD1 (LSB) to LD16 (MSB). These active-LOW LEDs are
always enabled; write 0b0 to illuminate an LED; write 0b1 to turn it off.
No wait states are required to latch data into the 74LVC574A registers.
PCS3N is programmed for zero wait states by setting register
p3wait = 0x0000.
3.4Memory and Memory-Mapped Peripherals
The EB402 memory consists of internal memory, which is inside the
LSI402ZX, and external memory, which can be on-board or off-board.
On-board external memory consists of flash memory, asynchronous
SRAM, and SBSRAM. The EEI allows placing additional external
memory on a daughterboard. Refer to Appendix A, Schematics,for
EB402 memory interface details. The following memory topics are
described in this section:
•Internal Memory
•External Memory and Memory-Mapped Peripherals
Memory and Memory-Mapped Peripherals3-19
Page 42
3.4.1 Internal Memory
The LSI402ZX has a 2 Kword boot ROM that provides start-up and selftest capabilities, 62 Kwords of internal instruction (program) memory,and
62 Kwords of internal data memory. Refer to LSI402ZX Digital SignalProcessor User’s Guide for a comprehensive explanation of the
LSI402ZX memory architecture.
3.4.2 External Memory and Memory-Mapped Peripherals
The EB402 provides external memory space that is accessible to the
LSI402ZX through its XBUS interface. The LSI402ZX can address up to
2 Mwords of external memory. External memory may be on-or off-board.
External memory space may be used for instruction memory, data
memory, or peripherals. In general, on-board jumpers map the memory
as instruction space, data space, or peripheral space. These jumper
settings are documented in Section 5.1, “EB402 Jumpers,” page 5-2.
The Evaluation Board has SBSRAM, flash memory, SRAM, an EEI, and
a UART that are mapped into the LSI402ZX memory space. The EEI
buffers the XBUS signals and permits it to interface with off-board
memory. Figure 3.8 shows how the external memory is configured.
3-20Hardware Overview
Page 43
Figure 3.8External Memory
Data Bus [31:0]
Address Bus [17:0]
DCS0N
RD WR0N WR1N
ICS0N
RD WR0N
LSI402ZX
ICS[0:3]N, DCS[0:3]N, PCS[0:3]N
DCS2N
ICS1N
RD WR0N
DCS1N
DCS3N
RD WR0N
HOLD
HOLDA
JP14
JP18
2
JP17
JP13
JP16
JP19
3
EN
SyncBurst
SRAM
128K x 32
EN
Flash
512K x 16
EN
EN
EN
Asynchronous
SRAM
EN
256K x 16
EN
EEI
EN
D[31:0]
A[17:0]
D[15:0]
A[17:0]
D[15:0]
A[17:0]
D[15:0]
A[17:0]
D[8:0]
PCS0N
EN
UART
A[2:0]
Memory and Memory-Mapped Peripherals3-21
Page 44
3.4.2.1 SRAM
The on-board SRAM is an IDT 71V416S10Y, a 256 kword x 16-bit
asynchronous SRAM with a 10 ns access time. The 71V416S10Y can
be configured as instruction memory or data memory. To configure the
SRAM as instruction memory that is enabled by ICS1N, install JP13. To
configure the SRAM as instruction memory that is enabled by ICS0N,
install a jumper between pins 2–3 of JP18. To configure the SRAM as
bootable instruction memory, install JP3 (IBOOT-OPEN), and install a
jumper between pins 2–3 of JP18. To configure the SRAM as data
memory that is enabled by DCS1N, install JP16.
3.4.2.2 SBSRAM
The SBSRAM is a Micron Semiconductor Products, Inc.,
MT58L128L32PT, which is a 128 kword x 32- bit pipe-lined single-cycle
deselect (SCD) memory. The SBSRAM can be used for very high speed
burst transfer data memory. DCS0N enables data memory when jumper
JP14 is installed.
3.4.2.3 Flash Memory
The flash memory is a Micron Semiconductor Products, Inc.,
MT28F800B3WG-10T, a 512 kword by 16-bit flash memory with a 100 ns
access time. The MT28F800B3WG-10T is in-circuit erasable and
programmable.
The flash memory can be used as instruction memory or data memory.
To configure the flash memory as instruction memory that is enabled by
ICS0N, install a jumper between pins 1–2 of JP18. To configure the flash
memory as data memory that is enabled by DCS2N, install JP17.
The LSI402ZX can boot from the flash memory. To boot from flash
memory, install the IBOOT-OPEN jumper, JP3, and install a jumper
between pins 1–2 of JP18.
3-22Hardware Overview
Page 45
3.4.2.4 Wait States
The flash memory device has 19 address lines, ADDR[18:0]. The XBUS
controls ADDR[17:0], which allows it to directly access 256 kwords of
flash memory. A second 256 kword boot/instruction block is
enabled/disabled by removing/installing jumper JP15. JP15 controls the
memory’s high order address bit, A18. This design allows two versions
of the code to coexist in the flash memory; each version is in a separate
memory location, which can be accessed by installing or removing A18.
Wait states are required when fetching instructions or data from external
memory. The number and duration of wait-states depends on the
processor clock rate (instruction cycle time). To calculate the minimum
number of wait states, use the following formula:
W = [(t
access+tsetup
)/T
cycle
]–1
where:
•W is the number of wait states required for an external access.
•t
SRAM and 100 ns for Flash ROM).
•t
•T
For example, assume the LSI402ZX processor clock is operating at
100 MHz. This clock frequency corresponds to
T
cycle
as external instruction memory is calculated as follows:
W = [(15 ns + 4 ns)/10 ns] – 1
W = 0.9
When W is greater than 0 but less than 1, round-up W to 1. When W is
negative, no wait states are required.
The maximum number of wait states is 128. When the LSI402ZX boots,
it defaults to the maximum number.
is the access time of the external memory device (10 ns for
access
is the required EB402 external data set-up time (4 ns).
setup
is the processor instruction cycle time.
cycle
= 1/100 MHz = 10 ns. The number of wait states for SRAM used
Memory and Memory-Mapped Peripherals3-23
Page 46
3.4.2.5 Memory Space Allocation
External memory can be configured as instruction memory, data
memory, or peripheral memory. In general, on-board jumpers configure
the memory. Table 3.6 shows how the Evaluation Board uses the chip
selects to map on-board memory.
Table 3.6Memory Chip Select
Chip SelectMemory SpaceDescription
ICS0NInstruction SpaceSelects flash memory or SRAM
ICS1NInstruction SpaceSelects SRAM
ICS2NInstruction SpaceNot Used
ICS3NInstruction SpaceNot Used
DCS0NData SpaceSelects SBSRAM
DCS1NData SpaceSelects SRAM
DCS2NData SpaceSelects flash memory
DCS3NData SpaceSelects EEI
PCS0NPeripheral SpaceSelects on-board UART
PCS1NPeripheral SpaceNot Used
PCS2NPeripheral SpaceNot Used
PCS3NPeripheral SpaceSelects LED Display
3-24Hardware Overview
Page 47
3.4.2.6 UART Memory Space
Although not memory, the on-board UART is mapped into the LSI402ZX
peripheral memory space. It is enabled by PCS0N. Accessing peripheral
memory requires wait states. These calculations are shown in
Section 3.4.2.4, “Wait States.”
3.4.2.7 External Expansion Interface (EEI)
The XBUS control, address, and data signals are buffered and routed to
two external connectors: the control signals go to J8; the address and
data signals go to J11. These connectors provide a physical interface for
mounting a daughterboard that can have additional external memory or
peripherals. The EEI daughterboard can be used as instruction space,
data space, or peripheral space.
Memory and Memory-Mapped Peripherals3-25
Page 48
3-26Hardware Overview
Page 49
Chapter 4
Operation
This chapter describes the Evaluation Board operating modes. This
chapter includes the following sections:
•Section 4.1, “Boot Modes”
•Section 4.2, “JTAG Emulation”
•Section 4.3, “RS-232-Based Emulation”
•Section 4.4, “Using Stand-Alone Mode”
4.1Boot Modes
The LSI402ZX performs a self-test when it boots from internal ROM. The
self-test writes to all internal memory locations. When the self-test
completes, the LSI402ZX writes test results to the LED display
(LED1–LED16), which is enabled by PCS3N.
After the test results are written to the LED display, the boot ROM code
instructs the LSI402ZX to read PIO1 to determine the HPI transfer mode.
Jumper JP10 selects pull-up or pull-down termination for PIO1. If PIO1
is pulled-up (HIGH), HPI transfer mode is set to Motorola mode. If PIO1
is pulled-down (LOW), HPI transfer mode is set to Intel mode.
Next, PIO0 is driven LOW for a few seconds to indicate completion of
self-test, then driven HIGH, then reset to input mode. The Evaluation
Board uses PIO0 as a discrete signal to the Serial Port 0 Interface
connector, where it is used to enable the codec daughterboard.
Jumper JP11 selects pull-up or pull-down termination for this signal.
EB402 Evaluation Board User’s Guide4-1
Page 50
LED3 is connected to PIO0 and illuminates whenever PIO0 is LOW. The
evaluation board illuminates LED3 when the self-test diagnostic starts,
and extinguishes LED3 when the diagnostic completes successfully
(approximately 5 seconds). If the self-test fails, LED3 remains
illuminated. However, PIO0 is also connected to SPORT0, and a
low impedance load connected to PIO0 on the SPORT0 daughterboard
can also cause LED3 to illuminate.
Refer to LSI402ZX Digital Signal Processor User’s Guide for more
information about self-test.
4.2JTAG Emulation
The LSI402ZX JTAG port IEEE 1149.1-compliant test access port (TAP)
that provides access to all on-chip resources. The DEU works with code
residing in the boot ROM to provide full-speed in-circuit emulation and to
allow full visibility and control of the device’s memory and registers. Refer
to LSI402ZX Digital Signal Processor User’s Guide for additional
information about the JTAG port and the DEU.
4.2.1 JTAG Software Tools
To use the EB402 in the JTAG mode, you need software tools that are
compatible with your JTAG controller hardware.
4.2.1.1 ZSP SDK Software Development KIt
Using the Corelis JTAG controller with the EB402 requires the ZSP SDK
Software Development Kit. This kit includes a C-language cross compiler,
assembler and linker, simulator, debugger, and software drivers for the
Corelis JTAG controllers. The user interface is the same for emulation
and simulation.
The SDK software tools are compatible with DOS, Windows 95,
Windows 98, Windows 2000, Windows NT, and Solaris operating
systems. Check the ZSP web site (http://www.zsp.com) for the latest
information about compatible computers, operating systems, JTAG
controllers, and development software.
4-2Operation
Page 51
SDK only provides a command line interface for Solaris. Refer to ZSP
SDK Software Development Kit User’s Guide for additional information
about installing and using this software package.
4.2.1.2 Green Hills Software ZSP Development Kit
Using the Macraigor JTAG controller with the EB402 requires the Green
Hills Software ZSP DevelopmentKit. The kit includes a C-language cross
compiler, assembler and linker, simulator, debugger,and software drivers
for the Macraigor JTAG controller. The Green Hills Software ZSP
development tools are compatible with DOS, Windows 95, Windows 98,
Windows 2000, Windows NT, and Solaris operating systems. Check the
ZSP web site (http://www.zsp.com) for the latest information about
compatible computers, operating systems, JTAG controllers, and
development software.
4.2.2 JTAG Hardware Tools
JTAG emulation requires a JTAG controller on the host computer with its
own specific software driver and JTAG interface cable. These items are
included with the Corelis JTAG emulators BD-PCMCIA1149 and
BD-PCI1149, which are available from LSI Logic Corporation.
The Macraigor Raven JTAG emulator is also compatible with the EB402.
This controller provides a hardware reset from the user interface.
JTAG Emulation4-3
Page 52
4.2.3 Installing JTAG Tools
Follow this procedure to install the JTAG tools:
1.Install your Corelis or Macgraigor JTAG controller in the host computer.
2.On the evaluation board, connect the Corelis JTAG cable to the
10-pin, low-profile header, J7, or connect the Macraigor JTAG cable to
the 16-pin, low-profile header, J5. These connections are shown
in Figure 4.1.
Figure 4.1JTAG Emulation Tools
Host Computer
JTAG
Controller
3.Next, install your software emulation tools on the host computer.
Refer to the ZSP SDK Software Development Kit User’s Guide or the
Green Hills Software Embedded ZSP Development Guide for system
requirements, installation procedures, and operating procedures.
4.2.4 Using JTAG Tools
Refer to the LSI Logic ZSP SDK Software Development Kit User’s Guide
or the Green Hills Software Embedded ZSP Development Guide for
operating procedures for these JTAG tools.
4.3RS-232-Based Emulation
RS-232-based emulation requires the RS-232 cable that is included with
the EB402 to connect it to the host computer. The ZSP400 SDK Software
Development Kit must be installed on the host computer.
JTAG Cable
J7/J5
EB402
LSI402ZX
On the evaluation board, the RS-232 interface connects to the LSI402ZX
through an on-board UART and provides access to all on-chip resources.
The DEU works with code residing in the bootable flash ROM to provide
4-4Operation
Page 53
full-speed, in-circuit emulation and to allow full visibility and control of the
device’s memory and registers. Refer to LSI402ZX Digital SignalProcessor User’s Guide for additional information about the DEU.
4.3.1 Connecting RS-232 Hardware
To use the EB402 in RS-232-based emulation mode, connect the host
computer’s RS-232 serial port to J10 on the evaluation board using the
RS-232 cable, as shown in Figure 4.2. J10 is a DB-9 connector. The
RS-232 cable is included in the EB402 package.
Figure 4.2RS-232-Based Emulation
Host Computer
RS-232 Port
RS-232 Cable
J10
4.3.2 Installing SDK and Using the RS-232 Interface
You must install the SDK software emulation tools to use the RS-232
interface in RS-232-based emulation mode. The ZSP SDK Software
Development Kit includes a C-language cross compiler, assembler and
linker, simulator, debugger, and software drivers for the hardware
emulation tools. These tools are compatible with DOS, Windows 95,
Windows 98, Windows 2000, Windows NT, and Solaris operating
systems. Check the ZSP web site (http://www.zsp.com) for the latest
information about compatible development software.
The user interface is the same for emulation and simulation. SDK only
provides a command line interface for Solaris. Refer to the ZSP SDKSoftware Development Kit User’s Guide for additional information about
installing and using this software package.
EB402
LSI401ZX
RS-232-Based Emulation4-5
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4.4Using Stand-Alone Mode
In stand-alone mode, the EB402 executes code from on-board memory.
No host computer is required.
To operate the Evaluation Board in stand-alone mode, use the following
procedure:
1.The on-board flash memory is preprogrammed with executable
demonstration code that you can use without modification.
However, you can also write your own executable demonstration files
and store them in the flash memory. Flash memory is relatively slow,
so accessing it requires wait states. At reset, the LSI402ZX is
programmed for 128 wait states, which is the maximum number. For
full-speed program execution, write your code to move the
application code from flash memory to the DSP’s internal RAM.
2.Configure the Evaluation Board to boot from flash memory by
installing the IBOOT jumper, JP3.
4-6Operation
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Chapter 5
Board Layout and
Jumper Settings
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This chapter describes the physical layout of the EB402. It includes
connectors, jumpers, and default jumper settings for the Evaluation
Board, as shipped by LSI Logic Corporation. Figure 5.1 is a simplified
drawing of the Evaluation Board that locates all the major components
discussed in this section.
This section describes the Evaluation Board jumpers. Table 5.1 lists
jumper numbers, jumper labels, pin connections, default settings, and a
description. Pin 1 of all jumpers is marked on the board silk screen. Most
jumpers also have a descriptive label.
5-2Board Layout and Jumper Settings
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Table 5.1Evaluation Board Jumper Settings and Descriptions
Note: NC pins are not connected; reserved pins are for factory use.
External Connectors5-11
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5-12Board Layout and Jumper Settings
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Appendix A
Schematics
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This appendix contains the schematics for the EB402 (Revision 2 PCB)
and the BD-EBM-CODEC-1 module. These drawings are also viewable
on the CD-ROM that is included with the EB402 package in portable
document format (PDF).
•Figure A.1, EB402 Schematics (Sheet 1 of 6)
•Figure A.2, EB402 Schematics (Sheet 2 of 6)
•Figure A.3, EB402 Schematics (Sheet 3 of 6)
•Figure A.4, EB402 Schematics (Sheet 4 of 6)
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•Figure A.5, EB402 Schematics (Sheet 5 of 6)
•Figure A.6, EB402 Schematics (Sheet 6 of 6)
•Figure A.7, BD-EBM-CODEC-1 Schematic Sheet 1 of 1
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EB402 Evaluation Board User’s GuideA-1
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A-2
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Figure A.1EB402 Schematics (Sheet 1 of 6)
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Figure A.2EB402 Schematics (Sheet 2 of 6)
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A-4
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Figure A.3EB402 Schematics (Sheet 3 of 6)
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Figure A.4EB402 Schematics (Sheet 4 of 6)
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Figure A.5EB402 Schematics (Sheet 5 of 6)
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Figure A.6EB402 Schematics (Sheet 6 of 6)
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A-8
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Figure A.7BD-EBM-CODEC-1 Schematic Sheet 1 of 1
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Appendix B
Bill of Materials
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Appendix B provides the bills of materials for the EB402 and the
BD-EBM-CODEC-1 codec module. The EB402 (Revision 2 PCB) bill of
materials is listed in Table B.1.
We would appreciate your feedback on this document. Please copy the
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Page 82
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