LSI EB402 User Manual

USER’S GUIDE

EB402 Evaluation Board

July 2001

®

l14020.A

This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.

Document DB15-000143-01, First Edition (July 2001)
This document describes Revision 1 and Revision 2 of the LSI Logic Corporation
EB402 Evaluation Board and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.

LSI Logic Corporation reserves the right to make changes to anyproductsherein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.

Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT

The LSI Logic logo design and ZSP are trademarks or registered trademarks of
LSI Logic Corporation. Solaris is a trademark of Sun Microsystems, Inc. Windows
95, Windows 98, Windows 2000, and Windows NT are registered trademarks of
Microsoft Corporation. All other brand and product names may be trademarks of
their respective companies.

GL

To receive product literature, visit us at http://www.lsilogic.com. and
http://www.zsp.com.

For a current list of our distributors, sales offices, and design resource
centers, view our web page located at

http://www.lsilogic.com/contacts/na_salesoffices.html

ii

Preface

This document is the primary reference and user’s guide for Revision 1
and Revision 2 of the EB402 Evaluation Board. Unless otherwise noted,
references to the EB402 apply to Revision 1 and Revision 2 printed
circuit boards (PCBs). LSI Logic incorporated the following changes in
Revision 2 of the EB402 Evaluation Board:

• Added + 9 VDC power to SPORT0 and SPORT1 to increase serial

port versatility.

• Added Macraigor JTAG Interface (J5 reserved on Revision 1).

• Added Diode CR1 to PCB to accommodate Macraigor JTAG Interface.

The EB402 is the evaluation board for LSI402ZX Digital Signal
Processors (DSPs). In this manual, the EB402 Evaluation Board is
referred to as the EB402.

Audience

This document assumes that you are familiar with DSPs and related
support devices. The people who benefit from this book are:

• Engineers and managers who are evaluating the LSI402ZX DSP for

possible use in a system.

• Engineers who are designing the LSI402ZX DSP into a system.

Preface iii

Organization

This document has the following chapters:

• Chapter 1, Introduction, provides an overview of the EB402 and

• Chapter 2, Installation, explains how to install EB402 hardware and

• Chapter 3, Hardware Overview, describes the LSI402ZX DSP signals,

• Chapter 4, Operation, explains the EB402 operating modes.

• Chapter 5, Board Layout and Jumper Settings, shows the physical

• Appendix A, Schematics, contains the schematics for the EB402

• Appendix B, Bill of Materials, lists the materials used in the EB402

Related Publications

describes its features.

verify its functionality with an RS-232-based or a JTAG-basedemulator.

the EB402 external interfaces, and the on-board memory configuration.

layout of the EB402, lists jumpers and their default settings, and
provides the pinouts for the PCB interface connectors.

and the BD-EBM-CODEC-1 Codec Daughterboard.

and the BD-EBM-CODEC-1 Codec Daughterboard.

The following documents provide supplemental information:
LSI402ZX Digital Signal Processor User’s Guide, LSI Logic Corporation,

Order No. R14021.B.
ZSP Digital Signal Processor Architecture Technical Manual, LSI Logic

Corporation, Order No. l14036.A.
EB402 Evaluation Board Getting Started, LSI Logic Corporation, Order

No. R14019.A.
ZSP SDK Software Development Kit User’s Guide, LSI Logic

Corporation, Order No. R14013.A.

iv Preface

Embedded ZSP Development Guide and associated documents for

MULTI version 3.5, Green Hills Software.
ZSP web site, www.zsp.com.
If you would like further information about components that are not

LSI Logic products, refer to the manufacturers’ information.

Conventions Used in This Manual

The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.

Courier typeface (Courier) is used for source code. Courier typeface is
also used for information that is displayed on a terminal monitor.

Preface v

vi Preface

Contents

Chapter 1 Introduction

1.1 Product Features 1-1

1.2 Operating Modes 1-2

1.2.1 JTAG Mode 1-2

1.2.2 RS-232 Mode 1-3

1.2.3 Stand-Alone Mode 1-3

1.3 Block Diagram 1-4

1.4 Packing List 1-5

1.5 Related Components 1-5

Chapter 2 Installation

2.1 Board Layout 2-1

2.2 Preparing to Install the Evaluation Board 2-2

2.3 Installing the Evaluation Board 2-3

2.4 Power-Up Sequence 2-5

Chapter 3 Hardware Overview

3.1 Clock and Control Signals 3-3

3.1.1 CLKIN (Master Clock Input) 3-3

3.1.2 CLKOUT (DSP Clock Output) 3-3

3.1.3 PLLBYPASS (PLL Bypass) 3-4

3.1.4 PLLSEL[3:0] (PLL Multiplier Select) 3-4

3.1.5 RSTN (Device Reset) 3-5

3.1.6 IBOOT (Memory Map Select) 3-6

3.1.7 INT[4:0] (External Hardware Interrupts), NMI
(Nonmaskable Interrupt) 3-6

3.1.8 HALT (Halt Processor Clock) 3-7

3.2 PIO[7:0] (Programmable I/Os) 3-7

Contents vii

3.2.1 Controlling the Codecs 3-8

3.2.2 Controlling the HPI Mode 3-9

3.2.3 Controlling the External Expansion Interface (EEI) 3-9

3.2.4 Controlling Test and Debug Configurations 3-9

3.3 External Interfaces 3-10

3.3.1 JTAG Interfaces 3-11

3.3.2 RS-232 Interface 3-13

3.3.3 BD-EBM-CODEC-1 Daughterboard 3-14

3.3.4 Host Processor Interface (HPI) 3-18

3.3.5 External Expansion Interface (EEI) 3-19

3.3.6 Discrete LED Display 3-19

3.4 Memory and Memory-Mapped Peripherals 3-19

3.4.1 Internal Memory 3-20

3.4.2 External Memory and Memory-Mapped

Chapter 4 Operation

4.1 Boot Modes 4-1

4.2 JTAG Emulation 4-2

4.2.1 JTAG Software Tools 4-2

4.2.2 JTAG Hardware Tools 4-3

4.2.3 Installing JTAG Tools 4-4

4.2.4 Using JTAG Tools 4-4

4.3 RS-232-Based Emulation 4-4

4.3.1 Connecting RS-232 Hardware 4-5

4.3.2 Installing SDK and Using the RS-232 Interface 4-5

4.4 Using Stand-Alone Mode 4-6

Peripherals 3-20

Chapter 5 Board Layout and Jumper Settings

5.1 EB402 Jumpers 5-2

5.2 External Connectors 5-5

Appendix A Schematics

Appendix B Bill of Materials

Customer Feedback

viii Contents

Figures

1.1 EB402 Block Diagram 1-4

2.1 Board Layout 2-2

3.1 Evaluation Board Block Diagram 3-2

3.2 Corelis JTAG Connector 3-11

3.3 Macraigor JTAG Connector 3-12

3.4 RS-232 Interface 3-13

3.5 Serial Port Interfaces to Codec Daughterboards 3-14

3.6 J3, BD-EBM-CODEC-1 Serial Port Connector 3-15

3.7 EBM CODEC-1 Board Layout 3-17

3.8 External Memory 3-21

4.1 JTAG Emulation Tools 4-4

4.2 RS-232-Based Emulation 4-5

5.1 Evaluation Board Layout 5-2

5.2 J5, Macraigor, JTAG Connector 5-6

5.3 J6, HPI Interface Connector 5-7

5.4 J7, Corelis JTAG Interface Connector 5-7

5.5 J10, RS-232 Interface Connector 5-8

5.6 J3, SPORT0 Daughterboard Interface Connector 5-8

5.7 J2, SPORT1 Daughterboard Interface Connector 5-9

5.8 J11, EEI A/D Connector 5-10

5.9 J8, EEI Control Connector 5-11
A.1 EB402 Schematics (Sheet 1 of 6) A-2
A.2 EB402 Schematics (Sheet 2 of 6) A-3
A.3 EB402 Schematics (Sheet 3 of 6) A-4
A.4 EB402 Schematics (Sheet 4 of 6) A-5
A.5 EB402 Schematics (Sheet 5 of 6) A-6
A.6 EB402 Schematics (Sheet 6 of 6) A-7
A.7 BD-EBM-CODEC-1 Schematic Sheet 1 of 1 A-8

Tables

3.1 PLL Multiplier Selections 3-4

3.2 LSI402ZX External Interrupt Signal Use 3-6

3.3 PIO Signal Use 3-8

3.4 BD-EBM-CODEC-1 Audio Connectors 3-16

3.5 BD-EBM-CODEC-1 Jumper Settings and Descriptions 3-18

Contents ix

3.6 Memory Chip Select 3-24

5.1 Evaluation Board Jumper Settings and Descriptions 5-3

5.2 Connector Summary 5-5
B.1 EB402 Bill of Materials B-1
B.2 BD-EBM-CODEC Bill of Materials B-5

x Contents

Chapter 1
Introduction

The EB402 is the evaluation board for the LSI Logic Corporation
LSI402ZX Digital Signal Processor (DSP) device. The EB402 provides a
hardware platform for evaluating the device and a software platform for
developing, debugging, and demonstrating real-time applications for the
LSI402ZX DSP. The EB402 also provides a reference design for
hardware designers, and a flexible full-featured emulation platform for
DSP software designers.

This chapter includes the following sections:

• Section 1.1, “Product Features”

• Section 1.2, “Operating Modes”

• Section 1.3, “Block Diagram”

• Section 1.4, “Packing List”

• Section 1.5, “Related Components”

1.1 Product Features

The EB402 provides the following features:

• RS-232 and JTAG interfaces for emulation, download, and debug.

• Full-speed execution of DSP programs.

• Full visibility and control of device memory and registers.

• Boot execution from nonvolatile flash memory for stand-alone test

and demonstration.

• On-board flash memory, SBSRAM, and SRAM for external

instruction and data memory.

EB402 Evaluation Board User’s Guide 1-1

• External Expansion Interface (EEI) for connecting additional external

memory and peripherals.

• Two serial port interfaces for flexible peripheral configurations.

• Codec Daughterboard(s) that supports up to eight channels of

real-time analog audio I/O.

• Host Processor Interface (HPI) for connecting the EB402 to a host

microprocessor.

1.2 Operating Modes

The EB402 has three operating modes:

• JTAG-Based Emulation

• RS-232-Based Emulation

• Stand-Alone Mode

The development and debug capabilities of JTAG- and RS-232-based
emulators are similar. Both modes provide access to all on-chip
resources. The device emulation unit (DEU) works in conjunction with
code residing in the boot ROM to provide full-speed in-circuit emulation,
and to allow full visibility and control of the device’s memory and registers.

The major differences between JTAG- and RS-232-based emulation are
communication speed, RS-232 stack requirements, and hardware debug
capabilities. JTAG-based emulation offers access to hardware debug
capabilities that are not available with RS-232-based emulation. Refer to
the ZSP™ SDK Software Development Kit User’s Guide for more
information about hardware debug capabilities.

1.2.1 JTAG Mode

The EB402 supports JTAG controllers from these manufacturers:

• Corelis JTAG Controller

• Macraigor Raven Controller

Check the ZSP web site (http://www.zsp.com) for the latest information
about compatible JTAG controllers and software.

1-2 Introduction

1.2.1.1 Corelis JTAG Controller

JTAG-based emulation requires an IBM-compatible PC, a Corelis JTAG
controller (PCI or PCMCIA) installed on the PC, a JTAG cable connecting
the PC to the EB402, and the LSI Logic Corporation SDK Software
Development Kit. SDK provides a compiler, assembler, linker, debugger,
and other utilities required to create, simulate, debug and execute
LSI402ZX programs on the EB402.

1.2.1.2 Macraigor Raven JTAG Controller

JTAG-based emulation requires an IBM-compatible PC with a parallel
port, a JTAG cable between the parallel port and connector J5 on the
EB402, and the Green Hills Software ZSP development tools. These
software tools provide a compiler, assembler, linker, debugger, and other
utilities required to create, simulate, debug and execute LSI402ZX
programs on the EB402. The Macraigor Raven JTAG controller provides
a hardware reset from the user interface.

1.2.2 RS-232 Mode

RS-232 mode works with IBM-compatible PCs, and workstations running
Solaris 2.5 and later versions. Using either type of system requires an
RS-232 cable and the ZSP SDK Software Development Kit. An RS-232
cable is included with the EB402 package.

SDK provides GUI and command line interfaces for IBM-compatible PC
systems; a command line interface is provided for Solaris. Check the
ZSP web site (http://www.zsp.com) for the latest information about
compatible computers, operating systems, and development software.

RS-232-based emulation does not support modifying the %smode control
register. Consequently, the emulator can access internal memory, but not
external memory.

Note: SDK 2.1 and earlier versions do not support the LSI402ZX.

1.2.3 Stand-Alone Mode

In stand-alone mode, the EB402 executes code from on-board memory
without a host computer attached to the evaluation board. This mode can
demonstrate the Evaluation Board. For example, you can write a

Operating Modes 1-3

stand-alone application and run it on the EB402, or use the
demonstration code that is included in the flash ROM. The flash ROM is
preprogrammed with code that supports serial port debug and
illuminates LEDs that indicate a successful self-test.

1.3 Block Diagram

A simplified block diagram of the EB402 is shown in Figure 1.1.

Figure 1.1 EB402 Block Diagram

JTAG I/F

HP I/F

Serial Port

Daughter Card I/F

(Codec Installed)

Serial Port

Daughter Card I/F

INT4

UART

JTAG

HPI

INT2
Serial Port 0
PIO[1:0]

INT3
Serial Port 1
PIO[3:2]

INT4

Flash RAM
512 K x 16

LSI402ZX

HOLD/HOLDA

XBUS

SRAM

256 K x 16

CLKIN

PLL

RSTN

PIO[6:4]

INT[1:0]

Access Control

SB-SRAM

128 K x 32

Clock

Support

Reset
Logic

16-Bit

External Expansion I/F

LED

Display

RS-232C

1-4 Introduction

Off-Board I/F

On-Board Memory

Logic

1.4 Packing List

The EB402 package includes the following components:

• EB402 PCB.

• BD-EBM-CODEC-1 Codec Daughterboard installed on EB402 PCB.

• Power Supply (input; 120 V or 240 V AC 50/60Hz; output: 9 V DC,

2.5 A) with separate AC power cable.

• RS-232 serial cable (9-pin) for RS-232-based emulation.

• This user’s guide, Document DB15-000143-01.

• EB402 Evaluation Board Getting Started.

Confirm that these items are included with your EB402. If any items are
missing, contact LSI Logic Corporation or your LSI Logic manufacturer’s
representative.

1.5 Related Components

Although the following items are not part of the EB402 package, you may
need these items to use with the EB402.

• ZSP400 Software Development Kit (SDK), SW-ZSP400SDK.

LSI Logic USA distribution contacts: Arrow, Avnet, or Insight.

• Green Hills Software MULTI 2000 Integrated Development

Environment. E-mail contact: [e-mail].

• Corelis PCI JTAG Emulator, BD-PCI1149. LSI Logic USA distribution

contacts: Arrow, Avnet, or Insight.

• Corelis PCMCIA JTAG Emulator, BD-PCMCIA1149. LSI Logic USA

distribution contacts: Arrow, Avnet, or Insight.

• Macraigor Systems RAVEN Parallel Port JTAG Interface. Contact:

http://www.macraigor.com.

Packing List 1-5

The following software components are available on the ZSP web site
(http://www.zsp.com):

• Example code

• Utility software

LSI Logic international distributors are listed in the back of this user’s guide.

1-6 Introduction

Chapter 2
Installation

This chapter explains how to install the EB402 and verify that it is
functioning correctly. It includes the following sections:

• Section 2.1, “Board Layout”

• Section 2.2, “Preparing to Install the Evaluation Board”

• Section 2.3, “Installing the Evaluation Board”

• Section 2.4, “Power-Up Sequence”

2.1 Board Layout

Figure 2.1 is a simplified drawing of the EB402 PCB. It shows the

location of the components that are referenced in this section.

EB402 Evaluation Board User’s Guide 2-1

Figure 2.1 Board Layout

20

19

J2

SPORT1

2

1

JTAG

J7

2

1

131415

2

1

J5

456

JP5 JP6 JP7 JP8 JP9 JP10 JP11

3.3V

16

LED1

VR1 VR1

R11

R12

J9

OFF

S3

ON

1.8V

LED2

J10 1

RESET

2

3

01123

PIO
PIN1-2(0)
PIN2-3(1)

3

LED3

SELFTEST

S1

20

19

BD-EBM_CODEC-1 Module

J3

EB402 S/N 134-30
REV 2/2.1

SN:

J1

PLL OUT

SPORT0

1

2

J4

PLL

REF IN

JP1

S4

INT 0

1

2

1

1

4

3

LSB

MSB

JP2
JP3

4

LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15
LD16

JP4

1

TP5

1.8V

CGND

TP6

TP7

IOGND

JP15

TP8

3.3V

A18

1

1

A
E

K
R

LSI402ZX

U5

51015

16

T

1

J6

HPI

JP18

XBOOT

JP20

JP13

IC1-A

FPV

JP14
D0-SB

JP16
D1-A

JP17
D2-F

A

F

JP19
D3-XEN

1

3

13

JP21
A16

JP22
A17

13

CLKIN

1

S2

0

C4

PLLSEL

8

BYP

JP12

OPEN

1 EXT A/DJ11

3

1

EXT CNTL

J8

2.2 Preparing to Install the Evaluation Board

Prepare to install the EB402 by following this procedure:

1. Using appropriate antistatic measures to prevent electrostatic
discharge (ESD) damage, unpack the PCB and the other components.

2. Verify that you have received all the components. Refer to

Section 1.4, “PackingList” on page 1-5, for the contents of the EB402

package. Inspect the components to verify that none are damaged.
If any components are missing or damaged, contact LSI Logic
Corporation or your LSI Logic manufacturer’s representative.

2-2 Installation

3. Place the PCB on a flat, dry surface. Like most electronic devices,
the Evaluation Board should be kept away from strong heat and
electromagnetic interference sources, including electric heaters.

4. Familiarize yourself with the PCB. You need to identify and
manipulate connectors, controls, indicators, and jumpers during the
installation. Figure 2.1 shows the board’s components. Refer to

Chapter 5, Board Layout and Jumper Settings, for additional

information on this subject.

2.3 Installing the Evaluation Board

Refer to the silk screen on the PCB for the location of components
referenced in this section. Refer to Table 5.1 on page 5-3 for additional
information about setting jumpers. To configure and install the EB402,
perform the following tasks:

1. Set the PCBs power switch, S3, to the OFF position.

2. Connect the input of the AC power supply to an AC power outlet. The
EB402 power supply is compatible with 120 V or 60 Hz and
240 V or 50 Hz sources.

3. Connect the power supply’s DC output to the EB402 power jack, J9.

4. Select either RS-232- or JTAG-based emulation. You may not use
both emulation modes simultaneously.

For RS-232-based emulation, use the RS-232 cable supplied with
the EB402 to connect the host PC’s RS-232 port to the DB-9
connector, J10, on the PCB.

For JTAG-based emulation, use a JTAG cable to connect the JTAG
interface on the host PC to the JTAG connector, J7 (Corelis) or
J5 (Macraigor), on the PCB.

Installing the Evaluation Board 2-3

5. Select the boot device. You may boot from either the on-board
external memory or the on-chip internal memory.

To boot from on-board external memory, install the IBOOT jumper,
JP3. Also, verify that the XBOOT jumper, JP18, is installed. The
position of JP18 determines whether flash memory or asynchronous
SRAM is the boot memory. To select SRAM, use a jumper to connect
pins 2–3 of JP18. To select flash memory, use a jumper to connect
pins 1–2 of JP18.

To boot from the LSI402ZX on-chip boot ROM, remove the jumper
at JP3.

6. Verify that the HALT jumper, JP4, is not installed. Installing JP4
causes the DSP to halt.

7. Verify that the GTN jumper, JP2, is not installed. Installing JP2
disables the LSI402ZX I/O drivers.

8. Select the reference clock. You can choose either the on-board
oscillator or an external clock source.

To select the on-board 10 MHz oscillator for the LSI402ZX reference
clock, use a jumper to connect pins 1–2 of JP1.

To select an external clock for the LSI402ZX reference clock, use a
jumper to connect pins 2–3 of JP1. Connect the external clock to
BNC connector J4.

9. Select the processor clock. You can select either the DSP PLL, or
CLKIN for the processor clock.

To select the output of the LSI402ZX PLL for the processor clock,
install the BYP jumper, JP12.

To bypass the PLL and select CLKIN for the processor clock,
remove JP12.

2-4 Installation

2.4 Power-Up Sequence

1. Set the power switch, S3, to the ON position.

2. Verify that the two surface mounted LEDs illuminate. LED1 is
connected to the 3.3 V regulator, VR1. LED2 is connected to the

1.8 V regulator, VR2. Illumination only indicates that the regulators
are producing an output voltage, not necessarily the specified voltage.

3. Measure the output voltage of VR1 at TP8. The specified output
voltage is 3.3 V, +/- 5%. The voltage is normally within specification.
If necessary, adjust the voltage with 25-turn potentiometer R11.

4. Measure the output of voltage regulator VR2 at TP5. The specified
output voltage is 1.8 V, +/- 5%. The voltage is normally within
specification. If necessary, adjust the voltage with 25-turn
potentiometer R12.

5. Verify that the self-test diagnostic completes successfully.The EB402
runs a self-test diagnostic when it boots from its internal ROM. The
LSI402ZX illuminates LED3 when the test starts and extinguishes
LED3 when the self-test completes successfully. If LED3 remains
illuminated at the end of the self-test, the test failed. Refer to
LSI402ZX Digital Signal Processor User’s Guide and Section 4.1,

“Boot Modes,” page 4-1, for more information about self-test.

6. If the self-test fails, momentarily press the reset switch, S1, to reset
the board.

Power-Up Sequence 2-5

2-6 Installation

Chapter 3
Hardware Overview

This chapter is an overview of the EB402 hardware. It describes
LSI402ZX clock and control signals, programmable I/O signals, external
interfaces, the codec daughterboard, and memory.

Only a few LSI402ZX signals are described in this chapter. Each of these
signals has a jumper, switch, or external connection that a user must
manipulate to configure the Evaluation Board. These configuration options
are explained in the following sections. For a complete listing of EB402
jumper settings, refer to Table 5.1. For a comprehensive description of all
DSP signals, refer to LSI402ZX Digital Signal Processor User’s Guide.

The chapter includes the following sections:

• Section 3.1, “Clock and Control Signals”

• Section 3.2, “PIO[7:0] (Programmable I/Os)”

• Section 3.3, “External Interfaces”

• Section 3.4, “Memory and Memory-Mapped Peripherals”

Figure 3.1 is a block diagram of the EB402.

EB402 Evaluation Board User’s Guide 3-1

Figure 3.1 Evaluation Board Block Diagram

Macraigor

J5

[7]

J3

2

SPORT0

BD-EBM-CODEC-1

2

SPORT1

J2

BD-EBM-CODEC-1

16

INT0

EEI

J8, J11

INT1
HOLD

HOLDA
PIO4,5,6

SYSRESETN

Connector

PIO0-6
Pull-Up/Pull-Down
Selection

PIO7

to CHIP
SELECT
CONFIG

18
32
12

16

Asynchronous

256 K x 16

JTAG

7

18

SRAM

Vcc

2

WR0N,
RDN

Corelis

Connector

JTAG

5

5

Buffer

5

JTAG CLKIN RSTN
IBOOT
PIO7
PIO[6:0]

8

Serial Port 0
INT2

8

Serial Port 1
INT3

DB AB

32

17

5

Syncburst

SRAM

128 K x 32

J7

10 MHz

OSC

LSI402ZX

XBUS

[17:0][31:0]

WR0N,
WR1N,

RDN
MEMCLK,

ADSN

Control

16

Memory

512 K x 16

J4

EXT CLKIN

SYSRESETN

INT0
INT1

HPI

INT4

2

18

Flash

8 3

RDN,
WR0N

From EEI

16 Data, 4 Ctrl, 2 Flags

22

7.372 MHz
OSC

UART

3

WRN,
RDN,
PCS0N

16

LEDs

LD[16:1]

Power

Monitor

Power

Monitor

UART

4

PCS3N

RS-232

8

3.3 V

1.8 V

4

Address
Data
Control

DCS[3:0]N,
ICS[3:0]N

Switch

S1

J6

HPI Connector

RS-232

J10

Connector

Switch

S3

Power

J9

3-2 Hardware Overview

VR1

VR2

Voltage Regulators

3.3 V

1.8 V

VDDIO33

PLLVDD

Chip Select

Configuration

3.1 Clock and Control Signals

This section describes LSI402ZX clock and control signals. Not all signals
are described. Refer to LSI402ZX Digital Signal Processor User’s Guide
for complete information about all LSI402ZX clock and control signals.

These clock and control signals are described in this section:

• CLKIN (Master Clock Input)

• CLKOUT (DSP Clock Output)

• PLLBYPASS (PLL Bypass)

• PLLSEL[3:0] (PLL Multiplier Select)

• RSTN (Device Reset)

• IBOOT (Memory Map Select)

• INT[4:0] (External Hardware Interrupts)

• NMI (Nonmaskable Interrupt)

• HALT (Halt Processor Clock)

3.1.1 CLKIN (Master Clock Input)

CLKIN is the Master Clock Input to the LSI402ZX. The setting of jumper
JP1 determines the clock’s source.

On-Board Oscillator – The EB402 provides an on-board 10 MHz
oscillator to clock the LSI402ZX. Connect pins 1–2 of JP1 to select the
on-board oscillator.

External Oscillator – The EB402 also allows an external oscillator to
clock the LSI402ZX. To use an external oscillator, connect pins 2–3 of
JP1, and connect an external oscillator to BNC connector J4.

3.1.2 CLKOUT (DSP Clock Output)

This signal is the DSP Clock output (buffered). The CLKOUT signal is
routed to BNC connector J1. The source of CLKOUT depends on the
level of the PLLBYPASS signal, which is controlled by jumper JP12.

Clock and Control Signals 3-3

3.1.3 PLLBYPASS (PLL Bypass)

When PLLBYPASS is LOW (JP12 installed), CLKIN is the PLL input, and
the PLL output is the DSP Clock. When PLLBYPASS is HIGH (JP12
removed), the PLL is bypassed, and CLKIN is the DSP Clock. During
normal operation, the level of PLLBYPASS must remain constant.

3.1.4 PLLSEL[3:0] (PLL Multiplier Select)

PLLSEL[3:0] are 4 binary-coded bits that determine the value of the PLL
multiplier. If the PLL is enabled, the product of the multiplier value and
the CLKIN frequency is the frequency of the processor clock.

Set the multiplier with the rotary hex encoder, S2. The encoder has 16
positions that correspond to multipliers of 10–25. Multiplier 25 is reserved
for test. The EB402 provides a 10 MHz clock to CLKIN. Therefore, using
the on-board oscillator, the range of operating frequencies is
100–240 MHz. Table 3.1 shows the PLL multiplier select options.

The PLL multiplier should only be changed when the EB402 is not
operating because changing the multiplier causes the PLL to lose lock.
Refer to LSI402ZX Digital Signal Processor User’s Guide for more
information about PLL multiplier selection.

Table 3.1 PLL Multiplier Selections

S2 Position PLLSEL[3:0] CLKIN Multiplier

0 0b0000 10.0 1 0b0001 11.0 2 0b0010 12.0 3 0b0011 13.0 4 0b0100 14.0 5 0b0101 15.0 6 0b0110 16.0 7 0b0111 17.0 8 0b1000 18.0 9 0b1001 19.0

3-4 Hardware Overview

Table 3.1 PLL Multiplier Selections (Cont.)

S2 Position PLLSEL[3:0] CLKIN Multiplier

A 0b1010 20.0 B 0b1011 21.0 C 0b1100 22.0 D 0b1101 23.0 E 0b1110 24.0 F 0b1111 Reserved

Important: PLLSEL[3:0] = 0b1111 is reserved for test, so do not set

3.1.5 RSTN (Device Reset)

RSTN is the Device Reset input to the LSI402ZX. RSTN is driven by the
EB402 SYSRESETN signal. The output voltages of the EB402 power
supplies are monitored by circuits that generate a system reset signal if
a power supply voltage drops below its low-voltage threshold. The
open-drain outputs of both power monitors are connected, in a wired-OR
configuration, to a single 1 kΩ pull-up resistor. Figure 3.1 shows
these connections.

the PLLSEL switch to position F.

A MAX6337 power monitor is connected to the 1.8 V supply and
generates a reset signal if the output voltage drops below 1.6 V. The
power monitor holds SYSRESETN LOW for 100 ms. The reset input of
the power monitor is pulled-up internally and has no external connection.

A MAX6315 power monitor is connected to the 3.3 V supply to generate
a reset signal if the output voltage drops below 2.6 V. A normally-open
momentary push-button switch, S1, is connected to the Master Reset
(MRN) input of the power monitor. When activated, the switch causes the
power monitor to trigger a reset signal to the LSI402ZX. The power
monitor holds SYSRESETN LOW for 1.12 seconds.

SYSRESETN is inverted and routed to the EB402 on-board UART to
reset serial communications. For test purposes, SYSRESETN is
connected to J8, which is the control connector for the EEI.

Clock and Control Signals 3-5

3.1.6 IBOOT (Memory Map Select)

IBOOT is an input to the LSI402ZX. This signal selects the boot mode
for the LSI402ZX. To boot from the device’s internal memory, remove
jumper JP3. To boot from on-board external memory (Flash//SRAM),
install a jumper at JP3. For more information about selecting external
memory, refer to Section 3.4, “Memory and Memory-Mapped

Peripherals,” page 3-19.

3.1.7 INT[4:0] (External Hardware Interrupts), NMI (Nonmaskable Interrupt)

INT[4:0] and NMI are external interrupt signals to the LSI402ZX. These
active-HIGH input signals are pulled LOW on the EB402. The EB402
uses these interrupts as shown in Table 3.2.

Table 3.2 LSI402ZX External Interrupt Signal Use

Interrupt On-Board Use External Use

INT0 Revision 2 PCB only,

connected to switch S4. Not
used on Revision 1 PCB.

INT1 Not used. Available to user;

INT2 Connected to SPORT0

Interface connector, J3.
(Not used by
EB-EBM-CODEC-1)

INT3 Connected to SPORT1

Interface connector, J2.
(Not used by
BD-EBM-CODEC-1)

INT4 INT4 is connected to the

UART’s interrupt output.

NMI Not used. Not available to user.

Available to user;
connected to the control
connector, J8, of the EEI.

connected to the control
connector, J8, of the EEI.

Available to user;
connected to the control
connector, J8, of the EEI.

Available to user;
connected to the control
connector, J8, of the EEI.

Not available to user.

3-6 Hardware Overview

3.1.8 HALT (Halt Processor Clock)

HALT is an input to the LSI402ZX. When HALT is asserted, the
processor clock is disabled and halts the processor. This signal is pulled
LOW on the EB402. To halt the processor while it is running, install
jumper JP4.

RSTN or NMI must be used to wake a halted DSP. RSTN resets the
processor. NMI restarts the processor from where it has halted.

3.2 PIO[7:0] (Programmable I/Os)

The LSI402ZX has 8 programmable input/output (PIO) signals. These
signals are used by the LSI402ZX internal boot ROM and the Evaluation
Board itself. Some programmable I/O signals are available to the user on
the EEI. Refer to LSI402ZX Digital Signal Processor User’s Guide for
additional information about the LSI402ZX PIO signals.

The EB402 uses the PIOs to control the codecs, control the EEI, and
select the HPI mode. The PIOs can also be used for testing the
Evaluation Board and the user’s programs. The PIO signals have
user-configured jumpers to select pull up/pull-down termination for these
signals. The jumpers and resistors are shown in Figure 3.1.

PIO[7:0] (Programmable I/Os) 3-7

PIO signal use is shown in Table 3.3.

Table 3.3 PIO Signal Use

PIO Signal BOOT ROM Use EB402 Use External Use

PIO0 Output goes LOW for a

short interval to signal
completion of self-test.

PIO1 For HPI mode select. Input

HIGH selects Motorola
mode; input LOW selects
Intel mode.

PIO2 Not used. Enables codec on

PIO3 Not used. Resets codec on SPORT1.

PIO4 Not used. Pull-up/pull-down jumper,

PIO5 Not used. Pull-up/pull-down jumper,

PIO6 Not used. Pull-up/pull-down jumper,

Enables codec on
SPORT0. Jumper JP11
selects pull-up/pull-down
termination.

Resets codec on SPORT0.
Jumper JP10 selects
pull-up/pull-down
termination.

SPORT1. Jumper JP9
selects pull-up/pull-down
termination.

Jumper JP8 selects pull­up/pull-down termination.

JP7, selectable to support
boot modes.

JP6, selectable to support
boot modes.

JP5, selectable to support
boot modes.

Available for SPORT0
daughterboard control.

Available for SPORT0
daughterboard control.

Available for SPORT1
daughterboard control.

Available for SPORT1
daughterboard control.

Available as a general
purpose output pin at the
EEI Control Connector.

Available as a general
purpose output pin at the
EEI Control Connector.

Available as a general
purpose output pin at the
EEI Control Connector.

PIO7 Not used. Not used. Not available.

3.2.1 Controlling the Codecs

You must reset the serial port audio codec daughterboards
(BD-EBM-CODEC-1), select their operating mode, and enable them
before using them. Use PIO[3:0] to reset and enable the codecs. One
codec is included with the EB402 package. It is configured and installed
on SPORT0.

3-8 Hardware Overview

Each PIO has a user configured jumper to select pull-up or pull-down
termination. The default configuration is pulled-up. When the PIOs are
configured as inputs, the jumpers can be used to continuously reset, or
enable, a codec for testing or debugging.

PIO0 enables the codec on Serial Port 0. Jumper JP11 selects pull-up
or pull-down termination. LED 3 is connected to PIO0 and illuminates
whenever PIO0 is LOW.

PIO1 resets the codec on Serial Port 0. Jumper JP10 selects pull-up or
pull-down termination.

PIO2 enables the codec on Serial Port 1. Jumper JP9 selects pull-up or
pull-down termination.

PIO3 resets the codec on Serial Port 1. Jumper JP8 selects pull-up or
pull-down termination.

3.2.2 Controlling the HPI Mode

When booting from the on-chip ROM, PIO1 controls the mode of the
LSI402ZX HPI. As the LSI402ZX comes out of reset, PIO1 selects Intel
or Motorola operating mode. If PIO1 is pulled-up (HIGH), HPI transfer
mode is set to Motorola mode. If PIO1 is pulled-down (LOW), HPI
transfer mode is set to Intel mode.

3.2.3 Controlling the External Expansion Interface (EEI)

PIO[6:4] control peripheral devices attached to the EEI. PIO[6:4] are
terminated by pull-up or pull-down resistors, which are connected to the
signal lines by user configured jumpers. The default configuration is
pulled-up.

3.2.4 Controlling Test and Debug Configurations

When PIO[6:0] are configured as inputs, the pull-up/pull-down resistors
can set input conditions for test programs, or control the program’s flow.
For example, a resistor can set an input HIGH when testing a software
loop that waits for a HIGH input before continuing the program.

PIO[7:0] (Programmable I/Os) 3-9

3.3 External Interfaces

The section provides an overview of the EB402 external interfaces. In this
section, external interfaces are the physical interfaces users encounter
when operating the EB402. Refer to Section 5.2, “External Connectors,”

page 5-5, for additional information about external interfaces.

This section describes the following interfaces:

• JTAG Interface

• RS-232 Interface

• LSI402ZX Serial Port Interfaces

• Codec Interfaces

• Host Processor Interface (HPI

• External Expansion Interface (EEI)

• Discrete LED Display

3-10 Hardware Overview

3.3.1 JTAG Interfaces

The EB402 provides two JTAG interfaces to support emulators from
Corelis and Macraigor.

3.3.1.1 Corelis JTAG Interface

The Corelis JTAG connector, J7, provides a physical interface to the host
computer. The JTAG interface signals are buffered and connected to a
10-pin, low-profile header. Figure 3.2 shows the header and the signals
that connect to its pins.

Figure 3.2 Corelis JTAG Connector

Header J7

1

TDI

1

1

3

TRSTn

2

GND

4

GND

5

TDO

1

TCK

7

1

9

TMS

Note: These signals are pulled up by a 1 kΩ resistor at the LSI402ZX.

The Corelis JTAG interface works with the SDK software tools and the
Corelis JTAG emulator (installed on the host computer) to provide
full-speed, in-circuit emulation.

3.3.1.2 Macraigor JTAG Interface

The Macraigor JTAG connector, J5, provides a physical interface to the
Macraigor JTA G controller installed on the host computer. The JTAG
interface signals are bufferedand connected to a 16-pin, low-profile header.

Figure 3.3 shows the header and the signals that connect to its pins.

10

6

GND

8

GND
GND

External Interfaces 3-11

Figure 3.3 Macraigor JTAG Connector

XTDO

XTCK

SYSRESTN

XTDI

NC

TMS

NC

NC

1
3
5
7

9
11
13
15

2

GND

4

XTRSTN

6

VDD_SENSE

8

NC

10

NC

12

NC

14

NC

16

GND

The Macraigor JTAG interface works with the Green Hills Software
development tools and the Macraigor JTAG emulator that is attached to
the PC parallel port to provide full-speed in-circuit emulation.

3-12 Hardware Overview

3.3.2 RS-232 Interface

The EB402 has an RS-232 interface to provide a communication link
between the Evaluation Board and a host PC or workstation. The RS-232
interface uses a 9-pin female D-type connector, J10. The interface may
be used for emulation, or as a general-purpose serial interface.

When the host computer runs the debugger included with the SDK
software tools, the RS-232 interface can be used for in-circuit emulation
without any additional hardware.

The TL16C750 UART connects to the LSI402ZX as a memory-mapped
peripheral. The UART is enabled by PCS0N. On the evaluation board,
INT4 is dedicated to the RS-232 interface. The RS-232 interface and its
associated circuitry are shown in Figure 3.4.

Figure 3.4 RS-232 Interface

Data Bus

ADDR[2:0]

INT4

RESET

RCLK

7.372 MHz

3

RCLK
BAUDOUTN

TL16C750C

UART

INTRPT
MR

XIN

Control Bus

8

SIN

SOUT

RTSN

CTSN

PCS0NRDNWR0N

Address Bus

R1OUT
T1IN

T3IN
R2OUT

T1OUT

MAX3233E

RS-232

T3OUT

GND/Vss

R1IN

R2IN

SHDNENN

SPDIN

SPDO

SPDTR
SPDSR

SPDCD

SPRTS
SPCTS

GND/Vss

J10

3
2
4
6
1
8
7

5

External Interfaces 3-13

3.3.3 BD-EBM-CODEC-1 Daughterboard

The LSI402ZX has two identical synchronous serial ports for receiving
and transmitting serial data. Each serial port is connected to a 20-pin
connector on the evaluation board; Serial Port 0 is connected to J3;
Serial Port 1 is connected to J2. The connectors provide a physical
interface for mounting daughterboards on the EB402. The standard
daughterboard is an audio codec module, BD-EBM-CODEC-1. One
BD-EBM-CODEC-1, configured and installed on SPORTO, is included
with the Evaluation Board. Figure 3.5 shows two BD-EBM-CODEC-1
modules connected to the LSI402ZX serial ports.

Figure 3.5 Serial Port Interfaces to Codec Daughterboards

LSI402ZX

Serial
Port 0

Serial
Port 1

S0OBE

S0IBF

S0XFS

S0DO
S0XCLK
S0RCLK

S0RFS

S0DI

INT2
PIO0
PIO1

S1OBE

S1IBF

S1XFS

S1DO
S1XCLK
S1RCLK

S1RFS

S1DI

INT3
PIO2
PIO3

BD-EBM-CODEC-1

NC
NC
SDRFS
SDI
SCLK

SDXFS
SDO

NC
CODEC ENABLE
CODEC RESETN

NC
NC
SDRFS
SDI
SCLK

SDXFS
SDO
NC
CODEC ENABLE
CODEC RESETN

AD73322

AD73322

BD-EBM-CODEC-1

AD73322

AD73322

Cascade
Configuration

Cascade
Configuration

A1

A2

A3

A4

Audio
Jacks

A1

A2

A3

A4

Audio
Jacks

Note: NC pins are not connected.

3-14 Hardware Overview

Figure 3.6 shows the pin numbers and signal names for J3, which is the

20-pin serial port connector on the codec daughterboard.

Figure 3.6 J3, BD-EBM-CODEC-1 Serial Port Connector

INT2
PIO0
PIO1

1
3
5
7
9
11
13
15
17
19

2

DVDD

4

SOD1

6

SORFS

8

SYSRESETN

10

SDRCLK

12

DGND

14

SOXFS

16

DGND

18

SDXCLK

20

DGND

DVDD

10 MHz*

+9 VDC*

SOD0

SDIBF

SDOBE

DGND

Note: * Revision 2 PCBs only; no connection on Revision 1 PCBs.

The codec receives audio frequency signals from an external system
through two audio jacks. The codec digitizes the signals and transmits
them to the LSI402ZX for processing. The module also receives processed
digital signals from the LSI402ZX, converts them to analog signals, and
transmits them to an external system through two other audio jacks.

Analog input signals from the audio jacks are sent to the 16-bit
analog-to-digital converters (ADCs) in the AD73322s, which are general
purpose dual-analog front-end devices. There are two of these devices
on each daughterboard, and each device has two ADCs. After the analog
signals are digitized, they are transmitted to the EB402 through the
AD73322’s serial ports.

The codec module receives processed digital signals from the EB402
through the AD73322 serial ports. The AD73322s perform a
digital-to-analog conversion (DAC) on the signals and transmit them to
an external system through two audio output jacks.

The codec analog outputs are limited to driving high-impedance loads.
They should only be used to drive amplified speakers that accept
line-level inputs. Do not connect passive, low-impedance (8 Ω) speakers
to these outputs. The analog inputs must also be line-level signals.

External Interfaces 3-15

Each BD-EBM-CODEC-1 module provides four 3.5 mm stereo audio
jacks for connecting external audio signals to the board. There are two
input-jacks and two output-jacks; one input-jack and one output-jack is
dedicated to each AD73322. Because each jack is a stereo connector,
the daughterboard supports a maximum of four inputs and four outputs.

Table 3.4 lists the audio connectors.

Table 3.4 BD-EBM-CODEC-1 Audio Connectors

Connector Label I/O Configuration AD73322

A1 A1 OUT Output U2
A2 A2 IN Input U2
A3 A3 OUT Output U3
A4 A4 IN Input U3

3-16 Hardware Overview

The daughterboard ADCs must be configured in cascade mode to permit
the maximum number of I/Os. The codec module is configured with
removable jumpers. Cascade mode is the default configuration. The
BD-EBM-CODEC-1 board layout, shown in Figure 3.7, shows the
location of these jumpers.

Figure 3.7 EBM CODEC-1 Board Layout

20

19

2

1

CHANNELS 1- 2

CHANNELS 3- 4

A1 INA3 OUTA2 INA1OUT

U3U2U1

EBM-CODEC-1

REV 0

J1

FS

J4

FS

J5

DO

1

J2

1

MCLK

DISABLE 3-2 2-1 ENABLE

1

External Interfaces 3-17

The codec module’s jumper settings are shown in Table 3.5.

Table 3.5 BD-EBM-CODEC-1 Jumper Settings and Descriptions

No. Label Description Pin 1 Pin 2 Pin 3

J1 FS Connects frame sync

output to frame sync input

J2 MCLK Enables the on-board

16.384 MHz clock

J4 FS Configures codec for

cascade mode

J5 DO Configures codec for

cascade mode

SORFS SOXFS N/A Installed

DVDD OSC EN DGND Pins 1–2

C_B_OFS SORFS C_A_OFS Pins 1–2

CODEC_B_DO SOD1 CODEC_A_DO Pins 1–2

To connect input frame sync to output frame sync, install jumper J1. This
is the default configuration.

To enable the codec’s 16.384 MHz oscillator, install a jumper to connect
pins 1–2 of J2. This is the default configuration.

To cascade the AD73322s, you must install two jumpers: connect
pins 1–2 of J4; connect pins 1–2 of J5. This is the default configuration.
To operate the codec using a single AD73322, install two jumpers:
connect pins 2–3 pins of J4; connect pins 2–3 of J5.

3.3.4 Host Processor Interface (HPI)

Default
Position

The LSI402ZX HPI is an asynchronous 16-bit parallel port that allows an
external device to connect to the EB402. The HPI supports word
transfers for Motorola- and Intel-style memory interfaces. The LSI402ZX
internal boot ROM supports downloading code through the HPI, so an
external device connected to this interface can download code from a
host processor to the DSP. Refer to LSI402ZX Digital Signal Processor
User’s Guide for more information. The pinouts of the HPI connector, J6,
are shown in Figure 5.3 on page 5-7.

3-18 Hardware Overview

3.3.5 External Expansion Interface (EEI)

The EEI allows extending the LSI402ZX XBUS to an external system.
For example, the EEI allows the LSI402ZX to control off-board memory
and peripherals.

The XBUS control, address, and data signals are buffered and connected
to two external connectors; J8 has the control signals; J11 has the
address and data signals. These connectors provide a physical interface
for mounting a daughterboard that can provide additional external memory
or peripherals. The EEI uses the LSI402ZX HOLD/HOLDA protocol.

3.3.6 Discrete LED Display

After booting from the on-chip ROM, the LSI402ZX runs through an internal
diagnostic program and writes the self-test results into operand registers.
The results are also sent to the 74L VC574Aregisters, using PCS3N for the
write select. These registers drive 16 LEDs that display the results.

A write to anywhere in address space 0xFF00 to 0xFFFF will access the
LEDs because they are controlled by write select PCS3N. The LEDs are
numbered LD1 (LSB) to LD16 (MSB). These active-LOW LEDs are
always enabled; write 0b0 to illuminate an LED; write 0b1 to turn it off.

No wait states are required to latch data into the 74LVC574A registers.
PCS3N is programmed for zero wait states by setting register
p3wait = 0x0000.

3.4 Memory and Memory-Mapped Peripherals

The EB402 memory consists of internal memory, which is inside the
LSI402ZX, and external memory, which can be on-board or off-board.
On-board external memory consists of flash memory, asynchronous
SRAM, and SBSRAM. The EEI allows placing additional external
memory on a daughterboard. Refer to Appendix A, Schematics,for
EB402 memory interface details. The following memory topics are
described in this section:

• Internal Memory

• External Memory and Memory-Mapped Peripherals

Memory and Memory-Mapped Peripherals 3-19

3.4.1 Internal Memory

The LSI402ZX has a 2 Kword boot ROM that provides start-up and self­test capabilities, 62 Kwords of internal instruction (program) memory,and
62 Kwords of internal data memory. Refer to LSI402ZX Digital Signal
Processor User’s Guide for a comprehensive explanation of the
LSI402ZX memory architecture.

3.4.2 External Memory and Memory-Mapped Peripherals

The EB402 provides external memory space that is accessible to the
LSI402ZX through its XBUS interface. The LSI402ZX can address up to
2 Mwords of external memory. External memory may be on-or off-board.

External memory space may be used for instruction memory, data
memory, or peripherals. In general, on-board jumpers map the memory
as instruction space, data space, or peripheral space. These jumper
settings are documented in Section 5.1, “EB402 Jumpers,” page 5-2.

The Evaluation Board has SBSRAM, flash memory, SRAM, an EEI, and
a UART that are mapped into the LSI402ZX memory space. The EEI
buffers the XBUS signals and permits it to interface with off-board
memory. Figure 3.8 shows how the external memory is configured.

3-20 Hardware Overview

Figure 3.8 External Memory

Data Bus [31:0]

Address Bus [17:0]

DCS0N

RD WR0N WR1N

ICS0N

RD WR0N

LSI402ZX

ICS[0:3]N, DCS[0:3]N, PCS[0:3]N

DCS2N

ICS1N
RD WR0N

DCS1N

DCS3N
RD WR0N

HOLD
HOLDA

JP14

JP18

2

JP17

JP13

JP16

JP19

3

EN

SyncBurst

SRAM

128K x 32

EN

Flash

512K x 16

EN

EN
EN

Asynchronous

SRAM

EN

256K x 16

EN

EEI

EN

D[31:0]

A[17:0]

D[15:0]

A[17:0]

D[15:0]

A[17:0]

D[15:0]

A[17:0]

D[8:0]

PCS0N

EN

UART

A[2:0]

Memory and Memory-Mapped Peripherals 3-21

3.4.2.1 SRAM

The on-board SRAM is an IDT 71V416S10Y, a 256 kword x 16-bit
asynchronous SRAM with a 10 ns access time. The 71V416S10Y can
be configured as instruction memory or data memory. To configure the
SRAM as instruction memory that is enabled by ICS1N, install JP13. To
configure the SRAM as instruction memory that is enabled by ICS0N,
install a jumper between pins 2–3 of JP18. To configure the SRAM as
bootable instruction memory, install JP3 (IBOOT-OPEN), and install a
jumper between pins 2–3 of JP18. To configure the SRAM as data
memory that is enabled by DCS1N, install JP16.

3.4.2.2 SBSRAM

The SBSRAM is a Micron Semiconductor Products, Inc.,
MT58L128L32PT, which is a 128 kword x 32- bit pipe-lined single-cycle
deselect (SCD) memory. The SBSRAM can be used for very high speed
burst transfer data memory. DCS0N enables data memory when jumper
JP14 is installed.

3.4.2.3 Flash Memory

The flash memory is a Micron Semiconductor Products, Inc.,
MT28F800B3WG-10T, a 512 kword by 16-bit flash memory with a 100 ns
access time. The MT28F800B3WG-10T is in-circuit erasable and
programmable.

The flash memory can be used as instruction memory or data memory.
To configure the flash memory as instruction memory that is enabled by
ICS0N, install a jumper between pins 1–2 of JP18. To configure the flash
memory as data memory that is enabled by DCS2N, install JP17.

The LSI402ZX can boot from the flash memory. To boot from flash
memory, install the IBOOT-OPEN jumper, JP3, and install a jumper
between pins 1–2 of JP18.

3-22 Hardware Overview

3.4.2.4 Wait States

The flash memory device has 19 address lines, ADDR[18:0]. The XBUS
controls ADDR[17:0], which allows it to directly access 256 kwords of
flash memory. A second 256 kword boot/instruction block is
enabled/disabled by removing/installing jumper JP15. JP15 controls the
memory’s high order address bit, A18. This design allows two versions
of the code to coexist in the flash memory; each version is in a separate
memory location, which can be accessed by installing or removing A18.

Wait states are required when fetching instructions or data from external
memory. The number and duration of wait-states depends on the
processor clock rate (instruction cycle time). To calculate the minimum
number of wait states, use the following formula:

W = [(t

access+tsetup

)/T

cycle

]–1

where:

• W is the number of wait states required for an external access.

• t

SRAM and 100 ns for Flash ROM).

• t

• T

For example, assume the LSI402ZX processor clock is operating at
100 MHz. This clock frequency corresponds to
T

cycle

as external instruction memory is calculated as follows:

W = [(15 ns + 4 ns)/10 ns] – 1
W = 0.9

When W is greater than 0 but less than 1, round-up W to 1. When W is
negative, no wait states are required.

The maximum number of wait states is 128. When the LSI402ZX boots,
it defaults to the maximum number.

is the access time of the external memory device (10 ns for

access

is the required EB402 external data set-up time (4 ns).

setup

is the processor instruction cycle time.

cycle

= 1/100 MHz = 10 ns. The number of wait states for SRAM used

Memory and Memory-Mapped Peripherals 3-23

3.4.2.5 Memory Space Allocation

External memory can be configured as instruction memory, data
memory, or peripheral memory. In general, on-board jumpers configure
the memory. Table 3.6 shows how the Evaluation Board uses the chip
selects to map on-board memory.

Table 3.6 Memory Chip Select

Chip Select Memory Space Description

ICS0N Instruction Space Selects flash memory or SRAM
ICS1N Instruction Space Selects SRAM
ICS2N Instruction Space Not Used
ICS3N Instruction Space Not Used
DCS0N Data Space Selects SBSRAM
DCS1N Data Space Selects SRAM
DCS2N Data Space Selects flash memory
DCS3N Data Space Selects EEI
PCS0N Peripheral Space Selects on-board UART
PCS1N Peripheral Space Not Used
PCS2N Peripheral Space Not Used
PCS3N Peripheral Space Selects LED Display

3-24 Hardware Overview

3.4.2.6 UART Memory Space

Although not memory, the on-board UART is mapped into the LSI402ZX
peripheral memory space. It is enabled by PCS0N. Accessing peripheral
memory requires wait states. These calculations are shown in

Section 3.4.2.4, “Wait States.”

3.4.2.7 External Expansion Interface (EEI)

The XBUS control, address, and data signals are buffered and routed to
two external connectors: the control signals go to J8; the address and
data signals go to J11. These connectors provide a physical interface for
mounting a daughterboard that can have additional external memory or
peripherals. The EEI daughterboard can be used as instruction space,
data space, or peripheral space.

Memory and Memory-Mapped Peripherals 3-25

3-26 Hardware Overview

Chapter 4
Operation

This chapter describes the Evaluation Board operating modes. This
chapter includes the following sections:

• Section 4.1, “Boot Modes”

• Section 4.2, “JTAG Emulation”

• Section 4.3, “RS-232-Based Emulation”

• Section 4.4, “Using Stand-Alone Mode”

4.1 Boot Modes

The LSI402ZX performs a self-test when it boots from internal ROM. The
self-test writes to all internal memory locations. When the self-test
completes, the LSI402ZX writes test results to the LED display
(LED1–LED16), which is enabled by PCS3N.

After the test results are written to the LED display, the boot ROM code
instructs the LSI402ZX to read PIO1 to determine the HPI transfer mode.
Jumper JP10 selects pull-up or pull-down termination for PIO1. If PIO1
is pulled-up (HIGH), HPI transfer mode is set to Motorola mode. If PIO1
is pulled-down (LOW), HPI transfer mode is set to Intel mode.

Next, PIO0 is driven LOW for a few seconds to indicate completion of
self-test, then driven HIGH, then reset to input mode. The Evaluation
Board uses PIO0 as a discrete signal to the Serial Port 0 Interface
connector, where it is used to enable the codec daughterboard.
Jumper JP11 selects pull-up or pull-down termination for this signal.

EB402 Evaluation Board User’s Guide 4-1

LED3 is connected to PIO0 and illuminates whenever PIO0 is LOW. The
evaluation board illuminates LED3 when the self-test diagnostic starts,
and extinguishes LED3 when the diagnostic completes successfully
(approximately 5 seconds). If the self-test fails, LED3 remains
illuminated. However, PIO0 is also connected to SPORT0, and a
low impedance load connected to PIO0 on the SPORT0 daughterboard
can also cause LED3 to illuminate.

Refer to LSI402ZX Digital Signal Processor User’s Guide for more
information about self-test.

4.2 JTAG Emulation

The LSI402ZX JTAG port IEEE 1149.1-compliant test access port (TAP)
that provides access to all on-chip resources. The DEU works with code
residing in the boot ROM to provide full-speed in-circuit emulation and to
allow full visibility and control of the device’s memory and registers. Refer
to LSI402ZX Digital Signal Processor User’s Guide for additional
information about the JTAG port and the DEU.

4.2.1 JTAG Software Tools

To use the EB402 in the JTAG mode, you need software tools that are
compatible with your JTAG controller hardware.

4.2.1.1 ZSP SDK Software Development KIt

Using the Corelis JTAG controller with the EB402 requires the ZSP SDK
Software Development Kit. This kit includes a C-language cross compiler,
assembler and linker, simulator, debugger, and software drivers for the
Corelis JTAG controllers. The user interface is the same for emulation
and simulation.

The SDK software tools are compatible with DOS, Windows 95,
Windows 98, Windows 2000, Windows NT, and Solaris operating
systems. Check the ZSP web site (http://www.zsp.com) for the latest
information about compatible computers, operating systems, JTAG
controllers, and development software.

4-2 Operation

SDK only provides a command line interface for Solaris. Refer to ZSP
SDK Software Development Kit User’s Guide for additional information

about installing and using this software package.

4.2.1.2 Green Hills Software ZSP Development Kit

Using the Macraigor JTAG controller with the EB402 requires the Green
Hills Software ZSP DevelopmentKit. The kit includes a C-language cross
compiler, assembler and linker, simulator, debugger,and software drivers
for the Macraigor JTAG controller. The Green Hills Software ZSP
development tools are compatible with DOS, Windows 95, Windows 98,
Windows 2000, Windows NT, and Solaris operating systems. Check the
ZSP web site (http://www.zsp.com) for the latest information about
compatible computers, operating systems, JTAG controllers, and
development software.

4.2.2 JTAG Hardware Tools

JTAG emulation requires a JTAG controller on the host computer with its
own specific software driver and JTAG interface cable. These items are
included with the Corelis JTAG emulators BD-PCMCIA1149 and
BD-PCI1149, which are available from LSI Logic Corporation.

The Macraigor Raven JTAG emulator is also compatible with the EB402.
This controller provides a hardware reset from the user interface.

JTAG Emulation 4-3

4.2.3 Installing JTAG Tools

Follow this procedure to install the JTAG tools:

1. Install your Corelis or Macgraigor JTAG controller in the host computer.

2. On the evaluation board, connect the Corelis JTAG cable to the
10-pin, low-profile header, J7, or connect the Macraigor JTAG cable to
the 16-pin, low-profile header, J5. These connections are shown
in Figure 4.1.

Figure 4.1 JTAG Emulation Tools

Host Computer

JTAG

Controller

3. Next, install your software emulation tools on the host computer.
Refer to the ZSP SDK Software Development Kit User’s Guide or the
Green Hills Software Embedded ZSP Development Guide for system
requirements, installation procedures, and operating procedures.

4.2.4 Using JTAG Tools

Refer to the LSI Logic ZSP SDK Software Development Kit User’s Guide
or the Green Hills Software Embedded ZSP Development Guide for
operating procedures for these JTAG tools.

4.3 RS-232-Based Emulation

RS-232-based emulation requires the RS-232 cable that is included with
the EB402 to connect it to the host computer. The ZSP400 SDK Software
Development Kit must be installed on the host computer.

JTAG Cable

J7/J5

EB402

LSI402ZX

On the evaluation board, the RS-232 interface connects to the LSI402ZX
through an on-board UART and provides access to all on-chip resources.
The DEU works with code residing in the bootable flash ROM to provide

4-4 Operation

full-speed, in-circuit emulation and to allow full visibility and control of the
device’s memory and registers. Refer to LSI402ZX Digital Signal
Processor User’s Guide for additional information about the DEU.

4.3.1 Connecting RS-232 Hardware

To use the EB402 in RS-232-based emulation mode, connect the host
computer’s RS-232 serial port to J10 on the evaluation board using the
RS-232 cable, as shown in Figure 4.2. J10 is a DB-9 connector. The
RS-232 cable is included in the EB402 package.

Figure 4.2 RS-232-Based Emulation

Host Computer

RS-232 Port

RS-232 Cable

J10

4.3.2 Installing SDK and Using the RS-232 Interface

You must install the SDK software emulation tools to use the RS-232
interface in RS-232-based emulation mode. The ZSP SDK Software
Development Kit includes a C-language cross compiler, assembler and
linker, simulator, debugger, and software drivers for the hardware
emulation tools. These tools are compatible with DOS, Windows 95,
Windows 98, Windows 2000, Windows NT, and Solaris operating
systems. Check the ZSP web site (http://www.zsp.com) for the latest
information about compatible development software.

The user interface is the same for emulation and simulation. SDK only
provides a command line interface for Solaris. Refer to the ZSP SDK
Software Development Kit User’s Guide for additional information about
installing and using this software package.

EB402

LSI401ZX

RS-232-Based Emulation 4-5

4.4 Using Stand-Alone Mode

In stand-alone mode, the EB402 executes code from on-board memory.
No host computer is required.

To operate the Evaluation Board in stand-alone mode, use the following
procedure:

1. The on-board flash memory is preprogrammed with executable
demonstration code that you can use without modification.

However, you can also write your own executable demonstration files
and store them in the flash memory. Flash memory is relatively slow,
so accessing it requires wait states. At reset, the LSI402ZX is
programmed for 128 wait states, which is the maximum number. For
full-speed program execution, write your code to move the
application code from flash memory to the DSP’s internal RAM.

2. Configure the Evaluation Board to boot from flash memory by
installing the IBOOT jumper, JP3.

4-6 Operation

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

4.333 pc

Chapter 5
Board Layout and
Jumper Settings

12 pc

12.938 pc

This chapter describes the physical layout of the EB402. It includes
connectors, jumpers, and default jumper settings for the Evaluation
Board, as shipped by LSI Logic Corporation. Figure 5.1 is a simplified
drawing of the Evaluation Board that locates all the major components
discussed in this section.

This chapter includes the following sections:

• Section 5.1, “EB402 Jumpers”

• Section 5.2, “External Connectors”

13.851 pc

34.732 pc

EB402 Evaluation Board User’s Guide 5-1

48.583 pc

52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

Figure 5.1 Evaluation Board Layout

20

19

1.8V

1.8V

CGND
CGND

TP6
TP6

IOGND
IOGND

3.3V

3.3V

20

19

BD-EBM_CODEC-1 Module

BD-EBM_CODEC-1 Module

J3
J3

SPORT0
SPORT0

1

2

1

2

1
1

J6
J6

HPI

U5
U5

51015

1
1

51015

A
A
E
E

LSI402Z

TP5

LSI402ZX

K

TP5

K
R

R

T
T

16
16

HPI

JP18

XBOOT

JP18

XBOOT

JP20
JP20

OPEN
OPEN

JP13

IC1-A

JP13

IC1-A

FPV
FPV

JP14
D0-SB

JP14
D0-SB

JP16
D1-A

JP16
D1-A

JP17
D2-F

JP17

A

F

D2-F

JP19

A

F

D3-XEN

JP19

1

3

D3-XEN

1

3

13

JP21

13

A16

JP21
A16

JP22
A17

JP22

13

A17

13

SN:
SN:

J1
J1

PLL OUT
PLL OUT

J4
J4

PLL
PLL

REF IN
REF IN

JP1

CLKIN

JP1

CLKIN

3

1

3

1

S2

0

S2

0

C4
C4

PLLSEL

8

PLLSEL

8

BYP

JP12

BYP

JP12

1 EXT A/DJ11
1 EXT A/DJ11

EB402 S/N 134-30
EB402 S/N 134-30

REV 2/2.1
REV 2/2.1

1
1

EXT CNTL
EXT CNTL

J8
J8

44.25 pc

20
20

SPORT1
SPORT1

2
2

JTAG
JTAG

J7

1

2

1

J7

1

2

1

131415
131415

16
16

VR1 VR1
VR1 VR1

R11
R11

J9
J9

OFF
OFF

S3
S3

ON
ON

19
19

J2
J2

1
1

2
2

J5
J5

456
456

JP5 JP6 JP7 JP8 JP9 JP10 JP11
JP5 JP6 JP7 JP8 JP9 JP10 JP11

3.3V

3.3V

LED1
LED1

R12
R12

1.8V

LED2

1.8V

LED2

J10 1
J10 1

RESET

2

RESET

2
3

3

01123
01123

PIO
PIN1-2(0)

PIO
PIN2-3(1)

PIN1-2(0)

3

PIN2-3(1)

3

LED3

LED3
SELFTEST
SELFTEST

S4

S1

INT 0

S4

S1

1
1

4
4

1

2

1

INT 0

1

JP2

1

2
3

3

LSB
LSB

MSB
MSB

JP2
JP3

4

JP3

4

JP4
JP4

1
1

LD1
LD1

LD2
LD2

LD3
LD3

LD4
LD4

LD5
LD5

LD6
LD6

LD7
LD7

LD8

TP7

LD8

LD9

TP7

LD9

LD10

JP15

LD10

LD11

TP8

JP15

LD11

TP8

A18

LD12

A18

LD12

LD13

1

LD13

LD14

1

LD14

LD15
LD15

LD16
LD16

4.333 pc

5.1 EB402 Jumpers

This section describes the Evaluation Board jumpers. Table 5.1 lists
jumper numbers, jumper labels, pin connections, default settings, and a
description. Pin 1 of all jumpers is marked on the board silk screen. Most
jumpers also have a descriptive label.

5-2 Board Layout and Jumper Settings

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52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

4.333 pc

Table 5.1 Evaluation Board Jumper Settings and Descriptions

No. Label Description Pin 1 Pin 2 Pin 3 Default

44.25 pc

JP1 CLKIN Selects the source for the

Master Clock.

JP2 GTN GTN – Factory use only.

Leave jumper open. Installing
jumper disables LSI402ZX
I/O drivers.

JP3 IBOOT IBOOT – Leave jumper open

to boot from internal ROM.
Install jumper to boot from
external memory.

JP4 HALT HALT – Install jumper to halt

the DSP.

JP5 PIO6 Selects pull-up or pull-down

termination for PIO6. PIO6 is
used by the EEI.

JP6 PIO5 Selects pull-up or pull-down

termination for PIO5. PIO5 is
use by the EEI.

JP7 PIO4 Selects pull-up or pull-down

termination for PIO4. PIO4 is
used by the EEI.

JP8 PIO3 Selects pull-up or pull-down

termination for PIO3. PIO3 is
used by the SPORT1
Daughterboard Interface.

On-board
10 MHz

Gnd GTN

CLOCKIN External

clock
N/A Open

Pins 1–2

pull-up

Gnd IBOOT

N/A Open

pull-up

HALT

+3.3 V N/A Open

pull-down
Pull-down PIO6 Pull-up Pins 2–3

Pull-down PIO5 Pull-up Pins 2–3

Pull-down PIO4 Pull-up Pins 2–3

Pull-down PIO3 Pull-up Pins 2–3

JP9 PIO2 Selects pull-up or pull-down

termination for PIO2. PIO2 is
used by the SPORT1
Daughterboard Interface.

JP10 PIO1 Selects pull-up or pull-down

termination for PIO1. PIO1 is
used by the SPORT0
Daughterboard Interface.

JP11 PIO0 Selects pull-up or pull-down

fortermination for PIO0. PIO0
is used by the SPORT0
Daughterboard Interface.

EB402 Jumpers 5-3

Pull-down PIO2 Pull-up Pins 2–3

Pull-down PIO1 Pull-up Pins 2–3

Pull-down PIO0 Pull-up Pins 2–3

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52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

Table 5.1 Evaluation Board Jumper Settings and Descriptions (Cont.)

4.333 pc

No. Label Description Pin 1 Pin 2 Pin 3 Default

44.25 pc

JP12 BYP PLLBYPASS – Remove this

jumper to bypass the on-chip
PLL, and use CLKIN for the
processor clock.

JP13 IC1-A This jumper lets ICS1N

enable the asynchronous
SRAM.

JP14 D0-SB This jumper lets DCS0N

enable the SyncBurst SRAM.

JP15 A18 Flash address 18 – Install

jumper to access upper 256
Kwords of address space.

JP16 D1-A This jumper lets DCS1N

enable asynchronous SRAM.

JP17 D2-F This jumper lets DCS2N

enable flash memory.

JP18 XBOOT Selects flash memory or

asynchronous SRAM as the
XBUS boot device.

JP19 D3-XEN This jumper lets DCS3N

enable the EEI. To enable the
EEI with another chip select,
or combination thereof,
connect the chip enables
together at this point.

Gnd PLLBYPA

N/A Installed

SS pull-up

ICSN1 SRAMEN/ N/A Pins 1–2

SBSRAMEN/ DCS0N N/A Pins 1–2

Flash

Gnd N/A Open
address
18 pull-up

SRAMEN/ DCS1N N/A Pins 1–2

FLASHEN/ DCS2N N/A Open

FLASHEN/ ICSN0 SRAMEN/ Pins 1–2

XEN/ DCS3N N/A Pins 1–2

JP20 FPV This jumper enables flash

Flash VPP +3.3 V N/A Pins 1–2

memory erase and write
operations.

JP21 A16 Selects pull-up or pull-down

Pull-up ADDR16 Pull-down Pins 1–2

termination for ADDR16.

JP22 A17 Selects pull-up or pull-down

Pull-up ADDR17 Pull-down Pins 1–2

termination for ADDR17.

5-4 Board Layout and Jumper Settings

48.583 pc

52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

4.333 pc

5.2 External Connectors

This section describes the evaluation board’s external connectors.

Table 5.2 lists all evaluation board connectors. It shows the connector

number,silk-screen label, and a functional description of each connector.
Figures referenced in the table illustrate connector pinout information.

Table 5.2 Connector Summary

Connector Label Functional Description

J1 PLL OUT Processor Clock Output (CLKOUT)
J2 SPORT1 Serial Port 1 Daughterboard Interface (See Figure 5.6)
J3 SPORT0 Serial Port 0 Daughterboard Interface (See Figure 5.7)
J4 PLL REF IN External Clock Input (CLKIN)
J5 – Macraigor JTAG Interface (See Figure 5.2
J6 HPI HPI Interface (See Figure 5.3)

44.25 pc

J7 JTAG Corelis JTAG Interface (See Figure 5.4
J8 EXT CNTL EEI Control (See Figure 5.9)

J9 – 9-Volt DC Power Supply Input
J10 – RS-232 Interface (See Figure 5.5)
J11 EXT A/D EEI Address/Data (See Figure 5.8)

48.583 pc

External Connectors 5-5

52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

Figure 5.2 shows the Macraigor JTAG Interface connector, connector

4.333 pc

pins, and signal names.

Figure 5.2 J5, Macraigor, JTAG Connector

44.25 pc

TDO

TDI

NC

TCK

TMS

NC

HRESTN

NC

11
13
15

1
3
5
7

9

2

GND

4

VDD_SENSE
NC

6

TRSTN

8

10

NC

12

NC

14

NC-Key

16

GND

5-6 Board Layout and Jumper Settings

48.583 pc

52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

Figure 5.3 shows the HPI Interface connector, connector pins, and

4.333 pc

signal names.

Figure 5.3 J6, HPI Interface Connector

44.25 pc

+ 9VDC
HPI DATA 01
HPI DATA 02

GND
HPI DATA 05
HPI DATA 06

GND
HPI DATA 09

GND 19
HPI DATA 13
HPI DATA 14

GND

HWRN

HCSN

GND

HOBIB

1
3
5
7
9
11
13
15
17HPI DATA 10

21
23
25
27
29
31
33

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34

HPI DATA 00
GND
HPI DATA 03
HPI DATA 04
GND
HPI DATA 07
HPI DATA 08
GND
HPI DATA 11
HPI DATA 12
GND
HPI DATA 15
HRDN
GND
HSTS
HOBE
HRESET

Figure 5.4 shows the Corelis JTAG Interface connector, connector pins,

and signal names.

Figure 5.4 J7, Corelis JTAG Interface Connector

10

2

GND

4

GND
GND

6

GND

8

GND

TRSTN

TDI
TDO
TMS

TCK

1
3
5
7
9

External Connectors 5-7

48.583 pc

52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

Figure 5.5 shows the RS-232 Interface connector, connector pins, and

4.333 pc

signal names.

Figure 5.5 J10, RS-232 Interface Connector

44.25 pc

TXD
RXD

GND

1

6

*DSR

2

7

CTS

3

8

RTS

4

9

RI (No Connection)

5

*DCD

*DTR

Note: Pins 1, 4, and 6 are tied together.

Figure 5.6 shows the Serial Port 0 Daughterboard Interface connector,

connector pins, and signal names.

Figure 5.6 J3, SPORT0 Daughterboard Interface Connector

VDDIO33

INT2
PIO0
PIO1

*10 MHz

*+9VDC

S0DO

S0IBF

S0OBE

GND

1
3
5
7
9
11
13
15
17
19

2
4
6

8
10
12
14
16
18
20

VDDIO33
S0DI
S0RFS
SYSRESETN
S0RCLK
GND
S0XFS
GND
S0XCLK
GND

Note: Revision 2 PCBs only; no connection on Revision 1 PCBs.

5-8 Board Layout and Jumper Settings

48.583 pc

52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

Figure 5.7 shows the Serial Port 1 Daughterboard Interface connector,

4.333 pc

connector pins, and signal names.

Figure 5.7 J2, SPORT1 Daughterboard Interface Connector

44.25 pc

INT3
PIO2
PIO3

GND

1
3
5
7
9
11
13
15
17
19

VDDIO33

*10 MHz

*+9VDC

S1DO
S1IBF

S1OBE

Note: Revision 2 PCBs only; no connection on Revision 1 PCBs.

2
4
6

8
10
12
14
16
18
20

VDDIO33
S1DI
S1RFS
SYSRESET
S1RCLK
GND
S1XFS
GND
S1XCLK
GND

External Connectors 5-9

48.583 pc

52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

Figure 5.8 shows the EEI address and data connector, connector pins,

and signal names.

Figure 5.8 J11, EEI A/D Connector

NC

1

35

RGND

NC

2

36

GND

NC

3

37

GND
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

+3.3 VDC

GND

+3.3 VDC

GND

GND

RGND

XD01

XD02

GND

XD05

XD06

GND

GND

XD10

XD11

XD12

XD13

GND

RGND

XA01

XA02

GND

XA05

XA06

GND

XA09

XA10

GND

XA13

XA14

GND

44.25 pc

NC
NC
NC
NC
NC
NC

XD00

GND
XD03
XD04

GND
XD07
XD08
XD09

GND

RGND

GND
XD14
XD15

XA00

GND

XA03
XA04

GND

XA07
XA08

GND

XA11
XA12

GND

XA15

4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

4.333 pc

Note: NC pins are not connected.

r

5-10 Board Layout and Jumper Settings

48.583 pc

52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

Figure 5.9 shows the EEI control connector, connector pins, and

4.333 pc

signal names.

Figure 5.9 J8, EEI Control Connector

44.25 pc

NC
Reserved
Reserved

NC

NC

NC

NC
Reserved
Reserved

NC

GND

XRDY

XHOLD

GND

XSPAREIN0

XHOLDA

XPIO4

GND

RGND

GND

XSPAREIO2

XSYSRESETN

XRDN

GND

XADDR17

XICS0N

GND

XICS3N

XDCS0N

GND

XDCS3N

XPCS0N

GND

XPCS3N

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

RGND
GND
GND
+3.3 VDC
GND
+3.3 VDC
GND
GND
RGND
NC
NC
GND
XINT0
XINT1
GND
GND
XPIO5
XPIO6
XSPAREIO0
XSPAREIO1
GND
RGND
XWR0N
XADDR16
GND
XICS1N
XICS2N
GND
XDCS1N
XDCS2N
GND
XPCS1N
XPCS2N
GND

Note: NC pins are not connected; reserved pins are for factory use.

External Connectors 5-11

48.583 pc

52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

4.333 pc

44.25 pc

48.583 pc

5-12 Board Layout and Jumper Settings

52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

4.333 pc

Appendix A
Schematics

12 pc

12.938 pc

This appendix contains the schematics for the EB402 (Revision 2 PCB)
and the BD-EBM-CODEC-1 module. These drawings are also viewable
on the CD-ROM that is included with the EB402 package in portable
document format (PDF).

• Figure A.1, EB402 Schematics (Sheet 1 of 6)

• Figure A.2, EB402 Schematics (Sheet 2 of 6)

• Figure A.3, EB402 Schematics (Sheet 3 of 6)

• Figure A.4, EB402 Schematics (Sheet 4 of 6)

13.851 pc

34.732 pc

• Figure A.5, EB402 Schematics (Sheet 5 of 6)

• Figure A.6, EB402 Schematics (Sheet 6 of 6)

• Figure A.7, BD-EBM-CODEC-1 Schematic Sheet 1 of 1

48.583 pc

EB402 Evaluation Board User’s Guide A-1

52.5 pc

A-2

3.75 pc

44.25 pc

44.25 pc

5.4 pc 49.65 pc1.5 pc

Figure A.1 EB402 Schematics (Sheet 1 of 6)

38.25 pc34.5 pc

3.75 pc

44.25 pc

44.25 pc

5.4 pc 49.65 pc1.5 pc

Figure A.2 EB402 Schematics (Sheet 2 of 6)

A-3

38.25 pc34.5 pc

A-4

3.75 pc

44.25 pc

44.25 pc

5.4 pc 49.65 pc1.5 pc

Figure A.3 EB402 Schematics (Sheet 3 of 6)

38.25 pc34.5 pc

3.75 pc

44.25 pc

44.25 pc

5.4 pc 49.65 pc1.5 pc

Figure A.4 EB402 Schematics (Sheet 4 of 6)

A-5

38.25 pc34.5 pc

A-6

3.75 pc

44.25 pc

44.25 pc

5.4 pc 49.65 pc1.5 pc

Figure A.5 EB402 Schematics (Sheet 5 of 6)

38.25 pc34.5 pc

3.75 pc

44.25 pc

44.25 pc

5.4 pc 49.65 pc1.5 pc

Figure A.6 EB402 Schematics (Sheet 6 of 6)

A-7

38.25 pc34.5 pc

A-8

3.75 pc

44.25 pc

44.25 pc

5.4 pc 49.65 pc1.5 pc

Figure A.7 BD-EBM-CODEC-1 Schematic Sheet 1 of 1

38.25 pc34.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

4.333 pc

Appendix B
Bill of Materials

12 pc

12.938 pc

Appendix B provides the bills of materials for the EB402 and the
BD-EBM-CODEC-1 codec module. The EB402 (Revision 2 PCB) bill of
materials is listed in Table B.1.

Table B.1 EB402 Bill of Materials

Item Quantity Reference Part Description Source

1 1 U2 SN74LVTH244APWR Octal Buffer TI
2 1 U13 71V416S10Y SRAM IDT

13.851 pc

34.732 pc

3 1 U7 SN74LVC08AD AND Gate TI
4 1 U5 LSI402ZX DSP LSI Logic
5 1 U1 MAX6315US26D4-T Power Monitor Maxim
6 1 U3 MAX6337US16D3-T Power Monitor Maxim
7 1 U11 MAX3233ECPP RS-232 XCVR Maxim
8 1 U9 MT28F800B3WG10T 8M Flash Boot

Block
9 1 U18 MT58L128L32PT SBSRAM Micron
10 3 U6, U15, U20 QS3VH125S1 Quad SW IDT
11 1 U4 QS3VH245Q Switch IDT
12 4 U8, U10, U17, U19 QS74LCX2X2H2452 XCVR IDT
13 2 U14, U16 SN74LVC574ADW Latch TI
14 1 U12 TL16C750FN UART TI

Micron

48.583 pc

EB402 Evaluation Board User’s Guide B-1

52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

Table B.1 EB402 Bill of Materials (Cont.)

4.333 pc

Item Quantity Reference Part Description Source

44.25 pc

15 1 Y1 SE2818CT-ND 10 MHz Crystal

Oscillator

Epson
Electronics
America, Inc.

16 1 Y2 SE2814CT-ND 7.372 MHz

Crystal

Oscillator

Epson
Electronics

America, Inc.
17 2 VR1, VR2 LM338AT Regulator National Semi
18 1 Q1 MMBT2907ALT1 PNP Transistor Motorola
19 19 LD1–LD16, LED1–LED3 SS-Type LED Panasonic
20 1 D1 MURS110T3 SMT Rectifier Motorola
21 2 R11, R12 3299W-501-ND 500 Ω Pot

Bournes

25-Turn

22 28 R5, R8–R10, R13–R16,

R21–R25, R29–R33,
R36, R38–R40,

CRCW08051002FR4 10 kΩ

SMT Resistor
805

Vishay Dale

R42–R44, R46, R49,
R50

23 6 R3, R19–R20, R26–R28 CRCW08051001FR4 1 kΩ SMT

Vishay Dale

Resistor 805

24 2 R37, R48 CRCW1206-241-5% 240 Ω

Vishay Dale

SMT Resistor

25 1 R45 CRCW1206-503-5% 50 kΩ

SMT Resistor

26 1 R47 CRCW1206-471-5% 470 Ω SMT

Resistor

27 5 R17, R18, RP2–RP4 EXB-AA10P472J 4.7 kΩ Resistor

Network

28 2 R6, R7 MSP10A-01 270 Ω

Resistor
Network

29 1 RP1 MSP06A-01 4.7 kΩ Resistor

SIP

B-2 Bill of Materials

Vishay Dale

Vishay Dale

Panasonic

Vishay Dale

Vishay Dale

48.583 pc

52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

Table B.1 EB402 Bill of Materials (Cont.)

4.333 pc

Item Quantity Reference Part Description Source

44.25 pc

30 3 R1, R2, R4 770-101-10k 10 kΩ Resistor

CTS

Network

31 49 C10–C14, C16, C17,

C19, C20, C22, C23,

PCC1762CT-ND 0.1 µF

SMT Cap

Panasonic

C25,C25–C27, C32,
C36–C39, C43, C46,
C48, C50, C52, C53,
C56–C64, C67, C71,
C72, C74, C78, C79,
C81–C83, C85,
C88–C92

32 7 C44, C51, C70,

C75–C77, C80

293D105X9020A2T 1 µF SMT Cap Vishay-

Sprague
33 9 C1–C9 293D106X9010C2T 10 µF SMT Cap Vishay-

Sprague
34 27 C15, C18, C21, C24,

C28–C31, C33–C35,

PCC1750CT-ND 0.01 µF

SMT Cap

Panasonic

C40–C42, C45, C47,
C49, C54, C55, C65,
C66, C68, C69, C73,
C84, C86, C87

35 2 L1, L2 5800-100 10 µH

JW Miller

Choke Coil
36 1 S3 7101SYCQE SPDT Switch C&K
37 2 S1, S4 TL1105AF250Q PB Switch E-Switch
38 1 S2 350041GS Rotary Switch EECO
39 2 J8, J11 15-87-0305 68-Pin

Molex

Connector
40 2 J1, J4 28JR272-1 BNC Jack Berg

Electronics

41 1 J5 2516-6002UG 16-Pin

3M

Connector
42 1 J7 2510-6002UB 10-Pin Header 3M
43 1 J10 745781-4 DB9F AMP

B-3

48.583 pc

52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

Table B.1 EB402 Bill of Materials (Cont.)

4.333 pc

Item Quantity Reference Part Description Source

44 1 J9 16PJ031 Power Jack Mouser

44.25 pc

45 J6 66506-076 34-Pin

Berg

Connector
46 11 JP1, JP5–JP11, JP18,

JP21, JP22

47 11 JP2–JP4, JP12–JP17,

69190-403 3-Pin Straight

Berg

Header

69190-402 2-Pin Header Berg

JP19, JP20
48 2 J2, J3 2520-6002UB 20-Pin Header 3M
49 9 JMP1–JMP9 65474-002 Jumper Berg
50 2 ASSY1, ASSY2 6107B-14 Heat Sink Thermalloy
51 2 MTG1, MTG2 4880 Mounting Kit Thermalloy
52 8 M17–M24 N2321090 Nylon 4-40

Nut and Washer

53 8 M9–M16 N2321080 1/4" Nylon

Electronix
Express

–

Screw 4-40

54 8 M1–M8 4802 0.5" Standoff

Keystone
M/F 4-40
Thread

55 2 R34, R35 0.0EBK-ND 0 Ω Resistor Digi-Key
56 1 CR1 BAU99LTI Diode Motorola

Table B.2 is the EBM-CODEC-1 bill of materials.

B-4 Bill of Materials

48.583 pc

52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

4.333 pc

Table B.2 BD-EBM-CODEC Bill of Materials

Item Quantity Reference Part Description Source

44.25 pc

1 1 U1 SN74LV74 Dual D-Type

Flip-Flop

2 2 U2, U3 AD73322AR Dual Analog

Texas
Instruments

Analog Devices

Front End

3 1 Y1 SG-8002JC16.384M-

PCC

16.384 MHz
Oscillator

Epson
Electronics
America, Inc.

4 4 C17–C20 ECU-V1H333KBW 0.033 µF

Panasonic

SMT Ceramic

5 4 C13, C15, C21, C22 ECU-V1H473KBW 0.047 µF

Panasonic

SMT Ceramic

6 13 C9–C12, C14, C16,

C23–C29

PCC104BCT-ND 0.1 µF

SMT CAP

Panasonic

7 8 C1–C8 293D106X9010C2T 10 µF SMT Cap Vishay-Sprague
8 4 R1, R2, R9, R11 CRCW08051000FR4 100 Ω

Vishay Dale

SMT Resistor

9 4 R3, R4, R10, R11 CRCW08051002FR4 10 kΩ

Vishay Dale

SMT Resistor

10 4 R5–R8 CRCW08054702FR4 47 kΩ

Vishay Dale

SMT Resistor

11 6 L1–L6 MI1206K310R-00 20 nH RFI

Steward

Suppress Bead

12 4 A1–A4 161-3504 Audio Jack Mouser

Electronic

13 3 J2, J4, J5 69190-403 3-Pin Straight

Berg

Header
14 1 J1 69190-402 2-Pin Header Berg
15 1 J3 9120-4500JL 20-PinPolarized

3M
Board Mount
Socket

B-5

48.583 pc

52.5 pc

3.75 pc 10.25 pc 11.25 pc 38.25 pc

34.5 pc

4.333 pc

44.25 pc

48.583 pc

B-6 Bill of Materials

52.5 pc

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