LSI 53C875A User Manual

TECHNICAL

MANUAL

LSI53C875A
PCI to Ultra SCSI
Controller

Version 2.0

December 2000

®

S14047

This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.

Document DB14-000143-01, Second Edition (December 2000).
This document describes the LSI Logic LSI53C875APCIto Ultra SCSI Controller
and will remain the official reference source for all revisions/releases of this
product until rescinded by an update.

To receive product literature, visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property r ights of
LSI Logic or third parties.

Ultra SCSI is the term used by the SCSI Trade Association (STA) to describe
Fast-20 SCSI, as documented in the SCSI-3 Fast-20 Parallel Interface standard,
X3,277-199X.

Copyright © 2000 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT

The LSI Logic logo design, TolerANT, and SCRIPTS are registered trademarks
or trademarks of LSI Logic Corporation. All other brand and product names may
be trademarks of their respective companies.

HH

ii

Audience

Preface

This book is the primary reference and technical manual for the
LSI53C875A PCI to Ultra SCSI Controller. It contains a complete
functional description for the product and also includes complete physical
and electrical specifications.

This manual provides reference information on the LSI53C875A PCI to
Ultra SCSI Controller. It is intended for system designers and
programmers who are using this device to design an Ultra SCSI port for
PCI-based personal computers, workstations, servers or embedded
applications.

Organization

This document has the following chapters and appendixes:

• Chapter 1, General Description includes general information about

the LSI53C875A.

• Chapter 2, Functional Description describes the main functional

areas of the chip in more detail, including interfaces to the SCSI bus
and external memory.

• Chapter 3, Signal Descriptions contains pin diagrams and signal

descriptions.

• Chapter 4, Registers describes each bit in the operating registers,

and is organized by register address.

• Chapter 5, SCSI SCRIPTS Instruction Set defines all of the SCSI

SCRIPTS instructions that are supported by the LSI53C875A.

Preface iii

• Chapter 6, Electrical Specifications contains the electrical

• Appendix A, Register Summary is a register summary.

• Appendix B,ExternalMemoryInterface Diagram Examples contains

Related Publications

For background information, please contact:

ANSI

11 W est 42nd Street
New York, NY 10036
[phone]
Ask for document number X3.131-199X (SCSI-2)

Global Engineering Documents

15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
Ask for document number X3.131-1994 (SCSI-2); X3.253 (SCSI-3
Parallel Interface)

characteristics and AC timing diagrams.

several example interface drawings for connecting the LSI53C875A
to external ROMs.

ENDL Publications

14426 Black Walnut Court
Saratoga, CA 95070
[phone]
Document names: SCSI Bench Reference, SCSI Encyclopedia,

SCSI Tutor

Prentice Hall

113 Sylvan Avenue
Englewood Cliffs, NJ 07632
[phone]
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding

the Small Computer System Interface

LSI Logic World Wide Web Home Page

www.lsilogic.com

iv Preface

PCI Special Interest Group

2575 N.E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]

Conventions Used in This Manual

The word assert means to drive a signal true or active . The word
deassert means to drive a signal false or inactive.

Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.

Revision Record

Revision Date Remarks

Preliminary 5/00 Preliminary draft version of the manual.

1.0 6/00 Preliminary version of the manual.

2.0 12/00 Final version of the manual.

Preface v

vi Preface

Contents

Chapter 1 General Description

1.1 New Features in the LSI53C875A 1-3

1.2 Benefits of Ultra SCSI 1-3

1.3 TolerANT

1.4 LSI53C875A Benefits Summary 1-4

1.4.1 SCSI Performance 1-5

1.4.2 PCI Performance 1-6

1.4.3 Integration 1-6

1.4.4 Ease of Use 1-6

1.4.5 Flexibility 1-7

1.4.6 Reliability 1-8

1.4.7 Testability 1-8

®

Technology 1-4

Chapter 2 Functional Description

2.1 PCI Functional Description 2-2

2.1.1 PCI Addressing 2-2

2.1.2 PCI Bus Commands and Functions Supported 2-3

2.1.3 PCI Cache Mode 2-9

2.2 SCSI Functional Description 2-16

2.2.1 SCRIPTS Processor 2-17

2.2.2 Internal SCRIPTS RAM 2-18

2.2.3 64-Bit Addressing in SCRIPTS 2-19

2.2.4 Hardware Control of SCSI Activity LED 2-19

2.2.5 Designing an Ultra SCSI System 2-20

2.2.6 Prefetching SCRIPTS Instructions 2-21

2.2.7 Opcode Fetch Burst Capability 2-22

2.2.8 Load and Store Instructions 2-22

2.2.9 JTAG Boundary Scan Testing 2-23

2.2.10 SCSI Loopback Mode 2-23

Contents vii

2.2.11 Parity Options 2-24

2.2.12 DMA FIFO 2-27

2.2.13 SCSI Bus Interface 2-32

2.2.14 Select/Reselect During Selection/Reselection 2-33

2.2.15 Synchronous Operation 2-34

2.2.16 Interrupt Handling 2-37

2.2.17 Chained Block Moves 2-44

2.3 Parallel ROM Interface 2-48

2.4 Serial EEPROM Interface 2-50

2.4.1 Default Download Mode 2-50

2.4.2 No Download Mode 2-51

2.5 Power Management 2-51

2.5.1 Power State D0 2-52

2.5.2 Power State D1 2-52

2.5.3 Power State D2 2-53

2.5.4 Power State D3 2-53

Chapter 3 Signal Descriptions

3.1 LSI53C875A Functional Signal Grouping 3-2

3.2 Signal Descriptions 3-3

3.2.1 Internal Pull-ups on LSI53C875A Signals 3-3

3.3 PCI Bus Interface Signals 3-4

3.3.1 System Signals 3-4

3.3.2 Address and Data Signals 3-5

3.3.3 Interface Control Signals 3-6

3.3.4 Arbitration Signals 3-7

3.3.5 Error Reporting Signals 3-7

3.3.6 Interrupt Signal 3-8

3.4 SCSI Bus Interface Signals 3-8

3.4.1 SCSI Bus Interface Signal 3-8

3.4.2 SCSI Signals 3-9

3.4.3 SCSI Control Signals 3-9

3.5 GPIO Signals 3-10

3.6 ROM Flash and Memory Interface Signals 3-11

3.7 Test Interface Signals 3-12

3.8 Power and Ground Signals 3-13

3.9 MAD Bus Programming 3-14

viii Contents

Chapter 4 Registers

4.1 PCI Configuration Registers 4-1

4.2 SCSI Registers 4-18

4.3 64-Bit SCRIPTS Selectors 4-99

4.4 Phase Mismatch Jump Registers 4-103

Chapter 5 SCSI SCRIPTS Instruction Set

5.1 Low Level Register Interface Mode 5-1

5.2 High Level SCSI SCRIPTS Mode 5-2

5.2.1 Sample Operation 5-3

5.3 Block Move Instruction 5-6

5.3.1 First Dword 5-6

5.3.2 Second Dword 5-13

5.4 I/O Instruction 5-13

5.4.1 First Dword 5-14

5.4.2 Second Dword 5-21

5.5 Read/Write Instructions 5-22

5.5.1 First Dword 5-22

5.5.2 Second Dword 5-23

5.5.3 Read-Modify-Write Cycles 5-23

5.5.4 Move To/From SFBR Cycles 5-24

5.6 Transfer Control Instructions 5-25

5.6.1 First Dword 5-26

5.6.2 Second Dword 5-32

5.7 Memory Move Instructions 5-32

5.7.1 First Dword 5-33

5.7.2 Read/Write System Memory from SCRIPTS 5-34

5.7.3 Second Dword 5-34

5.7.4 Third Dword 5-35

5.8 Load and Store Instructions 5-35

5.8.1 First Dword 5-36

5.8.2 Second Dword 5-37

Chapter 6 Electrical Specifications

6.1 DC Characteristics 6-1

6.2 TolerANT Technology Electrical Characteristics 6-5

Contents ix

6.3 AC Characteristics 6-9

6.4 PCI and External Memory Interface Timing Diagrams 6-11

6.4.1 Target Timing 6-13

6.4.2 Initiator Timing 6-19

6.4.3 External Memory Timing 6-35

6.5 SCSI Timing Diagrams 6-52

6.6 Package Diagrams 6-58

Appendix A Register Summary

Appendix B External Memory Interface Diagram Examples

Index

Customer Feedback

Figures

1.1 Typical LSI53C875A System Application 1-2

1.2 Typical LSI53C875A Board Application 1-2

2.1 LSI53C875A Block Diagram 2-2

2.2 Parity Checking/Generation 2-27

2.3 DMA FIFO Sections 2-28

2.4 LSI53C875A Host Interface SCSI Data Paths 2-29

2.5 Regulated Termination for Ultra SCSI 2-33

2.6 Determining the Synchronous Transfer Rate 2-35

2.7 Block Move and Chained Block Move Instructions 2-45

3.1 LSI53C875A Functional Signal Grouping 3-2

5.1 SCRIPTS Overview 5-5

6.1 Rise and Fall Time Test Condition 6-7

6.2 SCSI Input Filtering 6-7

6.3 Hysteresis of SCSI Receivers 6-7

6.4 Input Current as a Function of Input Voltage 6-8

6.5 Output Current as a Function of Output Voltage 6-8

6.6 External Clock 6-9

6.7 Reset Input 6-10

6.8 Interrupt Output 6-11

xContents

6.9 PCI Configuration Register Read 6-13

6.10 PCI Configuration Register Write 6-14

6.11 32-Bit Operating Register/SCRIPTS RAM Read 6-15

6.12 64-Bit Address Operating Register/SCRIPTS RAM Read 6-16

6.13 32-Bit Operating Register/SCRIPTS RAM Write 6-17

6.14 64-Bit Address Operating Register/SCRIPTS RAM Write 6-18

6.15 Nonburst Opcode Fetch, 32-Bit Address and Data 6-20

6.16 Burst Opcode Fetch, 32-Bit Address and Data 6-22

6.17 Back-to-Back Read, 32-Bit Address and Data 6-24

6.18 Back-to-Back Write, 32-Bit Address and Data 6-26

6.19 Burst Read, 32-Bit Address and Data 6-28

6.20 Burst Read, 64-Bit Address and Data 6-30

6.21 Burst Write, 32-Bit Address and Data 6-32

6.22 Burst Write, 64-Bit Address and 32-Bit Data 6-34

6.23 External Memory Read 6-36

6.24 External Memory Write 6-40

6.25 Normal/Fast Memory (

≥ 128 Kbytes) Single Byte

Access Read Cycle 6-42

6.26 Normal/Fast Memory (

≥ 128 Kbytes) Single Byte

Access Write Cycle 6-43

6.27 Normal/Fast Memory (

≥ 128 Kbytes) Multiple Byte

Access Read Cycle 6-44

6.28 Normal/Fast Memory (

≥ 128 Kbytes) Multiple Byte

Access Write Cycle 6-46

6.29 Slow Memory (

6.30 Slow Memory (

6.31

6.32

≤ 64 Kbytes ROM Read Cycle 6-50
≤ 64 Kbyte ROM Write Cycle 6-51

≤ 128 Kbytes) Read Cycle 6-48
≤ 128 Kbytes) Write Cycle 6-49

6.33 Initiator Asynchronous Send 6-52

6.34 Initiator Asynchronous Receive 6-53

6.35 Target Asynchronous Send 6-54

6.36 Target Asynchronous Receive 6-55

6.37 Initiator and T arget Synchronous Transfer 6-57

6.38 LSI53C875A 160-Pin PQFP Mechanical Drawing 6-58

6.39 169-Pin BGA Mechanical Drawing 6-61
B.1 16KbyteInterfacewith200nsMemory B-1
B.2 64KbyteInterfacewith150nsMemory B-2

Contents xi

Tables

B.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte

Interface with 150 ns Memory B-3

B.4 512 Kbyte Interface with 150 ns Memory B-4

2.1 PCI Bus Commands and Encoding Types for the
LSI53C875A 2-4

2.2 PCI Cache Mode Alignment 2-12

2.3 Bits Used for Parity Control and Generation 2-25

2.4 SCSI Parity Control 2-26

2.5 SCSI Parity Errors and Interrupts 2-26

2.6 Parallel ROM Support 2-49

2.7 Mode A Serial EEPROM Data Format 2-51

2.8 Power States 2-52

3.1 LSI53C875A Internal Pull-ups 3-3

3.2 System Signals 3-4

3.3 Address and Data Signals 3-5

3.4 Interface Control Signals 3-6

3.5 Arbitration Signals 3-7

3.6 Error Reporting Signals 3-7

3.7 Interrupt Signal 3-8

3.8 SCSI Bus Interface Signal 3-8

3.9 SCSI Signals 3-9

3.10 SCSI Control Signals 3-9

3.11 GPIO Signals 3-10

3.12 ROM Flash and Memory Interface Signals 3-11

3.13 Test Interface Signals 3-12

3.14 Power and Ground Signals 3-13

3.15 Decode of MAD Pins 3-14

4.1 PCI Configuration Register Map 4-2

4.2 SCSI Register Address Map 4-19

4.3 Examples of Synchronous Transfer Periods and Rates
for SCSI-1 4-32

4.4 Example Transfer Periods and Rates for Fast SCSI-2
and Ultra SCSI 4-33

4.5 Maximum Synchronous Offset 4-34

4.6 SCSI Synchronous Data FIFO Word Count 4-44

5.1 SCRIPTS Instructions 5-3

xii Contents

5.2 SCSI Information Transfer Phase 5-12

5.3 Read/Write Instructions 5-24

5.4 Transfer Control Instructions 5-26

5.5 SCSI Phase Comparisons 5-29

6.1 Absolute Maximum Stress Ratings 6-2

6.2 Operating Conditions 6-2

6.3 Input Capacitance 6-2

6.4 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/,
MWE/ 6-3

6.5 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/,
GPIO[2:4] 6-3

6.6 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR 6-4

6.7 Input Signals—CLK, GNT/, IDSEL, RST/, SCLK, TCK,
TDI, TEST_HSC, TEST_RST, TMS, TRST/ 6-4

6.8 Output Signal—TDO 6-4

6.9 Output Signals—IRQ/, MAC/_TESTOUT, REQ/ 6-5

6.10 Output Signal—SERR/ 6-5

6.11 TolerANT Technology Electrical Characteristics for SE
SCSI Signals 6-6

6.12 External Clock 6-9

6.13 Reset Input 6-10

6.14 Interrupt Output 6-10

6.15 PCI Configuration Register Read 6-13

6.16 PCI Configuration Register Write 6-14

6.17 32-Bit Operating Register/SCRIPTS RAM Read 6-15

6.18 64-Bit Address Operating Register/SCRIPTS RAM Read 6-16

6.19 32-Bit Operating Register/SCRIPTS RAM Write 6-17

6.20 64-Bit Address Operating Register/SCRIPTS RAM Write 6-18

6.21 Nonburst Opcode Fetch, 32-Bit Address and Data 6-19

6.22 Burst Opcode Fetch, 32-Bit Address and Data 6-21

6.23 Back-to-Back Read, 32-Bit Address and Data 6-23

6.24 Back-to-Back Write, 32-Bit Address and Data 6-25

6.25 Burst Read, 32-Bit Address and Data 6-27

6.26 Burst Read, 64-Bit Address and Data 6-29

6.27 Burst Write, 32-Bit Address and Data 6-31

6.28 Burst Write, 64-Bit Address and 32-Bit Data 6-33

6.29 External Memory Read 6-35

Contents xiii

6.30 External Memory Write 6-38

6.31 Normal/Fast Memory (

≥ 128 Kbytes) Single Byte

Access Read Cycle 6-42

6.32 Normal/Fast Memory (

≥ 128 Kbytes) Single Byte

Access Write Cycle 6-43

6.33 Slow Memory (

≤ 128 Kbytes) Read Cycle 6-48

6.34 Slow Memory (≤ 128 Kbytes) Write Cycle 6-49

6.35

6.36

≤= 64 Kbytes ROM Read Cycle 6-50
≤ 64 Kbyte ROM Write Cycle 6-51

6.37 Initiator Asynchronous Send 6-52

6.38 Initiator Asynchronous Receive 6-53

6.39 Target Asynchronous Send 6-54

6.40 Target Asynchronous Receive 6-55

6.41 SCSI-1 Transfers (5.0 Mbytes) 6-55

6.42 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or

20.0 Mbytes (16-Bit Transfers) 40 MHz Clock 6-56

6.43 Ultra SCSI Transfers 20.0 Mbytes (8-Bit Transfers) or

40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 6-56

6.44 160 PQFP Pin List by Location 6-60

6.45 169 BGA Pin List by Location 6-62

A.1 LSI53C875A PCI Register Map A-1
A.2 LSI53C875A SCSI Register Map A-2

xiv Contents

Chapter 1
General Description

Chapter 1 is divided into the following sections:

• Section 1.1, “New Features in the LSI53C875A”

• Section 1.2, “Benefits of Ultra SCSI”

• Section 1.3, “TolerANT

• Section 1.4, “LSI53C875A Benefits Summary”

The LSI53C875A PCI to Ultra SCSI Controller brings Ultra SCSI
performance to host adapter, workstation, and general computer designs,
making it easy to add a high-performance SCSI bus to any PCI system.
It supports Ultra SCSI transfer rates with Single-Ended (SE) signaling for
SCSI devices.

The LSI53C875A has a local memory bus for local storage of the
device’s BIOS ROM in flash memory or standard EEPROMs. The
LSI53C875A supports programming of local flash memory for updates to
BIOS. Chapter 6, “Electrical Specifications,” has the chip package and
BGA specifications. Appendix B, “External Memory Interface Diagram

Examples,” has system diagrams showing the connections of the

LSI53C875A with an external ROM or flash memory.

®

Technology”

The LSI53C875A integrates a high-perf ormance SCSI core, a 64-bit PCI
bus master DMA core, and the LSI Logic SCSI SCRIPTS™ processor to
meet the flexibility requirements of SCSI-3 and Ultra SCSI standards. It
implements multithreaded I/O algorithms with a minimum of processor
intervention, solving the protocol overhead problems of previous
intelligent and nonintelligent adapter designs.

Figure 1.1 illustrates a typical LSI53C875A system and Figure 1.2

illustrates a typical LSI53C875A board application.

LSI53C875A PCI to Ultra SCSI Controller 1-1

Figure 1.1 Typical LSI53C875A System Application

PCI Bus

Interface

Controller

Processor Bus

Central

Processing

Unit

(CPU)

PCI Bus

Typical PCI

Computer System

Architecture

LSI53C875A

PCItoWideUltra

SCSI Controller

PCI Graphic Accelerator

PCI Fast Ethernet

Memory

Controller

Memory

Figure 1.2 Typical LSI53C875A Board Application

SCSI Bus

Fixed Disk, Optical Disk
Printer, Tape, and Other

Peripherals

SCSI Data,

Parity and

68 Pin

SCSI
Wide

Connector

Control
Signals

PCI Address, Data, Parityand Control Signals

1-2 General Description

LSI53C875A
32 Bit PCI to

SCSI Controller

PCI Interface

Memory

Address/Data

Bus

GPIO[1:0]

Memory Control

Block

Flash EEPROM

Serial EEPROM

1.1 New Features in the LSI53C875A

The LSI53C875A is a drop-in replacement for the LSI53C875 PCI to
Ultra SCSI Controller, with these additional benefits:

• Supports 32-bit PCI Interface with 64-bit addressing.

• Handles SCSI phase mismatches in SCRIPTS without interrupting

the CPU .

• Supports JTAG boundary scanning.

• Supports PC99 Power Management.

– Automatically downloads Subsystem Vendor ID , Subsystem ID,

and PCI power management levels D0, D1, D2, and D3.

• Improves PCI bus efficiency through improved PCI caching design.

• Transfers Load/Store data to or from 4 Kbytes of internal SCRIPTS

RAM.

Additional features of the LSI53C875A include:

• Hardware control of SCSI activity LED.

• 32-bit ISTAT registers (Interrupt Status Zero (ISTAT0), Interrupt

Status One (ISTAT1), Mailbox Zero (MBOX0), Mailbox One
(MBOX1)).

• Optional 944 byte DMA FIFO supports large block transfers at Ultra

SCSI speeds. The default FIFO size of 112 bytes is also supported.

1.2 Benefits of Ultra SCSI

Ultra SCSI is an extension of the SPI-2 draft standard that allows faster
synchronous SCSI transfer rates. When enabled, Ultra SCSI performs
20 megatransfers per second. The LSI53C875A can perf orm 16-bit, Ultra
SCSI synchronous transfers as fast as 40 Mbytes/s. This advantage is
most noticeable in heavily loaded systems or with applications with large
block requirements, such as video on-demand and image processing.

An advantage of Ultra SCSI is that it significantly improves SCSI
bandwidth while preserving existing hardware and software investments.
The primary software changes required enable the chip to perform

New Features in the LSI53C875A 1-3

synchronous negotiations for Ultra SCSI rates and to enable the clock
quadrupler. Chapter 2, “Functional Description,” contains more
information on Ultra SCSI design.

1.3 TolerANT®Technology

The LSI53C875A features TolerANT technology, which includes active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation actively drives the SCSI Request,
Acknowledge, Data, and Parity signals HIGH rather than allowing them
to be passively pulled up by terminators. Active negation is enabled by
setting bit 7 in the SCSI Test Three (STEST3) register.

TolerANT receiver technology improves data integrity in unreliable
cabling environments where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions, without the long signal delay associated with
RC-type input filters. This improved driver and receiver technology helps
eliminate double clocking of data, the single biggest reliability issue with
SCSI operations.

The benefits of TolerANT technology include increased immunity to noise
when the signal is going HIGH, better performance due to balanced duty
cycles, and improvedfastSCSI transfer rates. In addition, TolerANT SCSI
devices do not cause glitches on the SCSI bus at power-up or
power-down, so other devices on the bus are also protected from data
corruption. TolerANT technology is compatible with both the Alternative
One and Alternative Twotermination schemes proposed by the American
National Standards Institute.

1.4 LSI53C875A Benefits Summary

This section of the chapter provides an overview of the LSI53C875A
features and benefits. It contains these topics:

• SCSI Performance

• PCI Performance

• Integration

1-4 General Description

• Ease of Use

• Flexibility

• Reliability

• Testability

1.4.1 SCSI Performance

To improve SCSI performance, the LSI53C875A:

• Has integrated SE transceivers.

• Bursts up to 512 bytes across the PCI bus through its 944 byte FIFO.

• Perf orms wide, Ultra SCSI synchronous transfers as fast as

40 Mbytes/s.

• Can handle phase mismatches in SCRIPTS without interrupting the

system processor, eliminating the need for CPU intervention during
an I/O disconnect/reselect sequence.

• Achieve Ultra SCSI transfer rates with an input frequency of 20 MHz

with the on-chip SCSI clock quadrupler .

• Includes 4 Kbytes internal RAM for SCRIPTS instruction storage.

• Has 31 levels of SCSI synchronous offset.

• Supports variable block size and scatter/gather data transfers.

• Performs sustained memory-to-memory DMA transfers to

approximately 100 Mbytes/s.

• Minimizes SCSI I/O start latency.

• Performs complex bus sequences without interrupts, including

restoring data pointers.

• Reduces ISR overhead through a unique interrupt status reporting

method.

• Uses Load/Store SCRIPTS instructions which increase performance

of data transfers to and from the chip registers without using PCI
cycles.

• Has SCRIPTS support for 64-bit addressing.

• Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast

I/O context switching.

LSI53C875A Benefits Summary 1-5

• Supports additional arithmetic capability with the Expanded Register

Move instruction.

1.4.2 PCI Performance

To improve PCI performance, the LSI53C875A:

• Complies with PCI 2.2 specification.

• Supports 32-bit 33 MHz PCI interface with 64-bit addressing.

• Supports dual address cycles which can be generated for all

SCRIPTS for > 4 Gbyte addressability.

• Bursts 2, 4, 8, 16, 32, 64, or 128 Dword transfers across the PCI bus.

• Supports 32-bit word data bursts with variable burst lengths.

• Prefetches up to 8 Dwords of SCRIPTS instructions.

• Bursts SCRIPTS opcode fetches across the PCI bus.

• Perf orms zero wait-state bus master data bursts faster than

110 Mbytes/s (@ 33 MHz).

• Supports PCI Cache Line Size register.

• Supports PCI Write and Invalidate, Read Line, and Read Multiple

commands.

• Complies with PCI Bus Power Management Specification Rev 1.1.

1.4.3 Integration

Features of the LSI53C875A which ease integration include:

• High-perfor mance SCSI core.

• Integrated SE transceivers.

• Full 32-bit PCI DMA bus master.

• Integrated SCRIPTS processor.

• Memory-to-Memory Move instructions allow use as a third party PCI

bus DMA controller.

1.4.4 Ease of Use

The LSI53C875A provides:

1-6 General Description

1.4.5 Flexibility

• Up to one megabyte of add-in memory support for BIOS and

SCRIPTS storage.

• Reduced SCSI development effort.

• Compiler-compatible with existing LSI53C7XX and LSI53C8XX

family SCRIPTS.

• Direct connection to PCI and SCSI SE.

• Development tools and sample SCSI SCRIPTS available.

• Five GPIO pins.

• Maskable and pollable interrupts.

• Wide SCSI, A or P cable, and up to 15 devices supported.

• Three programmable SCSI timers: Select/Reselect,

Handshake-to-Handshake, and General Purpose. The time-out
period is programmable from 100

µs to greater than 25.6 seconds.

• Software for PC-based operating system support.

• Support for relative jumps.

• SCSI Selected as ID bits for responding with multiple IDs.

The LSI53C875A provides:

• High le vel programming interface (SCSI SCRIPTS).

• Ability to program local and bus flash memory.

• Selectable 112 or 944 byte DMA FIFO for backward compatibility.

• Tailored SCSI sequences execute from main system RAM or internal

SCRIPTS RAM.

• Flexible programming interface to tune I/O performance or to adapt

to unique SCSI devices.

• Support for changes in the logical I/O interface definition.

• Low level access to all registers and all SCSI bus signals.

• Fetch, Master, and Memory Access control pins.

• Separate SCSI and system clocks.

LSI53C875A Benefits Summary 1-7

1.4.6 Reliability

• SCSI clock quadrupler bits enable Ultra SCSI transfer rates with a 20

or 40 MHz SCSI clock input.

• Selectable IRQ pin disable bit.

• Ability to route system clock to SCSI clock.

• Compatible with 3.3 V and 5 V PCI.

Enhanced reliability features of the LSI53C875A include:

• 2 kV ESD protection on SCSI signals.

• Protection against bus reflections due to impedance mismatches.

• Controlled bus assertion times (reduces RFI, improves reliability, and

eases FCC certification).

• Latch-up protection greater than 150 mA.

• Voltage feed-through protection (minimum leakage current through

SCSI pads).

• High proportion (> 25%) of device pins are power or ground.

• Power and ground isolation of I/O pads and internal chip logic.

• TolerANT technology, which provides:

– Active negation of SCSI Data, Parity, Request, and Acknowledge

signals for improved fast SCSI transfer rates.

– Input signal filtering on SCSI receivers improves data integrity,

even in noisy cabling environments.

1.4.7 Testability

The LSI53C875A provides improved testability through:

• Access to all SCSI signals through programmed I/O.

• SCSI loopback diagnostics.

• SCSI bus signal continuity checking.

• Support for single step mode operation.

• JTAG boundary scan.

1-8 General Description

Chapter 2
Functional Description

Chapter 2 is divided into the following sections:

• Section 2.1, “PCI Functional Description”

• Section 2.2, “SCSI Functional Description”

• Section 2.3, “Parallel ROM Interface”

• Section 2.4, “Serial EEPROM Interface”

• Section 2.5, “Power Management”

The LSI53C875A PCI to Ultra SCSI Controller is composed of the
following modules:

• 32-bit PCI Interface with 64-bit addressing

• PCI-to-Wide Ultra SCSI Controller

• ROM/Flash Memory Controller

• Serial EEPROM Controller

Figure 2.1 illustrates the relationship between these modules.

LSI53C875A PCI to Ultra SCSI Controller 2-1

Figure 2.1 LSI53C875A Block Diagram

PCI Bus

32 Bit PCI Interface, PCI Configuration Register

Wide Ultra SCSI Controller

4Kbyte

SCRIPTS RAM

944 byte

DMA FIFO

SCSI FIFO and SCSI Control Block

JTAG

JTAG Bus WideUltra

SCSI SCRIPTS

Processor

8 Dword SCRIPTS

Prefetch Buffer

Operating
Registers

SE TolerANT

Drivers and Receivers

SCSI Bus

2.1 PCI Functional Description

ROM/Flash Serial EEPROM

Memory

Control

Local

Memory

Bus

ROM/Flash

Memory Bus

Controller and

Autoconfiguration

2-Wire Serial

EEPROM Bus

The LSI53C875A implements a PCI-to-Wide Ultra SCSI controller.

2.1.1 PCI Addressing

There are three physical PCI-defined address spaces:

• PCI Configuration space.

• I/O space for operating registers.

• Memory space for operating registers.

2-2 Functional Description

2.1.1.1 Configuration Space

The host processor uses the PCI configuration space to initialize the
LSI53C875A through a defined set of configuration space registers. The
Configuration registers are accessible only by system BIOS during PCI
configuration cycles. The configuration space is a contiguous
256 X 8-bit set of addresses. Decoding C_BE[3:0]/ determines if a PCI
cycle is intended to access the configuration register space. The IDSEL
bus signal is a “chip select” that allows access to the configuration
register space only. A configuration read/write cycle without IDSEL is
ignored. The eight lower order address bits, AD[7:0], select a specific
8-bit register. AD[10:8] are decoded as well, but they must be zero or the
LSI53C875A does not respond. According to the PCI specification,
AD[10:8] are reserved for multifunction devices.

At initialization time, each PCI device is assigned a base address for I/O
and memory accesses. In the case of the LSI53C875A, the upper 24 bits
of the address are selected. On every access, the LSI53C875A
compares its assigned base addresses with the value on the
Address/Data bus during the PCI address phase. If the upper 24 bits
match, the access is for the LSI53C875A and the low-order eight bits
define the register being accessed. A decode of C_BE[3:0]/ determines
which registers and what type of access is to be performed.

I/O Space – The PCI specification defines I/O space as a contiguous
32-bit I/O address that is shared by all system resources, including the
LSI53C875A. Base Address Register Zero (I/O) determines which
256-byte I/O area this device occupies.

Memory Space – The PCI specification defines memory space as a
contiguous 64-bit memory address that is shared by all system
resources, including the LSI53C875A. Base Address Register One

(MEMORY) determines which 1 Kbyte memory area this device

occupies. Base Address Register Two (SCRIPTS RAM) determines the
4 Kbyte memory area occupied by SCRIPTS RAM.

2.1.2 PCI Bus Commands and Functions Supported

Bus commands indicate to the target the type of transaction the master
is requesting. Bus commands are encoded on the C_BE[3:0]/ lines
during the address phase. PCI bus commands and encoding types
appear in Table 2.1.

PCI Functional Description 2-3

Table 2.1 PCI Bus Commands and Encoding Types for the LSI53C875A

C_BE[3:0]/ Command Type Supported as Master Supported as Slave

0b0000 Interrupt Acknowledge No No
0b0001 Special Cycle No No
0b0010 I/O Read Yes Yes
0b0011 I/O Write Yes Yes
0b0100 Reserved n/a n/a
0b0101 Reserved n/a n/a
0b0110 Memory Read Yes Yes
0b0111 Memory Write Yes Yes
0b1000 Reserved n/a n/a
0b1001 Reserved n/a n/a
0b1010 Configuration Read No Yes
0b1011 Configuration Write No Yes
0b1100 Memory Read Multiple Yes

1

Yes (defaults to 0b0110)
0b1101 Dual Address Cycle (DAC) Yes No
0b1110 Memory Read Line Yes
0b1111 Memory Write and Invalidate Yes

1. See the DMA Mode (DMODE) register.

2. See the Chip Test Three (CTEST3) register.

1

2

2.1.2.1 Interrupt Acknowledge Command

The LSI53C875A does not respond to this command as a slave and it
never generates this command as a master.

2.1.2.2 Special Cycle Command

The LSI53C875A does not respond to this command as a slave and it
never generates this command as a master.

2-4 Functional Description

Yes (defaults to 0b0110)

Yes (defaults to 0b0111)

2.1.2.3 I/O Read Command

The I/O Read command reads data from an agent mapped in I/O
address space. All 32 address bits are decoded.

2.1.2.4 I/O Write Command

The I/O Write command writes data to an agent mapped in I/O address
space. All 32 address bits are decoded.

2.1.2.5 Reserved Command

The LSI53C875A does not respond to this command as a slave and it
never generates this command as a master.

2.1.2.6 Memory Read Command

The Memory Read command reads data from an agent mapped in the
Memory Address Space. The target is free to do an anticipatory read for
this command only if it can guarantee that such a read has no side
effects.

2.1.2.7 Memory Write Command

The Memory Write command writes data to an agent mapped in the
Memory Address Space. When the target returns “ready,” it assumes
responsibility for the coherency (which includes ordering) of the subject
data.

2.1.2.8 Configuration Read Command

The Configuration Read command reads the configuration space of each
agent. An agent is selected during a configuration access when its
IDSEL signal is asserted and AD[1:0] are 0b00.

2.1.2.9 Configuration Write Command

The Configuration Write command transfers data to the configuration
space of each agent. An agent is selected when its IDSEL signal is
asserted and AD[1:0] are 0b00.

PCI Functional Description 2-5

2.1.2.10 Memory Read Multiple Command

This command is identical to the Memory Read command except that it
additionally indicates that the master may intend to fetch more than one
cache line before disconnecting. The LSI53C875A supports PCI Memory
Read Multiple functionality and issues Memory Read Multiple commands
on the PCI bus when the Read Multiple Mode is enabled. This mode is
enabled by setting bit 2 (ERMP) of the DMA Mode (DMODE) register. If
cache mode is enabled, a Memory Read Multiple command is issued on
all read cycles, except opcode fetches, when the following conditions are
met:

• The CLSE bit (Cache Line Size Enable, bit 7, DMA Control (DCNTL)

register) and the ERMP bit (Enable Read Multiple, bit 2, DMA Mode

(DMODE) register) are set.

• The CacheLineSizeregister for each function contains a legal burst

size value (2, 4, 8, 16, 32, or 64) and that value is less than or equal
to the DMODE burst size.

• The transfer will cross a cache line boundary.

When these conditions are met, the chip issues a Memory Read Multiple
command instead of a Memory Read during all PCI read cycles.

Burst Size Selection – The Read Multiple command reads in multiple
cache lines of data in a single bus ownership. The number of cache lines
to read is a multiple of the cache line size specified in Revision 2.2 of
the PCI specification. The logic selects the largest multiple of the cache
line size based on the amount of data to transfer, with the maximum
allowable burst size determined from the DMA Mode (DMODE) burst size
bits, and the Chip Test Five (CTEST5),bit2.

2.1.2.11 Dual Address Cycle (DAC) Command

The LSI53C875A performs DACs when 64-bit addressing is required.
Refer to the PCI 2.2 specification. If any of the selector registers contain
a nonzero value, a DAC is generated. See 64-bit SCRIPTS Selectors in

Chapter 4, “Registers,” for additional information.

2.1.2.12 Memory Read Line Command

This command is identical to the Memory Read command, except that it
additionally indicates that the master intends to fetch a complete cache

2-6 Functional Description

line. This command is intendedfor use with bulk sequential data transfers
where the memory system and the requesting master might gain some
performance advantage by reading to a cache line boundary rather than
a single memory cycle. The Read Line function in the LSI53C875A takes
advantage of the PCI 2.2 specification regarding issuing this command.

If the cache mode is disabled, Read Line commands are not issued.
If the cache mode is enabled, a Read Line command is issued on all

read cycles, except nonprefetch opcode fetches, when the following
conditions are met:

• The CLSE (Cache Line Size Enable, bit 7, DMA Control (DCNTL)

register) and ERL (Enable Read Line, bit 3, DMA Mode (DMODE)
register) bits are set.

• The Cache Line Size register must contain a legal burst size value

in Dwords (2, 4, 8, 16, 32, 64, or 128) and that value is less than or
equal to the DMA Mode (DMODE) burst size.

• The transfer will cross a Dword boundary but not a cache line

boundary.

When these conditions are met, the chip issues a Read Line command
instead of a Memory Read during all PCI read cycles. Otherwise, it
issues a normal Memory Read command.

Read Multiple with Read Line Enabled – When both the Read Multiple
and Read Line modes are enabled, the Read Line command is not
issued if the above conditions are met. Instead, a Read Multiple
command is issued, even though the conditions for Read Line are met.

If the Read Multiple mode is enabled and the Read Line mode is
disabled, Read Multiple commands are issued if the Read Multiple
conditions are met.

PCI Functional Description 2-7

2.1.2.13 Memory Write and Invalidate Command

The Memory Write and Invalidate command is identical to the Memory
Write command, except that it additionally guarantees a minimum
transfer of one complete cache line; that is to say, the master intends to
write all bytes within the addressed cache line in a single PCI transaction
unless interrupted by the target. This command requires implementation
of the PCI Cache Line Size register at address 0x0C in PCI configuration
space. The LSI53C875A enables Memory Write and Invalidate cycles
when bit 0 (WRIE) in the Chip Test Three (CTEST3) register and bit 4
(WIE) in the PCI Command register are set. When the following
conditions are met, Memory Write and Invalidate commands are issued:

1. The CLSE bit (Cache Line Size Enable, bit 7, DMA Control (DCNTL)
register), WRIE bit (Write and Invalidate Enable, bit 0, Chip Test

Three (CTEST3) register), and PCI configuration Command register,

bit 4 are set.

2. The Cache Line Size register contains a legal burst size value in
Dwords (2, 4, 8, 16, 32, 64, or 128) and that value is less than or
equal to the DMA Mode (DMODE) burst size.

3. The chip has enough bytes in the DMA FIFO to complete at least
one full cache line burst.

4. The chip is aligned to a cache line boundary.

When these conditions are met, the LSI53C875A issues a Memory Write
and Invalidate command instead of a Memory Write command during all
PCI write cycles.

Multiple Cache Line Transfers – The Memory Write and Invalidate
command can write multiple cache lines of data in a single bus
ownership. The chip issues a burst transfer as soon as it reaches a
cache line boundary. The size of the transfer is not automatically the
cache line size, but rather a multiple of the cache line size specified in
Revision 2.2 of the PCI specification. The logic selects the largest
multiple of the cache line size based on the amount of data to transfer,
with the maximum allowable burst size determined from the DMA Mode

(DMODE) burst size bits, and Chip Test Five (CTEST5), bit2.Ifmultiple

cache line size transfers are not desired, set the DMA Mode (DMODE)
burst size to exactly the cache line size and the chip only issues single
cache line transfers.

2-8 Functional Description

After each data transfer, the chip re-evaluates the burst size based on
the amount of remaining data to transfer and again selects the highest
possible multiple of the cache line size, and no larger than the DMA

Mode (DMODE) burst size. The most likely scenario of this scheme is

that the chip selects the DMA Mode (DMODE) burst size after alignment,
and issues bursts of this size. The burst size is, in effect, throttled down
toward the end of a long Memory Move or Block Move transfer until only
the cache line size burst size is left. The chip finishes the transfer with
this burst size.

Latency – In accordance with the PCI specification, the latency timer is
ignored when issuing a Memory Write and Invalidate command such that
when a latency time-out occurs, the LSI53C875A continues to transfer
up to a cache line boundary. At that point, the chip relinquishes the bus,
and finishes the transfer at a later time using another bus ownership. If
the chip is transferring multiple cache lines it continues to transfer until
the next cache boundary is reached.

PCI Target Retry – During a Memory Write and Invalidate transfer, if the
target device issues a retry (STOP with no TRDY/, indicating that no data
was transferred), the chip relinquishes the bus and immediately tries to
finish the transfer on another bus ownership. The chip issues another
Memory Write and Invalidate command on the next ownership, in
accordance with the PCI specification.

PCI Target Disconnect – During a Memory Write and Invalidate
transfer, if the target device issues a disconnect the LSI53C875A
relinquishes the bus and immediately tries to finish the transfer on
another bus ownership. The chip does not issue another Memory Write
and Invalidate command on the next ownership unless the address is
aligned.

2.1.3 PCI Cache Mode

The LSI53C875A supports the PCI specification for an 8-bit Cache Line

Size register located in the PCI configuration space. The Cache Line
Size register provides the ability to sense and react to nonaligned

addresses corresponding to cache line boundaries. In conjunction with
the CacheLineSizeregister, the PCI commands Memory Read Line,
Memory Read Multiple, and Memory Write and Invalidate are each

PCI Functional Description 2-9

software enabled or disabled to allow the user full flexibility in using these
commands.

2.1.3.1 Enabling Cache Mode

In order to enable the cache logic to issue PCI cache commands
(Memory Read Line, Memory Read Multiple, and Memory Write and
Invalidate) on any given PCI master operation the following conditions
must be met:

• The Cache Line Size Enable bit in the DMA Control (DCNTL) register

must be set.

• The PCI CacheLineSizeregister must contain a valid binary cache

size, i.e. 2, 4, 8, 16, 32, 64, or 128 Dwords. Only these values are
considered valid cache sizes.

• The programmed burst size (in Dwords) must be equal to or greater

than the CacheLineSizeregister. The DMA Mode (DMODE) register
bits [7:6] and Chip Test Five (CTEST5) bit 2 are the burst length bits.

• The part must be doing a PCI Master transfer. The following PCI

Master transactions do not utilize the PCI cache logic and thus no
PCI cache command is issued during these types of cycles: a
nonprefetch SCRIPTS fetch, a Load/Store data transfer, or a data
flush operation. All other types of PCI Master transactions will utilize
the PCI cache logic.

The above conditions must be met for the cache logic to control the type
of PCI cache command that is issued, along with any alignment that may
be necessary during write operations. If these conditions are not met for
any given PCI Master transaction, a Memory Read or Memory Write is
issued and no cache write alignment is done.

2.1.3.2 Issuing Cache Commands

In order to issue each type of PCI cache command, the corresponding
enable bit must be set (2 bits in the case of Memory Write and
Invalidate). These bits are detailed below:

• To issue Memory Read Line commands, the Read Line enable bit in

the DMA Mode (DMODE) register must be set.

2-10 Functional Description

• To issue Memory Read Multiple commands, the Read Multiple

enable bit in the DMA Mode (DMODE) register must be set.

• To issue Memory Write and Invalidate commands, both the Write and

Invalidate enables in the Chip Test Three (CTEST3) register and the
PCI configuration command register must be set.

If the corresponding cache command being issued is not enabled then
the cache logic falls back to the next command enabled. Specifically, if
Memory Read Multiple is not enabled and Memory Read Lines are, read
lines are issued in place of read multiple. If no cache commands are
enabled, cache write alignment still occurs but no cache commands are
issued, only memory reads and memory writes.

2.1.3.3 Memory Read Caching

The type of Memory Read command issued depends on the starting
location of the transfer and the number of bytes being transferred. During
reads, no cache alignment is done (this is not required nor optimal per
PCI 2.2 specification) and reads will always be either a programmed
burst length in size, as set in the DMA Mode (DMODE) and Chip Test

Three (CTEST3) registers. In the case of a transfer which is smaller than

the burst length, all bytes for that transfer are read in one PCI burst
transaction. If the transfer will cross a Dword boundary (A[1:0] = 0b00) a
Memory Read Line command is issued. When the transfer will cross a
cache boundary (depends on cache line size programmed into the PCI
configuration register), a Memory Read Multiple command is issued. If a
transfer will not cross a Dword or cache boundary or if cache mode is
not enabled a Memory Read command is issued.

2.1.3.4 Memory Write Caching

Writes are aligned in a single burst transfer to get to a cache boundary.
At that point, Memory Write and Invalidate commands are issued and
continue at the burst length programmed into the DMA Mode (DMODE)
register. Memory Write and Invalidate commands are issued as long as
the remaining byte count is greater than the Memory Write and Invalidate
threshold. When the byte count goes below this threshold, a single
Memory Write burst is issued to complete the transfer. The general
pattern for PCI writes is:

• A single Memory Write to align to a cache boundary.

PCI Functional Description 2-11

• Multiple Memory Write and Invalidates.

• A single data residual Memory Write to complete the transfer.

Table 2.2 describes PCI cache mode alignment.

Table 2.2 PCI Cache Mode Alignment

Host Memory

A00h

B04h

08h
C0Ch
D10h

14h

18h

1Ch

E20h

24h

28h

G40h

H50h

2-12 Functional Description

2Ch

F30h

34h

38h

3Ch

44h

48h

4Ch

54h

58h

5Ch

60h

2.1.3.5 Examples:

MR = Memory Read, MRL = Memory Read Line, MRM = Memory Read
Multiple, MW = Memory Write, MWI = Memory Write and Invalidate.

Read Example 1 –

Burst=4Dwords,CacheLineSize=4Dwords:

AtoB: MRL(6bytes)
AtoC: MRL (13 bytes)
AtoD: MRL (15 bytes)

CtoD: MRM (5 bytes)
CtoE: MRM (15 bytes)

DtoF: MRL (15 bytes)

AtoH: MRL (15 bytes)

AtoG: MRL (15 bytes)

MR (2 bytes)

MRM (6 bytes)

MRL (16 bytes)
MR (1 byte)

MRL (16 bytes)
MRL (16 bytes)
MRL (16 bytes)
MRL (16 bytes)
MR (2 bytes)

MRL (16 bytes)
MRL (16 bytes)
MRL (16 bytes)
MR (3 bytes)

Read Example 2 –

Burst=8Dwords,CacheLineSize=4Dwords:

AtoB: MRL(6bytes)
AtoC: MRL (13 bytes)
AtoD: MRM (17 bytes)
CtoD: MRM (5 bytes)

PCI Functional Description 2-13

CtoE: MRM (21 bytes)
DtoF: MRM (31 bytes)

MR (1 byte)

AtoH: MRM (31 bytes)

AtoG: MRM (31 bytes)

MRM (32 bytes)
MRM (18 bytes)

MRM (32 bytes)
MR (3 bytes)

Read Example 3 –

Burst = 16 Dwords, Cache Line Size = 8 Dwords:

AtoB: MRL(6bytes)
AtoC: MRL (13 bytes)
AtoD: MRL (17 bytes)
CtoD: MRL(5bytes)
CtoE: MRM (21 bytes)
DtoF: MRM (32 bytes)
AtoH: MRM (63 bytes)

MRL (16 bytes)
MRM (2 bytes)

AtoG: 2 transfers, MRM (63 bytes), MR (3 bytes)

Write Example 1 –

Burst=4Dwords,CacheLineSize=4Dwords:

AtoB: MW (6 bytes)
AtoC: MW (13 bytes)
AtoD: MW (17 bytes)
CtoD: MW (5 bytes)
CtoE: MW (3 bytes)

MWI (16 bytes)
MW (2 bytes)

2-14 Functional Description

DtoF: MW (15 bytes)

MWI (16 bytes)
MW (1 byte)

AtoH: MW (15 bytes)

AtoG: MW (15 bytes)

MWI (16 bytes)
MWI (16 bytes)
MWI (16 bytes)
MWI (16 bytes)
MW (2 bytes)

MWI (16 bytes)
MWI (16 bytes)
MWI (16 bytes)
MW (3 bytes)

Write Example 2 –

Burst=8Dwords,CacheLineSize=4Dwords:

AtoB: MW (6 bytes)
AtoC: MW (13 bytes)
AtoD: MW (17 bytes)
CtoD: MW (5 bytes)
CtoE: MW (3 bytes)

MWI (16 bytes)
MW (2 bytes)

DtoF: MW (15 bytes)

MWI (16 bytes)
MW (1 byte)

AtoH: MW (15 bytes)

MWI (32 bytes)
MWI (32 bytes)
MW (2 bytes)

AtoG: MW (15 bytes)

PCI Functional Description 2-15

MWI (32 bytes)
MWI (16 bytes)
MW (3 bytes)

Write Example 3 –

Burst = 16 Dwords, Cache Line Size = 8 Dwords:

AtoB: MW (6 bytes)
AtoC: MW (13 bytes)
AtoD: MW (17 bytes)
CtoD: MW (5 bytes)
CtoE: MW (21 bytes)
DtoF: MW (32 bytes)
AtoH: MW (15 bytes)

AtoG: MW (15 bytes)

MWI (64 bytes)
MW (2 bytes)

MWI (32 bytes)
MW (18 bytes)

2.1.3.6 Memory-to-Memory Moves

Memory-to-Memory Moves also support PCI cache commands, as
described above, with one limitation. Memory Write and Invalidate on
Memory-to-Memory Move writes are only supported if the source and
destination address are quad word aligned. If the source and destination
are not quad word aligned (that is, Source address [2:0] == Destination
Address [2:0]), write aligning is not performed and Memory Write and
Invalidate commands are not issued. The LSI53C875A is little endian
only.

2.2 SCSI Functional Description

The LSI53C875A provides an Ultra SCSI controller that supports an
8-bit or 16-bit bus. The controller supports Wide Ultra SCSI synchronous
transfer rates up to 40Mbytes/s. The SCSI core can be programmed with
SCSI SCRIPTS, making it easy to “fine tune” the system for specific
mass storage devices or Ultra SCSI requirements.

The LSI53C875A offers low level register access or a high-level control
interface. Like first generation SCSI devices, the LSI53C875A is

2-16 Functional Description

accessed as a register-oriented device. Error recovery and/or diagnostic
procedures use the ability to sample and/or assert any signal on the
SCSI bus. In support of SCSI loopback diagnostics, the SCSI core may
perform a self-selection and operate as both an initiator and a target.

The LSI53C875A is controlled by the integrated SCRIPTS processor
through a high-level logical interface. Commands controlling the SCSI
core are fetched out of the main host memory or local memory. These
commands instruct the SCSI core to Select, Reselect, Disconnect, Wait
for a Disconnect, Transfer Information, Change Bus Phases and, in
general, implement all aspects of the SCSI protocol. The SCRIPTS
processor is a special high-speed processor optimized for SCSI protocol.

2.2.1 SCRIPTS Processor

The SCSI SCRIPTS processor allows both DMA and SCSI commands
to be fetched from host memory or internal SCRIPTS RAM. Algorithms
written in SCSI SCRIPTS control the actions of the SCSI and DMA
cores. The SCRIPTS processor executes complex SCSI bus sequences
independently of the host

Algorithms may be designed to tune SCSI bus performance, to adjust to
new bus device types (such as scanners, communication gateways, etc.),
or to incorporate changes in the SCSI-2 or SCSI-3 logical bus definitions
without sacrificing I/O performance. SCSI SCRIPTS are hardware
independent, so they can be used interchangeably on any host or CPU
system bus. SCSI SCRIPTS handle conditions like Phase Mismatch.

= CPU.

2.2.1.1 Phase Mismatch Handling in SCRIPTS

The LSI53C875A can handle phase mismatches due to drive
disconnects without needing to interrupt the processor. The primary goal
of this logic is to completely eliminate the need for CPU intervention
during an I/O disconnect/reselect sequence.

Storing the appropriate information to later restart the I/O can be done
through SCRIPTS, eliminating the need for processor intervention during
an I/O disconnect/reselect sequence. Calculations are performed such
that the appropriate information is av ailable to SCRIPTS so that an I/O
state can be properly stored for restart later.

SCSI Functional Descr i ption 2-17

The Phase Mismatch Jump logic powers up disabled and must be
enabled by setting the Phase Mismatch Jump Enable bit (ENPMJ, bit 7
in the Chip Control 0 (CCNTL0) register).

Utilizing the information supplied in the PhaseMismatchJumpAddress

1(PMJAD1)and Phase Mismatch Jump Address 2 (PMJAD2) registers,

described in Chapter 4, “Registers,” SCRIPTS handles all overhead
involved in a disconnect/reselect sequence with a modest number of
instructions.

2.2.2 Internal SCRIPTS RAM

The LSI53C875A has 4 Kbyte (1024 x 32 bits) of internal, general
purpose RAM. The RAM is designed for SCRIPTS program storage, but
is not limited to this type of information. When the chip fetches SCRIPTS
instructions or Table Indirect information from the internal RAM, these
fetches remain internal to the chip and do not use the PCI bus. Other
types of access to the RAM by the chip, except Load/Store, use the PCI
bus, as if they were external accesses. The SCRIPTS RAM powers up
enabled by default.

The RAM can be relocated by the PCI system BIOS anywhere in the
32-bit address space. The Base Address Register T wo (SCRIPTS RAM)
in the PCI configuration space contains the base address of the internal
RAM. To simplify loading of the SCRIPTS instructions, the base address
of the RAM appears in the Scratch Register B (SCRATCHB) register
when bit 3 of the Chip Test Two (CTEST2) register is set. The RAM is
byte accessible from the PCI bus and is visible to any bus mastering
device on the bus. External accesses to the RAM (by the CPU) follow
the same timing sequence as a standard slave register access, except
that the required target wait-states drop from 5 to 3.

A complete set of development tools is available for writing custom
drivers with SCSI SCRIPTS. For more information on the SCSI SCRIPTS
instructions supported by the LSI53C875A, see Chapter 5, “SCSI

SCRIPTS Instruction Set.”

2-18 Functional Description

2.2.3 64-Bit Addressing in SCRIPTS

The LSI53C875A has a 32-bit PCI interface which provides 64-bit
address capability in the initiator mode.

DACs can be generated for all SCRIPTS operations. There are six
selector registers which hold the upper Dword of a 64-bit address. All but
one of these is static and requires manual loading using a CPU access,
a Load/Store instruction, or a Memory Mov e instruction. One of the
selector registers is dynamic and is used during 64-bit direct block moves
only. All selectors default to zero, meaning the LSI53C875A powers-up
in a state where only Single Address Cycles (SACs) are generated.
When any of the selector registers are written to a nonzero value, DACs
are generated.

Direct, Table Indirect and Indirect Block moves, Memory-to-Memory
Moves, Load and Store instructions, and jumps are all instructions with
64-bit address capability.

Crossing the 4 Gbyte boundary on any one SCRIPTS operation is not
permitted and software needs to take care that any given SCRIPTS
operation will not cross the 4 Gbyte boundary.

2.2.4 Hardware Control of SCSI Activity LED

The LSI53C875A has the ability to control a LED through the GPIO_0
pin to indicate that it is connected to the SCSI bus. Formerly this function
was done by a software driver.

When bit 5 (LED_CNTL) in the General Purpose Pin Control Zero

(GPCNTL0) register is set and bit 6 (Fetch Enable) in the General
Purpose Pin Control Zero (GPCNTL0) register is cleared and the

LSI53C875A is not performing an EEPROM autodownload, then bit 3
(CON) in the Interrupt Status Zero (ISTAT0) register is presented at the
GPIO_0 pin.

The CON (Connected) bit in Interrupt Status Zero (ISTAT0) is set anytime
the LSI53C875A is connected to the SCSI bus either as an initiator or a
target. This will happen after the LSI53C875A has successfully
completed a selection or when it has successfully responded to a
selection or reselection. It will also be set when the LSI53C875A wins
arbitration in low level mode.

SCSI Functional Descr i ption 2-19

2.2.5 Designing an Ultra SCSI System

Since Ultra SCSI is based on existing SCSI standards, it can use existing
driver programs as long as the software is able to negotiate for Ultra
SCSI synchronous transfer rates. Additional software modifications are
needed to take advantage of the new features in the LSI53C875A.

For additional information on Ultra SCSI, refer to the SPI-2 working
document which is available from the SCSI BBS referenced at the
beginning of this manual. Chapter 6, “Electrical Specifications,” contains
Ultra SCSI timing information. In addition to the guidelines in the draft
standard, make the following software and hardware adjustments to
accommodate Ultra SCSI transfers:

• Set the Ultra Enable bit to enable Ultra SCSI transfers.

• Set the TolerANT Enable bit, bit 7 in the SCSI Test Three (STEST3)

register, whenever the Ultra Enable bit is set.

• Do not extend the SREQ/SACK filtering period with SCSI Test Two

(STEST2) bit 1. When the Ultra Enable bit is set, the filtering period

is fixed at 15 ns for Ultra SCSI, regardless of the value of the
SREQ/SACK Filtering bit.

• Use the SCSI clock quadrupler.

A 20 or 40 MHz input must be supplied if using the SCSI clock
quadrupler for an Ultra design.

2.2.5.1 Using the SCSI Clock Quadrupler

The LSI53C875A can quadruple the frequency of a 20 MHz SCSI clock,
allowing the system to perform Ultra SCSI transfers. This option is user
selectable with bit settings in the SCSI Test One (STEST1), SCSI Test

Three (STEST3),andSCSI Control Three (SCNTL3) registers. At

power-on or reset, the quadrupler is disabled and powered down. Follow
these steps to use the clock quadrupler:

Step 1. Set the SCLK Quadrupler Enable bit (SCSI Test One

(STEST1),bit3).

Step 2. Poll bit 5 of the SCSI Test Four (STEST4) register.

The LSI53C875A sets this bit as soon as it locks in the
quadrupled frequency. The frequency lockup takes
approximately 100

2-20 Functional Description

µs.

Step3. HalttheSCSIclockbysettingtheHaltSCSIClockbit(SCSI

Test Three (STEST3),bit5).

Step 4. Set the clock conversion factor using the SCF and CCF fields

in the SCSI Control Three (SCNTL3) register.

Step 5. Set the SCLK Quadrupler Select bit (SCSI Test One (STEST1),

bit 2).

Step 6. Clear the Halt SCSI Clock bit.

2.2.6 Prefetching SCRIPTS Instructions

When enabled by setting the Prefetch Enable bit (bit 5) in the DMA

Control (DCNTL) register, the prefetch logic in the LSI53C875A fetches

8 Dwords of instructions. The prefetch logic automatically determines the
maximum burst size that it can perform, based on the burst length as
determined by the values in the DMA Mode (DMODE) register. If the unit
cannot perform bursts of at least four Dwords, it disables itself. While the
chip is prefetching SCRIPTS instructions, it will use PCI cache
commands Memory Read Line, and Memory Read Multiple, if PCI
caching is enabled.

Note:

The LSI53C875A may flush the contents of the prefetch unit under
certain conditions, listed below, to ensure that the chip always operates
from the most current version of the SCRIPTS instruction. When one of
these conditions apply, the contents of the prefetch unit are automatically
flushed.

This feature is only useful if fetching SCRIPTS instructions
from main memory. Due to the short access time of
SCRIPTS RAM, prefetchingis not necessary when fetching
instructions from this memory.

• On every Memory Move instruction. The Memory Move instruction is

often used to place modified code directly into memor y. To make
sure that the chip executes all recent modifications, the prefetch unit
flushes its contents and loads the modified code every time an
instruction is issued. To avoid inadvertently flushing the prefetch unit
contents, use the No Flush option for all Memory Move operations
that do not modify code within the ne xt 8 Dwords. For more
information on this instruction refer to Chapter 5, “SCSI SCRIPTS

Instruction Set.”

SCSI Functional Descr i ption 2-21

• On every Store instruction. The Store instruction may also be used

to place modified code directly into memory. To avoid inadvertently
flushing the prefetch unit contents use the No Flush option for all
Store operations that do not modify code within the next 8 Dwords.

• On every write to the DMA SCRIPTS Pointer (DSP) register.

• On all Transfer Control instructions when the transfer conditions are

met. This is necessary because the next instruction to execute is not
the sequential next instruction in the prefetch unit.

• WhenthePrefetchFlushbit(DMA Control (DCNTL) register, bit 6)

is set. The unit flushes whenever this bit is set. The bit is self­clearing.

2.2.7 Opcode Fetch Burst Capability

Setting the Burst Opcode Fetch Enable bit (bit 1) in the DMA Mode

(DMODE) register (0x38) causes the LSI53C875A to burst in the first two

Dwords of all instruction fetches. If the instruction is a Memory-to­Memory Move, the third Dword is accessed in a separate ownership. If
the instruction is an indirect type, the additional Dword is accessed in a
subsequent bus ownership. If the instruction is a Tabl e Indirect Block
Move, the chip uses two accesses to obtain the four Dwords required, in
two bursts of two Dwords each.

Note:

This feature is only useful if Prefetching is disabled and
SCRIPTS instructions are fetched from main memory. Due
to the short SCRIPTS RAM access time, burst opcode
fetching is not necessary when fetching instructions from
this memory.

2.2.8 Load and Store Instructions

The LSI53C875A supports the Load and Store instruction type, which
simplifies the movement of data between memory and the internal chip
registers. It also enables the chip to transfer bytes to addresses relative
to the Data Structure Address (DSA) register. Load and Store data
transfers to or from the SCRIPTS RAM will remain internal to the chip
and will not generate PCI bus cycles. While a Load/Store to or from
SCRIPTS RAM is occurring, any external PCI slave cycles that occur are
retried on the PCI bus. This feature can be disabled by setting the DILS
bit in the Chip C ontrol 0 (CCNTL0) register. For more information on the

2-22 Functional Description

Load and Store instructions, refer to Chapter 5, “SCSI SCRIPTS

Instruction Set.”

2.2.9 JTAG Boundary Scan Testing

The LSI53C875A includes support for JTAG boundary scan testing in
accordance with the IEEE 1149.1 specification with one exception, which
is explained in this section. This device accepts all required boundary
scan instructions including the optional CLAMP, HIGH-Z, and IDCODE
instructions.

The LSI53C875A uses an 8-bit instruction register to support all
boundary scan instructions. The data registers included in the device are
the Boundary Data register, the IDCODE register, and the Bypass
register. This device can handle a 10 MHz TCLK frequency for TDO and
TDI.

Due to design constraints, the RST/ pin (system reset) always 3-states
the SCSI pins when it is asserted. Boundary scan logic does not control
this action, and this is not compliant with the specification. There are two
solutions that resolve this issue:

1. Use the RST/ pin as a boundary scan compliance pin. When the pin
is deasserted, the device is boundary scan compliant and when
asserted, the device is noncompliant. To maintain compliance the
RST/pinmustbedrivenHIGH.

2. When RST/ is asserted during boundary scan testing the expected
output on the SCSI pins must be the HIGH-Z condition, and not what
is contained in the boundary scan data registers for the SCSI pin
output cells.

2.2.10 SCSI Loopback Mode

The LSI53C875A loopback mode allows testing of both initiator and
target functions and, in effect, lets the chip communicate with itself.
When the Loopback Enable bit is set in the SCSI Test Two (STEST2)
register, bit 4, the LSI53C875A allows control of all SCSI signals whether
the chip is operating in the initiator or target mode. For more information
on this mode of operation refer to the LSI Logic SCSI SCRIPTS

Processor Programming Guide.

SCSI Functional Descr i ption 2-23

2.2.11 Parity Options

The LSI53C875A implements a flexible parity scheme that allows control
of the parity sense, allows parity checking to be turned on or off, and has
the ability to deliberately send a byte with bad parity over the SCSI bus
to test parity error recovery procedures. Table 2.3 defines the bits that
are involved in parity control and observation. Table 2.4 describes the
parity control function of the Enable Parity Checking and Assert SCSI
Even Parity bits in the SCSI Control One (SCNTL1) register, bit 2.

Table 2.5 describes the options available when a parity error occurs.
Figure 2.2 shows where parity checking is done in the LSI53C875A.

2-24 Functional Description

Table 2.3 Bits Used for Parity Control and Generation

Bit Name Location Description

Assert SATN/ on
Parity Errors

Enable Parity
Checking

Assert Even SCSI
Parity

Disable Halt on
SATN/ or a Parity
Error (Target Mode
Only)

Enable Parity Error
Interrupt

Parity Error SCSI Interrupt

Status of SCSI
Parity Signal

SCSI SDP1 Signal SCSI Status Two

Latched SCSI Parity SSTAT 2, Bit 3 and

SCSI Control Zero
(SCNTL0),Bit1

SCSI Control Zero
(SCNTL0),Bit3

SCSI Control One
(SCNTL1),Bit2

SCSI Control One
(SCNTL1),Bit5

SCSI Interrupt
Enable Zero
(SIEN0),Bit0

Status Zero
(SIST0),Bit0

SCSI Status Zero
(SSTAT0),Bit0

(SSTAT2),Bit0

SCSI Status One
(SSTAT1),Bit3

Causes the LSI53C875A to automatically assert SATN/
when it detects a SCSI parity error while operating as an
initiator.

Enables the LSI53C875A to check for parity errors. The
LSI53C875A checks for odd parity.

Determines the SCSI parity sense generated by the
LSI53C875A to the SCSI bus.

Causes the LSI53C875A not to halt operations when a
parity error is detected in target mode.

Determines whether the LSI53C875A generates an
interrupt when it detects a SCSI parity error.

This status bit is set whenever the LSI53C875A detects a
parity error on the SCSI bus.

This status bit represents the active HIGH current state of
the SCSI SDP0 parity signal.

This bit represents the active HIGH current state of the
SCSI SDP1 parity signal.

These bits reflect the SCSI odd parity signal
corresponding to the data latched into the SCSI Input

Data Latch (SIDL) register.

Master Parity Error
Enable

Master Data Parity
Error

Master Data Parity
Error Interrupt
Enable

Chip Test Four
(CTEST4),Bit3

DMA Status
(DSTAT),Bit6

DMA Interrupt
Enable (DIEN),

Bit 6

SCSI Functional Descr i ption 2-25

Enables parity checking during PCI master data phases.

Set when the LSI53C875A
target device signaling a parity error during a data phase.

By clearing this bit, a Master Data Parity Error does not
cause assertion of INTA/ (or INTB/), but the status bit is
set in the DMA Status (DSTAT) register.

, as a PCI master, detects a

Table 2.4 SCSI Parity Control

EPC

1

ASEP

2

Description

0 0 Does not check for parity errors. Parity is generated when sending

SCSI data. Asserts odd parity when sending SCSI data.

0 1 Does not check for parity errors. Parity is generated when sending

SCSI data. Asserts even parity when sending SCSI data.

1 0 Checks forodd parity on SCSI data received. Parity is generated when

sending SCSI data. Asserts odd parity when sending SCSI data.

1 1 Checks forodd parity on SCSI data received. Parity is generated when

sending SCSI data. Asserts even parity when sending SCSI data.

1. EPC = Enable Parity Checking (bit 3 SCSI Control Zero (SCNTL0)).

2. ASEP = Assert SCSI Even Parity (bit 2 SCSI Control One (SCNTL1)).

Table 2.5 SCSI Parity Errors and Interrupts

1

DHP

0 0 Halts when a parity erroroccurs in the target or initiatormodeand does

0 1 Halts when a parity error occurs in the target mode and generates an

PAR

2

Description

NOT generate an interrupt.

interrupt in the target or initiator mode.

1 0 Does not halt in target mode when a parity error occurs until the end

of the transfer. An interrupt is not generated.

1 1 Does not halt in target mode when a parity error occurs until the end

of the transfer. An interrupt is generated.

1. DHP = Disable Halt on SATN/ or Parity Error (bit 5 SCSI Control One (SCNTL1)).

2. PAR = Parity Error (bit 0 SCSI Interrupt Enable Zero (SIEN0)).

2-26 Functional Description

Figure 2.2 Parity Checking/Generation

Asynchronous

SCSI Send

PCI Interface**

X

DMA FIFO*

(64 bits X 118)

SODL Register*

S

SCSI Interface**

X = Check parity
G = Generate 32-bit even PCI parity
S = Generate 8-bit odd SCSI parity

Asynchronous

SCSI Receive

PCI Interface**

DMA FIFO*

(64 bits X 118)

SIDL Register*

SCSI Interface**

2.2.12 DMA FIFO

Synchronous

SCSI Send

PCI Interface**

G

(64 bits X 118)

SODL Register*

X

SODR Register* SCSI Interface**

SCSI Interface**

X

DMA FIFO*

S

Synchronous

SCSI Receive

PCI Interface**

G

DMA FIFO*

(64 bits X 118)

X

SCSI FIFO**

(8 or 16 bits x 31)

X

* = No parity protection
** = Parity protected

The DMA FIFO is 8 bytes wide by 118 transfers deep. The DMA FIFO is
illustrated in Figure 2.3. The default DMA FIFO size is 112 bytes to
assure compatibility with older products in the LSI53C8XX family.

The DMA FIFO size may be set to 944 bytes by setting the DMA FIFO
Size bit, bit 5, in the Chip Test Five (CTEST5) register.

SCSI Functional Descr i ption 2-27

Figure 2.3 DMA FIFO Sections

8 Bytes Wide

.

.

.

118

Transfers

Deep

8Bits

Byte Lane 7

2.2.12.1 Data Paths

8Bits

Byte Lane 6

8Bits

Byte Lane 5

8Bits

Byte Lane 4

8Bits

Byte Lane 3

8Bits

Byte Lane 2

8Bits

Byte Lane 1

8Bits

Byte Lane 0

The LSI53C875A automatically supports misaligned DMA transfers. A
944-byte FIFO allows the LSI53C875A to support 2, 4, 8, 16, 32, 64, or
128 Dword bursts across the PCI bus interface.

The data path through the LSI53C875A is dependent on whether data is
being moved into or out of the chip, and whether SCSI data is being
transferred asynchronously or synchronously.

Figure 2.4 shows how data is moved to/from the SCSI bus in each of the

different modes.

.

.

.

2-28 Functional Description

Figure 2.4 LSI53C875A Host Interface SCSI Data Paths

Asynchronous

SCSI Send

PCI Interface**

DMA FIFO*

(8 Bytes x 118)

SODL Register*

SCSI Interface**

Asynchronous

SCSI Receive

PCI Interface**

DMA FIFO*

(8 Bytes x 118)

SWIDE Register

SIDL Register*

SCSI Interface**

Synchronous

SCSI Send

PCI Interface**

DMA FIFO*

(8 Bytes x 118)

SODL Register*

SODR Register* SCSI Interface**

SCSI Interface**

Synchronous

SCSI Receive

PCI Interface**

DMA FIFO*

(8 Bytes x 118)

SCSI FIFO**

(1 or 2 Bytes x 31)

* = No parity protection

** = Parity protected

SWIDE Register

The following steps determine if any bytes remain in the data path when
the chip halts an operation:

Asynchronous SCSI Send –

Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Chip Test

Five (CTEST5) register cleared), look at the DMA FIFO
(DFIFO) and DMA Byte Counter (DBC) registers and calculate

if there are bytes left in the DMA FIFO. To makethis calculation,
subtract the seven least significant bits of the DBC register from
the 7-bit value of the DFIFO register. AND the result with 0x7F
for a byte count between zero and 112.

If the DMA FIFO size is set to 944 bytes (bit 5 of the Chip Test

Five (CTEST5) register is set), subtract the 10 least significant

SCSI Functional Descr i ption 2-29

bits of the DBC register from the 10-bit value of the DMA FIFO
Byte Offset Counter, which consists of bits [1:0] in the CTEST5
register and bits [7:0] of the DMA FIFO register. AND the result
with 0x3FF for a byte count between zero and 944.

Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) and SCSI Status

Two (SSTAT2) registers to determine if any bytes are left in the
SCSI Output Data Latch (SODL) register.Ifbit5issetinthe

SSTAT0 or SST AT2 register, then the least significant byte or
the most significant byte in the SODL register is full,
respectively. Checking this bit also reveals bytes left in the
SODL register from a Chained Move operation with an odd byte
count.

Synchronous SCSI Send –

Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Chip Test

Five (CTEST5) register cleared), look at the DFIFO and DBC

registers and calculate if there are bytes left in the DMA FIFO.
To makethis calculation, subtract the seven least significant bits
of the DMA Byte Counter (DBC) register from the 7-bit value of
the DMA FIFO (DFIFO) register. AND the result with 0x7F for
a byte count between zero and 112.

If the DMA FIFO size is set to 944 bytes (bit 5 of the CTEST5
register is set), subtract the 10 least significant bits of the DBC
register from the 10-bit value of the DMA FIFO Byte Offset
Counter, which consists of bits [1:0] in the CTEST5 register and
bits [7:0] of the DMA FIFO register. AND the result with 0x3FF
for a byte count between zero and 944.

Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) and SCSI Status

Two (SSTAT2) registers to determine if any bytes are left in the
SCSI Output Data Latch (SODL) register.Ifbit5issetinthe

SSTAT0 or SST AT2 register, then the least significant byte or
the most significant byte in the SODL register is full,
respectively. Checking this bit also reveals bytes left in the
SODL register from a Chained Move operation with an odd byte
count.

Step 3. Read bit 6 in the SCSI Status Zero (SSTAT0) and SCSI Status

Two (SSTAT2) registers to determine if any bytes are left in the

SODR register (a hidden buffer register which is not
accessible). If bit 6 is set in the SSTAT0 or SSTAT2 register,

2-30 Functional Description

then the least significant byte or the most significant byte in the
SODR register is full, respectively.

Asynchronous SCSI Receive –

Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Chip Test

Five (CTEST5) register cleared), look at the DMA FIFO
(DFIFO) and DMA Byte Counter (DBC) registers and calculate

if there are bytes left in the DMA FIFO. To makethis calculation,
subtract the seven least significant bits of the DBC register from
the 7-bit value of the DFIFO register. AND the result with 0x7F
for a byte count between zero and 88.

If the DMA FIFO size is set to 944 bytes (bit 5 of the Chip Test

Five (CTEST5) register is set), subtract the 10 least significant

bits of the DMA Byte Counter (DBC) register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the CTEST5 register and bits [7:0] of the DMA FIFO
register. AND the result with 0x3FF for a byte count between
zero and 944.

Step 2. Read bit 7 in the SCSI Status Zero (SSTAT0) and SCSI Status

Two (SSTAT2) registers to determine if any bytes are left in the
SCSI Input Data Latch (SIDL) register.Ifbit7issetinthe

SSTAT0 or SST AT2 register, then the least significant byte or
the most significant byte is full, respectively.

Step 3. If any wide transfers have been performed using the Chained

Move instruction, read the Wide SCSI Receive bit (SCSI Status

Two (SSTAT2), bit 0) to determine whether a byte is left in the
SCSI Wide Residue (SWIDE) register.

Synchronous SCSI Receive –

Step 1. If the DMA FIFO size is set to 112 bytes, subtract the seven

least significant bits of the DMA Byte Counter (DBC) register
from the 7-bit value of the DMA FIFO (DFIFO) register. AND
the result with 0x7F for a byte count between zero and 112.

If the DMA FIFO size is set to 944 bytes (bit 5 of the Chip Test

Five (CTEST5) register is set), subtract the 10 least significant

bits of the DBC register from the 10-bit value of the DMA FIFO
Byte Offset Counter, which consists of bits [1:0] in the Chip Test

Five (CTEST5) register and bits [7:0] of the DMA FIFO register.

SCSI Functional Descr i ption 2-31

AND the result with 0x3FF for a byte count between zero and

944.

Step 2. Read the SCSI Status One (SSTAT1) register and examine bits

[7:4], the binary representation of the number of valid bytes in
the SCSI FIFO, to determine if any bytes are left in the SCSI
FIFO.

Step 3. If any wide transfers have been performed using the Chained

Move instruction, read the Wide SCSI Receive bit (SCSI

Control Two (SCNTL2), bit 0) to determine whether a byte is left

in the SCSI Wide Residue (SWIDE) register.

2.2.13 SCSI Bus Interface

The LSI53C875A performs SE transfers. TolerANT technology provides
signal filtering at the inputs of SREQ/ and SACK/ to increase immunity
to signal reflections.

2.2.13.1 SCSI Termination

The terminator networks provide the biasing needed to pull signals to an
inactive voltage level. They also match the impedance seen at the end
of the cable with the characteristic impedance of the cable. Terminators
must be installed at the ex treme ends of the SCSI chain and only at the
ends. No system should ever have more or less than two terminators
installed and active. SCSI host adapters should provide a means of
accommodating terminators. The terminators should be socketed, so that
if not needed they may be removed, or there should be a means of
disabling them with software.

SE cables can use a 220
(Term Power) line and a 330
performance nature of the LSI53C875A, regulated or active termination
is recommended. Figure 2.5 shows a Unitrode active terminator. For
additional information, refer to the SCSI-2 Specification. TolerANT
technology active negation can be used with either termination network.

: IftheLSI53C875Aisusedwithan8-bitSCSIbus,all

Note

16 data lines must still be terminated or pulled HIGH.

Note

: Active termination is required for Ultra SCSI synchronous

transfers.

2-32 Functional Description

Ω pull-up to the terminator power supply

Ω pull-down to ground. Due to the high

Figure 2.5 Regulated Termina tion for Ultra SCSI

UC5601QP

(UC5610 for Ultra SCSI)

2.85 V
C1

C2

2

REG_OUT

TERML1
TERML2
TERML3
TERML4
TERML5
TERML6
TERML7
TERML8
TERML9

20
21
22
23
24
25
26
27
28

SD0 (J1.40)
SD1 (J1.41)
SD2 (J1.42)
SD3 (J1.43)
SD4 (J1.44)
SD5 (J1.45)
SD6 (J1.46)
SD7 (J1.47)
SDP0 (J1.48)

19

DISCONNECT

(UC5614 for Ultra SCSI)

14

C3

Note:

1. C1 - 10

2. C2 - 0.1

3. C3 - 2.2

4. J1 - 68-pin, high density “P” connector

µFSMT

µFSMT
µFSMT

REG_OUT

6

DISCONNECT

UC5603DP

TERML10
TERML11
TERML12
TERML13
TERML14
TERML15
TERML16
TERML17
TERML18

TERML1
TERML2
TERML3
TERML4
TERML5
TERML6
TERML7
TERML8
TERML9

3
4
5
6
7
8
9
10
11

10
9
8
7
3
2
1
16
15

ATN (J1.55)
BSY (J1.57)
ACK (J1.58)
RST (J1.59)
MSG (J1.60)
SEL (J1.61)
C/D (J1.62)
REQ (J1.63)
I/O (J1.64)

SD15 (J1.38)
SD14 (J1.37)
SD13 (J1.36)
SD12 (J1.35)
SD11 (J1.68)
SD10 (J1.67)
SD9 (J1.66)
SD8 (J1.65)
SDP1 (J1.39)

2.2.14 Select/Reselect During Selection/Reselection

In multithreaded SCSI I/O environments, it is not uncommon to be
selected or reselected while trying to perform selection/reselection. This

SCSI Functional Descr i ption 2-33

situation may occur when a SCSI controller (operating in the initiator
mode) tries to select a target and is reselected by another. The Select
SCRIPTS instruction has an alternate address to which the SCRIPTS will
jump when this situation occurs. The analogous situation for target
devices is being selected while trying to perform a reselection.

Once a change in operating mode occurs, the initiator SCRIPTS should
start with a Set Initiator instruction or the target SCRIPTS should start
with a Set Target instruction. The Selection and Reselection Enable bits
(SCSI Chip ID (SCID) bits 5 and 6, respectively) should both be asserted
so that the LSI53C875A may respond as an initiator or as a target. If only
selection is enabled, the LSI53C875A cannot be reselected as an
initiator. There are also status and interrupt bits in the SCSI Interrupt

Status Zero (SIST0) and SCSI Interrupt Enable Zero (SIEN0) registers,

respectively, indicating that the LSI53C875A has been selected (bit 5)
and reselected (bit 4).

2.2.15 Synchronous Operation

The LSI53C875A can transfer synchronous SCSI data in both the
initiator and target modes. The SCSI Transfer (SXFER) register controls
both the synchronous offset and the transfer period. It may be loaded by
the CPU before SCRIPTS execution begins, from within SCRIPTS using
a Table Indirect I/O instruction, or with a Read-Modify-Write instruction.

The LSI53C875A can receive data from the SCSI bus at a synchronous
transfer period as short as 50 ns, regardless of the transfer period used
to send data. The LSI53C875A can receive data at one-four th of the
divided SCLK frequency. Depending on the SCLK frequency, the
negotiated transfer period, and the synchronous clock divider, the
LSI53C875A can send synchronous data at intervals as short as 50 ns
for Ultra SCSI, 100 ns for fast SCSI and 200 ns for SCSI-1.

2.2.15.1 Determining the Data Transfer Rate

Synchronous data transfer rates are controlled by bits in two different
registers of the LSI53C875A. Following is a brief description of the bits.

Figure 2.6 illustrates the clock division factors used in each register, and

the role of the register bits in determining the transfer rate.

2-34 Functional Description

Figure 2.6 Determining the Synchronous Transfer Rate

SCLK

SCF2 SCF1 SCF0 SCF

Divisor

0011

0101.5
0112
1003
0003
1014
1106
1118

SCF

Divider

Clock

Quadrupler

QCLK

CCF

Divider

CCF2 CCF1 CCF0 Divisor QCLK (MHz)

0 0 1 1 50.1–66.00
0 1 0 1.5 16.67–25.00
0 1 1 2 25.1–37.50
1 0 0 3 37.51–50.00
0 0 0 3 50.01–66.00
1 0 1 4 75.01–80.00
1 1 0 6 120
1 1 1 8 160

This point

must not

exceed

160 MHz

TP2 TP1 TP0 XFERP

Divisor
0004
0015
0106
0117
1008
1019
11010
11111

Divide by 4

Receive

Clock

Synchronous

Divider

Send Clock

(to SCSI Bus)

This point must

not exceed 20 MHz.

Asynchronous

SCSI Logic

Example 1 (using 40 MHz clock)
SCLK = 40MHz

QCLK (Quadrupled SCSI Clock) = 160 MHz
SCF = 1 (/1), XFERP = 4 (/8), CCF = 7 (/8)

Synchronous send rate = (QCLK/SCF)/XFERP =
(160/1) /8

Synchronous receive rate = (QCLK/SCF) /4 =
(160/1) /4

1

= 20 Mbytes/s

2

= 40 Mbytes/s

Example 2 (using 20 MHz clock)
SCLK = 20MHz

QCLK (Quadrupled SCSI Clock) = 80 MHz
SCF = 1 (/1), XFERP = 0 (/4), CCF = 5(/4)

Synchronous send rate = (QCLK/SCF)/XFERP =
(80/1) /4 = 20 Mbytes/s

Synchronous receive rate = (QCLK/SCF) /4 =
(80/1) /4 = 20 Mbytes/s

Note:

• Synchronous send rate must not exceed 20 Mbytes/s because the

LSI53C875A is an Ultra SCSI device.

• Although maximum synchronous receive rate is 40 Mbytes/s the

maximum transfer rate is 20 Mbytes/s because the LSI53C875A is an
Ultra S CSI device.

SCSI Functional Descr i ption 2-35

2.2.15.2 SCSI Control Three (SCNTL3) Register, Bits [6:4] (SCF[2:0])

The SCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the synchronous SCSI control logic.
The output from this divider controls the rate at which data can be
received; this rate must not exceed 160 MHz. The receive rate of
synchronous SCSI data is one-fourth of the SCF divider output. For
example, if SCLK is 80 MHz and the SCF value is set to divide by one,
then the maximum rate at which data can be received is 20 MHz
(80/(1*4) = 20).

2.2.15.3 SCSI Control Three (SCNTL3) Register, Bits [2:0] (CCF[2:0])

The CCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the asynchronous SCSI core logic.
This divider must be set according to the input clock frequency in the
table.

2.2.15.4 SCSI Transfer (SXFER) Register, Bits [7:5] (TP[2:0])

The TP[2:0] divider bits determine the SCSI synchronous transfer period
when sending synchronous SCSI data in either the initiator or target
mode. This value further divides the output from the SCF divider.

2.2.15.5 Ultra SCSI Synchronous Data Transfers

Ultra SCSI is an extension of the current Fast SCSI-2 synchronous
transfer specifications. It allows synchronous transfer periods to be
negotiated down as low as 50 ns, which is half the 100 ns period allowed
under Fast SCSI-2. This allows a maximum transfer rate of 40 Mbytes/s
on a 16-bit SCSI bus. The LSI53C875A has a SCSI clock quadrupler that
must be enabled for the chip to perform Ultra SCSI transfers with a 20
or 40 MHz oscillator. In addition, the following bit values affect the chip’s
ability to support Ultra SCSI synchronous transfer rates:

• Clock Conversion Factor bits, SCSI Control Three (SCNTL3) register

bits [2:0] and Synchronous Clock Conversion Factor bits, SCNTL3
register bits [6:4]. These fields support a value of 111 (binary),
allowing the 160 MHz SCLK frequency to be divided by 8 for the
asynchronous logic.

2-36 Functional Description

• Ultra SCSI Enable bit, SCSI Control Three (SCNTL3) register bit 7.

Setting this bit enables Ultra SCSI synchronous transfers in systems
that use the internal SCSI clock quadrupler.

• TolerANT Enable bit, SCSI Test Three (STEST3) register bit 7. Active

negation must be enabled for the LSI53C875A to perform Ultra SCSI
transfers.

2.2.16 Interrupt Handling

The SCRIPTS processors in the LSI53C875A perform most functions
independently of the host microprocessor. However, certain interrupt
situations must be handled by the external microprocessor. This section
explains all aspects of interrupts as they apply to the LSI53C875A.

2.2.16.1 Polling and Hardware Interrupts

The external microprocessor is informed of an interrupt condition by
polling or hardware interrupts. Polling means that the microprocessor
must continually loop and read a register until it detects a bit that is set
indicating an interrupt. This method is the fastest, but it wastes CPU time
that could be used for other system tasks. The preferred method of
detecting interrupts in most systems is hardware interrupts. In this case,
the LSI53C875A asserts the Interrupt Request (IRQ/) line that interrupts
the microprocessor, causing the microprocessor to execute an interrupt
service routine. A hybrid approach would use hardware interrupts for
long waits, and use polling for short waits.

2.2.16.2 Registers

The registers in the LSI53C875A that are used for detecting or defining
interrupts are Interrupt Status Zero (ISTAT0), Interrupt Status One

(ISTAT1), Mailbox Zero (MBOX0), Mailbox One (MBOX1), SCSI Interrupt
Status Zero (SIST0), SCSI Interrupt Status One (SIST1), DMA Status
(DSTAT), SCSI Interrupt Enable Zero (SIEN0), SCSI Interrupt Enable
One (SIEN1), DMA Control (DCNTL),andDMA Interrupt Enable (DIEN).

ISTAT – The ISTAT register includes the Interrupt Status Zero (ISTAT0),

Interrupt Status One (ISTAT1), Chip Test Zero (CTEST0),andMailbox
One (MBOX1) registers. It is the only register that can be accessed as a

slave during the SCRIPTS operation. Therefore, it is the register that is

SCSI Functional Descr i ption 2-37

polled when polled interrupts are used. It is also the first register that
should be read after the IRQ/ pin is asserted in association with a
hardware interrupt. The INTF (Interrupt-on-the-Fly) bit should be the first
interrupt serviced. It must be written to one to be cleared. This interrupt
must be cleared before servicing any other interrupts.

See Register 0x14, Interrupt Status Zero (ISTAT0) register, bit 5 Signal
process in Chapter 4, “Registers,” for additional information.

The host (C Code) or the SCRIPTS code could potentially try to access
the mailbox bits at the same time.

If the SIP bit in the Interrupt Status Zero (ISTAT0) register is set, then a
SCSI-type interrupt has occurred and the SCSI Interrupt Status Zero

(SIST0) and SCSI Interrupt Status One (SIST1) registers should be read.

If the DIP bit in the Interrupt Status Zero (ISTAT0) register is set, then a
DMA-type interrupt has occurred and the DMA Status (DSTAT) register
should be read.

SCSI-type and DMA-type interrupts may occur simultaneously, so in
some cases both SIP and DIP may be set.

SIST0 and SIST1 – The SCSI Interrupt Status Zero (SIST0) and SCSI

Interrupt Status One (SIST1) registers contain SCSI-type interrupt bits.

Reading these registers determines which condition or conditions caused
the SCSI-type interrupt, and clears that SCSI interrupt condition.

If the LSI53C875A is receiving data from the SCSI bus and a fatal
interrupt condition occurs, the chip attempts to send the contents of the
DMA FIFO to memory before generating the interrupt.

If the LSI53C875A is sending data to the SCSI bus and a fatal SCSI
interrupt condition occurs, data could be left in the DMA FIFO. Because
of this the DMA FIFO Empty (DFE) bit in DMA Status (DSTAT) should be
checked.

If this bit is cleared, set the CLF (Clear DMA FIFO) and CSF (Clear SCSI
FIFO) bits before continuing. The CLF bit is bit 2 in Chip Test Three

(CTEST3). The CSF bit is bit 1 in SCSI Test Three (STEST3).

DSTAT – The DMA Status (DSTAT) register contains the DMA-type
interrupt bits. Reading this register determines which condition or

2-38 Functional Description

conditions caused the DMA-type interrupt, and clears that DMA interrupt
condition. Bit 7 in DSTAT, DFE, is purely a status bit; it will not generate
an interrupt under any circumstances and will not be cleared when read.
DMA interrupts flush neither the DMA nor SCSI FIFOs before generating
the interrupt, so the DFE bit in the DMA Status (DSTAT) register should
be checked after any DMA interrupt.

If the DFE bit is cleared, then the FIFOs must be cleared by setting the
CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits, or flushed by
setting the FLF (Flush DMA FIFO) bit.

SIEN0 and SIEN1 – The SCSI Interrupt Enable Zero (SIEN0) and SCSI

Interrupt Enable One (SIEN1) registers are the interrupt enable registers

for the SCSI interrupts in SCSI Interrupt Status Zero (SIST0) and SCSI

Interrupt Status One (SIST1).

DIEN – The DMA Interrupt Enable (DIEN) register is the interrupt enable
register for DMA interrupts in DMA Status (DSTAT).

DCNTL – When bit 1 in the DMA Control (DCNTL) register is set, the
IRQ/ pin is not asserted when an interrupt condition occurs. The interrupt
is not lost or ignored, but is merely masked at the pin. Clearing this bit
when an interrupt is pending immediately causes the IRQ/ pin to assert.
As with any register other than ISTAT , this register cannot be accessed
except by a SCRIPTS instruction during SCRIPTS execution.

2.2.16.3 Fatal vs. Nonfatal Interrupts

A fatal interrupt, as the name implies, always causes the SCRIPTS to
stop running. All nonfatal interrupts become fatal when they are enabled
by setting the appropriate interrupt enable bit. Interrupt masking is
discussed in Section 2.2.16.4, “Masking.” All DMA interrupts (indicated
by the DIP bit in ISTAT and one or more bits in DMA Status (DSTAT)
being set) are fatal.

Some SCSI interrupts (indicated by the SIP bit in the Interrupt Status

Zero (ISTAT0) and one or more bits in SCSI Interrupt Status Zero
(SIST0) or SCSI Interrupt Status One (SIST1) being set) are nonfatal.

When the LSI53C875A is operating in the Initiator mode, only the
Function Complete (CMP), Selected (SEL), Reselected (RSL), General

SCSI Functional Descr i ption 2-39

2.2.16.4 Masking

Purpose Timer Expired (GEN), and Handshake-to-Handshake Timer
Expired (HTH) interrupts are nonfatal.

When operating in the Target mode, CMP, SEL, RSL, Target mode:
SATN/ active (M/A), GEN, and HTH are nonfatal. Refer to the description
for the Disable Halt on a Parity Error or SATN/ active (Target Mode Only)
(DHP) bit in the SCSI Control One (SCNTL1) register to configure the
chip’s behavior when the SATN/ interrupt is enabled during Target mode
operation. The Interrupt-on-the-Fly interrupt is also nonfatal, since
SCRIPTS can continue when it occurs.

The reason for nonfatal interrupts is to prevent the SCRIPTS from
stopping when an interrupt occurs that does not require service from the
CPU. This prevents an interrupt when arbitration is complete (CMP set),
when the LSI53C875A is selected or reselected (SEL or RSL set), when
the initiator asserts A TN (target mode: SATN/ active), or when the
General Purpose or Handshake-to-Handshake timers expire. These
interrupts are not needed for events that occur during high-level
SCRIPTS operation.

Masking an interrupt means disabling or ignoring that interrupt. Interrupts
canbemaskedbyclearingbitsintheSCSI Interrupt Enable Zero

(SIEN0) and SCSI Interrupt Enable One (SIEN1) (for SCSI interrupts)

registers or DMA Interrupt Enable (DIEN) (for DMA interrupts) register.
How the chip responds to masked interrupts depends on: whether polling
or hardware interrupts are being used; whether the interrupt is fatal or
nonfatal; and whether the chip is operating in the Initiator or Target mode.

If a nonfatal interrupt is masked and that condition occurs, the SCRIPTS
do not stop, the appropriate bit in the SCSI Interrupt Status Zero (SIST0)
or SCSI Interrupt Status One (SIST1) is still set, the SIP bit in the

Interrupt Status Zero (ISTAT0) is not set, and the IRQ/ pin is not

asserted.
If a fatal interrupt is masked and that condition occurs, then the SCRIPTS

still stop, the appropriate bit in the DMA Status (DSTAT), SCSI Interrupt

Status Zero (SIST0),orSCSI Interrupt Status One (SIST1) register is

set, and the SIP or DIP bit in the Interrupt Status Zero (ISTAT0) register
is set, but the IRQ/ pin is not asserted.

2-40 Functional Description

Interrupts can be disabled by setting SYNC_IRQD bit 0 in the Interrupt

Status One (ISTAT1) register. If an interrupt is already asserted and

SYNC_IRQD is then set, the interrupt will remain asserted until serviced.
At this point, the IRQ/ pin is blocked for future interrupts until this bit is

cleared. When the LSI53C875A is initialized, enable all fatal interrupts if
you are using hardware interrupts. If a fatal interrupt is disabled and that
interrupt condition occurs, the SCRIPTS halt and the system never
knows it unless it times out and checks the ISTAT register after a certain
period of inactivity.

If you are polling the ISTAT instead of using hardware interrupts, then
masking a fatal interrupt makes no difference since the SIP and DIP bits
in the Interrupt Status Zero (ISTAT0) inform the system of interrupts, not
the IRQ/ pin.

Masking an interrupt after IRQ/ is asserted does not cause deassertion
of IRQ/.

2.2.16.5 Stacked Interrupts

The LSI53C875A will stack interrupts if they occur one after the other. If
the SIP or DIP bits in the ISTAT register are set (first level), then there is
already at least one pending interrupt, and any future interrupts are
stacked in extra registers behind the SCSI Interrupt Status Zero (SIST0),

SCSI Interrupt Status One (SIST1), and DMA Status (DSTAT) registers

(second level). When two interrupts have occurred and the two levels of
the stack are full, any further interrupts set additional bits in the extra
registers behind SCSI Interrupt Status Zero (SIST0), SCSI Interrupt

Status One (SIST1), and DMA Status (DSTAT). When the first level of

interrupts are cleared, all the interrupts that came in afterward move into
SIST0, SIST1, and DSTAT. After the first interrupt is cleared by reading
the appropriate register, the IRQ/ pin is deasserted for a minimum of
three CLKs; the stacked interrupts move into SIST0, SIST1, or DSTAT;
and the IRQ/ pin is asserted once again.

Since a masked nonfatal interrupt does not set the SIP or DIP bits,
interrupt stacking does not occur. A masked, nonfatal interrupt still posts
the interrupt in SIST0, but does not assert the IRQ/ pin. Since no
interrupt is generated, future interrupts move into SCSI Interrupt Status

Zero (SIST0) or SCSI Interrupt Status One (SIST1) instead of being

stacked behind another interrupt. When another condition occurs that

SCSI Functional Descr i ption 2-41

generates an interrupt, the bit corresponding to the earlier masked
nonfatal interrupt is still set.

A related situation to interrupt stacking is when two interrupts occur
simultaneously. Since stacking does not occur until the SIP or DIP bits
are set, there is a small timing window in which multiple interrupts can
occur but are not stacked. These could be multiple SCSI interrupts (SIP
set), multiple DMA interrupts (DIP set), or multiple SCSI and multiple
DMA interrupts (both SIP and DIP set).

As previously mentioned, DMA interrupts do not attempt to flush the
FIFOs before generating the interrupt. It is important to set either the
Clear DMA FIFO (CLF) and Clear SCSI FIFO (CSF) bits if a DMA
interrupt occurs and the DMA FIFO Empty (DFE) bit is not set. This is
because any future SCSI interrupts are not posted until the DMA FIFO
is cleared of data. These ‘locked out’ SCSI interrupts are posted as soon
as the DMA FIFO is empty.

2.2.16.6 Halting in an Orderly Fashion

When an interrupt occurs, the LSI53C875A attempts to halt in an orderly
fashion.

• If the interrupt occurs in the middle of an instruction fetch, the fetch

is completed, except in the case of a Bus Fault. Execution does not
begin, but the DMA SCRIPTS Pointer (DSP) points to the next
instruction since it is updated when the current instruction is fetched.

• If the DMA direction is a write to memory and a SCSI interrupt

occurs, the LSI53C875A attempts to flush the DMA FIFO to memory
before halting. Under any other circumstances only the current cycle
is completed before halting, so the DFE bit in DMA Status (DSTAT)
register should be checked to see if any data remains in the DMA
FIFO.

• SCSI SREQ/SACK handshakes that have begun are completed

before halting.

• The LSI53C875A attempts to clean up any outstanding synchronous

offset before halting.

• In the case of Transfer Control Instructions, once instruction

execution begins it continues to completion before halting.

2-42 Functional Description

• If the instruction is a JUMP/CALL WHEN/IF <phase>, the DMA

SCRIPTS Pointer (DSP) is updated to the transfer address before

halting.

• All other instructions may halt before completion.

2.2.16.7 Sample Interrupt Service Routine

The following is a sample of an interrupt service routine for the
LSI53C875A. It can be repeated during polling or should be called when
the IRQ/ pin is asserted during hardware interrupts.

1. Read Interrupt Status Zero (ISTAT0).

2. If the INTF bit is set, it must be written to a one to clear this status.

3. If only the SIP bit is set, read SCSI Interrupt Status Zero (SIST0) and

SCSI Interrupt Status One (SIST1) to clear the SCSI interrupt

condition and get the SCSI interrupt status. The bits in the SIST0
and SIST1 tell which SCSI interrupts occurred and determine what
action is required to service the interrupts.

4. If only the DIP bit is set, read DMA Status (DSTAT) to clear the
interrupt condition and get the DMA interrupt status. The bits in
DSTAT tell which DMA interrupts occurred and determine what action
is required to service the interrupts.

5. If both the SIP and DIP bits are set, read SCSI Interrupt Status Zero

(SIST0), SCSI Interrupt Status One (SIST1),andDMA Status
(DSTAT) to clear the SCSI and DMA interrupt condition and get the

interrupt status. If using 8-bit reads of the SIST0, SIST1, and DSTAT
registers to clear interrupts, insert a 12 CLK delay between the
consecutive reads to ensure that the interrupts clear properly. Both
the SCSI and DMA interrupt conditions should be handled before
leaving the interrupt service routine. It is recommended that the DMA
interrupt is serviced before the SCSI interrupt, because a serious
DMA interrupt condition could influence how the SCSI interrupt is
acted upon.

6. When using polled interrupts, go back to Step 1 before leaving the
interrupt service routine, in case any stacked interrupts moved in
when the first interrupt was cleared. When using hardware interrupts,
the IRQ/ pin is asserted again if there are any stacked interrupts.
This should cause the system to re-enter the interrupt ser vice
routine.

SCSI Functional Descr i ption 2-43

2.2.17 Chained Block Moves

Since the LSI53C875A has the capability to transfer 16-bit wide SCSI
data, a unique situation occurs when dealing with odd bytes. The
Chained Move (CHMOV) SCRIPTS instruction along with the Wide SCSI
Send (WSS) and Wide SCSI Receive (WSR) bits in the SCSI Control

Two (SCNTL2) register are used to facilitate these situations. The

Chained Block Move instruction is illustrated in Figure 2.7.

2-44 Functional Description

Figure 2.7 Block Move and Chained Block Move Instructions

Host Memory

0x03

0x07 0x06 0x05 0x04

0x0B 0x0A 0x09 0x08

0x0F 0x0E 0x0D 0x0C

0x13 0x12 0x11 0x10

0x02 0x01 0x00

SCSI Bus

0x04 0x03

0x06 0x05

0x09

0x0B 0x0A

0x0D 0x0C

0x07

2.2.17.1 Wide SCSI Send Bit

The WSS bit is set whenever the SCSI controller is sending data
(Data-Out for initiator or Data-In for target) and the controller detects a
partial transfer at the end of a chained Block Move SCRIPTS instruction
(this flag is not set if a normal Block Move instruction is used). Under this
condition, the SCSI controller does not send the low-order byte of the last
partial memory transfer across the SCSI bus. Instead, the low-order byte
is temporarily stored in the lower byte of the SCSI Output Data Latch

(SODL) register and the WSS flag is set. The hardware uses the WSS

flag to determine what behavior must occur at the start of the next data
send transfer. When the WSS flag is set at the start of the next transfer,
the first byte (the high-order byte) of the next data send transfer is
“married” with the stored low-order byte in the SODL register; and the

SCSI Functional Descr i ption 2-45

32 Bits 16 Bits

two bytes are sent out across the bus, regardless of the type of Block
Move instruction (normal or chained). The flag is automatically cleared
when the “married” word is sent. The flag is alternately cleared through
SCRIPTS or by the microprocessor. Also, the microprocessor or
SCRIPTS can use this bit for error detection and recovery purposes.

2.2.17.2 Wide SCSI Receive Bit

The WSR bit is set whenever the SCSI controller is receiving data
(Data-In for initiator or Data-Out for target) and the controller detects a
partial transfer at the end of a block move or chained block move
SCRIPTS instruction. When WSR is set, the high-order byte of the last
SCSI bus transfer is not transferred to memory . Instead, the byte is
temporarily stored in the SCSI Wide Residue (SWIDE) register. The
hardware uses the WSR bit to determine what behavior must occur at
the start of the next data receive transfer. The bit is automatically cleared
at the start of the next data receive transfer. The bit can alternatively be
cleared by the microprocessor or through SCRIPTS. Also, the
microprocessor or SCRIPTS can use this bit for error detection and
recovery purposes.

2.2.17.3 SWIDE Register

This register stores data for partial byte data transfers. For receive data,
the SCSI Wide Residue (SWIDE) register holds the high-order byte of a
partial SCSI transfer which has not yet been transferred to memory. This
stored data may be a residue byte (and therefore ignored) or it may be
valid data that is transferred to memory at the beginning of the next Block
Move instruction.

2.2.17.4 SODL Register

For send data, the low-order byte of the SCSI Output Data Latch (SODL)
register holds the low-order byte of a partial memory transfer which has
not yet been transferred across the SCSI bus. This stored data is usually
“married” with the first byte of the next data send transfer, and both bytes
are sent across the SCSI bus at the start of the next data send block
move command.

2-46 Functional Description

2.2.17.5 Chained Block Move SCRIPTS Instruction

A chained Block Move SCRIPTS instruction is primarily used to transfer
consecutive data send or data receive blocks. Using the chained Block
Move instruction facilitates partial receive transfers and allows correct
partial send behavior without additional opcode overhead. Behavior of
the chained Block Move instruction varies slightly for sending and
receiving data.

For receive data (Data-In for initiator or Data-Out for target), a chained
Block Move instruction indicates that if a partial transfer occurred at the
end of the instruction, the WSR flag is set. The high-order byte of the
last SCSI transfer is stored in the SCSI Wide Residue (SWIDE) register
rather than transferred to memory. The contents of the SWIDE register
should be the first byte transferred to memory at the start of the chained
Block Move data stream. Since the byte count always represents data
transfers to/from memory (as opposed to the SCSI bus), the byte
transferred out of the SCSI Wide Residue (SWIDE) register is one of the
bytes in the byte count. If the WSR bit is cleared when a receive data
chained Block Move instruction is executed, the data transfer occurs
similar to that of the regular Block Mov e instruction. Whether the WSR
bit is set or cleared, when a normal block move instruction is e xecuted,
the contents of the SCSI Wide Residue (SWIDE) register are ignored
and the transfer takes place normally. For “N” consecutive wide data
receive Block Move instructions, the 2nd through the Nth Block Move
instructions should be chained block moves.

For send data (Data-Out for initiator or Data-In for target), a chained
Block Move instruction indicates that if a partial transfer terminates the
chained block move instruction, the last low-order byte (the partial
memorytransfer)shouldbestoredinthelowerbyteoftheSCSI Output

Data Latch (SODL) register and not sent across the SCSI bus. Without

the chained Block Move instruction, the last low-order byte would be sent
across the SCSI bus. The starting byte count represents data bytes
transferred from memory but not to the SCSI bus when a partial transfer
exists. For example, if the instruction is an Initiator chained Block Move
Data Out of five bytes (and WSS is not previously set), five bytes are
transferred out of memory to the SCSI controller, four bytes are
transferred from the SCSI controller across the SCSI bus, and one byte
is temporarily stored in the lower byte of the SCSI Output Data Latch

(SODL) register waiting to be married with the first byte of the next Block

Move instruction. Regardless of whether a chained Block Move or normal
Block Move instruction is used, if the WSS bit is set at the start of a data

SCSI Functional Descr i ption 2-47

send command, the first byte of the data send command is assumed to
be the high-order byte and is “married” with the low-order byte stored in
the lower byte of the SCSI Output Data Latch (SODL) register before the
two bytes are sent across the SCSI bus. For “N” consecutive wide data
send Block Move commands, the first through the (N
instructions should be Chained Block Moves.

CHMOV 5, 3 when Data_Out
Moves five bytes from address 0x03 in the host memory to the SCSI bus.

Bytes 0x03, 0x04, 0x05, and 0x06 are moved and byte 0x07 remains in
the low-order byte of the SCSI Output Data Latch (SODL) register and
ismarriedwiththefirstbyteofthefollowingMOVEinstruction.

MOVE 5, 9 when Data_Out
Moves five bytes from address 0x09 in the host memory to the SCSI bus.

2.3 Parallel ROM Interface

The LSI53C875A supports up to one megabyte of external memory in
binary increments from 16 Kbytes, to allow the use of expansion ROM
for add-in PCI cards. This interface is designed for low speed operations
such as downloading instruction code from ROM; it is not intended for
dynamic activities such as executing instructions.

th

– 1) Block Move

System requirements include the LSI53C875A, two or three external
8-bit address holding registers (HCT273 or HCT374), and the
appropriate memory device. The 4.7 k
require HC or HCT external components to be used. If in-system Flash
ROM updates are required, a 7406 (high voltage open collector inverter),
a MTD4P05, and several passive components are also needed. The
memory size and speed is determined by pull-up resistors on the
8-bit bidirectional memory bus at power-up. The LSI53C875A senses this
bus shortly after the release of the Reset signal and configures the

Expansion ROM Base Address register and the memory cycle state

machines for the appropriate conditions.
The external memory interface works with a variety of ROM sizes and

speeds. An example set of interface drawings is in Appendix B, “External

Memory Interface Diagram Examples.”

2-48 Functional Description

Ω pull-up resistors on the MAD bus

The LSI53C875A supports a variety of sizes and speeds of expansion
ROM, using pull-down resistors on the MAD[3:0] pins. The encoding of
pins MAD[3:1] allows the user to define how much external memory is
available to the LSI53C875A. Table 2.6 shows the memory space
associated with the possible values of MAD[3:1]. The MAD[3:1] pins are
fully described in Chapter 3, “Signal Descriptions.”

Table 2.6 Parallel ROM Support

MAD[3:1] Av ailable Memory Space

000 16 Kbytes
001 32 Kbytes
010 64 Kbytes
011 128 Kbytes
100 256 Kbytes
101 512 Kbytes
110 1024 Kbytes
111 no external memory present

To use one of the configurations mentioned above in a host adapter
board design, put 4.7 k

Ω pull-up resistors on the MAD pins

corresponding to the available memory space. For example, to connect
to a 64 Kbyte external ROM, use a pull-up on MAD2. If the external
memory interface is not used, MAD[3:1] should be pulled HIGH.

Note:

There are internal pull-downs on all of the MAD bus
signals.

The LSI53C875A allows the system to determine the size of the available
external memory using the Expansion ROM Base Address register in the
PCI configuration space. For more information on how this works, refer
to the PCI specification or the Expansion ROM Base Address register
description in Chapter 4, “Registers.”

MAD0 is the slow ROM pin. When pulled up, it enables two extra clock
cycles of data access time to allow use of slower memory devices. The
external memory interface also supports updates to flash memory.

Parallel ROM Interface 2-49

2.4 Serial EEPROM Interface

The LSI53C875A implements an interface that allows attachment of a
serial EEPROM device to the GPIO0 and GPIO1 pins. There are two
modes of operation relating to the serial EEPROM and the Subsystem
ID and Subsystem Vendor ID registers. These modes are programmable
through the MAD7 pin which is sampled at power-up.

2.4.1 Default Download Mode

In this mode, MAD7 is pulled down internally, GPIO0 is the serial data
signal (SDA) and GPIO1 is the serial clock signal (SCL). Certain data in
the serial EEPROM is automatically loaded into chip registers at
power-up.

The format of the serial EEPROM data is defined in Table 2.7.Ifthe
download is enabled and an EEPROM is not present, or the checksum
fails, the Subsystem ID and Subsystem Vendor ID registers read back all
zeros. At power-up, only five bytes are loaded into the chip from locations
0xFB through 0xFF.

The Subsystem ID and Subsystem Vendor ID registers are read only, in
accordance with the PCI specification, with a default value of all zeros if
the download fails.

2-50 Functional Description

Table 2.7 Mode A Serial EEPROM Data Format

Byte Name Description

0xFB SVID(0) Subsystem Vendor ID, LSB. This byte is loaded into the least significant

0xFC SVID(1) Subsystem Vendor ID, MSB. This byte is loaded into the most significant

0xFD SID(0) Subsystem ID, LSB. This byte is loaded into the least significant byte of

0xFE SID(1) Subsystem ID, MSB. This byte is loaded into the most significant byte of

0xFF CKSUM Checksum. This 8-bit checksum is formed by adding, bytewise, each byte

0x100–0xEOM UD User Data.

byte of the Subsystem Vendor ID register in the appropriate PCI
configuration space at chip power-up.

byte of the Subsystem Vendor ID register in the appropriate PCI
configuration space at chip power-up.

the Subsystem ID register in the appropriate PCI configuration space at
chip power-up.

the Subsystem ID register in the appropriate PCI configuration space at
chip power-up.

contained in locations 0x00–0x03 to the seed value 0x55, and then taking
the 2s complement of the result.

2.4.2 No Download Mode

When MAD7 is pulled up through an external resistor, the automatic
download is disabled and no data is automatically loaded into chip
registers at power-up. The Subsystem ID and Subsystem Vendor ID
registers are read only, per the PCI specification, with a default value of
0x1000 and 0x1000 respectively.

2.5 Power Management

The LSI53C875A complies with the PCI Bus Pow er Management
Interface Specification, Revision 1.1. The PCI Function Power States D0,
D1, D2, and D3 are defined in that specification.

D0 is the maximum powered state, and D3 is the minimum powered
state. Power state D3 is further categorized as D3hot or D3cold. A
function that is powered off is said to be in the D3cold power state.

Power Management 2-51

The LSI53C875A power states shown in Table 2.8 are independently
controlled through two power state bits that are located in the PCI Power

Management Control/Status (PMCSR) register 0x44.

Table 2.8 Power States

Configuration Register 0x44

Although the PCI Bus Power Management Interface Specification does
not allow power state transitions D2 to D1, D3 to D2, or D3 to D1, the
LSI53C875A hardware places no restriction on transitions between
power states.

As the device transitions from one power level to a lower one, the
attributes that occur from the higher power state level are carried over
into the lower power state level. For example, D1 disables the SCSI CLK.
Therefore, D2 will include this attribute as well as the attributes defined
in the Power State D2 section. The PCI Function Power States D0, D1,
D2, and D3 are described below. Power state actions are separate for
each function.

2.5.1 Power State D0

Bits [1:0] Power State Function

00 D0 Maximum Power
01 D1 Disables SCSI Clock
10 D2 Coma Mode
11 D3 Minimum Power

Power state D0 is the maximum power state and is the power-up default
state. The LSI53C875A is fully functional in this state.

2.5.2 Power State D1

Power state D1 is a lower power state than D0. In this state, the
LSI53C875A core is placed in the snooze mode and the SCSI CLK is
disabled. In the snooze mode, a SCSI reset does not generate an IRQ/
signal. However, the SCSI CLK is still disabled.

2-52 Functional Description

2.5.3 Power State D2

Power state D2 is a lower power state than D1. In this state the
LSI53C875A core is placed in the coma mode. The following PCI
Configuration Space command register enable bits are suppressed:

• I/O Space Enable

• Memory Space Enable

• Bus Mastering Enable

• SERR/Enable

• Enable Parity Error Response

Thus, the memory and I/O spaces cannot be accessed, and the
LSI53C875A cannot be a PCI bus master. Furthermore, all interrupts are
disabled when in power state D2. If changed from power state D2 to
power state D0, the previous values of the PCI command register are
restored. Also, any pending interrupts before the function entered power
state D2 are asserted.

2.5.4 Power State D3

Power state D3 is the minimum power state, which includes settings
called D3hot and D3cold. D3hot allows the device to transition to D0
using software. The LSI53C875A is considered to be in power state
D3cold when power is removed from the device. D3cold can transition to
D0 by applying V
soft reset is continually asserted while in power state D3, which clears
all pending interrupts and 3-states the SCSI bus. In addition, the device's
PCI command register is cleared and the Clock Quadrupler is disabled,
which results in additional power savings.

and resetting the device. Furthermore, the device's

CC

Power Management 2-53

2-54 Functional Description

Chapter 3
Signal Descriptions

This chapter presents the LSI53C875A pin configuration and signal
definitions using tables and illustrations. This chapter contains the
following sections:

• Section 3.1, “LSI53C875A Functional Signal Grouping”

• Section 3.2, “Signal Descriptions”

• Section 3.3, “PCI Bus Interface Signals”

• Section 3.4, “SCSI Bus Interface Signals”

• Section 3.5, “GPIO Signals”

• Section 3.6, “ROM Flash and Memory Interface Signals”

• Section 3.7, “T est Interface Signals”

• Section 3.8, “Power and Ground Signals”

• Section 3.9, “MAD Bus Programming”

A slash (/) at the end of a signal name indicates that the active state
occurs when the signal is at a LOW voltage. When the slash is absent,
the signal is active at a HIGH voltage.

LSI53C875A PCI to Ultra SCSI Controller 3-1

3.1 LSI53C875A Functional Signal Grouping

Figure 3.1 presents the LSI53C875A signals by functional group.

Figure 3.1 LSI53C875A Functional Signal Grouping

LSI53C875A

System

CLK
RST/

SCLK

PCI Bus Interface

ROM Flash

Address

and

Data

Interface

Control

Arbitration

Error

Reporting

Interrupt

SCSI

Function

GPIO

& Memory

Interface

AD[31:0]
C_BE[3:0]/
PAR

FRAME/
TRDY/
IRDY/
STOP/
DEVSEL/
IDSEL

REQ/
GNT/

PERR/
SERR/

IRQ/

GPIO0_FETCH/
GPIO1_MASTER/
GPIO2
GPIO3
GPIO4

MWE/
MCE/
MOE/
MAC/_TESTOUT
MAS0/
MAS1/
MAD[7:0]

SD[15:0]

SDP[1:0]

SCD

SIO

SMSG

SREQ

SACK
SBSY
SATN
SRST
SSEL

TEST_RST/
TEST_HSC/

MAC/_TESTOUT

TCK

TMS

TDI

TDO

TRST/

SCSI

SCSI BusInterface

Test
Interface

3-2 Signal Descriptions

3.2 Signal Descriptions

The Signal Descriptions are divided into PCI Bus Interface Signals, SCSI

Bus Interface Signals, GPIO Signals, ROM Flash and Memory Interface
Signals, Test Interface Signals,andPower and Ground Signals.

The PCI Bus Interface Signals are subdivided into System Signals,

Address and Data Signals, Interface Control Signals, Arbitration Signals,
Error Reporting Signals, and Interrupt Signal.

The SCSI Bus Interface Signals are subdivided into SCSI Bus Interface

Signals, SCSI Signals,andSCSI Control Signals.

Signals are assigned a type. There are five signal types:

I Input, a standard input only signal.
O Output, a standard output driver (typically a Totem Pole Output).
I/O Input and output (bidirectional).
T/S 3-state, a bidirectional, 3-state input/output signal.
S/T/S Sustained 3-state, an active LOW 3-state signal owned and driven by

one and only one agent at a time.

3.2.1 Internal Pull-ups on LSI53C875A Signals

Several signals in the LSI53C875A have internal pull-up resistors.

Table 3.1 describes the conditions that enable these pull-ups.

Table 3.1 LSI53C875A Internal Pull-ups

Signal Name Pull-up Current Conditions for Pull-up

IRQ/ 25 µA Pull-up enabled when the IRQ mode bit (bit 3 of DCNTL

GPIO[1:0] 25 µA Pull-up enabled when bits [1:0] of General Purpose Pin

TEST_HSC/ 25 µA Pull-up enabled all the time.
TEST_RST/ 25 µA Pull-up enabled all the time.
TRST,TCK,TMS,TDI 25µA Pull-up enabled all the time.

(0x3B)) is cleared.

Control Zero (GPCNTL0) are not set.

Signal Descriptions 3-3

3.3 PCI Bus Interface Signals

The PCI Bus Interface Signals section contains tables describing the
signals for the following signal groups: System Signals, Address and

Data Signals, Interface Control Signals, Arbitration Signals, Error
Reporting Signals, and Interrupt Signal.

3.3.1 System Signals

Table 3.2 describes the System signals.

Table 3.2 System Signals

Name PQFP BGA Type Strength Description

CLK 145 A6 I N/A Clock provides timing for all transactions on the PCI bus

RST/ 144 B6 I N/A Reset forcesthePCIsequencerofeachdevicetoa

and is an input to every PCI device. All other PCI signals
are sampled on the rising edge of CLK, and other timing
parameters are defined with respect to this edge. Clock
can optionally serve as the SCSI core clock, but this may
effect fast SCSI-2 (or faster) transfer rates.

known state. All T/S and S/T/S signals are forced to a high
impedance state, and all internal logic is reset. The RST/
input is synchronized internally to the rising edge of CLK.
The CLK input must be active while RST/ is active to
properly reset the device.

3-4 Signal Descriptions

3.3.2 Address and Data Signals

Table 3.3 describes Address and Data signals.

Table 3.3 Address and Data Signals

Name PQFP BGA Type Strength Description

AD[31:0] 150, 151,

153, 154,
156, 157,
159,160,3,
5, 6, 7, 9,
11–13, 28–
30, 32, 34–
36, 38, 40,
41, 43, 44,
46, 47, 49,
50

C_BE[3:0] 1, 15, 26,39A1, F3, H3,K4T/S 8 mA

PAR 25 H1 T/S 8 mA

B5, C5, A4,
B4, A3, C4,
D4, A2, C2,
E5, C1, D3,
E4-E1, H5,
J1, J2, H6,
K2, J4, L1,
L2, M1, N1,
M3, L3, N3,
L4, K5, N4

T/S 8 mA

PCI

PCI

PCI

Physical Dword Address and Data are
multiplexed on the same PCI pins. A bus
transactionconsists of an addressphase
followed by one or more data phases.
During the first clock of a transaction,
AD[31:0] contain a 32-bit physical byte
address. If the command is a DAC,
implying a 64-bit address, a second
address phase is required. During the
first phase, AD[31:0] will contain the
lower 32 bits of the address followed by
a second phasewith AD[31:0] containing
the upper 32 bits of the address. During
subsequent clocks, AD[31:0] contain
data. PCI supports both read and write
bursts. AD[7:0] define the least
significantbyte, andAD[31:24] definethe
most significant byte.

Bus Command and Byte Enables are
multiplexed on the same PCI pins.
During the address phase of a
transaction, C_BE[3:0]/ define the bus
command. During the data phase,
C_BE[3:0]/ are used as byte enables.
The byte enables determine which byte
lanes carry meaningful data. C_BE[0]/
applies to byte 0, and C_BE[3]/ to byte 3.

Parity is the even parity bit that protects
the AD[31:0] and C_BE[3:0]/ lines.
During the address phase, both the
address and command bits are covered.
During data phase, both data and byte
enables are covered.

PCI Bus Interface Signals 3-5

3.3.3 Interface Control Signals

Table 3.4 describes the Interface Control signals.

Table 3.4 Interface Control Signals

Name PQFP BGA Type Strength Description

FRAME/ 16 F2 S/T/S 8 mA PCI Cycle Frame isdriven by thecurrent mastertoindicate

TRDY/ 19 G3 S/T/S 8 mA PCI Target Ready indicates the target agent’s (selected

IRDY/ 17 F1 S/T/S 8 mA PCI Initiator Ready indicates the initiating agent’s (bus

STOP/ 22 G4 S/T/S 8 mA PCI Stop indicates that the selected target is requesting

the beginning and duration of an access. FRAME/ is
asserted to indicatethata bus transactionisbeginning.
While FRAME/ is deasserted, either the transaction is
in the final data phase or the bus is idle.

device’s) ability to complete the current data phase of
the transaction. TRDY/ is used with IRDY/. A data
phase is completed on any clock when used with
IRDY/. A data phase is completed on any clock when
both TRDY/ and IRDY/ are sampled asserted. During a
read, TRDY/ indicates that valid data is present on
AD[31:0]. D uring a write, it indicates that the target is
prepared to accept data. Wait cycles are inserted until
both IRDY/ and TRDY/ are asserted together.

master’s) ability to complete the current data phase of
the transaction. IRDY/ is used with TRDY/. A data
phase is completed on any clock when both IRDY/ and
TRDY/ are sampled asserted. During a write, IRDY/
indicates that valid data is present on AD[31:0]. During
a read, it indicates that the master is prepared to
accept data. Wait cycles are inserted until both IRDY/
and TRDY/ are asserted together.

the master to stop the current transaction.

DEVSEL/ 20 G2 S/T/S 8 mA PCI Device Select indicates that the driving device has

IDSEL 2 B1 I N/A Initialization Device Select is used as a chip select in

3-6 Signal Descriptions

decoded its address as the target of the current
access. As an input, it indicates to a master whether
any device on the bus has been selected.

place of the upper 24 address lines during
configuration read and write transactions.

3.3.4 Arbitration Signals

Table 3.5 describes Arbitration signals.

Table 3.5 Arbitration Signals

Name PQFP BGA Type Strength Description

REQ/ 148 E6 O 8 mA PCI Request indicates to the system arbiter that this agent

GNT/ 147 D6 I N/A Grant indicates to the agent that access to the PCI bus

desires use of the PCI bus. This is a point-to-point signal.
Every master has its own REQ/ signal.

has been granted. This is a point-to-point signal. Every
master has its own GNT/ signal.

3.3.5 Error Reporting Signals

Table 3.6 describes the Error Reporting signals.

Table 3.6 Error Reporting Signals

Name PQFP BGA Type Strength Description

PERR/ 24 H2 S/T/S8mAPCI Parity Error may be pulsed active by an agent that

detects a data parity error. PERR/ can be used by any
agent to signal data corruption. However, on detection of
a PERR/ pulse, the central resource may generate a
nonmaskable interrupt to the host CPU, which often
implies the system is unable to continue operation once
error processing is complete.

SERR/ 143 E7 O 8 mA PCI System Error is an open drain output used to report

address parity errors as well as critical errors other than
parity.

PCI Bus Interface Signals 3-7

3.3.6 Interrupt Signal

Table 3.7 describes the Interrupt signal.

Table 3.7 Interrupt Signal

Name PQFP BGA Type Strength Description

IRQ/ 52 M5 O 8 mA PCI Interrupt Request. This signal, when asserted LOW,

1. See Register0x4D, SCSI Test One (STEST1) in Chapter 4 for additional information on this signal.

indicates that an interrupting condition has occurred and
that service is required from the host CPU. The output
drive of this pin is open drain.

3.4 SCSI Bus Interface Signals

The SCSI Bus Interface signals section contains tables describing the
signals for the following signal groups: SCSI Bus Interface Signals, SCSI

Signals,andSCSI Control Signals.

3.4.1 SCSI Bus Interface Signal

Table 3.8 describes the SCSI Bus Interface signal.

Table 3.8 SCSI Bus Interface Signal

Name PQFP BGA Type Strength Description

SCLK 56 M6 I N/A SCSI Clock is used to derive all SCSI-related timings. The

speed of this clock is determined by the application’s
requirements.In someapplications, SCLK maybesourced
internally from the PCI bus clock (CLK). If SCLK is
internally sourced, then the SCLK pin should be tied low.

3-8 Signal Descriptions

3.4.2 SCSI Signals

Table 3.9 describes the SCSI signals.

Table 3.9 SCSI Signals

Name PQFP BGA Type Strength Description

SD[15:0] 113, 115–17,85–87, 89,

102, 103, 105–108,110,
111

SDP[1:0] 112, 101 F8, G13 I/O 48 mA SCSI SCSI Parity.

D13, E10, C13, D11, J9,
L13, K11, J10, G10, G9,
F13, F11–9, E12, E11

I/O 48 mA SCSI SCSI Data.

3.4.3 SCSI Control Signals

Table 3.10 describes the SCSI Control signals.

Table 3.10 SCSI Control Signals

Name PQFP BGA Type Strength Description

SCD 92 J12 I/O 48 mA SCSI phase line, command/data
SIO 90 K13 I/O 48 mA SCSI phase line, input/output.
SMSG 95 H11 I/O 48 mA SCSI phase line, message.
SREQ 91 J11 I/O 48 mA Data handshake line from target device.
SACK 97 H13 I/O 48 mA Data handshake signal from the initiator device.
SBSY 98 H9 I/O 48 mA SCSI bus arbitration signal, busy.
SATN 100 G12 I/O 48 mA SCSI Attention, the initiator is requesting a message out

phase.
SRST 96 H12 I/O 48 mA SCSI bus reset.
SSEL 94 H10 I/O 48 mA SCSI bus arbitration signal, select device.

SCSI Bus Interface Signals 3-9

3.5 GPIO Signals

Table 3.11 describes the SCSI GPIO signals.

Table 3.11 GPIO Signals

Name PQFP BGA Type Strength Description

GPIO0_FETCH/ 53 N5 I/O 8 mA SCSI General Purpose I/O pin. Optionally,

GPIO1_MASTER/ 54 K6 I/O 8 mA SCSI General Purpose I/O pin. Optionally,

GPIO2 68 J8 I/O 8 mA SCSI General Purpose I/O pin. This pin

GPIO3 70 M9 I/O 8 mA SCSI General Purpose I/O pin. This pin

GPIO4 71 L9 I/O 8 mA SCSI General Purpose I/O pin. GPIO4

when driven LOW, indicates that the next bus
request will be for an opcode fetch. This pin is
programmable at power-up through the MAD7
pin to serve as the data signal for the serial
EEPROM interface. This signal can also be
programmedtobedrivenLOWwhenthe
LSI53C875A is active on the SCSI bus.

when driven LOW, indicates that the
LSI53C875A is bus master. This pin is
programmable at power-up through the MAD7
pin to serve as the clock signal for the serial
EEPROM interface.

powers up as an input.

powers up as an input.

powersup as an output.(This pin may be used
as the enable line for VPP, the 12 V power
supply to the external flash memory interface.)

3-10 Signal Descriptions

3.6 ROM Flash and Memory Interface Signals

Table 3.12 describes the ROM Flash and Memory Interface signals.

Table 3.12 ROM Flash and Memory Interface Signals

Name PQFP BGA Type Strength Description

MWE/ 139 C7 O 4 mA Memory Write Enable. Thispinisusedasawrite

MCE/ 141 A7 O 4 mA Memory Chip Enable. Thispinisusedasachip

MOE/ 140 B7 O 4 mA Memory Output Enable. Thispinisusedasan

MAC/_
TESTOUT

MAS0/ 137 A8 O 4 mA Memory Address Strobe 0. This pin is used to

MAS1/ 136 B8 O 4 mA Memory Address Strobe 1. This pin is used to

77 L10 O 16 mA Memory Access Control. This pin can be

enable signal to an external flash memory.

enable signal to an external EEPROM or flash
memory device.

output enable signal to an external EEPROM or
flash memory during read operations. It is also
used to test the connectivity of the LSI53C875A
signals in test mode.

programmed to indicate local or system memory
accessed (non-PCI applications). It is also used to
test the connectivity of the LSI53C875A signals in
test mode.

latch in theleast significant address byte(bits [7:0])
of an external EEPROM or flash memory. Since
the LSI53C875A moves addresses eight bits at a
time, this pin connects to the clock of an external
bank of flip-flops which are used to assemble up to
a 20-bit address for the external memory.

latch in the most significant address byte (bits
[15:8]) of an external EEPROM or flash memor y.
Since the LSI53C875A moves addresses eight bits
at a time, this pin connects to the clock of an
external bank of flip-flops which assemble up to a
20-bit address for the external memory.

ROM Flash and Memory Interface Signals 3-11

Table 3.12 ROM Flash and Memory Interface Signals (Cont.)

Name PQFP BGA Type Strength Description

MAD[7:0] 59–62,

64–67

L7, M7,
N7, K7,
M8, N8,
L8, K8

I/O 4 mA Memory Address/Data Bus. This bus is used in

conjunction with the memory address strobe pins
and external address latches to assemble up to a
20-bit address for an external EEPROM or flash
memory. This bus will put out the least significant
byte first and finishes with the most significant bits.
It is also used to write data to a flash memory or
read data into the chip from external EEPROM/
flash memory. These pins have static pull-downs.

3.7 Test Interface Signals

Table 3.13 describes Test Interface signals.

Table 3.13 Test Interface Signals

Name PQFP BGA Type Strength Description

TEST_HSC/ 126 A11 I N/A Test Halt SCSI Clock. For LSI Logic test purposes

only. Pulled HIGH internally. This signal can also
cause a full chip reset.

TCK 130 A10 I N/A Test Clock. This pin provides the clock for the JTAG

test logic.

TMS 57 N6 I N/A Test Mode Select. The signal received at TMS is

decoded by the TAP controller to control JTAG test
operations. This pin has a static pull-down.

TDI 142 D7 I N/A Test Data In. Serial test instructions are received by

TEST_RST/ 127 C10 I N/A Test Reset. For test purposes only. Pulled HIGH

TDO 58 J6 O 4 mA Test Data Out. This pin is the serial output for test

TRST/ 131 C9 I N/A Test Reset. This pin provides a reset for JTAG Test

3-12 Signal Descriptions

the JTAG test logic at this pin. This pin has a static
pull-down.

internally.

instructions and data from the JTAG test logic.

Logic. Pulled HIGH internally.

3.8 Power and Ground Signals

Table 3.14 describes the Power and Ground signals.

Table 3.14 Power and Ground Signals

Name PQFP BGA Type Strength Description

VSS_I/O 4, 10, 14, 18,

23, 27,31,37,
42, 48,69,79,
88, 93, 99,
104, 109,114,
123, 133,152,
158

VDD_I/O 8, 21, 33, 45,

63, 74, 84,
118, 128,138,
155

VDD_CORE 51, 83, 149 A5, L5, L12 P N/A Power for core logic.
VSS_CORE 55, 80, 146 C6, L6, N12 G N/A Ground for core logic.
VDDA 129 D9 P N/A Power for analog cells (clock

VSSA 132 B9 G N/A Ground for analog cells (clock

NC 72, 73,75,76,

78, 81, 82,
119–122,124,
125, 134, 135

A9,B11,D12,
E13, F12,
G11, J13,
K10, K12, N9

B10, C12, D2,
D5, E8, G1,
J5, J7, K1,
L11, M10

A12, A13, B2,
B3, B12, B13,
C3, C8, C11,
D1, D8, D10,
E9, F4-6, G5,
H4, H8, J3,
K3, K9, M2,
M4, M11-13,
N2, N10, N11,
N13

G N/A Ground for PCI bus

drivers/receivers, SCSI bus
drivers/receivers, local memory
interface drivers, and other I/O
pins.

P N/A Power for PCI bus

drivers/receivers, SCSI bus
drivers/receivers, local memory
interface drivers/receivers, and
other I/O pins.

quadrupler and diffsense logic).

quadrupler and diffsense logic).

N/A N/A These pins have NO internal

connection.

Note:

The I/O driver pad rows and digital core have isolated power supplies as indicated by the “I/O”
and “CORE” extensions on their respective V
should be connected directly to the primary power and ground planes of the circuit board. Bypass
capacitors of 0.01 µF should be applied between adjacent V
Do not connect bypass capacitors between V
boundaries.

Power and Ground Signals 3-13

and VDDnames. These power and ground pins

SS

and VDDpairs wherever possible.

and VDDpairs that cross power and ground bus

SS

SS

3.9 MAD Bus Programming

The MAD[7:0] pins, in addition to serving as the address/data bus for the
local memory interface, also are used to program power-up options for
the chip. A particular option is programmed allowing the internal
pull-down current sink to pull the pin LOW at reset or by connecting a

Ω resistor between the appropriate MAD[x] pin and V

4.7 k
pull-down resistors require that HC or HCT external components are
used for the memory interface. The MAD[7:0] pins are sensed by internal
circuitry three PCI clock cycles after RST/ is deasserted.

• MAD[7] Serial EEPROM programmable option. When allowed to be

pulled LOW by the internal pull-down current sink, the automatic data
download is enabled. When pulled HIGH by an external resistor, the
automatic data download is disabled. Please see Section 2.4, “Serial

EEPROM Interface,” in Chapter 2 and Subsystem ID and Subsystem
Vendor ID registers in Chapter 4 for additional information.

• MAD[6:4] Reserved and may be left floating.

• The MAD[3:1] pins are used to set the size of the external expansion

ROM device attached. Encoding for these pins are listed in

Table 3.15 (“0” indicates a pull-down resistor is attached, “1”

indicates a pull-up resistor is attached).

SS

.The

T able 3.15 Decode of MAD Pins

MAD[3:1] Available Memory Space

000 16 Kbyte
001 32 Kbyte
010 64 Kbyte
011 128 Kbyte
100 256 Kbyte
101 512 Kbyte
110 1024 Kbyte
111 no external memory present

3-14 Signal Descriptions

• The MAD[0] pin is the slow ROM pin. When pulled up, it enables two

extra cycles of data access time to allow use of slower memory
devices.

• All MAD pins have internal pull-down resistors.

MAD Bus Programming 3-15

3-16 Signal Descriptions

Chapter 4
Registers

This chapter describes all LSI53C875A registers and is divided into the
following sections:

• Section 4.1 “PCI Configuration Registers”

• Section 4.2 “SCSI Registers”

• Section 4.3 “64-Bit SCRIPTS Selectors”

• Section 4.4 “Phase Mismatch Jump Registers”

In the register descriptions, the term “set” is used to refer to bits that are
programmed to a binary one. Similarly, the term “cleared” is used to refer
to bits that are programmed to a binary zero. Write any bits marked as
reserved to zero; mask all information read from them. Reserved bit
functions may change at any time. Unless otherwise indicated, all bits in
registers are active HIGH, that is, the feature is enabled by setting the
bit. The bottom row of every register diagram shows the default register
values, which are enabled after the chip is powered on or reset.
Reserved registers and bits are shaded in the register tables.

4.1 PCI Configuration Registers

The PCI Configuration registers are accessed by performing a
configuration read/write to the device with its IDSEL pin asserted and the
appropriate value in AD[10:8] during the address phase of the
transaction. The LSI53C875A responds to a binary value of 000b.

Table 4.1 describes the PCI configuration registers

All PCI-compliant devices must support the Vendor ID, Device ID,

Command,andStatus registers. Support of other PCI-compliant

registers is optional. In the LSI53C875A, registers that are not supported
are not writable and return all zeros when read. Only those registers and

LSI53C875A PCI to Ultra SCSI Controller 4-1

bits that are currently supported by the LSI53C875A are described in this
chapter. Reserved bits should not be accessed

.

Table 4.1 PCI Configuration Register Map

31 1615 0

Device ID Vendor ID 0x00

Status Command 0x04

Class Code Revision ID (Rev ID) 0x08

Not Supported Header Type Latency Timer Cache Line Size 0x0C

Base Address Register Zero (I/O) 0x10

Base Address Register One (MEMORY) bits [31:0] 0x14

Base Address Register Two (SCRIPTS RAM) 0x18

Not Suppo rted 0x1C
Not Suppo rted 0x20
Not Suppo rted 0x24

Reserved 0x28

Subsystem ID Subsystem Vendor ID 0x2C

Expansion ROM Base Address 0x30

Reserved Capabilities Pointer 0x34

Reserved 0x38

Max_Lat Min_Gnt Interrupt Pin Interrupt Line 0x3C

Power Management Capabilities (PMC) Next Item Pointer Capability ID 0x40

Data

Bridge Support Exten-

sions (PMCSR_BSE)

Not Suppo rted 0x48

Power Management Control/Status (PMCSR) 0x44

Registers:0x00–0x01

Vendor ID
Read Only

15 0

0001000000000000

VID Vendor ID [15:0]

4-2 Registers

VID

This 16-bit register identifies the manufacturer of the
device. The Vendor ID is 0x1000.

Registers:0x02–0x03

Device ID
Read Only

15 0

DID

0000000000010011

DID Device ID [15:0]

This 16-bit register identifies the particular device. The
LSI53C875A Device ID is 0x0013.

Registers:0x04–0x05

Command
Read/Write

15 9876543 2 10

RSER EPER RWIEREBMEMSEIS

x x x x x x x0x0x0x0 00

The Command register provides coarse control over a device’s ability to
generate and respond to PCI cycles. When a zero is written to this
register, the LSI53C875A is logically disconnected from the PCI bus for
all accesses except configuration accesses.

R Reserved [15:9]
SE SERR/ Enable 8

This bit enables the SERR/ driver. SERR/ is disabled
when this bit is cleared. The default value of this bit is
zero. This bit and bit 6 must be set to report address
parity errors.

R Reserved 7
EPER Enable Parity Error Response 6

This bit allows the LSI53C875A to detect parity errors on
the PCI bus and report these errors to the system. Only
data parity checking is enabled and disabled with this bit.
The LSI53C875A always generates parity for the PCI
bus.

PCI Configuration Registers 4-3

R Reserved 5
WIE Write and Invalidate Enable 4

This bit allows the LSI53C875A to generate write and
invalidate commands on the PCI bus. The WIE bit in the

DMA Control (DCNTL) register must also be set for the

device to generate Write and Invalidate commands.

R Reserved 3
EBM Enable Bus Mastering 2

This bit controls the ability of the LSI53C875A to act as
a master on the PCI bus. A value of zero disables this
device from generating PCI bus master accesses. A
value of one allows the LSI53C875A to behave as a bus
master. The device must be a bus master in order to fetch
SCRIPTS instructions and transfer data.

EMS Enable Memory Space 1

This bit controls the ability of the LSI53C875A to respond
to Memory space accesses. A value of zero disables the
device response. A value of one allows the LSI53C875A
to respond to Memory Space accesses at the address
range specified by Base Address Register One (MEM-

ORY) and Base Address Register Tw o (SCRIPTS RAM)

registers in the PCI configuration space.

EIS Enable I/O Space 0

4-4 Registers

This bit controls the LSI53C875A response to I/O space
accesses. A value of zero disables the device response.
A value of one allows the LSI53C875A to respond to I/O
Space accesses at the address range specified by the

Base Address Register Zero (I/O) register in the PCI

configuration space.

Registers:0x06–0x07

Status
Read/Write

15 14 13 12 11 10 9 8 7 5 4 3 0

DPE SSE RMA RTA

0000

Reads to this register behavenormally.Writes are slightly different in that
bits can be cleared, but not set. A bit is cleared whenever the register is
written, and the data in the corresponding bit location is a one. For
instance, to clear bit 15 and not affect any other bits, write the value
0x8000 to the register.

DPE Detected Parity Error (from Slave) 15

SSE Signaled System Error 14

RMA Received Master Abort (from Master) 13

R DT[1:0] DPR RNC R

x010x x x1x x x x

This bit is set by the LSI53C875A whenev er it detects a
data parity error, even if data parity error handling is
disabled.

This bit is set whenever the device asserts the SERR/
signal.

A master device should set this bit whenever its
transaction (except for Special Cycle) is terminated with
Master Abort.

RTA Received Target Abort (from Master) 12

A master device should set this bit whenever its
transaction is terminated by target abort.

R Reserved 11
DT[1:0] DEVSEL/ Timing [10:9]

These bits encode the timing of DEVSEL/. These are
encoded as:

0b00 fast
0b01 medium
0b10 slow
0b11 reser ved

PCI Configuration Registers 4-5

These bits are read only and should indicate the slowest
time that a device asserts DEVSEL/ for any bus
command except Configuration Read and Configuration
Write. The LSI53C875A supports a value of 0b01.

DPR Data Parity Error Reported 8

This bit is set when all of the following conditions are met:

• The bus agent asserted PERR/ itself or observed

PERR/ asserted.

• The agent setting this bit acted as the bus master for

the operation in which the error occurred.

• The Parity Error Response bit in the Command

register is set.

R Reserved [7:5]
NC New Capabilities 4

This bit is set to indicate a list of extended capabilities
such as PCI Power Management. This bit is read only.

R Reserved [3:0]

Register: 0x08

Revision ID (Rev ID)
Read Only

7 0

xxxxxxxx

RID Revision ID [7:0]

4-6 Registers

RID

This register contains the current revision level of the
device.

Registers:0x09–0x0B

Class Code
Read Only

23 0

CC

000000010000000000000000

CC Class Code [23:0]

This 24-bit register is used to identify the generic function
of the device. The upper byte of this register is a base
class code, the middle byte is a subclass code, and the
lower byte identifies a specific register level programming
interface. The value of this register is 0x010000, which
identifies a SCSI controller.

Register: 0x0C

CacheLineSize
Read/Write

7 0

CLS

00000000

CLS Cache Line Size [7:0]

This register specifies the system cache line size in units
of 32-bit words. The value in this register is used by the
device to determine whether to use Write and Invalidate
or Write commands for performing write cycles, and
whether to use Read, Read Line, or Read Multiple
commands for performing read cycles as a bus master.
Devices participating in the caching protocol use this field
to know when to retry burst accesses at cache line
boundaries. These devices can ignore the PCI cache
support lines (SDONE and SB0/) when this register is
cleared to 0. If this register is programmed to a number
which is not a power of 2, the device will not use PCI
performance commands to perform data transfers.

PCI Configuration Registers 4-7

Register: 0x0D

Latency Timer
Read/Write

7 0

LT

00000000

LT Latency Timer [7:0]

The Latency Timer register specifies, in units of PCI bus
clocks, the value of the Latency Timer for this PCI bus
master. The LSI53C875A supports this timer. All eight
bits are writable, allowing latency values of 0–255 PCI
clocks. Use the following equation to calculate an
optimum latency value for the LSI53C875A.
Latency = 2 + (Burst Size x (typical wait states + 1))
Values greater than optimum are also acceptable.

Register: 0x0E

Header Type
Read Only

7 0

HT

00000000

HT Header Type [7:0]

Register: 0x0F

Not Suppor ted

4-8 Registers

This register identifies the layout of bytes 0x10 through
0x3F in configuration space and also whether or not the
device contains multiple functions.Since the LSI53C875A
is not a multifunction controller the value of this register
is 0x00.