LSI 53C810A User Manual

TECHNICAL

MANUAL

LSI53C810A
PCI to SCSI I/O
Processor

Version 2.1

March 2001

®

S14067

This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.

Document DB14-000168-00, First Edition (March 2001)
This document describes the LSI Logic LSI53C810A PCI to SCSI I/O Processor
and will remain the official reference source for all revisions/releases of this
product until rescinded by an update.

To receive product literature, visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.

Copyright © 1995–2001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT

The LSI Logic logo design, TolerANT, SDMS, and SCRIPTS are registered
trademarks or trademarks of LSI Logic Corporation. All other brand and product
names may be trademarks of their respective companies.

ii

Audience

Organization

Preface

This book is the primary reference and technical manual for the LSI Logic
LSI53C810A PCI to SCSI I/O Processor. It contains a complete
functional description for the product and includes complete physical and
electrical specifications.

This manual provides reference information on the LSI53C810A PCI to
SCSI I/O processor.It is intended forsystemdesigners and programmers
who are using this device to design a SCSI port for PCI-based personal
computers, workstations, or embedded applications.

This document has the following chapters and appendix:

• Chapter 1, General Description, includes general information about

the LSI53C810A and other members of the LSI53C8XX family of PCI
to SCSI I/O processors.

• Chapter 2, Functional Description, describes the main functional

areas of the chip in more detail, including the interfaces to the SCSI
bus.

• Chapter 3, PCI Functional Description, describes the chip’s

connection to the PCI bus, including the PCI commands and
configuration registers supported.

• Chapter 4, Signal Descriptions, contains the pin diagrams and

definitions of each signal.

• Chapter 5, Operating Registers, describes each bit in the operating

registers, organized by address.

Preface iii

• Chapter 6, Instruction Set of the I/O Processor, defines all of the

• Chapter 7, Electrical Characteristics, contains the electrical

• Appendix A, Register Summary, is a register summary.

Related Publications

For background please contact:

ANSI

11 West 42nd Street
New York, NY 10036
[phone]
Ask for document number X3.131-199X (SCSI-2)

Global Engineering Documents

15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
Ask for document number X3.131-1994 (SCSI-2) or X3.253

(SCSI-3 Parallel Interface)

SCSI SCRIPTS instructions that are supported by the LSI53C810A.

characteristics and AC timings for the chip.

ENDL Publications

14426 Black Walnut Court
Saratoga, CA 95070
[phone]
Document names:

SCSI Tutor

Prentice Hall

113 Sylvan Avenue
Englewood Cliffs, NJ 07632
[phone]
Ask for document number ISBN 0-13-796855-8,

the Small Computer System Interface

LSI Logic World Wide Web Home Page

www.lsil.com

iv Preface

SCSI Bench Reference, SCSI Encyclopedia,

SCSI: Understanding

PCI Special Interest Group

2575 N. E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]

SCSI SCRIPTS™ Processors Programming Guide,

S14044.A

Conventions Used in This Manual

The word

deassert

assert

means to drive a signal true or active. The word

means to drive a signal false or inactive.

Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.

Revision Record

Revision Date Remarks

1.0 6/95 First version.

2.0 7/96 Revised technical manual.

2.1 3/01 All product names changed from SYM to LSI.

Order Number

Preface v

vi Preface

Contents

Chapter 1 General Description

1.1 TolerANT®Technology 1-2

1.2 LSI53C810A Benefits Summary 1-3

1.2.1 SCSI Performance 1-3

1.2.2 PCI Performance 1-4

1.2.3 Integration 1-4

1.2.4 Ease of Use 1-4

1.2.5 Flexibility 1-5

1.2.6 Reliability 1-5

1.2.7 Testability 1-6

Chapter 2 Functional Description

2.1 SCSI Core 2-1

2.1.1 DMA Core 2-2

2.2 SCRIPTS Processor 2-2

2.2.1 SDMS Software: The Total SCSI Solution 2-3

2.3 Prefetching SCRIPTS Instructions 2-3

2.3.1 Opcode Fetch Burst Capability 2-4

2.4 PCI Cache Mode 2-4

2.4.1 Load and Store Instructions 2-5

2.4.2 3.3 V/5 V PCI Interface 2-5

2.4.3 Loopback Mode 2-5

2.5 Parity Options 2-5

2.5.1 DMA FIFO 2-8

2.6 SCSI Bus Interface 2-11

2.6.1 Terminator Networks 2-11

2.6.2 Select/Reselect During Selection/Reselection 2-11

2.6.3 Synchronous Operation 2-13

Contents vii

2.7 Interrupt Handling 2-15

2.7.1 Polling and Hardware Interrupts 2-15

Chapter 3 PCI Functional Description

3.1 PCI Addressing 3-1

3.1.1 Configuration Space 3-1

3.1.2 PCI Bus Commands and Functions Supported 3-2

3.2 PCI Cache Mode 3-3

3.2.1 Support for PCI Cache Line Size Register 3-3

3.2.2 Selection of Cache Line Size 3-4

3.2.3 Alignment 3-4

3.2.4 Memory Read Multiple Command 3-7

3.2.5 Unsupported PCI Commands 3-8

3.3 Configuration Registers 3-9

Chapter 4 Signal Descriptions

4.1 PCI Bus Interface Signals 4-5

4.1.1 System Signals 4-5

4.1.2 Address and Data Signals 4-6

4.1.3 Interface Control Signals 4-7

4.1.4 Arbitration Signals 4-8

4.1.5 Error Reporting Signals 4-8

4.2 SCSI Bus Interface Signals 4-9

4.2.1 SCSI Bus Interface Signals 4-9

4.2.2 Additional Interface Signals 4-10

Chapter 5 Operating Registers

Chapter 6 Instruction Set of the I/O Processor

6.1 Low Level Register Interface Mode 6-1

6.2 SCSI SCRIPTS 6-2

6.2.1 Sample Operation 6-3

6.3 Block Move Instructions 6-5

6.3.1 First Dword 6-6

6.3.2 Second Dword 6-12

6.4 I/O Instruction 6-13

viii Contents

6.4.1 First Dword 6-13

6.4.2 Second Dword 6-22

6.5 Read/Write Instructions 6-23

6.5.1 First Dword 6-23

6.5.2 Second Dword 6-23

6.5.3 Read-Modify-Write Cycles 6-23

6.5.4 Move To/From SFBR Cycles 6-24

6.6 Transfer Control Instructions 6-27

6.6.1 First Dword 6-27

6.6.2 Second Dword 6-35

6.7 Memory Move Instructions 6-36

6.7.1 First Dword 6-38

6.7.2 Second Dword 6-38

6.7.3 Third Dword 6-38

6.7.4 Read/Write System Memory from a SCRIPTS
Instruction 6-39

6.8 Load and Store Instructions 6-39

6.8.1 First Dword 6-40

6.8.2 Second Dword 6-41

Chapter 7 Electrical Characteristics

7.1 DC Characteristics 7-1

7.2 TolerANT Technology 7-6

7.3 AC Characteristics 7-10

7.4 PCI Interface Timing Diagrams 7-12

7.4.1 Target Timing 7-13

7.4.2 Initiator Timing 7-17

7.5 PCI Interface Timing 7-26

7.6 SCSI Timings 7-27

7.7 Package Drawings 7-33

Appendix A Register Summary

Index

Customer Feedback

Contents ix

Figures

1.1 LSI53C810A System Diagram 1-7

1.2 LSI53C810A Chip Block Diagram 1-8

2.1 DMA FIFO Sections 2-8

2.2 LSI53C810A Host Interface Data Paths 2-10

2.3 Active or Regulated Termination 2-12

2.4 Determining the Synchronous Transfer Rate 2-15

4.1 LSI53C810A Pin Diagram 4-2

4.2 Functional Signal Grouping 4-4

5.1 Register Address Map 5-2

6.1 SCRIPTS Overview 6-5

6.2 Block Move Instruction Register 6-8

6.3 I/O Instruction Register 6-16

6.4 Read/Write Register Instruction 6-25

6.5 Transfer Control Instruction 6-30

6.6 Memory to Memory Move Instruction 6-37

6.7 Load and Store Instruction Format 6-42

7.1 Rise and Fall Time Test Conditions 7-8

7.2 SCSI Input Filtering 7-8

7.3 Hysteresis of SCSI Receiver 7-8

7.4 Input Current as a Function of Input Voltage 7-9

7.5 Output Current as a Function of Output Voltage 7-9

7.6 Clock Timing 7-10

7.7 Reset Input 7-11

7.8 Interrupt Output Waveforms 7-11

7.9 PCI Configuration Register Read 7-13

7.10 PCI Configuration Register Write 7-14

7.11 Target Read 7-15

7.12 Target Write 7-16

7.13 OpCode Fetch, Nonburst 7-17

7.14 Burst Opcode Fetch 7-18

7.15 Back-to-Back Read 7-19

7.16 Back-to-Back Write 7-20

7.17 Burst Read 7-22

7.18 Burst Write 7-24

7.19 Initiator Asynchronous Send 7-27

7.20 Initiator Asynchronous Receive 7-28

x Contents

Tables

7.21 Target Asynchronous Send 7-29

7.22 Target Asynchronous Receive 7-30

7.23 Initiator and Target Synchronous Transfers 7-30

7.24 100 LD PQFP (UD) Mechanical Drawing (Sheet 1 of 2) 7-34

2.1 Bits Used for Parity Control and Observation 2-6

2.2 SCSI Parity Control 2-7

2.3 SCSI Parity Errors and Interrupts 2-7

3.1 PCI Bus Commands and Encoding Types 3-9

3.2 PCI Configuration Register Map 3-10

4.1 Power and Ground Signals 4-3

4.2 System Signals 4-5

4.3 Address and Data Signals 4-6

4.4 Interface Control Signals 4-7

4.5 Arbitration Signals 4-8

4.6 Error Reporting Signals 4-8

4.7 SCSI Bus Interface Signals 4-9

4.8 Additional Interface Signals 4-10

5.1 Synchronous Clock Conversion Factor 5-10

5.2 Asynchronous Clock Conversion Factor 5-11

5.3 Examples of Synchronous Transfer Periods and
Rates for SCSI-1 5-13

5.4 Examples of Synchronous Transfer Periods and
Rates for Fast SCSI 5-14

5.5 SCSI Synchronous Offset Values 5-15

6.1 SCRIPTS Instructions 6-3

6.2 Read/Write Instructions 6-26

7.1 Absolute Maximum Stress Ratings 7-2

7.2 Operating Conditions 7-2

7.3 SCSI Signals—SD[7:0]/, SDP/, SREQ/, SACK/ 7-3

7.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/,
SSEL/, SRST/ 7-3

7.5 Input Signals—CLK, SCLK, GNT/, IDSEL, RST/, TESTIN 7-3

7.6 Capacitance 7-4

7.7 Output Signals—MAC/_TESTOUT, REQ/ 7-4

7.8 Output Signal—IRQ/ 7-4

7.9 Output Signal—SERR/ 7-5

Contents xi

7.10 Bidirectional Signals—AD[31:0], C_BE/[3:0], FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR/ 7-5

7.11 Bidirectional Signals—GPIO0_FETCH/,
GPIO1_MASTER/ 7-6

7.12 TolerANT Technology Electrical Characteristics 7-7

7.13 Clock Timing 7-10

7.14 Reset Input Timing 7-11

7.15 Interrupt Output 7-11

7.16 PCI Timing 7-26

7.17 Initiator Asynchronous Send (5 Mbytes/s) 7-27

7.18 Initiator Asynchronous Receive (5 Mbytes/s) 7-28

7.19 Target Asynchronous Send (5 Mbytes/s) 7-29

7.20 Target Asynchronous Receive (5 Mbytes/s) 7-30

7.21 SCSI-1 Transfers (SE, 5.0 Mbytes/s) 7-31

7.22 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers),
40 MHz Clock) 7-31

7.23 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers),
50 MHz Clock) 7-32

A.1 Configuration Registers A-1
A.2 SCSI Registers A-2

xii Contents

Chapter 1
General Description

Chapter 1 is divided into the following sections:

• Section 1.1, “TolerANT

®

Technology”

• Section 1.2, “LSI53C810A Benefits Summary”

The LSI53C810A PCI to SCSI I/O processor brings high-performance I/O
solutions to host adapter, workstation, and general computer designs,
making it easy to add SCSI to any PCI system.

The LSI53C810A is a pin-for-pin replacement for the LSI53C810 PCI to
SCSI I/O processor. It performs fast SCSI transfers in Single-Ended (SE)
mode, and improves performance by optimizing PCI bus utilization.

The LSI53C810A integrates a high-performance SCSI core, a PCI bus
master DMA core, and the LSI Logic SCSI SCRIPTS™ processor to
meet the flexibility requirements of SCSI-1, SCSI-2, and future SCSI
standards. It is designed to implement multithreaded I/O algorithms with
a minimum of processor intervention, solving the protocol overhead
problems of previous intelligent and nonintelligent adapter designs.

The LSI53C810A is fully supported by the LSI Logic Storage Device
Management System (SDMS™), a software package that supports the
Advanced SCSI Protocol Interface (ASPI). SDMS software provides
BIOS and driver support for hard disk, tape, removable media products,
and CD-ROM under the major PC operating systems.

The LSI53C810A is packaged in a compact rectangular 100-pin Plastic
Quad Flat Pack (PQFP) package to minimize board space requirements.
It operates the SCSI bus at 5 Mbytes/s asynchronously or 10 Mbytes/s
synchronously, and bursts data to the host at full PCI speeds. The
LSI53C810A increases SCRIPTS performance and reduces PCI bus
overhead by allowing instruction prefetches of 4 or 8 Dwords.

LSI53C810A PCI to SCSI I/O Processor 1-1

Software development tools are available to developers who use the
SCSI SCRIPTS language to create customized SCSI software
applications. The LSI53C810A allows easy firmware upgrades and is
supported by advanced SCRIPTS commands.

1.1 TolerANT®Technology

The LSI53C810A features TolerANT technology, which includes active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation actively drives the SCSI Request,
Acknowledge, Data, and Parity signals HIGH rather than allowing them
to be passively pulled up by terminators. Active negation is enabled by
setting bit 7 in the SCSI Test Three (STEST3) register.

TolerANT receiver technology improves data integrity in unreliable
cabling environments where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions, without the long signal delay associated with
RC-type input filters. This improved driver and receiver technology helps
eliminate double clocking of data, the single biggest reliability issue with
SCSI operations. The TolerANT input signal filtering is a built in feature
of all LSI Logic fast SCSI devices. On the LSI53C8XX family products,
the user may select a filtering period of 30 or 60 ns, with bit 1 in the SCSI

Test Two (STEST2) register.

The benefits of TolerANT technology include increased immunity to noise
when the signal is going HIGH, better performance due to balanced duty
cycles, and improvedfast SCSI transfer rates. In addition, TolerANT SCSI
devices do not cause glitches on the SCSI bus at power-up or
power-down, so other devices on the bus are also protected from data
corruption. TolerANT technology is compatible with both the Alternative
One and Alternative Two termination schemes proposed by the American
National Standards Institute.

1-2 General Description

1.2 LSI53C810A Benefits Summary

This section provides an overview of the LSI53C810A features and
benefits. It contains these topics:

• SCSI Performance

• PCI Performance

• Integration

• Ease of Use

• Flexibility

• Reliability

• Testability

1.2.1 SCSI Performance

To improve SCSI performance, the LSI53C810A:

• Complies with PCI 2.1 specification

• Supports variable block size and scatter/gather data transfers

• Minimizes SCSI I/O start latency

• Performs complex bus sequences without interrupts, including

restore data pointers

• Reduces Interrupt Service Routine (ISR) overhead through a unique

interrupt status reporting method

• Performs fast SCSI bus transfers in SE mode

– up to 7 Mbytes/s asynchronous
– 10 Mbytes/s synchronous

• Increases performance of data transfers to and from the chip

registers with new load and store SCRIPTS instruction

• Supports target disconnect and later reselect with no interrupt to the

system processor

• Supports execution of multithreaded I/O algorithms in SCSI

SCRIPTS with fast I/O context switching

LSI53C810A Benefits Summary 1-3

1.2.2 PCI Performance

To improve PCI performance, the LSI53C810A:

• Bursts 2, 4, 8, or 16 Dwords across PCI bus with 80-byte DMA FIFO

• Prefetches up to 8 Dwords of SCRIPTS instructions

• Supports 32-bit word data bursts with variable burst lengths.

• Bursts SCRIPTS opcode fetches across the PCI bus

• Performs zero wait-state bus master data bursts faster than

110 Mbytes/s (@ 33 MHz)

• Supports PCI Cache Line Size register

1.2.3 Integration

Features of the LSI53C810A which ease integration include:

• 3.3 V/5 V PCI interface

• Full 32-bit PCI DMA bus master

• DMA controller using Memory-to-Memory Move instructions

• High-performance SCSI core

• Integrated SCRIPTS processor

• Compact 100-pin PQFP packaging

1.2.4 Ease of Use

The LSI53C810A provides:

• Direct PCI-to-SCSI connection

• Reduced SCSI development effort

• Support for the ASPI software standard using SDMS software

• Compatibility with existing LSI53C7XX and LSI53C8XX family

SCRIPTS

• Direct connection to PCI and SCSI SE bus

• Development tools and sample SCSI SCRIPTS

• Maskable and pollable interrupts

1-4 General Description

1.2.5 Flexibility

• Three programmable SCSI timers: Select/Reselect, Handshake-to-

Handshake, and General Purpose. The time-out period is
programmable from 100 µs to greater than 1.6 seconds

• SDMS software for complete PC-based operating system support

• Support for relative jump

• New SCSI Selected As ID (SSAID) bits for use when responding with

multiple IDs

The LSI53C810A provides:

• High level programming interface (SCSI SCRIPTS)

• Support for execution of tailored SCSI sequences from main system

RAM

• Flexible programming interface to tune I/O performance or to adapt

to unique SCSI devices

• Flexibility to accommodate changes in the logical I/O interface

definition

• Low level access to all registers and all SCSI bus signals

1.2.6 Reliability

• Fetch, Master, and Memory Access control pins

• Support for indirect fetching of DMA address and byte counts so that

SCRIPTS can be placed in a PROM

• Separate SCSI and system clocks

• Selectable IRQ pin disable bit

• Ability to route system clock to SCSI clock

Enhanced reliability features of the LSI53C810A include:

• 2 kV ESD protection on SCSI signals

• Typical 300 mV SCSI bus hysteresis

• Average operating supply current of 50 mA

• Protection against bus reflections due to impedance mismatches

LSI53C810A Benefits Summary 1-5

1.2.7 Testability

• Controlled bus assertion times (reduces RFI, improves reliability, and

eases FCC certification)

• Latch-up protection greater than 150 mA

• Voltage feed-through protection (minimum leakage current through

SCSI pads)

• High proportion (> 25%) of pins power and ground

• Power and ground isolation of I/O pads and internal chip logic

• TolerANT technology, which provides:

– Active negation of SCSI Data, Parity, Request, and Acknowledge

signals for improved fast SCSI transfer rates.

– Input signal filtering on SCSI receivers improves data integrity,

even in noisy cabling environments.

The LSI53C810A provides improved testability through:

• Access to all SCSI signals through programmed I/O

• SCSI loopback diagnostics

• SCSI bus signal continuity checking

• Support for single step mode operation

• Test mode (AND tree) to check pin continuity to the board

A system diagram showing the connections of the LSI53C810A in a PCI
system is pictured in Figure 1.1. A block diagram of the LSI53C810A is
pictured in Figure 1.2.

1-6 General Description

Figure 1.1 LSI53C810A System Diagram

SCSI Connection

V

V

DD

SS

PCI Bus LSI53C810A

40 MHz Oscillator or

Optional Internal

Connection to PCI

Bus Clock

CPU Baseboard

CPU Box

SCSI Term Connection

SCSI Bus

Peripheral

Bulkhead

LSI53C810A Benefits Summary 1-7

Figure 1.2 LSI53C810A Chip Block Diagram

PCI

PCI Master and Slave Control Block

Data

FIFO

80 Bytes

SCSI

SCRIPTS

SCSI FIFO and SCSI Control Block

TolerANT Technology Drivers and Receivers

Operating
Registers

SE SCSI Bus

Configuration

Registers

1-8 General Description

Chapter 2
Functional Description

Chapter 2 is divided into the following sections:

• Section 2.1, “SCSI Core”

• Section 2.2, “SCRIPTS Processor”

• Section 2.3, “Prefetching SCRIPTS Instructions”

• Section 2.4, “PCI Cache Mode”

• Section 2.5, “Parity Options”

• Section 2.6, “SCSI Bus Interface”

• Section 2.7, “Interrupt Handling”

The LSI53C810A contains three functional blocks: the SCSI Core, the
DMA Core, and the SCRIPTS Processor. The LSI53C810A is fully
supported by the SDMS, a complete software package that supports the
LSI Logic product line of SCSI processors and controllers.

2.1 SCSI Core

The SCSI core supports synchronous transfer rates up to 10 Mbytes/s
and asynchronous transfer rates up to 7 Mbytes/s on an 8-bit SCSI bus.
The SCSI core can be programmed with SCSI SCRIPTS, making it easy
to fine tune the system for specific mass storage devices or advanced
SCSI requirements.

The SCSI core offers low-level register access or a high-level control
interface. Like first generation SCSI devices, the LSI53C810A SCSI core
can be accessed as a register-oriented device. The ability to sample
and/or assert any signal on the SCSI bus can be used in error recovery

LSI53C810A PCI to SCSI I/O Processor 2-1

2.1.1 DMA Core

and diagnostic procedures. In support of loopback diagnostics, the SCSI
core can perform a self-selection and operate as both an initiator and a
target.

The SCSI core is controlled by the integrated SCRIPTS processor
through a high-level logical interface. Commands controlling the SCSI
core are fetched out of the main host memory or local memory. These
commands instruct the SCSI core to Select, Reselect, Disconnect, Wait
for a Disconnect, Transfer Information, Change Bus Phases and, in
general, implement all aspects of the SCSI protocol. The SCRIPTS
processor is a special high-speed processor optimized for SCSI protocol.

The DMA core is a bus master DMA device that attaches directly to the
industry standard PCI bus. The DMA core is tightly coupled to the SCSI
core through the SCRIPTS processor, which supports uninterrupted
scatter/gather memory operations.

The LSI53C810A supports 32-bit memory and automatically supports
misaligned DMA transfers. An 80-byte FIFO allows 2, 4, 8, or 16 Dword
bursts across the PCI bus interface to run efficiently without throttling the
bus during PCI bus latency.

2.2 SCRIPTS Processor

The SCSI SCRIPTS processor allows both DMA and SCSI commands
to be fetched from host memory. Algorithms written in SCSI SCRIPTS
control the actions of the SCSI and DMA cores and are executed from
32-bit system RAM. The SCRIPTS processor executes complex SCSI
bus sequences independently of the host CPU.

The SCRIPTS processor can begin a SCSI I/O operation in
approximately 500 ns. This compares with 2–8 ms required for traditional
intelligent host adapters. Algorithms may be designed to tune SCSI bus
performance, to adjust to new bus device types (such as scanners,
communication gateways, etc.), or to incorporate changes in the SCSI-2
or SCSI-3 logical bus definitions without sacrificing I/O performance.
SCSI SCRIPTS are hardware independent, so they can be used
interchangeably on any host or CPU system bus.

2-2 Functional Description

A complete set of development tools is available for writing custom
drivers with SCSI SCRIPTS. For more information on SCSI SCRIPTS
instructions supported by the LSI53C810A, see Chapter 6, “Instruction

Set of the I/O Processor.”

2.2.1 SDMS Software: The Total SCSI Solution

For users who do not need to develop custom drivers, LSI Logic provides
a total SCSI solution in PC environments with SDMS software. SDMS
software provides BIOS and driver support for hard disk, tape, and
removable media peripherals for the major PC-based operating systems.

SDMS software includes a SCSI BIOS to manage all SCSI functions
related to the device. It also provides a series of SCSI device drivers that
support most major operating systems. SDMS software supports a
multithreaded I/O application programming interface (API) for
user-developed SCSI applications. SDMS software supports both the
ASPI and CAM SCSI software specifications.

2.3 Prefetching SCRIPTS Instructions

When enabled by setting the Prefetch Enable bit (bit 5) in the DMA

Control (DCNTL) register, the prefetch logic in the LSI53C810A fetches

4 or 8 Dwords of instructions. The prefetch logic automatically
determines the maximum burst size that it can perform, based on the
burst length as determined by the values in the DMA Mode (DMODE)
register and the PCI Cache Line Size register (if cache mode is enabled).
If the unit cannot perform bursts of at least 4 Dwords, it disables itself.

The LSI53C810A may flush the contents of the prefetch unit under
certain conditions, listed below, to ensure that the chip always operates
from the most current version of the software. When one of these
conditions apply, the contents of the prefetch unit are automatically
flushed.

• On every Memory Move instruction. The Memory Move (MMOV)

instruction is often used to place modified code directly into memory.
To make sure that the chip executes all recent modifications, the
prefetch unit flushes its contents and loads the modified code every
time a MMOV instruction is issued. To avoid inadvertently flushing

Prefetching SCRIPTS Instructions 2-3

the prefetch unit contents, use the No Flush Memory to Memory
Move (NFMMOV) instruction for all MMOV operations that do not
modify code within the next 4 to 8 Dwords. For more information on
this instruction, refer to Chapter 6, “Instruction Set of the I/O

Processor.”

• On every Store instruction. The Store instruction may also be used

to place modified code directly into memory. To avoid inadvertently
flushing the prefetch unit contents use the No Flush option for all
Store operations that do not modify code within the next 8 Dwords.

• On every write to the DMA SCRIPTS Pointer (DSP) register.

• On all Transfer Control instructions when the transfer conditions are

met. This is necessary because the next instruction to execute is not
the sequential next instruction in the prefetch unit.

• When the Prefetch Flush bit (DMA Control (DCNTL) bit 6) is set. The

unit flushes whenever this bit is set. The bit is self-clearing.

2.3.1 Opcode Fetch Burst Capability

Setting the Burst Opcode Fetch Enable bit (bit 1) in the DMA Mode

(DMODE) register (0x38) causes the LSI53C810A to burst in the first two

Dwords of all instruction fetches. If the instruction is a Memory-to­Memory Move, the third Dword is accessed in a separate ownership. If
the instruction is an indirect type, the additional Dword is accessed in a
subsequent bus ownership. If the instruction is a Table Indirect Block
Move, the chip uses two accesses to obtain the four Dwords required, in
two bursts of two Dwords each.

Note: This feature can only be used if SCRIPTS prefetching is

disabled.

2.4 PCI Cache Mode

The LSI53C810A supports the PCI specification for an 8-bit Cache Line

Size register located in PCI configuration space. The Cache Line Size

register provides the ability to sense and react to nonaligned addresses
corresponding to cache line boundaries. In conjunction with the Cache

Line Size register, the PCI commands Read Line, Read Multiple, and

2-4 Functional Description

Write and Invalidate are each software enabled or disabled to allow the
user full flexibility in using these commands. For more information on PCI
cache mode operations, refer to Chapter 3, “PCI Functional Description.”

2.4.1 Load and Store Instructions

The LSI53C810A supports the Load and Store instruction type, which
simplifies the movement of data between memory and the internal chip
registers. It also enables the LSI53C810A to transfer bytes to addresses
relative to the Data Structure Address (DSA) register. For more
information on the Load and Store instructions, refer to

Chapter 6, “Instruction Set of the I/O Processor.”

2.4.2 3.3 V/5 V PCI Interface

The LSI53C810A can attach directly to a 3.3 V or a 5 V PCI interface,
due to separate VDDpins for the PCI bus drivers. This allows the devices
to be used on the universal board recommended by the PCI Special
Interest Group.

2.4.3 Loopback Mode

The LSI53C810A loopback mode allows testing of both initiator and
target functions and, in effect, lets the chip communicate with itself.
When the Loopback Enable bit is set in the SCSI Test Two (STEST2)
register, bit 4, the LSI53C810A allows control of all SCSI signals whether
the chip is operating in the initiator or target mode. For more information
on this mode of operation refer to the

Programming Guide

.

SCSI SCRIPTS Processors

2.5 Parity Options

The LSI53C810A implements a flexible parity scheme that allows control
of the parity sense, allows parity checking to be turned on or off, and has
the ability to deliberately send a byte with bad parity over the SCSI bus
to test parity error recovery procedures. Table 2.1 defines the bits that
are involved in parity control and observation. Table 2.2 describes the
parity control function of the Enable Parity Checking and Assert SCSI
Even Parity bits in the SCSI Control Zero (SCNTL0) register. Table 2.3
describes the options available when a parity error occurs.

Parity Options 2-5

Table 2.1 Bits Used for Parity Control and Observation

BIt Name Location Description

Assert SATN/ on Parity
Errors

Enable Parity Checking SCSI Control

Assert Even SCSI Parity SCSI Control

Disable Halt on SATN/or
a Parity Error (Target
Mode Only)

Enable Parity Error
Interrupt

Parity Error SCSI Interrupt

Status of SCSI Parity
Signal

Latched SCSI Parity SCSI Status One

SCSI Control
Zero (SCNTL0),

Bit 1

Zero (SCNTL0),

Bit 3

One (SCNTL1),

Bit 2

SCSI Control
One (SCNTL1),

Bit 5

SCSI Interrupt
Enable Zero
(SIEN0), Bit 0

Status Zero
(SIST0), Bit 0

SCSIStatusZero
(SSTAT0), Bit 0

(SSTAT1), Bit 3

Causes the LSI53C810Ato automatically assert SATN/
when it detects a parity error while operating as an
initiator.

Enables the LSI53C810A to check for parity errors.
The LSI53C810A checks for odd parity.

Determines the SCSI parity sense generated by the
LSI53C810A to the SCSI bus.

Causes the LSI53C810A not to halt operations when a
parity error is detected in target mode.

Determines whether the LSI53C810A generates an
interrupt when it detects a SCSI parity error.

This status bit is set whenever the LSI53C810A
detects a parity error on the SCSI bus.

This status bit represents the active HIGH current state
of the SCSI SDP0 parity signal.

This bit reflects the SCSI odd parity signal
corresponding to the data latched into the SCSI Input

Data Latch (SIDL) register.

Master Parity Error
Enable

Master Data Parity Error DMA Status

Master Data Parity Error
Interrupt Enable

Chip Test Four
(CTEST4), Bit 3

(DSTAT), Bit 6

DMA Interrupt
Enable (DIEN),

Bit 6

2-6 Functional Description

Enables parity checking during master data phases.

Set when the LSI53C810A, as a PCI master, detects a
target device signaling a parity error during a data
phase.

By clearing this bit, a Master Data Parity Error does not
cause assertion of IRQ/, but the status bit is set in the

DMA Status (DSTAT) register.

Table 2.2 SCSI Parity Control

EPC AESP Description

0 0 Does not check for parity errors. Parity is generated when sending

0 1 Does not check for parity errors. Parity is generated when sending

1 0 Checks for odd parity on SCSI data received. Parity is generated

1 1 Checks for odd parity on SCSI data received. Parity is generated

1. Key:
EPC = Enable Parity Checking (bit 3, SCSI Control Zero (SCNTL0)).
ASEP = Assert SCSI Even Parity (bit 2, SCSI Control One (SCNTL1)).

SCSI data. Asserts odd parity when sending SCSI data.

SCSI data. Asserts even parity when sending SCSI data.

when sending SCSI data. Asserts odd parity when sending SCSI
data.

when sending SCSI data. Asserts even parity when sending SCSI
data.

Table 2.3 SCSI Parity Errors and Interrupts

DPH PAR Description

0 0 Halts when a parity error occurs in the target or initiator mode and

0 1 Halts when a parity error occurs in the target mode and generates

does not generate an interrupt.

an interrupt in target or initiator mode.

1 0 Does not halt in target mode when a parity error occurs until the

1 1 Does not halt in target mode when a parity error occurs until the

Key:
DHP = Disable Halt on SATN/ or Parity Error (bit 5, SCSI Control One (SCNTL1).
PAR = Parity Error (bit 0, SCSI Interrupt Enable Zero (SIEN0).
This table only applies when the Enable Parity Checking bit is set.

end of the transfer. An interrupt is not generated.

end of the transfer. An interrupt is generated.

Parity Options 2-7

2.5.1 DMA FIFO

The DMA FIFO is divided into four sections, each one byte wide and
20 transfers deep. The DMA FIFO is illustrated in Figure 2.1.

Figure 2.1 DMA FIFO Sections

32-bits Wide

20
Bytes
Deep

8-bits

Byte Lane 3

2.5.1.1 Data Paths

The data path through the LSI53C810A is dependent on whether data is
being moved into or out of the chip, and whether SCSI data is being
transferred asynchronously or synchronously.

Figure 2.2 shows how data is moved to/from the SCSI bus in each of the

different modes.
The following steps determine if any bytes remain in the data path when

the chip halts an operation:

2-8 Functional Description

8-bits

Byte Lane 2

8-bits

Byte Lane 1

8-bits

Byte Lane 0

Asynchronous SCSI Send –

Step 1. Look at the DMA FIFO (DFIFO) and DMA Byte Counter (DBC)

registers and calculate if there are bytes left in the DMA FIFO.
To make this calculation, subtract the seven least significant bits
of the DMA Byte Counter (DBC) register from the 7-bit value of
the DMA FIFO (DFIFO) register. AND the result with 0x7F for
a byte count between zero and 80.

Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) register to

determine if any bytes are left in the SCSI Output Data Latch

(SODL) register. If bit 5 is set in SSTAT0, then the SODL

register is full.

Synchronous SCSI Send –

Step 1. Look at the DMA FIFO (DFIFO) and DMA Byte Counter (DBC)

registers and calculate if there are bytes left in the DMA FIFO.
To make this calculation, subtract the seven least significant bits
of the DMA Byte Counter (DBC) register from the 7-bit value of
the DMA FIFO (DFIFO) register. AND the result with 0x7F for
a byte count between zero and 80.

Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) register to

determine if any bytes are left in the SCSI Output Data Latch

(SODL) register. If bit 5 is set in SSTAT0, then the SCSI Output
Data Latch (SODL) register is full.

Step 3. Read bit 6 in the SCSI Status Zero (SSTAT0) register to

determine if any bytes are left in the SODR register. If bit 6 is
set in SSTAT0, then the SODR register is full.

Asynchronous SCSI Receive –

Step 1. Look at the DMA FIFO (DFIFO) and DMA Byte Counter (DBC)

registers and calculate if there are bytes left in the DMA FIFO.
To make this calculation, subtract the seven least significant bits
of the DMA Byte Counter (DBC) register from the 7-bit value of
the DMA FIFO (DFIFO) register. AND the result with 0x7F for
a byte count between zero and 80.

Parity Options 2-9

Step 2. Read bit 7 in the SCSI Status Zero (SSTAT0) register to

determine if any bytes are left in the SCSI Input Data Latch

(SIDL) register. If bit 7 is set in SSTAT0, then the SCSI Input
Data Latch (SIDL) register is full.

Synchronous SCSI Receive –

Step 1. Subtract the seven least significant bits of the DMA Byte

Counter (DBC) register from the 7-bit value of the DMA FIFO
(DFIFO) register. AND the result with 0x7F for a byte count

between zero and 80.

Step 2. Read the SCSI Status One (SSTAT1) register and examine bits

[7:4], the binary representation of the number of valid bytes in
the SCSI FIFO, to determine if any bytes are left in the SCSI
FIFO.

Figure 2.2 LSI53C810A Host Interface Data Paths

PCI

Interface

DMA FIFO

(4-bytes x 20)

SODL Register SIDL Register

Asynchronous

SCSI Send

PCI

Interface

DMA FIFO

(4-bytes x 20)

SCSI InterfaceSCSI Interface

Asynchronous
SCSI Receive

PCI

Interface

DMA FIFO

(4-bytes x 20)

SODL Register

SODR Register

SCSI Interface

Synchronous

SCSI Send

PCI

Interface

DMA FIFO

(4-bytes x 20)

SCSI FIFO

SCSI Interface

Synchronous

SCSI Receive

2-10 Functional Description