LSI 53C770 (ULTRA FAST SCSI ctrl.) 53C770 Data Manual

TECHNICAL

MANUAL

LSI53C770
Ultra SCSI I/O
Processor

Version 2.1

March 2001

®

S14061

This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.

Document DB14-000161-00, First Edition (March 2001)
This document describes the LSI Logic LSI53C770 Ultra SCSI I/O Processor and
will remain the official reference source for all revisions/releases of this product
until rescinded by an update.

To receive product literature, visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.

Copyright © 1995–2001 by LSI Logic Corporation. All rights reserved.

TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, SCRIPTS, and TolerANT are trademarks or registered
trademarks of LSI Logic Corporation. All other brand and product names may be
trademarks of their respective companies.

ii

Audience

Organization

Preface

This technical manual provides reference information on the LSI53C770
Ultra SCSI I/O Processor. It contains a complete functional description
for the product and includes complete physical and electrical
specifications for it.

This manual assumes some prior knowledge of current and proposed
SCSI and PCI standards.

This document has the following chapters and appendix:

• Chapter 1, General Description

• Chapter 2, Functional Description

• Chapter 3, Signal Descriptions

• Chapter 4, Registers

• Chapter 5, Instruction Set of the I/O Processor

• Chapter 6, Electrical Characteristics

• Appendix A, Register Summary

Preface iii

Related Publications

For background information, please contact:

ANSI

11 West 42nd Street
New York, NY 10036
[phone]
Ask for document number X3.131-199X (SCSI-2)

Global Engineering Documents

15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
Ask for document number X3.131-1994 (SCSI-2) or X3.253

(SCSI-3 Parallel Interface)

ENDL Publications

14426 Black Walnut Court
Saratoga, CA 95070
[phone]
Document names:

Tutor

SCSI Bench Reference, SCSI Encyclopedia, SCSI

Prentice Hall

113 Sylvan Avenue
Englewood Cliffs, NJ 07632
[phone]
Ask for document number ISBN 0-13-796855-8,

the Small Computer System Interface

LSI Logic World Wide Web Home Page

www.lsil.com

PCI Special Interest Group

2575 N. E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]

iv Preface

SCSI: Understanding

Conventions Used in This Manual

The first time a word or phrase is defined in this manual, it is

The word

deassert

assert

means to drive a signal true or active. The word

means to drive a signal false or inactive. Signals that are active

italicized.

LOW end in a “/.”

Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.

Revision Record

Version Date Remarks

1.0 9/94 Preliminary.

2.0 7/96 Changed Fast-20 to Ultra SCSI throughout document.

2.1 3/01 All product names changed from SYM to LSI.

Preface v

vi Preface

Contents

Chapter 1 General Description

1.1 Benefits of Ultra SCSI 1-2

1.1.1 TolerANT®Technology 1-2

1.2 LSI53C770 Features Summary 1-3

1.2.1 Performance 1-3

1.2.2 Integration 1-4

1.2.3 Ease of Use 1-4

1.2.4 Flexibility 1-5

1.2.5 Reliability 1-5

1.2.6 Testability 1-6

1.3 Summary of New Features in the LSI53C770 1-8

Chapter 2 Functional Description

2.1 SCSI Core 2-1

2.1.1 DMA Core 2-2

2.2 SCRIPTS Processor 2-2

2.2.1 Internal SCRIPTS RAM 2-3

2.2.2 Designing an Ultra SCSI System 2-4

2.2.3 Using the SCSI Clock Doubler 2-5

2.2.4 Big/Little Endian Support 2-6

2.2.5 Big Endian Mode 2-7

2.2.6 Little Endian Mode 2-7

2.2.7 Loopback Mode 2-7

2.2.8 Parity Options 2-8

2.3 DMA FIFO 2-12

2.3.1 Data Path 2-12

2.3.2 DMA FIFO 2-13

2.3.3 Asynchronous SCSI Send 2-14

2.3.4 Synchronous SCSI Send 2-14

Contents vii

2.3.5 Asynchronous SCSI Receive 2-14

2.3.6 Synchronous SCSI Receive 2-15

2.4 Host Interface 2-15

2.4.1 Misaligned Transfers 2-15

2.4.2 Transfer Size Throttling 2-15

2.4.3 BERR/_TEA/ Pin Function 2-18

2.4.4 Functionality of BERR/_TEA/ in Master Mode 2-18

2.4.5 Functionality of BERR/_TEA/ in Slave Mode 2-18

2.4.6 Bus Retry 2-19

2.4.7 Noncache Line Burst 2-19

2.4.8 Cache Line Burst 2-19

2.4.9 Using the Back Off Signal to Relinquish the Bus 2-20

2.5 Bidirectional STERM/-TA/-ReadyIn/ 2-21

2.6 SCSI Bus Interface 2-23

2.6.1 SCSI Termination 2-23

2.6.2 Select/Reselect During Selection/Reselection 2-26

2.6.3 Synchronous Operation 2-26

2.6.4 Determining the Data Transfer Rate 2-27

2.6.5 Ultra SCSI Synchronous Data Transfers 2-28

2.7 Interrupt Handling 2-29

2.7.1 Polling vs. Hardware Interrupts 2-29

2.7.2 Registers 2-29

2.7.3 Fatal vs. Nonfatal Interrupts 2-31

2.7.4 Enabling Interrupts 2-31

2.7.5 Stacked Interrupts 2-32

2.7.6 Halting in an Orderly Fashion 2-33

2.7.7 Sample Interrupt Service Routine 2-34

Chapter 3 Signal Descriptions

Chapter 4 Registers

4.1 Register Descriptions 4-1

Chapter 5 Instruction Set of the I/O Processor

5.1 SCSI SCRIPTS 5-1

5.2 Block Move Instruction 5-3

5.2.1 First Dword 5-3

viii Contents

5.2.2 Second Dword 5-9

5.3 I/O Instructions 5-10

5.3.1 First Dword 5-10

5.3.2 Second Dword 5-17

5.4 Read/Write Instructions 5-18

5.4.1 First Dword 5-18

5.5 Transfer Control Instructions 5-22

5.5.1 First Dword 5-22

5.5.2 Second Dword 5-29

5.6 Memory Move Instructions 5-30

5.6.1 First Dword 5-31

5.6.2 Second Dword 5-32

Chapter 6 Electrical Characteristics

6.1 DC Characteristics 6-2

6.2 LSI Logic TolerANT Technology 6-6

6.3 AC Characteristics 6-10

6.4 Bus Mode 1 Slave Cycle 6-12

6.4.1 Bus Mode 1 Slave Read Sequence 6-12

6.4.2 Bus Mode 1 Slave Write Sequence 6-15

6.5 Bus Mode 1 Host Bus Arbitration 6-18

6.5.1 Bus Arbitration Sequence 6-18

6.6 Bus Mode 1 Fast Arbitration 6-21

6.6.1 Fast Arbitration Sequence 6-21

6.7 Bus Mode 1 Master Cycle 6-24

6.7.1 Bus Mode 1 Master Read Sequence 6-24

6.7.2 Bus Mode 1 Bus Master Write Sequence 6-28

6.8 Bus Mode 2 Slave Cycle 6-32

6.8.1 Bus Mode 2 Slave Read Sequence 6-32

6.8.2 Bus Mode 2 Slave Write Sequence 6-35

6.9 Bus Mode 2 Host Bus Arbitration 6-38

6.9.1 Bus Mode 2 Bus Arbitration Sequence 6-38

6.10 Bus Mode 2 Fast Arbitration 6-41

6.10.1 Bus Mode 2 Fast Arbitration Sequence 6-41

6.11 Bus Mode 2 Master Cycle 6-43

6.11.1 Bus Mode 2 Master Read Sequence 6-43

6.11.2 Bus Mode 2 Bus Master Write Sequence 6-47

Contents ix

6.12 Bus Mode 2 Mux Mode Cycle 6-50

6.12.1 Mux Mode Read Sequence 6-50

6.12.2 Mux Mode Write Sequence 6-54

6.13 Bus Mode 3 and 4 Slave Cycle 6-57

6.13.1 Bus Mode 3 and 4 Slave Read Sequence 6-57

6.13.2 Bus Mode 3 and 4 Slave Write Sequence 6-61

6.14 Bus Mode 3 and 4 Host Bus Arbitration 6-64

6.14.1 Bus Arbitration Sequence 6-64

6.15 Bus Mode 3 and 4 Fast Arbitration 6-67

6.15.1 Fast Arbitration Sequence 6-67

6.16 Bus Mode 3 and 4 Master Cycle 6-70

6.16.1 Bus Mode 3 and 4 Bus Master Read Sequence 6-70

6.16.2 Bus Mode 3 and 4 Bus Master Write Sequence 6-76

6.17 SCSI Timing Diagrams 6-82

6.18 Package Drawings 6-89

Appendix A Register Summary

Index

Customer Feedback

Figures

1.1 LSI53C770 Block Diagram 1-7

2.1 DMA FIFO Byte Lanes 2-12

2.2 LSI53C770 Data Paths 2-13

2.3 Transfer Size Throttling 2-17

2.4 SLACK/ Tied Back to STERM/, EA Bit Not Set 2-22

2.5 Bidirectional STERM/, EA Bit Set 2-22

2.6 LSI53C770 Differential Wiring Diagram 2-24

2.7 Regulated Termination 2-25

2.8 Determining the Synchronous Transfer Rate 2-27

3.1 LSI53C770 Pin Diagram, Bus Modes 1 and 2 3-2

3.2 LSI53C770 Pin Diagram, Bus Modes 3 and 4 3-3

5.1 Block Move Instruction Register 5-3

5.2 Block Move and Chained Block Move Instructions 5-9

x Contents

5.3 I/O Instruction Register 5-11

5.4 Read/Write Instruction Register 5-19

5.5 Transfer Control Instruction Register 5-24

5.6 Memory Move Instruction Register 5-31

6.1 Rise and Fall Time Test Conditions 6-8

6.2 SCSI Input Filtering 6-8

6.3 Hysteresis of SCSI Receiver 6-8

6.4 Input Current as a Function of Input Voltage 6-9

6.5 Output Current as a Function of Output Voltage 6-9

6.6 Clock Waveform 6-10

6.7 Reset Input Waveforms 6-11

6.8 Interrupt Output Waveforms 6-11

6.9 Bus Mode 1 Slave Read Waveforms 6-13

6.10 Bus Mode 1 Slave Write Waveforms 6-16

6.11 Bus Mode 1 Host Bus Arbitration 6-19

6.12 Bus Mode 1 Fast Arbitration 6-22

6.13 Bus Mode 1 Bus Master Read (Cache Line Burst
Requested but not Acknowledged) 6-25

6.14 Bus Mode 1 Bus Master Read (Cache Line Burst) 6-26

6.15 Bus Mode 1 Bus Master Write (Cache Line Burst
Requested but not Acknowledged) 6-29

6.16 Bus Mode 1 Bus Master Write (Cache Line Burst) 6-30

6.17 Bus Mode 2 Slave Read Waveforms 6-33

6.18 Bus Mode 2 Slave Write Waveforms 6-36

6.19 Bus Mode 2 Host Bus Arbitration 6-39

6.20 Bus Mode 2 Fast Arbitration 6-42

6.21 Bus Mode 2 Bus Master Read (Cache Line Burst
Requested but not Acknowledged) 6-44

6.22 Bus Mode 2 Bus Master Read (Cache Line Burst) 6-45

6.23 Bus Mode 2 Bus Master Write (Cache Line Burst
Requested but not Acknowledged) 6-48

6.24 Mux Mode Read Cycle (Cache Line Burst Requested
but not Acknowledged) 6-51

6.25 Mux Mode Read Cycle (Cache Line Burst) 6-52

6.26 Mux Mode Write Cycle (Noncache Line Burst) 6-55

6.27 Mux Mode Write Cycle (Cache Line Burst) 6-56

6.28 Bus Mode 3 and 4 Slave Read Cycle 6-59

6.29 Bus Mode 3 and 4 Slave Write Cycle 6-62

Contents xi

Tables

6.30 Bus Modes 3 and 4 Host Bus Arbitration 6-65

6.31 Bus Mode 3 and 4 Fast Arbitration 6-68

6.32 Bus Mode 3 and 4 Bus Master Read
(Nonpreview of Address) 6-71

6.33 Bus Mode 3 and 4 Bus Master Read
(Preview of Address) 6-72

6.34 Bus Mode 4 Bus Master Read (Cache Line Burst) 6-74

6.35 Bus Mode 3 and 4 Bus Master Write
(Nonpreview of Address) 6-77

6.36 Bus Mode 3 and 4 Bus Master Write
(Preview of Address) 6-78

6.37 Bus Mode 4 Bus Master Write (Cache Line Burst) 6-80

6.38 Initiator Asynchronous Send 6-82

6.39 Initiator Asynchronous Receive 6-82

6.40 Target Asynchronous Send 6-83

6.41 Target Asynchronous Receive 6-83

6.42 Initiator and Target Synchronous Transfers 6-84

6.43 208-Pin PQFP (P9) Mechanical Drawing (Sheet 1 of 2) 6-89

2.1 Big and Little Endian Addressing 2-6

2.2 Bits Used in Parity Control and Generation 2-8

2.3 SCSI Parity Control 2-10

2.4 Parity Errors and Interrupts 2-11

3.1 Power and Ground Signals 3-4

3.2 Address and Data Signals 3-4

3.3 Arbitration Signals 3-6

3.4 System Signals 3-7

3.5 Interface Control Signals 3-9

3.6 Additional Interface Signals 3-12

3.7 SCSI Signals 3-14

4.1 LSI53C770 Register Address Map 4-2

4.2 Examples of Synchronous Transfer Periods and
Rates for SCSI-1 4-17

4.3 Examples of Transfer Periods and Rates for Fast
SCSI and Ultra SCSI 4-18

4.4 SCSI Synchronous Data FIFO Word Count 4-27

4.5 SCRIPTS RAM Access 4-43

xii Contents

4.6 FC[2:1], TM[2:1] Pin Function 4-49

4.7 FC0_TM0 Pin Function 4-51

5.1 SCSI Information Transfer Phase 5-8

5.2 Read/Write Instructions 5-20

5.3 Transfer Control Instructions 5-23

5.4 SCSI Phase Comparisons 5-26

6.1 Absolute Maximum Stress Ratings 6-2

6.2 Operating Conditions 6-2

6.3 SCSI Signals SD[15:0], SDP0/, REQ/, MSG/, I_O/,
C_D/, ATN/, ACK/, BSY/, SEL/, RST/, SDP1 6-3

6.4 Input Signals—BG/-HLDAI/, BOFF/, RESET/, CS/,
BS[2:0]/, BCLK, SCLK, AUTO/, DIFFSENS 6-3

6.5 Input Signal—TSTIN/ 6-3

6.6 Output Signals—SDIR[15:0], SDIRP0, BSYDIR,
SELDIR, RSTDIR, TGS, IGS, SDIRP1 6-4

6.7 Output Signals—FETCH/, IRQ/, TSTOUT 6-4

6.8 Output Signal—SLACK/-READYO/, MASTER/, MAC/ 6-4

6.9 3-State Output Signals—A[31:7], FC[2:0]-TM[2:0],
SC[1:0], UPSO-TT0/, CBREQ/-TT1/, BR/-HOLD/ 6-5

6.10 Bidirectional Signals—A[6:0], D[31:0], DP[3:0],
DS/-DLE/, AS/-TS/-ADS/, R_W/, BE0, BE1/, SIZ[1:0],
BHE/-BE2, SIZ1-BE3, BERR/-TEA/, HALT/-TIP/,
BGACK-BB/, CBACK/-TBI/, STERM/-TA/-READYI/,
GPIO[4:0] 6-5

6.11 Capacitance 6-5

6.12 TolerANT Active Negation Technology Electrical
Characteristics 6-7

6.13 Clock Timing 6-10

6.14 Reset Input Timing 6-11

6.15 Interrupt Output Timing 6-11

6.16 Bus Mode 1 Slave Read Timing 6-14

6.17 Bus Mode 1 Slave Write Timing 6-17

6.18 Bus Mode 1 Host Bus Arbitration Timing 6-20

6.19 Bus Mode 1 Fast Arbitration Timing 6-23

6.20 Bus Mode 1 Master Read Timing 6-27

6.21 Bus Mode 1 Master Write Timing 6-31

6.22 Bus Mode 2 Slave Read Timing 6-34

6.23 Bus Mode 2 Slave Write Timing 6-37

Contents xiii

6.24 Bus Mode 2 Host Bus Arbitration Timing 6-40

6.25 Bus Mode 2 Fast Arbitration Timing 6-42

6.26 Bus Mode 2 Bus Master Read Timing 6-46

6.27 Bus Mode 2 Bus Master Write Timing 6-49

6.28 Bus Mode 2 Mux Mode Read Timing 6-53

6.29 Bus Mode 2 Mux Mode Write Timing 6-57

6.30 Bus Mode 3 and 4 Slave Read Timing 6-60

6.31 Bus Mode 3 and 4 Slave Write Timing 6-63

6.32 Bus Mode 3 and 4 Bus Arbitration Timing 6-66

6.33 Bus Mode 3 and 4 Fast Arbitration 6-69

6.34 Bus Mode 3 and 4 Bus Master Read Timing 6-73

6.35 Bus Mode 4 Bus Master Read Timing
(Cache Line Burst) 6-75

6.36 Bus Mode 3 and 4 Bus Master Write Timing 6-79

6.37 Bus Mode 4 Bus Master Write Timing
(Cache Line Burst) 6-81

6.38 Initiator Asynchronous Send Timing 6-82

6.39 Initiator Asynchronous Receive Timing 6-83

6.40 Target Asynchronous Send Timing 6-83

6.41 Target Asynchronous Receive Timing 6-84

6.42 SCSI-1 Transfers (SE 5.0 Mbytes/s) 6-84

6.43 SCSI-1 Transfers (Differential, 4.17 Mbytes/s) 6-85

6.44 SCSI-2 Fast Transfers (10.0 Mbytes/s, 40 MHz Clock) 6-85

6.45 SCSI-2 Fast Transfers (10.0 Mbytes/s, 50 MHz Clock) 6-86

6.46 Ultra SCSI SE Transfers (20.0 Mbytes/s
(8-Bit Transfers) or 40.0 Mbytes/s (16-Bit Transfers),
80 or 100 MHz Clock) 6-87

6.47 Ultra SCSI Differential Transfers (20.0 Mbytes/s
(8-Bit Transfers) or 40.0 Mbytes/s (16-Bit Transfers),
80 or 100 MHz Clock) 6-88

A.1 LSI53C770 Register Summary A-1

xiv Contents

Chapter 1
General Description

This chapter contains the following sections:

•

Section 1.1, “Benefits of Ultra SCSI”

• Section 1.2, “LSI53C770 Features Summary”

• Section 1.3, “Summary of New Features in the LSI53C770”

The LSI53C770 Ultra SCSI I/O Processor is a member of the
LSI53C7XX family of intelligent, single chip, third generation SCSI host
adapters. A high-performance SCSI core and an intelligent 16- or 32-bit
bus master DMA core are integrated with a SCSI SCRIPTS™ processor
to accommodate the flexibility requirements of not only SCSI-1, SCSI-2,
and future SCSI standards. The LSI53C770 solves the protocol overhead
problems that have plagued all previous intelligent and nonintelligent
adapter designs.

The LSI53C770 is designed to completely implement a multithreaded I/O
algorithm in either a workstation or file server environment, completely
free of processor intervention except at the end of an I/O transfer. In
addition, the LSI53C770 provides automatic relocation of SCRIPTS, and
requires no dynamic alteration of SCRIPTS instructions at the start of an
I/O operation. All of the SCRIPTS code may be placed on a PROM. The
LSI53C770 allows easy firmware upgrades and is SCRIPTS compatible
with the LSI53C710 and the LSI53C8XX family.

The LSI53C770 supports four different host processor interfaces, or bus
modes. Bus Mode 1 closely resembles the Motorola 68030 interface, and
Bus Mode 2 closely resembles the Motorola 68040 interface. Bus Mode 3
closely resembles the Intel 80386SX interface; the 16-bit host interface
should be enabled in this mode. Finally, Bus Mode 4 closely resembles
the 80386DX interface. Bus Modes 1, 2, and 4 support both the big and

LSI53C770 Ultra SCSI I/O Processor 1-1

little endian byte ordering schemes and Bus Mode 3 supports little
endian byte ordering, for a total of seven operating modes. Select the
modes by using the bus mode select pins (BS[2:0]).

The LSI53C770 is a pin-for-pin replacement of the LSI53C720. It
performs Ultra SCSI data transfers at 20 Mbytes/s (8-bit) or 40 Mbytes/s
(16-bit). It is packaged in a 208-pin quad flat pack, and performs both
Single-Ended (SE) and differential transfers.

1.1 Benefits of Ultra SCSI

Ultra SCSI is an extension of the SCSI-3 standard that expands the
bandwidth of the SCSI bus and allows faster synchronous SCSI transfer
rates. When enabled, Ultra SCSI performs 20 megatransfers during an
I/O operation, resulting in approximately twice the synchronous transfer
rates of fast SCSI-2. The LSI53C770 can perform 8-bit, Ultra SCSI
synchronous transfers as fast as 20 Mbytes/s. This advantage is most
noticeable in heavily loaded systems or large block size requirements,
such as video on-demand and image processing.

An advantage of Ultra SCSI is that it significantly improves SCSI
bandwidth while preserving existing hardware and software investments.
The LSI53C770 is compatible with all existing LSI53C720 and
LSI53C720SE software; the only changes required are to enable the chip
to perform synchronous negotiations for Ultra SCSI rates. The
LSI53C770 can use the same board socket as an LSI53C720, with the
addition of an 80/100 MHz SCLK or internal SCSI clock doubler (clock
doubler works at 40 to 50 MHz input) which provides the correct
frequency when transferring synchronous SCSI data at 50 ns transfer
rates. Some changes to existing cabling or system designs may be
needed to maintain signal integrity at Ultra SCSI synchronous transfer
rates. These design issues are discussed in

Chapter 2.

1.1.1 TolerANT®Technology

The LSI53C770 features TolerANT technology, which includes active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation actively drives SCSI REQ, ACK, Data, and
Parity signals HIGH by transistors on each pin. The 48 mA drivers
actively force the SCSI bus signal to the HIGH (negated) state faster than

1-2 General Description

passive pull-up drivers. TolerANT receivers filter SCSI bus signals to
eliminate unwanted transitions, without the long signal delay associated
with RC-type input filters. This improved driver and receiver technology
helps eliminate the double clocking of data, the single biggest reliability
issue with SCSI operations. TolerANT technology improves data integrity
in unreliable cabling environments where other devices would be subject
to data corruption. The benefits of TolerANT technology include
increased immunity to noise when the signal is going HIGH, increased
performance due to balanced duty cycles, and improved Fast SCSI
transfer rates. Setting bit 7 in the SCSI Test Register Three (STEST3)
register enables active negation. It can be used in both SE and
differential mode. TolerANT technology is compatible with both the
Alternative One and Alternative Two termination schemes proposed by
the American National Standards Institute.

1.2 LSI53C770 Features Summary

This section provides an overview of the LSI53C770 features and
benefits. It contains information on Performance, Integration, Ease of
Use, Flexibility, Reliability, and Testability.

1.2.1 Performance

To improve performance, the LSI53C770:

• Performs Ultra SCSI synchronous transfers as fast as 40 Mbytes/s

(with wide SCSI)

• Includes 4 Kbytes internal RAM for SCRIPTS instruction storage

• Supports variable block size and scatter/gather data transfers

• Supports 16- and 32-bit data bursts with variable burst lengths

• Performs memory-to-memory DMA transfers in excess of

44 Mbytes/s

• Minimizes SCSI I/O start latency

• Performs complex bus sequences without interrupts, including

restore data pointers

• Reduces ISR overhead with unique interrupt status reporting

• Performs memory transfers in excess of 100 Mbytes/s (@ 33 MHz)

LSI53C770 Features Summary 1-3

• Uses a 96-byte DMA FIFO to support cache line bursting

• Uses up to 16 levels of synchronous SCSI offset for optimum speed

• Provides an additional 32 scratch registers

1.2.2 Integration

Features of the LSI53C770 which ease integration include:

• Full 16- or 32-bit DMA bus master

• High-performance wide SCSI core

• RISC-based SCSI SCRIPTS processor

• Allows intelligent host adapter performance on a mainboard

1.2.3 Ease of Use

The LSI53C770:

• Reduces SCSI development effort

• Supports big and little endian environments

• Uses existing LSI53C720 SCRIPTS

matching during Ultra SCSI transfers

• Includes development tools and sample SCSI SCRIPTS

• Supports maskable and pollable interrupts

• Supports wide SCSI, A or P cable, and up to 16 devices

• Interfaces with seven different host processor buses, including

Motorola (680X0 family) and Intel (80X86 family)

• Supports odd byte block sizes in conjunction with wide SCSI

• Provides three programmable SCSI timers: Select/Reselect,

Handshake-to-Handshake, and General Purpose. The time-out

period is programmable from 100 µs to greater than 1.6 seconds.

• The handshake-to-handshake and general purpose timers use a

scale factor to increase the amount of time before expiration.

• The handshake-to-handshake timer has an optional mode that allows

it to operate as a bus activity timer for all SCSI transfers.

1-4 General Description

1.2.4 Flexibility

The LSI53C770 provides:

• A high level programming interface (SCSI SCRIPTS)

• Tailored SCSI sequences to be executed from main memory or from

a host adapter board’s local memory

• Use of flexible sequences to tune I/O performance or to adapt to

unique SCSI devices

• Changes in the logical I/O interface definition

• Low level programmability (register oriented)

• A target to disconnect and later reselect with no interrupt to the

system processor

• A multithreaded I/O algorithm to be executed in SCSI SCRIPTS with

fast I/O context switching

• Relative jumps

• Indirect fetching of DMA address and byte counts so that SCRIPTS

can be placed in a PROM

• Separate SCSI and system clocks

1.2.5 Reliability

• Double the SCSI clock input during Ultra SCSI transfer modes

• A new SSAID (SCSI Selected as ID) register

Enhanced reliability features of the LSI53C770 include:

• TolerANT SCSI driver and receiver technology

• 2 kV ESD protection on SCSI signals

• Typical 350 mV SCSI bus hysteresis

• Protection against bus reflections due to impedance mismatches

• Controlled bus assertion times (reduces RFI, improves reliability, and

eases FCC certification)

• Latch-up protection greater than 150 mA

• Voltage feed-through protection (minimum leakage current through

SCSI pads)

LSI53C770 Features Summary 1-5

1.2.6 Testability

• 20% of pins power and ground

• Ground isolation of I/O pads and chip logic

The LSI53C770 provides improved testability through:

• Access to all SCSI signals through programmed I/O

• SCSI loopback diagnostics

• Self-selection capability

• SCSI bus signal continuity checking

• Support for single step mode operation

1-6 General Description

Figure 1.1 illustrates the LSI53C770 Block Diagram.

Figure 1.1 LSI53C770 Block Diagram

(16 levels)

SCSI Core

DMA Core

DMA FIFO
(96 bytes)

SCSI
FIFO

SCSI Data

Sync Control

Async Control

SCSI Registers

Test and Reserved Registers

DMA Registers

I/O Control

SCSI Control

SCSI

Sequences

SCRIPTS

RAM

SCRIPTS
Processor

Host Bus

Control

Host Data Host Control

LSI53C770 Features Summary 1-7

1.3 Summary of New Features in the LSI53C770

For more information on enabling or using these new features, please
refer to the chapter indicated with each topic.

• Support for Ultra SCSI data transfers (

Chapter 6)

Chapter 2, Chapter 4, and

• DMA FIFO increased to 96 bytes (Chapter 2)

• SCSI offset increased to 16 levels (Chapter 4, SCSI Transfer

(SXFER) register description)

• Internal SCRIPTS RAM (Chapter 2, Chapter 4)

• Expanded timers (Chapter 4, SCSI Timer Register 0 (STIME0) and

SCSI Timer Register One (STIME1) register descriptions)

• Expanded SCSI Longitudinal Parity (SLPAR) register (Chapter 4,

SCSI Longitudinal Parity (SLPAR) register description)

• Additional Read-Modify-Write Instructions (Chapter 5, Read/Write

instructions)

• SCSI Clock Doubler (Chapter 2, Chapter 4)

• SCSI Selector ID Register (SSID) register (Chapter 4)

• Fairness timer update (Chapter 4, DMA Mode (DMODE) register

description)

• Additional 32 Scratch registers (Chapter 4)

• Vendor unique enhancements (Chapter 4, SCSI Control Register

Two (SCNTL2) register description)

• DIFFSENSE Sense bit to detect a differential System (Chapter 5,

SCSI Status Two (SSTAT2) register description)

1-8 General Description

Chapter 2
Functional Description

The LSI53C770 is composed of three interrelated functional blocks: the
SCSI Core, the DMA Core, and the SCRIPTS Processor.

This chapter contains the following sections:

•

Section 2.1, “SCSI Core”

• Section 2.2, “SCRIPTS Processor”

• Section 2.3, “DMA FIFO”

• Section 2.4, “Host Interface”

• Section 2.5, “Bidirectional STERM/-TA/-ReadyIn/”

• Section 2.6, “SCSI Bus Interface”

• Section 2.7, “Interrupt Handling”

This chapter describes the major functional aspects of the chip. For
detailed information on implementing or using specific features, refer to
later chapters in this manual. Chapter 3 contains detailed information on
the LSI53C770 pins. Chapter 4 describes all of the operating registers
and bits. Chapter 5 describes the LSI53C770 instruction set, and

Chapter 6 contains the chip electrical specifications and timing data.

2.1 SCSI Core

The SCSI core supports the SCSI-2 fast and wide bus. It supports
synchronous transfer rates of up to 20 Mbytes/s or 40 Mbytes/s in
Ultra SCSI, and asynchronous transfer rates up to 10 Mbytes/s. The
programmable SCSI interface makes it easy to “fine tune” the system for
specific mass storage devices or advanced SCSI requirements.

LSI53C770 Ultra SCSI I/O Processor 2-1

2.1.1 DMA Core

The SCSI core offers low level register access or a high level control
interface. Like first generation SCSI devices, the LSI53C770 SCSI core
can be accessed as a register oriented device. The ability to sample
and/or assert any signal on the SCSI bus can be used in error recovery
and diagnostic procedures. In support of loopback diagnostics, the SCSI
core may perform a self-selection and operate as both an initiator and a
target. This can test all data paths in the chip. The LSI53C770 uses an
“AND tree” to test the SCSI pins for physical connection to the board or
the SCSI bus.

Unlike previous generation devices, the SCSI core can be controlled by
the SCRIPTS processor, a high level logical interface optimized for SCSI
protocol. SCRIPTS routines controlling the SCSI core are fetched out of
the main host memory or local PROM. These commands instruct the
SCSI core to select, reselect, disconnect, wait for a disconnect, transfer
information, change bus phases and in general, implement all aspects of
the SCSI protocol.

The DMA core is a bus master DMA device that is made to attach to Intel
(80386SX and 80386DX), and Motorola (68030 and 68040) processors.

The LSI53C770 supports 16- or 32-bit memory and automatically
supports misaligned DMA transfers. A 96-byte FIFO allows the
LSI53C770 to burst two, four, eight, or 16 Dwords across the memory
bus interface. This DMA interface does not support dynamic bus sizing.

The DMA core communicates with the SCSI core through the SCRIPTS
processor, which supports uninterrupted scatter/gather memory
operations.

2.2 SCRIPTS Processor

The SCSI SCRIPTS processor allows both DMA and SCSI commands
to be fetched from host memory or internal SCRIPTS RAM. Algorithms
written in SCSI SCRIPTS control the actions of the SCSI and DMA
cores, which are executed from 16- or 32-bit system memory. The
SCRIPTS processor executes complex SCSI bus sequences
independently of the host CPU.

2-2 Functional Description

The SCRIPTS processor can begin a SCSI I/O operation in
approximately 500 ns. This compares with 2–8 ms required for traditional
intelligent host adapters. The SCRIPTS processor supports customized
algorithms to tune SCSI bus performance, adjust to new bus device
types (i.e. scanners, communication gateways, etc.), or incorporate
changes in the SCSI logical bus definitions without sacrificing I/O
performance. SCSI SCRIPTS are hardware independent, so they can be
used interchangeably on any host or CPU system bus.

2.2.1 Internal SCRIPTS RAM

The LSI53C770 has 4 Kbytes (1000 x 32 bits) of internal, general
purpose RAM. The RAM is designed for SCRIPTS program storage, but
is not limited to this type of information. When the chip fetches SCRIPTS
instructions or Table Indirect information from the internal RAM, these
fetches remain internal to the chip and do not use the host bus. Other
types of access to the RAM by the LSI53C770 use the host bus as if
they were external accesses. When the internal RAM is enabled, the
LSI53C770 uses the shadowed
register as the base address of the RAM when bit 0 is set in the Chip

Test Five (CTEST5) register.

The internal RAM can be enabled and used in the following ways:

Scratch Register A (SCRATCHA)

• Register based through indexed addressing.

• Increased chip select address space that includes support for the

chip registers and internal RAM with a single chip select pin.

• An additional chip select pin supporting only internal RAM with the

original Chip Select pin supporting only the chip registers.

The register based method allows use of the SCRIPTS RAM in existing
LSI53C720 designs without hardware changes. To use this method, clear

Chip Test Five (CTEST5), bit 2 and set Chip Test Five (CTEST5), bit 1.

The internal RAM is mapped into the chip registers using indexed
addressing in a shadowed Scratch Register B (SCRATCHB) register. The
RAM replaces the Scratch Registers C–J (SCRATCHC–J) registers, and
may optionally be used as a block of scratchpad RAM. When the chip
determines that a SCRIPTS address is in the internal RAM space, the
opcode fetch sequence accesses the internal RAM without using the
host bus. Indirect and table indirect functions also determine if the
address is contained in internal RAM space and fetch data from the RAM

SCRIPTS Processor 2-3

without host bus access. Read-Modify-Write operations or Memory Move
instructions can be used to modify the RAM while SCRIPTS are running,
but the host cannot access the RAM during SCRIPTS operation.

The increased chip select address space method defines 4 Kbyte
address space for the chip registers and the 4 Kbyte space for the
SCRIPTS RAM. To enable this mode, set Chip Test Five (CTEST5), bit 2
and clear Chip Test Five (CTEST5), bit 1. The registers are located at
addresses 0x0000 through 0x007F, repeating at intervals of 128 bytes
until the 4 K byte boundary. The RAM occupies addresses 0x1000
through 0x1FFF. The RAM is accessible by the host during SCRIPTS
execution, but up to seven additional wait-states may be added to a slave
read or write access if it occurs while an internal SCRIPTS access is in
progress. Read-Modify-Write operations or Memory Move instructions
can be used to modify the RAM while SCRIPTS are running.

An additional chip select pin, the RAMCS/ pin, can be used to define a
4 Kbyte address space for the internal RAM by setting bits 1 and 2 of
the Chip Test Five (CTEST5) register. The RAM is accessible by the host
during SCRIPTS execution, but up to seven additional wait-states may
be added to a slave read or write access if it occurs while an internal
SCRIPTS access is in progress. Read-Modify-Write operations or
Memory Move instructions can be used to modify the RAM while
SCRIPTS are running.

2.2.2 Designing an Ultra SCSI System

Migrating an existing SE SCSI design from SCSI-2 to Ultra SCSI requires
minor software modifications as well as consideration for some hardware
design guidelines. Since Ultra SCSI is based on existing SCSI standards,
it can use existing software programs as long as the software is able to
negotiate for Ultra SCSI synchronous transfer rates.

In the area of hardware, the primary area of concern in SE systems is
to maintain signal integrity at high data transfer rates. To assure reliable
operation at Ultra SCSI transfer speeds, follow the system design
parameters recommended in the SCSI-3 Fast-20 Parallel Interface draft
standard. Chapter 6 contains Ultra SCSI timing information. In addition
to the guidelines in the draft standard, make the following software and
hardware adjustments to accommodate Ultra SCSI transfers:

2-4 Functional Description

• Set the Ultra Enable bit to enable Ultra SCSI transfers. (SCSI Control

Three (SCNTL3), bit 7).

• Set the TolerANT Enable bit, bit 7 in the SCSI Test Register Three

(STEST3) register whenever the Ultra SCSI Enable bit is set.

• Do not extend the SREQ/SACK filtering period with SCSI Test

Register Two (STEST2), bit 1.

• Use an 80/100 MHz SCSI clock or enable the SCSI clock doubler

(clock doubler works at 40 to 50 MHz input) using bits 2 and 3 of the

SCSI Test Register One (STEST1) register. Set the halt SCSI clock

(HSC) bit in SCSI Test Register Three (STEST3) before switching to
the doubled SCSI clock.

2.2.3 Using the SCSI Clock Doubler

The LSI53C770 can double the frequency of a 40–50 MHz SCSI clock,
allowing the system to perform Ultra SCSI transfers in systems that do
not have 80 MHz clock input. This option is user-selectable with bit
settings in the SCSI Test Register One (STEST1), SCSI Test Register

Three (STEST3), and SCSI Control Three (SCNTL3) registers. At

power-on or reset, the doubler is disabled and powered down. Follow
these steps to use the clock doubler:

1. Set the SCLK Doubler Enable bit (SCSI Test Register One

(STEST1), bit 3).

2. Wait 20 µs.

3. Halt the SCSI clock by setting the Halt SCSI Clock bit (SCSI Test

Register Three (STEST3), bit 5).

4. Set the clock conversion factor using the SCF and CCF fields in the

SCSI Control Three (SCNTL3) register.

5. Set the SCLK Doubler Select bit (SCSI Test Register One (STEST1),

bit 2).

6. Clear the Halt SCSI Clock bit.

SCRIPTS Processor 2-5

2.2.4 Big/Little Endian Support

The Bus Mode Select pin gives the LSI53C770 the flexibility of operating
with either big or little endian byte orientation. Internally, in either mode,
the byte lanes of the DMA FIFO and registers are not modified. The
LSI53C770 supports byte, word, and Dword slave accesses in both big
and little endian modes (word accesses must be word aligned).

When a Dword is accessed, no repositioning of the individual bytes is
necessary, since Dwords are addressed by the address of the least
significant byte. SCRIPTS always uses Dwords in 32-bit systems, so
compatibility is maintained between systems using different byte
orientations. When a word is accessed, individual bytes must be
repositioned. Internally, the LSI53C770 adjusts the byte control logic of
the DMA FIFO and register decodes to access the appropriate byte
lanes. The registers always appear on the same byte lane, but the
address of the register are repositioned. Words are addressed by the
address of the least significant byte. Big/little endian mode selection has
the most effect on individual byte access, as illustrated in

Table 2.1 Big and Little Endian Addressing

Table 2.1.

System Data Bus

LSI53C770 Pins

Register

Little Endian Address

Big Endian Address

Note: The LSI53C770 supports big endian addressing in 16-bit

systems with Bus Modes 1 and 2 only.

Data to be transferred between system memory and the SCSI bus
always start at address zero and continue through address ‘n’ - there is
no byte ordering in the chip. The first byte in from the SCSI bus goes to
address 0, the second to address 1, etc. Going out onto the SCSI bus,
address zero is the first byte out on the SCSI bus, address 1 is the
second byte, etc.

2-6 Functional Description

[31:24] [23:16] [15:8] [7:0]

[31:24] [23:16] [15:8] [7:0]

SCNTL3 SCNTL2 SCNTL1 SCNTL0

0x03 0x02 0x01 0x00

0x00 0x01 0x02 0x03

Correct SCRIPTS are generated if the SCRIPTS compiler is run on a
system that has the same byte ordering as the target system. Any
SCRIPTS patching in memory must patch the instruction in the order that
the SCRIPTS processor expects it.

Software drivers for the LSI53C770 should access registers by their
logical name (i.e., “SCNTL0”) rather than by their address. The logical
name should be equated to the register’s big endian address in big
endian mode (SCNTL0 = 0x03), and its little endian address in little
endian mode (SCNTL0 = 0x00). This way, there is no change to the
software when moving from one mode to the other; only the equate
statement setting the operating modes needs to be changed. Addressing
of registers from within a SCRIPTS instruction is independent of bus
mode. Internally, the LSI53C770 always operates in little endian mode.

2.2.5 Big Endian Mode

Big endian addressing is used primarily in designs based on Motorola
processors. The LSI53C770 treats D[31:24] as the lowest physical
memory address. The register map is left justified (Address 0x03 =
SCNTL0).

2.2.6 Little Endian Mode

Little endian is used primarily in designs based on Intel processors. This
mode treats D[7:0] as the lowest physical memory address. The register
map is right justified (Address 0x00 = SCNTL0) as detailed in

2.2.7 Loopback Mode

The LSI53C770 loopback mode allows testing of both initiator and target
functions and, in effect, lets the chip talk to itself. This allows diagnostic
testing of the DMA and SCSI cores, the SCRIPTS processor, and all
internal data paths. When the Loopback Enable bit is set in the SCSI

Test Register Two (STEST2) register, the LSI53C770 allows control of all

SCSI signals, whether it is operating in initiator or target mode.

SCRIPTS Processor 2-7

Table 2.1.

2.2.8 Parity Options

The LSI53C770 implements a flexible parity scheme that allows control
of the parity sense, allows parity checking to be turned on or off, and has
the ability to deliberately send a byte with bad parity over the SCSI bus
to test parity error recovery procedures. The following bits are involved
in parity control and observation:

Table 2.2 Bits Used in Parity Control and Generation

Bit Name Location Description

Assert ATN/ on
Parity Errors

Enable Parity
Generation

Enable Parity
Checking

Assert Even
SCSI Parity

Disable Halt on
ATN/ or a Parity
Error (Target
Mode Only)

Enable Parity
Error Interrupt

SCSI Control Zero
(SCNTL0), bit 1

SCSI Control Zero
(SCNTL0), bit 2

SCSI Control Zero
(SCNTL0), bit 3

SCSI Control One
(SCNTL1), bit 2

SCSI Control One
(SCNTL1)

, bit 5

SCSI Interrupt
Enable Zero
(SIEN0), bit 0

Parity Error SCSI Interrupt

Status Zero
(SIST0), bit 0

Status of SCSI
Parity Signal

SCSI Status Zero
(SSTAT0), bit 0 and
SCSI Status Two
(SSTAT2), bit 0

Causes the LSI53C770 to automatically assert SCSI ATN/
when it detects a parity error (on either the SCSI or the data
bus) while operating as an initiator.

Determines whether the LSI53C770 generates parity sent to
the SCSI bus or allows parity to “flow through” the chip
to/from the SCSI bus and system bus.

Enables the LSI53C770 to check for parity errors. The
LSI53C770 checks for odd parity.

Determines the SCSI parity sense generated by the
LSI53C770 being sent to the host. Parity generation must be
enabled.

Causes the LSI53C770 to halt operations when a parity error
is detected in target mode.

Determines whether the LSI53C770 will generate an
interrupt when it detects a parity error.

This status bit is set whenever the LSI53C770 has detected
a parity error on either the SCSI bus or the system bus.

These status bits represent the live SCSI Parity Signal
(SDP0 and SDP1).

2-8 Functional Description

Table 2.2 Bits Used in Parity Control and Generation (Cont.)

Bit Name Location Description

Latched SCSI
Parity Signal

DMA FIFO Parity Chip Test Two

DMA FIFO Parity Chip Test Zero

SCSI FIFO Parity

SCSI Status One
(SSTAT1), bit 3 and
SCSI Status Two
(SSTAT2), bit 3

(CTEST2)

(CTEST0), bit 3

, bit 3

SCSI Test
Register One
(STEST1), bit 0

Generate
Receive Parity

Enable Host
Parity Checking

Chip Test Zero
(CTEST0), bit 4

Chip Test Four
(CTEST4), bit 3

These status bits contain the SCSI parity of the bytes
latched in the SCSI Input Data Latch (SIDL).

This status bit represents the parity bit in the DMA FIFO after
data is read from the FIFO by reading the Chip Test Six

(CTEST6) register.

This write only bit is written to the DMA FIFO after writing
data to the DMA FIFO by writing the Chip Test Six (CTEST6)
register.

This status bit represents the parity bit in the SCSI FIFO
after data is read from the FIFO by reading the SCSI Output

Data Latch (SODL) register, once bit 0 in SCSI Test Register
Three (STEST3) is asserted.

When this bit is set and the LSI53C770 is in parity
pass-through mode (bit 2 in the SCSI Control Zero

(SCNTL0) register is clear), parity received on the SCSI bus

will not pass through the DMA FIFO. New parity will be
generated.
When this bit is cleared, and parity pass through mode is
enabled (Bit 2 of
parity received on the SCSI bus will pass through the
LSI53C770 unmodified.

Setting this bit enables parity checking during slave write and
DMA read execution, if the Enable Parity Generation bit is
cleared (SCSI Control Zero (SCNTL0), bit 2).

SCSI Control Zero (SCNTL0) is clear),

SCRIPTS Processor 2-9

Table 2.3 describes the SCSI Parity Control functions.

Table 2.3 SCSI Parity Control

EPG1EPC2AESP3Description

0 0 0 Does not check for parity errors. Parity flows from DP[3:0] through the chip

to the SCSI bus when sending SCSI data. Parity flows from the SCSI bus
to DP[3:0] when receiving SCSI data. Asserts odd parity when sending SCSI
data.

0 0 1 Does not check for parity errors. Parity flows from DP[3:0] through the chip

to the SCSI bus when sending SCSI data. Parity flows from the SCSI bus
to DP[3:0] when receiving SCSI data. Asserts even parity when sending
SCSI data.

0 1 0 Checks for odd parity on both host and SCSI data when received. Parity

flows from DP[3:0] through the chip to the SCSI bus when sending SCSI
data. Parity flows from the SCSI bus to DP[3:0] when receiving SCSI data.
Asserts odd parity when sending SCSI data.

0 1 1 Checks for odd parity on both host and SCSI data when received. Parity

flows from DP[3:0] through the chip to the SCSI bus when sending SCSI
data. Parity flows from the SCSI bus to DP[3:0] when receiving SCSI data.
Asserts even parity when sending SCSI data.

1 0 0 Does not check for parity errors. Parity on DP[3:0] is ignored. Parity is

generated when sending SCSI data. Parity flows from the SCSI bus to the
chip, but is not asserted on DP[3:0] when receiving SCSI data. Asserts odd
parity when sending SCSI data.

1 0 1 Does not check for parity errors. Parity on DP[3:0] is ignored. Parity is

generated when sending SCSI data. Parity flows from the SCSI bus to the
chip, but is not asserted on DP[3:0] when receiving SCSI data. Asserts even
parity when sending SCSI data.

1 1 0 Checks for odd parity on SCSI data received. Parity on DP[3:0] is ignored.

Parity is generated when sending SCSI data. Parity flows from the SCSI bus
to the chip, but is not asserted on DP[3:0] when receiving SCSI data.
Asserts odd parity when sending SCSI data.

1 1 1 Checks for odd parity on SCSI data received. Parity on DP[3:0] is ignored.

Parity is generated when sending SCSI data. Parity flows from the SCSI bus
to the chip, but is not asserted on DP[3:0] when receiving SCSI data.
Asserts even parity when sending SCSI data.

1. Enable Parity Generation.

2. Enable Parity Checking.

3. Assert SCSI Even Parity.

2-10 Functional Description

Table 2.4 describes the options available when a parity error occurs.
Table 2.4 only applies when the Enable Parity Checking bit is set.

Table 2.4 Parity Errors and Interrupts

DHP PAR Description

0 0 Does not halt when a parity error occurs in target or initiator mode.

0 1 Does not halt when a parity error occurs in target or initiator mode.

1 0 Does not halt when a parity error occurs in target or initiator mode.

1 1 Halts when a parity error occurs in target mode and will generate an

interrupt in target or initiator mode

1. Initiator mode parity error interrupts are generated at the end of a block move.

1

SCRIPTS Processor 2-11

2.3 DMA FIFO

The LSI53C770 DMA FIFO is a 36 x 24 bit FIFO. It is divided into 4 byte
lanes, each 9 bits wide and 24 transfers deep, as shown in

Figure 2.1 DMA FIFO Byte Lanes

Transfers

Figure 2.1.

36-bits Wide

24

Deep

9-bits

Byte Lane 3

2.3.1 Data Path

When the LSI53C770 halts a data transfer operation, check the data path
to determine if any bytes remain that have not been transferred. The data
path through the LSI53C770 is dependent on whether data is being
moved into or out of the chip, and whether SCSI data is being transferred
asynchronously or synchronously.
to/from the SCSI bus in each of the different modes.

2-12 Functional Description

9-bits

Byte Lane 2

Figure 2.2 shows how data is moved

9-bits

Byte Lane 1

9-bits

Byte Lane 0

Figure 2.2 LSI53C770 Data Paths

Host Bus

Interface

DMA FIFO

(36-bits x 24)

SODL Register SIDL Register

Asynchronous

SCSI Send

Host Bus
Interface

DMA FIFO

(36-bits x 24)

SCSI InterfaceSCSI Interface

Asynchronous
SCSI Receive

2.3.2 DMA FIFO

In all types of transfers, the DMA FIFO is used in the data path. The DFE
bit in the
data in the DMA FIFO. To check the DMA FIFO, use the following
procedure. The other parts of the data path may contain data. To check
the data path, follow the steps indicated for each type of transfer.

Host Bus

Interface

DMA FIFO

(36-bits x 24)

SWIDE Register

SODL Register

SODR Register

SCSI Interface

Synchronous

SCSI Send

Host Bus

Interface

DMA FIFO

(36-bits x 24)

SWIDE Register

SCSI FIFO

SCSI Interface

Synchronous

SCSI Receive

DMA Status (DSTAT) register indicates whether there is any

2.3.2.1 Checking the Data Path

When transferring data from the host bus to the SCSI bus, subtract the
seven least significant bits of the DMA Byte Counter (DBC) register from
the 7-bit value of the DMA FIFO (DFIFO) register. AND the result with
0x7F for the byte count between zero and 96.

When transferring data from the SCSI bus to the host bus, subtract the
seven least significant bits of the DMA Byte Counter (DBC) register from
the 7-bit value of the DMA FIFO (DFIFO) register. AND the result with
0x7F and take the 2’s complement to obtain the byte count between
zero and 96.

DMA FIFO 2-13

2.3.3 Asynchronous SCSI Send –

1. Read the

(SSTAT2) registers to determine if any bytes are left in the SCSI
Output Data Latch (SODL) register. If bit 5 is set in the SCSI Status
Zero (SSTAT0) or SCSI Status Two (SSTAT2), then the least

significant byte or the most significant byte in the SCSI Output Data

Latch (SODL) register is full, respectively. Checking this bit also

reveals bytes left in the SCSI Output Data Latch (SODL) register
from a Chained Move operation with an odd byte count.

SCSI Status Zero (SSTAT0) and SCSI Status Two

2.3.4 Synchronous SCSI Send –

1. Read bit 5 in the SCSI Status Zero (SSTAT0) and SCSI Status Two

(SSTAT2) registers to determine if any bytes are left in the SCSI
Output Data Latch (SODL) register. If bit 5 is set in the SCSI Status
Zero (SSTAT0) or SCSI Status Two (SSTAT2), then the least

significant byte or the most significant byte in the SCSI Output Data

Latch (SODL) register is full, respectively. Checking this bit also

reveals bytes left in the SCSI Output Data Latch (SODL) register
from a Chained Move operation with an odd byte count.

2. Read bit 6 in the SCSI Status Zero (SSTAT0) and SCSI Status Two

(SSTAT2) registers to determine if any bytes are left in the SODR

register. If bit 6 is set in the SCSI Status Zero (SSTAT0) or SCSI

Status Two (SSTAT2), then the least significant byte or the most

significant byte in the SODR register is full, respectively.

2.3.5 Asynchronous SCSI Receive –

1. Read bit 7 in the SCSI Status Zero (SSTAT0) and SCSI Status Two

(SSTAT2) register to determine if any bytes are left in the SCSI Input
Data Latch (SIDL) register. If bit 7 is set in the SCSI Status Zero
(SSTAT0) or SCSI Status Two (SSTAT2), then the least significant

byte or the most significant byte is full, respectively.

2. If any wide transfers have been performed using the Chained Move

instruction, read the Wide SCSI Receive bit (SCSI Control Register

Two (SCNTL2), bit 0) to determine whether a byte is left in the SCSI
Wide Residue Data (SWIDE) register.

2-14 Functional Description

2.3.6 Synchronous SCSI Receive –

1. Read the

(SSTAT2) registers and examine bits [7:4], the binary representation

of the number of valid bytes in the SCSI FIFO, to determine if any
bytes are left in the SCSI FIFO.

2. If any wide transfers have been performed using the Chained Move

instruction, read the Wide SCSI Receive bit (SCSI Control Register

Two (SCNTL2), bit 0) to determine whether a byte is left in the SCSI
Wide Residue Data (SWIDE) register.

2.4 Host Interface

The LSI53C770 can be interfaced with both 680X0-type and 80X86-type
host processors using big or little endian byte ordering, for a total of
seven host bus interface modes. The modes are selected with the Bus
Mode Select pins, defined in

2.4.1 Misaligned Transfers

The LSI53C770 accommodates block data transfers beginning or ending
on odd byte or odd word addresses in system memory. Such addresses
are termed “misaligned.” An odd byte is defined as one in which the
address contains A0 = 1; an odd word is defined as one in which the
address contains A1 = 1. Misaligned transfers differ depending on the
type of transfer and whether they occur at the start or end of the transfer.
The LSI53C770 does not perform 24-bit transfers.

SCSI Status Zero (SSTAT0) and SCSI Status Two

Chapter 3.

2.4.2 Transfer Size Throttling

The burst control logic in the LSI53C770 includes an optional throttling
technique which does not allow a size change to occur within a bus
ownership. When size throttling is enabled, a new bus ownership occurs
each time the transfer changes size. When size throttling is enabled, bit 0
(Snoop Pins Mode) of the Chip Test Three (CTEST3) register should be
clear. Size throttling can be enabled or disabled using the Size Throttle
Enable bit, bit 7 in the DMA Control (DCNTL) register. Cache line
bursting is controlled with the Cache Burst Disable bit, bit 7 in the

Test Zero (CTEST0) register.

Host Interface 2-15

Chip

Figure 2.3 illustrates the function of the CDIS and STE bits. In Item 1,

cache line bursting is enabled and size throttling is disabled. Since the
starting address is at an odd byte boundary, the LSI53C770 lines up to
a word boundary by performing a single byte transfer in a single bus
ownership. Then, since the address is at an odd word boundary
(bit A1 = 1), the LSI53C770 lines up to a Dword boundary by performing
a single word transfer in a single bus ownership. At this point, one Dword
transfer is performed per bus ownership until the address bits line up to
a cache line boundary A(3) = A(2) = A(1) = A(0) = 0. Once aligned, the
cache line, Dword, word, and byte are transferred in a single bus
ownership to complete the transfer.

In Item 2, cache line bursting and size throttling are enabled. The
LSI53C770 lines up to a cache line boundary as described for Figure 2.3.
Once aligned, the cache line and Dword are transferred in the same bus
ownership since the two are considered the same size. The remaining
word and byte are transferred in two separate bus ownerships to
complete the transfer.

In Item 3, cache line bursting and size throttling are disabled. The
LSI53C770 completes eight transfers in one bus ownership, since the
burst length is set to eight. The remaining four transfers are transferred
in one bus ownership to complete the transfer.

In Item 4, cache line bursting is disabled and size throttling is enabled.
The LSI53C770 lines up to a Dword boundary. Since the address starts
on an odd byte boundary, the LSI53C770 lines up to a word boundary
by performing a single byte transfer in a single bus ownership. Then,
since the address is at an odd word boundary, the LSI53C770 lines up
to a Dword boundary by performing a single word transfer in a single bus
ownership. Once aligned, Dwords are transferred in the same bus
ownership. The remaining word and byte are transferred in separate bus
ownerships to complete the transfer.

2-16 Functional Description

Figure 2.3 Transfer Size Throttling

1. CDIS = 0, STE = 0 2. CDIS = 0, STE = 1

Address bits A1–A0

Address bits A5–A2

Address bits A5–A2

Note:

1. CDIS – Cache Burst Disable bit; STE = Size Throttle Enable bit.

2. At the start of the diagram, 38 bytes remain to be transferred.

3. The programmable burst length is 8.

4. Each of the shaded areas represents a new bus ownership.

5. The numbers within the shaded areas represent the number of transfers performed in the bus ownership.

6. For each alignment and bursting to be attempted, the entire transfer must be at least 31 bytes, this is
dictated by chip architecture.

00 01 10 01

0000

0001

0010

0011

0100

0101

0110

0111

1000

3. CDIS = 1, STE = 0 4. CDIS = 1, STE = 1

0000

0001

0010

0011

0100

0101

0110

1010

1000

1

1

1

1

Cache

(Four Transfers)

5

67

Address bits A1–A0

00 01 10 01

1

2

34

Address bits A5–A2

Address bits A5–A2

0000

0001

0010

0011

0100

0101

0110

0111

1000

Address bits A1–A0

00 01 10 01

0000

0001

0010

0011

0100

0101

0110

0111

1000

(Four Transfers)

Address bits A1–A0

00 01 10 01

1

Cache

67

1

11

11

1

1

1

5

1

1

2

3

4

5

6

7

8

Host Interface 2-17

2.4.3 BERR/_TEA/ Pin Function

This section describes the function of the BERR/_TEA/ pin on the
LSI53C770 SCSI I/O Processor.

2.4.4 Functionality of BERR/_TEA/ in Master Mode

In Master Mode, BERR/_TEA/ is used in conjunction with TA/ to indicate
to the LSI53C770 that one of the following conditions has occurred:

TEA/ TA/ Condition

1 1 Execute a wait-state

1 0 Normal cycle acknowledge

0 1 Bus error condition has occurred

0 0 Retry the current cycle after relinquishing the bus

1. In Bus Mode 1, the chip attempts a bus retry operation only if BERR/ asserts
in conjunction with HALT/.

2. In Bus Mode 2, the chip attempts a bus retry operation if TEA/ asserts in
conjunction with TA/.

1

2.4.5 Functionality of BERR/_TEA/ in Slave Mode

In Slave Mode the LSI53C770 responds to requests from an external
master in one of the following ways:

TEA/ SLACK/ TA/

1 1 1 Requests the bus master to insert a wait-state

1 0 0 Normal cycle acknowledge

0 1 1 Access exception has occurred

1

Condition

2

0 0 0 Reserved

1. TA/ does not assert during slave cycles unless the Enable Ack bit in the DMA

Control (DCNTL) register is set.

2-18 Functional Description

Address exceptions are:

Bus Mode 1: All of the cases mentioned above plus any 3 byte

Bus Mode 2: • any misaligned 2-byte transfer (A0 = 1)

Bus Mode 3 and 4: No bus exceptions will occur and the TEA/ pin will never

2.4.6 Bus Retry

Bus Retry allows the LSI53C770 to retry the previous cycle using the
same address, size, and other information. Bus retry occurs when an
external device asserts the appropriate bus signals, forcing the chip to
release the host bus. It tries to regain control of the host bus immediately,
without a fairness delay. Once the chip regains control of the host bus, it
retries the previous cycle.

2.4.7 Noncache Line Burst

In Bus Mode 1, an external device initiates a bus retry by asserting the
HALT/ and BERR/ signals. In Bus Mode 2, the TA/ and TEA/ signals are
used to initiate a bus retry. In Bus Modes 3 and 4, a bus retry is initiated
by asserting the TEA/ and READYI/ signals. When an external device
asserts these signals, the LSI53C770 asserts the Bus Request (BR/)
signal (Bus Modes 1 and 2) or the HOLD/ signal (Bus Modes 3 and 4).
This is done without a fairness delay to try to regain control of the host
bus. This repeats indefinitely (as long as the signals remain asserted)
until the cycle completes normally, or a bus error occurs. During a
noncache line burst, a bus retry can be executed in any cycle.

transfer.

• any misaligned Dword (A1–A0 not equal to 00)

• any 2-byte transfer in big endian mode

be asserted. One-, two-, three-, and four-byte operations
are allowed.

2.4.8 Cache Line Burst

During a cache line burst, the bus retry must be executed during the first
cycle for the Bus Retry to execute properly in all bus modes.

In Bus Mode 1, if the LSI53C770 is attempting a cache line burst, it will
retry the bus cycle and assert Cache Burst Request (CBREQ/) again. If
a bus retry is attempted during one of the subsequent cycles of the

Host Interface 2-19

cache line burst, the LSI53C770 halts the transfer until the HALT/ signal
is deasserted. If the Bus Error (BERR/) signal is still asserted at this time,
the transfer will abort.

In Bus Mode 2, if the LSI53C770 is attempting a cache line burst, it will
retry the bus cycle and asserts SIZ0 and SIZ1 again. If a bus retry is
attempted during one of the subsequent cycles of the cache line burst,
the transfer will abort. If the Transfer Error (TEA/) signal is still asserted
at this time, the LSI53C770 will abort the transfer.

In Bus Mode 4 (Bus Mode 3 does not support cache line bursting), if the
LSI53C770 is attempting a cache line burst, it will retry the bus cycle and
assert Cache Burst Request (CBREQ/) again. If a bus retry is attempted
during one of the subsequent cycles of the cache line burst, the
LSI53C770 will halt the transfer until the READYI/ signal is asserted. If
the TEA/ signal is still asserted at this time, the LSI53C770 will abort the
transfer.

If the BERR/ or TEA/ signal is asserted without HALT/, TA/, or READYI/,
a Bus Fault interrupt will be generated, which sets bit 5 in the DMA

Status (DSTAT) register (0x0C). The LSI53C770 will not automatically

attempt to regain control of the host bus. A bus retry cannot be attempted
during a Preview of Address (PA). For more information on the PA/
signal, refer to Chapter 3 and Chapter 4.

2.4.9 Using the Back Off Signal to Relinquish the Bus

The LSI53C770 may also relinquish the host bus when the Back Off
(BOFF/) signal is asserted. For more information on the operation of this
signal, refer to Chapter 3, “Signal Descriptions.” BOFF/ causes the
LSI53C770 to release the bus and stay off in accordance with the timing
data in Chapter 6, “Electrical Characteristics.” Because BOFF/ is
sampled only at the beginning and end of each cycle, the LSI53C770
may get off the bus by executing a bus retry, then assert BOFF/ at the
end of the cycle to prevent the chip from immediately trying to regain
control of the bus. During a backoff or retry, register access functions
normally. When the device resumes DMA operation, retried data is
transferred.

2-20 Functional Description

2.5 Bidirectional STERM/-TA/-ReadyIn/

The STERM/_TA/_ReadyIn/ (referred to in this section as STERM/)
signal terminates a read or write cycle. In a typical system, STERM/ is a
wired-OR signal driven by slave devices and monitored by bus masters.
When the master is faster than the slave device being accessed, a cycle
may be terminated as soon as the slave is ready. Slave devices that are
faster than the master present a special problem in that they are required
to insert wait-states to allow the master to catch up. The LSI53C770 can
accommodate both situations.

During slave accesses, the SLACK/-ReadyO/ (Referred to as SLACK/)
output provides an indication that the LSI53C770 is ready to terminate a
read or write cycle. After asserting SLACK/, the LSI53C770 samples
STERM/ on every subsequent rising BCLK edge until it is sampled
active, at which time the read/write cycle terminates. Any time between
SLACK/ and STERM/ is treated as a wait-state; a read/write cycle may
be stretched indefinitely. However on a write cycle, data is taken into the
LSI53C770 before the SLACK/ signal is asserted. Wait states may not
be added to allow for late write data.

Typically, SLACK/ is tied back to STERM/ as in
CPU is not capable of completing a slave cycle in the minimum time
required by the LSI53C770, SLACK/ must be delayed before asserting
STERM/. If the system CPU is capable of running slave write cycles with
zero additional wait-states, no delay is necessary.

In systems where the CPU is faster than the LSI53C770, SLACK/ may
be connected to STERM/ with external logic, but the best solution is to
set the Enable Acknowledge (EA) bit in the DMA Control (DCNTL)
register to internally connect SLACK/ to STERM. When the EA bit is set,
the STERM/ pin changes from being an input in both master and slave
modes, and becomes bidirectional: input in master mode, and output in
slave mode. This way, no external logic is required and proper timing for
zero wait-state operation is guaranteed. Setting the EA bit must be the
first slave I/O access to the LSI53C770. In addition, when the Enable
Acknowledge bit is set, a signal with the same timing characteristics as
SLACK/ is driven onto the STERM/_TA/ pin, as illustrated in Figure 2.4.
The external timing on this signal is the same as the signal generated if

Figure 2.4. If the system

Bidirectional STERM/-TA/-ReadyIn/ 2-21

EA was not used, as illustrated in Figure 2.5. The additional control logic
3-states STERM/_TA/ for 5 ns after it is deasserted. The SLACK/ signal
is always driven.

Figure 2.4 SLACK/ Tied Back to STERM/, EA Bit Not Set

5V

470

STERM/-TA/

Open Collector

PAL Delay

Figure 2.5 Bidirectional STERM/, EA Bit Set

5V

470

STERM/-TA/

LSI53C770

Internal
SLACK/

Into
Chip

STERM/-TA/

LSI53C770

SLACK

SLACK/

2-22 Functional Description

EA

Additional Control

2.6 SCSI Bus Interface

The LSI53C770 contains open drain output drivers that can be
connected directly to the SCSI bus. Each output is isolated from the
power supply to ensure that a powered-down LSI53C770 has no effect
on an active SCSI bus (CMOS “voltage feed-through”). Additionally,
TolerANT technology provides signal filtering at the inputs of REQ/ and
ACK/ to increase immunity to signal reflections.

In differential mode, the SDIR [15:0], SDIRP [1:0], IGS, TGS, RSTDIR,
BSYDIR, and SELDIR signals control the direction of external differential
pair transceivers. See
diagram. The suggested value for the 15 pull-up resistors in the diagram
is 1.5 K. The pull-up value should be no lower than the transceiver I
can tolerate, but not so high as to cause RC timing problems.

2.6.1 SCSI Termination

SCSI terminators provide the biasing needed to pull inactive signals to
an inactive voltage level, and are required for both SE and differential
applications. Terminators must be installed at the extreme ends of the
SCSI cable, and only at the ends; no system should ever have more or
less than two sets of terminators installed and active. SCSI host adapters
should provide a means of accommodating terminators. The terminators
should be socketed, so that if not needed they may be removed. SE
cables are terminated differently from differential cables. SE cables use

a 220 Ω pull-up to the termination power supply (Term-Power) line and
a 330 Ω pull-down to ground. Differential cables use a 330 Ω pull-up from
“– SIG” to Term-Power, a 330 Ω pull-down from “+ SIG” to ground, and
a 150 Ω resistor from “– SIG” to “+ SIG”.

Figure 2.6 for the suggested differential wiring

OL

Because of the high-performance nature of the LSI53C770, Regulated
(or Active) termination is recommended. Figure 2.7 shows a Unitrode
active terminator. For additional information, refer to the SCSI-2
Specification. TolerANT technology active negation can be used with any
type of termination.

Note: If the LSI53C770 is used in a design with a 8-bit SCSI bus,

all 16 data lines must be terminated or pulled HIGH.

Note: Active termination is required in SE Ultra SCSI systems.

SCSI Bus Interface 2-23

Figure 2.6 LSI53C770 Differential Wiring Diagram

LSI53C770

SELDIR
BSYDIR
RSTDIR

SEL/
BSY/
RST/

REQ/

ACK/

MSG/

C/D/

ATN/

TGS

IGS

SD8-15/

SDIRP0

SDIR7
SDIR6
SDIR5
SDIR4
SDIR3
SDIR2
SDIR1
SDIR0

SDP/
SD7/
SD6/
SD5/
SD4/
SD3/
SD2/
SD1/
SD0/

DIFFSENS

I/O/

VDD

VDD

VDD

1K Ω

680 Ω

680 Ω

VDD

VDD

VDD

680 Ω

680 Ω

680 Ω

SEL/

BSY/

RST/

MSG/

C_D/

I_O/

ATN/

DIFFSENS

SD0/

SD1/

SD2/

SD3/

SD4/

SD5/

SD5/

SD7/

SDP/

DIFFSENS

VDD

1K Ω

SELDIR

BSYDIR

RSTDIR
REQ/

ACK/

SDIR0

SDIR1

SDIR2

SDIR3

SDIR4

SDIR5

SDIR6

SDIR7

SDIRP

DIFFSENS

Schottky

Diode

75LBC976 #1

CDE0
CDE1
CDE2
BSR
CRE

1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE

75LBC976 #2

CDE0
CDE1
CDE2
BSR
CRE

1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE

DIFFSENS (pin 21)

-SEL (42)

1B+

+SEL (41)

1B-

-BSY (34)

2B+

+BSY (33)

2B-

-RST (38)

3B+

+RST (37)

3B-

-REQ (46)

4B+

+REQ (45)

4B-

-ACK (36)

5B+

+ACK (35)

5B-

-MSG (40)

6B+

+MSG (39)

6B-

-C/D (44)

7B+

+C/D (43)

7B-

-I/O (48)

8B+

+I/O (47)

8B-

-ATN (30)

9B+

+ATN (29)

9B-

-DB0 (4)

1B+

+DB0 (3)

1B-

-DB1 (6)

2B+

+DB1 (5)

2B-

-DB2 (8)

3B+

+DB2 (7)

3B-

-DB3 (10)

4B+

+DB3 (9)

4B-

-DB4 (12)

5B+

+DB4 (11)

5B-

-DB5 (14)

6B+

+DB5 (13)

6B-

-DB6 (16)

7B+

+DB6 (15)

7B-

-DB7 (18)

8B+

+DB7 (17)

8B-

-DBP (20)

9B+

+DBP (19)

9B-

SCSI
BUS

2-24 Functional Description

Figure 2.7 Regulated Termination

UC5601QP

2.85V

C1

C2

2

REG_OUT

19

DISCONNECT

UC5603DP

TERML1
TERML2
TERML3
TERML4
TERML5
TERML6
TERML7
TERML8
TERML9

TERML10
TERML11
TERML12
TERML13
TERML14
TERML15
TERML16
TERML17
TERML18

20
21
22
23
24
25
26
27
28

10
11

SD0 (J1.40)
SD1 (J1.41)
SD2 (J1.42)
SD3 (J1.43)
SD4 (J1.44)
SD5 (J1.45)
SD6 (J1.46)
SD7 (J1.47)
SDP0 (J1.48)

3
4
5
6
7
8
9

ATN (J1.55)
BSY (J1.57)
ACK (J1.58)
RST (J1.59)
MSG (J1.60)
SEL (J1.61)
C/D (J1.62)
REQ (J1.63)
I/O (J1.64)

C3

14

REG_OUT

6

DISCONNECT

TERM1
TERM2
TERM3
TERM4
TERM5
TERM6
TERM7
TERM8
TERM9

10

16
15

9
8
7
3
2
1

SD15 (J1.38)
SD14 (J1.37)
SD13 (J1.36)
SD12 (J1.35)
SD11 (J1.68)
SD10 (J1.67)
SD9 (J1.66)
SD8 (J1.65)
SDP1 (J1.39)

SCSI Bus Interface 2-25

2.6.2 Select/Reselect During Selection/Reselection

In multithreaded SCSI I/O environments, it is not uncommon to be
selected or reselected while trying to perform selection/reselection. This
situation may occur when a SCSI controller (operating in the initiator
mode) tries to select one target and gets reselected by another. The
analogous situation for target devices is being selected while trying to
perform a reselection. The SCSI SCRIPTS language allows interrupt free
handling of multithreaded operations.

Once a change in operating mode occurs, the initiator SCRIPTS should
start with a Set Initiator instruction or the target SCRIPTS should start
with a Set Target instruction. The Enable Response to Selection and
Enable Response to Reselection bits (
respectively) should both be asserted so that the LSI53C770 may
respond as an initiator or as a target.

The selection or reselection enable bits allow the LSI53C770 to respond
as either a target or an initiator. For example, if only selection is enabled,
the LSI53C770 cannot be reselected as an initiator. There are also
interrupt status and interrupt enable bits in the SCSI Interrupt Status

Zero (SIST0) and SCSI Interrupt Enable Zero (SIEN0) registers

respectively, indicating if the LSI53C770 has been selected (bit 5) or
reselected (bit 4).

SCSI Chip ID (SCID) bits 5 and 6,

2.6.3 Synchronous Operation

The LSI53C770 transfers synchronous SCSI data in both initiator and
target modes. The SCSI Transfer (SXFER) register controls both the
synchronous offset and the transfer period, and may be loaded by the
CPU before SCRIPTS execution begins or from within a SCRIPTS
program. The LSI53C770 can always receive data from the SCSI bus at
a synchronous transfer period as short as 160 ns for SCSI-1 or 80 ns for
SCSI-2, regardless of the transfer period used to send data. Therefore,
when negotiating for synchronous data transfers, the suggested transfer
period is 80 or 160 ns. Depending on the SCLK frequency and the
synchronous clock divider, the LSI53C770 can send synchronous data at
intervals as short as 100 or 200 ns.

2-26 Functional Description

2.6.4 Determining the Data Transfer Rate

This section is an overview of how the LSI53C770 controls synchronous
data transfers. For more information, refer to the full bit descriptions in

Chapter 4. Synchronous data transfer rates are controlled by bits in two

different registers of the LSI53C770. A brief description of the bits is
provided below.

Figure 2.8 illustrates the clock division factors used in each register, and

the role of the register bits in determining the transfer rate.

Figure 2.8 Determining the Synchronous Transfer Rate

SCF2 SCF1 SCF0 SCF

0011
0 1 0 1.5
0112
1003
0003
1014

SCLK

CCF2 CCF1 CCF0 Divisor

0011
0 1 0 1.5
0112
1003
0003
1014

Divisor

SCF

Divider

CCF

Divider

TP2 TP1 TP0 XFERP

Divisor
0004
0015
0106
0117
1008
1019
11010
11111

This point

must not

exceed

100 MHz

This point

must not

exceed

25 MHz

Example:
SCLK = 80 MHz, SCF = 1 (/1), XFERP = 0 (/4),
CCF = 5 (/4)

Synchronous send rate = (SCLK/SCF) /XFERP
= (80/1) /4 = 20 Mbytes/s
Synchronous receive rate = (SCLK/SCF) = (80/1) /4
= 20 Mbytes/s

Divide by 4

Synchronous

Divider

Asynchronous

SCSI Logic

Receive

Clock

Send Clock

(to SCSI Bus)

SCSI Bus Interface 2-27

2.6.4.1 SCSI Control Three (SCNTL3) Register, Bits [6:4] (SCF[2:0])

The SCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the synchronous SCSI control logic.
The output from this divider must not exceed 80 MHz. The receive rate
is one-fourth of the divider output. For example, if SCLK is 80 MHz and
the SCF value is set to divide by two, then the maximum rate at which
data can be received is 10 MHz (80/2)/4 = 10.

2.6.4.2 SCNTL3 Register, Bits [2:0] (CCF[2:0])

The CCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the synchronous SCSI core logic. This
divider must be set according to the input clock frequency in the table.

2.6.4.3 SXFER Register, Bits [7:5] (TP[2:0])

The TP[2:0] bits determine the SCSI synchronous transfer period when
sending synchronous SCSI data in either initiator or target mode.

2.6.5 Ultra SCSI Synchronous Data Transfers

Ultra SCSI is simply an extension of current Fast SCSI-2 synchronous
transfer specifications. It allows synchronous transfer periods to be
negotiated to as low as 50 ns, which is half the 100 ns period allowed
under Fast SCSI-2. This will allow a maximum transfer rate of
40 Mbytes/s on a 16-bit SCSI bus. The LSI53C770 requires an 80 MHz
SCSI clock input to perform Ultra SCSI transfers. In addition, the
following bit values affect the chip’s ability to support Ultra SCSI
synchronous transfer rates:

• Clock Conversion Factor bits, SCSI Control Three (SCNTL3) register,

bits [2:0] and Synchronous Clock Conversion Factor bits, SCSI

Control Three (SCNTL3) register, bits [6:4].

These fields support a value of 101 (binary), allowing the SCLK
frequency to be divided down by 4. This allows systems using an
80/100 MHz clock or the internal clock doubler (clock doubler works
at 40 to 50 MHz input), to operate at Fast SCSI-2 transfer rates as
well as Ultra SCSI rates, if needed.

• Ultra Enable bit, SCSI Control Three (SCNTL3) register, bit 7.

Setting this bit enables Ultra SCSI synchronous transfers in systems
that have an 80 MHz clock or that use the SCSI clock doubler.

2-28 Functional Description

2.7 Interrupt Handling

The SCRIPTS processor in the LSI53C770 performs most functions
independently of the host microprocessor. However, certain interrupt
situations must be handled by the external microprocessor. This section
explains all aspects of interrupts as they apply to the LSI53C770.

2.7.1 Polling vs. Hardware Interrupts

The external microprocessor is informed of an interrupt condition by
polling or hardware interrupts. Polling means that the microprocessor
must continually loop and read a register until it detects a bit that is set
indicating an interrupt. This method is the fastest, but it wastes CPU time
that could be used for other system tasks. The preferred method of
detecting interrupts in most systems is hardware interrupts. In this case,
the LSI53C770 asserts the Interrupt Request (IRQ/) line that interrupts
the microprocessor, causing the microprocessor to execute an interrupt
service routine. A hybrid approach would use hardware for long waits,
and use polling for short waits.

2.7.2 Registers

The registers in the LSI53C770 that are used for detecting or defining
interrupts are the

(SIST0), SCSI Interrupt Status One (SIST1), DMA Status (DSTAT), SCSI
Interrupt Enable Zero (SIEN0), SCSI Interrupt Enable One (SIEN1), and
DMA Interrupt Enable (DIEN).

Interrupt Status (ISTAT), SCSI Interrupt Status Zero

ISTAT – Interrupt Status (ISTAT) is the only register that can be accessed

as a slave during SCRIPTS operation. Therefore, it is the register that is
polled when polled interrupts are used. It is also the first register that
should be read after the IRQ/ pin is asserted in association with a
hardware interrupt. The INTF (Interrupt-on-the-Fly) bit should be the first
interrupt serviced. To service this interrupt, write a one to the INTF bit. If
the SIP bit in the Interrupt Status (ISTAT) register is set, then a
SCSI-type interrupt has occurred and the SCSI Interrupt Status Zero

(SIST0) and SCSI Interrupt Status One (SIST1) registers should be read.

If the DIP bit in the Interrupt Status (ISTAT) register is set, then a

Interrupt Handling 2-29

DMA-type interrupt has occurred and the DMA Status (DSTAT) register
should be read. SCSI-type and DMA-type interrupts may occur
simultaneously, so in some cases both SIP and DIP may be set.

SIST0 and SIST1 – The SCSI Interrupt Status Zero (SIST0) and SCSI

Interrupt Status One (SIST1) registers contain the SCSI-type interrupt

bits. Reading these registers determines which condition or conditions
caused the SCSI-type interrupt, and clears that SCSI interrupt condition.
If the LSI53C770 is receiving data from the SCSI bus and a fatal interrupt
condition occurs, the chip attempts to send the contents of the DMA
FIFO to memory before generating the interrupt. If the LSI53C770 is
sending data to the SCSI bus and a fatal SCSI interrupt condition occurs,
data could be left in the DMA FIFO. Because of this the DMA FIFO
Empty (DFE) bit in DMA Status (DSTAT) should be checked. If this bit is
cleared, set the CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits
before continuing.

DSTAT – The DMA Status (DSTAT) register contains the DMA-type
interrupt bits. Reading this register determines which condition or
conditions caused the DMA-type interrupt, and clears that DMA interrupt
condition. Bit 7 in DMA Status (DSTAT), DFE, is purely a status bit; it will
not generate an interrupt under any circumstances and will not be
cleared when read. DMA interrupts flush neither the DMA nor SCSI FIFO
before generating the interrupt, so the DFE bit in the DMA Status

(DSTAT) register should be checked after any DMA interrupt. If the DFE

bit is cleared, then the FIFOs must be cleared by setting the CLF and
CSF bits, or flushed by setting the FLF (Flush DMA FIFO) bit. The CLF
bit is bit 2 in Chip Test Three (CTEST3). The FLF bit is bit 3 in Chip Test

Three (CTEST3). The CSF bit is bit 1 in SCSI Test Register Three
(STEST3).

SIEN0 and SIEN1 – The SCSI Interrupt Enable Zero (SIEN0) and SCSI

Interrupt Enable One (SIEN1) registers are the interrupt enable registers

for the SCSI interrupts in SCSI Interrupt Status Zero (SIST0) and SCSI

Interrupt Status One (SIST1).

DIEN – The DMA Interrupt Enable (DIEN) register is the interrupt enable
register for DMA interrupts in DMA Status (DSTAT).

2-30 Functional Description

2.7.3 Fatal vs. Nonfatal Interrupts

A fatal interrupt, as the name implies, always causes the SCRIPTS to
stop running. A nonfatal interrupt causes the SCRIPTS to stop running
only if the interrupt is enabled. Interrupt enabling and masking are
discussed later in this section.

All DMA interrupts (indicated by the DIP bit in
and one or more bits in DMA Status (DSTAT) being set) are fatal. Some
SCSI interrupts (indicated by the SIP bit in the Interrupt Status (ISTAT)
and one or more bits in SCSI Interrupt Status Zero (SIST0) or SCSI

Interrupt Status One (SIST1) being set) are nonfatal. When the

LSI53C770 is operating in the Initiator mode, only the CMP (Function
Complete) and SEL (Selected or Reselected) interrupts are nonfatal.

When operating in Target mode CMP, SEL, and M/A (Target mode: ATN/
active) are nonfatal. Refer to the description for the DHP (Disable Halt
on a Parity Error or ATN/ active (Target Mode Only)) bit in the SCSI

Control One (SCNTL1) register to configure the chip’s behavior when the

ATN/ interrupt is enabled during Target mode operation. The Interrupt-on­the-Fly interrupt is also nonfatal, since SCRIPTS can continue when it
occurs.

The reason for nonfatal interrupts is to prevent the SCRIPTS from
stopping when an interrupt occurs that does not require service from the
CPU. This prevents an interrupt when arbitration is complete (CMP set),
when the LSI53C770 is selected or reselected (SEL set), when there is
a general purpose or handshake to handshake time-out, or when the
initiator has asserted ATN (target mode: ATN/ active). These interrupts
are not needed for events that occur during high-level SCRIPTS
operation.

Interrupt Status (ISTAT)

2.7.4 Enabling Interrupts

In the LSI53C770, the SCSI and DMA Interrupt Enable registers (SIEN
and DIEN) are used to enable the various interrupting conditions. The
default value of these registers is to disable, or mask, all interrupts.
Masking an interrupt means ignoring that interrupt. To mask any of these
interrupts, clear the appropriate bits in the SIEN (for SCSI interrupts)
registers or DIEN (for DMA interrupts) registers. How the chip responds

Interrupt Handling 2-31

to masked interrupts depends on: whether polling or hardware interrupts
are being used; whether the interrupt is fatal or nonfatal; and whether the
chip is operating in Initiator or Target mode.

If a nonfatal interrupt is masked and that condition occurs, the SCRIPTS
do not stop, the appropriate bit in the SCSI Interrupt Status Zero (SIST0)
or SCSI Interrupt Status One (SIST1) is still set, the SIP bit in the

Interrupt Status (ISTAT) is not set, and the IRQ/ pin is not asserted. See

the Section 2.7.3, “Fatal vs. Nonfatal Interrupts,” for a list of the nonfatal
interrupts.

If a fatal interrupt is masked and that condition occurs, then the SCRIPTS
still stops, the appropriate bit in the DMA Status (DSTAT), SCSI Interrupt

Status Zero (SIST0),orSCSI Interrupt Status One (SIST1) register is

set, the SIP or DIP bits in the Interrupt Status (ISTAT) is set, but the IRQ/
pin is not asserted. When the chip is initialized, enable all fatal interrupts
if you are using hardware interrupts. If a fatal interrupt is disabled and
that interrupt condition occurs, the SCRIPTS halts and the system will
never know it unless it times out and checks the Interrupt Status (ISTAT)
after a certain period of inactivity.

If you are polling the Interrupt Status (ISTAT) instead of using hardware
interrupts, then masking a fatal interrupt makes no difference since the
SIP and DIP bits in the Interrupt Status (ISTAT) inform the system of
interrupts, not the IRQ/ pin. Masking an interrupt after IRQ/ is asserted
does not cause deassertion of IRQ/.

2.7.5 Stacked Interrupts

The LSI53C770 will stack interrupts if they occur one after the other. If
the SIP or DIP bits in the Interrupt Status (ISTAT) register are set (first
level), then there is already at least one pending interrupt, and any future
interrupts are stacked in extra registers behind the SCSI Interrupt Status

Zero (SIST0), SCSI Interrupt Status One (SIST1), and DMA Status
(DSTAT) registers (second level). When two interrupts have occurred and

the two levels of the stack are full, any further interrupts set additional
bits in the extra registers behind SCSI Interrupt Status Zero (SIST0),

SCSI Interrupt Status One (SIST1), and DMA Status (DSTAT). When the

first level of interrupts are cleared, all the interrupts that came in
afterward move into the

Interrupt Status One (SIST1), and DMA Status (DSTAT). After the first

interrupt is cleared by reading the appropriate register, the IRQ/ pin is

2-32 Functional Description

SCSI Interrupt Status Zero (SIST0), SCSI

deasserted for a set time as published in Chapter 6; the stacked
interrupt(s) move into the SCSI Interrupt Status Zero (SIST0), SCSI

Interrupt Status One (SIST1),orDMA Status (DSTAT); and the IRQ/ pin

is asserted once again.

Since a masked nonfatal interrupt does not set the SIP or DIP bits,
interrupt stacking does not occur as a result of a masked, nonfatal
interrupt. A masked, nonfatal interrupt still posts the interrupt in SCSI

Interrupt Status Zero (SIST0) or SCSI Interrupt Status One (SIST1),but

does not assert the IRQ/ pin. Since no interrupt is generated, future
interrupts move into the SCSI Interrupt Status Zero (SIST0) or SCSI

Interrupt Status One (SIST1) instead of being stacked behind another

interrupt. When another condition occurs that generates an interrupt, the
bit corresponding to the earlier masked nonfatal interrupt is still set.

A related situation to interrupt stacking is when two interrupts occur
simultaneously. Since stacking does not occur until the SIP or DIP bits
are set, there is a small timing window in which multiple interrupts can
occur but are not stacked. These could be multiple SCSI interrupts (SIP
set), multiple DMA interrupts (DIP set), or a combination of SCSI and
DMA interrupts (both SIP and DIP set).

As previously mentioned, DMA interrupts do not attempt to flush the
FIFOs before generating the interrupt. It is important to set either the
CLF (Clear DMA) or CSF (SCSI FIFO) bit if a DMA interrupt occurs and
the DFE (DMA FIFO Empty) bit is not set. This is because any future
SCSI interrupts are not posted until the DMA FIFO is clear of data.
These ‘locked out’ SCSI interrupts are posted as soon as the DMA FIFO
is empty.

2.7.6 Halting in an Orderly Fashion

When an interrupt occurs, the LSI53C770 attempts to halt in an orderly
fashion. All instructions may halt before completion, except for the ones
described below.

• If an interrupt occurs in the middle of an instruction fetch, the fetch

is completed, except in the case of a Bus Fault or Watchdog
Time-out. Execution does not begin, but the

(DSP) points to the next instruction since it is updated when the

current SCRIPTS routine is fetched.

Interrupt Handling 2-33

DMA SCRIPTS Pointer

• If the DMA direction is a write to memory and a SCSI interrupt

occurs, the LSI53C770 attempts to flush the DMA FIFO to memory
before halting. Under any other circumstances only the current cycle
is completed before halting, so the DFE bit in DMA Status (DSTAT)
should be checked to see if any data remains in the DMA FIFO.

• SCSI REQ/ACK handshakes that have begun are completed before

halting.

• The LSI53C770 attempts to clean up any outstanding synchronous

offset before halting.

• In the case of Transfer Control Instructions, once instruction

execution begins it continues to completion before halting.

• If the instruction is a JUMP/CALL WHEN <phase>, the DMA

SCRIPTS Pointer (DSP) is updated to the transfer address before

halting.

2.7.7 Sample Interrupt Service Routine

The following is a sample of an interrupt service routine for the
LSI53C770. It can be repeated during if polling or should be called when
the IRQ/ pin is asserted during hardware interrupts.

1. Read Interrupt Status (ISTAT).

2. If the INTF bit is set, it must be written to a one to clear this status.

3. If only the SIP bit is set, read SCSI Interrupt Status Zero (SIST0) and

SCSI Interrupt Status One (SIST1) to clear the SCSI interrupt

condition and get the SCSI interrupt status. The bits in the SCSI

Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1)

tell which SCSI interrupt(s) occurred and determine what action is
required to service the interrupt(s).

4. If only the DIP bit is set, read the DMA Status (DSTAT) to clear the
interrupt condition and get the DMA interrupt status. The bits in DMA

Status (DSTAT) tells which DMA interrupts occurred and determine

what action is required to service the interrupts.

5. If both the SIP and DIP bits are set, read SCSI Interrupt Status Zero

(SIST0), SCSI Interrupt Status One (SIST1), and DMA Status
(DSTAT) to clear the SCSI and DMA interrupt condition and get the

interrupt status. If using 8-bit reads of the

(SIST0), SCSI Interrupt Status One (SIST1), and DMA Status
(DSTAT) registers to clear interrupts, insert 12 BCLKs between the

2-34 Functional Description

SCSI Interrupt Status Zero

consecutive reads to ensure that the interrupts clear properly. Both
the SCSI and DMA interrupt conditions should be handled before
leaving the interrupt service routine. It is recommended that the DMA
interrupt is serviced before the SCSI interrupt, because a serious
DMA interrupt condition could influence how the SCSI interrupt is
acted upon.

6. When using polled interrupts, go back to Step 1 before leaving the
interrupt service routine, in case any stacked interrupts moved in
when the first interrupt was cleared. When using hardware interrupts,
the IRQ/ pin is asserted again if there are any stacked interrupts.
This should cause the system to re-enter the interrupt service
routine.

Interrupt Handling 2-35

2-36 Functional Description

Chapter 3
Signal Descriptions

The LSI53C770 host bus can operate in one of four modes: Bus Mode 1
(68030-like), Bus Mode 2 (68040-like), Bus Mode 3 (80386SX-like), and
Bus Mode 4 (80386DX-like). Both big and little endian byte ordering are
supported in Bus Modes 1, 2, and 4. The bus mode is selected by using
the BS[2:0] pins. A function is listed on the table as NC (not connected)
if it is not active for a given bus mode. A slash (/) indicates an active LOW
signal. All pins have a totem pole (push-pull) architecture unless
otherwise noted.

Figure 3.1 illustrates the LSI53C770 pin diagram for Bus Modes 1 and 2.
Figure 3.2 illustrates the LSI53C770 pin diagram for Bus Modes 3 and 4.

LSI53C770 Ultra SCSI I/O Processor 3-1

Figure 3.1 LSI53C770 Pin Diagram, Bus Modes 1 and 2

RAMCS/

VSS

A10
A11
A12
A13
A14

VSS

A15
A16
A17

VDD

A18
A19

VSS

A20
A21
A22
A23
A24

VSS

A25
A26
A27

MAC/

VDD

A28
A29

VSS

A30
A31

AS/-TS/

SIZ1

SIZ0
FC2-TM2
FC1-TM1
FC0-TM0

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4

VSS

R_W/

CBREQ/-TT1

UPSO-TT0
CBACK/-TBI
STERM/-TA/
BERR/-TEA/

NCNCA9A8VDDA7A6A5VSSA4A3A2A1A0SDIR12

208

206

207

1

NC

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

NC

51

NC

52

5355575961636567697173757779818385878889909192949698100

5456586062646668707274767880828486

200

202

204

199

201

203

205

SDIR13

SDIR14

SDIR15

VSS

SDIRP1

SDIR0

SDIR1

VDD

SDIR2

SDIR3

SDIR4

TSTIN/

VSS

SDIR5

SDIR6

SDIR7

SDIRP0

SD12/

SD13/

SD14/

VSS

SD15/

SDP1

SD0/

SD1/

VSS

SD2/

SD3/

SD4/

SD5/

VSS

SD6/

SD7/

SDP0/

ATN/NCNC

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

192

193

194

195

196

198

197

188

190

182

184

186

176

178

180

170

172

174

164

166

168

LSI53C770

SCSI I/O Processor

208-Pin QFP

Top View

Bus Modes 1 and 2

93959799101

158

160

162

156

NC

155

NC

154

VSS

153

BSY/

152

ACK/

151

RST/

150

MSG/

149

SEL/

148

VSS

147

C/D

146

REQ/

145

I/O

144

SD8/
VSS

143

SD9

142

SD10/

141

SD11/

140

SDIR8

139

SDIR9

138

SDIR10

137

SDIR11

136

VSS

135

BSYDIR

134

RSTDIR

133

SELDIR

132

IGS

131

VDD

130

TGS

129

DIFFSENS

128

AUTO/

127

IRQ/

126

SCLK

125

BR/

124

BG/

123

VDD

122

BGACK/-BB/

121

FETCH/

120

VSS

119

BOFF/

118

RESET/

117

CS/

116

SLACK/

115

BS2

114

BS1

113

BS0

112

SC1

111

SC0

110

DS/-DLE

109

DP0

108

D0

107

NC

106

NC

105

102

104

103

NC

NC

D31

D30

D29

D28

D27

D26

D25

D24

VDD

MASTER/

HALT/-TIP/

BCLK

VSS

VDD

D23

DP3_ABRT/

Note: NC pins are not connected.

3-2 Signal Descriptions

VSS

D22

D21

D20

D19

D18

D17

TSTOUT

VSS

D16

DP2

VDD

D15

D14

D13

D12

VSS

D11

D10

D7D6D5

D4

D3

D2

D9

D8

DP1

VSS

VDD

VSS

D1

NC

NC

Figure 3.2 LSI53C770 Pin Diagram, Bus Modes 3 and 4

RAMCS/

VSS

A10
A11
A12
A13
A14

VSS

A15
A16
A17

VDD

A18
A19

VSS

A20
A21
A22
A23
A24

VSS

A25
A26
A27

MAC/

VDD

A28
A29

VSS

A30
A31

ADS/

NC_BE3/

BHE/-BE2/

PA/-FC2

FC1

FC0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4

VSS

W_R/

TT1/

TT0/

TBI/

READY1/

TEA/

NCNCA9A8VDDA7A6A5VSSA4A3A2A1_BE1/

208

1

NC

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

NC

51

NC

52

5355575961636567697173757779818385878889909192949698100

5456586062646668707274767880828486

202

204

206

201

203

205

207

A0_BE0/

SDIR12

SDIR13

SDIR14

SDIR15

VSS

SDIRP1

SDIR0

SDIR1

VDD

SDIR2

SDIR3

SDIR4

TSTIN/

VSS

SDIR5

SDIR6

SDIR7

SDIRP0

SD12/

SD13/

SD14/

VSS

SD15/

SDP1

SD0/

SD1/

VSS

SD2/

SD3/

SD4/

SD5/

VSS

SD6/

SD7/

SDP0/

ATN/NCNC

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

192

193

194

195

196

198

200

197

199

188

190

182

184

186

176

178

180

170

172

174

164

166

168

LSI53C770

SCSI I/O Processor

208-Pin QFP

Bus Modes 3 and 4

93959799101

158

160

162

156

NC

155

NC

154

VSS

153

BSY/

152

ACK/

151

RST/

150

MSG/

149

SEL/

148

VSS

147

C/D/

146

REQ/

145

I/O

144

SD8/
VSS

143

SD9

142

SD10/

141

SD11/

140

SDIR8

139

SDIR9

138

SDIR10

137

SDIR11

136

VSS

135

BSYDIR

134

RSTDIR

133

SELDIR

132

IGS

131

VDD

130

TGS

129

DIFFSENS

128

AUTO/

127

IRQ/

126

SCLK

125

HOLD/

124

HLDAI/

123

VDD

122

BB/

121

FETCH/

120

VSS

119

BOFF/

118

RESET/

117

CS/

116

READY0/

115

BS2

114

BS1

113

BS0

112

SC1

111

SC0

110

DLE

109

DP0

108

D0

107

NC

106

NC

105

102

104

103

D7D6D5

D4

D3

D2

NC

NC

MASTER/

VDD

TIP/

BCLK

D31

D30

D29

D28

VSS

D27

D26

VDD

D25

D24

D9

D16

D15

D14

D23

D22

D21

D20

D19

D18

D17

VSS

DP3_ABRT/

VSS

TSTOUT

DP2

VDD

D13

D12

VSS

D11

D10

D8

DP1

VSS

VDD

VSS

D1

NC

NC

Note: The decoupling capacitor arrangements shown above are recommended to maximize the benefits

of the internal split ground system. Capacitor values between 0.01 and 0.1 µF should provide
adequate noise isolation. Because of the number of high current drivers on the LSI53C770, a
multilayer PC board with power and ground planes is required.

3-3

Table 3.1 describes the Power and Ground Signals group.

Table 3.1 Power and Ground Signals

Symbol Pin No. Description

V

SS

V

DD

3, 9, 16, 22, 30, 44, 63, 71,
79, 87, 93, 100, 119, 135,
143, 148, 154, 163, 168,
173, 181, 190, 200

13, 27, 56, 66, 82, 97, 122,
130, 186, 204

–

–

Table 3.2 describes the Address and Data Signals group.

Table 3.2 Address and Data Signals

Bus
Mode 1

D[31:0] D[31:0] D[31:0] D[31:0] 59–62, 64–65,

DP[2:0] DP[2:0] DP[2:0] DP[2:0] 81, 92, 108 Host Bus Data Parity (I/O, I/O).

Bus
Mode 2

Bus
Mode 3

Bus
Mode 4 Pin No.

67–68, 70,
72–77, 80,
83–86,
88–91,
94–96, 98, 99,
101, 102, 107

Description
(Slave Type, Master Type)

Host Data Bus (I/O, I/O). Main data path into

host memory for all bus modes.
Note: To interface to a 16-bit bus, Bit 3 in the

DMA Control (DCNTL) register should be set

and data lines 31 through 16 should be tied
to data lines 15 through 0, respectively.

In all bus modes:
DP0 provides parity for D[7:0]
DP1 provides parity for D[15:8]
DP2 provides parity for D[23:16]
Note: To interface to a 16-bit bus and to
support parity, DP3 and DP2 should be tied
to DP1 and DP0, respectively.

DP3_
Abort/

DP3_
Abort/

DP3_
Abort/

DP3_
Abort/

3-4 Signal Descriptions

69 Host Bus Data Parity (I/O, I/O). In all bus

modes, DP3 provides parity for D[31:24].
Parity is valid on all byte lanes, including
unused lanes. To disable Parity Through
mode, set bit 2 in the

(SCNTL0) register. DP3 becomes a hardware

abort input (ABRT/) when Parity Through
mode is disabled. When Abort/ is asserted,
the LSI53C770 finishes the current transfer,
then gets off the bus. An abort leaves data in
an undetermined state and does not flush the
FIFOs.

SCSI Control Zero

Table 3.2 Address and Data Signals (Cont.)

Bus
Mode 1

DS/ DLE DLE DLE 109 Data Strobe (Z, O). In Bus Mode 1, this

A[31:2] A[31:2] A[31:2] A[31:2] 32, 31, 29, 28,

A[1:0] A[1:0] A[1:0] BE/[1:0] 196, 1950 A[1:0]. In Bus Modes 1, 2, and 3, these pins

AS/ TS/ ADS/ ADS/ 33 Address Strobe (I, O). In Bus Mode 1, this

Bus
Mode 2

Bus
Mode 3

Bus
Mode 4 Pin No.

25–23, 21–17,
15, 14, 12–10,
8–4, 206, 205,
203–201,
199–195

Description
(Slave Type, Master Type)

signal indicates that valid data has been or
should be placed on the data lines. It is
typically used when data becomes valid
asynchronously to the clock.
DLE—

Data Latch

2, 3, and 4, this signal transparently latches
read data into the LSI53C770 prior to an
Acknowledge. It is typically used when data
becomes valid asynchronously to the clock.
Tie this signal HIGH if it is not used.

Address Bus (I, O). In all bus modes, this
signal provides an address bus to the host
memory.

are part of the address bus.
BE/[1:0]. In Bus Mode 4, this signal enables
data transfer on the byte lane D[15:8] and
D[7:0].

signal indicates that a valid address is on
A[31:0].
Transfer Start (I, O). In Bus Mode 2, Transfer
Start indicates that a bus cycle is starting and
all of the status and address lines are valid.
Address Status (I, O). In Bus Modes 3 and
4, this signal indicates that a valid bus cycle
definition and address are being driven.

Enable (I, I) In Bus Modes

3-5

Table 3.3 describes the Arbitration Signals group.

Table 3.3 Arbitration Signals

Bus
Mode 1

BR/ BR/ HOLD/ HOLD/ 124 Bus Request (O, O). In Bus Modes 1 and 2, this signal

BG/ BG/ HLDAI/ HLDAI/ 123 Bus Grant (I, I). In Bus Modes 1 and 2, this signal

BGACK/ BB/ BB/ BB/ 121 Bus Grant Acknowledge (Z, I/O). In Bus Mode 1, this

BOFF/ BOFF/ BOFF/ BOFF/ 118 Back Off (I, I). In all bus modes, this forces the

Bus
Mode 2

Bus
Mode 3

Bus
Mode 4

Pin

Description

No.

(Slave Type, Master Type)

indicates there is a request to use the host bus.
Hold (O, O). In Bus Modes 3 and 4, this signal indicates
there is a request to use the host bus.

indicates that the host bus has been granted to the
LSI53C770.
Hold Acknowledge (I, I). In Bus Modes 3 and 4, this
signal indicates that the previous bus master has given
up use of the host bus.

signal indicates that the LSI53C770 or another device
has taken control of the host signals.
Bus Busy (wire-OR) (Z, I/O). In Bus Modes 2, 3, and
4, this signal indicates that the LSI53C770 or another
device has taken control of the host bus signals.

LSI53C770 to relinquish bus mastership at the end of
the current cycle, if the proper setup timing
requirements are met. When BOFF/ deasserts, a new
arbitration takes place and the cycles resume. BOFF/ is
sampled at every start cycle. During worst case
operation, if timing is not met it takes the LSI53C770
two clocks to get off the host bus. The start cycle
becomes a release cycle. If BOFF/ asserts during
arbitration, the LSI53C770 completes arbitration and
gets off the bus at the first start cycle.

3-6 Signal Descriptions

Table 3.4 describes the System Signals group.

Table 3.4 System Signals

Bus
Mode 1

BCLK BCLK BCLK BCLK 58 Bus Clock (I, I). This clock controls all host related

RESET/ RESET/ RESET/ RESET/ 117 Chip Reset (I, I). Forces a full chip reset in all bus

CS/ CS/ CS/ CS/ 116 Chip Select (I, I). Selects the LSI53C770 as a

RAMCS/ RAMCS/ RAMCS/ RAMCS/ 2 SCRIPTS RAM Chip Select (I, I). When enabled,

IRQ/ IRQ/ IRQ/ IRQ/ 126 Interrupt (O, O). In all bus modes, this signal

UPSO TT0/ TT0/ TT0/ 47 User Programmable Status (Z, O). General

Bus
Mode 2

Bus
Mode 3

Bus
Mode 4

Pin

Description

No.

(Slave type, Master type)

activity in all bus modes.

modes.

slave I/O device in all bus modes. When CS/ is
detected:
Bus Mode 1—CBACK/ is deasserted
Bus Modes 2, 3, 4—TBI/ is asserted

defines a 4K byte address space for the 4K bytes
SCRIPTS RAM. This type of SCRIPTS RAM
access is enabled by setting bits 1 and 2 of the

Chip Test Five (CTEST5) register.

indicates that service is required from the host
CPU.

purpose line in Bus Mode 1. The value in the
register bit is asserted while the chip is bus master.
Transfer Type Zero (Z, O). In Bus Modes 2, 3, and
4 this signal indicates the current bus transfer type.
This pin can be programmed from a register bit
(default = 0). It is asserted only when the
LSI53C770 is bus master.

SIZ0 SIZ0 BHE/ BE2/ 35 Transfer Size Zero (I, O). In Bus Modes 1 and 2,

SIZ0 indicates the current transfer size in
combination with SIZ1 (see table under the SIZ1
pin description).
Byte High Enable (I, O). In Bus Mode 3, this signal
enables data transfer on the high order byte lane
D[15:8].
Byte Enable Two (I, O). In Bus Mode 4, this signal
enables data transfer on byte lane D[23:16].

3-7

Table 3.4 System Signals (Cont.)

Bus
Mode 1

SIZ1 SIZ1 NC BE3/ 34 Transfer Size One (I, O). In Bus Modes 1 and 2,

STERM/ TA/ READYI/ READYI/ 49 Synchronous Cycle Termination (I/O, I). In Bus

Bus
Mode 2

Bus
Mode 3

Bus
Mode 4

Pin

Description

No.

(Slave type, Master type)

SIZ1 indicates the current transfer size in
combination with the SIZ0 pin, as shown in the
table below:

SIZ1, SIZ0

0,0 Dword (4 bytes)
0,1 Byte (1 byte)
1,0 Word (2-byte slave accesses are allowed,

if word-aligned)

1,1 Bus Mode 1, Illegal; Bus Mode 2, Cache

Line Burst (since cache line bursts are not
supported in slave mode, this size request
will result in standard Dword slave

access).
Byte Enable Three (I, O). In Bus Mode 4, this
signal enables data transfer on byte lane D[31:24].

Mode 1, this signal acknowledges transfer to a
32-bit wide port.
Transfer Acknowledge (I/O, I). In Bus Mode 2, this
signal acknowledges transfer to a 32-bit wide port.
Ready In (I, I). In Bus Modes 3 and 4 during master
mode operation, this signal indicates that the slave
device is ready to transfer or receive data. During
slave mode, this signal is monitored by the
LSI53C770 to determine when to stop driving the
bus.

3-8 Signal Descriptions

Table 3.5 describes the Interface Control Signals group.

Table 3.5 Interface Control Signals

Bus
Mode 1

R_W/ R_W/ W_R/ W_R/ 45 Read/Write (I, O). Indicates the current

SLACK/ SLACK/ READYO/ READYO/ 115 Slave Acknowledge (O, O). Asserted in Bus

FC2_PA/ TM2 FC2_PA/ FC2_PA/ 36 Function Codes/Preview of Address,

FC[1:0] TM[1:0] FC[1:0] FC[1:0] 37–38Function Codes and Transfer Modifiers.

Bus
Mode 2

Bus
Mode 3

Bus
Mode 4

Pin

Description

No.

(Slave type, Master type)

direction of the data transfer relative to the
current master.

Modes 1 and 2 to indicate the internal end of
a valid slave mode cycle. The external slave
cycle ends when the LSI53C770 observes
either STERM/-TA/ or BERR/-TEA.
Ready Out (O, O). Asserted in Bus Modes 3
and 4 to indicate the end of a slave mode
cycle.

Transfer Modifier.
FC2, TM2 (Z, O). User definable from bit 5 in

DMA Mode (DMODE) register in

the
conjunction with the Bus Mode bit (bit 6) in the

DMA Control (DCNTL) register.

PA/ (I, I). This input signal is used to tell the
LSI53C770/SE that the system is ready for the
next address/value and byte enable signal.
FC2 becomes PA/ when the Bus Mode bit
(DMA Control (DCNTL), bit 6) is set.

For all bus modes:
FC0–TM0 (Z, O). Indicates the status of the
current bus cycle. For more information on the
operation of this pin, refer to description of the
the Program Data bit (
bit 3) in Chapter 4.
FC(1)–TM(1) (Z, O). User definable from bit 4
in the DMA Mode (DMODE) register in
conjunction with bit 6 in the

(DCNTL) register. For more information, refer

to the description of the Function Code 1 bit
(DMA Mode (DMODE), bit 4) in Chapter 4.

DMA Mode (DMODE),

DMA Control

3-9

Table 3.5 Interface Control Signals (Cont.)

Bus
Mode 1

SC[1:0] SC[1:0] SC[1:0] SC[1:0] 111–

MASTER/ MASTER/ MASTER/ MASTER/ 55 Master Status (O, O). Driven LOW when the

FETCH/ FETCH/ FETCH/ FETCH/ 120 Fetching OpCode (O, O). In all bus modes,

CBREQ/ TT1/ TT1/ CBREQ/ 46 Cache Burst Request (Z, O). In Bus Modes

Bus
Mode 2

Bus
Mode 3

Bus
Mode 4

Pin

Description

No.

(Slave type, Master type)

Snoop Control (Z(O), O). Indicates the bus

110

snooping level in all bus modes. The bits are
user programmable through register bits. They
are asserted when the LSI53C770 is bus
master. SC[1:0] may be optionally used as
pure outputs, active in both master and slave
modes.

LSI53C770 becomes bus master. This signal
is valid in all bus modes. This signal is driven
at all times except when the LSI53C770 is in
ZMODE.

this signal indicates that the next bus request
will be for an opcode fetch.

1 and 4, Cache Burst Request indicates an
attempt to execute a line transfer of four
Dwords. CBREQ/ is valid in Mode 4 only when
386 Cache Mode is enabled (Cache 386 bit,

Chip Test Zero (CTEST0) register).

Transfer Type Bit One (Z, O). Transfer Type
bit one is a 3-state output line indicating the
current bus transfer type in all four bus modes.
TT1/ is not valid in Bus Mode 4 if Cache 386
mode is enabled. This bit can be programmed
from bit 1 in the Chip Test Zero (CTEST0)
register. It is only asserted when the
LSI53C770 is bus master.

CBACK/ TBI/ TBI/ TBI/ 48 Cache Burst Acknowledge (O, I). In Bus

Mode 1 this signal indicates that the memory
system or LSI53C770 can handle a burst
request. In slave mode this signal is
deasserted in response to CS/.
Transfer Burst Inhibit (O, I). In Bus Modes 2,
3, and 4 Transfer Burst Inhibit indicates that
the memory or the LSI53C770 cannot handle
a burst request at this time. In slave mode this
signal is asserted in response to CS/.

3-10 Signal Descriptions

Table 3.5 Interface Control Signals (Cont.)

Bus
Mode 1

BS[2:0] BS[2:0] BS[2:0] BS[2:0] 114–

Bus
Mode 2

Bus
Mode 3

Bus
Mode 4

Pin
No.

112

Description
(Slave type, Master type)

Bus Mode Select (I, I) These signals are

active in all four bus modes. They select
between Motorola/Intel (BS2), Big/Little
Endian (BS1), and 386SX/_030 and
386DX/_040 (BS0).

BS2 BS1 BS0 Bus Mode

0 0 0 80386DX-like,

Little Endian,
Bus Mode 4

0 0 1 80386SX-like,

Little Endian,
Bus Mode 3

0 1 0 80386DX-like,

Big Endian,

Bus Mode 4
0 1 1 Reserved
1 0 0 68040-like,

Little Endian,

Bus Mode 2
1 0 1 68030-like,

Little Endian,

Bus Mode 1
1 1 0 68040-like,

Big Endian,

Bus Mode 2
1 1 1 68030-Like,

Big Endian,

Bus Mode 1

3-11

Table 3.6 describes the Additional Interface Signals group.

Table 3.6 Additional Interface Signals

Bus
Mode 1

MAC/ MAC/ MAC/ MAC/ 26 Memory Access Control (O, O). This signal

TSTOUT TSTOUT TSTOUT TSTOUT 78 Test Out (O, O). This signal is used to test the

TSTIN/ TSTIN/ TSTIN/ TSTIN/ 182 Test In (I, I). When this pin is driven LOW, the

Bus
Mode 2

Bus
Mode 3

Bus
Mode 4

Pin

Description

No.

(Slave Type, Master Type)

indicates if the next access will be to local
(onboard) or far (system) memory. When
MAC/=1, the memory access is to local
memory. When MAC/ = 0, the access is to far
memory. The default setting is zero; all
accesses are far.

connectivity of the LSI53C770 signals using an
“AND tree” scheme. The Test Out pin is only
driven when the Test In pin is driven LOW;
otherwise the signal is 3-stated.

LSI53C770 connects all input and outputs
(excluding certain SCSI bus signals) to an
“AND tree.” The SCSI control signals and data
lines (SD[15:0], SDP[1:0], CD/, IO/, MSG/,
REQ/, ACK/, BSY/, SEL/, ATN/, RST/, and
DIFFSENS) are not connected to the “AND
tree.” The output of the “AND tree” is connected
to the Test Out pin. This allows manufacturers
to verify chip connectivity to the board, and to
determine exactly which pins are not properly
attached. When the TSTIN pin is driven LOW,
internal pull-ups are enabled on all input,
output, and bidirectional pins, all outputs and
bidirectional signals will be 3-stated, and the
TSTOUT pin will be enabled. Connectivity can
be tested by driving one of the LSI53C770 pins
LOW. The TSTOUT pin should respond
accordingly by driving LOW.

BERR/ TEA/ TEA/ TEA/ 50 Bus Error Acknowledge (O, I). In Bus Mode

1, this indicates that a bus fault has occurred.
Used with HALT/ to force a bus retry. Will be
asserted on an illegal slave access.
Transfer Error Acknowledge (O, I). Indicates
that a bus fault has occurred in Bus Modes 2,
3, or 4. Used in conjunction with TA/-READYI/
to force a bus retry. Will be asserted on an
illegal slave access.

3-12 Signal Descriptions

Table 3.6 Additional Interface Signals (Cont.)

Bus
Mode 1

HALT/ TIP/ TIP/ TIP/ 57 Halt (Z, I). Input only in Bus Mode 1, used with

AUTO/ AUTO/ AUTO/ AUTO/ 127 SCRIPTS Autostart Mode (I, I). In all bus

GPIO[4:0] GPIO[4:0] GPIO[4:0] GPIO[4:0] 43–39General Purpose Input/Output (I/O, I/O). In all

Bus
Mode 2

Bus
Mode 3

Bus
Mode 4

Pin

Description

No.

(Slave Type, Master Type)

BERR/ to indicate a bus retry cycle.
Transfer in Progress (Z, O). Output signal for
Bus Modes 2, 3, and 4, indicating that bus
activity is in progress.

modes, this signal selects between automatic
SCRIPTS and manual SCRIPTS start modes.
AUTO/ = 0 Auto start. The

Pointer (DSP) register will point to an address

of all zeros following a chip reset. This address
is the starting address of the SCRIPTS
instructions. The SCRIPTS instructions will be
automatically fetched and executed until an
Interrupt instruction occurs.
AUTO/ = 1 Manual start. The

Pointer (DSP) must be written to so that it

points to the starting address of the SCRIPTS
instructions. The SCRIPTS instructions will be
automatically fetched and executed until an
interrupt condition occurs.

bus modes, these signals are user
programmable inputs/outputs. GPIO[3:0] power
up as inputs, and GPIO4 powers up as an
output.

DMA SCRIPTS

DMA SCRIPTS

3-13

Table 3.7 describes the SCSI Signals group.

Table 3.7 SCSI Signals

Bus
Mode 1

Bus
Mode 2

Bus
Mode 3

Bus
Mode 4 Pin No.

Description
(Slave Type, Master Type)

DIFFSENS DIFFSENS DIFFSENS DIFFSENS 128 Differential Sense (I, I). This pin

detects the presence of a SE device
on a differential system. When using
external differential transceivers and
a zero is detected on this pin, all chip
SCSI outputs will be 3-stated to avoid
damage to the transceivers. When
running in SE mode, this pin should
be tied HIGH. The normal value of
this pin is 1.

SCLK SCLK SCLK SCLK 125 SCSI Clock (I, I). SCLK is used to

derive all SCSI related timings. The
speed of this clock will be determined
by the application requirements; in
some applications, SCLK and BCLK
may be tied to the same source.

SDATA/ SDATA/ SDATA/ SDATA/ 172,

174–176,
140–142,
144, 161,
162,
164–167,

SCSI Data (I/O, I/O). These open
collector signals include the following
data lines and parity signals for all
bus modes.
SD[15:0]/ 16-bit SCSI data bus

SDP[1:0]/ SCSI data parity pins
169, 170,
171, 160

SCTRL/ SCTRL/ SCTRL/ SCTRL/ 147, 145,

150, 146,
152, 153,
149, 159,
151

3-14 Signal Descriptions

Open Collector SCSI Control signals

(I/O, I/O):

C_D/ SCSI phase line,

command/data
I_O/ SCSI phase line, input/output
MSG/ SCSI phase line, message
REQ/ Data handshake signal from

target device
ACK/ Data handshake signal from

initiator device

1

BSY/

SEL/

SCSI bus arbitration signal,

signal busy

1

SCSI bus arbitration signal,

select device
ATN/ Attention, the initiator is

requesting a message out

phase

1

RST/

SCSI bus reset

Table 3.7 SCSI Signals (Cont.)

Bus
Mode 1

SDIR[15:0] SDIR[15:0] SDIR[15:0] SDIR[15:0] 191–194,

SDIRP0 SDIRP0 SDIRP0 SDIRP0 177 SCSI Parity Direction Control

SDIRP1 SDIRP1 SDIRP1 SDIRP1 189 SCSI Parity Direction Control

BSYDIR BSYDIR BSYDIR BSYDIR 134 SCSI BSY/ Control (O, O).

SELDIR SELDIR SELDIR SELDIR 132 SCSI SEL/ Control (O, O).

RSTDIR RSTDIR RSTDIR RSTDIR 133 SCSI RST/ Control (O, O).

Bus
Mode 2

Bus
Mode 3

Bus
Mode 4 Pin No.

136–139,
178–180,
183–185,
187, 188

Description
(Slave Type, Master Type)

SCSI Data Direction Control (O, O).

Differential driver direction control for
SCSI data lines.

(O, O).
Differential driver direction control for
SCSI parity signal (bits [7:0]).

(O, O).
Differential driver direction control for
SCSI parity signal (bits [15:8]).

Differential driver enable control for
SCSI BSY/ signal.

Differential driver enable control for
SCSI SEL/ signal.

Differential driver enable control for
SCSI RST/ signal.

IGS IGS IGS IGS 131 Initiator Direction Control (O, O).

Differential driver direction control for
initiator driver group.

TGS TGS TGS TGS 129 Target Direction Control (O, O).

Differential driver direction control for
target driver group.

1. Input only in differential mode

3-15

3-16 Signal Descriptions

Chapter 4
Registers

Throughout this chapter, registers are referenced by their little endian
addresses, with big endian addresses in parentheses. The terms “set”
and “assert” are used to refer to bits that are programmed to a binary
one. Similarly, the terms “deassert,” “clear,” and “reset” are used to refer
to bits that are programmed to a binary zero. Reserved bits should
always be written to zero; mask all information read from them. Reserved
bit functions may be changed at any time. Unless otherwise indicated, all
bits in registers are active HIGH; the feature is enabled by setting the bit.

4.1 Register Descriptions

The bottom of every register diagram shows the default register values,
which are enabled after the chip is powered on or reset. Registers can
be addressed as bytes, words, or Dwords. Other access sizes will result
in bus errors.

Warning: The only register that the host CPU can access while the

LSI53C770 is executing SCRIPTS is the Interrupt Status

(ISTAT) register; attempts to access other registers will

interfere with the operation of the chip. However, all
registers are accessible using SCRIPTS.

LSI53C770 Ultra SCSI I/O Processor 4-1

Table 4.1 is the register address map.

Table 4.1 LSI53C770 Register Address Map

31 16 15 0

SCNTL3 SCNTL2 SCNTL1 SCNTL0 0x00
GPREG SDID SXFER SCID 0x04

SBCL SSID SOCL SFBR 0x08

SSTAT2 SSTAT1 SSTAT0 DSTAT 0x0C

DSA 0x10

RESERVED ISTAT 0x14

CTEST3 CTEST2 CTEST1 CTEST0 0x18

TEMP 0x1C

CTEST6 CTEST5 CTEST4 DFIFO 0x20

DCMD DBC 0x24

DNAD 0x28

DSP 0x2C

DSPS 0x30

SCRATCHA 0x34

DCNTL DWT DIEN DMODE 0x38

ADDER 0x3C

SIST1 SIST0 SIEN1 SIEN0 0x40

GPCNTL MACNTL SWIDE SLPAR 0x44

RESPID1 RESPID0 STIME1 STIME0 0x48

STEST3 STEST2 STEST1 STEST0 0x4C

RESERVED SIDL 0x50
RESERVED SODL 0x54

RESERVED SBDL 0x58

SCRATCHB 0x5C
SCRATCHC 0x60
SCRATCHD 0x64

SCRATCHE 0x68

SCRATCHF 0x6C

SCRATCHG 0x70
SCRATCHH 0x74

SCRATCHI 0x78

SCRATCHJ 0x7C

4-2 Registers

Register: 0x00 (0x03)

SCSI Control Zero (SCNTL0)
Read/Write

76543210

ARB[1:0] START WATN/ EPC EPG AAP TRG

11000000

ARB[1:0] Arbitration Mode Bits 1 and 0 [7:6]

ARB1 ARB0 Arbitration Mode

0 0 Simple arbitration

0 1 Reserved

1 0 Reserved

1 1 Full arbitration, selection/reselection

Simple Arbitration

1. The LSI53C770 waits for a bus free condition to
occur.

2. It asserts BSY/ and its SCSI ID (contained in the

SCSI Chip ID (SCID) register) onto the SCSI bus. If

the SEL/ signal is asserted by another SCSI device,
the LSI53C770 deasserts BSY/, deasserts its ID and
sets the Lost Arbitration bit (bit 3) in the SCSI Status

Zero (SSTAT0) register.

3. After an arbitration delay, the CPU reads the SCSI

Bus Data Lines (SBDL) register to check if a higher

priority SCSI ID is present. If no higher priority ID bit
is set, and the Lost Arbitration bit is not set, the
LSI53C770 wins arbitration.

4. Once the LSI53C770 wins arbitration, SEL is
asserted using the SCSI Output Control Latch

(SOCL) register for a bus clear plus a bus settle

delay (1.2 µs) before a low level selection is

performed.

Register Descriptions 4-3

Full Arbitration, Selection/Reselection

1. The LSI53C770 waits for a bus free condition.

2. It asserts BSY/ and its SCSI ID (the ID stored in the

SCSI Chip ID (SCID) register) onto the SCSI bus.

3. If the SEL/ signal is asserted by another SCSI
device or if the LSI53C770 detects a higher priority
ID, the LSI53C770 deasserts BSY/, deasserts its ID,
and waits until the next bus free state to try
arbitration again.

4. The LSI53C770 repeats arbitration until it wins
control of the SCSI bus. When it wins, the Won
Arbitration bit is set in the SCSI Status Zero

(SSTAT0) register, bit 2.

5. The LSI53C770 performs selection by asserting the
following onto the SCSI bus: SEL/, the target’s ID
(stored in the SCSI Destination ID (SDID) register)
and the LSI53C770 ID (the highest priority ID stored
in the SCSI Chip ID (SCID) register).

6. After a selection is complete, the Function Complete
bit is set in the SCSI Interrupt Status Zero (SIST0)
register, bit 6.

START Start Sequence 5

4-4 Registers

7. If a selection time-out occurs, the Selection Time-out
bit is set in the SCSI Interrupt Status One (SIST1)
register, bit 2.

When this bit is set, the LSI53C770 starts the arbitration
sequence indicated by the Arbitration Mode bits. The
Start Sequence bit is accessed directly in low level mode;
during SCSI SCRIPTS operations, this bit is controlled by
the SCRIPTS processor. Do not start an arbitration
sequence if the Connected bit, bit 4 in the SCSI Control

One (SCNTL1) register indicates that LSI53C770 is

already connected to the SCSI bus. This bit is
automatically cleared when the arbitration sequence is
complete. If a sequence is aborted, check the connected
bit in the in the SCSI Control One (SCNTL1) register to
verify that the LSI53C770 is not connected to the SCSI
bus.

WATN/ Select with ATN/ on a Start Sequence 4

When this bit is set and the LSI53C770 is in initiator
mode, the SCSI ATN/ signal is asserted during
LSI53C770 selection of a target device. This is to inform
the target that the LSI53C770 has a message to send. If
a selection time-out occurs while attempting to select a
target device, ATN/ is deasserted at the same time SEL/
is deasserted. When this bit is clear, the ATN/ signal is
not asserted during selection. When executing SCSI
SCRIPTS, this bit is controlled by the SCRIPTS
processor, but manual setting is possible in low level
mode.

EPC Enable Parity Checking 3

When this bit is set, the LSI53C770 checks the SCSI data
bus for odd parity when data is received from the SCSI
bus in either initiator or target mode. It also checks the
host data bus for odd parity if bit 2, the Enable Parity
Generation bit, is cleared. Host data bus parity is checked
as data is loaded into the SCSI Output Data Latch

(SODL) register when sending SCSI data in either

initiator or target mode. If a parity error is detected, bit 0
of the SCSI Status Zero (SSTAT0) register is set and an
interrupt may be generated.

If the LSI53C770 is operating in initiator mode and a
parity error is detected, assertion of ATN/ is optional, but
the transfer continues until the target changes phase.
When this bit is cleared, parity errors are not reported.

EPG Enable Parity Generation/Parity Through 2

When this bit is set, the LSI53C770 generates SCSI
parity. The host data bus parity lines DP[3:0] are ignored
and should not be used as parity signals. When this bit
is cleared, the parity present on the host data parity lines
flows through the LSI53C770 internal FIFOs and is driven
onto the SCSI bus when sending data (if the host bus is
set to even parity, it is changed to odd before it is sent to
the SCSI bus). This bit is set to enable the DP3_ABRT/
pin to function as an abort input (ABRT/).

AAP Assert ATN/ on Parity Error 1

When this bit is set, the LSI53C770 automatically asserts
the SCSI ATN/ signal upon detection of a parity error.
ATN/ is only asserted in initiator mode. The ATN/ signal

Register Descriptions 4-5

is asserted before deasserting ACK/ during the transfer
of the byte with the parity error. The Enable Parity
Checking bit must also be set for the LSI53C770 to
assert ATN/ in this manner. The following parity errors
can occur:

• A parity error detected on data received from the

SCSI bus.

• A parity error detected on data transferred to the

LSI53C770 from the host data bus.

If the Assert ATN/ on Parity Error bit is cleared or the
Enable Parity Checking bit is cleared, ATN/ is not
automatically asserted on the SCSI bus when a parity
error is received.

TRG Target Mode 0

This bit determines the default operating mode of the
LSI53C770. The user must manually set target or initiator
mode. This can be done using the SCRIPTS language
(SET target or CLEAR target). When this bit is set, the
chip is a target device by default. When the target mode
bit is cleared, the LSI53C770 is an initiator device by
default. Writing this bit while not connected may cause
the loss of a selection or reselection due to the changing
of target or initiator roles.

Register: 0x01 (0x02)

SCSI Control One (SCNTL1)
Read/Write

76543210

EXC ADB DHP CON RST AESP IARB SST

00000000

EXC Extra Clock Cycle of Data Setup 7

4-6 Registers

When this bit is set, an extra clock period of data setup
is added to each SCSI send data transfer. The extra data
setup time can provide additional system design flexibility,
though it affects the SCSI transfer rates. Clearing this bit
disables the extra clock cycle of data setup time.

ADB Assert SCSI Data Bus 6

When this bit is set, the LSI53C770 drives the contents
of the SCSI Output Data Latch (SODL) register onto the
SCSI data bus. When the LSI53C770 is an initiator, the
SCSI I/O signal must be inactive to assert the SCSI Out-

put Data Latch (SODL) contents onto the SCSI bus. The

low order data and parity signal is always asserted onto
the SCSI bus, whereas the high order data and parity
signal is only asserted onto the SCSI bus if the Enable
Wide SCSI bit (SCSI Control Three (SCNTL3), bit 3) is
asserted and a data phase is specified by the SCSI
phase signals. When the LSI53C770 is a target, the SCSI
I/O signal must be active to assert the SCSI Output Data

Latch (SODL) contents onto the SCSI bus. The contents

of the SCSI Output Data Latch (SODL) register can be
asserted at any time, even before the LSI53C770 is
connected to the SCSI bus. Clear this bit when executing
SCSI SCRIPTS. It is normally used only for diagnostics
testing or operation in low level mode.

DHP Disable Halt on Parity Error or ATN (Target Only) 5

The DHP bit is only defined for target mode operation.
When this bit is clear, the LSI53C770 halts the SCSI data
transfer when a parity error is detected or when the ATN/
signal is asserted. If ATN/ or a parity error is received in
the middle of a data transfer, the LSI53C770 may transfer
up to three additional bytes (or words, if wide SCSI is
enabled) before halting to synchronize between internal
core cells. During synchronous operation, the LSI53C770
halts when there are no more outstanding synchronous
offsets. If the LSI53C770 is receiving data, any data
residing in the SCSI or DMA FIFOs is sent to memory
before halting. While sending data in target mode with
pass parity enabled, the byte with the parity error is not
sent across the SCSI bus. When this bit is set, the
LSI53C770 does not halt the SCSI transfer when ATN/ or
a parity error is received.

CON Connected 4

This bit is automatically set any time the LSI53C770 is
connected to the SCSI bus as an initiator or as a target.
It is set after the LSI53C770 successfully completing
arbitration or when it responds to a bus-initiated selection
or reselection. This bit is also set after the chip wins

Register Descriptions 4-7

simple arbitration when operating in low level mode.
When this bit is clear, the LSI53C770 is not connected to
the SCSI bus.

The CPU can force a connected or disconnected
condition by setting or clearing this bit. This feature is
used primarily during loopback mode.

RST Assert SCSI RST/ Signal 3

Setting this bit asserts the SCSI RST/ signal. The RST/

signal remains asserted until this bit is cleared. The 25 µs

minimum assertion time defined in the SCSI specification
must be timed out by the controlling microprocessor. In
differential mode, RST/ becomes an input, and setting
this bit causes RSTDIR to be asserted.

Note: Setting this bit in SCRIPTS causes a fatal interrupt, which

halts SCRIPTS execution.

AESP Assert Even SCSI Parity (force bad parity) 2

When this bit is set and the Enable Parity Generation bit
is set (bit 2 in the SCSI Control Zero (SCNTL0) register),
the LSI53C770 asserts even parity. It forces a SCSI par­ity error on each byte sent to the SCSI bus from the
LSI53C770. If parity checking is enabled, then the
LSI53C770 checks data received for odd parity. This bit
is used for diagnostic testing and is cleared during
normal operation. It is useful to generate parity errors to
test error handling functions.

IARB Immediate Arbitration 1

4-8 Registers

Setting this bit causes the SCSI core to immediately
begin arbitration once a Bus Free phase is detected
following an expected SCSI disconnect. This bit is useful
for multithreaded applications. The ARB[1:0] bits in SCSI

Control Zero (SCNTL0) should be set for full arbitration

and selection before setting Immediate Arbitration.

Arbitration is retried until won. At that point, the
LSI53C770 holds BSY and SEL asserted, and waits for
a select or reselect sequence to be requested. The
Immediate Arbitration bit is reset automatically when the
selection or reselection sequence is completed, or times
out.

An unexpected disconnect condition clears IARB without
attempting arbitration. See the SCSI Disconnect
Unexpected bit (SCSI Control Register Two (SCNTL2),
bit 7) for more information on expected versus
unexpected disconnects.

An immediate arbitration sequence can be aborted. First,
the Abort bit in the SCRIPTS processor registers should
be set. Then one of two things happens:

• The Won Arbitration bit (SCSI Status Zero (SSTAT0),

bit 2) will be asserted. In this case, the Immediate
Arbitration bit needs to be reset. This will complete the
abort sequence and disconnect the LSI53C770 from
the SCSI bus. If it is not acceptable to go to Bus Free
phase immediately following the arbitration phase, a
low level selection may instead be performed.

• The abort will complete because the LSI53C770 loses

arbitration. This can be detected by the Immediate
Arbitration bit being deasserted. The Lost Arbitration
bit (SCSI Status Zero (SSTAT0), bit 3) should not be
used to detect this condition. No further action needs
to be taken in this case.

SST Start SCSI Transfer 0

This bit is automatically set during SCRIPTS execution,
and should not be used. It causes the SCSI core to begin
a SCSI transfer, including REQ/ACK handshaking. The
determination of whether the transfer is a send or receive
is made according to the value written to the I/O bit in

SCSI Output Control Latch (SOCL). This bit is

self-clearing. This bit should not be set for low level
operation.

Register Descriptions 4-9

Register: 0x02 (0x01)

SCSI Control Register Two (SCNTL2)
Read/Write

76543210

SDU CHM SLPMD SLPHBEN WSS VUE1 VUE0 WSR

00000000

SDU SCSI Disconnect Unexpected 7

When this bit is set, the SCSI core is not expecting the
SCSI bus to enter the Bus Free phase. If it does, an
unexpected disconnect error is generated (see the
Unexpected Disconnect bit in the

Zero (SIST0) register, bit 2).

During normal SCRIPTS mode operation, this bit is set
automatically whenever the SCSI core is reselected, or
successfully selects another SCSI device. The SDU bit
should be cleared with a register write (Move
0x7f_&_SCNTL2_to_SCNTL2) before the SCSI core
expects a disconnect to occur, normally prior to sending
an Abort, Abort Tag, Bus Device Reset, Clear Queue, or
Release Recovery message, or before deasserting ACK
after receiving a Disconnect command or Command
Complete message.

SCSI Interrupt Status

CHM Chained Mode 6

4-10 Registers

This bit determines whether or not the SCSI core is
programmed for chained SCSI mode. This bit is
automatically set by the Chained Block Move (CHMOV)
SCRIPTS instruction and is automatically cleared by the
Block Move SCRIPTS instruction (MOVE).

Chained mode is primarily used to transfer consecutive
wide data blocks. Using chained mode facilitates partial
receive transfers and allows correct partial send behavior.
When this bit is set and a data transfer ends on an odd
byte boundary, the LSI53C770 stores the last byte in the

SCSI Wide Residue Data (SWIDE) register during a

receive operation, or in the SCSI Output Data Latch

(SODL) register during a send operation. This byte is

combined with the first byte from the subsequent transfer
so that a wide transfer is completed.

SLPMD SLPAR Mode Bit 5

If this bit is cleared, the SCSI Longitudinal Parity (SLPAR)
register functions like the LSI53C720. If this bit is set, the

SCSI Longitudinal Parity (SLPAR) register reflects the

high or low byte of the SLPAR word, depending on the
state of SCSI Control Register Two (SCNTL2), bit 4. It
also allows a seed value to be written to the SCSI Lon-

gitudinal Parity (SLPAR) register.

SLPHBEN SLPAR High Byte Enable 4

If this bit is cleared, the low byte of the SLPAR word is
accessible through the SCSI Longitudinal Parity (SLPAR)
register. If this bit is set, the high byte of the SLPAR word
is present in the SCSI Longitudinal Parity (SLPAR)
register.

WSS Wide SCSI Send 3

When read, this bit returns the value of the Wide SCSI
Send (WSS) flag. Asserting this bit clears the WSS flag.
This clearing function is self-clearing.

When the WSS flag is high following a wide SCSI send
operation, the SCSI core is holding a byte of “chain” data
in the SCSI Output Data Latch (SODL) register. This data
becomes the first low-order byte sent when married with
a high-order byte during a subsequent data send transfer.

Performing a SCSI receive operation clears this bit. Also,
performing any nonwide transfer clears this bit.

VUE1 Vendor Unique Enhancements Bit 1 2

This bit is a read only value indicating whether the group
code field in the SCSI instruction is standard or vendor
unique. If reset, the bit indicates standard group codes; if
set, the bit indicates vendor unique group codes. The
value in this bit is reloaded at the beginning of all
asynchronous target receives. The default for this bit is
reset.

VUE0 Vendor Unique Enhancements Bit 0 1

This bit is used to disable the automatic byte count reload
during Block Move instructions in the command phase. If
this bit is cleared, the device reloads the Block Move byte
count if the first byte received is one of the standard
group codes. If this bit is set, the device does not reload
the Block Move byte count, regardless of the group code.

Register Descriptions 4-11

WSR Wide SCSI Receive 0

When read, this bit returns the value of the Wide SCSI
Receive (WSR) flag. Setting this bit clears the WSR flag.
This clearing function is self-clearing.

The WSR flag indicates that the SCSI core received data
from the SCSI bus, detected a possible partial transfer at
the end of a chained or nonchained block move
command, and temporarily stored the high-order byte in
the SCSI Wide Residue Data (SWIDE) register rather
than passing the byte out the DMA channel. The
hardware uses the WSR status flag to determine what
behavior must occur at the start of the next data receive
transfer. When the flag is set, the stored data in SCSI

Wide Residue Data (SWIDE) may be “residue” data, valid

data for a subsequent data transfer, or overrun data. The
byte is read as normal data by starting a data receive
transfer.

Performing a SCSI send operation clears this bit. Also,
performing any nonwide transfer clears this bit.

Register: 0x03 (0x00)

SCSI Control Three (SCNTL3)
Read/Write

76 432 0

Ultra SCF[2:0] EWS CCF[2:0]

00000000

Ultra Ultra Enable 7

4-12 Registers

Setting this bit enables Ultra SCSI synchronous SCSI
transfers in systems that have an 80 MHz clock. The
default value of this bit is 0. This bit should remain
cleared in systems that have a 40 MHz clock, unless the
SCSI clock doubler feature is used to increase the SCLK
frequency to at least 80 MHz.

When this bit is set, the signal filtering period for SREQ/
and SACK/ automatically changes to 15 ns, regardless of
the value of the Extend REQ/ACK Filtering bit in the SCSI

Test Register Two (STEST2) register.

SCF[2:0] Synchronous Clock Conversion Factor [6:4]

These bits select a factor by which the frequency of
SCLK is divided before being presented to the
synchronous SCSI control logic. Write these to the same
value as the Clock Conversion Factor bits below unless
fast SCSI operation is desired. See the table under the
description of bits [2:0] of this register for the valid
combinations. For additional information on how the
synchronous transfer rate is determined, refer to

Chapter 2. To migrate from a Fast SCSI-2 system with a

40 MHz clock, divide the clock by a factor of two or more
to achieve the same synchronous transfer rate in a
system with an 80 MHz clock.

EWS Enable Wide SCSI 3

When this bit is clear, all information transfer phases are
assumed to be eight bits, transmitted on SD[7:0]/, and
SDP0/. When this bit is asserted, data transfers are done
16 bits at a time, with the least significant byte on
SD[7:0]/, and SDP0/ and the most significant byte on
SD[14:8], SDP1/. Command, Status, and Message
phases are not affected by this bit.

CCF[2:0] Clock Conversion Factor [2:0]

These bits select a factor by which the frequency of
SCLK is divided before being presented to the SCSI core.
The bits are encoded as follows. All other combinations
are reserved and should never be used. The
synchronous portion of the SCSI core can be run at a
different clock rate for fast SCSI. See the synchronous
clock conversion factor bits above.

Register Descriptions 4-13

SCF2

CCF2

SCF1
CCF1

0 0 0 SCLK/3 50.01-75

0 0 1 SCLK/1 16.67-25

0 1 0 SCLK/1.5 25.01-37.5

0 1 1 SCLK/2 37.51-50

1 0 0 SCLK/3 50.01-75

1 0 1 SCLK/4 75.01-100.00

1 1 0 Reserved –

1 1 1 Reserved –

SCF0
CCF0

Factor

Frequency

SCSI Clock

(MHz)

It is important that these bits be set to the proper values
to guarantee that the LSI53C770 meets the SCSI timings
as defined by the ANSI specification. To migrate from a
Fast SCSI-2 system with a 40 MHz clock, divide the clock
by a factor of two or more to achieve the same
synchronous transfer rate in a system with an 80 MHz
clock. If the SCSI clock doubler is enabled, use the
desired frequency after doubling to determine the
conversion factor.

Register: 0x04 (0x07)

SCSI Chip ID (SCID)
Read/Write

76543 0

R RRE SRE R ID[3:0]

x00x0000

R Reserved 7

RRE Enable Response to Reselection 6

4-14 Registers

When this bit is set, the LSI53C770 is enabled to respond
to bus-initiated reselection at the chip ID in the Response

ID Zero (RESPID0) and Response ID One (RESPID1)

registers. Note that the LSI53C770 does not
automatically reconfigure itself to initiator mode as a
result of being reselected.

SRE Enable Response to Selection 5

When this bit is set, the LSI53C770 is able to respond to
bus-initiated selection at the chip ID encoded in the

Response ID Zero (RESPID0) and Response ID One
(RESPID1) registers. Note that the chip does not

automatically reconfigure itself to target mode as a result
of being selected.

R Reserved 4

ID[3:0] Encoded Chip SCSI ID [3:0]

These bits are used to store the LSI53C770 encoded
SCSI ID. This is the ID which the chip asserts when
awaiting for the SCSI bus. The priority of the 16 possible
IDs, in descending order is:

Highest Lowest

7654321015141312111098

Register: 0x05 (0x06)

SCSI Transfer (SXFER)
Read/Write

7 543 0

TP[2:0] R MO[3:0]

000x0000

When using Table Indirect I/O commands, bits [7:5] and [3:0] of this
register are loaded from the I/O data structure. For additional information
on how to determine the synchronous transfer rate is determined, refer

Chapter 2, "Functional Description."

to

TP[2:0] SCSI Synchronous Transfer Period [7:5]

These bits determine the SCSI synchronous transfer
period (XFERP) used by the LSI53C770 when sending
synchronous SCSI data in either initiator or target mode.
These bits control the programmable dividers in the chip.

Register Descriptions 4-15

Note: For Ultra SCSI transfers, the ideal transfer period is 4,

however, 5 is acceptable. Setting the transfer period to a
value greater than 5 is not recommended.

TP2 TP1 TP0 XFERP

00 0 4

00 1 5

01 0 6

01 1 7

10 0 8

10 1 9

11 0 10

11 1 11

The synchronous transfer period the LSI53C770 should
use when transferring SCSI data is determined in the
following example.

The LSI53C770 is connected to a hard disk which can
transfer data at 10 Mbytes/s synchronously. The
LSI53C770 SCLK is running at 40 MHz. The
synchronous transfer period (SXFERP) is found as
follows:

Synchronous Send Rate = (SCLK/SCF)/XFERP

Synchronous Receive Rate = (SCLK/SCF) / 4

Where:

4-16 Registers

SCLK SCLK

XFERP Synchronous transfer period, SCNTL3 bits

SCF Synchronous Clock Conversion Factor SCNTL3 bits

Table 4.2 Examples of Synchronous Transfer Periods and Rates for SCSI-1

SCSI

CLK/SCNTL3

CLK (MHz)

80 ÷ 4 4 200 5 5
80 ÷ 4 5 250 4 5

66.67 ÷ 3 4 180 5.55 5.55

66.67 ÷ 3 5 225 4.44 5.55
50 ÷ 2 4 160 6.25 6.25
50 ÷ 2 5 200 5 6.25
40 ÷ 2 4 200 5 5

37.50 ÷ 1.5 4 160 6.25 6.25

33.33 ÷ 1.5 4 180 5.55 5.55
25 ÷ 1 4 160 6.25 6.25
20 ÷ 1 4 200 5 5

16.67 ÷ 1 4 240 4.17 4.17

Bits[6:4] XFERP

Synchronous

Transfer Period

(ns)

Synchronous

Send Rate
(Mbytes/s)

Synchronous
Receive Rate

(Mbytes/s)

Register Descriptions 4-17

Table 4.3 Examples of Transfer Periods and Rates for Fast SCSI and Ultra SCSI

Synchronous

SCSI CLK/SCNTL3

CLK (MHz)

80 ÷ 1 4 50 20.0 20.0
80 ÷ 2 4 100 10.0 10.0

66.67 ÷ 1.5 4 90 11.11 11.11

66.67 ÷ 1.5 5 112.5 8.88 8.88
50 ÷ 1 4 80 12.5 12.5
50 ÷ 1 5 100 10.0 12.5
40 ÷ 1 4 100 10.0 10.0

37.50 ÷ 1 4 106.67 9.375 9.375

33.33 ÷ 1 4 120 8.33 8.33
25 ÷ 1 4 160 6.25 6.25
20 ÷ 1 4 200 5 5

16.67 ÷ 1 4 240 4.17 4.17

Bits[6:4] XFERP

Transfer

Period (ns)

Synchronous

Send Rate

(Mbytes/s)

Synchronous
Receive Rate

(Mbytes/s)

R Reserved 4

MO[3:0] Max SCSI Synchronous Offset) [3:0]

4-18 Registers

These bits describe the maximum SCSI synchronous
offset used by the LSI53C770 when transferring
synchronous SCSI data in either initiator or target mode.
The following table describes the possible combinations
and their relationship to the synchronous data offset used
by the LSI53C770. These bits determine the
LSI53C770’s method of transfer for Data-In and Data-Out
phases only; all other information transfers will occur
asynchronously.

MO3 MO2 MO1 MO0 Synchronous Offset

0 0 0 0 0-Asynchronous

00 0 1 1

00 1 0 2

00 1 1 3

01 0 0 4

01 0 1 5

01 1 0 6

01 1 1 7

10 0 0 8

1 x x 1 Reserved

1 x 1 x Reserved

1 1 x x Reserved

Register: 0x06 (0x05)

SCSI Destination ID (SDID)
Read/Write

7430

R ID[3:0]

x x x x0000

R Reserved [7:4]

ID[3:0] Encoded Destination SCSI ID [3:0]

Writing these bits sets the SCSI ID of the intended
initiator or target during SCSI reselection or selection
phases, respectively. When executing SCRIPTS, the
SCRIPTS processor writes the destination SCSI ID to
this register. The SCSI ID is defined by the user in a
SCSI SCRIPTS Select or Reselect instruction. The value
written is the binary-encoded ID. The priority of the
16 possible IDs, in descending order, is:

Highest Lowest

7654321015141312111098

Register Descriptions 4-19

Register: 0x07 (0x04)

General Purpose (GPREG)
Read/Write

754 0

R GPIO[4:0]

x x x01111

R Reserved [7:5]

GPIO[4:0] General Purpose Inputs/Outputs [4:0]

These bits allow the LSI53C770 to detect the input
signals of a connected device. The general purpose
inputs can be used to sense the LSI53C770 chip ID or
board configuration at power up. It is also possible to
program these signals as live inputs and sense them
through a register to register Move Instruction. These are
live signals; if the pin is changing, the data is also
changing. The bit values in the

(GPCNTL) register (0x47) determine whether these bits

are inputs or outputs. Bits [3:0] power up as inputs, and
Bit 4 powers up as an output. The general purpose output
feature may be used to enable attached ROM, RAM,
LEDs, or other components on an LSI53C770 board.

General Purpose Control

Note: The input pins all have 100 µA internal pull-ups.

Register: 0x08 (0x0B)

SCSI First Byte Received (SFBR)
Read/Write

7 0

00000000

1B[7:0] First Byte Received [7:0]

4-20 Registers

1B[7:0]

This register contains the first byte received in any
asynchronous information transfer phase. For example,
when the LSI53C770 is operating in initiator mode, this
register contains the first byte received in Message-In,
Status, and Data-In phases.

When a Block Move Instruction is executed for a
particular phase, the first byte received is stored in this
register, even if the present phase is the same as the last
phase. The first byte value received for a particular input
phase is not valid until after a Move instruction is
executed.

This register is also the accumulator for register read­modify-writes with SCSI First Byte Received (SFBR) as
the destination. This allows bit testing after an operation.

This register also holds the state of the lower eight bits
of the SCSI data bus during a selection or reselection,
unless the COM bit in the DMA Control (DCNTL) register
is set.

Register: 0x09 (0x0A)

SCSI Output Control Latch (SOCL)
Read/Write

76543210

REQ ACK BSY SEL ATN MSG C/D I/O

00000000

REQ Assert SCSI REQ/ Signal 7

ACK Assert SCSI ACK/ Signal 6

BSY Assert SCSI BSY/ Signal 5

SEL Assert SCSI SEL/ Signal 4

ATN Assert SCSI ATN/ Signal 3

MSG Assert SCSI MSG/ Signal 2

C/D Assert SCSI C_D/ Signal 1

I/O Assert SCSI I_O/ Signal 0

This register is used primarily for diagnostic testing or
programmed I/O operation. It is controlled by the
SCRIPTS processor when executing SCSI SCRIPTS.

SCSI Output Control Latch (SOCL) is only used when

transferring data using programmed I/O. Some bits are

Register Descriptions 4-21

set (1) or reset (0) when executing SCSI SCRIPTS. Do
not write to the register once the LSI53C770 starts
executing SCSI SCRIPTS.

Register: 0x0A (0x09)

SCSI Selector ID Register (SSID)
Read Only

76 43 0

VAL R Encoded SCSI Destination ID

x x x xxxxx

VAL SCSI Valid Bit 7

If VAL is asserted, then the two SCSI IDs are detected
on the bus during a bus-initiated selection or reselection,
and the encoded destination SCSI ID bits below are valid.
If VAL is deasserted, only one ID is present and the
contents of the encoded destination ID are meaningless.

R Reserved [6:4]

Encoded SCSI Destination ID

Encoded SCSI Destination ID [3:0]

Reading the SCSI Selector ID Register (SSID) register
immediately after the LSI53C770 is selected or
reselected returns the binary-encoded SCSI ID of the
device that performed the operation. These bits are
invalid for targets that are selected under the single
initiator option of the SCSI-1 specification. This condition
can be detected by examining the VAL bit above.

4-22 Registers

Register: 0x0B (0x08)

SCSI Bus Control Lines (SBCL)
Read Only

76543210

REQ ACK BSY SEL ATN MSG C/D I/O

xxxxxxxx

REQ REQ/ Status 7

ACK ACK/ Status 6

BSY BSY/ Status 5

SEL SEL/ Status 4

ATN ATN/ Status 3

MSG MSG/ Status 2

C/D C_D/ Status 1

I/O I_O/ Status 0

This register returns the SCSI control line status. A bit is set when the
corresponding SCSI control line is asserted. These bits are not latched;
they are a true representation of what is on the SCSI bus at the time the
register is read. This register can be used for diagnostics testing or
operation in low level mode.

Register: 0x0C (0x0F)

DMA Status (DSTAT)
Read Only

76543210

DFE HPE BF ABRT SSI SIR WTD IID

10000000

Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register because additional
interrupts may be pending (the LSI53C770 stacks interrupts). The DIP bit

Register Descriptions 4-23

in the Interrupt Status (ISTAT) register will also be cleared. DMA interrupt
conditions may be individually masked through the DMA Interrupt Enable

(DIEN) register.

When performing consecutive 8-bit reads of the DMA Status (DSTAT),

SCSI Interrupt Status Zero (SIST0), and SCSI Interrupt Status One
(SIST1) registers (in any order), insert a delay equivalent to 12 BCLK

periods between the reads to ensure the interrupts clear properly. To
avoid missing a SCSI interrupt while reading any of these registers when
the Interrupt Status (ISTAT) SIP and DIP bits may not be set, read SCSI

Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1)

before DMA Status (DSTAT).

DFE DMA FIFO Empty 7

This status bit is set when the DMA FIFO (DFIFO) is
empty. This bit may be changing at the time this register
is read. It may be used to determine if any data resides
in the FIFO when an error occurs and an interrupt is
generated. This bit is a pure status bit and does not
cause an interrupt. This bit is not cleared by reading the
register.

HPE Host Parity Error 6

This bit is set when a host bus parity error is detected
during a slave write or DMA read operation.

BF Bus Fault 5

ABRT Aborted 4

SSI SCRIPTS Step Interrupt 3

4-24 Registers

This bit is set when a host bus fault condition is detected.
A host bus fault can only occur when the LSI53C770 is
bus master, and is defined as a memory cycle that ends
with the assertion of BERR/ or TEA/.

This bit is set when an abort condition occurs. An abort
condition occurs because of the following: the
DP3_ABRT/ input signal is asserted by another device
(parity generation mode) or a software abort command is
issued by setting bit 7 of the Interrupt Status (ISTAT)
register.

If the Single Step Mode bit in the DMA Control (DCNTL)
register is set, this bit is set and an interrupt is generated
after successful execution of each SCRIPTS instruction.

SIR SCRIPTS Interrupt Instruction Received 2

This status bit is set whenever a SCRIPTS Interrupt
instruction is received.

WTD Watchdog Time-out Detected 1

This status bit is set when the watchdog timer
decrements to zero. The watchdog timer is only used for
the host memory interface. When the timer decrements
to zero, it indicates that the memory system did not
assert the acknowledge signal within the specified
time-out period.

IID Illegal Instruction Detected 0

This status bit is set any time an illegal instruction is
detected, whether the LSI53C770 is operating in
single step mode or automatically executing SCSI
SCRIPTS.

This bit is also set if the LSI53C770 is executing a Wait
Disconnect instruction and the SCSI REQ line asserts
without a disconnect occurring.

Register: 0x0D (0x0E)

SCSI Status Zero (SSTAT0)
Read Only

76543210

ILF ORF OLF AIP LOA WOA RST/ SDP/

00000000

ILF SIDL Least Significant Byte Full 7

This bit is set when the least significant byte in the

SCSI
Input Data Latch (SIDL) register contains data. Data is

transferred from the SCSI bus to the SCSI Input Data

Latch (SIDL) register before being sent to the DMA FIFO

and then to the host bus. The SCSI Input Data Latch

(SIDL) register contains SCSI data received

asynchronously. Synchronous data received does not
flow through this register.

ORF SODR Least Significant Byte Full 6

This bit is set when the least significant byte in the SCSI
Output Data Register (SODR, a hidden buffer register
which is not accessible) contains data. The SODR

Register Descriptions 4-25

register is used by the SCSI logic as a second storage
register when sending data synchronously. It is not
readable or writable by the user. It is possible to use this
bit to determine how many bytes reside in the chip when
an error occurs.

OLF SODL Least Significant Byte Full 5

This bit is set when the least significant byte in the SCSI

Output Data Latch (SODL) contains data. The SCSI Out­put Data Latch (SODL) register is the interface between

the DMA logic and the SCSI bus. In synchronous mode,
data is transferred from the host bus to the SCSI Output

Data Latch (SODL) register, and then to the SODR

register before being sent to the SCSI bus. In
asynchronous mode, data is transferred from the host
bustotheSCSI Output Data Latch (SODL) register, and
then to the SCSI bus. The SODR buffer register is not
used for asynchronous transfers. It is possible to use this
bit to determine how many bytes reside in the chip when
an error occurs.

AIP Arbitration in Progress 4

Arbitration in Progress (AIP = 1) indicates that the
LSI53C770 has detected a Bus Free condition, asserted
BSY, and asserted its SCSI ID onto the SCSI bus.

LOA Lost Arbitration 3

WOA Won Arbitration 2

RST/ SCSI RST/ Signal 1

4-26 Registers

When set, LOA indicates that the LSI53C770 has
detected a bus free condition, arbitrated for the SCSI bus,
and lost arbitration due to another SCSI device asserting
the SEL/ signal.

When set, WOA indicates that the LSI53C770 has
detected a Bus Free condition, arbitrated for the SCSI
bus and won arbitration. The arbitration mode selected in
the SCSI Control Zero (SCNTL0) register must be full
arbitration and selection to set this bit.

This bit reports the current status of the SCSI RST/
signal, and the RST signal (bit 6) in the Interrupt Status

(ISTAT) register. This bit is not latched and may change

as it is read.