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LMU112PC50
Datasheet
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LOGIC LMU112PC50, LMU112JC50, LMU112JC25, LMU112PC25 Datasheet

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DEVICES INCORPORATED
LMU112
12 x 12-bit Parallel Multiplier
LMU112
DEVICES INCORPORATED
FEATURES DESCRIPTION
❑❑
❑ 25 ns Worst-Case Multiply Time
❑❑ ❑❑
❑ Low Power CMOS Technology
❑ Replaces Fairchild MPY112K
❑ Two’s Complement or Unsigned
Operands
❑❑
❑ Three-State Outputs
❑❑ ❑❑
❑ Package Styles Available:
• 48-pin PDIP
• 52-pin PLCC, J-Lead
The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with Fairchilds’s MPY112K.
The A and B input operands are loaded into their respective registers on the rising edge of the separate clock inputs (CLK A and CLK B). Two’s complement or unsigned magnitude operands are accommo­dated via the operand control bit (TC)
LMU112 BLOCK DIAGRAM
A
11-0
12 12
A REGISTERCLK A
CLK B
12 x 12-bit Parallel Multiplier
which is loaded along with the B operands. The operands are specified to be in two’s complement format when TC is asserted and unsigned magnitude when TC is deasserted. Mixed mode operation is not allowed.
For two’s complement operands, the 17 most significant bits at the output of the asynchronous multiplier array are shifted one bit position to the left. This is done to discard the redundant copy of the sign-bit, which is in the most significant bit position, and extend the bit precision by one bit. The result is then truncated to the 16 MSB’s and loaded into the output
B
TC
B REGISTER
11-0
register on the rising edge of CLK B. The contents of the output register are
made available via three-state buffers by asserting OE. When OE is de­asserted, the outputs (R23-8) are in the high impedance state.
OE
24
FORMAT ADJUST
16
RESULT REGISTER
16
R
23-8
1
Multipliers
08/16/2000–LDS.112-K
DEVICES INCORPORATED
FIGURE 1A.INPUT FORMATS
LMU112
12 x 12-bit Parallel Multiplier
IN
A
Fractional Two’s Complement (TC = 1)
11 10 9 2 1 0
–2
(Sign)
0
2–12
–2
2–92
–102–11
Integer Two’s Complement (TC = 1)
11 10 9 2 1 0
11
–2
(Sign)
2102
9
22212
11 10 9 2 1 0
–12–22–3
2
–102–112–12
2
11 10 9 2 1 0
1121029
2
22212
11 10 9 2 1 0
–2
(Sign)
11 10 9 2 1 0
0
–2
(Sign)
Unsigned Fractional (TC = 0)
11 10 9 2 1 0 2
Unsigned Integer (TC = 0)
11 10 9 2 1 0
0
2
0
2–12
11
2102
–12–22–3
1121029
B
IN
–2
9
–102–11
2–92
22212
–102–112–12
2
22212
0
0
FIGURE 1B.OUTPUT FORMATS
23 22 21 14 13 12
0
–2
2–12
(Sign)
23 22 21 14 13 12
22
–2
2212
(Sign)
23 22 21 14 13 12
–12–22–3
2
23 22 21 14 13 12
23222221
2
MSP LSP
Fractional Two’s Complement
11 10 9 8
–2
2–92
–102–11
–122–132–142–15
2
Integer Two’s Complement
11 10 9 8
20
2132122
11
10292827
2
Unsigned Fractional
11 10 9 8
–102–112–12
2
–132–142–152–16
2
Unsigned Integer
11 10 9 8
2142132
12
112102928
2
Multipliers
2
08/16/2000–LDS.112-K
DEVICES INCORPORATED
LMU112
12 x 12-bit Parallel Multiplier
MAXIMUM RATINGS
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground............................................................................ –0.5 V to +7.0V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS
Active Operation, Commercial 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25V Active Operation, Military –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V
ELECTRICAL CHARACTERISTICS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
To meet specified electrical and switching characteristics
Mode Temperature Range (Ambient) Supply Voltage
Over Operating Conditions (Note 4)
Symbol Parameter Test Condition Min Typ Max Unit
VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 V VOL Output Low Voltage VCC = Min., IOL = 8.0 mA 0.5 V VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage (Note 3) 0.0 0.8 V IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±20 µA IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±20 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 10 20 mA ICC2 VCC Current, Quiescent (Note 7) 1.0 mA
Multipliers
3
08/16/2000–LDS.112-K
DEVICES INCORPORATED
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
SWITCHING CHARACTERISTICS
LMU112
12 x 12-bit Parallel Multiplier
COMMERCIAL OPERATING RANGE (0°C to +70°C)
Symbol Parameter Min Max Min Max Min Max
tMC Clocked Multiply Time 60 50 25 tPW Clock Pulse Width 15 15 10 tS Input Register Setup Time 15 15 10 tH Input Register Hold Time 3 3 1 tD Output Delay 25 25 20 tENA Three-State Output Enable Delay (Note 11) 25 25 20 tDIS Three-State Output Disable Delay (Note 11) 25 25 20
MILITARY OPERATING RANGE (–55°C to +125°C)
Symbol Parameter Min Max Min Max Min Max
tMC Clocked Multiply Time 65 55 30 tPW Clock Pulse Width 20 20 12 tS Input Register Setup Time 15 15 12 tH Input Register Hold Time 3 3 3 tD Output Delay 30 30 25 tENA Three-State Output Enable Delay (Note 11) 30 30 25 tDIS Three-State Output Disable Delay (Note 11) 30 30 25
Notes 9, 10 (ns)
Notes 9, 10 (ns)
2345678901
2345678901
*
60
2345678901
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2345678901
2345678901
2345678901
2345678901
2345678901
2345678901
23456789012345678901234567890121
23456789012345678901234567890121
*
65
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
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23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
23456789012345678901234567890121
LMU112–
50 25
LMU112–
*
55
30
*
SWITCHING WAVEFORMS
INPUT
CLK A
CLK B
OE
23-8
R
2345678901234567890123
2345678901234567890123
*DISCONTINUED SPEED GRADE
t
t
S
H
t
MC
t
PW
t
D
t
DIS
t
PW
t
ENA
HIGH IMPEDANCE
Multipliers
4
08/16/2000–LDS.112-K
DEVICES INCORPORATED
S1
I
OH
I
OL
V
TH
C
L
DUT
OE
0.2 V
t
DIS
t
ENA
0.2 V
1.5 V 1.5 V
3.5V Vth
1
Z
0
Z
Z
1
Z
0
1.5 V
1.5 V
0V Vth
VOL*
V
OH
*
V
OL
*
V
OH
*
Measured V
OL
with IOH = –10mA and IOL = 10mA
Measured V
OH
with IOH = –10mA and IOL = 10mA
NOTES
LMU112
12 x 12-bit Parallel Multiplier
1. Maximum Ratings indicate stress specifications only. Functional oper­ation of these products at values beyond those indicated in the Operating Condi­tions table is not implied. Exposure to maximum rating conditions for ex­tended periods may affect reliability.
2. The products described by this spec­ification include internal circuitry de­signed to protect the chip from damag­ing substrate injection currents and ac­cumulations of static charge. Neverthe­less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values.
3. This device provides hard clamping of transient undershoot and overshoot. In­put levels below ground or above VCC will be clamped beginning at –0.6 V and VCC + 0.6 V. The device can withstand indefinite operation with inputs in the range of –0.5 V to +7.0 V. Device opera­tion will not be adversely affected, how­ever, input current levels will be well in excess of 100 mA.
9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed.
This device has high-speed outputs ca­pable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended:
a. A 0.1 µF ceramic capacitor should be installed between VCC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common.
11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing volt­age, VTH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Z­to-1 and 1-to-Z tests.
12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
FIGURE B. THRESHOLD LEVELS
4. Actual test conditions may vary from those designated but operation is guar­anteed as specified.
5. Supply current for a given applica­tion can be accurately approximated by:
2
NCV F
where
4
N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency
6. Tested with all outputs changing ev­ery cycle and no load, at a 5 MHz clock rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed but not 100% tested.
b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers.
c. Input voltages should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin.
10. Each parameter is shown as a min­imum or maximum value. Input re­quirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter­nal system must supply at least that much time to meet the worst-case re­quirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time.
5
Multipliers
08/16/2000–LDS.112-K
DEVICES INCORPORATED
ORDERING INFORMATION
LMU112
12 x 12-bit Parallel Multiplier
48-pin
A A
V V
B B
TC
CLK B
OE R R R R R
52-pin
1
10
2
11
3
B
0
4
B
1
5
B
2
6
B
3
7
B
4
8
B
5
9
B
6
10
B
7
11
B
8
12
CC
13
CC
14
B
9
15
10
16
11
17 18 19 20
23
21
22
22
21
23
20
24
19
48
A
9
47
A
8
46
A
7
45
A
6
44
A
5
43
A
4
42
A
3
41
A
2
40
A
1
39
A
0
38
CLK A
37
GND
36
GND
35
R
8
34
R
9
33
R
10
32
R
11
31
R
12
30
R
13
29
R
14
28
R
15
27
R
16
26
R
17
25
R
18
V V
B B
TC
CLK B
NC
B
4
B
5
B
6
B
7
B
8 CC CC
B
9
10 11
3B2B1B0A11A10A9A8A7A6A5A4
NC
B
1234567
8 9 10 11 12 13 14 15 16 17 18 19 20
23R22R21R20R19R18R17R16R15R14R13
OE
R
52 51 50 49 48 47
Top
View
2827 29 30 31 332221 23 24 25 26
46
NC
45
3
A
44
A
2
43
A
1
42
A
0
41
CLK A
40
GND
39
GND
38
8
R
37
R
9
36
R
10
35
R
11
34
R
32
12
NC
Speed
50 ns 25 ns
Plastic DIP
(P5)
0°C to +70°C — COMMERCIAL SCREENING
LMU112PC50 LMU112PC25
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Plastic J-Lead Chip Carrier
(J5)
LMU112JC50 LMU112JC25
Multipliers
6
08/16/2000–LDS.112-K
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