LOGIC LMU112PC50, LMU112JC50, LMU112JC25, LMU112PC25 Datasheet
DEVICES INCORPORATED
LMU112
12 x 12-bit Parallel Multiplier
LMU112
DEVICES INCORPORATED
FEATURES DESCRIPTION
❑❑
❑ 25 ns Worst-Case Multiply Time
❑❑
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❑ Low Power CMOS Technology
❑❑
❑❑
❑ Replaces Fairchild MPY112K
❑❑
❑❑
❑ Two’s Complement or Unsigned
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Operands
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❑ Three-State Outputs
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❑ Package Styles Available:
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• 48-pin PDIP
• 52-pin PLCC, J-Lead
The LMU112 is a high-speed, low
power 12-bit parallel multiplier built
using advanced CMOS technology.
The LMU112 is pin and functionally
compatible with Fairchilds’s MPY112K.
The A and B input operands are
loaded into their respective registers
on the rising edge of the separate
clock inputs (CLK A and CLK B).
Two’s complement or unsigned
magnitude operands are accommodated via the operand control bit (TC)
LMU112 BLOCK DIAGRAM
A
11-0
12 12
A REGISTERCLK A
CLK B
12 x 12-bit Parallel Multiplier
which is loaded along with the B
operands. The operands are specified
to be in two’s complement format
when TC is asserted and unsigned
magnitude when TC is deasserted.
Mixed mode operation is not allowed.
For two’s complement operands, the
17 most significant bits at the output
of the asynchronous multiplier array
are shifted one bit position to the left.
This is done to discard the redundant
copy of the sign-bit, which is in the
most significant bit position, and
extend the bit precision by one bit.
The result is then truncated to the 16
MSB’s and loaded into the output
B
TC
B REGISTER
11-0
register on the rising edge of CLK B.
The contents of the output register are
made available via three-state buffers
by asserting OE. When OE is deasserted, the outputs (R23-8) are in the
high impedance state.
OE
24
FORMAT ADJUST
16
RESULT REGISTER
16
R
23-8
1
Multipliers
08/16/2000–LDS.112-K
DEVICES INCORPORATED
FIGURE 1A.INPUT FORMATS
LMU112
12 x 12-bit Parallel Multiplier
IN
A
Fractional Two’s Complement (TC = 1)
11 10 9 2 1 0
–2
(Sign)
0
2–12
–2
2–92
–102–11
Integer Two’s Complement (TC = 1)
11 10 9 2 1 0
11
–2
(Sign)
2102
9
22212
11 10 9 2 1 0
–12–22–3
2
–102–112–12
2
11 10 9 2 1 0
1121029
2
22212
11 10 9 2 1 0
–2
(Sign)
11 10 9 2 1 0
0
–2
(Sign)
Unsigned Fractional (TC = 0)
11 10 9 2 1 0
2
Unsigned Integer (TC = 0)
11 10 9 2 1 0
0
2
0
2–12
11
2102
–12–22–3
1121029
B
IN
–2
9
–102–11
2–92
22212
–102–112–12
2
22212
0
0
FIGURE 1B.OUTPUT FORMATS
23 22 21 14 13 12
0
–2
2–12
(Sign)
23 22 21 14 13 12
22
–2
2212
(Sign)
23 22 21 14 13 12
–12–22–3
2
23 22 21 14 13 12
23222221
2
MSP LSP
Fractional Two’s Complement
11 10 9 8
–2
2–92
–102–11
–122–132–142–15
2
Integer Two’s Complement
11 10 9 8
20
2132122
11
10292827
2
Unsigned Fractional
11 10 9 8
–102–112–12
2
–132–142–152–16
2
Unsigned Integer
11 10 9 8
2142132
12
112102928
2
Multipliers
2
08/16/2000–LDS.112-K
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