LOGIC LMS12JC40, LMS12JC35 Datasheet
DEVICES INCORPORATED
LMS12
12-bit Cascadable Multiplier-Summer
LMS12
DEVICES INCORPORATED
12-bit Cascadable Multiplier-Summer
FEATURES DESCRIPTION
❑❑
❑ 12 x 12-bit Multiplier with
❑❑
Pipelined 26-bit Output Summer
❑❑
❑ Summer has 26-bit Input Port Fully
❑❑
Independent from Multiplier
Inputs
❑❑
❑ Cascadable to Form Video Rate FIR
❑❑
Filter with 3-bit Headroom
❑❑
❑ A, B, and C Input Registers Sepa-
❑❑
rately Enabled for Maximum
Flexibility
❑❑
❑ 28 MHz Data Rate for FIR Filtering
❑❑
Applications
❑❑
❑ High Speed, Low Power CMOS
❑❑
Technology
❑❑
❑ 84-pin PLCC, J-Lead
❑❑
The LMS12 is a high-speed 12 x 12-bit
combinatorial multiplier integrated
with a 26-bit adder in a single 84-pin
package. It is an ideal building block
for the implementation of very highspeed FIR filters for video, RADAR,
and other similar applications. The
LMS12 implements the general form
(A•B) + C. As a result, it is also useful
in implementing polynomial approximations to transcendental functions.
ARCHITECTURE
A block diagram of the LMS12 is
shown below. Its major features are
discussed individually in the following paragraphs.
MULTIPLIER
The A11-0 and B11-0 inputs to the
LMS12 are captured at the rising edge
of the clock in the 12-bit A and B input
registers, respectively. These registers
are independently enabled by the
LMS12 BLOCK DIAGRAM
A
11-0
12
ENA ENB
CLK
C
25-0
A REGISTER
24
PRODUCT REGISTER
SIGN
EXTENDED
26 26
26
C REGISTER
B
11-0
B REGISTER
242
12
26
S REGISTER
S
OE
25-0
FTS
ENA and ENB inputs. The registered
input data are then applied to a
12 x 12-bit multiplier array, which
produces a 24-bit result. Both the
inputs and outputs of the multiplier
are in two’s complement format. The
multiplication result forms the input
to the 24-bit product register.
SUMMER
The C25-0 inputs to the LMS12 form a
26-bit two’s complement number
which is captured in the C register at
the rising edge of the clock. The C
register is enabled by assertion of the
ENC input. The summer is a 26-bit
adder which operates on the C
register data and the sign extended
contents of the product register to
produce a 26-bit sum. This sum is
applied to the 26-bit S register.
OUTPUT
The FTS input is the feedthrough
control for the S register. When FTS is
asserted, the summer result is applied
directly to the S output port. When
FTS is deasserted, data from the S
register is output on the S port,
effecting a one-cycle delay of the
summer result. The S output port can
be forced to a high-impedance state by
driving the OE control line high. FTS
would be asserted for conventional
FIR filter applications, however the
insertion of zero-coefficient filter taps
may be accomplished by negating
FTS. Negating FTS also allows
application of the same filter transfer
function to two interleaved datastreams with successive input and
output sample points occurring on
alternate clock cycles.
ENC
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DEVICES INCORPORATED
FIGURE 1. FLOW DIAGRAM FOR 5-TAP FIR FILTER
x(n)
h
h
4
3
LMS12
12-bit Cascadable Multiplier-Summer
h
2
h
1
h
0
x(n)
A
4
h
4
–1
Z
h
Z
APPLICATIONS
The LMS12 is designed specifically for
high-speed FIR filtering applications
requiring a throughput rate of one
output sample per clock period. By
cascading LMS12 units, the transpose
form of the FIR transfer function is
implemented directly, with each of the
LMS12 units supplying one of the
filter weights, and the cascaded
summers accumulating the results.
The signal flow graph for a 5-tap FIR
filter and the equivalent implementation using LMS12’s is shown in
Figure 1.
–1
Z
A
3
3
–1
–1
Z
h
2
–1
Z
–1
Z
A
2
The operation of the 5-tap FIR filter
implementation of Figure 1 is depicted
in Table 1. The filter weights h4 - h0
are assumed to be latched in the B
input registers of the LMS12 units.
The x(n) data is applied in parallel to
the A input registers of all devices.
For descriptive purposes in the table,
the A register contents and sum
output data of each device is labelled
–1
Z
h1
–1
Z
y(n)
A
1
h
Z
A
0
0
–1
according to the index of the weight
applied by that device; i.e., S0 is
produced by the rightmost device,
which has h0 as its filter weight and
A0 as its input register contents. Each
column represents one clock cycle,
with the data passing a particular
point in the system illustrated across
each row.
y(n)
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LMS12
DEVICES INCORPORATED
TABLE 1. TIMING EXAMPLE FOR 5-TAP NONDECIMATING FIR FILTER
CLK Cycle 1 2 3 4 56789
X(n) Xn Xn+1 Xn+2 Xn+3 Xn+4 Xn+5 Xn+6 Xn+7 Xn+8
A4 Register Xn Xn+1 Xn+2 Xn+3 Xn+4 Xn+5 Xn+6 Xn+7
Sum 4 h4Xn h4Xn+1 h4Xn+2 h4Xn+3 h4Xn+4 h4Xn+5 h4Xn+6
A3 Register Xn Xn+1 Xn+2 Xn+3 Xn+4 Xn+5 Xn+6 Xn+7
Sum 3 h3Xn h3Xn+1 h3Xn+2 h3Xn+3 h3Xn+4 h3Xn+5 h3Xn+6
+h4Xn–1 +h4Xn +h4Xn+1 +h4Xn+2 +h4Xn+3 +h4Xn+4 +h4Xn+5
A2 Register Xn Xn+1 Xn+2 Xn+3 Xn+4 Xn+5 Xn+6 Xn+7
Sum 2 h2Xn h2Xn+1 h2Xn+2 h2Xn+3 h2Xn+4 h2Xn+5 h2Xn+6
+h3Xn–1 +h3Xn +h3Xn+1 +h3Xn+2 +h3Xn+3 +h3Xn+4 +h3Xn+5
+h4Xn–2 +h4Xn–1 +h4Xn +h4Xn+1 +h4Xn+2 +h4Xn+3 +h4Xn+4
A1 Register Xn Xn+1 Xn+2 Xn+3 Xn+4 Xn+5 Xn+6 Xn+7
Sum 1 h1Xn h1Xn+1 h1Xn+2 h1Xn+3 h1Xn+4 h1Xn+5 h1Xn+6
+h2Xn–1 +h2Xn +h2Xn+1 +h2Xn+2 +h2Xn+3 +h2Xn+4 +h2Xn+5
+h3Xn–2 +h3Xn–1 +h3Xn +h3Xn+1 +h3Xn+2 +h3Xn+3 +h3Xn+4
+h4Xn–3 +h4Xn–2 +h4Xn–1 +h4Xn +h4Xn+1 +h4Xn+2 +h4Xn+3
A0 Register Xn Xn+1 Xn+2 Xn+3 Xn+4 Xn+5 Xn+6 Xn+7
Sum 0 h0Xn h0Xn+1 h0Xn+2 h0Xn+3 h0Xn+4 h0Xn+5 h0Xn+6
+h1Xn–1 +h1Xn +h1Xn+1 +h1Xn+2 +h1Xn+3 +h1Xn+4 +h1Xn+5
+h2Xn–2 +h2Xn–1 +h2Xn +h2Xn+1 +h2Xn+2 +h2Xn+3 +h2Xn+4
+h3Xn–3 +h3Xn–2 +h3Xn–1 +h3Xn +h3Xn+1 +h3Xn+2 +h3Xn+3
+h4Xn–4 +h4Xn–3 +h4Xn–2 +h4Xn–1 +h4Xn +h4Xn+1 +h4Xn+2
12-bit Cascadable Multiplier-Summer
FIGURE 2A.INPUT FORMATS
11 10 9 2 1 0
0
2–12
–2
–2
(Sign)
11 10 9 2 1 0
11
–2
(Sign)
2102
9
FIGURE 2B.OUTPUT FORMATS
25 24
3
2
–2
2
(Sign)
25 24
25
24
–2
2
(Sign)
A
IN
Fractional Two’s Complement
–102–11
2–92
Integer Two’s Complement
22212
0
Fractional Two’s Complement
23 22 21 14 13 12
1202–1
2
Integer Two’s Complement
23 22 21 14 13 12
23222221
2
2–82–92
2142132
–10
B
IN
11 10 9 2 1 0
0
–2
(Sign)
2–12
–2
2–92
–102–11
11 10 9 2 1 0
11
–2
(Sign)
2102
9
22212
0
11 10 9 2 1 0
–112–122–13
2
–202–212–22
2
11 10 9 2 1 0
12
1121029
2
22212
0
Multiplier-Summers
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