LOGIC LF9502JC25, LF9502JC20 Datasheet
DEVICES INCORPORATED
LF9502
2K Programmable Line Buffer
LF9502
DEVICES INCORPORATED
FEATURES DESCRIPTION
❑❑
❑ 50 MHz Maximum Operating
❑❑
Frequency
❑❑
❑ Programmable Buffer Length from
❑❑
2 to 2049 Clock Cycles
❑❑
❑ 10-bit Data Inputs and Outputs
❑❑
❑❑
❑ Data Delay and Data Recirculation
❑❑
Modes
❑❑
❑ Supports Positive or Negative Edge
❑❑
System Clocks
❑❑
❑ Expandable Data Word Width or
❑❑
Buffer Length
❑❑
❑ 44-pin PLCC, J-Lead
❑❑
The LF9502 is a high-speed, 10-bit
programmable line buffer. Some
applications the LF9502 is useful for
include sample rate conversion, data
time compression/expansion, software controlled data alignment, and
programmable serial data shifting. By
using the MODSEL pin, two different
modes of operation can be selected:
delay mode and data recirculation
mode. The delay mode provides a
minimum of 2 to a maximum of 2049
clock cycles of delay between the
input and output of the device. The
data recirculation mode provides a
feedback path from the data output to
the data input for use as a programmable circular buffer.
By using the length control input
(LC10-0) and the length control enable
(LCEN) the length of the delay buffer
or amount of recirculation delay can
2K Programmable Line Buffer
be programmed. Providing a delay
value on the LC10-0 inputs and driving
LCEN LOW will load the delay value
into the length control register on the
next selected clock edge. Two registers, one preceeding the programmable delay RAM and one following,
are included in the delay path. Therefore, the programmed delay value
should equal the desired delay minus
2. This consequently means that the
value loaded into the length control
register must range from 0 to 2047 (to
provide an overall range of 2 to 2049).
The active edge of the clock input,
either positive or negative edge, can
be selected with the clock select
(CLKSEL) input. All timing is based
on the active clock edge selected by
CLKSEL. Data can be held temporarily by using the clock enable
(CLKEN) input.
LF9502 BLOCK DIAGRAM
DI9-0
CLKSEL
CLKEN
10
CLK
MODSEL
REGISTER
MUX
CLOCK
GENERATOR
10 10
REGISTER
TO ALL REGISTERS
LCO10-0 LCEN
11
REGISTER
11
PROGRAMMABLE
10
10
2K DELAY RAM
10
REGISTER
OE
10
DO
9-0
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08/16/2000–LDS.9502-G
DEVICES INCORPORATED
LF9502
2K Programmable Line Buffer
SIGNAL DEFINITIONS
Power
VCC and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The active edge of CLK, selected by
CLKSEL, strobes all registers. All
timing specifications are referenced to
the active edge of CLK.
Inputs
DI9-0 — Data Input
10-bit data, from the data input, is
latched into the device on the active
edge of CLK when MODSEL is LOW.
LC10-0 — Length Control Input
The 11-bit value is used to specify the
length of the delay buffer, between
DI9-0 and DO9-0, or the amount of
recirculation delay. An integer value
ranging from 0 to 2047 is used to
select a delay ranging from 2 to 2049
clock cycles. The value placed on the
LC10-0 inputs is equal to the desired
delay minus 2. The data presented on
LC10-0 is loaded into the device on the
active edge of CLK, selected by
CLKSEL, in conjunction with LCEN
being driven LOW.
Outputs
DO9-0 — Data Output
The 10-bit data output appears on
DO9-0 on the Nth clock cycle, where N
is the overall delay (desired delay).
Controls
LCEN — Length Control Enable
When LCEN is driven LOW, the next
active clock edge will cause the
loading of the delay value present at
the LC10-0 input.
OE — Output Enable
The Output Enable controls the state
of DO9-0. Driving OE LOW enables
the output port. When OE is HIGH,
DO9-0 is placed in a high-impedance
state. The internal transfer of data is
not affected by this control.
MODSEL — Mode Select
The Mode Select pin is used to choose
the desired mode of operation: data
delay mode or data recirculation
mode. Driving MODSEL LOW places
the device in the delay mode. The
device operates as a programmable
pipeline register. New data from the
DI9-0 input is loaded on every active
edge of CLK. Driving MODSEL
HIGH places the device in the data
recirculation mode. The device
operates as a programmable circular
buffer. The output of the device is
routed back to the input. MODSEL
may be changed during device
operation (synchronously), however,
the required setup and hold times,
with respect to CLK, must be met.
CLKSEL — Clock Select
The CLKSEL control allows the
selection of the active edge of CLK. A
LOW on CLKSEL selects negativeedge triggering of the device. Driving
CLKSEL HIGH selects positive-edge
triggering. All timing specifications
are referrenced to the selected active
edge of CLK.
CLKEN — Clock Enable
The Clock Enable control enables and
disables the CLK input. Driving
CLKEN LOW enables CLK and causes
the device to operate in a normal
fashion. When CLKEN is HIGH, CLK
is disabled and the device will hold all
internal operations and data. CLKEN
may be changed during device
operation (synchronously), however,
the required setup and hold times,
with respect to CLK, must be met.
The changing of CLKEN takes effect
on the active edge of CLK following
the edge in which it was latched.
Video Imaging Products
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08/16/2000–LDS.9502-G
DEVICES INCORPORATED
LF9502
2K Programmable Line Buffer
MAXIMUM RATINGS
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground............................................................................ –0.5 V to +7.0V
Input signal with respect to ground ............................................................................... –0.5 V to VCC + 0.5 V
Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS
Active Operation, Commercial 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V
ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Condition Min Typ Max Unit
Above which useful life may be impaired (Notes 1, 2, 3, 8)
To meet specified electrical and switching characteristics
Mode Temperature Range (Ambient) Supply Voltage
Over Operating Conditions (Note 4)
VOH Output High Voltage VCC = Min., IOH = –4.0 mA 2.4 V
VOL Output Low Voltage VCC = Min., IOL = 4.0 mA 0.4 V
VIH Input High Voltage 2.0 VCC V
VIL Input Low Voltage (Note 3) 0.0 0.8 V
IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±10 µA
IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±10 µA
ICC1 VCC Current, Dynamic (Notes 5, 6) 125 mA
ICC2 VCC Current, Quiescent (Note 7) 500 µA
CIN Input Capacitance TA = 25°C, f = 1 MHz 10 pF
COUT Output Capacitance TA = 25°C, f = 1 MHz 10 pF
Video Imaging Products
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