LOGIC LF48212QC25, LF48212JC25, LF48212JC20, LF48212QC20 Datasheet
DEVICES INCORPORATED
Video Imaging Products
1
LF48212
12 x 12-bit Alpha Mixer
08/16/2000–LDS.48212-F
❑❑
❑❑
❑ 50 MHz Data and Computation
Rate
❑❑
❑❑
❑ Two’s Complement or Unsigned
Operands
❑❑
❑❑
❑ On-board Programmable Delay
Stages
❑❑
❑❑
❑ Programmable Output Rounding
❑❑
❑❑
❑ Replaces Harris HSP48212
❑❑
❑❑
❑ Package Styles Available:
• 68-pin PLCC, J-Lead
• 64-pin PQFP
FEATURES DESCRIPTION
LF48212
12 x 12-bit Alpha Mixer
DEVICES INCORPORATED
The LF48212 is a high-speed video
alpha mixer capable of mixing video
signals at real-time video rates. It
takes two 12-bit video signals and
mixes them together using an alpha
mix factor . Alpha determines the
weighting that each video signal
receives during the mix operation.
The input video data can be in either
unsigned or two’s complement
format, but both inputs must be in the
same format. Independently controlled programmable delay stages are
provided for the input and control
signals to allow for allignment of
input data if necessary. The delay
stages can be programmed to have
from 0 to 7 delays. The 13-bit output
of the alpha mixer is registered with
three-state drivers and may be
rounded to 8, 10, 12, or 13-bits.
LF48212 BLOCK DIAGRAM
DINA
11-0
α
11-0
DINB
11-0
FORMAT
FORMAT
0-7
α
1.0 –
α
0-7
0-7
ADJUST
FORMAT
DOUT
12-0
0-70-7
TC
RND
1-0
DELAY CONTROL
REGISTER
BYPASS
DEL
LD
CLK
MIXEN
OE
NOTE: NUMBERS IN REGISTERS INDICATE
NUMBER OF PIPELINE DELAYS.
12 12 12
13
2
15
44
DEVICES INCORPORATED
LF48212
12 x 12-bit Alpha Mixer
2
Video Imaging Products
08/16/2000–LDS.48212-F
SIGNAL DEFINITIONS
Power
VCC and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers except for the Delay
Control Register .
Inputs
DINA11-0 — Pixel Data Input A
DINA11-0 is one of the 12-bit registered data input ports. Data is latched
on the rising edge of CLK.
DINB11-0 — Pixel Data Input B
DINB11-0 is the other 12-bit registered
data input port. Data is latched on the
rising edge of CLK.
α
11-0 — Alpha Mix Input
α11-0 determines the weighting
applied to the data input signals
before being mixed together. DINA11-0
and DINB11-0 receive weightings of α
and 1.0 – α respectively. α11-0 is
unsigned and restricted to the range of
0 to 1.0. Figure 1 shows the data
format for α11-0. If a value greater
than 1.0 is latched into the Alpha Mix
Input, internal circuitry will force the
value to be equal to 1.0. Data is
latched on the rising edge of CLK.
DEL — Delay Data Input
DEL is used to load the Delay Control
Register . The Delay Contr ol Register
contains a 15-bit value which determines the number of delay stages
added to the input and control signals.
The 15-bit data value is loaded serially
into the Delay Control Register using
DEL and LD. Data present on DEL is
latched on the rising edge of LD.
FIGURE 1. ALPHA MIX INPUT FORMAT
11 10 9 6 5 487 3210
2
02–12–2
2–52–62
–7
2–32
–4
2–82–92
–102–11
Outputs
DOUT12-0 — Data Output
DOUT12-0 is the 13-bit registered data
output port.
Controls
TC — Data Format Control
TC determines if the input data is in
unsigned or two’s complement
format. If TC is LOW, the data is in
two’s complement format. If TC is
HIGH, the data is in unsigned format.
Data present on TC is latched on the
rising edge of CLK. TC only affects
the data that is being latched into the
LF48212. Changing TC does not affect
internal data already in the pipeline.
MIXEN — Alpha Mix Input Enable
When HIGH, data on α11-0 is latched
into the LF48212 on the rising edge of
CLK. When LOW, data on α11-0 is not
latched and the last value loaded is
held as the alpha mix value.
LD — Load Strobe
The rising edge of LD latches the data
on DEL into the Delay Control Register.
BYPASS — Bypass Delay Stage Control
The BYPASS control is used to bypass
the internal programmable delay
stages. When BYPASS is set HIGH,
the Delay Control Register will
automatically be loaded with a “0”.
This will set the number of programmable delay stages to zero for all
input and control signals. When
BYPASS is LOW, the desired number
of delay stages can be set by loading
RND1-0 ROUNDING FORMAT
00 Round to 8-bits
01 Round to 10-bits
10 Round to 12-bits
11 Round to 13-bits
TABLE 1. OUTPUT ROUNDING
the Delay Control Register with the
appropriate value. Note that this
signal is not intended to change
during active operation of the
LF48212.
RND1-0 — Output Rounding Control
RND1-0 determines how the output of
the LF48212 is rounded. The output
may be rounded to 8, 10, 12, or 13-bits.
Table 1 lists the different rounding
possibilities and the associated value
for RND1-0. Rounding is accomplished by adding a “1” to the bit to
the right of what will become the least
significant bit. Then the bit that had
the “1” added to it and all bits to the
right of it are set to “0”. Data present
on RND1-0 is latched on the rising
edge of CLK. When RND1-0 is latched
in, it only applies to the video input
data latched in at the same time.
Changing RND1-0 does not affect the
rounding format for internal data
already in the pipeline.
OE — Output Enable
When OE is LOW, DOUT12-0 is
enabled for output. When OE is
HIGH, DOUT12-0 is placed in a highimpedance state.
DEVICES INCORPORATED
Video Imaging Products
3
LF48212
12 x 12-bit Alpha Mixer
08/16/2000–LDS.48212-F
FUNCTIONAL DESCRIPTION
The two video signals to be mixed
together are input to the LF48212
using DINA11-0 and DINB11-0. Data
present on DINA11-0 and DINB11-0 is
latched on the rising edge of CLK.
The input data may be in either
unsigned or two’s complement
format, but both inputs must be in the
same format. TC determines the
format of the input data. When TC is
HIGH, the input data is in unsigned
format. When TC is LOW, the input
data is in two’s complement format.
TC is latched on the rising edge of
CLK and only affects the input data
latched in at the same time. The data
already in the pipeline is not affected
when TC changes.
DINA11-0 and DINB11-0 are mixed
together using an alpha mix factor
(α11-0) as defined by the equation
listed in Figure 2. α11-0 is unsigned
and restricted to the range of 0 to 1.0.
MIXEN controls the loading of alpha
mix data. When MIXEN is HIGH,
data present on α11-0 is latched on the
rising edge of CLK. When MIXEN is
LOW, data present on α11-0 is not
latched and the last value loaded is
held as the alpha mix value.
It is possible to add extra delay stages
to the input data and control signals
by using the programmable delay
stages. The 15-bit value (DELAY14-0)
stored in the Delay Control Register
determines the number of delay stages
added. DELAY14-0 is divided into 5
groups of 3-bits each. Each 3-bit
group contains the delay information
for one of the input data or control
signals. Figure 3 shows the block
diagram of the Delay Control Register
as well as a list of the input data and
control signals that may be delayed
and the DELAY signals that control
them. The delay length can be programmed to be from 0 to 7 stages. The
delay length is set by loading the
binary equivalent of the desired delay
length into the appropriate 3-bit
group. For example, to add four extra
delay stages to DINB11-0, DELAY5-3
should be set to “100”. DELAY14-0 is
loaded serially into the Delay Control
Register using DEL and LD. DELAY0
is the first value loaded and DELAY14
is the last. Data present on DEL is
latched on the rising edge of LD.
BYPASS is used to disable the programmable delay stages. When
BYPASS is HIGH, the Delay Control
Register is automatically loaded with
a “0”. This sets all programmable
delay stages to a length of zero. When
BYPASS is LOW, the Delay Control
Register may be loaded to set the
desired number of delay stages. Note
that BYPASS is not intended to change
during active operation of the
LF48212.
The Adjust stage of the LF48212 is
used to maximize the precision of the
output data. Since α can never be
larger than 1.0, the most significant bit
of the internal summer output is not
needed. The Adjust stage takes the
output of the internal summer and left
shifts the data one bit position. This
removes the MSB of the internal
summer output and provides one
more bit of precision for the output
data.
The output data of the LF48212 may
be rounded to 8, 10, 12, or 13-bits.
RND1-0 determines how the output is
rounded (See Table 1). RND1-0 is
latched on the rising edge of CLK and
only affects the input data latched in
at the same time. The data already in
the pipeline is not affected when
RND1-0 changes.
FIGURE 3. DELAY CONTROL REGISTER BLOCK DIAGRAM
DEL
LD
DQ DQ DQ
DELAY
14
DELAY
13
DELAY
12
LD LD
DQ DQ DQ
DELAY
11
DELAY
10
DELAY
9
LD LD
DQ DQ DQ
DELAY
8
DELAY
7
DELAY
6
LD LD
DQ DQ DQ
DELAY
5
DELAY
4
DELAY
3
LD LD
DQ DQ DQ
DELAY
2
DELAY
1
DELAY
0
LD LD
RND
1-0
DELAY
TC DELAY
α
11-0
DELAY
DINB
11-0
DELAY
DINA
11-0
DELAY
FIGURE 2. OUTPUT EQUATION
OUTPUT = α(DINA) + (1 – α)DINB
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