LOGIC LF3347QC15, LF3347QC12 Datasheet
DEVICES INCORPORATED
LF3347
High-Speed Image Filter with Coefficient RAM
LF3347
DEVICES INCORPORATED
High-Speed Image Filter with Coefficient RAM
FEATURES DESCRIPTION
❑❑
❑ 83 MHz Data Input and Compu-
❑❑
tation Rate
❑❑
❑ Four 12 x 12-bit Multipliers with
❑❑
Individual Data and Coefficient
Inputs
❑❑
❑ Four 256 x 12-bit Coefficient Banks
❑❑
❑❑
❑ 32-bit Accumulator
❑❑
❑❑
❑ Selectable 16-bit Data Output with
❑❑
User-Defined Rounding and Limiting
❑❑
❑ Two’s Complement Operands
❑❑
❑❑
❑ 3.3 Volt Power Supply
❑❑
❑❑
❑ 5 Volt Tolerant I/O
❑❑
❑ ❑
❑ 120-pin PQFP
❑ ❑
The LF3347 consists of an array of
four 12 x 12-bit registered multipliers
followed by two summers and a
32-bit accumulator. The LF3347
provides four 256 x 12-bit coefficient
banks which are capable of storing
256 different sets of filter coefficients
for the multiplier array. All multiplier data inputs are user accessible
and can be updated every clock cycle
with two’s complement data. The
pipelined architecture has fully
registered input and output ports and
an asynchronous three-state output
enable control to simplify the design
of complex systems.
LF3347 BLOCK DIAGRAM
12
CC
11-0
LD
CCCLK
ENBA
A
7-0
INTERFACE
8
LF
Coefficient
Bank 1
(256 x 12-bit)
Coefficient
Bank 2
(256 x 12-bit)
Coefficient
Bank 3
(256 x 12-bit)
A 32-bit accumulator allows cumulative word growth which may be
internally rounded to 16-bits. Output
data is updated every clock cycle and
may be held under user control. The
data inputs/outputs and control
inputs are registered on the rising
edge of CLK. The Control/Coefficient Data Input, CC11-0, is registered
on the rising edge of CCCLK.
The LF3347 is ideal for performing
pixel interpolation in image manipulation and filtering applications. The
LF3347 can perform a bilinear interpolation of an image (4-pixel kernels)
at real-time video rates when used
Coefficient
Bank 4
(256 x 12-bit)
D1
11-0
ENB
1
12 12
2222
ACC
SHIFT
4-0
OE
CLK TO ALL REGISTERS
3
5
5
25
D2
11-0
ENB
2
12 12
D3
11-0
ENB
3
12 12
32
Rounding
5
Selecting
Limiting
Circuit
16
16
S
15-0
Rounding/
Limiting
Registers
NOTE: NUMBERS IN REGISTERS INDICATE
D4
11-0
ENB
4
12 12
25
LMTENSELLMT
SELRND
3-0
4 4
466
4 4
OCEN
NUMBER OF PIPELINE DELAYS
3-0
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DEVICES INCORPORATED
11 10 9 2 1 0
–2
0
(Sign)
2–12
–2
2–92
–102–11
11 10 9 2 1 0
–2
0
(Sign)
2–12
–2
2–92
–102–11
11 10 9 2 1 0
–2
11
(Sign)
2102
9
22212
0
11 10 9 2 1 0
–2
11
(Sign)
2102
9
22212
0
Fractional Two's Complement
Integer Two's Complement
Data Coefficient
LF3347
High-Speed Image Filter with Coefficient RAM
with an image resampling sequencer. Larger kernels or more
complex functions can be realized
by utilizing multiple devices.
Unrestricted access to all data
ports and addressable coefficient
banks provides the LF3347 with
considerable flexibility in applications such as digital filters, adaptive FIR filters, mixers, and other
similar systems requiring highspeed processing.
SIGNAL DEFINITIONS
Power
VCC and GND
+3.3 V power supply. All pins must
be connected.
Clocks
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
FIGURE 1. INPUT FORMATS
TABLE 1. OUTPUT FORMATS
SHIFT4-0 S15 S14 S13 · · · S8 S7 · · · S2 S1 S0
00000 F15 F14 F13 · · · F8 F7 · · · F2 F1 F0
00001 F16 F15 F14 · · · F9 F8 · · · F3 F2 F1
00010 F17 F16 F15 · · · F10 F9 · · · F4 F3 F2
· ··· ·· ···
· ··· ·· ···
· ··· ·· ···
01110 F29 F28 F27 · · · F22 F21 · · · F16 F15 F14
CCCLK — Coefficient/Control Clock
When LD is LOW, the rising edge of
CCCLK latches data on CC11-0 into the
device.
Inputs
D111-0 – D411-0 — Data Input
D1–D4 are the 12-bit registered data
input ports. Data is latched on the
rising edge of CLK.
A7-0 — Row Address
A7-0 determines which row in the
coefficient banks feed data to the
multipliers. A7-0 is latched on the
rising edge of CLK. When a new
row address is loaded into the row
address register, data from the
coefficient banks will be latched into
the multiplier input registers on the
next rising edge of CLK.
01111 F30 F29 F28 · · · F23 F22 · · · F17 F16 F15
10000 F31 F30 F29 · · · F24 F23 · · · F18 F17 F16
CC11-0 — Control/Coefficient Data Input
CC11-0 is used to load data into the
coefficient banks and control registers. Data present on CC11-0 is
latched on the rising edge of CCCLK
when LD is LOW.
Outputs
S15-0 — Data Output
S15-0 is the 16-bit registered data
output port.
Controls
ENB1–ENB4 — Data Input Enables
The ENBN (N = 1, 2, 3, or 4) inputs
allow the DN registers to be updated
on each clock cycle. When ENBN is
LOW, data on DN11-0 is latched into
the DN register on the rising edge of
CLK. When ENBN is HIGH, data on
DN11-0 is not latched into the DN
register and the register contents
will not be changed.
ENBA — Row Address Input Enable
The ENBA input allows the row
address register to be updated on
each clock cycle. When ENBA is
LOW, data on A7-0 is latched into
the row address register on the rising
edge of CLK. When ENBA is HIGH,
data on A7-0 is not latched into the
row address register and the register
contents will not be changed.
OE — Output Enable
When OE is LOW, S15-0 is enabled for
output. When OE is HIGH, S15-0 is
placed in a high-impedance state.
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LF3347
DEVICES INCORPORATED
TABLE 2. REGISTER FORMATS
Register Load Address Bits Register Description A7-0 SELRND3-0 SELLMT3-0
CS0 000H 11-0 Coefficient Set 0 00H
CS1 001H 11-0 Coefficient Set 1 01H
··· · ·
··· · ·
··· · ·
CS255 0FFH 11-0 Coefficient Set 255 FFH
RND0 800H 31-0 Rounding Register 0 0 0 0 0
RND1 801H 31-0 Rounding Register 1 0 0 0 1
··· · ·
··· · ·
··· · ·
RND15 80FH 31-0 Rounding Register 15 1 1 1 1
LMT0 C00H 31-16/15-0 Upper / Lower Limit Register 0 0 0 0 0
LMT1 C01H 31-16/15-0 Upper / Lower Limit Register 0 0 0 0 1
··· · ·
··· · ·
··· · ·
LMT15 C0FH 31-16/15-0 Upper / Lower Limit Register 15 1 1 1 1
High-Speed Image Filter with Coefficient RAM
OCEN — Output Clock Enable
When OCEN is LOW, the output
register is enabled for data loading.
When OCEN is HIGH, output register
loading is disabled and the register’s
contents will not change.
ACC — Accumulator Control
The ACC input determines whether
internal accumulation is performed. If
ACC is LOW, no accumulation is
performed, the prior accumulated sum
is cleared, and the current sum of
products is output. When ACC is
HIGH, the emerging product is added
to the sum of the previous products.
LD — Load Control
LD enables the loading of data into the
coefficient banks and control registers
(control registers are the round and limit
registers). When LD is LOW, data on
CC11-0 is latched into the device on the
rising edge of CCCLK. When LD is
HIGH, data cannot be loaded into the
coefficient banks and control registers.
When enabling the input circuitry for
data loading, the LF3347 requires a
HIGH to LOW transition of LD in order
to function properly. Therefore, LD
needs to be set HIGH immediately after
power up to ensure proper operation of
the input circuitry.
It takes five CCCLK clock cycles to load
one coefficient set into the four coefficient
banks or to load one control register.
When the input circuitry is enabled (LD
goes LOW), the first value loaded into the
device on CC11-0 is an address which
determines what will be loaded (see
Table 2). The next four values loaded on
CC11-0 is the data to be loaded into the
coefficient banks or control register (see
Tables 3-5). After the last data value is
loaded, another coefficient bank address
or control register may be loaded by
feeding another address into CC11-0.
When all desired coefficient banks and
control registers are loaded, the input
circuitry must be disabled by setting LD HIGH.
SELRND3-0 — Round Select
SELRND3-0 allows the user to select
which rounding register will be used
in the rounding circuit to round/offset
the data.
SHIFT4-0 — Shift
SHIFT4-0 determines which 16-bits of
the 32-bits from the accumulator are
passed to the output (see Table 1).
FIGURE 2. ROUNDING, SELECTING,
LIMITING CIRCUITRY
32
RND
31-0
SHIFT
4-0
ULMT
15-0
LLMT
15-0
SELLMT3-0 — Limit Select
SELLMT3-0 allows the user to control
which limiting register will be used in
the limiting circuit to set the upper
and lower limits on the data.
LMTEN — Limit Enable
When LMTEN is LOW, limiting is
enabled and the selected limit register
is used to determine the valid range of
output values for the overall filter.
When HIGH, limiting is disabled.
RND
32
32
SELECT
16
16
LIMIT
16
LMTEN
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