LOGIC LF3310QC15, LF3310QC12 Datasheet
DEVICES INCORPORATED
LF3310
Horizontal / Vertical Digital Image Filter
LF3310
DEVICES INCORPORATED
Horizontal / Vertical Digital Image Filter
FEATURES DESCRIPTION
❑❑
❑ 83 MHz Data Rate
❑❑
❑❑
❑ 12-bit Data and Coefficients
❑❑
❑❑
❑ On-board Memory for 256 Horizontal
❑❑
and Vertical Coefficient Sets
❑❑
❑ LF InterfaceTM Allows All 512
❑❑
Coefficient Sets to be Updated
Within Vertical Blanking
❑❑
❑ Selectable 12-bit Data Output with
❑❑
User-Defined Rounding and
Limiting
❑❑
❑ Seven 3K x 12-bit, Programmable
❑❑
Two-Mode Line Buffers
❑❑
❑ 16 Horizontal Filter Taps
❑❑
❑❑
❑ 8 Vertical Filter Taps
❑❑
❑❑
❑ Two Operating Modes: Dimension-
❑❑
ally Separate and Orthogonal
❑❑
❑ Supports Interleaved Data Streams
❑❑
❑❑
❑ Horizontal Filter Supports Decima-
❑❑
tion up to 16:1 for Increasing
Number of Filter Taps
❑❑
❑ 3.3 Volt Power Supply
❑❑
❑❑
❑ 5 Volt Tolerant I/O
❑❑
❑❑
❑ 144 Lead PQFP
❑❑
The LF3310 is a two-dimensional digital
image filter capable of filtering data at
real-time video rates. The device
contains both a horizontal and a
vertical filter which may be cascaded or
used concurrently for two-dimensional
filtering. The input, coefficient, and
output data are all 12-bits and in two’s
complement format.
The horizontal filter is designed to take
advantage of symmetric coefficient sets.
When symmetric coefficient sets are
used, the horizontal filter can be
configured as a 16-tap FIR filter. When
asymmetric coefficient sets are used, it
can be configured as an 8-tap FIR filter.
The vertical filter is an 8-tap FIR filter
with all required line buffers contained
on-chip. The line buffers can store
video lines with lengths from 4 to 3076
pixels.
Horizontal filter Interleave/Decimation Registers (I/D Registers) and the
vertical filter line buffers allow
interleaved data to be fed directly into
the device and filtered without
separating the data into individual
data streams. The horizontal filter
can handle a maximum of sixteen
data sets interleaved together. The
vertical filter can handle interleaved
video lines which contain 3076 or less
data values. The I/D Registers and
horizontal accumulator facilitate
using decimation to increase the
number of filter taps in the horizontal
filter. Decimation of up to 16:1 is
supported.
The device has on-chip storage for 256
horizontal coefficient sets and 256
vertical coefficient sets. Each filter’s
coefficients are loaded independently
of each other allowing one filter’s
coefficients to be updated without
affecting the other filter’s coefficients.
In addition, a horizontal or vertical
coefficient set can be updated independently from the other coefficient
sets in the same filter.
LF3310 BLOCK DIAGRAM
DIN
11-0
12
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
8-TAP VERTICAL FILTER
256 COEFFICIENT SET STORAGE
1
16-TAP HORIZONTAL FILTER
256 COEFFICIENT SET STORAGE
12
DOUT
11-0
Video Imaging Products
11/08/2001-LDS.3310-H
DEVICES INCORPORATED
FIGURE 1. LF3310 FUNCTIONAL BLOCK DIAGRAM
LF3310
Horizontal / Vertical Digital Image Filter
IEO
DATA
REVERSAL
1-16
1-16
1-16
1-16
I/D REGISTERS
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
ALU
AB
ALU
AB
ALU
AB
ALU
AB
ALU
AB
ALU
AB
ALU
13 13 13 13 13 13 13
AB
ALU
13
AB
H Coef Bank 7
12
12
H Coef Bank 612H Coef Bank 5
12
12
12
H Coef Bank 4
12
12
3-0
HACC
"0"
32
32
DATA
DELAY
27 27
25 25 25 25 25 25 25 25
26
HRSL
4
LIMIT
3232
ROUND
SELECT
HORIZONTAL
12
LIMIT
ROUND
SELECT
VERTICAL
"0"
26
OE
11-0
12
DOUT
3-0
4
VRSL
VACC
TXFR
DATA
DELAY
H Coef Bank 0
H Coef Bank 1
CONFIGURATION AND
CONTROL REGISTERS
LF
LF
VERTICAL
INTERFACE
HORIZONTAL
12
12
11-0
11-0
DIN
HCF
HPAUSE
INTERFACE
12
11-0
VLD
HLD
VCF
VPAUSE
HCEN
H Coef Bank 2
8
7-0
HCA
H Coef Bank 3
8
VCEN
7-0
VCA
V Coef Bank 7 V Coef Bank 6 V Coef Bank 5 V Coef Bank 4
24
24
24
24
24
24
24
24
12
V Coef Bank 3
12
V Coef Bank 2
12
V Coef Bank 1
12 12 12 12
12
12
12
12
12
12
12
3K Line Buffer
3K Line Buffer
3K Line Buffer
3K Line Buffer
3K Line Buffer
3K Line Buffer
12
3K Line Buffer
12
V Coef Bank 0
CLK
VSHEN
HSHEN
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DEVICES INCORPORATED
31 30 29 2 1 0
–2
20
(Sign)
2192
18
2–92
–102–11
31 30 29 2 1 0
–2
20
(Sign)
2192
18
2–92
–102–11
Horizontal Accumulator Output Vertical Accumulator Output
LF3310
Horizontal / Vertical Digital Image Filter
SIGNAL DEFINITIONS
Power
VCC and GND
+3.3 V power supply. All pins must
be connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
Inputs
DIN11-0 — Data Input
DIN11-0 is the 12-bit registered data
input port. Data is latched on the
rising edge of CLK.
HCF11-0 — Horizontal Coefficient Input
HCF11-0 is used to load data into the
horizontal coefficient banks and the
Configuration/Control Registers.
Data present on HCF11-0 is latched
into the Horizontal LF InterfaceTM on
the rising edge of CLK when HLD is
LOW (see the LF InterfaceTM section
for a full discussion).
FIGURE 2. INPUT FORMATS
Input Data Coefficient Data
11 10 9 2 1 0
11
–2
(Sign)
2102
9
22212
0
11 10 9 2 1 0
–2
(Sign)
0
2–12
–2
2–92
–102–11
FIGURE 3. HORIZONTAL AND VERTICAL ACCUMULATOR FORMATS
TABLE 1. OUTPUT FORMATS
SLCT4-0 S11 S10 S9 · · · S6 S5 · · · S2 S1 S0
00000 F11 F10 F9 · · · F6 F5 · · · F2 F1 F0
00001 F12 F11 F10 · · · F7 F6 · · · F3 F2 F1
00010 F13 F12 F11 · · · F8 F7 · · · F4 F3 F2
· ··· ·· ···
· ··· ·· ···
· ··· ·· ···
10010 F29 F28 F27 · · · F24 F23 · · · F20 F19 F18
HCA7-0 — Horizontal Coefficient
Address
10011 F30 F29 F28 · · · F25 F24 · · · F21 F20 F19
10100 F31 F30 F29 · · · F26 F25 · · · F22 F21 F20
HCA7-0 determines which row of data
in the horizontal coefficient banks is
fed to the multipliers in the horizontal
filter. HCA7-0 is latched into the
Horizontal Coefficient Address
Register on the rising edge of CLK
when HCEN is LOW.
VCF11-0 — Vertical Coefficient Input
VCA7-0 — Vertical Coefficient Address
VCA7-0 determines which row of data
in the vertical coefficient banks is fed
to the multipliers in the vertical filter.
VCA7-0 is latched into the Vertical
Coefficient Address Register on the
rising edge of CLK when VCEN is
LOW.
VCF11-0 is used to load data into the
vertical coefficient banks and the
Configuration/Control Registers.
Data present on VCF11-0 is latched
into the Vertical LF InterfaceTM on the
rising edge of CLK when VLD is
Outputs
DOUT11-0 — Data Output
DOUT11-0 is the 12-bit registered data
output port.
LOW (see the LF InterfaceTM section
for a full discussion).
3
Controls
HLD — Horizontal Coefficient Load
When HLD is LOW, data on HCF11-0
is latched into the Horizontal LF
InterfaceTM on the rising edge of CLK.
When HLD is HIGH, data can not be
latched into the Horizontal LF
InterfaceTM. When enabling the LF
InterfaceTM for data input, a HIGH to
LOW transition of HLD is required in
order for the input circuitry to function properly. Therefore, HLD must
be set HIGH immediately after power
up to ensure proper operation of the
input circuitry (see the LF Interface
TM
section for a full discussion).
Video Imaging Products
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DEVICES INCORPORATED
LF3310
Horizontal / Vertical Digital Image Filter
HCEN —Horizontal Coefficient
Address Enable
When HCEN is LOW, data on HCA7-0
is latched into the Horizontal Coefficient Address Register on the rising
edge of CLK. When HCEN is HIGH,
data on HCA7-0 is not latched and the
register’s contents will not be
changed.
VLD — Vertical Coefficient Load
When VLD is LOW, data on VCF11-0
is latched into the Vertical LF
InterfaceTM on the rising edge of CLK.
When VLD is HIGH, data can not be
latched into the Vertical LF
InterfaceTM. When enabling the LF
InterfaceTM for data input, a HIGH to
LOW transition of VLD is required in
order for the input circuitry to function properly. Therefore, VLD must
be set HIGH immediately after power
up to ensure proper operation of the
input circuitry (see the LF Interface
TM
section for a full discussion).
VCEN — Vertical Coefficient Address
Enable
When VCEN is LOW, data on VCA7-0
is latched into the Vertical Coefficient
Address Register on the rising edge of
CLK. When VCEN is HIGH, data on
VCA7-0 is not latched and the
register’s contents will not be
changed.
TXFR — Horizontal Filter LIFO
Transfer Control
TXFR is used to change which LIFO in
the data reversal circuitry sends data to
the reverse data path and which LIFO
receives data from the forward data
path. When TXFR goes LOW, the LIFO
sending data to the reverse data path
becomes the LIFO receiving data from
the forward data path, and the LIFO
receiving data from the forward data
path becomes the LIFO sending data to
the reverse data path. The device must
see a HIGH to LOW transition of TXFR
in order to switch LIFOs.
HACC —Horizontal Accumulator
Control
When HACC is HIGH, the horizontal
accumulator is enabled for accumulation and the accumulator output
register is disabled for loading. When
HACC is LOW, no accumulation is
performed and the accumulator
output register is enabled for loading.
HACC is latched on the rising edge of
CLK.
VACC — Vertical Accumulator Control
When VACC is HIGH, the vertical
accumulator is enabled for accumulation and the accumulator output
register is disabled for loading. When
VACC is LOW, no accumulation is
performed and the accumulator
output register is enabled for loading.
VACC is latched on the rising edge of
CLK.
HSHEN — Horizontal Shift Enable
HSHEN enables or disables the
loading of data into the forward and
reverse I/D Registers in the horizontal filter when the device is in Dimensionally Separate Mode. If the device
is configured such that the horizontal
filter feeds the vertical filter, HSHEN
also enables or disables the loading of
data into the input register (DIN11-0).
If the device is configured such that
the vertical filter feeds the horizontal
filter and the vertical limit register is
under shift control, HSHEN also
enables or disables the loading of data
into the vertical limit register in the
vertical Round/Select/Limit circuitry.
In Orthogonal Mode, HSHEN also
enables or disables the loading of data
into the input register (DIN11-0) and
the line buffers in the vertical filter. It
is important to note that in Orthogonal Mode, either HSHEN or VSHEN
can disable data loading. Both must
be active to enable data loading in
Orthogonal Mode. Also in Orthogonal Mode, the horizontal and vertical
limit registers can not be disabled.
When HSHEN is LOW, data is loaded
into and shifted through the registers
HSHEN controls and the forward and
reverse I/D Registers on the rising
edge of CLK. When HSHEN is
HIGH, data is not loaded into or
shifted through the registers HSHEN
controls and the I/D Registers, and
their contents will not be changed.
HSHEN is latched on the rising edge
of CLK.
VSHEN — Vertical Shift Enable
VSHEN enables or disables the
loading of data into the line buffers in
the vertical filter when the device is in
Dimensionally Separate Mode. If the
device is configured such that the
vertical filter feeds the horizontal
filter, VSHEN also enables or disables
the loading of data into the input
register (DIN11-0). If the device is
configured such that the horizontal
filter feeds the vertical filter and the
horizontal limit register is under shift
control, VSHEN also enables or
disables the loading of data into the
horizontal limit register in the horizontal Round/Select/Limit circuitry.
In Orthogonal Mode, VSHEN also
enables or disables the loading of data
into the input register (DIN11-0) and
the forward and reverse I/D Registers
in the horizontal filter. It is important
to note that in Orthogonal Mode,
either HSHEN or VSHEN can disable
data loading. Both must be active to
enable data loading in Orthogonal
Mode. Also in Orthogonal Mode, the
horizontal and vertical limit registers
can not be disabled.
When VSHEN is LOW, data is loaded
into and shifted through the registers
VSHEN controls and the line buffers
on the rising edge of CLK. When
VSHEN is HIGH, data is not loaded
into or shifted through the registers
VSHEN controls and the line buffers,
and their contents will not be
changed. VSHEN is latched on the
rising edge of CLK.
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DEVICES INCORPORATED
DIN
11-0
HORIZONTAL FILTER
VERTICAL FILTER
LINE BUFFER
12
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
DOUT
11-0
12
12
LF3310
Horizontal / Vertical Digital Image Filter
HRSL3-0 — Horizontal Round/Select/
Limit Control
HRSL3-0 determines which of the
sixteen user-programmable Round/
Select/Limit registers (RSL registers)
are used in the horizontal Round/
Select/Limit circuitry (RSL circuitry).
A value of 0 on HRSL3-0 selects
RSL register 0. A value of 1 selects
round/select/limit register 1 and so
on. HRSL3-0 is latched on the rising
edge of CLK (see the horizontal
round, select, and limit sections for a
complete discussion).
VRSL3-0 —Vertical Round/Select/Limit
Control
VRSL3-0 determines which of the
sixteen user-programmable
RSL registers are used in the vertical
RSL circuitry. A value of 0 on
VRSL3-0 selects RSL register 0. A
value of 1 selects RSL register 1 and
so on. VRSL3-0 is latched on the rising
edge of CLK (see the vertical round,
select, and limit sections for a complete discussion).
FIGURE 4. DIMENSIONALLY SEPARATE MODE: H TO V
DIN
11-0
12
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
HORIZONTAL FILTER
12
12
VERTICAL FILTER
FIGURE 5. DIMENSIONALLY SEPARATE MODE: V TO H
DOUT
11-0
OE — Output Enable
When OE is LOW, DOUT11-0 is
enabled for output. When OE is
HIGH, DOUT11-0 is placed in a
high-impedance state.
HPAUSE — LF InterfaceTM Pause
When HPAUSE is HIGH, the Horizontal LF InterfaceTM loading
sequence is halted until HPAUSE is
returned to a LOW state. This
effectively allows the user to load
coefficients and Control Registers at a
slower rate than the master clock (see
the LF InterfaceTM section for a full
discussion).
VPAUSE — LF InterfaceTM Pause
When VPAUSE is HIGH, the Vertical
LF InterfaceTM loading sequence is
halted until VPAUSE is returned to a
LOW state. This effectively allows the
user to load coefficients and Control
Registers at a slower rate than the
master clock (see the LF Interface
TM
section for a full discussion).
OPERATIONAL MODES
Dimensionally Separate
In Dimensionally Separate Mode, the
horizontal and vertical filters are
cascaded together to form a
two-dimensional image filter (see
Figures 4 and 5). Bit 1 in Configuration Register 4 determines the cascade
order. If this bit is set to “0”, data on
5
DIN11-0 is fed into the horizontal filter
first. The horizontal filter then feeds
data into the vertical filter. If this bit
is set to “1”, data on DIN11-0 is fed
into the vertical filter first. The
vertical filter then feeds data into the
horizontal filter.
Orthogonal
In Orthogonal Mode, the horizontal
and vertical filters are used concurrently to implement an orthogonal
kernel on the input data (see Figure 6).
Video Imaging Products
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DEVICES INCORPORATED
LF3310
Horizontal / Vertical Digital Image Filter
FIGURE 6. ORTHOGONAL MODE
DIN
11-0
12
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
DATA
DELAY
HORIZONTAL FILTER
DATA
DELAY
VERTICAL FILTER
12
DOUT
FIGURE 7. 3-3, 5-5, AND 7-7 ORTHOGONAL KERNELS
V
1
V
V
1
H
HV
2
H
1
H
3
V
3
1
The HV Filter can handle kernel sizes
of 3-3, 5-5, and 7-7 (see Figure 7).
Data delay elements at the input of
the horizontal filter and the output of
the vertical filter are used to properly
align data so that the orthogonal
kernel is implemented correctly. The
data delays are automatically set to
the correct lengths based on the
programmed length of the line buffers
and the kernel size.
Kernel sizes of 3-3, 5-5, and 7-7
require that the horizontal filter’s
output be delayed by LB – 2, 2(LB) – 3,
and 3(LB) – 4 clock cycles respectively
before being added to the vertical
filter’s output (LB is the programmed
2
H
2
H
HV
3
H
2
H
4
H
5
V
4
V
5
1
line buffer length). The data delay at
the input of the horizontal filter
handles the LB, 2(LB), and 3(LB)
delays. The data delay at the output
of the vertical filter handles the – 2, – 3,
and – 4 delays. For example, if the line
buffers are programmed for a length of
720 and a 5–5 kernel is selected, the
horizontal filter input data delay will
be 1440 clock cycles and the vertical
filter output data delay will be 3 clock
cycles.
It is important to note that the first 3,
5, or 7 multipliers of the horizontal
and vertical filters must be used in
Orthogonal Mode. If other multipliers are used, data from the horizontal
and vertical filters will not line up
correctly because the data delays are
calculated assuming that the first 3, 5,
or 7 multipliers are used. Also, the
ALUs in the horizontal filter should
be configured to accept data from the
forward I/D Register path into ALU
Input A and force ALU Input B to 0.
FUNCTIONAL DESCRIPTION
Horizontal Filter
The horizontal filter is designed to
filter a digital image in the horizontal
dimension. This FIR filter can be
configured to have as many as 16-taps
when symmetric coefficient sets are
used and 8-taps when asymmetric
coefficient sets are used.
11-0
ALUs
The ALUs double the number of filter
taps available, when symmetric
V
1
V
2
V
3
HV
4
H
3
H
5
H
6
H
7
coefficient sets are used, by
pre-adding data values which are
then multiplied by a common coefficient (see Figure 8). The ALUs can
perform two operations: A+B and
B–A. Bit 0 of Configuration Register 0 determines the ALU operation.
V
5
V
6
V
7
A+B is used with even-symmetric
coefficient sets. B–A is used with
odd-symmetric coefficient sets. Also,
either the A or B operand may be set
to 0. Bits 1 and 2 of Configuration
Register 0 control the ALU inputs.
A+0 or B+0 are used with asymmetric
coefficient sets.
Interleave/Decimation Registers
The Interleave/Decimation Registers
(I/D Registers) feed the ALU inputs.
They allow the device to filter up to
sixteen data sets interleaved into the
same data stream without having to
separate the data sets. The I/D
Registers should be set to a length
equal to the number of data sets
interleaved together. For example, if
two data sets are interleaved together,
the I/D Registers should be set to a
length of two. Bits 1 through 4 of
Configuration Register 1 determine
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DEVICES INCORPORATED
FIGURE 8. SYMMETRIC COEFFICIENT SET EXAMPLES
12345678
LF3310
Horizontal / Vertical Digital Image Filter
5678
1234567
1234
Even-Tap, Even-Symmetric
Coefficient Set
FIGURE 9. I/D REGISTER DATA PATHS
REVERSAL
DATA
ALU
COEF 7
COEF 6
ALU
1-16
1-16
AB
1-16
1-16
AB
EVEN-TAP MODE ODD-TAP MODE ODD-TAP INTERLEAVE MODE
Odd-Tap, Even-Symmetric
Coefficient Set
REVERSAL
1-16
1-16
AB
ALU
1-16
1-16
AB
ALU
DATA
Delay Stage N–1
Delay Stage N
COEF 7
COEF 6
Even-Tap, Odd-Symmetric
Coefficient Set
REVERSAL
ALU
DATA
COEF 7
COEF 6
2
1-16
1-16
2
1-16
AB
ALU
1-16
AB
the I/D Register length.
The I/D Registers also facilitate using
decimation to increase the number of
filter taps. Decimation by N is
accomplished by reading the horizontal filter’s output once every N clock
cycles. The device supports decimation up to 16:1. With no decimation,
the maximum number of filter taps is
sixteen. When decimating by N, the
number of filter taps becomes 16N
because there are N–1 clock cycles
when the horizontal filter’s output is
not being read. The extra clock cycles
are used to calculate more filter taps.
When decimating, the I/D Registers
should be set to a length equal to the
decimation factor. For example,
when performing a 4:1 decimation,
the I/D Registers should be set to a
length of four. When not decimating
or when only one data set
(non-interleaved data) is fed into the
device, the I/D Registers should be
set to a length of one.
HSHEN enables or disables the
loading of data into the forward and
reverse I/D Registers when the device
is in Dimensionally Separate Mode
(see the HSHEN section for a full
discussion). When in Orthogonal
Mode, HSHEN also enables or
disables the loading of data into the
input register (DIN11-0) and the line
buffers.
It is important to note that in
Orthogonal Mode, either HSHEN or
VSHEN can disable the loading of
data into the input register (DIN11-0),
7
I/D Registers, and line buffers. Both
must be active to enable data loading
in Orthogonal Mode.
I/D Register Data Path Control
The multiplexer in the middle of the
I/D Register data path controls how
data is fed to the reverse data path.
The forward data path contains
the I/D Registers in which data
flows from left to right in the
block diagram in Figure 1. The
reverse data path contains the I/D
Registers in which data flows from
right to left. When the filter is
configured for an even number of
taps, data from the last I/D Register in the forward data path is fed
into the first I/D Register in the
reverse data path (see Figure 9).
Video Imaging Products
11/08/2001-LDS.3310-H
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