LOGIC LF2250QC25, LF2250QC20 Datasheet
DEVICES INCORPORATED
LF2250
12 x 10-bit Matrix Multiplier
LF2250
DEVICES INCORPORATED
FEATURES DESCRIPTION
❑❑
❑ 50 MHz Data and Computation
❑❑
Rate
❑❑
❑ Nine Multiplier Array with 12-bit
❑❑
Data and 10-bit Coefficient Inputs
❑❑
❑ Separate 16-bit Cascade Input and
❑❑
Output Ports
❑❑
❑ On-board Coefficient Storage
❑❑
❑❑
❑ Four User-Selectable Filtering and
❑❑
Transformation Functions:
• 3 x 3 Matrix Multiplier
• Cascadable 9-Tap FIR Filter
• Cascadable 3 x 3 Convolver
• Cascadable 4 x 2 Convolver
❑❑
❑ Replaces TRW/Raytheon/
❑❑
Fairchild TMC2250
❑❑
❑ 120-pin PQFP
❑❑
The LF2250 is a high-speed matrix
multiplier consisting of an array of
nine 12 x 10-bit multipliers. Internal
summing adders are also included to
provide the configurations needed to
implement matrix multiplications,
cascadable FIR filters, and pixel
convolvers.
The 3 x 3 matrix multiplier (triple dot
product) configuration of the LF2250
allows users to easily perform threedimensional perspective translations or
video format conversions at real-time
video rates. By using the LF2250 in
this configuration, conversions can be
made from the RGB (color component)
format to the YIQ (quadrature encoded
chrominance) or YUV (color difference) formats and vice versa (YIQ or
YUV to RGB).
In addition to color space conversions,
the LF2250 offers a range of selectable
configurations designed for filtering
applications. When configured as a
9-tap FIR filter, the LF2250 automatically
12 x 10-bit Matrix Multiplier
selects the necessary internal bus
structure and inserts the appropriate
data path delay elements. In addition,
a 16-bit cascade input port allows for
the creation of larger filters without a
reduction in throughput.
Real-time video image filtering using
the convolver modes of the LF2250 can
provide edge detection, texture
enhancement, and detail smoothing.
Both pixel convolver configurations,
3 x 3 and 4 x 2, deliver high-speed data
manipulation in a single chip solution.
By using the 16-bit cascade input port
to cascade two devices, cubic convolutions (4 x 4-pixel) can be easily accommodated with no decrease in throughput rates.
All inputs and outputs, as well as all
control lines, are registered on the
rising edge of clock. The LF2250
operates at clock rates up to 50 MHz
over the full commercial temperature
and supply voltage ranges.
LF2250 BLOCK DIAGRAM
CLK
1-0
MODE
CWE
1-0
A
DATA
INPUTS
COEFFICIENT
INPUTS
{
{
B
C
KA
KB
KC
11-0
11-0
11-0
9-0
9-0
9-0
2
2
12
12
12
12
10
10
10
9-MULTIPLIER
ARRAY
4
4
4
12
DATA
{
OUTPUTS
X
11-0
CASIN
Y
11-8
CASIN
Y
7-4
Y
3-0
CASOUT
Z
11-0
CASOUT
CASCADE
{
PORTS
15-4
XC
3-0
YC
Y
3-0
YC
15-4
ZC
PIN
{
NAME
11-0
11-8
7-4
3-0
11-0
Video Imaging Products
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08/16/2000–LDS.2250-L
DEVICES INCORPORATED
LF2250
12 x 10-bit Matrix Multiplier
TABLE 1. MODE SELECTION
MODE1-0 OPERATING MODE
00 3 x 3 Matrix Multiplier
01 9-Tap FIR Filter
10 3 x 3 Convolver
11 4 x 2 Convolver
OPERATING MODES
The LF2250 can realize four different
user-selectable digital filtering architectures as determined by the state of the
mode (MODE1-0) inputs. Upon
selection of the desired function, the
LF2250 automatically chooses the
appropriate internal data paths and
input/output bus structure. Table 1
details the modes of operation.
DATA FORMATTING
The coefficient input ports (KA, KB,
KC) are 10-bit fractional two’s complement format regardless of the operating
mode. The data input ports (A, B, C)
are 12-bit integer two’s complement
format regardless of the operating
mode.
In the matrix multiplier mode (Mode
00), the data output ports (X, Y, Z) are
12-bit integer two’s complement
format. In the FIR filter and convolver
modes (Modes 01, 10, 11), the X, Y, and
Z ports are configured as the cascade-in
(CASIN15-0) and cascade-out
(CASOUT15-0) ports. These ports
assume 16-bit (12-bit integer, 4-bit
fractional) two’s complement data on
both the inputs and outputs. Table 2
shows the data port formatting for
each of the four operating modes.
BIT WEIGHTING
The internal sum of products of the
LF2250 can grow to 23 bits. However,
in order to keep the output format of
the matrix multiply mode (Mode 00)
identical to the input format, the X, Y,
and Z outputs are truncated to 12-bit
integer words. In the filter modes
(Modes 01, 10, 11), the cascade output
is always half-LSB rounded to 16 bits
(12 integer bits and 4 fractional bits).
The user may half-LSB round the
output to any size less than 16 bits by
simply forcing a “1” into the bit
position of the cascade input immediately below the desired LSB. For
example, if half-LSB rounding to 12
bits is desired, then a “1” must be
forced into the CASIN3 bit position
(CASOUT4 would then be the LSB).
In all four modes, the user may adjust
the bit weighting, by applying an
identical scaling correction factor to
both the input and output data
streams. If the coefficients are rescaled, then the relative weightings of
the cascade-in and cascade-out ports
will differ accordingly. Figure 1
illustrates the input and output bit
weightings for all four modes.
DATA OVERFLOW
Because the LF2250’s matched input
and output data formats accommodate
unity gain (0 dB), input conditions that
could lead to numeric overflow may
exist. To ensure that no overflow
conditions occur, the user must be
aware of the maximum input data and
coefficient word sizes allowable for
each specific algorithm being performed.
SIGNAL DEFINITIONS
Power
VCC and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers. All timing specifications are referenced to the rising
edge of CLK.
Inputs
A11-0, B11-0, C11-0 — Data Inputs
A, B, and C are the 12-bit registered
data input ports. Data presented to
these ports is latched into the multiplier input registers for the current
operating mode (Table 1). In the filter
modes (Modes 01, 10, 11), the rising
edge of CLK internally right-shifts
new data to the next filter tap.
KA9-0, KB9-0, KC9-0 — Coefficient Inputs
KA, KB, and KC are the 10-bit registered coefficient input ports. Data
presented to these ports is latched
into the corresponding internal
coefficient register set defined by
CWE1-0 (Table 4) on the next rising
edge of CLK. Table 3 shows which
coefficient registers are available for
each coefficient input port.
TABLE 2. DATA PORT FORMATTING
PIN NAMES
MODE1-0 A11-0 B11-0 C11-0 KA9-0 KB9-0 KC9-0 XC11-0 YC11-8 Y7-4 YC3-0 ZC11-0
00 A11-0 B11-0 C11-0 KA9-0 KB9-0 KC9-0 X11-0 Y11-8 Y7-4 Y3-0 Z11-0
01 A11-0 A11-0 NC KA9-0 KB9-0 KC9-0 CASIN15-4 CASIN3-0 NC CASOUT3-0 CASOUT15-4
10 A11-0 B11-0 C11-0 KA9-0 KB9-0 KC9-0 CASIN15-4 CASIN3-0 NC CASOUT3-0 CASOUT15-4
11 A11-0 B11-0 NC KA9-0 KB9-0 KC9-0 CASIN15-4 CASIN3-0 NC CASOUT3-0 CASOUT15-4
Video Imaging Products
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08/16/2000–LDS.2250-L
DEVICES INCORPORATED
LF2250
12 x 10-bit Matrix Multiplier
FIGURE 1A.INPUT FORMATS
Data Input (All Modes)
11 10 9 6 5 487 3210
1121029
–2
(Sign)
282
Coefficient Input (All Modes)
987 43265 10
02–12–2
–2
(Sign)
2–32
Cascade Input (Modes 01, 10, 11)
15 14 13 10 9 81211 76543210
1121029
–2
(Sign)
282
7
26252
Internal Sum (All Modes)
20 19 18 3 2 117 0
1121029
–2
(Sign)
FIGURE 1B.OUTPUT FORMATS
Result (Mode 00)
11 10 9 6 5 487 3210
1121029
–2
(Sign)
282
7
26252
–4
4
8
2
7
26252
4
2322212
2–52–62
–7
2–82
232221202–12–22–32
2–62–72
–8
4
2322212
CASOUT15-0 — Cascade Output
In the filter modes (Modes 01, 10, 11),
the 12-bit Z port and four bits of the Y
port are internally reconfigured as the
0
16-bit registered cascade output port.
NOTE: The X, Y, and Z ports are
automatically reconfigured by the LF2250
as the cascade-in and cascade-out ports as
required for each operating mode.
–9
Because both the X and Z ports are used
for the cascade ports, all X port pins and
all Z port pins are labelled as XC and
ZC, respectively. All Y port pins that are
used for the cascade ports are labelled as
YC. Those Y port pins which are not
–4
used for the cascade ports are labelled as
Y.
Controls
MODE1-0 — Mode Select
–9
2
The registered mode select inputs
determine the operating mode of the
LF2250 (Table 1) for data being input
on the next clock cycle. When switching between modes, the internal
pipeline latencies of the device must
be observed. After switching operating modes, the user must allow
enough clock cycles to pass to flush
0
the internal registers before valid data
will appear on the outputs.
Cascade Out (Modes 01, 10, 11)
15 14 13 10 9 81211 76543210
1121029
–2
(Sign)
282
7
26252
CASIN15-0 — Cascade Input
In the filter modes (Modes 01, 10, 11),
the 12-bit X port and four bits of the Y
port are internally reconfigured as the
16-bit registered cascade input port.
Data presented to this port will be
added to the internal sum of products.
4
232221202–12–22–32
–4
Outputs
X11-0, Y11-0, Z11-0 — Data Outputs
X, Y, and Z are the 12-bit registered
output ports for the matrix multiply
mode (Mode 00). These ports are
automatically reconfigured for the
filter modes (Modes 01, 10, 11) as the
cascade-in and cascade-out ports.
3
CWE1-0 — Coefficient Write Enable
The registered coefficient write enable
inputs determine which internal
coefficient register set to update
(Table 4) on the next clock cycle.
TABLE 3. COEFFICIENT INPUTS
INPUT PORT REG. AVAILABLE
KA KA1, KA2, KA3
KB KB1, KB2, KB3
KC KC1, KC2, KC3
Video Imaging Products
08/16/2000–LDS.2250-L
DEVICES INCORPORATED
LF2250
12 x 10-bit Matrix Multiplier
TABLE 4. COEFF. REG. UPDATE
CWE1-0 COEFFICIENT SET
00 Hold All Registers
01 KA1, KB1, KC1
10 KA2, KB2, KC2
11 KA3, KB3, KC3
DETAILS OF OPERATION
3 x 3 Matrix Multiplier — Mode 00
In this mode, all three input ports (A,
B, C) and all three output ports (X, Y,
Z) are utilized to implement a 3 x 3
matrix multiplication (triple dot
product). Each rounded 12-bit output
is the sum of all three input words
multiplied by the appropriate coefficients (Table 5). The pipeline latency
for this mode is five clock cycles.
Therefore, the sum of products will
be output five clock cycles after the
input data has been latched. New
output data is subsequently available
every clock cycle thereafter.
(comprising of the summation of the
multiplications of the last nine data
inputs with their related coefficients)
becomes available (Table 5). The
CASIN term is also added to each
new output. The internal bus structure and pipeline delays allow new
input data to be added every cycle
while maintaining the structure of the
filtering operation. This addition of
new data every cycle produces the
effect of the convolution window
moving to the next pixel column.
4 x 2-Pixel Convolver — Mode 11
Using the A and B ports, input data is
loaded and multiplied by the onboard coefficients. These products
are then summed with the CASIN
data and rounded to create the 16-bit
output. The cascade ports allow
multiple devices to be used together
for use with larger kernels. As with
Mode 10, each cycle results in a 16-bit
output created from the products and
summations performed.
TABLE 5. LATENCY EQUATIONS
3 x 3 Matrix Multiplier — Mode 00
X(n+4) = A(n)KA1(n) + B(n)KB1(n) + C(n)KC1(n)
Y(n+4) = A(n)KA2(n) + B(n)KB2(n) + C(n)KC2(n)
Z(n+4) = A(n)KA3(n) + B(n)KB3(n) + C(n)KC3(n)
9-Tap FIR Filter — Mode 01
CASOUT(n+12) = A(n+8)KA3(n+8) + A(n+7)KA2(n+7) + A(n+6)KA1(n+6)
9-Tap FIR Filter — Mode 01
This mode utilizes the 12-bit A and B
data input ports as well as the 16-bit
CASIN port. The input data should
be presented to the A and B ports
simultaneously. The resulting 9sample response, which is half-LSB
rounded to 16 bits, begins after five
clock cycles and ends after 13 clock
cycles (Table 5). The pipeline latency
from the input of an impulse response
to the center of the output response is
nine clock cycles. The latency from
the CASIN port to the CASOUT port
is four clock cycles. New output data
is available every clock cycle.
3 x 3-Pixel Convolver — Mode 10
When configured in this mode, line
delayed data is loaded through the A,
B, and C input ports. During each
cycle, a new rounded 16-bit output
+ B(n+5)KB3(n+8) + B(n+4)KB2(n+7) + B(n+3)KB1(n+6)
+ B(n+2)KC3(n+8) + B(n+1)KC2(n+7) + B(n)KC1(n+6)
+ CASIN(n+9)
3 x 3-Pixel Convolver — Mode 10
CASOUT(n+6) = A(n+2)KA3(n+2) + A(n+1)KA2(n+1) + A(n)KA1(n)
+ B(n+2)KB3(n+2) + B(n+1)KB2(n+1) + B(n)KB1(n)
+ C(n+2)KC3(n+2) + C(n+1)KC2(n+1) + C(n)KC1(n)
+ CASIN(n+3)
4 x 2-Pixel Convolver — Mode 11
CASOUT(n+7) = A(n+3)KA3(n+3) + A(n+2)KA2(n+2) + A(n+1)KA1(n+1)
+ A(n)KC3(n+3) + B(n+3)KB3(n+3) + B(n+2)KB2(n+2)
+ B(n+1)KB1(n+1) + B(n)KC1(n+1)
+ CASIN(n+4)
Video Imaging Products
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08/16/2000–LDS.2250-L
DEVICES INCORPORATED
FIGURE 2. 3 X 3 MATRIX MULTIPLIER — MODE 00
12
A
KA1 KA2 KA3
10
KA
21 21 21
12
B
LF2250
12 x 10-bit Matrix Multiplier
KB
KC
KB3KB2KB1
10
21 21 21
12
C
KC1 KC2 KC3
10
21 21 21
12 (MSB) 12 (MSB) 12 (MSB)
XYZ
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