LOGIC LF2247QC25, LF2247QC15, LF2247JC15 Datasheet
DEVICES INCORPORATED
Video Imaging Products
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LF2247
Image Filter with Coefficient RAM
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08/16/2000–LDS.2247-H
❑❑
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❑ 66 MHz Data Input and Compu-
tation Rate
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❑ Four 11 x 10-bit Multipliers with
Individual Data and Coefficient
Inputs and a 25-bit Accumulator
❑❑
❑❑
❑ Four 32 x 11-bit Serially Loadable
Coefficient Registers
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❑ Fractional or Integer Two’s
Complement Operands
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❑ Package Styles Available:
• 84-pin PLCC, J-Lead
• 100-pin PQFP
FEATURES DESCRIPTION
LF2247
Image Filter with Coefficient RAM
DEVICES INCORPORATED
The LF2247 consists of an array of four
11 x 10-bit registered multipliers
followed by a summer and a 25-bit
accumulator. The LF2247 provides a
coefficient register file containing four
32 x 11-bit registers which are capable
of storing 32 different sets of filter
coefficients for the multiplier array.
All multiplier data inputs are user
accessible and can be updated every
clock cycle with either fractional or
integer two’s complement data. The
pipelined architecture has fully
registered input and output ports and
an asynchronous three-state output
enable control to simplify the design
of complex systems. The pipeline
latency for all inputs is five clock
cycles.
A 25-bit accumulator path allows
cumulative word growth which may
be internally rounded to 16 bits.
Output data is updated every clock
cycle and may be held under user
control. The data inputs/outputs and
control inputs are registered on the
rising edge of CLK. The Serial Data In
signal, SDIN, is registered on the
LF2247 BLOCK DIAGRAM
D1
9-0
10 11
ENB
1
D2
9-0
10 11
ENB
2
22
D3
9-0
10 11
ENB
3
D4
9-0
10 11
ENB
4
22
MS LS
S
15-0
ACC
FSEL
OEN
CLK TO ALL REGISTERS
(EXCEPT COEFFICIENT REGISTERS)
25
OCEN
Coefficient
Register 1
(32 x 11-bit)
Coefficient
Register 2
(32 x 11-bit)
Coefficient
Register 3
(32 x 11-bit)
Coefficient
Register 4
(32 x 11-bit)
A
4-0
SEN
SDIN
SCLK SCLK
5
ENBA
16
COEFFICIENT REGISTER FILE
SEN
SCLK
SEN
SCLK
SEN
DEVICES INCORPORATED
LF2247
Image Filter with Coefficient RAM
-2
Video Imaging Products
08/16/2000–LDS.2247-H
rising edge of SCLK. The LF2247
operates at a clock rate of 66 MHz
over the full temperature and supply
voltage ranges.
The LF2247 is applicable for performing pixel interpolation in image
manipulation and filtering applications. The LF2247 can perform a
bilinear interpolation of an image (4pixel kernels) at real-time video rates
when used with an image resampling
sequencer. Larger kernels or more
complex functions can be realized by
utilizing multiple devices.
Unrestricted access to all data ports
and an addressable coefficient register
file provides the LF2247 with considerable flexibility in applications such
as digital filters, adaptive FIR filters,
mixers, and other similar systems
requiring high-speed processing.
SIGNAL DEFINITIONS
Power
VCC and GND
+5 V power supply. All pins must be
connected.
Clocks
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers except for the
coefficient registers.
SCLK — Serial Clock
The rising edge of SCLK shifts data
into and through the coefficient
register file when it is enabled for
serial data shifting.
Inputs
D19-0 – D49-0 — Data Input
D1–D4 are the 10-bit registered data
input ports. Data is latched on the
rising edge of CLK.
A4-0 — Row Address
A4-0 determines which row of data in
the coefficient register file is used to
feed data to the multiplier array. A4-0
is latched on the rising edge of CLK.
When a new row address is loaded
into the row address register, data
from the register file will be latched
into the multiplier input registers on
the next rising edge of CLK.
SDIN — Serial Data Input
SDIN is used to serially load data into
the coefficient registers. Data present
on SDIN is shifted into the coefficient
register file on the rising edge of SCLK
when SEN is LOW. The 11-bit coefficients are loaded into the coefficient
register file in 16-bit words as shown
in Figure 2. The five most significant
bits of the first 16-bit word determine
which row the data is written to in the
coefficient registers. Note that the five
most significant bits of the remaining
three 16-bit words are ignored. After
all four 16-bit words are shifted into
the register file, the lower eleven bits
of each word (the coefficient data) are
stored into the coefficient registers.
Outputs
S15-0 — Data Output
S15-0 is the 16-bit registered data
output port.
Controls
ENB1–ENB4 — Data Input Enables
The ENBN (N = 1, 2, 3, or 4) inputs
allow the DN registers to be updated
on each clock cycle. When ENBN is
LOW, data on DN9-0 is latched into
FIGURE 1B.OUTPUT FORMATS
15 14 13 10 9 81211 76543210
–2
6
(Sign)
252
4
21202
–1
232
2
2–22–32–42–52–62–72–82
–9
15 14 13 10 9 81211 76543210
–2
15
(Sign)
2142
13
210292
8
2122
11
272625242322212
0
Fractional Two's Complement (FSEL = 0)
Integer Two's Complement (FSEL = 1)
FIGURE 1A.INPUT FORMATS
987 210
–2
0
(Sign)
2–12
–2
2–72–82
–9
10 9 8 2 1 0
–2
1
(Sign)
202
–1
2–72–82
–9
987 210
–2
9
(Sign)
282
7
22212
0
10 9 8 2 1 0
–2
10
(Sign)
292
8
22212
0
Fractional Two's Complement (FSEL = 0)
Integer Two's Complement (FSEL = 1)
Data Coefficient
DEVICES INCORPORATED
Video Imaging Products
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LF2247
Image Filter with Coefficient RAM
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08/16/2000–LDS.2247-H
the DN register on the rising edge of
CLK. When ENBN is HIGH, data on
DN9-0 is not latched into the DN
register and the register contents will
not be changed.
ENBA — Row Address Input Enable
The ENBA input allows the row
address register to be updated on each
clock cycle. When ENBA is LOW,
data on A4-0 is latched into the row
address register on the rising edge of
CLK. When ENBA is HIGH, data on
A4-0 is not latched into the row
address register and the register
contents will not be changed.
OEN — Output Enable
When OEN is LOW, S15-0 is enabled
for output. When OEN is HIGH, S15-0
is placed in a high-impedance state.
OCEN — Clock Enable
When OCEN is LOW, data in the premux register (accumulator output) is
loaded into the output register on the
next rising edge of CLK. When OCEN
is HIGH, data in the pre-mux register
is held preventing the output
register’s contents from changing (if
FSEL does not change). Accumulation
continues internally as long as ACC is
HIGH, despite the state of OCEN.
FSEL — Format Select
When FSEL is LOW, the data input
during the current clock cycle is
assumed to be in fractional two’s
complement format, and the upper 16
bits of the accumulator are presented
at the output. Rounding of the
accumulator result to 16 bits is per-
formed if the accumulator control
input ACC is LOW. When FSEL is
HIGH, the data input is assumed to be
in integer two’s complement format,
and the lower 16 bits of the accumulator are presented at the output. No
rounding is performed when FSEL is
HIGH.
ACC — Accumulator Control
The ACC input determines whether
internal accumulation is performed on
the data input during the current
clock cycle. If ACC is LOW, no
accumulation is performed, the prior
accumulated sum is cleared, and the
current sum of products is output. If
FSEL is also LOW, one-half LSB
rounding to 16 bits is performed on
the result. When ACC is HIGH, the
emerging product is added to the sum
of the previous products, without
additional rounding.
SEN — Serial Input Enable
The SEN input enables the shifting of
serial data through the registers in the
coefficient register file. When SEN is
LOW, serial data on SDIN is shifted
into the coefficient register file on the
rising edge of SCLK. SEN must
remain LOW until all four coefficients
have been clocked in. SEN does not
need to be pulsed between consecutive data sets. It can remain LOW
while the entire register file is loaded
by a constant bit stream. When SEN is
HIGH, data can not be shifted into the
register file and the register file’s
contents will not be changed. When
enabling the coefficient register file for
serial data input, the LF2247 requires
a HIGH to LOW transition of SEN in
order to function properly. Therefore,
SEN needs to be set HIGH immediately after power up to ensure proper
operation of the serial input circuitry.
FIGURE 2. SERIAL DATA FORMAT
231564897111210 13 15 1614 18 1917 21 2220 24 2523 27 2826 29 31 3230
34 3533 37 3836 40 4139 43 4442 45 47 4846 50 5149 53 5452 56 5755 59 6058 61 63 6462
0000111111011001XXXX0X0100001001
XXXX0X1101000001XXXX1X1111010001
FIRST 16-BIT WORD SECOND 16-BIT WORD
THIRD 16-BIT WORD FOURTH 16-BIT WORD
ROW
ADDRESS
DATA FOR
COEFFICIENT REGISTER 4
DON'T
CARES
DATA FOR
COEFFICIENT REGISTER 3
DON'T
CARES
DATA FOR
COEFFICIENT REGISTER 2
DON'T
CARES
DATA FOR
COEFFICIENT REGISTER 1
SHOWN IS SERIAL DATA STREAM TO LOAD ROW ADDRESS 2 WITH:
COEFFICIENT REGISTER 1 = 7E4
COEFFICIENT REGISTER 2 = 1A4
COEFFICIENT REGISTER 3 = 08C
COEFFICIENT REGISTER 4 = 7EC
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