LOGIC LF2246QC15, LF2246QC25 Datasheet
DEVICES INCORPORATED
LF2246
11 x 10-bit Image Filter
LF2246
DEVICES INCORPORATED
FEATURES DESCRIPTION
❑❑
❑ 66 MHz Data and Coefficient Input
❑❑
and Computation Rate
❑❑
❑ Four 11 x 10-bit Multipliers with
❑❑
Individual Data and Coefficient
Inputs and a 25-bit Accumulator
❑❑
❑ User-Selectable Fractional or
❑❑
Integer Two’s Complement Data
Formats
❑❑
❑ Fully Registered, Pipelined Archi-
❑❑
tecture
❑❑
❑ Input and Output Data Registers,
❑❑
with User-Configurable Enables
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❑ Three-State Outputs
❑❑
❑❑
❑ Fully TTL Compatible
❑❑
❑❑
❑ Ideally Suited for Image Processing
❑❑
and Filtering Applications
❑❑
❑ Replaces TRW/Raytheon/Fairchild
❑❑
TMC2246
❑❑
❑ 120-pin PQFPP
❑❑
The LF2246 consists of an array of
four 11 x 10-bit registered multipliers
followed by a summer and a 25-bit
accumulator. All multiplier inputs
are user accessible and can be updated every clock cycle with either
fractional or integer two’s complement data. The pipelined architecture
has fully registered input and output
ports and an asynchronous three-state
output enable control to simplify the
design of complex systems. The
pipeline latency for all inputs is five
clock cycles.
Storage for mixing and filtering
coefficients can be accomplished by
holding the data or coefficient inputs
over multiple clock cycles. A 25-bit
accumulator path allows cumulative
word growth which may be internally
rounded to 16 bits. Output data is
updated every clock cycle and may be
held under user control. All inputs,
11 x 10-bit Image Filter
outputs, and controls are registered
on the rising edge of clock, except for
OEN. The LF2246 operates at a clock
rate of 66 MHz over the full temperature and supply voltage ranges.
The LF2246 is applicable for performing pixel interpolation in image
manipulation and filtering applications. The LF2246 can perform a
bilinear interpolation of an image (4pixel kernels) at real-time video rates
when used with an image resampling
sequencer. Larger kernels or more
complex functions can be realized by
utilizing multiple devices.
Unrestricted access to all data and
coefficient input ports provides the
LF2246 with considerable flexibility in
applications such as digital filters,
adaptive FIR filters, mixers, and other
similar systems requiring high-speed
processing.
LF2246 BLOCK DIAGRAM
D1
ENSEL
10
ACC
FSEL
OEN
9–0
C1
10–0
ENB1 D2
11 10 11 10 11 10 11
22
9–0
C2
10–0
ENB2
MS LS
D3
9–0
C3
10–0
ENB3 D4
25
OCEN
22
9–0C410–0
ENB4
CLK
TO ALL REGISTERS
2-11
S
15–0
Video Imaging Products
08/16/2000–LDS.2246-K
DEVICES INCORPORATED
LF2246
11 x 10-bit Image Filter
FIGURE 1A.INPUT FORMATS
Data
Fractional Two’s Complement (FSEL = 0)
987 210
–2
(Sign)
0
2–12
–2
2–72–82
–9
Integer Two’s Complement (FSEL = 1)
987 210
–2
(Sign)
9
282
7
22212
0
FIGURE 1B.OUTPUT FORMATS
Fractional Two’s Complement (FSEL = 0)
15 14 13 10 9 81211 76543210
6
–2
(Sign)
15 14 13 10 9 81211 76543210
15
–2
(Sign)
SIGNAL DEFINITIONS
Power
VCC and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all enabled registers. All timing specifications are referenced to the rising edge of
CLK.
Inputs
D19–0–D49–0 — Data Input
D1–D4 are 10-bit data input registers.
The LSB is DN0 (Figure 1a).
C110–0–C410–0 — Coefficient Input
C1–C4 are 11-bit coefficient input registers. The LSB is CN0 (Figure 1a).
Outputs
S15–0 — Data Output
The current 16-bit result is available on
the S15–0 outputs (Figure 1b).
252
4
232
2
21202
Integer Two’s Complement (FSEL = 1)
2142
13
2122
11
210292
Coefficient
10 9 8 2 1 0
–2
(Sign)
1
202
–1
2–72–82
–9
10 9 8 2 1 0
10
–2
(Sign)
–1
2–22–32–42–52–62–72–82
8
272625242322212
292
8
22212
0
–9
0
Controls
ENB1–ENB4 — Input Enable
The ENBN (N = 1, 2, 3, or 4) input allows
either or both the DN and CN registers to
be updated on each clock cycle. When
ENBN is LOW, registers DN and CN are
both strobed by the next rising edge of
CLK. When ENBN is HIGH and ENSEL
is LOW, register DN is strobed while
register CN is held. If both ENBN and
ENSEL are HIGH, register DN is held,
and register CN is strobed (Table 1).
ENSEL — Enable Select
The ENSEL input in conjunction with
the individual input enables ENB1–
ENB4 determines whether the data or
the coefficient input registers will be
held on the next rising edge of CLK
(Table 1).
OEN — Output Enable
When the OEN signal is LOW, the current data in the output register is available on the S15–0 pins. When OEN is
HIGH, the outputs are in a high-impedance state.
TABLE 1. INPUT REGISTER CONTROL
INPUT REGISTER
ENB1-4 ENSEL HELD
1 1 Data ‘N’
1 0 Coefficient ‘N’
0 X None
X = “Don’t Care”
‘N’ = 1, 2, 3, or 4
OCEN — Clock Enable
When OCEN is LOW, data in the premux register (accumulator output) is
loaded into the output register on the
next rising edge of CLK. When OCEN
is HIGH, data in the pre-mux register is
held preventing the output register’s
contents from changing (if FSEL does
not change). Accumulation continues
internally as long as ACC is HIGH,
despite the state of OCEN.
FSEL — Format Select
When the FSEL input is LOW, the data
input during the current clock cycle is
assumed to be in fractional two’s
complement format, and the upper 16
bits of the accumulator are presented at
the output. Rounding of the accumulator result to 16 bits is performed if the
accumulator control input ACC is
LOW. When FSEL is HIGH, the data
input is assumed to be in integer two’s
complement format, and the lower 16
bits of the accumulator are presented at
the output. No rounding is performed
when FSEL is HIGH.
ACC — Accumulator Control
The ACC input determines whether internal accumulation is performed on
the data input during the current clock
cycle. If ACC is LOW, no accumulation
is performed, the prior accumulated
sum is cleared, and the current sum of
products is output. If FSEL is also LOW,
one-half LSB rounding to 16 bits is performed on the result. This allows summations without propagating roundoff
errors. When ACC is HIGH, the emerging product is added to the sum of the
previous products, without additional
rounding.
2-12
Video Imaging Products
08/16/2000–LDS.2246-K
DEVICES INCORPORATED
LF2246
11 x 10-bit Image Filter
MAXIMUM RATINGS
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground............................................................................ –0.5 V to +7.0V
Input signal with respect to ground ............................................................................... –0.5 V to VCC + 0.5 V
Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ................................................................................................................ ............... > 400 mA
OPERATING CONDITIONS
Active Operation, Commercial 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V
Active Operation, Military –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V
ELECTRICAL CHARACTERISTICS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
To meet specified electrical and switching characteristics
Mode Temperature Range (Ambient) Supply Voltage
Over Operating Conditions (Note 4)
Symbol Parameter Test Condition Min Typ Max Unit
VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 V
VOL Output Low Voltage VCC = Min., IOL = 4.0 mA 0.4 V
VIH Input High Voltage 2.0 VCC V
V IL Input Low Voltage (Note 3) 0.0 0.8 V
IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±10 µA
IOZ Output Leakage Current (Note 12) ±40 µA
ICC1 VCC Current, Dynamic (Notes 5, 6) 100 mA
ICC2 VCC Current, Quiescent (Note 7) 6mA
CIN Input Capacitance TA = 25°C, f = 1 MHz 10 pF
COUT Output Capacitance TA = 25°C, f = 1 MHz 10 pF
2-13
Video Imaging Products
08/16/2000–LDS.2246-K
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