LOGIC LF2242JC33, LF2242JC25, LF2242QC33, LF2242QC25 Datasheet

DEVICES INCORPORATED

12/16-bit Half-Band Interpolating/

DEVICES INCORPORATED

FEATURES DESCRIPTION

LF2242

12/16-bit Half-Band Interpolating/

LF2242

Decimating Digital Filter

Decimating Digital Filter

❑❑

❑ 40 MHz Clock Rate

❑❑
❑❑

❑ Passband (0 to 0.22f

❑❑

)

S

Ripple: ±0.02 dB

❑❑

❑ Stopband (0.28f

❑❑

to 0.5fS)

S

Rejection: 59.4 dB

❑❑

❑ User-Selectable 2:1 Decimation or

❑❑

1:2 Interpolation

❑❑

❑ 12-bit Two’s Complement Input

❑❑

and 16-bit Output with
User-Selectable Rounding, 8- to
16-Bits

❑❑

❑ User-Selectable Two’s Complement

❑❑

or Inverted Offset Binary Output
Formats

❑❑

❑ Three-State Outputs

❑❑
❑❑

❑ Replaces TRW/ Raytheon/

❑❑

Fairchild TMC2242

❑❑

❑ Package Styles Available:

❑❑

• 44-pin PLCC, J-Lead

• 44-pin PQFP

The LF2242 is a linear-phase, half-
band (low pass) interpolating/
decimating digital filter that, unlike
intricate analog filters, requires no
tuning. The LF2242 can also signifi­cantly reduce the complexity of
traditional analog anti-aliasing pre­filters without compromising the
signal bandwidth or attenuation. This
can be achieved by using the LF2242
as a decimating post-filter with an
A/D converter and by sampling the
signal at twice the rate needed.
Likewise, by using the LF2242 as an
interpolating pre-filter with a D/A
converter, the corresponding analog
reconstruction post-filter circuitry can
be simplified.

The coefficients of the LF2242 are
fixed, and the only user programming
required is the selection of the mode
(interpolate, decimate, or pass­through) and rounding. The asyn­chronous three-state output enable
control simplifies interfacing to a bus.

Data can be input into the LF2242 at a
rate of up to 40 million samples per
second. Within the 40 MHz I/O limit,
the output sample rate can be one­half, equal to, or two times the input

sample rate. Once data is clocked in,
the 55-value output response begins
after 7 clock cycles and ends after 61
clock cycles. The pipeline latency
from the input of an impulse response
to its corresponding output peak is 34
clock cycles.

The output data may be in either
two’s complement format or inverted
offset binary format. To avoid
truncation errors, the output data is
always internally rounded before it is
latched into the output register.
Rounding is user-selectable, and the
output data can be rounded from 16
bit values down to 8 bit values.

DC gain of the LF2242 is 1.0015
(0.0126 dB) in pass-through and
decimate modes and 0.5007 (–3.004
dB) in interpolate mode. Passband
ripple does not exceed ±0.02 dB from
0 to 0.22fS with stopband attenuation
greater than 59.4 dB from 0.28fS to

0.5fS (Nyquist frequency). The
response of the filter is –6 dB at 0.25fS.
Full compliance with CCIR Recom­mendation 601 (–12 dB at 0.25fS) can
be achieved by cascading two devices
serially.

LF2242 BLOCK DIAGRAM

SI

11–0

CLK

INTERPOLATION

CIRCUIT

3

TO ALL REGISTERS

55-TAP

FIR

FILTER

RND

3

3

ROUND

CIRCUIT

2–0

161212

DECIMATION

CIRCUIT

3

OE

16

SO

15–0

TCO

AND LIMIT

SYNCINT DEC

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1

08/16/2000–LDS.2242-K

DEVICES INCORPORATED

LF2242

12/16-bit Half-Band Interpolating/

Decimating Digital Filter

FIGURE 1. FREQUENCY RESPONSE OF FILTER

0
–10
–20
–30
–40
–50

GAIN (dB)

–60
–70
–80

0 0.1

SIGNAL DEFINITIONS

Power

VCC and GND

+5 V power supply. All pins must be
connected.

ƒ

0.2

S

ƒ

S

FREQUENCY (NORMALIZED)

Inputs

SI11–0 — Data Input

12-bit two’s complement data input
port. Data is latched into the register on
the rising edge of CLK. The LSB is SI0
(Figure 2).

0.3

Controls

INT — Interpolation Control

When INT is LOW and DEC is HIGH
(Table 1), the device internally forces
every other incoming data sample to
zero. This effectively halves the input
data rate and the output amplitude.

DEC — Decimation Control

When DEC is LOW and INT is HIGH
(Table 1), the output register is strobed on
every other rising edge of CLK (driven at
half the clock rate), decimating the output
data stream.

ƒ

0.4

S

ƒ

0.5

S

ƒ

S

TABLE 1. MODE SELECTION

INT DEC MODE

0 0 Pass-through*
0 1 Interpolate
1 0 Decimate
1 1 Pass-through*

*Input and output registers run at full

clock rate

Clock

CLK — Master Clock

The rising edge of CLK strobes all regis­ters. All timing specifications are refer­enced to the rising edge of CLK.

SYNC — Synchronization Control

Incoming data is synchronized by hold­ing SYNC HIGH on CLKN, and then by
bringing SYNC LOW on CLKN+1 with
the first word of input data. SYNC is held
LOW until resynchronization is desired,
or it can be toggled at half the clock rate.
For interpolation (INT = LOW), input
data should be presented at the first ris­ing edge of CLK for which SYNC is LOW
and then at every alternate rising edge of
CLK thereafter. SYNC is inactive if DEC
and INT are equal (pass-through mode).

Outputs

SO15-0 Data Output

The current 16-bit result is available on
the SO15-0 outputs. The LF2242’s limiter
ensures that a valid full-scale (7FFF
positive or 8000 negative) output will be
generated in the event of an internal
overflow. The LSB is SO0 (Figure 2).

2

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08/16/2000–LDS.2242-K

DEVICES INCORPORATED

LF2242

12/16-bit Half-Band Interpolating/

Decimating Digital Filter

FIGURE 2. INPUT AND OUTPUT FORMATS

Two’s Complement Input Format

10 9 8 2 1 011 3

02–12–2

–2

(Sign)

–3

2

2–82–92

Two’s Complement Output Format (TCO = 1, Non-interpolate)

14 13 12 2 1 015 3

02–12–2

–2

(Sign)

–3

2

–122–132–14

2

Two’s Complement Output Format (TCO = 1, Interpolate)

14 13 12 2 1 015 3

1202–1

–2

(Sign)

–2

2

–112–122–13

2

Inverted Offset Binary Output Format (TCO = 0, Non-interpolate)

14 13 12 2 1 015 3

02–12–2

2

(Sign)

–3

2

–122–132–14

2

Inverted Offset Binary Output Format (TCO = 0, Interpolate)

14 13 12 2 1 015 3

1202–1

2

(Sign)

–2

2

–112–122–13

2

–10

–11

2

–15

2

–14

2

–15

2

–14

2

RND2-0 — Rounding Control

The rounding control inputs set the posi­tion of the effective LSB of the output data
by adding a rounding bit to the internal
bit position that is one below that speci­fied by RND2-0. All bits below the effec­tive LSB position are subsequently ze­roed (Table 2).

TCO — Two’s Complement Format
Control

The TCO input determines the format of
the output data. When TCO is HIGH, the
output data is presented in two’s comple­ment format. When TCO is LOW, the
data is in inverted offset binary format
(all output bits are inverted except the
MSB — the MSB is unchanged).

OE — Output Enable

When the OE signal is LOW, the current
data in the output register is available on
the SO15-0 pins. When OE is HIGH, the
outputs are in a high-impedance state.

TABLE 2. ROUNDING FORMAT

RND2-0 SO15 SO14 SO13 SO12 • • • SO8 SO7 SO6 SO5 SO4 SO3 SO2 SO1 SO0

000XXXX• • • XXXXXXXXR
001XXXX• • • XXXXXXXR0
010XXXX• • • XXXXXXR00
011XXXX• • • XXXXXR000
100XXXX• • • XXXXR0000
101XXXX

• • • XXXR00000

110XXXX• • • XXR000000
111XXXX• • • XR0000000

'R' indicates the half-LSB rounded bit (effective LSB position)

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08/16/2000–LDS.2242-K