The L4C383 is a flexible, high speed,
cascadable 16-bit Arithmetic and Logic
Unit. The L4C383 is capable of
performing up to 32 different
arithmetic or logic functions.
The L4C383 can be cascaded to perform
32-bit or greater operations. See
“Cascading the L4C383” on the next
page.
ARCHITECTURE
The L4C383 operates on two 16-bit
operands (A and B) and produces a 16-
L4C383 BLOCK DIAGRAM
B15-B
FFFF
0
H
ENA
A15-A
0
1616
A REGISTERB REGISTER
FFFF
H
ENB
FTAB
bit result (F). Five select lines control
the ALU and provide 19 arithmetic and
13 logical functions. Registers are
provided on both the ALU inputs and
the output, but these may be bypassed
under user control. An internal feedback path allows the registered ALU
output to be routed to one or both of
the ALU inputs, accommodating chain
operations and accumulation.
ALU OPERATIONS
The S4–S0 lines specify the operation to
be performed. The ALU functions and
their select codes are shown in Table 1.
ALU STATUS
The ALU provides Overflow and Zero
status bits. A Carry output is also
provided for cascading multiple
devices, however it is only defined for
the 19 arithmetic functions. The ALU
sets the Zero output when all 16 output
bits are zero. The N, C16 and OVF flags
for the arithmetic operations are
defined in Table 2.
N, C
OVF, Z
FTF
OE
CLK
5
S
4-0
OPERAND REGISTERS
The L4C383 has two 16-bit wide input
registers for operands A and B. These
16
4
ALU
16
C
0
registers are rising edge triggered by a
common clock. The A register is
enabled for input by setting the ENA
control LOW, and the B register is
RESULT REGISTER
ENF
enabled for input by setting the ENB
control LOW. When either the ENA
control or ENB control is HIGH, the
data in the corresponding input register
will not change.
16
This architecture allows the L4C383 to
accept arguments from a single 16-bit
16
data bus. For those applications that do
not require registered inputs, both the
TO ALL REGISTERS
F15-F
0
A and B operand registers can be
bypassed with the FTAB control line.
Arithmetic Logic Units
1
08/16/2000–LDS.383-E
DEVICES INCORPORATED
L4C383
16-bit Cascadable ALU (Extended Set)
TABLE 1.ALU FUNCTIONS
S4-S0FUNCTION
00000A + B + C0
00001A OR B
00010A + B + C0
00011A + B + C0
00100A + C0
00101A OR F
00110A – 1 + C0
00111A + C0
01000A + F + C0
01001A OR F
01010A + F + C0
01011A + F + C0
01100F + B + C0
01101A OR B
01110F + B + C0
01111F + B + C0
10000A XOR B
10001A AND B
10010A AND B
10011A XNOR B
10100A XOR F
10101A AND F
10110A AND F
10111ALL 1's + C0
11000B + C0
11001A AND B
11010B + C0
11011B – 1 + C0
11100F + C0
11101A OR B
11110F – 1 + C0
11111F + C0
When the FTAB control is asserted
(FTAB = HIGH), data is routed
around the A and B input registers;
however, they continue to function
normally via the ENA and ENB
controls. The contents of the input
registers will again be available to the
ALU if the FTAB control is released.
TABLE 2.ALU STATUS FLAGS
Bit Carry Generate = gi =AiBifor i = 0 ... 15
Bit Carry Propagate = pi =Ai + Bifor i = 0 ... 15
P0 =p0
Pi =pi (Pi–1)for i = 1 ... 15
and
G0 =g0
Gi =gi + pi (Gi–1)for i = 1 ... 15
Ci =Gi–1 + Pi–1 (C0)for i = 1 ... 15
then
C16=G15 + P15C0
OVF = C15 XOR C16
Zero = All Output Bits Equal Zero
N = Sign Bit of ALU Operation
OUTPUT REGISTER
The output of the ALU drives the input of
a 16-bit register. This rising-edgetriggered register is clocked by the same
clock as the input registers. When the
ENF control is LOW, data from the ALU
will be clocked into the output register.
By disabling the output register, intermediate results can be held while loading
new input operands. Three-state drivers
controlled by the OE input allow the
L4C383 to be configured in a single
bidirectional bus system.
The output register can be bypassed by
asserting the FTF control signal (FTF =
HIGH). When the FTF control is asserted,
output data is routed around the output
register, however, it continues to function
normally via the ENF control. The
contents of the output register will again
be available on the output pins if FTF is
released.
CASCADING THE L4C383
Cascading the L4C383 to 32 bits is
accomplished simply by connecting the
C16 output of the least significant slice to
the C0 input of the most sig-nificant slice.
The S4-S0, ENA, ENB, and ENF lines are
common to both devices. The Zero output
flags should be logically ANDed to
produce the Zero flag for the 32-bit result.
The OVF and C16 outputs of the most
significant slice are valid for the 32-bit
result.
Propagation delay calculations for this
configuration require two steps: First
determine the propagation delay from the
input of interest to the C16 output of the
lower slice. Add this number to the delay
from the C0 input of the upper slice to the
output of interest (of the C0 setup time, if
the F register is used). The sum gives the
overall input-to-output delay (or setup
time) for the 32-bit configuration. This
method gives a conservative result, since
the C16 output is very lightly loaded.
Formulas for calculation of all critical
delays for a 32-bit system are shown in
Figures 4A through 4D.
Cascading to greater than 32 bits can be
accomplished by simply connecting the
C16 output of each slice to the C0 input of
the next more significant slice.
Propagation delays are calculated as
for the 32-bit case, except that the C0
to C16 delays for all intermediate slices
must be added to the overall delay for
each path.
Arithmetic Logic Units
2
08/16/2000–LDS.383-E
DEVICES INCORPORATED
FIGURE 4A.FTAB = 0, FTF = 0
FromToCalculated Specification Limit
Clock➞ F=Same as 16-bit case
Clock➞ Other=(Clock ➞ C16) + (C0➞ Out)
C0➞ Other=(C0➞ C16) + (C0➞ Out)
S4-S0➞ Other=(S4-S0➞ C16) + (C0➞ Out)
A, BSetup time=Same as 16-bit case
C0Setup time=(C 0➞ C16) + (C0 Setup time)
S4-S0Setup time=(S4-S0➞ C16) + (C0 Setup time)
ENA, ENB, ENFSetup time=Same as 16-bit case
Minimum cycle time=(Clock ➞ C16) + (C0 Setup time)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground............................................................................ –0.5V to +7.0V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS
Active Operation, Commercial 0°C to +70°C4.75V ≤VCC≤ 5.25 V
Active Operation, Military –55°C to +125°C4.50 V ≤VCC≤ 5.50 V
ELECTRICAL CHARACTERISTICS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
To meet specified electrical and switching characteristics
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot. Input levels below ground or above VCC
will be clamped beginning at –0.6 V and
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mA.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOHmin and VOL max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of IOH and IOL respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 µF ceramic capacitor should be
installed between VCCand Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device VCC
and the tester common, and device
ground and tester common.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, VTH, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
FIGURE B. THRESHOLD LEVELS
4. Actual test conditions may vary from
those designated but operation is guaranteed as specified.
5. Supply current for a given application can be accurately approximated by:
2
NCV F
where
4
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCCor Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
b. Ground and VCCsupply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the external system must supply at least that
much time to meet the worst-case requirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
10
Arithmetic Logic Units
08/16/2000–LDS.383-E
DEVICES INCORPORATED
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A
B
C
D
E
F
G
H
J
K
L
Top View
Through Package
(i.e., Component Side Pinout)
1234567891011
A
8
A
9
A
11
A
13
A
15
V
CC
C
16
N
OVF
OE
F
15
A
7
A
6
F
14
F
13
A
5
A
4
F
12
F
11
A
3
A
2
F
10
F
9
A
1
A
0
F
8
F
7
B
15
B
14
F
6
F
5
B
13
B
12
F
4
F
3
B
11
B
10
F
2
F
1
B
9
B
8
B
5
B
3
B
1
ENA
FTAB
S
3
S
1
C
0
F
0
A
10
A
12
A
14
CLK
GND
GND
ZERO
ENF
FTF
B
7
B
6
B
4
B
2
B
0
ENB
S
4
S
2
S
0
L4C383
16-bit Cascadable ALU (Extended Set)
ORDERING INFORMATION
68-pin
A8A7A6A5A4A3A2A1A0B15B14B13B12B11B10B9B
46663 6212
10
A
9
11
A
10
12
A
11
13
A
12
14
A
13
15
A
14
16
A
15
17
CLK
18
CC
V
19
GND
20
16
C
21
GND
22
N
23
ZERO
24
OVF
25
ENF
26
FTF
2732 33 34 35 36 37 386139 40941 42 43
28 29 30 31
OE
Plastic J-Lead Chip Carrier
Speed
(J2)
0°C to +70°C — COMMERCIAL SCREENING
26 ns
20 ns
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
L4C383JC26
L4C383JC20
5867
15F14F13F12F11F10
F
3
67686465
Top
View
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52
ENA
51
ENB
50
FTAB
49
S
48
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44
C
0
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Discontinued Package
Ceramic Pin Grid Array
(G1)
Arithmetic Logic Units
11
08/16/2000–LDS.383-E
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