DEVICES INCORPORATED
L4C383
16-bit Cascadable ALU (Extended Set)
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
FEATURES DESCRIPTION
❑❑
❑ High-Speed (15ns), Low Power
❑❑
16-bit Cascadable ALU
❑❑
❑ Extended Function Set
❑❑
(32 Advanced ALU Functions)
❑❑
❑ All Registers Have a Bypass Path
❑❑
for Complete Flexibility
❑❑
❑ Replaces IDT7383
❑❑
❑❑
❑ 68-pin PLCC, J-Lead
❑❑
The L4C383 is a flexible, high speed,
cascadable 16-bit Arithmetic and Logic
Unit. The L4C383 is capable of
performing up to 32 different
arithmetic or logic functions.
The L4C383 can be cascaded to perform
32-bit or greater operations. See
“Cascading the L4C383” on the next
page.
ARCHITECTURE
The L4C383 operates on two 16-bit
operands (A and B) and produces a 16-
L4C383 BLOCK DIAGRAM
B15-B
FFFF
0
H
ENA
A15-A
0
16 16
A REGISTER B REGISTER
FFFF
H
ENB
FTAB
bit result (F). Five select lines control
the ALU and provide 19 arithmetic and
13 logical functions. Registers are
provided on both the ALU inputs and
the output, but these may be bypassed
under user control. An internal feedback path allows the registered ALU
output to be routed to one or both of
the ALU inputs, accommodating chain
operations and accumulation.
ALU OPERATIONS
The S4–S0 lines specify the operation to
be performed. The ALU functions and
their select codes are shown in Table 1.
ALU STATUS
The ALU provides Overflow and Zero
status bits. A Carry output is also
provided for cascading multiple
devices, however it is only defined for
the 19 arithmetic functions. The ALU
sets the Zero output when all 16 output
bits are zero. The N, C16 and OVF flags
for the arithmetic operations are
defined in Table 2.
N, C
OVF, Z
FTF
OE
CLK
5
S
4-0
OPERAND REGISTERS
The L4C383 has two 16-bit wide input
registers for operands A and B. These
16
4
ALU
16
C
0
registers are rising edge triggered by a
common clock. The A register is
enabled for input by setting the ENA
control LOW, and the B register is
RESULT REGISTER
ENF
enabled for input by setting the ENB
control LOW. When either the ENA
control or ENB control is HIGH, the
data in the corresponding input register
will not change.
16
This architecture allows the L4C383 to
accept arguments from a single 16-bit
16
data bus. For those applications that do
not require registered inputs, both the
TO ALL REGISTERS
F15-F
0
A and B operand registers can be
bypassed with the FTAB control line.
Arithmetic Logic Units
1
08/16/2000–LDS.383-E
DEVICES INCORPORATED
L4C383
16-bit Cascadable ALU (Extended Set)
TABLE 1. ALU FUNCTIONS
S4-S0 FUNCTION
00000 A + B + C0
00001 A OR B
00010 A + B + C0
00011 A + B + C0
00100 A + C0
00101 A OR F
00110 A – 1 + C0
00111 A + C0
01000 A + F + C0
01001 A OR F
01010 A + F + C0
01011 A + F + C0
01100 F + B + C0
01101 A OR B
01110 F + B + C0
01111 F + B + C0
10000 A XOR B
10001 A AND B
10010 A AND B
10011 A XNOR B
10100 A XOR F
10101 A AND F
10110 A AND F
10111 ALL 1's + C0
11000 B + C0
11001 A AND B
11010 B + C0
11011 B – 1 + C0
11100 F + C0
11101 A OR B
11110 F – 1 + C0
11111 F + C0
When the FTAB control is asserted
(FTAB = HIGH), data is routed
around the A and B input registers;
however, they continue to function
normally via the ENA and ENB
controls. The contents of the input
registers will again be available to the
ALU if the FTAB control is released.
TABLE 2. ALU STATUS FLAGS
Bit Carry Generate = gi =AiBi for i = 0 ... 15
Bit Carry Propagate = pi =Ai + Bi for i = 0 ... 15
P0 =p0
Pi =pi (Pi–1) for i = 1 ... 15
and
G0 =g0
Gi =gi + pi (Gi–1) for i = 1 ... 15
Ci =Gi–1 + Pi–1 (C0) for i = 1 ... 15
then
C16 =G15 + P15C0
OVF = C15 XOR C16
Zero = All Output Bits Equal Zero
N = Sign Bit of ALU Operation
OUTPUT REGISTER
The output of the ALU drives the input of
a 16-bit register. This rising-edgetriggered register is clocked by the same
clock as the input registers. When the
ENF control is LOW, data from the ALU
will be clocked into the output register.
By disabling the output register, intermediate results can be held while loading
new input operands. Three-state drivers
controlled by the OE input allow the
L4C383 to be configured in a single
bidirectional bus system.
The output register can be bypassed by
asserting the FTF control signal (FTF =
HIGH). When the FTF control is asserted,
output data is routed around the output
register, however, it continues to function
normally via the ENF control. The
contents of the output register will again
be available on the output pins if FTF is
released.
CASCADING THE L4C383
Cascading the L4C383 to 32 bits is
accomplished simply by connecting the
C16 output of the least significant slice to
the C0 input of the most sig-nificant slice.
The S4-S0, ENA, ENB, and ENF lines are
common to both devices. The Zero output
flags should be logically ANDed to
produce the Zero flag for the 32-bit result.
The OVF and C16 outputs of the most
significant slice are valid for the 32-bit
result.
Propagation delay calculations for this
configuration require two steps: First
determine the propagation delay from the
input of interest to the C16 output of the
lower slice. Add this number to the delay
from the C0 input of the upper slice to the
output of interest (of the C0 setup time, if
the F register is used). The sum gives the
overall input-to-output delay (or setup
time) for the 32-bit configuration. This
method gives a conservative result, since
the C16 output is very lightly loaded.
Formulas for calculation of all critical
delays for a 32-bit system are shown in
Figures 4A through 4D.
Cascading to greater than 32 bits can be
accomplished by simply connecting the
C16 output of each slice to the C0 input of
the next more significant slice.
Propagation delays are calculated as
for the 32-bit case, except that the C0
to C16 delays for all intermediate slices
must be added to the overall delay for
each path.
Arithmetic Logic Units
2
08/16/2000–LDS.383-E
DEVICES INCORPORATED
FIGURE 4A. FTAB = 0, FTF = 0
From To Calculated Specification Limit
Clock ➞ F = Same as 16-bit case
Clock ➞ Other = (Clock ➞ C16) + (C0 ➞ Out)
C0 ➞ Other = (C0 ➞ C16) + (C0 ➞ Out)
S4-S0 ➞ Other = (S4-S0 ➞ C16) + (C0 ➞ Out)
A, B Setup time = Same as 16-bit case
C0 Setup time = (C 0 ➞ C16) + (C0 Setup time)
S4-S0 Setup time = (S4-S0 ➞ C16) + (C0 Setup time)
ENA, ENB, ENF Setup time = Same as 16-bit case
Minimum cycle time = (Clock ➞ C16) + (C0 Setup time)
L4C383
16-bit Cascadable ALU (Extended Set)
A31-A16
D
Q
A
MOST
16
SIGNIFICANT
SLICE
FIGURE 4B. FTAB = 0, FTF = 1
From To Calculated Specification Limit
Clock ➞ F = (Clock ➞ C16) + (C0 ➞ F)
Clock ➞ Other = (Clock ➞ C16) + (C0 ➞ Out)
C0 ➞ F = (C0 ➞ C16) + (C0 ➞ F)
C0 ➞ Other = (C0 ➞ C16) + (C0 ➞ Out)
S4-S0 ➞ F = (S4-S0 ➞ C16) + (C0 ➞ F)
S4-S0 ➞ Other = (S4-S0 ➞ C16) + (C0 ➞ Out)
A, B Setup time = Same as 16-bit case
C0 Setup time = (C0 ➞ C16) + (C0 Setup time)
S4-S0 Setup time = (S4-S0 ➞ C16) + (C0 Setup time)
ENA, ENB, ENF Setup time = Same as 16-bit case
Minimum cycle time = (Clock ➞ C16) + (C0 Setup time)
F
D
Q
F31-F16
B31-B16
D
Q
B
0
C
CLOCK CLOCK
A15-A0 B15-B0
D
Q
A
16
C
F
D
Q
16
F15-F0
D
Q
B
C
CLOCK
0–S4
S
C
0,
0
LEAST
SIGNIFICANT
SLICE
MOST
SIGNIFICANT
SLICE
A31-A16
D
Q
A
F
16
F31-F16
B31-B16
D
Q
B
0
C
A15-A0 B15-B0
D
Q
A
16
C
F
16
F15-F0
3
D
Q
B
C
CLOCK
0–S4
S
C
0,
0
LEAST
SIGNIFICANT
SLICE
Arithmetic Logic Units
08/16/2000–LDS.383-E
DEVICES INCORPORATED
FIGURE 4C. FTAB = 1, FTF = 0
From To Calculated Specification Limit
Clock ➞ F = Same as 16-bit case
A, B ➞ Other = (A, B ➞ C16) + (C0 ➞ Out)
C0 ➞ Other = (C0 ➞ C16) + (C0 ➞ Out)
S4-S0 ➞ Other = (S4-S0 ➞ C16) + (C0 ➞ Out)
A, B Setup time = (A, B ➞ C16) + (C0 Setup time)
C0 Setup time = (C0 ➞ C16) + (C0 Setup time)
S4-S0 Setup time = (S4-S0 ➞ C16) + (C0 Setup time)
ENA, ENB, ENF Setup time = Same as 16-bit case
Minimum cycle time = (Clock ➞ C16) + (C0 Setup time)
(F register accumulate loop)
A31-A
A
L4C383
16-bit Cascadable ALU (Extended Set)
16
B31-B
16
B
0
C
F
A15-A
A
16
C
0
B15-B
0
0–S4
S
C
0,
B
0
C
F
MOST
16
SIGNIFICANT
SLICE
FIGURE 4D. FTAB = 1, FTF = 1
From To Calculated Specification Limit
A, B ➞ F = (A, B ➞ C16) + (C0 ➞ F)
A, B ➞ Other = (A, B ➞ C16) + (C0 ➞ Out)
C0 ➞ F = (C0 ➞ C16) + (C0 ➞ F)
C0 ➞ Other = (C0 ➞ C16) + (C0 ➞ Out)
S4-S0 ➞ F = (S4-S0 ➞ C16) + (C0 ➞ F)
S4-S0 ➞ Other = (S4-S0 ➞ C16) + (C0 ➞ Out)
A, B Setup time = (A, B ➞ C16) + (C0 Setup time)
C0 Setup time = (C0 ➞ C16) + (C0 Setup time)
S4-S0 Setup time = (S4-S0 ➞ C16) + (C0 Setup time)
ENA, ENB, ENF Setup time = Same as 16-bit case
Minimum cycle time = (Clock ➞ C16) + (C0 Setup time)
(F register accumulate loop)
D
F31-F
16
D
Q
LEAST
Q
CLOCK CLOCK
SIGNIFICANT
F15-F
16
0
SLICE
MOST
SIGNIFICANT
SLICE
A31-A
A
16
16
F31-F
F
B31-B
16
16
B
0
C
A15-A
A
16
C
0
16
B15-B
0
0–S4
S
C
0,
B
0
C
F
LEAST
SIGNIFICANT
F15-F
0
SLICE
Arithmetic Logic Units
4
08/16/2000–LDS.383-E
DEVICES INCORPORATED
L4C383
16-bit Cascadable ALU (Extended Set)
MAXIMUM RATINGS
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground............................................................................ –0.5V to +7.0V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS
Active Operation, Commercial 0°C to +70°C 4.75V ≤ VCC ≤ 5.25 V
Active Operation, Military –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V
ELECTRICAL CHARACTERISTICS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
To meet specified electrical and switching characteristics
Mode Temperature Range (Ambient) Supply Voltage
Over Operating Conditions (Note 4)
Symbol Parameter Test Condition Min Typ Max Unit
VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 V
VOL Output Low Voltage VCC = Min., IOL = 8.0 mA 0.5 V
VIH Input High Voltage 2.0 VCC V
V IL Input Low Voltage (Note 3) 0.0 0.8 V
IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±20 µA
IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±20 µA
ICC1 VCC Current, Dynamic (Notes 5, 6) 15 30 mA
ICC2 VCC Current, Quiescent (Note 7) 1.5 mA
Arithmetic Logic Units
5
08/16/2000–LDS.383-E
DEVICES INCORPORATED
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
16-bit Cascadable ALU (Extended Set)
SWITCHING CHARACTERISTICS — COMMERCIAL OPERATING RANGE (0°C to +70°C)
L4C383
GUARANTEED MAXIMUM COMBINATIONAL DELAYS
23456789012345678901234567890121234567890123456789
To Output
From Input
FTAB = 0, FTF = 0
Clock
C0
S4-S0
FTAB = 0, FTF = 1
Clock
C0
S4-S0
FTAB = 1, FTF = 0
A15-A0, B15-B0
Clock
C0
S4-S0
FTAB = 1, FTF = 1
A15-A0, B15-B0
Clock
C0
S4-S0
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
F15-F0 N OVF, Z C16
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
L4C383-55
32 38 53 36
— — 34 22
—424242
56 38 53 36
37 — 34 22
55 42 42 42
—364637
32———
— — 34 22
—424242
55 36 46 37
56 38 53 36
37 — 34 22
55 42 42 42
*
Notes 9, 10 (ns)
L4C383-40
F15-F0 N OVF, Z C16
26 30 44 32
— — 28 20
—323435
46 30 44 32
30 — 28 20
40 32 34 35
—304032
26———
— — 28 20
—323435
40 30 40 32
46 30 44 32
30 — 28 20
40 32 34 35
*
L4C383-26
F15-F0 N OVF, Z C16
22 22 26 22
— — 18 18
—222222
28 22 26 22
22 — 18 18
26 22 22 22
—222222
22———
— — 18 18
—222222
26 22 22 22
28 22 26 22
22 — 18 18
26 22 22 22
GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE
Input
A15-A0, B15-B0
C0
S4-S0
ENA, ENB, ENF
TRI-STATE ENABLE/DISABLE TIMES
tENA
tDIS
2345678901234567890123
2345678901234567890123
*DISCONTINUED SPEED GRADE
234567890123456789012345
234567890123456789012345
234567890123456789012345
L4C383-55*L4C383-40*L4C383-26
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
20 18 16
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
20 18 16
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
Setup Hold Setup Hold
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
L4C383-55
FTAB = 0 FTAB = 1
82352
21 0 21 0
44 0 44 0
10 2 10 2
Notes 9, 10, 11 (ns)
*
Setup Hold Setup Hold
CLOCK CYCLE TIME AND PULSE WIDTH
Minimum Cycle Time
Highgoing Pulse
Lowgoing Pulse
6
L4C383-40
FTAB = 0 FTAB = 1
82282
16 0 16 0
32 0 32 0
10 2 10 2
*
Setup Hold Setup Hold
234567890123456789012345
234567890123456789012345
L4C383-55*L4C383-40*L4C383-26
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
43 34 20
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
15 10 10
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
15 10 10
234567890123456789012345
Arithmetic Logic Units
Notes 9, 10 (ns)
L4C383-26
FTAB = 0 FTAB = 1
82162
80 80
18 0 18 0
82 82
Notes 9, 10 (ns)
08/16/2000–LDS.383-E
DEVICES INCORPORATED
3
3
3
3
3
3
3
3
3
3
12345678901234567890123456
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
12345678901234567890123456
12345678901234567890123456
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
1
6
12345678901234567890123456
1234567890123
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1234567890123
4
4
16-bit Cascadable ALU (Extended Set)
SWITCHING CHARACTERISTICS — COMMERCIAL OPERATING RANGE (0°C to +70°C)
L4C383
GUARANTEED MAXIMUM COMBINATIONAL DELAYS
To Output
From Input
FTAB = 0, FTF = 0
Clock
C0
S4-S0
FTAB = 0, FTF = 1
Clock
C0
S4-S0
FTAB = 1, FTF = 0
A15-A0, B15-B0
Clock
C0
S4-S0
FTAB = 1, FTF = 1
A15-A0, B15-B0
Clock
C0
S4-S0
GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE
Input
A15-A0, B15-B0
C0
S4-S0
ENA, ENB, ENF
TRI-STATE ENABLE/DISABLE TIMES
L4C383-20 L4C383-15
tENA
tDIS
2345678901234567890123
2345678901234567890123
*DISCONTINUED SPEED GRADE
86
86
23456789012
23456789012
23456789012
23456789012
23456789012
23456789012
23456789012
23456789012
23456789012
23456789012
Notes 9, 10 (ns)
L4C383-20
F15-F0 N OVF, Z C16
11 20 20 20
— — 14 14
—182018
20 20 20 20
18 — 14 14
20 18 20 18
—162017
11———
— — 14 14
—182018
20 16 20 17
20 20 20 20
18 — 14 14
20 18 20 18
L4C383-20
FTAB = 0 FTAB = 1
Setup Hold Setup Hold
50140
12 0 12 0
15 0 15 0
50 50
Notes 9, 10, 11 (ns)
*
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
F15-F0 N OVF, Z C16
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
Setup Hold Setup Hold
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
L4C383-15
11 15 15 15
— — 13 13
—141514
15 15 15 15
14 — 13 13
15 14 15 14
—141514
11 — — —
— — 13 13
—141514
15 14 15 14
15 15 15 15
14 — 13 13
15 14 15 14
L4C383-15
FTAB = 0 FTAB = 1
50120
10 0 10 0
12 0 12 0
50 50
*
Notes 9, 10 (ns)
*
CLOCK CYCLE TIME AND PULSE WIDTH
23456789012
23456789012
23456789012
23456789012
23456789012
23456789012
23456789012
23456789012
23456789012
23456789012
23456789012
23456789012
23456789012
23456789012
23456789012
Minimum Cycle Time
Highgoing Pulse
Lowgoing Pulse
L4C383-20 L4C383-15
18 14
54
54
Arithmetic Logic Units
7
Notes 9, 10 (ns)
*
08/16/2000–LDS.383-E
DEVICES INCORPORATED
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
16-bit Cascadable ALU (Extended Set)
SWITCHING CHARACTERISTICS — MILITARY OPERATING RANGE (–55°C to +125°C)
L4C383
GUARANTEED MAXIMUM COMBINATIONAL DELAYS
To Output
From Input
FTAB = 0, FTF = 0
Clock
C0
S4-S0
FTAB = 0, FTF = 1
Clock
C0
S4-S0
FTAB = 1, FTF = 0
A15-A0, B15-B0
Clock
C0
S4-S0
FTAB = 1, FTF = 1
A15-A0, B15-B0
Clock
C0
S4-S0
GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE
Input
A15-A0, B15-B0
C0
S4-S0
ENA, ENB, ENF
TRI-STATE ENABLE/DISABLE TIMES
tENA
tDIS
2345678901234567890123
2345678901234567890123
*DISCONTINUED SPEED GRADE
23456789012345678901234567890121234
23456789012345678901234567890121234
23456789012345678901234567890121234
L4C383-65*L4C383-45*L4C383-30
23456789012345678901234567890121234
23456789012345678901234567890121234
23456789012345678901234567890121234
23456789012345678901234567890121234
22 20 18
23456789012345678901234567890121234
23456789012345678901234567890121234
23456789012345678901234567890121234
23456789012345678901234567890121234
22 20 18
23456789012345678901234567890121234
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
F15-F0 N OVF, Z C16
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
Setup Hold Setup Hold
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
2345678901234567890123456789012123456789012345678901234567890121234567890123
L4C383-65
37 44 63 45
— — 42 25
—484848
68 44 63 45
42 — 42 25
66 48 48 48
—445644
37———
— — 42 25
—484848
65 44 56 44
68 44 63 45
42 — 42 25
66 48 48 48
L4C383-65
FTAB = 0 FTAB = 1
10 3 43 3
25 0 25 0
50 0 50 0
12 2 12 2
Notes 9, 10, 11 (ns)
Notes 9, 10 (ns)
*
F15-F0 N OVF, Z C16
*
Setup Hold Setup Hold
CLOCK CYCLE TIME AND PULSE WIDTH
*
Minimum Cycle Time
Highgoing Pulse
Lowgoing Pulse
8
L4C383-45
*
F15-F0 N OVF, Z C16
28 34 50 34
— — 32 23
—383838
56 34 50 34
32 — 32 23
46 38 38 38
—324636
28 — — —
— — 32 23
—383838
45 32 46 36
56 34 50 34
32 — 32 23
46 38 38 38
*
L4C383-45
FTAB = 0 FTAB = 1
83333
20 0 20 0
36 0 36 0
10 2 10 2
234567890123456789012345678901212345
234567890123456789012345678901212345
L4C383-65*L4C383-45*L4C383-30
234567890123456789012345678901212345
234567890123456789012345678901212345
234567890123456789012345678901212345
234567890123456789012345678901212345
52 38 26
234567890123456789012345678901212345
234567890123456789012345678901212345
234567890123456789012345678901212345
234567890123456789012345678901212345
20 15 12
234567890123456789012345678901212345
234567890123456789012345678901212345
234567890123456789012345678901212345
234567890123456789012345678901212345
20 15 12
234567890123456789012345678901212345
Setup Hold Setup Hold
Arithmetic Logic Units
L4C383-30
*
26 28 34 28
— — 22 22
—282828
34 28 34 28
26 — 22 22
30 28 28 28
—282828
26———
— — 22 22
—282828
30 28 28 28
34 28 34 28
26 — 22 22
30 28 28 28
Notes 9, 10 (ns)
L4C383-30
*
FTAB = 0 FTAB = 1
83203
12 0 12 0
20 0 20 0
10 2 10 2
Notes 9, 10 (ns)
*
08/16/2000–LDS.383-E
DEVICES INCORPORATED
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
4
4
16-bit Cascadable ALU (Extended Set)
SWITCHING CHARACTERISTICS — MILITARY OPERATING RANGE (–55°C to +125°C)
L4C383
GUARANTEED MAXIMUM COMBINATIONAL DELAYS
23456789012345678901234567890121234567890123456789
To Output
From Input
FTAB = 0, FTF = 0
Clock
C0
S4-S0
FTAB = 0, FTF = 1
Clock
C0
S4-S0
FTAB = 1, FTF = 0
A15-A0, B15-B0
Clock
C0
S4-S0
FTAB = 1, FTF = 1
A15-A0, B15-B0
Clock
C0
S4-S0
GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE
Input
A15-A0, B15-B0
C0
S4-S0
ENA, ENB, ENF
TRI-STATE ENABLE/DISABLE TIMES
tENA
tDIS
2345678901234567890123
2345678901234567890123
*DISCONTINUED SPEED GRADE
23456789012345678901234
23456789012345678901234
L4C383-25*L4C383-20
23456789012345678901234
23456789012345678901234
23456789012345678901234
23456789012345678901234
14 10
23456789012345678901234
23456789012345678901234
23456789012345678901234
23456789012345678901234
14 10
23456789012345678901234
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
F15-F0 N OVF, Z C16
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
Setup Hold Setup Hold
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
23456789012345678901234567890121234567890123456789
L4C383-25
14 24 24 24
— — 18 18
—222422
25 24 24 24
21 — 18 18
25 22 24 22
—202522
14———
— — 18 18
—222422
25 20 25 22
25 24 24 24
21 — 18 18
25 22 24 22
L4C383-25
FTAB = 0 FTAB = 1
72142
14 0 14 0
19 0 19 0
70 70
Notes 9, 10, 11 (ns)
*
Notes 9, 10 (ns)
*
F15-F0 N OVF, Z C16
*
Setup Hold Setup Hold
CLOCK CYCLE TIME AND PULSE WIDTH
Minimum Cycle Time
Highgoing Pulse
Lowgoing Pulse
9
L4C383-20
*
14 20 20 20
— — 16 16
—182018
20 20 20 20
17 — 16 16
20 18 20 18
—172017
14 — — —
— — 16 16
—182018
20 17 20 17
20 20 20 20
17 — 16 16
20 18 20 18
L4C383-20
*
FTAB = 0 FTAB = 1
62122
12 0 12 0
16 0 16 0
60 60
234567890123456789012345
234567890123456789012345
L4C383-25*L4C383-20
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
20 18
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
86
234567890123456789012345
234567890123456789012345
234567890123456789012345
234567890123456789012345
86
234567890123456789012345
Arithmetic Logic Units
Notes 9, 10 (ns)
Notes 9, 10 (ns)
*
08/16/2000–LDS.383-E
DEVICES INCORPORATED
S1
I
OH
I
OL
V
TH
C
L
DUT
OE
0.2 V
t
DIS
t
ENA
0.2 V
1.5 V 1.5 V
3.5V Vth
1
Z
0
Z
Z
1
Z
0
1.5 V
1.5 V
0V Vth
VOL*
V
OH
*
V
OL
*
V
OH
*
Measured V
OL
with IOH = –10mA and IOL = 10mA
Measured V
OH
with IOH = –10mA and IOL = 10mA
NOTES
L4C383
16-bit Cascadable ALU (Extended Set)
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot. Input levels below ground or above VCC
will be clamped beginning at –0.6 V and
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in
excess of 100 mA.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of IOH and IOL respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs capable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 µF ceramic capacitor should be
installed between VCC and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device VCC
and the tester common, and device
ground and tester common.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, VTH, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
FIGURE B. THRESHOLD LEVELS
4. Actual test conditions may vary from
those designated but operation is guaranteed as specified.
5. Supply current for a given application can be accurately approximated by:
2
NCV F
where
4
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
b. Ground and VCC supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the external system must supply at least that
much time to meet the worst-case requirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
10
Arithmetic Logic Units
08/16/2000–LDS.383-E
DEVICES INCORPORATED
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
A
B
C
D
E
F
G
H
J
K
L
Top View
Through Package
(i.e., Component Side Pinout)
1234567 8 9 10 11
A
8
A
9
A
11
A
13
A
15
V
CC
C
16
N
OVF
OE
F
15
A
7
A
6
F
14
F
13
A
5
A
4
F
12
F
11
A
3
A
2
F
10
F
9
A
1
A
0
F
8
F
7
B
15
B
14
F
6
F
5
B
13
B
12
F
4
F
3
B
11
B
10
F
2
F
1
B
9
B
8
B
5
B
3
B
1
ENA
FTAB
S
3
S
1
C
0
F
0
A
10
A
12
A
14
CLK
GND
GND
ZERO
ENF
FTF
B
7
B
6
B
4
B
2
B
0
ENB
S
4
S
2
S
0
L4C383
16-bit Cascadable ALU (Extended Set)
ORDERING INFORMATION
68-pin
A8A7A6A5A4A3A2A1A0B15B14B13B12B11B10B9B
46663 6212
10
A
9
11
A
10
12
A
11
13
A
12
14
A
13
15
A
14
16
A
15
17
CLK
18
CC
V
19
GND
20
16
C
21
GND
22
N
23
ZERO
24
OVF
25
ENF
26
FTF
27 32 33 34 35 36 37 386139 40941 42 43
28 29 30 31
OE
Plastic J-Lead Chip Carrier
Speed
(J2)
0°C to +70°C — COMMERCIAL SCREENING
26 ns
20 ns
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
L4C383JC26
L4C383JC20
5867
15F14F13F12F11F10
F
3
6768 6465
Top
View
F9F8F7F6F5F4F3F2F1F
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
68-pin
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
8
60
B
59
B
58
B
57
B
56
B
55
B
54
B
53
B
52
ENA
51
ENB
50
FTAB
49
S
48
S
47
S
46
S
45
S
44
C
0
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
7
23456789012345678901234567890121234567890123456
6
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
5
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
4
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
3
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
2
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
1
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
0
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
4
23456789012345678901234567890121234567890123456
3
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
2
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
1
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
0
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
0
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
23456789012345678901234567890121234567890123456
Discontinued Package
Ceramic Pin Grid Array
(G1)
Arithmetic Logic Units
11
08/16/2000–LDS.383-E
Loading...