LOGIC L29C525PC20, L29C525PC15, L29C525JC15, L29C525JC20 Datasheet

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DEVICES INCORPORATED

L29C525

Dual Pipeline Register

Pipeline Registers

03/23/2000–LDS.29C525-G

❑❑

❑ Dual 8-Deep Pipeline Register ❑❑

❑❑

❑ Configurable to Single 16-Deep ❑❑

❑❑

❑ Low Power CMOS Technology ❑❑

❑❑

❑ Replaces AMD Am29525 ❑❑

❑❑

❑ Load, Shift, and Hold Instructions ❑❑

❑❑

❑ Separate Data In and Data Out Pins ❑❑

❑❑

❑ Three-State Outputs ❑❑

❑❑

❑ Package Styles Available:

• 28-pin Plastic DIP

• 28-pin Plastic LCC, J-Lead

FEATURES DESCRIPTION

L29C525

Dual Pipeline Register

DEVICES INCORPORATED

The L29C525 is a high-speed, low power CMOS pipeline register. It is pin-for-pin compatible with the AMD Am29525. The L29C525 can be configured as two independent 8-level pipelines or as a single 16-level pipeline. The configuration implemented is determined by the instruction code (I1-0) as shown in Table 2.

The I1-0 instruction code controls the internal routing of data and loading of each register. For instruction I1-0 = 00 (Push A and B), data applied at the D7-0 inputs is latched into register A0 on the rising edge of CLK. The contents of A0 simultaneously move to register A1, A1 moves to A2, and so on. The contents of register A7 are wrapped back to register B0. The registers on the B side are similarly shifted, with the contents of register B7 lost.

Instruction I1-0 = 01 (Push B) acts similarly to the Push A and B instruction, except that only the B side registers are shifted. The input data is applied to register B0, and the contents of register B7 are lost. The contents of the A side registers are unaffected. Instruction I1-0 = 10 (Push A) is identical to the Push B instruction, except that the A side registers are shifted and the B side registers are unaffected.

Instruction I1-0 = 11 (Hold) causes no internal data movement. It is equivalent to preventing the application of a clock edge to any internal register.

The contents of any of the registers is selectable at the output through the use of the S3-0 control inputs. The independence of the I and S control lines allows simultaneous reading and writing. Encoding for the S3-0 controls is given in Table 3.

L29C525 BLOCK DIAGRAM

7-0

1-0

CLK

MUX

3-0

A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7

DEVICES INCORPORATED

L29C525

Dual Pipeline Register

Pipeline Registers

03/27/2000–LDS.29C525-G

TABLE 1. REGISTER LOAD OPERATIONS

Single 16 Level Dual 8 Level

Push A and B Push A Hold All RegistersPush B

A0 A1 A2 A3 A4 A5 A6 A7

B0 B1 B2 B3 B4 B5 B6 B7

A0 A1 A2 A3 A4 A5 A6 A7

B0 B1 B2 B3 B4 B5 B6 B7

HOLD

A0 A1 A2 A3 A4 A5 A6 A7

B0 B1 B2 B3 B4 B5 B6 B7

HOLD

A0 A1 A2 A3 A4 A5 A6 A7

B0 B1 B2 B3 B4 B5 B6 B7

HOLDHOLD

TABLE 2. INSTRUCTION SET TABLE 3. OUTPUT SELECT

Inputs

Mnemonics I1 I0 Description

Shift 0 0 Push A and B LDB 0 1 Push B LDA 1 0 Push A HLD 1 1 Hold All Registers

S3 S2 S1 S0 Y7-0

0000A0 0001A1 0010A2 0011A3 0100A4 0101A5 0110A6 0111A7 1000B0 1001B1 1010B2 1011B3 1100B4 1101B5 1110B6 1111B7

DEVICES INCORPORATED

L29C525

Dual Pipeline Register

Pipeline Registers

03/32/2000–LDS.29C525-G

Symbol Parameter Test Condition Min Ty p Max Unit

VOH Output High Voltage VCC = Min., IOH = –12 mA 2.4 V VOL Output Low Voltage VCC = Min., IOL = 24 mA 0.5 V VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage (Note 3) 0.0 0.8 V IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±20 µA IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±20 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 10 35 mA ICC2 VCC Current, Quiescent (Note 7) 1.0 mA

Storage temperature ........................................................................................................... –65°C to +150°C

Operating ambient temperature........................................................................................... –55°C to +125°C

VCC supply voltage with respect to ground............................................................................ –0.5 V to +7.0V

Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V

Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V

Output current into low outputs............................................................................................................. 25 mA

Latchup current ............................................................................................................................... > 400 mA

MAXIMUM RATINGS

Above which useful life may be impaired (Notes 1, 2, 3, 8)

OPERATING CONDITIONS

To meet specified electrical and switching characteristics

ELECTRICAL CHARACTERISTICS

Over Operating Conditions (Note 4)

Mode Temperature Range (Ambient) Supply Voltage

Active Operation, Commercial 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V Active Operation, Military –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V

DEVICES INCORPORATED

L29C525

Dual Pipeline Register

Pipeline Registers

03/27/2000–LDS.29C525-G

23456789012345678901234567890

L29C525–

20 15

Symbol Parameter Min Max Min Max

tPD Clock to Output Delay 20 15 tSEL Select to Output Delay 20 15

tPW Clock Pulse Width 12 10 tSD Data Setup Time 7 5 tHD Data Hold Time 0 0 tSI Instruction Setup Time 7 5 tHI Instruction Hold Time 2 2 tENA Three-State Output Enable Delay (Note 11) 15 15 tDIS Three-State Output Disable Delay (Note 11) 13 13

COMMERCIAL OPERATING RANGE (0°C to +70°C)

Notes 9, 10 (ns)

SWITCHING CHARACTERISTICS

MILITARY OPERATING RANGE (–55°C to +125°C)

Notes 9, 10 (ns)

L29C525–

20*

Symbol Parameter Min Max Min Max

tPD Clock to Output Delay 25 20 tSEL Select to Output Delay 25 20

tPW Clock Pulse Width 12 12 tSD Data Setup Time 7 7 tHD Data Hold Time 2 2 tSI Instruction Setup Time 7 7 tHI Instruction Hold Time 2 2 tENA Three-State Output Enable Delay (Note 11) 15 15 tDIS Three-State Output Disable Delay (Note 11) 13 13

SWITCHING WAVEFORMS

HIGH IMPEDANCE

CLK

7-0

1-0

3-0

SEL

DIS

ENA

23456789012345678

*DISCONTINUED SPEED GRADE

DEVICES INCORPORATED

L29C525

Dual Pipeline Register

Pipeline Registers

03/32/2000–LDS.29C525-G

1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability.

2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values.

3. This device provides hard clamping of transient undershoot and overshoot. Input levels below ground or above VCC will be clamped beginning at –0.6 V and

VCC + 0.6 V. The device can withstand

indefinite operation with inputs in the range of –0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in excess of 100 mA.

4. Actual test conditions may vary from those designated but operation is guaranteed as specified.

5. Supply current for a given application can be accurately approximated by:

where

N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency

6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock rate.

7. Tested with all inputs within 0.1 V of

VCC or Ground, no load.

8. These parameters are guaranteed but not 100% tested.

NCV F

NOTES

9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except

tDIS test), and input levels of nominally

0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed.

This device has high-speed outputs capable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended:

a. A 0.1 µF ceramic capacitor should be installed between VCC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common.

b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers.

c. Input voltages should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin.

10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time.

11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, VTH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.

12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current.

DUT

0.2 V

DIS

ENA

0.2 V

1.5 V 1.5 V

3.5V Vth

1.5 V

0V Vth

VOL*

Measured V

with IOH = –10mA and IOL = 10mA

Measured V

with IOH = –10mA and IOL = 10mA

FIGURE B. THRESHOLD LEVELS

FIGURE A. OUTPUT LOADING CIRCUIT

DEVICES INCORPORATED

L29C525

Dual Pipeline Register

Pipeline Registers

03/27/2000–LDS.29C525-G

5 6 7 8 9 10 11

25 24 23 22 21 20 19

Top

View

12 17 18

28312

13 14 15 16

GND OE Y

GND

CLK

Y7Y6Y

D1D0S0S1S2S3Y

Plastic DIP

(P10)

L29C525PC20 L29C525PC15

28-pin — 0.3" wide

ORDERING INFORMATION

28-pin

0°C to +70°C — COMMERCIAL SCREENING

Speed

20 ns 15 ns

–55°C to +125°C — MIL-STD-883 COMPLIANT

–55°C to +125°C — COMMERCIAL SCREENING

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

S1 S0 D0 D1 D2 D3

VCC

GND

D5 D6 D7

CLK

S3 Y0 Y1 Y2 Y3 VCC GND OE Y

Y5 Y6 Y7 I1

Plastic J-Lead Chip Carrier

(J4)

L29C525JC20 L29C525JC15

–55°C to +125°C — MIL-STD-883 COMPLIANT

–55°C to +125°C — COMMERCIAL SCREENING

0°C to +70°C — COMMERCIAL SCREENING

LOGIC L29C525PC20, L29C525PC15, L29C525JC15, L29C525JC20 Datasheet

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